1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020, Intel Corporation
3  */
4 
5 #include <linux/clk-provider.h>
6 #include <linux/pci.h>
7 #include <linux/dmi.h>
8 #include "dwmac-intel.h"
9 #include "dwmac4.h"
10 #include "stmmac.h"
11 #include "stmmac_ptp.h"
12 
13 struct intel_priv_data {
14 	int mdio_adhoc_addr;	/* mdio address for serdes & etc */
15 	unsigned long crossts_adj;
16 	bool is_pse;
17 };
18 
19 /* This struct is used to associate PCI Function of MAC controller on a board,
20  * discovered via DMI, with the address of PHY connected to the MAC. The
21  * negative value of the address means that MAC controller is not connected
22  * with PHY.
23  */
24 struct stmmac_pci_func_data {
25 	unsigned int func;
26 	int phy_addr;
27 };
28 
29 struct stmmac_pci_dmi_data {
30 	const struct stmmac_pci_func_data *func;
31 	size_t nfuncs;
32 };
33 
34 struct stmmac_pci_info {
35 	int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
36 };
37 
38 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
39 				    const struct dmi_system_id *dmi_list)
40 {
41 	const struct stmmac_pci_func_data *func_data;
42 	const struct stmmac_pci_dmi_data *dmi_data;
43 	const struct dmi_system_id *dmi_id;
44 	int func = PCI_FUNC(pdev->devfn);
45 	size_t n;
46 
47 	dmi_id = dmi_first_match(dmi_list);
48 	if (!dmi_id)
49 		return -ENODEV;
50 
51 	dmi_data = dmi_id->driver_data;
52 	func_data = dmi_data->func;
53 
54 	for (n = 0; n < dmi_data->nfuncs; n++, func_data++)
55 		if (func_data->func == func)
56 			return func_data->phy_addr;
57 
58 	return -ENODEV;
59 }
60 
61 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr,
62 			      int phyreg, u32 mask, u32 val)
63 {
64 	unsigned int retries = 10;
65 	int val_rd;
66 
67 	do {
68 		val_rd = mdiobus_read(priv->mii, phyaddr, phyreg);
69 		if ((val_rd & mask) == (val & mask))
70 			return 0;
71 		udelay(POLL_DELAY_US);
72 	} while (--retries);
73 
74 	return -ETIMEDOUT;
75 }
76 
77 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
78 {
79 	struct intel_priv_data *intel_priv = priv_data;
80 	struct stmmac_priv *priv = netdev_priv(ndev);
81 	int serdes_phy_addr = 0;
82 	u32 data = 0;
83 
84 	if (!intel_priv->mdio_adhoc_addr)
85 		return 0;
86 
87 	serdes_phy_addr = intel_priv->mdio_adhoc_addr;
88 
89 	/* Set the serdes rate and the PCLK rate */
90 	data = mdiobus_read(priv->mii, serdes_phy_addr,
91 			    SERDES_GCR0);
92 
93 	data &= ~SERDES_RATE_MASK;
94 	data &= ~SERDES_PCLK_MASK;
95 
96 	if (priv->plat->max_speed == 2500)
97 		data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT |
98 			SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT;
99 	else
100 		data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT |
101 			SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT;
102 
103 	mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
104 
105 	/* assert clk_req */
106 	data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
107 	data |= SERDES_PLL_CLK;
108 	mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
109 
110 	/* check for clk_ack assertion */
111 	data = serdes_status_poll(priv, serdes_phy_addr,
112 				  SERDES_GSR0,
113 				  SERDES_PLL_CLK,
114 				  SERDES_PLL_CLK);
115 
116 	if (data) {
117 		dev_err(priv->device, "Serdes PLL clk request timeout\n");
118 		return data;
119 	}
120 
121 	/* assert lane reset */
122 	data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
123 	data |= SERDES_RST;
124 	mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
125 
126 	/* check for assert lane reset reflection */
127 	data = serdes_status_poll(priv, serdes_phy_addr,
128 				  SERDES_GSR0,
129 				  SERDES_RST,
130 				  SERDES_RST);
131 
132 	if (data) {
133 		dev_err(priv->device, "Serdes assert lane reset timeout\n");
134 		return data;
135 	}
136 
137 	/*  move power state to P0 */
138 	data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
139 
140 	data &= ~SERDES_PWR_ST_MASK;
141 	data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
142 
143 	mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
144 
145 	/* Check for P0 state */
146 	data = serdes_status_poll(priv, serdes_phy_addr,
147 				  SERDES_GSR0,
148 				  SERDES_PWR_ST_MASK,
149 				  SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT);
150 
151 	if (data) {
152 		dev_err(priv->device, "Serdes power state P0 timeout.\n");
153 		return data;
154 	}
155 
156 	/* PSE only - ungate SGMII PHY Rx Clock */
157 	if (intel_priv->is_pse)
158 		mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
159 			       0, SERDES_PHY_RX_CLK);
160 
161 	return 0;
162 }
163 
164 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
165 {
166 	struct intel_priv_data *intel_priv = intel_data;
167 	struct stmmac_priv *priv = netdev_priv(ndev);
168 	int serdes_phy_addr = 0;
169 	u32 data = 0;
170 
171 	if (!intel_priv->mdio_adhoc_addr)
172 		return;
173 
174 	serdes_phy_addr = intel_priv->mdio_adhoc_addr;
175 
176 	/* PSE only - gate SGMII PHY Rx Clock */
177 	if (intel_priv->is_pse)
178 		mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
179 			       SERDES_PHY_RX_CLK, 0);
180 
181 	/*  move power state to P3 */
182 	data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
183 
184 	data &= ~SERDES_PWR_ST_MASK;
185 	data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT;
186 
187 	mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
188 
189 	/* Check for P3 state */
190 	data = serdes_status_poll(priv, serdes_phy_addr,
191 				  SERDES_GSR0,
192 				  SERDES_PWR_ST_MASK,
193 				  SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT);
194 
195 	if (data) {
196 		dev_err(priv->device, "Serdes power state P3 timeout\n");
197 		return;
198 	}
199 
200 	/* de-assert clk_req */
201 	data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
202 	data &= ~SERDES_PLL_CLK;
203 	mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
204 
205 	/* check for clk_ack de-assert */
206 	data = serdes_status_poll(priv, serdes_phy_addr,
207 				  SERDES_GSR0,
208 				  SERDES_PLL_CLK,
209 				  (u32)~SERDES_PLL_CLK);
210 
211 	if (data) {
212 		dev_err(priv->device, "Serdes PLL clk de-assert timeout\n");
213 		return;
214 	}
215 
216 	/* de-assert lane reset */
217 	data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
218 	data &= ~SERDES_RST;
219 	mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
220 
221 	/* check for de-assert lane reset reflection */
222 	data = serdes_status_poll(priv, serdes_phy_addr,
223 				  SERDES_GSR0,
224 				  SERDES_RST,
225 				  (u32)~SERDES_RST);
226 
227 	if (data) {
228 		dev_err(priv->device, "Serdes de-assert lane reset timeout\n");
229 		return;
230 	}
231 }
232 
233 static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data)
234 {
235 	struct intel_priv_data *intel_priv = intel_data;
236 	struct stmmac_priv *priv = netdev_priv(ndev);
237 	int serdes_phy_addr = 0;
238 	u32 data = 0;
239 
240 	serdes_phy_addr = intel_priv->mdio_adhoc_addr;
241 
242 	/* Determine the link speed mode: 2.5Gbps/1Gbps */
243 	data = mdiobus_read(priv->mii, serdes_phy_addr,
244 			    SERDES_GCR);
245 
246 	if (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) ==
247 	    SERDES_LINK_MODE_2G5) {
248 		dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n");
249 		priv->plat->max_speed = 2500;
250 		priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX;
251 		priv->plat->mdio_bus_data->xpcs_an_inband = false;
252 	} else {
253 		priv->plat->max_speed = 1000;
254 		priv->plat->mdio_bus_data->xpcs_an_inband = true;
255 	}
256 }
257 
258 /* Program PTP Clock Frequency for different variant of
259  * Intel mGBE that has slightly different GPO mapping
260  */
261 static void intel_mgbe_ptp_clk_freq_config(void *npriv)
262 {
263 	struct stmmac_priv *priv = (struct stmmac_priv *)npriv;
264 	struct intel_priv_data *intel_priv;
265 	u32 gpio_value;
266 
267 	intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv;
268 
269 	gpio_value = readl(priv->ioaddr + GMAC_GPIO_STATUS);
270 
271 	if (intel_priv->is_pse) {
272 		/* For PSE GbE, use 200MHz */
273 		gpio_value &= ~PSE_PTP_CLK_FREQ_MASK;
274 		gpio_value |= PSE_PTP_CLK_FREQ_200MHZ;
275 	} else {
276 		/* For PCH GbE, use 200MHz */
277 		gpio_value &= ~PCH_PTP_CLK_FREQ_MASK;
278 		gpio_value |= PCH_PTP_CLK_FREQ_200MHZ;
279 	}
280 
281 	writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS);
282 }
283 
284 static void get_arttime(struct mii_bus *mii, int intel_adhoc_addr,
285 			u64 *art_time)
286 {
287 	u64 ns;
288 
289 	ns = mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE3);
290 	ns <<= GMAC4_ART_TIME_SHIFT;
291 	ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE2);
292 	ns <<= GMAC4_ART_TIME_SHIFT;
293 	ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE1);
294 	ns <<= GMAC4_ART_TIME_SHIFT;
295 	ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE0);
296 
297 	*art_time = ns;
298 }
299 
300 static int stmmac_cross_ts_isr(struct stmmac_priv *priv)
301 {
302 	return (readl(priv->ioaddr + GMAC_INT_STATUS) & GMAC_INT_TSIE);
303 }
304 
305 static int intel_crosststamp(ktime_t *device,
306 			     struct system_counterval_t *system,
307 			     void *ctx)
308 {
309 	struct intel_priv_data *intel_priv;
310 
311 	struct stmmac_priv *priv = (struct stmmac_priv *)ctx;
312 	void __iomem *ptpaddr = priv->ptpaddr;
313 	void __iomem *ioaddr = priv->hw->pcsr;
314 	unsigned long flags;
315 	u64 art_time = 0;
316 	u64 ptp_time = 0;
317 	u32 num_snapshot;
318 	u32 gpio_value;
319 	u32 acr_value;
320 	int i;
321 
322 	if (!boot_cpu_has(X86_FEATURE_ART))
323 		return -EOPNOTSUPP;
324 
325 	intel_priv = priv->plat->bsp_priv;
326 
327 	/* Both internal crosstimestamping and external triggered event
328 	 * timestamping cannot be run concurrently.
329 	 */
330 	if (priv->plat->ext_snapshot_en)
331 		return -EBUSY;
332 
333 	priv->plat->int_snapshot_en = 1;
334 
335 	mutex_lock(&priv->aux_ts_lock);
336 	/* Enable Internal snapshot trigger */
337 	acr_value = readl(ptpaddr + PTP_ACR);
338 	acr_value &= ~PTP_ACR_MASK;
339 	switch (priv->plat->int_snapshot_num) {
340 	case AUX_SNAPSHOT0:
341 		acr_value |= PTP_ACR_ATSEN0;
342 		break;
343 	case AUX_SNAPSHOT1:
344 		acr_value |= PTP_ACR_ATSEN1;
345 		break;
346 	case AUX_SNAPSHOT2:
347 		acr_value |= PTP_ACR_ATSEN2;
348 		break;
349 	case AUX_SNAPSHOT3:
350 		acr_value |= PTP_ACR_ATSEN3;
351 		break;
352 	default:
353 		mutex_unlock(&priv->aux_ts_lock);
354 		priv->plat->int_snapshot_en = 0;
355 		return -EINVAL;
356 	}
357 	writel(acr_value, ptpaddr + PTP_ACR);
358 
359 	/* Clear FIFO */
360 	acr_value = readl(ptpaddr + PTP_ACR);
361 	acr_value |= PTP_ACR_ATSFC;
362 	writel(acr_value, ptpaddr + PTP_ACR);
363 	/* Release the mutex */
364 	mutex_unlock(&priv->aux_ts_lock);
365 
366 	/* Trigger Internal snapshot signal
367 	 * Create a rising edge by just toggle the GPO1 to low
368 	 * and back to high.
369 	 */
370 	gpio_value = readl(ioaddr + GMAC_GPIO_STATUS);
371 	gpio_value &= ~GMAC_GPO1;
372 	writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
373 	gpio_value |= GMAC_GPO1;
374 	writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
375 
376 	/* Time sync done Indication - Interrupt method */
377 	if (!wait_event_interruptible_timeout(priv->tstamp_busy_wait,
378 					      stmmac_cross_ts_isr(priv),
379 					      HZ / 100)) {
380 		priv->plat->int_snapshot_en = 0;
381 		return -ETIMEDOUT;
382 	}
383 
384 	num_snapshot = (readl(ioaddr + GMAC_TIMESTAMP_STATUS) &
385 			GMAC_TIMESTAMP_ATSNS_MASK) >>
386 			GMAC_TIMESTAMP_ATSNS_SHIFT;
387 
388 	/* Repeat until the timestamps are from the FIFO last segment */
389 	for (i = 0; i < num_snapshot; i++) {
390 		read_lock_irqsave(&priv->ptp_lock, flags);
391 		stmmac_get_ptptime(priv, ptpaddr, &ptp_time);
392 		*device = ns_to_ktime(ptp_time);
393 		read_unlock_irqrestore(&priv->ptp_lock, flags);
394 		get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time);
395 		*system = convert_art_to_tsc(art_time);
396 	}
397 
398 	system->cycles *= intel_priv->crossts_adj;
399 	priv->plat->int_snapshot_en = 0;
400 
401 	return 0;
402 }
403 
404 static void intel_mgbe_pse_crossts_adj(struct intel_priv_data *intel_priv,
405 				       int base)
406 {
407 	if (boot_cpu_has(X86_FEATURE_ART)) {
408 		unsigned int art_freq;
409 
410 		/* On systems that support ART, ART frequency can be obtained
411 		 * from ECX register of CPUID leaf (0x15).
412 		 */
413 		art_freq = cpuid_ecx(ART_CPUID_LEAF);
414 		do_div(art_freq, base);
415 		intel_priv->crossts_adj = art_freq;
416 	}
417 }
418 
419 static void common_default_data(struct plat_stmmacenet_data *plat)
420 {
421 	plat->clk_csr = 2;	/* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
422 	plat->has_gmac = 1;
423 	plat->force_sf_dma_mode = 1;
424 
425 	plat->mdio_bus_data->needs_reset = true;
426 
427 	/* Set default value for multicast hash bins */
428 	plat->multicast_filter_bins = HASH_TABLE_SIZE;
429 
430 	/* Set default value for unicast filter entries */
431 	plat->unicast_filter_entries = 1;
432 
433 	/* Set the maxmtu to a default of JUMBO_LEN */
434 	plat->maxmtu = JUMBO_LEN;
435 
436 	/* Set default number of RX and TX queues to use */
437 	plat->tx_queues_to_use = 1;
438 	plat->rx_queues_to_use = 1;
439 
440 	/* Disable Priority config by default */
441 	plat->tx_queues_cfg[0].use_prio = false;
442 	plat->rx_queues_cfg[0].use_prio = false;
443 
444 	/* Disable RX queues routing by default */
445 	plat->rx_queues_cfg[0].pkt_route = 0x0;
446 }
447 
448 static int intel_mgbe_common_data(struct pci_dev *pdev,
449 				  struct plat_stmmacenet_data *plat)
450 {
451 	struct fwnode_handle *fwnode;
452 	char clk_name[20];
453 	int ret;
454 	int i;
455 
456 	plat->pdev = pdev;
457 	plat->phy_addr = -1;
458 	plat->clk_csr = 5;
459 	plat->has_gmac = 0;
460 	plat->has_gmac4 = 1;
461 	plat->force_sf_dma_mode = 0;
462 	plat->tso_en = 1;
463 	plat->sph_disable = 1;
464 
465 	/* Multiplying factor to the clk_eee_i clock time
466 	 * period to make it closer to 100 ns. This value
467 	 * should be programmed such that the clk_eee_time_period *
468 	 * (MULT_FACT_100NS + 1) should be within 80 ns to 120 ns
469 	 * clk_eee frequency is 19.2Mhz
470 	 * clk_eee_time_period is 52ns
471 	 * 52ns * (1 + 1) = 104ns
472 	 * MULT_FACT_100NS = 1
473 	 */
474 	plat->mult_fact_100ns = 1;
475 
476 	plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
477 
478 	for (i = 0; i < plat->rx_queues_to_use; i++) {
479 		plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
480 		plat->rx_queues_cfg[i].chan = i;
481 
482 		/* Disable Priority config by default */
483 		plat->rx_queues_cfg[i].use_prio = false;
484 
485 		/* Disable RX queues routing by default */
486 		plat->rx_queues_cfg[i].pkt_route = 0x0;
487 	}
488 
489 	for (i = 0; i < plat->tx_queues_to_use; i++) {
490 		plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
491 
492 		/* Disable Priority config by default */
493 		plat->tx_queues_cfg[i].use_prio = false;
494 		/* Default TX Q0 to use TSO and rest TXQ for TBS */
495 		if (i > 0)
496 			plat->tx_queues_cfg[i].tbs_en = 1;
497 	}
498 
499 	/* FIFO size is 4096 bytes for 1 tx/rx queue */
500 	plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
501 	plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
502 
503 	plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
504 	plat->tx_queues_cfg[0].weight = 0x09;
505 	plat->tx_queues_cfg[1].weight = 0x0A;
506 	plat->tx_queues_cfg[2].weight = 0x0B;
507 	plat->tx_queues_cfg[3].weight = 0x0C;
508 	plat->tx_queues_cfg[4].weight = 0x0D;
509 	plat->tx_queues_cfg[5].weight = 0x0E;
510 	plat->tx_queues_cfg[6].weight = 0x0F;
511 	plat->tx_queues_cfg[7].weight = 0x10;
512 
513 	plat->dma_cfg->pbl = 32;
514 	plat->dma_cfg->pblx8 = true;
515 	plat->dma_cfg->fixed_burst = 0;
516 	plat->dma_cfg->mixed_burst = 0;
517 	plat->dma_cfg->aal = 0;
518 	plat->dma_cfg->dche = true;
519 
520 	plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
521 				 GFP_KERNEL);
522 	if (!plat->axi)
523 		return -ENOMEM;
524 
525 	plat->axi->axi_lpi_en = 0;
526 	plat->axi->axi_xit_frm = 0;
527 	plat->axi->axi_wr_osr_lmt = 1;
528 	plat->axi->axi_rd_osr_lmt = 1;
529 	plat->axi->axi_blen[0] = 4;
530 	plat->axi->axi_blen[1] = 8;
531 	plat->axi->axi_blen[2] = 16;
532 
533 	plat->ptp_max_adj = plat->clk_ptp_rate;
534 	plat->eee_usecs_rate = plat->clk_ptp_rate;
535 
536 	/* Set system clock */
537 	sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev));
538 
539 	plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
540 						   clk_name, NULL, 0,
541 						   plat->clk_ptp_rate);
542 
543 	if (IS_ERR(plat->stmmac_clk)) {
544 		dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
545 		plat->stmmac_clk = NULL;
546 	}
547 
548 	ret = clk_prepare_enable(plat->stmmac_clk);
549 	if (ret) {
550 		clk_unregister_fixed_rate(plat->stmmac_clk);
551 		return ret;
552 	}
553 
554 	plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config;
555 
556 	/* Set default value for multicast hash bins */
557 	plat->multicast_filter_bins = HASH_TABLE_SIZE;
558 
559 	/* Set default value for unicast filter entries */
560 	plat->unicast_filter_entries = 1;
561 
562 	/* Set the maxmtu to a default of JUMBO_LEN */
563 	plat->maxmtu = JUMBO_LEN;
564 
565 	plat->vlan_fail_q_en = true;
566 
567 	/* Use the last Rx queue */
568 	plat->vlan_fail_q = plat->rx_queues_to_use - 1;
569 
570 	/* For fixed-link setup, we allow phy-mode setting */
571 	fwnode = dev_fwnode(&pdev->dev);
572 	if (fwnode) {
573 		int phy_mode;
574 
575 		/* "phy-mode" setting is optional. If it is set,
576 		 *  we allow either sgmii or 1000base-x for now.
577 		 */
578 		phy_mode = fwnode_get_phy_mode(fwnode);
579 		if (phy_mode >= 0) {
580 			if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
581 			    phy_mode == PHY_INTERFACE_MODE_1000BASEX)
582 				plat->phy_interface = phy_mode;
583 			else
584 				dev_warn(&pdev->dev, "Invalid phy-mode\n");
585 		}
586 	}
587 
588 	/* Intel mgbe SGMII interface uses pcs-xcps */
589 	if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII ||
590 	    plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
591 		plat->mdio_bus_data->has_xpcs = true;
592 		plat->mdio_bus_data->xpcs_an_inband = true;
593 	}
594 
595 	/* For fixed-link setup, we clear xpcs_an_inband */
596 	if (fwnode) {
597 		struct fwnode_handle *fixed_node;
598 
599 		fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link");
600 		if (fixed_node)
601 			plat->mdio_bus_data->xpcs_an_inband = false;
602 
603 		fwnode_handle_put(fixed_node);
604 	}
605 
606 	/* Ensure mdio bus scan skips intel serdes and pcs-xpcs */
607 	plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR;
608 	plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR;
609 
610 	plat->int_snapshot_num = AUX_SNAPSHOT1;
611 	plat->ext_snapshot_num = AUX_SNAPSHOT0;
612 
613 	plat->has_crossts = true;
614 	plat->crosststamp = intel_crosststamp;
615 	plat->int_snapshot_en = 0;
616 
617 	/* Setup MSI vector offset specific to Intel mGbE controller */
618 	plat->msi_mac_vec = 29;
619 	plat->msi_lpi_vec = 28;
620 	plat->msi_sfty_ce_vec = 27;
621 	plat->msi_sfty_ue_vec = 26;
622 	plat->msi_rx_base_vec = 0;
623 	plat->msi_tx_base_vec = 1;
624 
625 	return 0;
626 }
627 
628 static int ehl_common_data(struct pci_dev *pdev,
629 			   struct plat_stmmacenet_data *plat)
630 {
631 	plat->rx_queues_to_use = 8;
632 	plat->tx_queues_to_use = 8;
633 	plat->clk_ptp_rate = 200000000;
634 	plat->use_phy_wol = 1;
635 
636 	plat->safety_feat_cfg->tsoee = 1;
637 	plat->safety_feat_cfg->mrxpee = 1;
638 	plat->safety_feat_cfg->mestee = 1;
639 	plat->safety_feat_cfg->mrxee = 1;
640 	plat->safety_feat_cfg->mtxee = 1;
641 	plat->safety_feat_cfg->epsi = 0;
642 	plat->safety_feat_cfg->edpp = 0;
643 	plat->safety_feat_cfg->prtyen = 0;
644 	plat->safety_feat_cfg->tmouten = 0;
645 
646 	return intel_mgbe_common_data(pdev, plat);
647 }
648 
649 static int ehl_sgmii_data(struct pci_dev *pdev,
650 			  struct plat_stmmacenet_data *plat)
651 {
652 	plat->bus_id = 1;
653 	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
654 	plat->speed_mode_2500 = intel_speed_mode_2500;
655 	plat->serdes_powerup = intel_serdes_powerup;
656 	plat->serdes_powerdown = intel_serdes_powerdown;
657 
658 	return ehl_common_data(pdev, plat);
659 }
660 
661 static struct stmmac_pci_info ehl_sgmii1g_info = {
662 	.setup = ehl_sgmii_data,
663 };
664 
665 static int ehl_rgmii_data(struct pci_dev *pdev,
666 			  struct plat_stmmacenet_data *plat)
667 {
668 	plat->bus_id = 1;
669 	plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
670 
671 	return ehl_common_data(pdev, plat);
672 }
673 
674 static struct stmmac_pci_info ehl_rgmii1g_info = {
675 	.setup = ehl_rgmii_data,
676 };
677 
678 static int ehl_pse0_common_data(struct pci_dev *pdev,
679 				struct plat_stmmacenet_data *plat)
680 {
681 	struct intel_priv_data *intel_priv = plat->bsp_priv;
682 
683 	intel_priv->is_pse = true;
684 	plat->bus_id = 2;
685 	plat->addr64 = 32;
686 
687 	intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
688 
689 	return ehl_common_data(pdev, plat);
690 }
691 
692 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
693 				 struct plat_stmmacenet_data *plat)
694 {
695 	plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
696 	return ehl_pse0_common_data(pdev, plat);
697 }
698 
699 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = {
700 	.setup = ehl_pse0_rgmii1g_data,
701 };
702 
703 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
704 				 struct plat_stmmacenet_data *plat)
705 {
706 	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
707 	plat->speed_mode_2500 = intel_speed_mode_2500;
708 	plat->serdes_powerup = intel_serdes_powerup;
709 	plat->serdes_powerdown = intel_serdes_powerdown;
710 	return ehl_pse0_common_data(pdev, plat);
711 }
712 
713 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = {
714 	.setup = ehl_pse0_sgmii1g_data,
715 };
716 
717 static int ehl_pse1_common_data(struct pci_dev *pdev,
718 				struct plat_stmmacenet_data *plat)
719 {
720 	struct intel_priv_data *intel_priv = plat->bsp_priv;
721 
722 	intel_priv->is_pse = true;
723 	plat->bus_id = 3;
724 	plat->addr64 = 32;
725 
726 	intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
727 
728 	return ehl_common_data(pdev, plat);
729 }
730 
731 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
732 				 struct plat_stmmacenet_data *plat)
733 {
734 	plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
735 	return ehl_pse1_common_data(pdev, plat);
736 }
737 
738 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = {
739 	.setup = ehl_pse1_rgmii1g_data,
740 };
741 
742 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
743 				 struct plat_stmmacenet_data *plat)
744 {
745 	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
746 	plat->speed_mode_2500 = intel_speed_mode_2500;
747 	plat->serdes_powerup = intel_serdes_powerup;
748 	plat->serdes_powerdown = intel_serdes_powerdown;
749 	return ehl_pse1_common_data(pdev, plat);
750 }
751 
752 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = {
753 	.setup = ehl_pse1_sgmii1g_data,
754 };
755 
756 static int tgl_common_data(struct pci_dev *pdev,
757 			   struct plat_stmmacenet_data *plat)
758 {
759 	plat->rx_queues_to_use = 6;
760 	plat->tx_queues_to_use = 4;
761 	plat->clk_ptp_rate = 200000000;
762 	plat->speed_mode_2500 = intel_speed_mode_2500;
763 
764 	plat->safety_feat_cfg->tsoee = 1;
765 	plat->safety_feat_cfg->mrxpee = 0;
766 	plat->safety_feat_cfg->mestee = 1;
767 	plat->safety_feat_cfg->mrxee = 1;
768 	plat->safety_feat_cfg->mtxee = 1;
769 	plat->safety_feat_cfg->epsi = 0;
770 	plat->safety_feat_cfg->edpp = 0;
771 	plat->safety_feat_cfg->prtyen = 0;
772 	plat->safety_feat_cfg->tmouten = 0;
773 
774 	return intel_mgbe_common_data(pdev, plat);
775 }
776 
777 static int tgl_sgmii_phy0_data(struct pci_dev *pdev,
778 			       struct plat_stmmacenet_data *plat)
779 {
780 	plat->bus_id = 1;
781 	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
782 	plat->serdes_powerup = intel_serdes_powerup;
783 	plat->serdes_powerdown = intel_serdes_powerdown;
784 	return tgl_common_data(pdev, plat);
785 }
786 
787 static struct stmmac_pci_info tgl_sgmii1g_phy0_info = {
788 	.setup = tgl_sgmii_phy0_data,
789 };
790 
791 static int tgl_sgmii_phy1_data(struct pci_dev *pdev,
792 			       struct plat_stmmacenet_data *plat)
793 {
794 	plat->bus_id = 2;
795 	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
796 	plat->serdes_powerup = intel_serdes_powerup;
797 	plat->serdes_powerdown = intel_serdes_powerdown;
798 	return tgl_common_data(pdev, plat);
799 }
800 
801 static struct stmmac_pci_info tgl_sgmii1g_phy1_info = {
802 	.setup = tgl_sgmii_phy1_data,
803 };
804 
805 static int adls_sgmii_phy0_data(struct pci_dev *pdev,
806 				struct plat_stmmacenet_data *plat)
807 {
808 	plat->bus_id = 1;
809 	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
810 
811 	/* SerDes power up and power down are done in BIOS for ADL */
812 
813 	return tgl_common_data(pdev, plat);
814 }
815 
816 static struct stmmac_pci_info adls_sgmii1g_phy0_info = {
817 	.setup = adls_sgmii_phy0_data,
818 };
819 
820 static int adls_sgmii_phy1_data(struct pci_dev *pdev,
821 				struct plat_stmmacenet_data *plat)
822 {
823 	plat->bus_id = 2;
824 	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
825 
826 	/* SerDes power up and power down are done in BIOS for ADL */
827 
828 	return tgl_common_data(pdev, plat);
829 }
830 
831 static struct stmmac_pci_info adls_sgmii1g_phy1_info = {
832 	.setup = adls_sgmii_phy1_data,
833 };
834 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
835 	{
836 		.func = 6,
837 		.phy_addr = 1,
838 	},
839 };
840 
841 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {
842 	.func = galileo_stmmac_func_data,
843 	.nfuncs = ARRAY_SIZE(galileo_stmmac_func_data),
844 };
845 
846 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {
847 	{
848 		.func = 6,
849 		.phy_addr = 1,
850 	},
851 	{
852 		.func = 7,
853 		.phy_addr = 1,
854 	},
855 };
856 
857 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {
858 	.func = iot2040_stmmac_func_data,
859 	.nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data),
860 };
861 
862 static const struct dmi_system_id quark_pci_dmi[] = {
863 	{
864 		.matches = {
865 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
866 		},
867 		.driver_data = (void *)&galileo_stmmac_dmi_data,
868 	},
869 	{
870 		.matches = {
871 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
872 		},
873 		.driver_data = (void *)&galileo_stmmac_dmi_data,
874 	},
875 	/* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040.
876 	 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
877 	 * has only one pci network device while other asset tags are
878 	 * for IOT2040 which has two.
879 	 */
880 	{
881 		.matches = {
882 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
883 			DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
884 					"6ES7647-0AA00-0YA2"),
885 		},
886 		.driver_data = (void *)&galileo_stmmac_dmi_data,
887 	},
888 	{
889 		.matches = {
890 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
891 		},
892 		.driver_data = (void *)&iot2040_stmmac_dmi_data,
893 	},
894 	{}
895 };
896 
897 static int quark_default_data(struct pci_dev *pdev,
898 			      struct plat_stmmacenet_data *plat)
899 {
900 	int ret;
901 
902 	/* Set common default data first */
903 	common_default_data(plat);
904 
905 	/* Refuse to load the driver and register net device if MAC controller
906 	 * does not connect to any PHY interface.
907 	 */
908 	ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi);
909 	if (ret < 0) {
910 		/* Return error to the caller on DMI enabled boards. */
911 		if (dmi_get_system_info(DMI_BOARD_NAME))
912 			return ret;
913 
914 		/* Galileo boards with old firmware don't support DMI. We always
915 		 * use 1 here as PHY address, so at least the first found MAC
916 		 * controller would be probed.
917 		 */
918 		ret = 1;
919 	}
920 
921 	plat->bus_id = pci_dev_id(pdev);
922 	plat->phy_addr = ret;
923 	plat->phy_interface = PHY_INTERFACE_MODE_RMII;
924 
925 	plat->dma_cfg->pbl = 16;
926 	plat->dma_cfg->pblx8 = true;
927 	plat->dma_cfg->fixed_burst = 1;
928 	/* AXI (TODO) */
929 
930 	return 0;
931 }
932 
933 static const struct stmmac_pci_info quark_info = {
934 	.setup = quark_default_data,
935 };
936 
937 static int stmmac_config_single_msi(struct pci_dev *pdev,
938 				    struct plat_stmmacenet_data *plat,
939 				    struct stmmac_resources *res)
940 {
941 	int ret;
942 
943 	ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
944 	if (ret < 0) {
945 		dev_info(&pdev->dev, "%s: Single IRQ enablement failed\n",
946 			 __func__);
947 		return ret;
948 	}
949 
950 	res->irq = pci_irq_vector(pdev, 0);
951 	res->wol_irq = res->irq;
952 	plat->multi_msi_en = 0;
953 	dev_info(&pdev->dev, "%s: Single IRQ enablement successful\n",
954 		 __func__);
955 
956 	return 0;
957 }
958 
959 static int stmmac_config_multi_msi(struct pci_dev *pdev,
960 				   struct plat_stmmacenet_data *plat,
961 				   struct stmmac_resources *res)
962 {
963 	int ret;
964 	int i;
965 
966 	if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX ||
967 	    plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) {
968 		dev_info(&pdev->dev, "%s: Invalid RX & TX vector defined\n",
969 			 __func__);
970 		return -1;
971 	}
972 
973 	ret = pci_alloc_irq_vectors(pdev, 2, STMMAC_MSI_VEC_MAX,
974 				    PCI_IRQ_MSI | PCI_IRQ_MSIX);
975 	if (ret < 0) {
976 		dev_info(&pdev->dev, "%s: multi MSI enablement failed\n",
977 			 __func__);
978 		return ret;
979 	}
980 
981 	/* For RX MSI */
982 	for (i = 0; i < plat->rx_queues_to_use; i++) {
983 		res->rx_irq[i] = pci_irq_vector(pdev,
984 						plat->msi_rx_base_vec + i * 2);
985 	}
986 
987 	/* For TX MSI */
988 	for (i = 0; i < plat->tx_queues_to_use; i++) {
989 		res->tx_irq[i] = pci_irq_vector(pdev,
990 						plat->msi_tx_base_vec + i * 2);
991 	}
992 
993 	if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX)
994 		res->irq = pci_irq_vector(pdev, plat->msi_mac_vec);
995 	if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX)
996 		res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec);
997 	if (plat->msi_lpi_vec < STMMAC_MSI_VEC_MAX)
998 		res->lpi_irq = pci_irq_vector(pdev, plat->msi_lpi_vec);
999 	if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX)
1000 		res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec);
1001 	if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX)
1002 		res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec);
1003 
1004 	plat->multi_msi_en = 1;
1005 	dev_info(&pdev->dev, "%s: multi MSI enablement successful\n", __func__);
1006 
1007 	return 0;
1008 }
1009 
1010 /**
1011  * intel_eth_pci_probe
1012  *
1013  * @pdev: pci device pointer
1014  * @id: pointer to table of device id/id's.
1015  *
1016  * Description: This probing function gets called for all PCI devices which
1017  * match the ID table and are not "owned" by other driver yet. This function
1018  * gets passed a "struct pci_dev *" for each device whose entry in the ID table
1019  * matches the device. The probe functions returns zero when the driver choose
1020  * to take "ownership" of the device or an error code(-ve no) otherwise.
1021  */
1022 static int intel_eth_pci_probe(struct pci_dev *pdev,
1023 			       const struct pci_device_id *id)
1024 {
1025 	struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data;
1026 	struct intel_priv_data *intel_priv;
1027 	struct plat_stmmacenet_data *plat;
1028 	struct stmmac_resources res;
1029 	int ret;
1030 
1031 	intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL);
1032 	if (!intel_priv)
1033 		return -ENOMEM;
1034 
1035 	plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
1036 	if (!plat)
1037 		return -ENOMEM;
1038 
1039 	plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
1040 					   sizeof(*plat->mdio_bus_data),
1041 					   GFP_KERNEL);
1042 	if (!plat->mdio_bus_data)
1043 		return -ENOMEM;
1044 
1045 	plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
1046 				     GFP_KERNEL);
1047 	if (!plat->dma_cfg)
1048 		return -ENOMEM;
1049 
1050 	plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
1051 					     sizeof(*plat->safety_feat_cfg),
1052 					     GFP_KERNEL);
1053 	if (!plat->safety_feat_cfg)
1054 		return -ENOMEM;
1055 
1056 	/* Enable pci device */
1057 	ret = pcim_enable_device(pdev);
1058 	if (ret) {
1059 		dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
1060 			__func__);
1061 		return ret;
1062 	}
1063 
1064 	ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
1065 	if (ret)
1066 		return ret;
1067 
1068 	pci_set_master(pdev);
1069 
1070 	plat->bsp_priv = intel_priv;
1071 	intel_priv->mdio_adhoc_addr = INTEL_MGBE_ADHOC_ADDR;
1072 	intel_priv->crossts_adj = 1;
1073 
1074 	/* Initialize all MSI vectors to invalid so that it can be set
1075 	 * according to platform data settings below.
1076 	 * Note: MSI vector takes value from 0 upto 31 (STMMAC_MSI_VEC_MAX)
1077 	 */
1078 	plat->msi_mac_vec = STMMAC_MSI_VEC_MAX;
1079 	plat->msi_wol_vec = STMMAC_MSI_VEC_MAX;
1080 	plat->msi_lpi_vec = STMMAC_MSI_VEC_MAX;
1081 	plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX;
1082 	plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX;
1083 	plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX;
1084 	plat->msi_tx_base_vec = STMMAC_MSI_VEC_MAX;
1085 
1086 	ret = info->setup(pdev, plat);
1087 	if (ret)
1088 		return ret;
1089 
1090 	memset(&res, 0, sizeof(res));
1091 	res.addr = pcim_iomap_table(pdev)[0];
1092 
1093 	if (plat->eee_usecs_rate > 0) {
1094 		u32 tx_lpi_usec;
1095 
1096 		tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1;
1097 		writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER);
1098 	}
1099 
1100 	ret = stmmac_config_multi_msi(pdev, plat, &res);
1101 	if (ret) {
1102 		ret = stmmac_config_single_msi(pdev, plat, &res);
1103 		if (ret) {
1104 			dev_err(&pdev->dev, "%s: ERROR: failed to enable IRQ\n",
1105 				__func__);
1106 			goto err_alloc_irq;
1107 		}
1108 	}
1109 
1110 	ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
1111 	if (ret) {
1112 		goto err_alloc_irq;
1113 	}
1114 
1115 	return 0;
1116 
1117 err_alloc_irq:
1118 	clk_disable_unprepare(plat->stmmac_clk);
1119 	clk_unregister_fixed_rate(plat->stmmac_clk);
1120 	return ret;
1121 }
1122 
1123 /**
1124  * intel_eth_pci_remove
1125  *
1126  * @pdev: pci device pointer
1127  * Description: this function calls the main to free the net resources
1128  * and releases the PCI resources.
1129  */
1130 static void intel_eth_pci_remove(struct pci_dev *pdev)
1131 {
1132 	struct net_device *ndev = dev_get_drvdata(&pdev->dev);
1133 	struct stmmac_priv *priv = netdev_priv(ndev);
1134 
1135 	stmmac_dvr_remove(&pdev->dev);
1136 
1137 	clk_disable_unprepare(priv->plat->stmmac_clk);
1138 	clk_unregister_fixed_rate(priv->plat->stmmac_clk);
1139 
1140 	pcim_iounmap_regions(pdev, BIT(0));
1141 }
1142 
1143 static int __maybe_unused intel_eth_pci_suspend(struct device *dev)
1144 {
1145 	struct pci_dev *pdev = to_pci_dev(dev);
1146 	int ret;
1147 
1148 	ret = stmmac_suspend(dev);
1149 	if (ret)
1150 		return ret;
1151 
1152 	ret = pci_save_state(pdev);
1153 	if (ret)
1154 		return ret;
1155 
1156 	pci_wake_from_d3(pdev, true);
1157 	pci_set_power_state(pdev, PCI_D3hot);
1158 	return 0;
1159 }
1160 
1161 static int __maybe_unused intel_eth_pci_resume(struct device *dev)
1162 {
1163 	struct pci_dev *pdev = to_pci_dev(dev);
1164 	int ret;
1165 
1166 	pci_restore_state(pdev);
1167 	pci_set_power_state(pdev, PCI_D0);
1168 
1169 	ret = pcim_enable_device(pdev);
1170 	if (ret)
1171 		return ret;
1172 
1173 	pci_set_master(pdev);
1174 
1175 	return stmmac_resume(dev);
1176 }
1177 
1178 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
1179 			 intel_eth_pci_resume);
1180 
1181 #define PCI_DEVICE_ID_INTEL_QUARK		0x0937
1182 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G		0x4b30
1183 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G		0x4b31
1184 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5	0x4b32
1185 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
1186  * which are named PSE0 and PSE1
1187  */
1188 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G	0x4ba0
1189 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G	0x4ba1
1190 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5	0x4ba2
1191 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G	0x4bb0
1192 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G	0x4bb1
1193 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5	0x4bb2
1194 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0	0x43ac
1195 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1	0x43a2
1196 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G		0xa0ac
1197 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0	0x7aac
1198 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1	0x7aad
1199 #define PCI_DEVICE_ID_INTEL_ADLN_SGMII1G	0x54ac
1200 #define PCI_DEVICE_ID_INTEL_RPLP_SGMII1G	0x51ac
1201 
1202 static const struct pci_device_id intel_eth_pci_id_table[] = {
1203 	{ PCI_DEVICE_DATA(INTEL, QUARK, &quark_info) },
1204 	{ PCI_DEVICE_DATA(INTEL, EHL_RGMII1G, &ehl_rgmii1g_info) },
1205 	{ PCI_DEVICE_DATA(INTEL, EHL_SGMII1G, &ehl_sgmii1g_info) },
1206 	{ PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5, &ehl_sgmii1g_info) },
1207 	{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G, &ehl_pse0_rgmii1g_info) },
1208 	{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G, &ehl_pse0_sgmii1g_info) },
1209 	{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5, &ehl_pse0_sgmii1g_info) },
1210 	{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G, &ehl_pse1_rgmii1g_info) },
1211 	{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G, &ehl_pse1_sgmii1g_info) },
1212 	{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5, &ehl_pse1_sgmii1g_info) },
1213 	{ PCI_DEVICE_DATA(INTEL, TGL_SGMII1G, &tgl_sgmii1g_phy0_info) },
1214 	{ PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0, &tgl_sgmii1g_phy0_info) },
1215 	{ PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) },
1216 	{ PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) },
1217 	{ PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) },
1218 	{ PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &tgl_sgmii1g_phy0_info) },
1219 	{ PCI_DEVICE_DATA(INTEL, RPLP_SGMII1G, &tgl_sgmii1g_phy0_info) },
1220 	{}
1221 };
1222 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
1223 
1224 static struct pci_driver intel_eth_pci_driver = {
1225 	.name = "intel-eth-pci",
1226 	.id_table = intel_eth_pci_id_table,
1227 	.probe = intel_eth_pci_probe,
1228 	.remove = intel_eth_pci_remove,
1229 	.driver         = {
1230 		.pm     = &intel_eth_pm_ops,
1231 	},
1232 };
1233 
1234 module_pci_driver(intel_eth_pci_driver);
1235 
1236 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver");
1237 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>");
1238 MODULE_LICENSE("GPL v2");
1239