1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2020, Intel Corporation 3 */ 4 5 #include <linux/clk-provider.h> 6 #include <linux/pci.h> 7 #include <linux/dmi.h> 8 #include "dwmac-intel.h" 9 #include "dwmac4.h" 10 #include "stmmac.h" 11 12 struct intel_priv_data { 13 int mdio_adhoc_addr; /* mdio address for serdes & etc */ 14 }; 15 16 /* This struct is used to associate PCI Function of MAC controller on a board, 17 * discovered via DMI, with the address of PHY connected to the MAC. The 18 * negative value of the address means that MAC controller is not connected 19 * with PHY. 20 */ 21 struct stmmac_pci_func_data { 22 unsigned int func; 23 int phy_addr; 24 }; 25 26 struct stmmac_pci_dmi_data { 27 const struct stmmac_pci_func_data *func; 28 size_t nfuncs; 29 }; 30 31 struct stmmac_pci_info { 32 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); 33 }; 34 35 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, 36 const struct dmi_system_id *dmi_list) 37 { 38 const struct stmmac_pci_func_data *func_data; 39 const struct stmmac_pci_dmi_data *dmi_data; 40 const struct dmi_system_id *dmi_id; 41 int func = PCI_FUNC(pdev->devfn); 42 size_t n; 43 44 dmi_id = dmi_first_match(dmi_list); 45 if (!dmi_id) 46 return -ENODEV; 47 48 dmi_data = dmi_id->driver_data; 49 func_data = dmi_data->func; 50 51 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) 52 if (func_data->func == func) 53 return func_data->phy_addr; 54 55 return -ENODEV; 56 } 57 58 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr, 59 int phyreg, u32 mask, u32 val) 60 { 61 unsigned int retries = 10; 62 int val_rd; 63 64 do { 65 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg); 66 if ((val_rd & mask) == (val & mask)) 67 return 0; 68 udelay(POLL_DELAY_US); 69 } while (--retries); 70 71 return -ETIMEDOUT; 72 } 73 74 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) 75 { 76 struct intel_priv_data *intel_priv = priv_data; 77 struct stmmac_priv *priv = netdev_priv(ndev); 78 int serdes_phy_addr = 0; 79 u32 data = 0; 80 81 if (!intel_priv->mdio_adhoc_addr) 82 return 0; 83 84 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 85 86 /* assert clk_req */ 87 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 88 data |= SERDES_PLL_CLK; 89 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 90 91 /* check for clk_ack assertion */ 92 data = serdes_status_poll(priv, serdes_phy_addr, 93 SERDES_GSR0, 94 SERDES_PLL_CLK, 95 SERDES_PLL_CLK); 96 97 if (data) { 98 dev_err(priv->device, "Serdes PLL clk request timeout\n"); 99 return data; 100 } 101 102 /* assert lane reset */ 103 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 104 data |= SERDES_RST; 105 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 106 107 /* check for assert lane reset reflection */ 108 data = serdes_status_poll(priv, serdes_phy_addr, 109 SERDES_GSR0, 110 SERDES_RST, 111 SERDES_RST); 112 113 if (data) { 114 dev_err(priv->device, "Serdes assert lane reset timeout\n"); 115 return data; 116 } 117 118 /* move power state to P0 */ 119 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 120 121 data &= ~SERDES_PWR_ST_MASK; 122 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT; 123 124 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 125 126 /* Check for P0 state */ 127 data = serdes_status_poll(priv, serdes_phy_addr, 128 SERDES_GSR0, 129 SERDES_PWR_ST_MASK, 130 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT); 131 132 if (data) { 133 dev_err(priv->device, "Serdes power state P0 timeout.\n"); 134 return data; 135 } 136 137 return 0; 138 } 139 140 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) 141 { 142 struct intel_priv_data *intel_priv = intel_data; 143 struct stmmac_priv *priv = netdev_priv(ndev); 144 int serdes_phy_addr = 0; 145 u32 data = 0; 146 147 if (!intel_priv->mdio_adhoc_addr) 148 return; 149 150 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 151 152 /* move power state to P3 */ 153 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 154 155 data &= ~SERDES_PWR_ST_MASK; 156 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT; 157 158 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 159 160 /* Check for P3 state */ 161 data = serdes_status_poll(priv, serdes_phy_addr, 162 SERDES_GSR0, 163 SERDES_PWR_ST_MASK, 164 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT); 165 166 if (data) { 167 dev_err(priv->device, "Serdes power state P3 timeout\n"); 168 return; 169 } 170 171 /* de-assert clk_req */ 172 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 173 data &= ~SERDES_PLL_CLK; 174 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 175 176 /* check for clk_ack de-assert */ 177 data = serdes_status_poll(priv, serdes_phy_addr, 178 SERDES_GSR0, 179 SERDES_PLL_CLK, 180 (u32)~SERDES_PLL_CLK); 181 182 if (data) { 183 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n"); 184 return; 185 } 186 187 /* de-assert lane reset */ 188 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 189 data &= ~SERDES_RST; 190 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 191 192 /* check for de-assert lane reset reflection */ 193 data = serdes_status_poll(priv, serdes_phy_addr, 194 SERDES_GSR0, 195 SERDES_RST, 196 (u32)~SERDES_RST); 197 198 if (data) { 199 dev_err(priv->device, "Serdes de-assert lane reset timeout\n"); 200 return; 201 } 202 } 203 204 static void common_default_data(struct plat_stmmacenet_data *plat) 205 { 206 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ 207 plat->has_gmac = 1; 208 plat->force_sf_dma_mode = 1; 209 210 plat->mdio_bus_data->needs_reset = true; 211 212 /* Set default value for multicast hash bins */ 213 plat->multicast_filter_bins = HASH_TABLE_SIZE; 214 215 /* Set default value for unicast filter entries */ 216 plat->unicast_filter_entries = 1; 217 218 /* Set the maxmtu to a default of JUMBO_LEN */ 219 plat->maxmtu = JUMBO_LEN; 220 221 /* Set default number of RX and TX queues to use */ 222 plat->tx_queues_to_use = 1; 223 plat->rx_queues_to_use = 1; 224 225 /* Disable Priority config by default */ 226 plat->tx_queues_cfg[0].use_prio = false; 227 plat->rx_queues_cfg[0].use_prio = false; 228 229 /* Disable RX queues routing by default */ 230 plat->rx_queues_cfg[0].pkt_route = 0x0; 231 } 232 233 static int intel_mgbe_common_data(struct pci_dev *pdev, 234 struct plat_stmmacenet_data *plat) 235 { 236 int ret; 237 int i; 238 239 plat->pdev = pdev; 240 plat->phy_addr = -1; 241 plat->clk_csr = 5; 242 plat->has_gmac = 0; 243 plat->has_gmac4 = 1; 244 plat->force_sf_dma_mode = 0; 245 plat->tso_en = 1; 246 247 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; 248 249 for (i = 0; i < plat->rx_queues_to_use; i++) { 250 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 251 plat->rx_queues_cfg[i].chan = i; 252 253 /* Disable Priority config by default */ 254 plat->rx_queues_cfg[i].use_prio = false; 255 256 /* Disable RX queues routing by default */ 257 plat->rx_queues_cfg[i].pkt_route = 0x0; 258 } 259 260 for (i = 0; i < plat->tx_queues_to_use; i++) { 261 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 262 263 /* Disable Priority config by default */ 264 plat->tx_queues_cfg[i].use_prio = false; 265 } 266 267 /* FIFO size is 4096 bytes for 1 tx/rx queue */ 268 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; 269 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; 270 271 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; 272 plat->tx_queues_cfg[0].weight = 0x09; 273 plat->tx_queues_cfg[1].weight = 0x0A; 274 plat->tx_queues_cfg[2].weight = 0x0B; 275 plat->tx_queues_cfg[3].weight = 0x0C; 276 plat->tx_queues_cfg[4].weight = 0x0D; 277 plat->tx_queues_cfg[5].weight = 0x0E; 278 plat->tx_queues_cfg[6].weight = 0x0F; 279 plat->tx_queues_cfg[7].weight = 0x10; 280 281 plat->dma_cfg->pbl = 32; 282 plat->dma_cfg->pblx8 = true; 283 plat->dma_cfg->fixed_burst = 0; 284 plat->dma_cfg->mixed_burst = 0; 285 plat->dma_cfg->aal = 0; 286 287 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), 288 GFP_KERNEL); 289 if (!plat->axi) 290 return -ENOMEM; 291 292 plat->axi->axi_lpi_en = 0; 293 plat->axi->axi_xit_frm = 0; 294 plat->axi->axi_wr_osr_lmt = 1; 295 plat->axi->axi_rd_osr_lmt = 1; 296 plat->axi->axi_blen[0] = 4; 297 plat->axi->axi_blen[1] = 8; 298 plat->axi->axi_blen[2] = 16; 299 300 plat->ptp_max_adj = plat->clk_ptp_rate; 301 plat->eee_usecs_rate = plat->clk_ptp_rate; 302 303 /* Set system clock */ 304 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, 305 "stmmac-clk", NULL, 0, 306 plat->clk_ptp_rate); 307 308 if (IS_ERR(plat->stmmac_clk)) { 309 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); 310 plat->stmmac_clk = NULL; 311 } 312 313 ret = clk_prepare_enable(plat->stmmac_clk); 314 if (ret) { 315 clk_unregister_fixed_rate(plat->stmmac_clk); 316 return ret; 317 } 318 319 /* Set default value for multicast hash bins */ 320 plat->multicast_filter_bins = HASH_TABLE_SIZE; 321 322 /* Set default value for unicast filter entries */ 323 plat->unicast_filter_entries = 1; 324 325 /* Set the maxmtu to a default of JUMBO_LEN */ 326 plat->maxmtu = JUMBO_LEN; 327 328 plat->vlan_fail_q_en = true; 329 330 /* Use the last Rx queue */ 331 plat->vlan_fail_q = plat->rx_queues_to_use - 1; 332 333 return 0; 334 } 335 336 static int ehl_common_data(struct pci_dev *pdev, 337 struct plat_stmmacenet_data *plat) 338 { 339 plat->rx_queues_to_use = 8; 340 plat->tx_queues_to_use = 8; 341 plat->clk_ptp_rate = 200000000; 342 343 return intel_mgbe_common_data(pdev, plat); 344 } 345 346 static int ehl_sgmii_data(struct pci_dev *pdev, 347 struct plat_stmmacenet_data *plat) 348 { 349 plat->bus_id = 1; 350 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 351 352 plat->serdes_powerup = intel_serdes_powerup; 353 plat->serdes_powerdown = intel_serdes_powerdown; 354 355 return ehl_common_data(pdev, plat); 356 } 357 358 static struct stmmac_pci_info ehl_sgmii1g_info = { 359 .setup = ehl_sgmii_data, 360 }; 361 362 static int ehl_rgmii_data(struct pci_dev *pdev, 363 struct plat_stmmacenet_data *plat) 364 { 365 plat->bus_id = 1; 366 plat->phy_interface = PHY_INTERFACE_MODE_RGMII; 367 368 return ehl_common_data(pdev, plat); 369 } 370 371 static struct stmmac_pci_info ehl_rgmii1g_info = { 372 .setup = ehl_rgmii_data, 373 }; 374 375 static int ehl_pse0_common_data(struct pci_dev *pdev, 376 struct plat_stmmacenet_data *plat) 377 { 378 plat->bus_id = 2; 379 plat->addr64 = 32; 380 return ehl_common_data(pdev, plat); 381 } 382 383 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev, 384 struct plat_stmmacenet_data *plat) 385 { 386 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 387 return ehl_pse0_common_data(pdev, plat); 388 } 389 390 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = { 391 .setup = ehl_pse0_rgmii1g_data, 392 }; 393 394 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, 395 struct plat_stmmacenet_data *plat) 396 { 397 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 398 plat->serdes_powerup = intel_serdes_powerup; 399 plat->serdes_powerdown = intel_serdes_powerdown; 400 return ehl_pse0_common_data(pdev, plat); 401 } 402 403 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = { 404 .setup = ehl_pse0_sgmii1g_data, 405 }; 406 407 static int ehl_pse1_common_data(struct pci_dev *pdev, 408 struct plat_stmmacenet_data *plat) 409 { 410 plat->bus_id = 3; 411 plat->addr64 = 32; 412 return ehl_common_data(pdev, plat); 413 } 414 415 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev, 416 struct plat_stmmacenet_data *plat) 417 { 418 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 419 return ehl_pse1_common_data(pdev, plat); 420 } 421 422 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = { 423 .setup = ehl_pse1_rgmii1g_data, 424 }; 425 426 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, 427 struct plat_stmmacenet_data *plat) 428 { 429 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 430 plat->serdes_powerup = intel_serdes_powerup; 431 plat->serdes_powerdown = intel_serdes_powerdown; 432 return ehl_pse1_common_data(pdev, plat); 433 } 434 435 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = { 436 .setup = ehl_pse1_sgmii1g_data, 437 }; 438 439 static int tgl_common_data(struct pci_dev *pdev, 440 struct plat_stmmacenet_data *plat) 441 { 442 plat->rx_queues_to_use = 6; 443 plat->tx_queues_to_use = 4; 444 plat->clk_ptp_rate = 200000000; 445 446 return intel_mgbe_common_data(pdev, plat); 447 } 448 449 static int tgl_sgmii_data(struct pci_dev *pdev, 450 struct plat_stmmacenet_data *plat) 451 { 452 plat->bus_id = 1; 453 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 454 plat->serdes_powerup = intel_serdes_powerup; 455 plat->serdes_powerdown = intel_serdes_powerdown; 456 return tgl_common_data(pdev, plat); 457 } 458 459 static struct stmmac_pci_info tgl_sgmii1g_info = { 460 .setup = tgl_sgmii_data, 461 }; 462 463 static int adls_sgmii_data(struct pci_dev *pdev, 464 struct plat_stmmacenet_data *plat) 465 { 466 plat->bus_id = 1; 467 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 468 469 /* SerDes power up and power down are done in BIOS for ADL */ 470 471 return tgl_common_data(pdev, plat); 472 } 473 474 static struct stmmac_pci_info adls_sgmii1g_info = { 475 .setup = adls_sgmii_data, 476 }; 477 478 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { 479 { 480 .func = 6, 481 .phy_addr = 1, 482 }, 483 }; 484 485 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = { 486 .func = galileo_stmmac_func_data, 487 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data), 488 }; 489 490 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = { 491 { 492 .func = 6, 493 .phy_addr = 1, 494 }, 495 { 496 .func = 7, 497 .phy_addr = 1, 498 }, 499 }; 500 501 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = { 502 .func = iot2040_stmmac_func_data, 503 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data), 504 }; 505 506 static const struct dmi_system_id quark_pci_dmi[] = { 507 { 508 .matches = { 509 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 510 }, 511 .driver_data = (void *)&galileo_stmmac_dmi_data, 512 }, 513 { 514 .matches = { 515 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 516 }, 517 .driver_data = (void *)&galileo_stmmac_dmi_data, 518 }, 519 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040. 520 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which 521 * has only one pci network device while other asset tags are 522 * for IOT2040 which has two. 523 */ 524 { 525 .matches = { 526 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 527 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG, 528 "6ES7647-0AA00-0YA2"), 529 }, 530 .driver_data = (void *)&galileo_stmmac_dmi_data, 531 }, 532 { 533 .matches = { 534 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 535 }, 536 .driver_data = (void *)&iot2040_stmmac_dmi_data, 537 }, 538 {} 539 }; 540 541 static int quark_default_data(struct pci_dev *pdev, 542 struct plat_stmmacenet_data *plat) 543 { 544 int ret; 545 546 /* Set common default data first */ 547 common_default_data(plat); 548 549 /* Refuse to load the driver and register net device if MAC controller 550 * does not connect to any PHY interface. 551 */ 552 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi); 553 if (ret < 0) { 554 /* Return error to the caller on DMI enabled boards. */ 555 if (dmi_get_system_info(DMI_BOARD_NAME)) 556 return ret; 557 558 /* Galileo boards with old firmware don't support DMI. We always 559 * use 1 here as PHY address, so at least the first found MAC 560 * controller would be probed. 561 */ 562 ret = 1; 563 } 564 565 plat->bus_id = pci_dev_id(pdev); 566 plat->phy_addr = ret; 567 plat->phy_interface = PHY_INTERFACE_MODE_RMII; 568 569 plat->dma_cfg->pbl = 16; 570 plat->dma_cfg->pblx8 = true; 571 plat->dma_cfg->fixed_burst = 1; 572 /* AXI (TODO) */ 573 574 return 0; 575 } 576 577 static const struct stmmac_pci_info quark_info = { 578 .setup = quark_default_data, 579 }; 580 581 /** 582 * intel_eth_pci_probe 583 * 584 * @pdev: pci device pointer 585 * @id: pointer to table of device id/id's. 586 * 587 * Description: This probing function gets called for all PCI devices which 588 * match the ID table and are not "owned" by other driver yet. This function 589 * gets passed a "struct pci_dev *" for each device whose entry in the ID table 590 * matches the device. The probe functions returns zero when the driver choose 591 * to take "ownership" of the device or an error code(-ve no) otherwise. 592 */ 593 static int intel_eth_pci_probe(struct pci_dev *pdev, 594 const struct pci_device_id *id) 595 { 596 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; 597 struct intel_priv_data *intel_priv; 598 struct plat_stmmacenet_data *plat; 599 struct stmmac_resources res; 600 int ret; 601 602 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL); 603 if (!intel_priv) 604 return -ENOMEM; 605 606 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 607 if (!plat) 608 return -ENOMEM; 609 610 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, 611 sizeof(*plat->mdio_bus_data), 612 GFP_KERNEL); 613 if (!plat->mdio_bus_data) 614 return -ENOMEM; 615 616 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), 617 GFP_KERNEL); 618 if (!plat->dma_cfg) 619 return -ENOMEM; 620 621 /* Enable pci device */ 622 ret = pci_enable_device(pdev); 623 if (ret) { 624 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", 625 __func__); 626 return ret; 627 } 628 629 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 630 if (ret) 631 return ret; 632 633 pci_set_master(pdev); 634 635 plat->bsp_priv = intel_priv; 636 intel_priv->mdio_adhoc_addr = 0x15; 637 638 ret = info->setup(pdev, plat); 639 if (ret) 640 return ret; 641 642 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 643 if (ret < 0) 644 return ret; 645 646 memset(&res, 0, sizeof(res)); 647 res.addr = pcim_iomap_table(pdev)[0]; 648 res.wol_irq = pci_irq_vector(pdev, 0); 649 res.irq = pci_irq_vector(pdev, 0); 650 651 if (plat->eee_usecs_rate > 0) { 652 u32 tx_lpi_usec; 653 654 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1; 655 writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER); 656 } 657 658 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); 659 if (ret) { 660 pci_free_irq_vectors(pdev); 661 clk_disable_unprepare(plat->stmmac_clk); 662 clk_unregister_fixed_rate(plat->stmmac_clk); 663 } 664 665 return ret; 666 } 667 668 /** 669 * intel_eth_pci_remove 670 * 671 * @pdev: platform device pointer 672 * Description: this function calls the main to free the net resources 673 * and releases the PCI resources. 674 */ 675 static void intel_eth_pci_remove(struct pci_dev *pdev) 676 { 677 struct net_device *ndev = dev_get_drvdata(&pdev->dev); 678 struct stmmac_priv *priv = netdev_priv(ndev); 679 680 stmmac_dvr_remove(&pdev->dev); 681 682 pci_free_irq_vectors(pdev); 683 684 clk_unregister_fixed_rate(priv->plat->stmmac_clk); 685 686 pcim_iounmap_regions(pdev, BIT(0)); 687 688 pci_disable_device(pdev); 689 } 690 691 static int __maybe_unused intel_eth_pci_suspend(struct device *dev) 692 { 693 struct pci_dev *pdev = to_pci_dev(dev); 694 int ret; 695 696 ret = stmmac_suspend(dev); 697 if (ret) 698 return ret; 699 700 ret = pci_save_state(pdev); 701 if (ret) 702 return ret; 703 704 pci_disable_device(pdev); 705 pci_wake_from_d3(pdev, true); 706 return 0; 707 } 708 709 static int __maybe_unused intel_eth_pci_resume(struct device *dev) 710 { 711 struct pci_dev *pdev = to_pci_dev(dev); 712 int ret; 713 714 pci_restore_state(pdev); 715 pci_set_power_state(pdev, PCI_D0); 716 717 ret = pci_enable_device(pdev); 718 if (ret) 719 return ret; 720 721 pci_set_master(pdev); 722 723 return stmmac_resume(dev); 724 } 725 726 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend, 727 intel_eth_pci_resume); 728 729 #define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937 730 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30 731 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31 732 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID 0x4b32 733 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC 734 * which are named PSE0 and PSE1 735 */ 736 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0 737 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1 738 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2 739 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0 740 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1 741 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2 742 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0_ID 0x43ac 743 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1_ID 0x43a2 744 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac 745 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0_ID 0x7aac 746 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1_ID 0x7aad 747 748 static const struct pci_device_id intel_eth_pci_id_table[] = { 749 { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) }, 750 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_info) }, 751 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_info) }, 752 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_info) }, 753 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, &ehl_pse0_rgmii1g_info) }, 754 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, &ehl_pse0_sgmii1g_info) }, 755 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, &ehl_pse0_sgmii1g_info) }, 756 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, &ehl_pse1_rgmii1g_info) }, 757 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, &ehl_pse1_sgmii1g_info) }, 758 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, &ehl_pse1_sgmii1g_info) }, 759 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_info) }, 760 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0_ID, &tgl_sgmii1g_info) }, 761 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1_ID, &tgl_sgmii1g_info) }, 762 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0_ID, &adls_sgmii1g_info) }, 763 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1_ID, &adls_sgmii1g_info) }, 764 {} 765 }; 766 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table); 767 768 static struct pci_driver intel_eth_pci_driver = { 769 .name = "intel-eth-pci", 770 .id_table = intel_eth_pci_id_table, 771 .probe = intel_eth_pci_probe, 772 .remove = intel_eth_pci_remove, 773 .driver = { 774 .pm = &intel_eth_pm_ops, 775 }, 776 }; 777 778 module_pci_driver(intel_eth_pci_driver); 779 780 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver"); 781 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>"); 782 MODULE_LICENSE("GPL v2"); 783