1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2020, Intel Corporation 3 */ 4 5 #include <linux/clk-provider.h> 6 #include <linux/pci.h> 7 #include <linux/dmi.h> 8 #include "dwmac-intel.h" 9 #include "dwmac4.h" 10 #include "stmmac.h" 11 #include "stmmac_ptp.h" 12 13 struct intel_priv_data { 14 int mdio_adhoc_addr; /* mdio address for serdes & etc */ 15 unsigned long crossts_adj; 16 bool is_pse; 17 }; 18 19 /* This struct is used to associate PCI Function of MAC controller on a board, 20 * discovered via DMI, with the address of PHY connected to the MAC. The 21 * negative value of the address means that MAC controller is not connected 22 * with PHY. 23 */ 24 struct stmmac_pci_func_data { 25 unsigned int func; 26 int phy_addr; 27 }; 28 29 struct stmmac_pci_dmi_data { 30 const struct stmmac_pci_func_data *func; 31 size_t nfuncs; 32 }; 33 34 struct stmmac_pci_info { 35 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); 36 }; 37 38 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, 39 const struct dmi_system_id *dmi_list) 40 { 41 const struct stmmac_pci_func_data *func_data; 42 const struct stmmac_pci_dmi_data *dmi_data; 43 const struct dmi_system_id *dmi_id; 44 int func = PCI_FUNC(pdev->devfn); 45 size_t n; 46 47 dmi_id = dmi_first_match(dmi_list); 48 if (!dmi_id) 49 return -ENODEV; 50 51 dmi_data = dmi_id->driver_data; 52 func_data = dmi_data->func; 53 54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) 55 if (func_data->func == func) 56 return func_data->phy_addr; 57 58 return -ENODEV; 59 } 60 61 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr, 62 int phyreg, u32 mask, u32 val) 63 { 64 unsigned int retries = 10; 65 int val_rd; 66 67 do { 68 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg); 69 if ((val_rd & mask) == (val & mask)) 70 return 0; 71 udelay(POLL_DELAY_US); 72 } while (--retries); 73 74 return -ETIMEDOUT; 75 } 76 77 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) 78 { 79 struct intel_priv_data *intel_priv = priv_data; 80 struct stmmac_priv *priv = netdev_priv(ndev); 81 int serdes_phy_addr = 0; 82 u32 data = 0; 83 84 if (!intel_priv->mdio_adhoc_addr) 85 return 0; 86 87 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 88 89 /* Set the serdes rate and the PCLK rate */ 90 data = mdiobus_read(priv->mii, serdes_phy_addr, 91 SERDES_GCR0); 92 93 data &= ~SERDES_RATE_MASK; 94 data &= ~SERDES_PCLK_MASK; 95 96 if (priv->plat->max_speed == 2500) 97 data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT | 98 SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT; 99 else 100 data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT | 101 SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT; 102 103 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 104 105 /* assert clk_req */ 106 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 107 data |= SERDES_PLL_CLK; 108 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 109 110 /* check for clk_ack assertion */ 111 data = serdes_status_poll(priv, serdes_phy_addr, 112 SERDES_GSR0, 113 SERDES_PLL_CLK, 114 SERDES_PLL_CLK); 115 116 if (data) { 117 dev_err(priv->device, "Serdes PLL clk request timeout\n"); 118 return data; 119 } 120 121 /* assert lane reset */ 122 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 123 data |= SERDES_RST; 124 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 125 126 /* check for assert lane reset reflection */ 127 data = serdes_status_poll(priv, serdes_phy_addr, 128 SERDES_GSR0, 129 SERDES_RST, 130 SERDES_RST); 131 132 if (data) { 133 dev_err(priv->device, "Serdes assert lane reset timeout\n"); 134 return data; 135 } 136 137 /* move power state to P0 */ 138 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 139 140 data &= ~SERDES_PWR_ST_MASK; 141 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT; 142 143 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 144 145 /* Check for P0 state */ 146 data = serdes_status_poll(priv, serdes_phy_addr, 147 SERDES_GSR0, 148 SERDES_PWR_ST_MASK, 149 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT); 150 151 if (data) { 152 dev_err(priv->device, "Serdes power state P0 timeout.\n"); 153 return data; 154 } 155 156 /* PSE only - ungate SGMII PHY Rx Clock */ 157 if (intel_priv->is_pse) 158 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, 159 0, SERDES_PHY_RX_CLK); 160 161 return 0; 162 } 163 164 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) 165 { 166 struct intel_priv_data *intel_priv = intel_data; 167 struct stmmac_priv *priv = netdev_priv(ndev); 168 int serdes_phy_addr = 0; 169 u32 data = 0; 170 171 if (!intel_priv->mdio_adhoc_addr) 172 return; 173 174 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 175 176 /* PSE only - gate SGMII PHY Rx Clock */ 177 if (intel_priv->is_pse) 178 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, 179 SERDES_PHY_RX_CLK, 0); 180 181 /* move power state to P3 */ 182 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 183 184 data &= ~SERDES_PWR_ST_MASK; 185 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT; 186 187 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 188 189 /* Check for P3 state */ 190 data = serdes_status_poll(priv, serdes_phy_addr, 191 SERDES_GSR0, 192 SERDES_PWR_ST_MASK, 193 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT); 194 195 if (data) { 196 dev_err(priv->device, "Serdes power state P3 timeout\n"); 197 return; 198 } 199 200 /* de-assert clk_req */ 201 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 202 data &= ~SERDES_PLL_CLK; 203 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 204 205 /* check for clk_ack de-assert */ 206 data = serdes_status_poll(priv, serdes_phy_addr, 207 SERDES_GSR0, 208 SERDES_PLL_CLK, 209 (u32)~SERDES_PLL_CLK); 210 211 if (data) { 212 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n"); 213 return; 214 } 215 216 /* de-assert lane reset */ 217 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 218 data &= ~SERDES_RST; 219 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 220 221 /* check for de-assert lane reset reflection */ 222 data = serdes_status_poll(priv, serdes_phy_addr, 223 SERDES_GSR0, 224 SERDES_RST, 225 (u32)~SERDES_RST); 226 227 if (data) { 228 dev_err(priv->device, "Serdes de-assert lane reset timeout\n"); 229 return; 230 } 231 } 232 233 static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data) 234 { 235 struct intel_priv_data *intel_priv = intel_data; 236 struct stmmac_priv *priv = netdev_priv(ndev); 237 int serdes_phy_addr = 0; 238 u32 data = 0; 239 240 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 241 242 /* Determine the link speed mode: 2.5Gbps/1Gbps */ 243 data = mdiobus_read(priv->mii, serdes_phy_addr, 244 SERDES_GCR); 245 246 if (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) == 247 SERDES_LINK_MODE_2G5) { 248 dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n"); 249 priv->plat->max_speed = 2500; 250 priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX; 251 priv->plat->mdio_bus_data->xpcs_an_inband = false; 252 } else { 253 priv->plat->max_speed = 1000; 254 } 255 } 256 257 /* Program PTP Clock Frequency for different variant of 258 * Intel mGBE that has slightly different GPO mapping 259 */ 260 static void intel_mgbe_ptp_clk_freq_config(void *npriv) 261 { 262 struct stmmac_priv *priv = (struct stmmac_priv *)npriv; 263 struct intel_priv_data *intel_priv; 264 u32 gpio_value; 265 266 intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv; 267 268 gpio_value = readl(priv->ioaddr + GMAC_GPIO_STATUS); 269 270 if (intel_priv->is_pse) { 271 /* For PSE GbE, use 200MHz */ 272 gpio_value &= ~PSE_PTP_CLK_FREQ_MASK; 273 gpio_value |= PSE_PTP_CLK_FREQ_200MHZ; 274 } else { 275 /* For PCH GbE, use 200MHz */ 276 gpio_value &= ~PCH_PTP_CLK_FREQ_MASK; 277 gpio_value |= PCH_PTP_CLK_FREQ_200MHZ; 278 } 279 280 writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS); 281 } 282 283 static void get_arttime(struct mii_bus *mii, int intel_adhoc_addr, 284 u64 *art_time) 285 { 286 u64 ns; 287 288 ns = mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE3); 289 ns <<= GMAC4_ART_TIME_SHIFT; 290 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE2); 291 ns <<= GMAC4_ART_TIME_SHIFT; 292 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE1); 293 ns <<= GMAC4_ART_TIME_SHIFT; 294 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE0); 295 296 *art_time = ns; 297 } 298 299 static int stmmac_cross_ts_isr(struct stmmac_priv *priv) 300 { 301 return (readl(priv->ioaddr + GMAC_INT_STATUS) & GMAC_INT_TSIE); 302 } 303 304 static int intel_crosststamp(ktime_t *device, 305 struct system_counterval_t *system, 306 void *ctx) 307 { 308 struct intel_priv_data *intel_priv; 309 310 struct stmmac_priv *priv = (struct stmmac_priv *)ctx; 311 void __iomem *ptpaddr = priv->ptpaddr; 312 void __iomem *ioaddr = priv->hw->pcsr; 313 unsigned long flags; 314 u64 art_time = 0; 315 u64 ptp_time = 0; 316 u32 num_snapshot; 317 u32 gpio_value; 318 u32 acr_value; 319 int i; 320 321 if (!boot_cpu_has(X86_FEATURE_ART)) 322 return -EOPNOTSUPP; 323 324 intel_priv = priv->plat->bsp_priv; 325 326 /* Both internal crosstimestamping and external triggered event 327 * timestamping cannot be run concurrently. 328 */ 329 if (priv->plat->ext_snapshot_en) 330 return -EBUSY; 331 332 priv->plat->int_snapshot_en = 1; 333 334 mutex_lock(&priv->aux_ts_lock); 335 /* Enable Internal snapshot trigger */ 336 acr_value = readl(ptpaddr + PTP_ACR); 337 acr_value &= ~PTP_ACR_MASK; 338 switch (priv->plat->int_snapshot_num) { 339 case AUX_SNAPSHOT0: 340 acr_value |= PTP_ACR_ATSEN0; 341 break; 342 case AUX_SNAPSHOT1: 343 acr_value |= PTP_ACR_ATSEN1; 344 break; 345 case AUX_SNAPSHOT2: 346 acr_value |= PTP_ACR_ATSEN2; 347 break; 348 case AUX_SNAPSHOT3: 349 acr_value |= PTP_ACR_ATSEN3; 350 break; 351 default: 352 mutex_unlock(&priv->aux_ts_lock); 353 priv->plat->int_snapshot_en = 0; 354 return -EINVAL; 355 } 356 writel(acr_value, ptpaddr + PTP_ACR); 357 358 /* Clear FIFO */ 359 acr_value = readl(ptpaddr + PTP_ACR); 360 acr_value |= PTP_ACR_ATSFC; 361 writel(acr_value, ptpaddr + PTP_ACR); 362 /* Release the mutex */ 363 mutex_unlock(&priv->aux_ts_lock); 364 365 /* Trigger Internal snapshot signal 366 * Create a rising edge by just toggle the GPO1 to low 367 * and back to high. 368 */ 369 gpio_value = readl(ioaddr + GMAC_GPIO_STATUS); 370 gpio_value &= ~GMAC_GPO1; 371 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS); 372 gpio_value |= GMAC_GPO1; 373 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS); 374 375 /* Time sync done Indication - Interrupt method */ 376 if (!wait_event_interruptible_timeout(priv->tstamp_busy_wait, 377 stmmac_cross_ts_isr(priv), 378 HZ / 100)) { 379 priv->plat->int_snapshot_en = 0; 380 return -ETIMEDOUT; 381 } 382 383 num_snapshot = (readl(ioaddr + GMAC_TIMESTAMP_STATUS) & 384 GMAC_TIMESTAMP_ATSNS_MASK) >> 385 GMAC_TIMESTAMP_ATSNS_SHIFT; 386 387 /* Repeat until the timestamps are from the FIFO last segment */ 388 for (i = 0; i < num_snapshot; i++) { 389 read_lock_irqsave(&priv->ptp_lock, flags); 390 stmmac_get_ptptime(priv, ptpaddr, &ptp_time); 391 *device = ns_to_ktime(ptp_time); 392 read_unlock_irqrestore(&priv->ptp_lock, flags); 393 get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time); 394 *system = convert_art_to_tsc(art_time); 395 } 396 397 system->cycles *= intel_priv->crossts_adj; 398 priv->plat->int_snapshot_en = 0; 399 400 return 0; 401 } 402 403 static void intel_mgbe_pse_crossts_adj(struct intel_priv_data *intel_priv, 404 int base) 405 { 406 if (boot_cpu_has(X86_FEATURE_ART)) { 407 unsigned int art_freq; 408 409 /* On systems that support ART, ART frequency can be obtained 410 * from ECX register of CPUID leaf (0x15). 411 */ 412 art_freq = cpuid_ecx(ART_CPUID_LEAF); 413 do_div(art_freq, base); 414 intel_priv->crossts_adj = art_freq; 415 } 416 } 417 418 static void common_default_data(struct plat_stmmacenet_data *plat) 419 { 420 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ 421 plat->has_gmac = 1; 422 plat->force_sf_dma_mode = 1; 423 424 plat->mdio_bus_data->needs_reset = true; 425 426 /* Set default value for multicast hash bins */ 427 plat->multicast_filter_bins = HASH_TABLE_SIZE; 428 429 /* Set default value for unicast filter entries */ 430 plat->unicast_filter_entries = 1; 431 432 /* Set the maxmtu to a default of JUMBO_LEN */ 433 plat->maxmtu = JUMBO_LEN; 434 435 /* Set default number of RX and TX queues to use */ 436 plat->tx_queues_to_use = 1; 437 plat->rx_queues_to_use = 1; 438 439 /* Disable Priority config by default */ 440 plat->tx_queues_cfg[0].use_prio = false; 441 plat->rx_queues_cfg[0].use_prio = false; 442 443 /* Disable RX queues routing by default */ 444 plat->rx_queues_cfg[0].pkt_route = 0x0; 445 } 446 447 static int intel_mgbe_common_data(struct pci_dev *pdev, 448 struct plat_stmmacenet_data *plat) 449 { 450 struct fwnode_handle *fwnode; 451 char clk_name[20]; 452 int ret; 453 int i; 454 455 plat->pdev = pdev; 456 plat->phy_addr = -1; 457 plat->clk_csr = 5; 458 plat->has_gmac = 0; 459 plat->has_gmac4 = 1; 460 plat->force_sf_dma_mode = 0; 461 plat->tso_en = 1; 462 plat->sph_disable = 1; 463 464 /* Multiplying factor to the clk_eee_i clock time 465 * period to make it closer to 100 ns. This value 466 * should be programmed such that the clk_eee_time_period * 467 * (MULT_FACT_100NS + 1) should be within 80 ns to 120 ns 468 * clk_eee frequency is 19.2Mhz 469 * clk_eee_time_period is 52ns 470 * 52ns * (1 + 1) = 104ns 471 * MULT_FACT_100NS = 1 472 */ 473 plat->mult_fact_100ns = 1; 474 475 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; 476 477 for (i = 0; i < plat->rx_queues_to_use; i++) { 478 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 479 plat->rx_queues_cfg[i].chan = i; 480 481 /* Disable Priority config by default */ 482 plat->rx_queues_cfg[i].use_prio = false; 483 484 /* Disable RX queues routing by default */ 485 plat->rx_queues_cfg[i].pkt_route = 0x0; 486 } 487 488 for (i = 0; i < plat->tx_queues_to_use; i++) { 489 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 490 491 /* Disable Priority config by default */ 492 plat->tx_queues_cfg[i].use_prio = false; 493 /* Default TX Q0 to use TSO and rest TXQ for TBS */ 494 if (i > 0) 495 plat->tx_queues_cfg[i].tbs_en = 1; 496 } 497 498 /* FIFO size is 4096 bytes for 1 tx/rx queue */ 499 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; 500 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; 501 502 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; 503 plat->tx_queues_cfg[0].weight = 0x09; 504 plat->tx_queues_cfg[1].weight = 0x0A; 505 plat->tx_queues_cfg[2].weight = 0x0B; 506 plat->tx_queues_cfg[3].weight = 0x0C; 507 plat->tx_queues_cfg[4].weight = 0x0D; 508 plat->tx_queues_cfg[5].weight = 0x0E; 509 plat->tx_queues_cfg[6].weight = 0x0F; 510 plat->tx_queues_cfg[7].weight = 0x10; 511 512 plat->dma_cfg->pbl = 32; 513 plat->dma_cfg->pblx8 = true; 514 plat->dma_cfg->fixed_burst = 0; 515 plat->dma_cfg->mixed_burst = 0; 516 plat->dma_cfg->aal = 0; 517 plat->dma_cfg->dche = true; 518 519 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), 520 GFP_KERNEL); 521 if (!plat->axi) 522 return -ENOMEM; 523 524 plat->axi->axi_lpi_en = 0; 525 plat->axi->axi_xit_frm = 0; 526 plat->axi->axi_wr_osr_lmt = 1; 527 plat->axi->axi_rd_osr_lmt = 1; 528 plat->axi->axi_blen[0] = 4; 529 plat->axi->axi_blen[1] = 8; 530 plat->axi->axi_blen[2] = 16; 531 532 plat->ptp_max_adj = plat->clk_ptp_rate; 533 plat->eee_usecs_rate = plat->clk_ptp_rate; 534 535 /* Set system clock */ 536 sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev)); 537 538 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, 539 clk_name, NULL, 0, 540 plat->clk_ptp_rate); 541 542 if (IS_ERR(plat->stmmac_clk)) { 543 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); 544 plat->stmmac_clk = NULL; 545 } 546 547 ret = clk_prepare_enable(plat->stmmac_clk); 548 if (ret) { 549 clk_unregister_fixed_rate(plat->stmmac_clk); 550 return ret; 551 } 552 553 plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config; 554 555 /* Set default value for multicast hash bins */ 556 plat->multicast_filter_bins = HASH_TABLE_SIZE; 557 558 /* Set default value for unicast filter entries */ 559 plat->unicast_filter_entries = 1; 560 561 /* Set the maxmtu to a default of JUMBO_LEN */ 562 plat->maxmtu = JUMBO_LEN; 563 564 plat->vlan_fail_q_en = true; 565 566 /* Use the last Rx queue */ 567 plat->vlan_fail_q = plat->rx_queues_to_use - 1; 568 569 /* For fixed-link setup, we allow phy-mode setting */ 570 fwnode = dev_fwnode(&pdev->dev); 571 if (fwnode) { 572 int phy_mode; 573 574 /* "phy-mode" setting is optional. If it is set, 575 * we allow either sgmii or 1000base-x for now. 576 */ 577 phy_mode = fwnode_get_phy_mode(fwnode); 578 if (phy_mode >= 0) { 579 if (phy_mode == PHY_INTERFACE_MODE_SGMII || 580 phy_mode == PHY_INTERFACE_MODE_1000BASEX) 581 plat->phy_interface = phy_mode; 582 else 583 dev_warn(&pdev->dev, "Invalid phy-mode\n"); 584 } 585 } 586 587 /* Intel mgbe SGMII interface uses pcs-xcps */ 588 if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII || 589 plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { 590 plat->mdio_bus_data->has_xpcs = true; 591 plat->mdio_bus_data->xpcs_an_inband = true; 592 } 593 594 /* For fixed-link setup, we clear xpcs_an_inband */ 595 if (fwnode) { 596 struct fwnode_handle *fixed_node; 597 598 fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link"); 599 if (fixed_node) 600 plat->mdio_bus_data->xpcs_an_inband = false; 601 602 fwnode_handle_put(fixed_node); 603 } 604 605 /* Ensure mdio bus scan skips intel serdes and pcs-xpcs */ 606 plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR; 607 plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR; 608 609 plat->int_snapshot_num = AUX_SNAPSHOT1; 610 plat->ext_snapshot_num = AUX_SNAPSHOT0; 611 612 plat->crosststamp = intel_crosststamp; 613 plat->int_snapshot_en = 0; 614 615 /* Setup MSI vector offset specific to Intel mGbE controller */ 616 plat->msi_mac_vec = 29; 617 plat->msi_lpi_vec = 28; 618 plat->msi_sfty_ce_vec = 27; 619 plat->msi_sfty_ue_vec = 26; 620 plat->msi_rx_base_vec = 0; 621 plat->msi_tx_base_vec = 1; 622 623 return 0; 624 } 625 626 static int ehl_common_data(struct pci_dev *pdev, 627 struct plat_stmmacenet_data *plat) 628 { 629 plat->rx_queues_to_use = 8; 630 plat->tx_queues_to_use = 8; 631 plat->use_phy_wol = 1; 632 633 plat->safety_feat_cfg->tsoee = 1; 634 plat->safety_feat_cfg->mrxpee = 1; 635 plat->safety_feat_cfg->mestee = 1; 636 plat->safety_feat_cfg->mrxee = 1; 637 plat->safety_feat_cfg->mtxee = 1; 638 plat->safety_feat_cfg->epsi = 0; 639 plat->safety_feat_cfg->edpp = 0; 640 plat->safety_feat_cfg->prtyen = 0; 641 plat->safety_feat_cfg->tmouten = 0; 642 643 return intel_mgbe_common_data(pdev, plat); 644 } 645 646 static int ehl_sgmii_data(struct pci_dev *pdev, 647 struct plat_stmmacenet_data *plat) 648 { 649 plat->bus_id = 1; 650 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 651 plat->speed_mode_2500 = intel_speed_mode_2500; 652 plat->serdes_powerup = intel_serdes_powerup; 653 plat->serdes_powerdown = intel_serdes_powerdown; 654 655 plat->clk_ptp_rate = 204800000; 656 657 return ehl_common_data(pdev, plat); 658 } 659 660 static struct stmmac_pci_info ehl_sgmii1g_info = { 661 .setup = ehl_sgmii_data, 662 }; 663 664 static int ehl_rgmii_data(struct pci_dev *pdev, 665 struct plat_stmmacenet_data *plat) 666 { 667 plat->bus_id = 1; 668 plat->phy_interface = PHY_INTERFACE_MODE_RGMII; 669 670 plat->clk_ptp_rate = 204800000; 671 672 return ehl_common_data(pdev, plat); 673 } 674 675 static struct stmmac_pci_info ehl_rgmii1g_info = { 676 .setup = ehl_rgmii_data, 677 }; 678 679 static int ehl_pse0_common_data(struct pci_dev *pdev, 680 struct plat_stmmacenet_data *plat) 681 { 682 struct intel_priv_data *intel_priv = plat->bsp_priv; 683 684 intel_priv->is_pse = true; 685 plat->bus_id = 2; 686 plat->host_dma_width = 32; 687 688 plat->clk_ptp_rate = 200000000; 689 690 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ); 691 692 return ehl_common_data(pdev, plat); 693 } 694 695 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev, 696 struct plat_stmmacenet_data *plat) 697 { 698 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 699 return ehl_pse0_common_data(pdev, plat); 700 } 701 702 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = { 703 .setup = ehl_pse0_rgmii1g_data, 704 }; 705 706 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, 707 struct plat_stmmacenet_data *plat) 708 { 709 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 710 plat->speed_mode_2500 = intel_speed_mode_2500; 711 plat->serdes_powerup = intel_serdes_powerup; 712 plat->serdes_powerdown = intel_serdes_powerdown; 713 return ehl_pse0_common_data(pdev, plat); 714 } 715 716 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = { 717 .setup = ehl_pse0_sgmii1g_data, 718 }; 719 720 static int ehl_pse1_common_data(struct pci_dev *pdev, 721 struct plat_stmmacenet_data *plat) 722 { 723 struct intel_priv_data *intel_priv = plat->bsp_priv; 724 725 intel_priv->is_pse = true; 726 plat->bus_id = 3; 727 plat->host_dma_width = 32; 728 729 plat->clk_ptp_rate = 200000000; 730 731 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ); 732 733 return ehl_common_data(pdev, plat); 734 } 735 736 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev, 737 struct plat_stmmacenet_data *plat) 738 { 739 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 740 return ehl_pse1_common_data(pdev, plat); 741 } 742 743 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = { 744 .setup = ehl_pse1_rgmii1g_data, 745 }; 746 747 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, 748 struct plat_stmmacenet_data *plat) 749 { 750 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 751 plat->speed_mode_2500 = intel_speed_mode_2500; 752 plat->serdes_powerup = intel_serdes_powerup; 753 plat->serdes_powerdown = intel_serdes_powerdown; 754 return ehl_pse1_common_data(pdev, plat); 755 } 756 757 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = { 758 .setup = ehl_pse1_sgmii1g_data, 759 }; 760 761 static int tgl_common_data(struct pci_dev *pdev, 762 struct plat_stmmacenet_data *plat) 763 { 764 plat->rx_queues_to_use = 6; 765 plat->tx_queues_to_use = 4; 766 plat->clk_ptp_rate = 204800000; 767 plat->speed_mode_2500 = intel_speed_mode_2500; 768 769 plat->safety_feat_cfg->tsoee = 1; 770 plat->safety_feat_cfg->mrxpee = 0; 771 plat->safety_feat_cfg->mestee = 1; 772 plat->safety_feat_cfg->mrxee = 1; 773 plat->safety_feat_cfg->mtxee = 1; 774 plat->safety_feat_cfg->epsi = 0; 775 plat->safety_feat_cfg->edpp = 0; 776 plat->safety_feat_cfg->prtyen = 0; 777 plat->safety_feat_cfg->tmouten = 0; 778 779 return intel_mgbe_common_data(pdev, plat); 780 } 781 782 static int tgl_sgmii_phy0_data(struct pci_dev *pdev, 783 struct plat_stmmacenet_data *plat) 784 { 785 plat->bus_id = 1; 786 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 787 plat->serdes_powerup = intel_serdes_powerup; 788 plat->serdes_powerdown = intel_serdes_powerdown; 789 return tgl_common_data(pdev, plat); 790 } 791 792 static struct stmmac_pci_info tgl_sgmii1g_phy0_info = { 793 .setup = tgl_sgmii_phy0_data, 794 }; 795 796 static int tgl_sgmii_phy1_data(struct pci_dev *pdev, 797 struct plat_stmmacenet_data *plat) 798 { 799 plat->bus_id = 2; 800 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 801 plat->serdes_powerup = intel_serdes_powerup; 802 plat->serdes_powerdown = intel_serdes_powerdown; 803 return tgl_common_data(pdev, plat); 804 } 805 806 static struct stmmac_pci_info tgl_sgmii1g_phy1_info = { 807 .setup = tgl_sgmii_phy1_data, 808 }; 809 810 static int adls_sgmii_phy0_data(struct pci_dev *pdev, 811 struct plat_stmmacenet_data *plat) 812 { 813 plat->bus_id = 1; 814 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 815 816 /* SerDes power up and power down are done in BIOS for ADL */ 817 818 return tgl_common_data(pdev, plat); 819 } 820 821 static struct stmmac_pci_info adls_sgmii1g_phy0_info = { 822 .setup = adls_sgmii_phy0_data, 823 }; 824 825 static int adls_sgmii_phy1_data(struct pci_dev *pdev, 826 struct plat_stmmacenet_data *plat) 827 { 828 plat->bus_id = 2; 829 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 830 831 /* SerDes power up and power down are done in BIOS for ADL */ 832 833 return tgl_common_data(pdev, plat); 834 } 835 836 static struct stmmac_pci_info adls_sgmii1g_phy1_info = { 837 .setup = adls_sgmii_phy1_data, 838 }; 839 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { 840 { 841 .func = 6, 842 .phy_addr = 1, 843 }, 844 }; 845 846 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = { 847 .func = galileo_stmmac_func_data, 848 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data), 849 }; 850 851 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = { 852 { 853 .func = 6, 854 .phy_addr = 1, 855 }, 856 { 857 .func = 7, 858 .phy_addr = 1, 859 }, 860 }; 861 862 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = { 863 .func = iot2040_stmmac_func_data, 864 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data), 865 }; 866 867 static const struct dmi_system_id quark_pci_dmi[] = { 868 { 869 .matches = { 870 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 871 }, 872 .driver_data = (void *)&galileo_stmmac_dmi_data, 873 }, 874 { 875 .matches = { 876 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 877 }, 878 .driver_data = (void *)&galileo_stmmac_dmi_data, 879 }, 880 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040. 881 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which 882 * has only one pci network device while other asset tags are 883 * for IOT2040 which has two. 884 */ 885 { 886 .matches = { 887 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 888 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG, 889 "6ES7647-0AA00-0YA2"), 890 }, 891 .driver_data = (void *)&galileo_stmmac_dmi_data, 892 }, 893 { 894 .matches = { 895 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 896 }, 897 .driver_data = (void *)&iot2040_stmmac_dmi_data, 898 }, 899 {} 900 }; 901 902 static int quark_default_data(struct pci_dev *pdev, 903 struct plat_stmmacenet_data *plat) 904 { 905 int ret; 906 907 /* Set common default data first */ 908 common_default_data(plat); 909 910 /* Refuse to load the driver and register net device if MAC controller 911 * does not connect to any PHY interface. 912 */ 913 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi); 914 if (ret < 0) { 915 /* Return error to the caller on DMI enabled boards. */ 916 if (dmi_get_system_info(DMI_BOARD_NAME)) 917 return ret; 918 919 /* Galileo boards with old firmware don't support DMI. We always 920 * use 1 here as PHY address, so at least the first found MAC 921 * controller would be probed. 922 */ 923 ret = 1; 924 } 925 926 plat->bus_id = pci_dev_id(pdev); 927 plat->phy_addr = ret; 928 plat->phy_interface = PHY_INTERFACE_MODE_RMII; 929 930 plat->dma_cfg->pbl = 16; 931 plat->dma_cfg->pblx8 = true; 932 plat->dma_cfg->fixed_burst = 1; 933 /* AXI (TODO) */ 934 935 return 0; 936 } 937 938 static const struct stmmac_pci_info quark_info = { 939 .setup = quark_default_data, 940 }; 941 942 static int stmmac_config_single_msi(struct pci_dev *pdev, 943 struct plat_stmmacenet_data *plat, 944 struct stmmac_resources *res) 945 { 946 int ret; 947 948 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 949 if (ret < 0) { 950 dev_info(&pdev->dev, "%s: Single IRQ enablement failed\n", 951 __func__); 952 return ret; 953 } 954 955 res->irq = pci_irq_vector(pdev, 0); 956 res->wol_irq = res->irq; 957 plat->multi_msi_en = 0; 958 dev_info(&pdev->dev, "%s: Single IRQ enablement successful\n", 959 __func__); 960 961 return 0; 962 } 963 964 static int stmmac_config_multi_msi(struct pci_dev *pdev, 965 struct plat_stmmacenet_data *plat, 966 struct stmmac_resources *res) 967 { 968 int ret; 969 int i; 970 971 if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX || 972 plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) { 973 dev_info(&pdev->dev, "%s: Invalid RX & TX vector defined\n", 974 __func__); 975 return -1; 976 } 977 978 ret = pci_alloc_irq_vectors(pdev, 2, STMMAC_MSI_VEC_MAX, 979 PCI_IRQ_MSI | PCI_IRQ_MSIX); 980 if (ret < 0) { 981 dev_info(&pdev->dev, "%s: multi MSI enablement failed\n", 982 __func__); 983 return ret; 984 } 985 986 /* For RX MSI */ 987 for (i = 0; i < plat->rx_queues_to_use; i++) { 988 res->rx_irq[i] = pci_irq_vector(pdev, 989 plat->msi_rx_base_vec + i * 2); 990 } 991 992 /* For TX MSI */ 993 for (i = 0; i < plat->tx_queues_to_use; i++) { 994 res->tx_irq[i] = pci_irq_vector(pdev, 995 plat->msi_tx_base_vec + i * 2); 996 } 997 998 if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX) 999 res->irq = pci_irq_vector(pdev, plat->msi_mac_vec); 1000 if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX) 1001 res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec); 1002 if (plat->msi_lpi_vec < STMMAC_MSI_VEC_MAX) 1003 res->lpi_irq = pci_irq_vector(pdev, plat->msi_lpi_vec); 1004 if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX) 1005 res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec); 1006 if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX) 1007 res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec); 1008 1009 plat->multi_msi_en = 1; 1010 dev_info(&pdev->dev, "%s: multi MSI enablement successful\n", __func__); 1011 1012 return 0; 1013 } 1014 1015 /** 1016 * intel_eth_pci_probe 1017 * 1018 * @pdev: pci device pointer 1019 * @id: pointer to table of device id/id's. 1020 * 1021 * Description: This probing function gets called for all PCI devices which 1022 * match the ID table and are not "owned" by other driver yet. This function 1023 * gets passed a "struct pci_dev *" for each device whose entry in the ID table 1024 * matches the device. The probe functions returns zero when the driver choose 1025 * to take "ownership" of the device or an error code(-ve no) otherwise. 1026 */ 1027 static int intel_eth_pci_probe(struct pci_dev *pdev, 1028 const struct pci_device_id *id) 1029 { 1030 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; 1031 struct intel_priv_data *intel_priv; 1032 struct plat_stmmacenet_data *plat; 1033 struct stmmac_resources res; 1034 int ret; 1035 1036 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL); 1037 if (!intel_priv) 1038 return -ENOMEM; 1039 1040 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 1041 if (!plat) 1042 return -ENOMEM; 1043 1044 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, 1045 sizeof(*plat->mdio_bus_data), 1046 GFP_KERNEL); 1047 if (!plat->mdio_bus_data) 1048 return -ENOMEM; 1049 1050 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), 1051 GFP_KERNEL); 1052 if (!plat->dma_cfg) 1053 return -ENOMEM; 1054 1055 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev, 1056 sizeof(*plat->safety_feat_cfg), 1057 GFP_KERNEL); 1058 if (!plat->safety_feat_cfg) 1059 return -ENOMEM; 1060 1061 /* Enable pci device */ 1062 ret = pcim_enable_device(pdev); 1063 if (ret) { 1064 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", 1065 __func__); 1066 return ret; 1067 } 1068 1069 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 1070 if (ret) 1071 return ret; 1072 1073 pci_set_master(pdev); 1074 1075 plat->bsp_priv = intel_priv; 1076 intel_priv->mdio_adhoc_addr = INTEL_MGBE_ADHOC_ADDR; 1077 intel_priv->crossts_adj = 1; 1078 1079 /* Initialize all MSI vectors to invalid so that it can be set 1080 * according to platform data settings below. 1081 * Note: MSI vector takes value from 0 upto 31 (STMMAC_MSI_VEC_MAX) 1082 */ 1083 plat->msi_mac_vec = STMMAC_MSI_VEC_MAX; 1084 plat->msi_wol_vec = STMMAC_MSI_VEC_MAX; 1085 plat->msi_lpi_vec = STMMAC_MSI_VEC_MAX; 1086 plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX; 1087 plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX; 1088 plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX; 1089 plat->msi_tx_base_vec = STMMAC_MSI_VEC_MAX; 1090 1091 ret = info->setup(pdev, plat); 1092 if (ret) 1093 return ret; 1094 1095 memset(&res, 0, sizeof(res)); 1096 res.addr = pcim_iomap_table(pdev)[0]; 1097 1098 if (plat->eee_usecs_rate > 0) { 1099 u32 tx_lpi_usec; 1100 1101 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1; 1102 writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER); 1103 } 1104 1105 ret = stmmac_config_multi_msi(pdev, plat, &res); 1106 if (ret) { 1107 ret = stmmac_config_single_msi(pdev, plat, &res); 1108 if (ret) { 1109 dev_err(&pdev->dev, "%s: ERROR: failed to enable IRQ\n", 1110 __func__); 1111 goto err_alloc_irq; 1112 } 1113 } 1114 1115 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); 1116 if (ret) { 1117 goto err_alloc_irq; 1118 } 1119 1120 return 0; 1121 1122 err_alloc_irq: 1123 clk_disable_unprepare(plat->stmmac_clk); 1124 clk_unregister_fixed_rate(plat->stmmac_clk); 1125 return ret; 1126 } 1127 1128 /** 1129 * intel_eth_pci_remove 1130 * 1131 * @pdev: pci device pointer 1132 * Description: this function calls the main to free the net resources 1133 * and releases the PCI resources. 1134 */ 1135 static void intel_eth_pci_remove(struct pci_dev *pdev) 1136 { 1137 struct net_device *ndev = dev_get_drvdata(&pdev->dev); 1138 struct stmmac_priv *priv = netdev_priv(ndev); 1139 1140 stmmac_dvr_remove(&pdev->dev); 1141 1142 clk_disable_unprepare(priv->plat->stmmac_clk); 1143 clk_unregister_fixed_rate(priv->plat->stmmac_clk); 1144 } 1145 1146 static int __maybe_unused intel_eth_pci_suspend(struct device *dev) 1147 { 1148 struct pci_dev *pdev = to_pci_dev(dev); 1149 int ret; 1150 1151 ret = stmmac_suspend(dev); 1152 if (ret) 1153 return ret; 1154 1155 ret = pci_save_state(pdev); 1156 if (ret) 1157 return ret; 1158 1159 pci_wake_from_d3(pdev, true); 1160 pci_set_power_state(pdev, PCI_D3hot); 1161 return 0; 1162 } 1163 1164 static int __maybe_unused intel_eth_pci_resume(struct device *dev) 1165 { 1166 struct pci_dev *pdev = to_pci_dev(dev); 1167 int ret; 1168 1169 pci_restore_state(pdev); 1170 pci_set_power_state(pdev, PCI_D0); 1171 1172 ret = pcim_enable_device(pdev); 1173 if (ret) 1174 return ret; 1175 1176 pci_set_master(pdev); 1177 1178 return stmmac_resume(dev); 1179 } 1180 1181 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend, 1182 intel_eth_pci_resume); 1183 1184 #define PCI_DEVICE_ID_INTEL_QUARK 0x0937 1185 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G 0x4b30 1186 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G 0x4b31 1187 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32 1188 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC 1189 * which are named PSE0 and PSE1 1190 */ 1191 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0 1192 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1 1193 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 0x4ba2 1194 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0 1195 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1 1196 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 0x4bb2 1197 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0 0x43ac 1198 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1 0x43a2 1199 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G 0xa0ac 1200 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0 0x7aac 1201 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1 0x7aad 1202 #define PCI_DEVICE_ID_INTEL_ADLN_SGMII1G 0x54ac 1203 #define PCI_DEVICE_ID_INTEL_RPLP_SGMII1G 0x51ac 1204 1205 static const struct pci_device_id intel_eth_pci_id_table[] = { 1206 { PCI_DEVICE_DATA(INTEL, QUARK, &quark_info) }, 1207 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G, &ehl_rgmii1g_info) }, 1208 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G, &ehl_sgmii1g_info) }, 1209 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5, &ehl_sgmii1g_info) }, 1210 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G, &ehl_pse0_rgmii1g_info) }, 1211 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G, &ehl_pse0_sgmii1g_info) }, 1212 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5, &ehl_pse0_sgmii1g_info) }, 1213 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G, &ehl_pse1_rgmii1g_info) }, 1214 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G, &ehl_pse1_sgmii1g_info) }, 1215 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5, &ehl_pse1_sgmii1g_info) }, 1216 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G, &tgl_sgmii1g_phy0_info) }, 1217 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0, &tgl_sgmii1g_phy0_info) }, 1218 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) }, 1219 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) }, 1220 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) }, 1221 { PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &tgl_sgmii1g_phy0_info) }, 1222 { PCI_DEVICE_DATA(INTEL, RPLP_SGMII1G, &tgl_sgmii1g_phy0_info) }, 1223 {} 1224 }; 1225 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table); 1226 1227 static struct pci_driver intel_eth_pci_driver = { 1228 .name = "intel-eth-pci", 1229 .id_table = intel_eth_pci_id_table, 1230 .probe = intel_eth_pci_probe, 1231 .remove = intel_eth_pci_remove, 1232 .driver = { 1233 .pm = &intel_eth_pm_ops, 1234 }, 1235 }; 1236 1237 module_pci_driver(intel_eth_pci_driver); 1238 1239 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver"); 1240 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>"); 1241 MODULE_LICENSE("GPL v2"); 1242