1 /*******************************************************************************
2   Header File to describe the DMA descriptors and related definitions.
3   This is for DWMAC100 and 1000 cores.
4 
5   This program is free software; you can redistribute it and/or modify it
6   under the terms and conditions of the GNU General Public License,
7   version 2, as published by the Free Software Foundation.
8 
9   This program is distributed in the hope it will be useful, but WITHOUT
10   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12   more details.
13 
14   You should have received a copy of the GNU General Public License along with
15   this program; if not, write to the Free Software Foundation, Inc.,
16   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 
18   The full GNU General Public License is included in this distribution in
19   the file called "COPYING".
20 
21   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
22 *******************************************************************************/
23 
24 #ifndef __DESCS_H__
25 #define __DESCS_H__
26 
27 #include <linux/bitops.h>
28 
29 /* Normal receive descriptor defines */
30 
31 /* RDES0 */
32 #define	RDES0_PAYLOAD_CSUM_ERR	BIT(0)
33 #define	RDES0_CRC_ERROR		BIT(1)
34 #define	RDES0_DRIBBLING		BIT(2)
35 #define	RDES0_MII_ERROR		BIT(3)
36 #define	RDES0_RECEIVE_WATCHDOG	BIT(4)
37 #define	RDES0_FRAME_TYPE	BIT(5)
38 #define	RDES0_COLLISION		BIT(6)
39 #define	RDES0_IPC_CSUM_ERROR	BIT(7)
40 #define	RDES0_LAST_DESCRIPTOR	BIT(8)
41 #define	RDES0_FIRST_DESCRIPTOR	BIT(9)
42 #define	RDES0_VLAN_TAG		BIT(10)
43 #define	RDES0_OVERFLOW_ERROR	BIT(11)
44 #define	RDES0_LENGTH_ERROR	BIT(12)
45 #define	RDES0_SA_FILTER_FAIL	BIT(13)
46 #define	RDES0_DESCRIPTOR_ERROR	BIT(14)
47 #define	RDES0_ERROR_SUMMARY	BIT(15)
48 #define	RDES0_FRAME_LEN_MASK	GENMASK(29, 16)
49 #define RDES0_FRAME_LEN_SHIFT	16
50 #define	RDES0_DA_FILTER_FAIL	BIT(30)
51 #define	RDES0_OWN		BIT(31)
52 			/* RDES1 */
53 #define	RDES1_BUFFER1_SIZE_MASK		GENMASK(10, 0)
54 #define	RDES1_BUFFER2_SIZE_MASK		GENMASK(21, 11)
55 #define	RDES1_BUFFER2_SIZE_SHIFT	11
56 #define	RDES1_SECOND_ADDRESS_CHAINED	BIT(24)
57 #define	RDES1_END_RING			BIT(25)
58 #define	RDES1_DISABLE_IC		BIT(31)
59 
60 /* Enhanced receive descriptor defines */
61 
62 /* RDES0 (similar to normal RDES) */
63 #define	 ERDES0_RX_MAC_ADDR	BIT(0)
64 
65 /* RDES1: completely differ from normal desc definitions */
66 #define	ERDES1_BUFFER1_SIZE_MASK	GENMASK(12, 0)
67 #define	ERDES1_SECOND_ADDRESS_CHAINED	BIT(14)
68 #define	ERDES1_END_RING			BIT(15)
69 #define	ERDES1_BUFFER2_SIZE_MASK	GENMASK(28, 16)
70 #define ERDES1_BUFFER2_SIZE_SHIFT	16
71 #define	ERDES1_DISABLE_IC		BIT(31)
72 
73 /* Normal transmit descriptor defines */
74 /* TDES0 */
75 #define	TDES0_DEFERRED			BIT(0)
76 #define	TDES0_UNDERFLOW_ERROR		BIT(1)
77 #define	TDES0_EXCESSIVE_DEFERRAL	BIT(2)
78 #define	TDES0_COLLISION_COUNT_MASK	GENMASK(6, 3)
79 #define	TDES0_VLAN_FRAME		BIT(7)
80 #define	TDES0_EXCESSIVE_COLLISIONS	BIT(8)
81 #define	TDES0_LATE_COLLISION		BIT(9)
82 #define	TDES0_NO_CARRIER		BIT(10)
83 #define	TDES0_LOSS_CARRIER		BIT(11)
84 #define	TDES0_PAYLOAD_ERROR		BIT(12)
85 #define	TDES0_FRAME_FLUSHED		BIT(13)
86 #define	TDES0_JABBER_TIMEOUT		BIT(14)
87 #define	TDES0_ERROR_SUMMARY		BIT(15)
88 #define	TDES0_IP_HEADER_ERROR		BIT(16)
89 #define	TDES0_TIME_STAMP_STATUS		BIT(17)
90 #define	TDES0_OWN			BIT(31)
91 /* TDES1 */
92 #define	TDES1_BUFFER1_SIZE_MASK		GENMASK(10, 0)
93 #define	TDES1_BUFFER2_SIZE_MASK		GENMASK(21, 11)
94 #define	TDES1_BUFFER2_SIZE_SHIFT	11
95 #define	TDES1_TIME_STAMP_ENABLE		BIT(22)
96 #define	TDES1_DISABLE_PADDING		BIT(23)
97 #define	TDES1_SECOND_ADDRESS_CHAINED	BIT(24)
98 #define	TDES1_END_RING			BIT(25)
99 #define	TDES1_CRC_DISABLE		BIT(26)
100 #define	TDES1_CHECKSUM_INSERTION_MASK	GENMASK(28, 27)
101 #define	TDES1_CHECKSUM_INSERTION_SHIFT	27
102 #define	TDES1_FIRST_SEGMENT		BIT(29)
103 #define	TDES1_LAST_SEGMENT		BIT(30)
104 #define	TDES1_INTERRUPT			BIT(31)
105 
106 /* Enhanced transmit descriptor defines */
107 /* TDES0 */
108 #define	ETDES0_DEFERRED			BIT(0)
109 #define	ETDES0_UNDERFLOW_ERROR		BIT(1)
110 #define	ETDES0_EXCESSIVE_DEFERRAL	BIT(2)
111 #define	ETDES0_COLLISION_COUNT_MASK	GENMASK(6, 3)
112 #define	ETDES0_VLAN_FRAME		BIT(7)
113 #define	ETDES0_EXCESSIVE_COLLISIONS	BIT(8)
114 #define	ETDES0_LATE_COLLISION		BIT(9)
115 #define	ETDES0_NO_CARRIER		BIT(10)
116 #define	ETDES0_LOSS_CARRIER		BIT(11)
117 #define	ETDES0_PAYLOAD_ERROR		BIT(12)
118 #define	ETDES0_FRAME_FLUSHED		BIT(13)
119 #define	ETDES0_JABBER_TIMEOUT		BIT(14)
120 #define	ETDES0_ERROR_SUMMARY		BIT(15)
121 #define	ETDES0_IP_HEADER_ERROR		BIT(16)
122 #define	ETDES0_TIME_STAMP_STATUS	BIT(17)
123 #define	ETDES0_SECOND_ADDRESS_CHAINED	BIT(20)
124 #define	ETDES0_END_RING			BIT(21)
125 #define	ETDES0_CHECKSUM_INSERTION_MASK	GENMASK(23, 22)
126 #define	ETDES0_CHECKSUM_INSERTION_SHIFT	22
127 #define	ETDES0_TIME_STAMP_ENABLE	BIT(25)
128 #define	ETDES0_DISABLE_PADDING		BIT(26)
129 #define	ETDES0_CRC_DISABLE		BIT(27)
130 #define	ETDES0_FIRST_SEGMENT		BIT(28)
131 #define	ETDES0_LAST_SEGMENT		BIT(29)
132 #define	ETDES0_INTERRUPT		BIT(30)
133 #define	ETDES0_OWN			BIT(31)
134 /* TDES1 */
135 #define	ETDES1_BUFFER1_SIZE_MASK	GENMASK(12, 0)
136 #define	ETDES1_BUFFER2_SIZE_MASK	GENMASK(28, 16)
137 #define	ETDES1_BUFFER2_SIZE_SHIFT	16
138 
139 /* Extended Receive descriptor definitions */
140 #define	ERDES4_IP_PAYLOAD_TYPE_MASK	GENMASK(2, 6)
141 #define	ERDES4_IP_HDR_ERR		BIT(3)
142 #define	ERDES4_IP_PAYLOAD_ERR		BIT(4)
143 #define	ERDES4_IP_CSUM_BYPASSED		BIT(5)
144 #define	ERDES4_IPV4_PKT_RCVD		BIT(6)
145 #define	ERDES4_IPV6_PKT_RCVD		BIT(7)
146 #define	ERDES4_MSG_TYPE_MASK		GENMASK(11, 8)
147 #define	ERDES4_PTP_FRAME_TYPE		BIT(12)
148 #define	ERDES4_PTP_VER			BIT(13)
149 #define	ERDES4_TIMESTAMP_DROPPED	BIT(14)
150 #define	ERDES4_AV_PKT_RCVD		BIT(16)
151 #define	ERDES4_AV_TAGGED_PKT_RCVD	BIT(17)
152 #define	ERDES4_VLAN_TAG_PRI_VAL_MASK	GENMASK(20, 18)
153 #define	ERDES4_L3_FILTER_MATCH		BIT(24)
154 #define	ERDES4_L4_FILTER_MATCH		BIT(25)
155 #define	ERDES4_L3_L4_FILT_NO_MATCH_MASK	GENMASK(27, 26)
156 
157 /* Extended RDES4 message type definitions */
158 #define RDES_EXT_NO_PTP			0
159 #define RDES_EXT_SYNC			1
160 #define RDES_EXT_FOLLOW_UP		2
161 #define RDES_EXT_DELAY_REQ		3
162 #define RDES_EXT_DELAY_RESP		4
163 #define RDES_EXT_PDELAY_REQ		5
164 #define RDES_EXT_PDELAY_RESP		6
165 #define RDES_EXT_PDELAY_FOLLOW_UP	7
166 
167 /* Basic descriptor structure for normal and alternate descriptors */
168 struct dma_desc {
169 	unsigned int des0;
170 	unsigned int des1;
171 	unsigned int des2;
172 	unsigned int des3;
173 };
174 
175 /* Extended descriptor structure (e.g. >= databook 3.50a) */
176 struct dma_extended_desc {
177 	struct dma_desc basic;	/* Basic descriptors */
178 	unsigned int des4;	/* Extended Status */
179 	unsigned int des5;	/* Reserved */
180 	unsigned int des6;	/* Tx/Rx Timestamp Low */
181 	unsigned int des7;	/* Tx/Rx Timestamp High */
182 };
183 
184 /* Transmit checksum insertion control */
185 #define	TX_CIC_FULL	3	/* Include IP header and pseudoheader */
186 
187 #endif /* __DESCS_H__ */
188