1 /******************************************************************************* 2 STMMAC Common Header File 3 4 Copyright (C) 2007-2009 STMicroelectronics Ltd 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 23 *******************************************************************************/ 24 25 #ifndef __COMMON_H__ 26 #define __COMMON_H__ 27 28 #include <linux/etherdevice.h> 29 #include <linux/netdevice.h> 30 #include <linux/phy.h> 31 #include <linux/module.h> 32 #include <linux/init.h> 33 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) 34 #define STMMAC_VLAN_TAG_USED 35 #include <linux/if_vlan.h> 36 #endif 37 38 #include "descs.h" 39 #include "mmc.h" 40 41 /* Synopsys Core versions */ 42 #define DWMAC_CORE_3_40 0x34 43 #define DWMAC_CORE_3_50 0x35 44 45 #undef FRAME_FILTER_DEBUG 46 /* #define FRAME_FILTER_DEBUG */ 47 48 struct stmmac_extra_stats { 49 /* Transmit errors */ 50 unsigned long tx_underflow ____cacheline_aligned; 51 unsigned long tx_carrier; 52 unsigned long tx_losscarrier; 53 unsigned long vlan_tag; 54 unsigned long tx_deferred; 55 unsigned long tx_vlan; 56 unsigned long tx_jabber; 57 unsigned long tx_frame_flushed; 58 unsigned long tx_payload_error; 59 unsigned long tx_ip_header_error; 60 /* Receive errors */ 61 unsigned long rx_desc; 62 unsigned long sa_filter_fail; 63 unsigned long overflow_error; 64 unsigned long ipc_csum_error; 65 unsigned long rx_collision; 66 unsigned long rx_crc; 67 unsigned long dribbling_bit; 68 unsigned long rx_length; 69 unsigned long rx_mii; 70 unsigned long rx_multicast; 71 unsigned long rx_gmac_overflow; 72 unsigned long rx_watchdog; 73 unsigned long da_rx_filter_fail; 74 unsigned long sa_rx_filter_fail; 75 unsigned long rx_missed_cntr; 76 unsigned long rx_overflow_cntr; 77 unsigned long rx_vlan; 78 /* Tx/Rx IRQ error info */ 79 unsigned long tx_undeflow_irq; 80 unsigned long tx_process_stopped_irq; 81 unsigned long tx_jabber_irq; 82 unsigned long rx_overflow_irq; 83 unsigned long rx_buf_unav_irq; 84 unsigned long rx_process_stopped_irq; 85 unsigned long rx_watchdog_irq; 86 unsigned long tx_early_irq; 87 unsigned long fatal_bus_error_irq; 88 /* Tx/Rx IRQ Events */ 89 unsigned long rx_early_irq; 90 unsigned long threshold; 91 unsigned long tx_pkt_n; 92 unsigned long rx_pkt_n; 93 unsigned long normal_irq_n; 94 unsigned long rx_normal_irq_n; 95 unsigned long napi_poll; 96 unsigned long tx_normal_irq_n; 97 unsigned long tx_clean; 98 unsigned long tx_reset_ic_bit; 99 unsigned long irq_receive_pmt_irq_n; 100 /* MMC info */ 101 unsigned long mmc_tx_irq_n; 102 unsigned long mmc_rx_irq_n; 103 unsigned long mmc_rx_csum_offload_irq_n; 104 /* EEE */ 105 unsigned long irq_tx_path_in_lpi_mode_n; 106 unsigned long irq_tx_path_exit_lpi_mode_n; 107 unsigned long irq_rx_path_in_lpi_mode_n; 108 unsigned long irq_rx_path_exit_lpi_mode_n; 109 unsigned long phy_eee_wakeup_error_n; 110 /* Extended RDES status */ 111 unsigned long ip_hdr_err; 112 unsigned long ip_payload_err; 113 unsigned long ip_csum_bypassed; 114 unsigned long ipv4_pkt_rcvd; 115 unsigned long ipv6_pkt_rcvd; 116 unsigned long rx_msg_type_ext_no_ptp; 117 unsigned long rx_msg_type_sync; 118 unsigned long rx_msg_type_follow_up; 119 unsigned long rx_msg_type_delay_req; 120 unsigned long rx_msg_type_delay_resp; 121 unsigned long rx_msg_type_pdelay_req; 122 unsigned long rx_msg_type_pdelay_resp; 123 unsigned long rx_msg_type_pdelay_follow_up; 124 unsigned long ptp_frame_type; 125 unsigned long ptp_ver; 126 unsigned long timestamp_dropped; 127 unsigned long av_pkt_rcvd; 128 unsigned long av_tagged_pkt_rcvd; 129 unsigned long vlan_tag_priority_val; 130 unsigned long l3_filter_match; 131 unsigned long l4_filter_match; 132 unsigned long l3_l4_filter_no_match; 133 /* PCS */ 134 unsigned long irq_pcs_ane_n; 135 unsigned long irq_pcs_link_n; 136 unsigned long irq_rgmii_n; 137 unsigned long pcs_link; 138 unsigned long pcs_duplex; 139 unsigned long pcs_speed; 140 }; 141 142 /* CSR Frequency Access Defines*/ 143 #define CSR_F_35M 35000000 144 #define CSR_F_60M 60000000 145 #define CSR_F_100M 100000000 146 #define CSR_F_150M 150000000 147 #define CSR_F_250M 250000000 148 #define CSR_F_300M 300000000 149 150 #define MAC_CSR_H_FRQ_MASK 0x20 151 152 #define HASH_TABLE_SIZE 64 153 #define PAUSE_TIME 0x200 154 155 /* Flow Control defines */ 156 #define FLOW_OFF 0 157 #define FLOW_RX 1 158 #define FLOW_TX 2 159 #define FLOW_AUTO (FLOW_TX | FLOW_RX) 160 161 /* PCS defines */ 162 #define STMMAC_PCS_RGMII (1 << 0) 163 #define STMMAC_PCS_SGMII (1 << 1) 164 #define STMMAC_PCS_TBI (1 << 2) 165 #define STMMAC_PCS_RTBI (1 << 3) 166 167 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */ 168 169 /* DAM HW feature register fields */ 170 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */ 171 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */ 172 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */ 173 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */ 174 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */ 175 #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */ 176 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */ 177 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */ 178 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */ 179 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */ 180 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */ 181 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */ 182 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */ 183 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */ 184 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */ 185 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */ 186 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */ 187 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */ 188 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */ 189 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */ 190 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */ 191 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */ 192 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */ 193 /* Timestamping with Internal System Time */ 194 #define DMA_HW_FEAT_INTTSEN 0x02000000 195 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */ 196 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */ 197 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */ 198 #define DEFAULT_DMA_PBL 8 199 200 /* Max/Min RI Watchdog Timer count value */ 201 #define MAX_DMA_RIWT 0xff 202 #define MIN_DMA_RIWT 0x20 203 /* Tx coalesce parameters */ 204 #define STMMAC_COAL_TX_TIMER 40000 205 #define STMMAC_MAX_COAL_TX_TICK 100000 206 #define STMMAC_TX_MAX_FRAMES 256 207 #define STMMAC_TX_FRAMES 64 208 209 /* Rx IPC status */ 210 enum rx_frame_status { 211 good_frame = 0, 212 discard_frame = 1, 213 csum_none = 2, 214 llc_snap = 4, 215 }; 216 217 enum dma_irq_status { 218 tx_hard_error = 0x1, 219 tx_hard_error_bump_tc = 0x2, 220 handle_rx = 0x4, 221 handle_tx = 0x8, 222 }; 223 224 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 1) 225 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 2) 226 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 3) 227 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 4) 228 229 #define CORE_PCS_ANE_COMPLETE (1 << 5) 230 #define CORE_PCS_LINK_STATUS (1 << 6) 231 #define CORE_RGMII_IRQ (1 << 7) 232 233 struct rgmii_adv { 234 unsigned int pause; 235 unsigned int duplex; 236 unsigned int lp_pause; 237 unsigned int lp_duplex; 238 }; 239 240 #define STMMAC_PCS_PAUSE 1 241 #define STMMAC_PCS_ASYM_PAUSE 2 242 243 /* DMA HW capabilities */ 244 struct dma_features { 245 unsigned int mbps_10_100; 246 unsigned int mbps_1000; 247 unsigned int half_duplex; 248 unsigned int hash_filter; 249 unsigned int multi_addr; 250 unsigned int pcs; 251 unsigned int sma_mdio; 252 unsigned int pmt_remote_wake_up; 253 unsigned int pmt_magic_frame; 254 unsigned int rmon; 255 /* IEEE 1588-2002 */ 256 unsigned int time_stamp; 257 /* IEEE 1588-2008 */ 258 unsigned int atime_stamp; 259 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 260 unsigned int eee; 261 unsigned int av; 262 /* TX and RX csum */ 263 unsigned int tx_coe; 264 unsigned int rx_coe_type1; 265 unsigned int rx_coe_type2; 266 unsigned int rxfifo_over_2048; 267 /* TX and RX number of channels */ 268 unsigned int number_rx_channel; 269 unsigned int number_tx_channel; 270 /* Alternate (enhanced) DESC mode */ 271 unsigned int enh_desc; 272 }; 273 274 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */ 275 #define BUF_SIZE_16KiB 16384 276 #define BUF_SIZE_8KiB 8192 277 #define BUF_SIZE_4KiB 4096 278 #define BUF_SIZE_2KiB 2048 279 280 /* Power Down and WOL */ 281 #define PMT_NOT_SUPPORTED 0 282 #define PMT_SUPPORTED 1 283 284 /* Common MAC defines */ 285 #define MAC_CTRL_REG 0x00000000 /* MAC Control */ 286 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ 287 #define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */ 288 289 /* Default LPI timers */ 290 #define STMMAC_DEFAULT_LIT_LS 0x3E8 291 #define STMMAC_DEFAULT_TWT_LS 0x0 292 293 #define STMMAC_CHAIN_MODE 0x1 294 #define STMMAC_RING_MODE 0x2 295 296 struct stmmac_desc_ops { 297 /* DMA RX descriptor ring initialization */ 298 void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode, 299 int end); 300 /* DMA TX descriptor ring initialization */ 301 void (*init_tx_desc) (struct dma_desc *p, int mode, int end); 302 303 /* Invoked by the xmit function to prepare the tx descriptor */ 304 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len, 305 int csum_flag, int mode); 306 /* Set/get the owner of the descriptor */ 307 void (*set_tx_owner) (struct dma_desc *p); 308 int (*get_tx_owner) (struct dma_desc *p); 309 /* Invoked by the xmit function to close the tx descriptor */ 310 void (*close_tx_desc) (struct dma_desc *p); 311 /* Clean the tx descriptor as soon as the tx irq is received */ 312 void (*release_tx_desc) (struct dma_desc *p, int mode); 313 /* Clear interrupt on tx frame completion. When this bit is 314 * set an interrupt happens as soon as the frame is transmitted */ 315 void (*clear_tx_ic) (struct dma_desc *p); 316 /* Last tx segment reports the transmit status */ 317 int (*get_tx_ls) (struct dma_desc *p); 318 /* Return the transmit status looking at the TDES1 */ 319 int (*tx_status) (void *data, struct stmmac_extra_stats *x, 320 struct dma_desc *p, void __iomem *ioaddr); 321 /* Get the buffer size from the descriptor */ 322 int (*get_tx_len) (struct dma_desc *p); 323 /* Handle extra events on specific interrupts hw dependent */ 324 int (*get_rx_owner) (struct dma_desc *p); 325 void (*set_rx_owner) (struct dma_desc *p); 326 /* Get the receive frame size */ 327 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type); 328 /* Return the reception status looking at the RDES1 */ 329 int (*rx_status) (void *data, struct stmmac_extra_stats *x, 330 struct dma_desc *p); 331 void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x, 332 struct dma_extended_desc *p); 333 /* Set tx timestamp enable bit */ 334 void (*enable_tx_timestamp) (struct dma_desc *p); 335 /* get tx timestamp status */ 336 int (*get_tx_timestamp_status) (struct dma_desc *p); 337 /* get timestamp value */ 338 u64(*get_timestamp) (void *desc, u32 ats); 339 /* get rx timestamp status */ 340 int (*get_rx_timestamp_status) (void *desc, u32 ats); 341 }; 342 343 struct stmmac_dma_ops { 344 /* DMA core initialization */ 345 int (*init) (void __iomem *ioaddr, int pbl, int fb, int mb, 346 int burst_len, u32 dma_tx, u32 dma_rx, int atds); 347 /* Dump DMA registers */ 348 void (*dump_regs) (void __iomem *ioaddr); 349 /* Set tx/rx threshold in the csr6 register 350 * An invalid value enables the store-and-forward mode */ 351 void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode); 352 /* To track extra statistic (if supported) */ 353 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x, 354 void __iomem *ioaddr); 355 void (*enable_dma_transmission) (void __iomem *ioaddr); 356 void (*enable_dma_irq) (void __iomem *ioaddr); 357 void (*disable_dma_irq) (void __iomem *ioaddr); 358 void (*start_tx) (void __iomem *ioaddr); 359 void (*stop_tx) (void __iomem *ioaddr); 360 void (*start_rx) (void __iomem *ioaddr); 361 void (*stop_rx) (void __iomem *ioaddr); 362 int (*dma_interrupt) (void __iomem *ioaddr, 363 struct stmmac_extra_stats *x); 364 /* If supported then get the optional core features */ 365 unsigned int (*get_hw_feature) (void __iomem *ioaddr); 366 /* Program the HW RX Watchdog */ 367 void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt); 368 }; 369 370 struct stmmac_ops { 371 /* MAC core initialization */ 372 void (*core_init) (void __iomem *ioaddr); 373 /* Enable and verify that the IPC module is supported */ 374 int (*rx_ipc) (void __iomem *ioaddr); 375 /* Dump MAC registers */ 376 void (*dump_regs) (void __iomem *ioaddr); 377 /* Handle extra events on specific interrupts hw dependent */ 378 int (*host_irq_status) (void __iomem *ioaddr, 379 struct stmmac_extra_stats *x); 380 /* Multicast filter setting */ 381 void (*set_filter) (struct net_device *dev, int id); 382 /* Flow control setting */ 383 void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex, 384 unsigned int fc, unsigned int pause_time); 385 /* Set power management mode (e.g. magic frame) */ 386 void (*pmt) (void __iomem *ioaddr, unsigned long mode); 387 /* Set/Get Unicast MAC addresses */ 388 void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr, 389 unsigned int reg_n); 390 void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr, 391 unsigned int reg_n); 392 void (*set_eee_mode) (void __iomem *ioaddr); 393 void (*reset_eee_mode) (void __iomem *ioaddr); 394 void (*set_eee_timer) (void __iomem *ioaddr, int ls, int tw); 395 void (*set_eee_pls) (void __iomem *ioaddr, int link); 396 void (*ctrl_ane) (void __iomem *ioaddr, bool restart); 397 void (*get_adv) (void __iomem *ioaddr, struct rgmii_adv *adv); 398 }; 399 400 struct stmmac_hwtimestamp { 401 void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data); 402 void (*config_sub_second_increment) (void __iomem *ioaddr); 403 int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec); 404 int (*config_addend) (void __iomem *ioaddr, u32 addend); 405 int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec, 406 int add_sub); 407 u64(*get_systime) (void __iomem *ioaddr); 408 }; 409 410 struct mac_link { 411 int port; 412 int duplex; 413 int speed; 414 }; 415 416 struct mii_regs { 417 unsigned int addr; /* MII Address */ 418 unsigned int data; /* MII Data */ 419 }; 420 421 struct stmmac_ring_mode_ops { 422 unsigned int (*is_jumbo_frm) (int len, int ehn_desc); 423 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum); 424 void (*refill_desc3) (void *priv, struct dma_desc *p); 425 void (*init_desc3) (struct dma_desc *p); 426 void (*clean_desc3) (void *priv, struct dma_desc *p); 427 int (*set_16kib_bfsize) (int mtu); 428 }; 429 430 struct stmmac_chain_mode_ops { 431 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size, 432 unsigned int extend_desc); 433 unsigned int (*is_jumbo_frm) (int len, int ehn_desc); 434 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum); 435 void (*refill_desc3) (void *priv, struct dma_desc *p); 436 void (*clean_desc3) (void *priv, struct dma_desc *p); 437 }; 438 439 struct mac_device_info { 440 const struct stmmac_ops *mac; 441 const struct stmmac_desc_ops *desc; 442 const struct stmmac_dma_ops *dma; 443 const struct stmmac_ring_mode_ops *ring; 444 const struct stmmac_chain_mode_ops *chain; 445 const struct stmmac_hwtimestamp *ptp; 446 struct mii_regs mii; /* MII register Addresses */ 447 struct mac_link link; 448 unsigned int synopsys_uid; 449 }; 450 451 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr); 452 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr); 453 454 extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6], 455 unsigned int high, unsigned int low); 456 extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 457 unsigned int high, unsigned int low); 458 459 extern void stmmac_set_mac(void __iomem *ioaddr, bool enable); 460 461 extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr); 462 extern const struct stmmac_ring_mode_ops ring_mode_ops; 463 extern const struct stmmac_chain_mode_ops chain_mode_ops; 464 465 #endif /* __COMMON_H__ */ 466