1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 STMMAC Common Header File 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #ifndef __COMMON_H__ 12 #define __COMMON_H__ 13 14 #include <linux/etherdevice.h> 15 #include <linux/netdevice.h> 16 #include <linux/stmmac.h> 17 #include <linux/phy.h> 18 #include <linux/pcs/pcs-xpcs.h> 19 #include <linux/module.h> 20 #if IS_ENABLED(CONFIG_VLAN_8021Q) 21 #define STMMAC_VLAN_TAG_USED 22 #include <linux/if_vlan.h> 23 #endif 24 25 #include "descs.h" 26 #include "hwif.h" 27 #include "mmc.h" 28 29 /* Synopsys Core versions */ 30 #define DWMAC_CORE_3_40 0x34 31 #define DWMAC_CORE_3_50 0x35 32 #define DWMAC_CORE_4_00 0x40 33 #define DWMAC_CORE_4_10 0x41 34 #define DWMAC_CORE_5_00 0x50 35 #define DWMAC_CORE_5_10 0x51 36 #define DWMAC_CORE_5_20 0x52 37 #define DWXGMAC_CORE_2_10 0x21 38 #define DWXLGMAC_CORE_2_00 0x20 39 40 /* Device ID */ 41 #define DWXGMAC_ID 0x76 42 #define DWXLGMAC_ID 0x27 43 44 #define STMMAC_CHAN0 0 /* Always supported and default for all chips */ 45 46 /* TX and RX Descriptor Length, these need to be power of two. 47 * TX descriptor length less than 64 may cause transmit queue timed out error. 48 * RX descriptor length less than 64 may cause inconsistent Rx chain error. 49 */ 50 #define DMA_MIN_TX_SIZE 64 51 #define DMA_MAX_TX_SIZE 1024 52 #define DMA_DEFAULT_TX_SIZE 512 53 #define DMA_MIN_RX_SIZE 64 54 #define DMA_MAX_RX_SIZE 1024 55 #define DMA_DEFAULT_RX_SIZE 512 56 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1)) 57 58 #undef FRAME_FILTER_DEBUG 59 /* #define FRAME_FILTER_DEBUG */ 60 61 /* Extra statistic and debug information exposed by ethtool */ 62 struct stmmac_extra_stats { 63 /* Transmit errors */ 64 unsigned long tx_underflow ____cacheline_aligned; 65 unsigned long tx_carrier; 66 unsigned long tx_losscarrier; 67 unsigned long vlan_tag; 68 unsigned long tx_deferred; 69 unsigned long tx_vlan; 70 unsigned long tx_jabber; 71 unsigned long tx_frame_flushed; 72 unsigned long tx_payload_error; 73 unsigned long tx_ip_header_error; 74 /* Receive errors */ 75 unsigned long rx_desc; 76 unsigned long sa_filter_fail; 77 unsigned long overflow_error; 78 unsigned long ipc_csum_error; 79 unsigned long rx_collision; 80 unsigned long rx_crc_errors; 81 unsigned long dribbling_bit; 82 unsigned long rx_length; 83 unsigned long rx_mii; 84 unsigned long rx_multicast; 85 unsigned long rx_gmac_overflow; 86 unsigned long rx_watchdog; 87 unsigned long da_rx_filter_fail; 88 unsigned long sa_rx_filter_fail; 89 unsigned long rx_missed_cntr; 90 unsigned long rx_overflow_cntr; 91 unsigned long rx_vlan; 92 unsigned long rx_split_hdr_pkt_n; 93 /* Tx/Rx IRQ error info */ 94 unsigned long tx_undeflow_irq; 95 unsigned long tx_process_stopped_irq; 96 unsigned long tx_jabber_irq; 97 unsigned long rx_overflow_irq; 98 unsigned long rx_buf_unav_irq; 99 unsigned long rx_process_stopped_irq; 100 unsigned long rx_watchdog_irq; 101 unsigned long tx_early_irq; 102 unsigned long fatal_bus_error_irq; 103 /* Tx/Rx IRQ Events */ 104 unsigned long rx_early_irq; 105 unsigned long threshold; 106 unsigned long tx_pkt_n; 107 unsigned long rx_pkt_n; 108 unsigned long normal_irq_n; 109 unsigned long rx_normal_irq_n; 110 unsigned long napi_poll; 111 unsigned long tx_normal_irq_n; 112 unsigned long tx_clean; 113 unsigned long tx_set_ic_bit; 114 unsigned long irq_receive_pmt_irq_n; 115 /* MMC info */ 116 unsigned long mmc_tx_irq_n; 117 unsigned long mmc_rx_irq_n; 118 unsigned long mmc_rx_csum_offload_irq_n; 119 /* EEE */ 120 unsigned long irq_tx_path_in_lpi_mode_n; 121 unsigned long irq_tx_path_exit_lpi_mode_n; 122 unsigned long irq_rx_path_in_lpi_mode_n; 123 unsigned long irq_rx_path_exit_lpi_mode_n; 124 unsigned long phy_eee_wakeup_error_n; 125 /* Extended RDES status */ 126 unsigned long ip_hdr_err; 127 unsigned long ip_payload_err; 128 unsigned long ip_csum_bypassed; 129 unsigned long ipv4_pkt_rcvd; 130 unsigned long ipv6_pkt_rcvd; 131 unsigned long no_ptp_rx_msg_type_ext; 132 unsigned long ptp_rx_msg_type_sync; 133 unsigned long ptp_rx_msg_type_follow_up; 134 unsigned long ptp_rx_msg_type_delay_req; 135 unsigned long ptp_rx_msg_type_delay_resp; 136 unsigned long ptp_rx_msg_type_pdelay_req; 137 unsigned long ptp_rx_msg_type_pdelay_resp; 138 unsigned long ptp_rx_msg_type_pdelay_follow_up; 139 unsigned long ptp_rx_msg_type_announce; 140 unsigned long ptp_rx_msg_type_management; 141 unsigned long ptp_rx_msg_pkt_reserved_type; 142 unsigned long ptp_frame_type; 143 unsigned long ptp_ver; 144 unsigned long timestamp_dropped; 145 unsigned long av_pkt_rcvd; 146 unsigned long av_tagged_pkt_rcvd; 147 unsigned long vlan_tag_priority_val; 148 unsigned long l3_filter_match; 149 unsigned long l4_filter_match; 150 unsigned long l3_l4_filter_no_match; 151 /* PCS */ 152 unsigned long irq_pcs_ane_n; 153 unsigned long irq_pcs_link_n; 154 unsigned long irq_rgmii_n; 155 unsigned long pcs_link; 156 unsigned long pcs_duplex; 157 unsigned long pcs_speed; 158 /* debug register */ 159 unsigned long mtl_tx_status_fifo_full; 160 unsigned long mtl_tx_fifo_not_empty; 161 unsigned long mmtl_fifo_ctrl; 162 unsigned long mtl_tx_fifo_read_ctrl_write; 163 unsigned long mtl_tx_fifo_read_ctrl_wait; 164 unsigned long mtl_tx_fifo_read_ctrl_read; 165 unsigned long mtl_tx_fifo_read_ctrl_idle; 166 unsigned long mac_tx_in_pause; 167 unsigned long mac_tx_frame_ctrl_xfer; 168 unsigned long mac_tx_frame_ctrl_idle; 169 unsigned long mac_tx_frame_ctrl_wait; 170 unsigned long mac_tx_frame_ctrl_pause; 171 unsigned long mac_gmii_tx_proto_engine; 172 unsigned long mtl_rx_fifo_fill_level_full; 173 unsigned long mtl_rx_fifo_fill_above_thresh; 174 unsigned long mtl_rx_fifo_fill_below_thresh; 175 unsigned long mtl_rx_fifo_fill_level_empty; 176 unsigned long mtl_rx_fifo_read_ctrl_flush; 177 unsigned long mtl_rx_fifo_read_ctrl_read_data; 178 unsigned long mtl_rx_fifo_read_ctrl_status; 179 unsigned long mtl_rx_fifo_read_ctrl_idle; 180 unsigned long mtl_rx_fifo_ctrl_active; 181 unsigned long mac_rx_frame_ctrl_fifo; 182 unsigned long mac_gmii_rx_proto_engine; 183 /* TSO */ 184 unsigned long tx_tso_frames; 185 unsigned long tx_tso_nfrags; 186 /* EST */ 187 unsigned long mtl_est_cgce; 188 unsigned long mtl_est_hlbs; 189 unsigned long mtl_est_hlbf; 190 unsigned long mtl_est_btre; 191 unsigned long mtl_est_btrlm; 192 }; 193 194 /* Safety Feature statistics exposed by ethtool */ 195 struct stmmac_safety_stats { 196 unsigned long mac_errors[32]; 197 unsigned long mtl_errors[32]; 198 unsigned long dma_errors[32]; 199 }; 200 201 /* Number of fields in Safety Stats */ 202 #define STMMAC_SAFETY_FEAT_SIZE \ 203 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long)) 204 205 /* CSR Frequency Access Defines*/ 206 #define CSR_F_35M 35000000 207 #define CSR_F_60M 60000000 208 #define CSR_F_100M 100000000 209 #define CSR_F_150M 150000000 210 #define CSR_F_250M 250000000 211 #define CSR_F_300M 300000000 212 213 #define MAC_CSR_H_FRQ_MASK 0x20 214 215 #define HASH_TABLE_SIZE 64 216 #define PAUSE_TIME 0xffff 217 218 /* Flow Control defines */ 219 #define FLOW_OFF 0 220 #define FLOW_RX 1 221 #define FLOW_TX 2 222 #define FLOW_AUTO (FLOW_TX | FLOW_RX) 223 224 /* PCS defines */ 225 #define STMMAC_PCS_RGMII (1 << 0) 226 #define STMMAC_PCS_SGMII (1 << 1) 227 #define STMMAC_PCS_TBI (1 << 2) 228 #define STMMAC_PCS_RTBI (1 << 3) 229 230 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */ 231 232 /* DAM HW feature register fields */ 233 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */ 234 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */ 235 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */ 236 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */ 237 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */ 238 #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */ 239 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */ 240 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */ 241 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */ 242 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */ 243 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */ 244 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */ 245 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */ 246 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */ 247 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */ 248 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */ 249 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */ 250 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */ 251 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */ 252 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */ 253 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */ 254 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */ 255 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */ 256 /* Timestamping with Internal System Time */ 257 #define DMA_HW_FEAT_INTTSEN 0x02000000 258 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */ 259 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */ 260 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */ 261 #define DEFAULT_DMA_PBL 8 262 263 /* MSI defines */ 264 #define STMMAC_MSI_VEC_MAX 32 265 266 /* PCS status and mask defines */ 267 #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */ 268 #define PCS_LINK_IRQ BIT(1) /* PCS Link */ 269 #define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */ 270 271 /* Max/Min RI Watchdog Timer count value */ 272 #define MAX_DMA_RIWT 0xff 273 #define MIN_DMA_RIWT 0x10 274 #define DEF_DMA_RIWT 0xa0 275 /* Tx coalesce parameters */ 276 #define STMMAC_COAL_TX_TIMER 1000 277 #define STMMAC_MAX_COAL_TX_TICK 100000 278 #define STMMAC_TX_MAX_FRAMES 256 279 #define STMMAC_TX_FRAMES 25 280 #define STMMAC_RX_FRAMES 0 281 282 /* Packets types */ 283 enum packets_types { 284 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */ 285 PACKET_PTPQ = 0x2, /* PTP Packets */ 286 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */ 287 PACKET_UPQ = 0x4, /* Untagged Packets */ 288 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */ 289 }; 290 291 /* Rx IPC status */ 292 enum rx_frame_status { 293 good_frame = 0x0, 294 discard_frame = 0x1, 295 csum_none = 0x2, 296 llc_snap = 0x4, 297 dma_own = 0x8, 298 rx_not_ls = 0x10, 299 }; 300 301 /* Tx status */ 302 enum tx_frame_status { 303 tx_done = 0x0, 304 tx_not_ls = 0x1, 305 tx_err = 0x2, 306 tx_dma_own = 0x4, 307 }; 308 309 enum dma_irq_status { 310 tx_hard_error = 0x1, 311 tx_hard_error_bump_tc = 0x2, 312 handle_rx = 0x4, 313 handle_tx = 0x8, 314 }; 315 316 enum dma_irq_dir { 317 DMA_DIR_RX = 0x1, 318 DMA_DIR_TX = 0x2, 319 DMA_DIR_RXTX = 0x3, 320 }; 321 322 enum request_irq_err { 323 REQ_IRQ_ERR_ALL, 324 REQ_IRQ_ERR_TX, 325 REQ_IRQ_ERR_RX, 326 REQ_IRQ_ERR_SFTY_UE, 327 REQ_IRQ_ERR_SFTY_CE, 328 REQ_IRQ_ERR_LPI, 329 REQ_IRQ_ERR_WOL, 330 REQ_IRQ_ERR_MAC, 331 REQ_IRQ_ERR_NO, 332 }; 333 334 /* EEE and LPI defines */ 335 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0) 336 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1) 337 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2) 338 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3) 339 340 /* FPE defines */ 341 #define FPE_EVENT_UNKNOWN 0 342 #define FPE_EVENT_TRSP BIT(0) 343 #define FPE_EVENT_TVER BIT(1) 344 #define FPE_EVENT_RRSP BIT(2) 345 #define FPE_EVENT_RVER BIT(3) 346 347 #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8) 348 349 /* Physical Coding Sublayer */ 350 struct rgmii_adv { 351 unsigned int pause; 352 unsigned int duplex; 353 unsigned int lp_pause; 354 unsigned int lp_duplex; 355 }; 356 357 #define STMMAC_PCS_PAUSE 1 358 #define STMMAC_PCS_ASYM_PAUSE 2 359 360 /* DMA HW capabilities */ 361 struct dma_features { 362 unsigned int mbps_10_100; 363 unsigned int mbps_1000; 364 unsigned int half_duplex; 365 unsigned int hash_filter; 366 unsigned int multi_addr; 367 unsigned int pcs; 368 unsigned int sma_mdio; 369 unsigned int pmt_remote_wake_up; 370 unsigned int pmt_magic_frame; 371 unsigned int rmon; 372 /* IEEE 1588-2002 */ 373 unsigned int time_stamp; 374 /* IEEE 1588-2008 */ 375 unsigned int atime_stamp; 376 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 377 unsigned int eee; 378 unsigned int av; 379 unsigned int hash_tb_sz; 380 unsigned int tsoen; 381 /* TX and RX csum */ 382 unsigned int tx_coe; 383 unsigned int rx_coe; 384 unsigned int rx_coe_type1; 385 unsigned int rx_coe_type2; 386 unsigned int rxfifo_over_2048; 387 /* TX and RX number of channels */ 388 unsigned int number_rx_channel; 389 unsigned int number_tx_channel; 390 /* TX and RX number of queues */ 391 unsigned int number_rx_queues; 392 unsigned int number_tx_queues; 393 /* PPS output */ 394 unsigned int pps_out_num; 395 /* Alternate (enhanced) DESC mode */ 396 unsigned int enh_desc; 397 /* TX and RX FIFO sizes */ 398 unsigned int tx_fifo_size; 399 unsigned int rx_fifo_size; 400 /* Automotive Safety Package */ 401 unsigned int asp; 402 /* RX Parser */ 403 unsigned int frpsel; 404 unsigned int frpbs; 405 unsigned int frpes; 406 unsigned int addr64; 407 unsigned int rssen; 408 unsigned int vlhash; 409 unsigned int sphen; 410 unsigned int vlins; 411 unsigned int dvlan; 412 unsigned int l3l4fnum; 413 unsigned int arpoffsel; 414 /* TSN Features */ 415 unsigned int estwid; 416 unsigned int estdep; 417 unsigned int estsel; 418 unsigned int fpesel; 419 unsigned int tbssel; 420 /* Numbers of Auxiliary Snapshot Inputs */ 421 unsigned int aux_snapshot_n; 422 }; 423 424 /* RX Buffer size must be multiple of 4/8/16 bytes */ 425 #define BUF_SIZE_16KiB 16368 426 #define BUF_SIZE_8KiB 8188 427 #define BUF_SIZE_4KiB 4096 428 #define BUF_SIZE_2KiB 2048 429 430 /* Power Down and WOL */ 431 #define PMT_NOT_SUPPORTED 0 432 #define PMT_SUPPORTED 1 433 434 /* Common MAC defines */ 435 #define MAC_CTRL_REG 0x00000000 /* MAC Control */ 436 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ 437 #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */ 438 439 /* Default LPI timers */ 440 #define STMMAC_DEFAULT_LIT_LS 0x3E8 441 #define STMMAC_DEFAULT_TWT_LS 0x1E 442 #define STMMAC_ET_MAX 0xFFFFF 443 444 #define STMMAC_CHAIN_MODE 0x1 445 #define STMMAC_RING_MODE 0x2 446 447 #define JUMBO_LEN 9000 448 449 /* Receive Side Scaling */ 450 #define STMMAC_RSS_HASH_KEY_SIZE 40 451 #define STMMAC_RSS_MAX_TABLE_SIZE 256 452 453 /* VLAN */ 454 #define STMMAC_VLAN_NONE 0x0 455 #define STMMAC_VLAN_REMOVE 0x1 456 #define STMMAC_VLAN_INSERT 0x2 457 #define STMMAC_VLAN_REPLACE 0x3 458 459 extern const struct stmmac_desc_ops enh_desc_ops; 460 extern const struct stmmac_desc_ops ndesc_ops; 461 462 struct mac_device_info; 463 464 extern const struct stmmac_hwtimestamp stmmac_ptp; 465 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops; 466 467 struct mac_link { 468 u32 speed_mask; 469 u32 speed10; 470 u32 speed100; 471 u32 speed1000; 472 u32 speed2500; 473 u32 duplex; 474 struct { 475 u32 speed2500; 476 u32 speed5000; 477 u32 speed10000; 478 } xgmii; 479 struct { 480 u32 speed25000; 481 u32 speed40000; 482 u32 speed50000; 483 u32 speed100000; 484 } xlgmii; 485 }; 486 487 struct mii_regs { 488 unsigned int addr; /* MII Address */ 489 unsigned int data; /* MII Data */ 490 unsigned int addr_shift; /* MII address shift */ 491 unsigned int reg_shift; /* MII reg shift */ 492 unsigned int addr_mask; /* MII address mask */ 493 unsigned int reg_mask; /* MII reg mask */ 494 unsigned int clk_csr_shift; 495 unsigned int clk_csr_mask; 496 }; 497 498 struct mac_device_info { 499 const struct stmmac_ops *mac; 500 const struct stmmac_desc_ops *desc; 501 const struct stmmac_dma_ops *dma; 502 const struct stmmac_mode_ops *mode; 503 const struct stmmac_hwtimestamp *ptp; 504 const struct stmmac_tc_ops *tc; 505 const struct stmmac_mmc_ops *mmc; 506 struct dw_xpcs *xpcs; 507 struct mii_regs mii; /* MII register Addresses */ 508 struct mac_link link; 509 void __iomem *pcsr; /* vpointer to device CSRs */ 510 unsigned int multicast_filter_bins; 511 unsigned int unicast_filter_entries; 512 unsigned int mcast_bits_log2; 513 unsigned int rx_csum; 514 unsigned int pcs; 515 unsigned int pmt; 516 unsigned int ps; 517 unsigned int xlgmac; 518 unsigned int num_vlan; 519 u32 vlan_filter[32]; 520 unsigned int promisc; 521 bool vlan_fail_q_en; 522 u8 vlan_fail_q; 523 }; 524 525 struct stmmac_rx_routing { 526 u32 reg_mask; 527 u32 reg_shift; 528 }; 529 530 int dwmac100_setup(struct stmmac_priv *priv); 531 int dwmac1000_setup(struct stmmac_priv *priv); 532 int dwmac4_setup(struct stmmac_priv *priv); 533 int dwxgmac2_setup(struct stmmac_priv *priv); 534 int dwxlgmac2_setup(struct stmmac_priv *priv); 535 536 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6], 537 unsigned int high, unsigned int low); 538 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 539 unsigned int high, unsigned int low); 540 void stmmac_set_mac(void __iomem *ioaddr, bool enable); 541 542 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6], 543 unsigned int high, unsigned int low); 544 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 545 unsigned int high, unsigned int low); 546 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable); 547 548 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr); 549 550 extern const struct stmmac_mode_ops ring_mode_ops; 551 extern const struct stmmac_mode_ops chain_mode_ops; 552 extern const struct stmmac_desc_ops dwmac4_desc_ops; 553 554 #endif /* __COMMON_H__ */ 555