1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 STMMAC Common Header File 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #ifndef __COMMON_H__ 12 #define __COMMON_H__ 13 14 #include <linux/etherdevice.h> 15 #include <linux/netdevice.h> 16 #include <linux/stmmac.h> 17 #include <linux/phy.h> 18 #include <linux/pcs/pcs-xpcs.h> 19 #include <linux/module.h> 20 #if IS_ENABLED(CONFIG_VLAN_8021Q) 21 #define STMMAC_VLAN_TAG_USED 22 #include <linux/if_vlan.h> 23 #endif 24 25 #include "descs.h" 26 #include "hwif.h" 27 #include "mmc.h" 28 29 /* Synopsys Core versions */ 30 #define DWMAC_CORE_3_40 0x34 31 #define DWMAC_CORE_3_50 0x35 32 #define DWMAC_CORE_4_00 0x40 33 #define DWMAC_CORE_4_10 0x41 34 #define DWMAC_CORE_5_00 0x50 35 #define DWMAC_CORE_5_10 0x51 36 #define DWMAC_CORE_5_20 0x52 37 #define DWXGMAC_CORE_2_10 0x21 38 #define DWXLGMAC_CORE_2_00 0x20 39 40 /* Device ID */ 41 #define DWXGMAC_ID 0x76 42 #define DWXLGMAC_ID 0x27 43 44 #define STMMAC_CHAN0 0 /* Always supported and default for all chips */ 45 46 /* TX and RX Descriptor Length, these need to be power of two. 47 * TX descriptor length less than 64 may cause transmit queue timed out error. 48 * RX descriptor length less than 64 may cause inconsistent Rx chain error. 49 */ 50 #define DMA_MIN_TX_SIZE 64 51 #define DMA_MAX_TX_SIZE 1024 52 #define DMA_DEFAULT_TX_SIZE 512 53 #define DMA_MIN_RX_SIZE 64 54 #define DMA_MAX_RX_SIZE 1024 55 #define DMA_DEFAULT_RX_SIZE 512 56 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1)) 57 58 #undef FRAME_FILTER_DEBUG 59 /* #define FRAME_FILTER_DEBUG */ 60 61 struct stmmac_txq_stats { 62 u64 tx_bytes; 63 u64 tx_packets; 64 u64 tx_pkt_n; 65 u64 tx_normal_irq_n; 66 u64 napi_poll; 67 u64 tx_clean; 68 u64 tx_set_ic_bit; 69 u64 tx_tso_frames; 70 u64 tx_tso_nfrags; 71 struct u64_stats_sync syncp; 72 }; 73 74 struct stmmac_rxq_stats { 75 u64 rx_bytes; 76 u64 rx_packets; 77 u64 rx_pkt_n; 78 u64 rx_normal_irq_n; 79 u64 napi_poll; 80 struct u64_stats_sync syncp; 81 }; 82 83 /* Extra statistic and debug information exposed by ethtool */ 84 struct stmmac_extra_stats { 85 /* Transmit errors */ 86 unsigned long tx_underflow ____cacheline_aligned; 87 unsigned long tx_carrier; 88 unsigned long tx_losscarrier; 89 unsigned long vlan_tag; 90 unsigned long tx_deferred; 91 unsigned long tx_vlan; 92 unsigned long tx_jabber; 93 unsigned long tx_frame_flushed; 94 unsigned long tx_payload_error; 95 unsigned long tx_ip_header_error; 96 unsigned long tx_collision; 97 /* Receive errors */ 98 unsigned long rx_desc; 99 unsigned long sa_filter_fail; 100 unsigned long overflow_error; 101 unsigned long ipc_csum_error; 102 unsigned long rx_collision; 103 unsigned long rx_crc_errors; 104 unsigned long dribbling_bit; 105 unsigned long rx_length; 106 unsigned long rx_mii; 107 unsigned long rx_multicast; 108 unsigned long rx_gmac_overflow; 109 unsigned long rx_watchdog; 110 unsigned long da_rx_filter_fail; 111 unsigned long sa_rx_filter_fail; 112 unsigned long rx_missed_cntr; 113 unsigned long rx_overflow_cntr; 114 unsigned long rx_vlan; 115 unsigned long rx_split_hdr_pkt_n; 116 /* Tx/Rx IRQ error info */ 117 unsigned long tx_undeflow_irq; 118 unsigned long tx_process_stopped_irq; 119 unsigned long tx_jabber_irq; 120 unsigned long rx_overflow_irq; 121 unsigned long rx_buf_unav_irq; 122 unsigned long rx_process_stopped_irq; 123 unsigned long rx_watchdog_irq; 124 unsigned long tx_early_irq; 125 unsigned long fatal_bus_error_irq; 126 /* Tx/Rx IRQ Events */ 127 unsigned long rx_early_irq; 128 unsigned long threshold; 129 unsigned long irq_receive_pmt_irq_n; 130 /* MMC info */ 131 unsigned long mmc_tx_irq_n; 132 unsigned long mmc_rx_irq_n; 133 unsigned long mmc_rx_csum_offload_irq_n; 134 /* EEE */ 135 unsigned long irq_tx_path_in_lpi_mode_n; 136 unsigned long irq_tx_path_exit_lpi_mode_n; 137 unsigned long irq_rx_path_in_lpi_mode_n; 138 unsigned long irq_rx_path_exit_lpi_mode_n; 139 unsigned long phy_eee_wakeup_error_n; 140 /* Extended RDES status */ 141 unsigned long ip_hdr_err; 142 unsigned long ip_payload_err; 143 unsigned long ip_csum_bypassed; 144 unsigned long ipv4_pkt_rcvd; 145 unsigned long ipv6_pkt_rcvd; 146 unsigned long no_ptp_rx_msg_type_ext; 147 unsigned long ptp_rx_msg_type_sync; 148 unsigned long ptp_rx_msg_type_follow_up; 149 unsigned long ptp_rx_msg_type_delay_req; 150 unsigned long ptp_rx_msg_type_delay_resp; 151 unsigned long ptp_rx_msg_type_pdelay_req; 152 unsigned long ptp_rx_msg_type_pdelay_resp; 153 unsigned long ptp_rx_msg_type_pdelay_follow_up; 154 unsigned long ptp_rx_msg_type_announce; 155 unsigned long ptp_rx_msg_type_management; 156 unsigned long ptp_rx_msg_pkt_reserved_type; 157 unsigned long ptp_frame_type; 158 unsigned long ptp_ver; 159 unsigned long timestamp_dropped; 160 unsigned long av_pkt_rcvd; 161 unsigned long av_tagged_pkt_rcvd; 162 unsigned long vlan_tag_priority_val; 163 unsigned long l3_filter_match; 164 unsigned long l4_filter_match; 165 unsigned long l3_l4_filter_no_match; 166 /* PCS */ 167 unsigned long irq_pcs_ane_n; 168 unsigned long irq_pcs_link_n; 169 unsigned long irq_rgmii_n; 170 unsigned long pcs_link; 171 unsigned long pcs_duplex; 172 unsigned long pcs_speed; 173 /* debug register */ 174 unsigned long mtl_tx_status_fifo_full; 175 unsigned long mtl_tx_fifo_not_empty; 176 unsigned long mmtl_fifo_ctrl; 177 unsigned long mtl_tx_fifo_read_ctrl_write; 178 unsigned long mtl_tx_fifo_read_ctrl_wait; 179 unsigned long mtl_tx_fifo_read_ctrl_read; 180 unsigned long mtl_tx_fifo_read_ctrl_idle; 181 unsigned long mac_tx_in_pause; 182 unsigned long mac_tx_frame_ctrl_xfer; 183 unsigned long mac_tx_frame_ctrl_idle; 184 unsigned long mac_tx_frame_ctrl_wait; 185 unsigned long mac_tx_frame_ctrl_pause; 186 unsigned long mac_gmii_tx_proto_engine; 187 unsigned long mtl_rx_fifo_fill_level_full; 188 unsigned long mtl_rx_fifo_fill_above_thresh; 189 unsigned long mtl_rx_fifo_fill_below_thresh; 190 unsigned long mtl_rx_fifo_fill_level_empty; 191 unsigned long mtl_rx_fifo_read_ctrl_flush; 192 unsigned long mtl_rx_fifo_read_ctrl_read_data; 193 unsigned long mtl_rx_fifo_read_ctrl_status; 194 unsigned long mtl_rx_fifo_read_ctrl_idle; 195 unsigned long mtl_rx_fifo_ctrl_active; 196 unsigned long mac_rx_frame_ctrl_fifo; 197 unsigned long mac_gmii_rx_proto_engine; 198 /* EST */ 199 unsigned long mtl_est_cgce; 200 unsigned long mtl_est_hlbs; 201 unsigned long mtl_est_hlbf; 202 unsigned long mtl_est_btre; 203 unsigned long mtl_est_btrlm; 204 unsigned long rx_dropped; 205 unsigned long rx_errors; 206 unsigned long tx_dropped; 207 unsigned long tx_errors; 208 }; 209 210 /* Safety Feature statistics exposed by ethtool */ 211 struct stmmac_safety_stats { 212 unsigned long mac_errors[32]; 213 unsigned long mtl_errors[32]; 214 unsigned long dma_errors[32]; 215 }; 216 217 /* Number of fields in Safety Stats */ 218 #define STMMAC_SAFETY_FEAT_SIZE \ 219 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long)) 220 221 /* CSR Frequency Access Defines*/ 222 #define CSR_F_35M 35000000 223 #define CSR_F_60M 60000000 224 #define CSR_F_100M 100000000 225 #define CSR_F_150M 150000000 226 #define CSR_F_250M 250000000 227 #define CSR_F_300M 300000000 228 229 #define MAC_CSR_H_FRQ_MASK 0x20 230 231 #define HASH_TABLE_SIZE 64 232 #define PAUSE_TIME 0xffff 233 234 /* Flow Control defines */ 235 #define FLOW_OFF 0 236 #define FLOW_RX 1 237 #define FLOW_TX 2 238 #define FLOW_AUTO (FLOW_TX | FLOW_RX) 239 240 /* PCS defines */ 241 #define STMMAC_PCS_RGMII (1 << 0) 242 #define STMMAC_PCS_SGMII (1 << 1) 243 #define STMMAC_PCS_TBI (1 << 2) 244 #define STMMAC_PCS_RTBI (1 << 3) 245 246 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */ 247 248 /* DMA HW feature register fields */ 249 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */ 250 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */ 251 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */ 252 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */ 253 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */ 254 #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */ 255 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */ 256 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */ 257 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */ 258 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */ 259 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */ 260 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */ 261 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */ 262 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */ 263 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */ 264 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */ 265 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */ 266 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */ 267 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */ 268 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */ 269 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */ 270 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */ 271 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */ 272 /* Timestamping with Internal System Time */ 273 #define DMA_HW_FEAT_INTTSEN 0x02000000 274 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */ 275 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */ 276 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */ 277 #define DEFAULT_DMA_PBL 8 278 279 /* MSI defines */ 280 #define STMMAC_MSI_VEC_MAX 32 281 282 /* PCS status and mask defines */ 283 #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */ 284 #define PCS_LINK_IRQ BIT(1) /* PCS Link */ 285 #define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */ 286 287 /* Max/Min RI Watchdog Timer count value */ 288 #define MAX_DMA_RIWT 0xff 289 #define MIN_DMA_RIWT 0x10 290 #define DEF_DMA_RIWT 0xa0 291 /* Tx coalesce parameters */ 292 #define STMMAC_COAL_TX_TIMER 1000 293 #define STMMAC_MAX_COAL_TX_TICK 100000 294 #define STMMAC_TX_MAX_FRAMES 256 295 #define STMMAC_TX_FRAMES 25 296 #define STMMAC_RX_FRAMES 0 297 298 /* Packets types */ 299 enum packets_types { 300 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */ 301 PACKET_PTPQ = 0x2, /* PTP Packets */ 302 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */ 303 PACKET_UPQ = 0x4, /* Untagged Packets */ 304 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */ 305 }; 306 307 /* Rx IPC status */ 308 enum rx_frame_status { 309 good_frame = 0x0, 310 discard_frame = 0x1, 311 csum_none = 0x2, 312 llc_snap = 0x4, 313 dma_own = 0x8, 314 rx_not_ls = 0x10, 315 }; 316 317 /* Tx status */ 318 enum tx_frame_status { 319 tx_done = 0x0, 320 tx_not_ls = 0x1, 321 tx_err = 0x2, 322 tx_dma_own = 0x4, 323 tx_err_bump_tc = 0x8, 324 }; 325 326 enum dma_irq_status { 327 tx_hard_error = 0x1, 328 tx_hard_error_bump_tc = 0x2, 329 handle_rx = 0x4, 330 handle_tx = 0x8, 331 }; 332 333 enum dma_irq_dir { 334 DMA_DIR_RX = 0x1, 335 DMA_DIR_TX = 0x2, 336 DMA_DIR_RXTX = 0x3, 337 }; 338 339 enum request_irq_err { 340 REQ_IRQ_ERR_ALL, 341 REQ_IRQ_ERR_TX, 342 REQ_IRQ_ERR_RX, 343 REQ_IRQ_ERR_SFTY_UE, 344 REQ_IRQ_ERR_SFTY_CE, 345 REQ_IRQ_ERR_LPI, 346 REQ_IRQ_ERR_WOL, 347 REQ_IRQ_ERR_MAC, 348 REQ_IRQ_ERR_NO, 349 }; 350 351 /* EEE and LPI defines */ 352 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0) 353 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1) 354 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2) 355 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3) 356 357 /* FPE defines */ 358 #define FPE_EVENT_UNKNOWN 0 359 #define FPE_EVENT_TRSP BIT(0) 360 #define FPE_EVENT_TVER BIT(1) 361 #define FPE_EVENT_RRSP BIT(2) 362 #define FPE_EVENT_RVER BIT(3) 363 364 #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8) 365 366 /* Physical Coding Sublayer */ 367 struct rgmii_adv { 368 unsigned int pause; 369 unsigned int duplex; 370 unsigned int lp_pause; 371 unsigned int lp_duplex; 372 }; 373 374 #define STMMAC_PCS_PAUSE 1 375 #define STMMAC_PCS_ASYM_PAUSE 2 376 377 /* DMA HW capabilities */ 378 struct dma_features { 379 unsigned int mbps_10_100; 380 unsigned int mbps_1000; 381 unsigned int half_duplex; 382 unsigned int hash_filter; 383 unsigned int multi_addr; 384 unsigned int pcs; 385 unsigned int sma_mdio; 386 unsigned int pmt_remote_wake_up; 387 unsigned int pmt_magic_frame; 388 unsigned int rmon; 389 /* IEEE 1588-2002 */ 390 unsigned int time_stamp; 391 /* IEEE 1588-2008 */ 392 unsigned int atime_stamp; 393 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 394 unsigned int eee; 395 unsigned int av; 396 unsigned int hash_tb_sz; 397 unsigned int tsoen; 398 /* TX and RX csum */ 399 unsigned int tx_coe; 400 unsigned int rx_coe; 401 unsigned int rx_coe_type1; 402 unsigned int rx_coe_type2; 403 unsigned int rxfifo_over_2048; 404 /* TX and RX number of channels */ 405 unsigned int number_rx_channel; 406 unsigned int number_tx_channel; 407 /* TX and RX number of queues */ 408 unsigned int number_rx_queues; 409 unsigned int number_tx_queues; 410 /* PPS output */ 411 unsigned int pps_out_num; 412 /* Alternate (enhanced) DESC mode */ 413 unsigned int enh_desc; 414 /* TX and RX FIFO sizes */ 415 unsigned int tx_fifo_size; 416 unsigned int rx_fifo_size; 417 /* Automotive Safety Package */ 418 unsigned int asp; 419 /* RX Parser */ 420 unsigned int frpsel; 421 unsigned int frpbs; 422 unsigned int frpes; 423 unsigned int addr64; 424 unsigned int host_dma_width; 425 unsigned int rssen; 426 unsigned int vlhash; 427 unsigned int sphen; 428 unsigned int vlins; 429 unsigned int dvlan; 430 unsigned int l3l4fnum; 431 unsigned int arpoffsel; 432 /* TSN Features */ 433 unsigned int estwid; 434 unsigned int estdep; 435 unsigned int estsel; 436 unsigned int fpesel; 437 unsigned int tbssel; 438 /* Numbers of Auxiliary Snapshot Inputs */ 439 unsigned int aux_snapshot_n; 440 }; 441 442 /* RX Buffer size must be multiple of 4/8/16 bytes */ 443 #define BUF_SIZE_16KiB 16368 444 #define BUF_SIZE_8KiB 8188 445 #define BUF_SIZE_4KiB 4096 446 #define BUF_SIZE_2KiB 2048 447 448 /* Power Down and WOL */ 449 #define PMT_NOT_SUPPORTED 0 450 #define PMT_SUPPORTED 1 451 452 /* Common MAC defines */ 453 #define MAC_CTRL_REG 0x00000000 /* MAC Control */ 454 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ 455 #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */ 456 457 /* Default LPI timers */ 458 #define STMMAC_DEFAULT_LIT_LS 0x3E8 459 #define STMMAC_DEFAULT_TWT_LS 0x1E 460 #define STMMAC_ET_MAX 0xFFFFF 461 462 #define STMMAC_CHAIN_MODE 0x1 463 #define STMMAC_RING_MODE 0x2 464 465 #define JUMBO_LEN 9000 466 467 /* Receive Side Scaling */ 468 #define STMMAC_RSS_HASH_KEY_SIZE 40 469 #define STMMAC_RSS_MAX_TABLE_SIZE 256 470 471 /* VLAN */ 472 #define STMMAC_VLAN_NONE 0x0 473 #define STMMAC_VLAN_REMOVE 0x1 474 #define STMMAC_VLAN_INSERT 0x2 475 #define STMMAC_VLAN_REPLACE 0x3 476 477 extern const struct stmmac_desc_ops enh_desc_ops; 478 extern const struct stmmac_desc_ops ndesc_ops; 479 480 struct mac_device_info; 481 482 extern const struct stmmac_hwtimestamp stmmac_ptp; 483 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops; 484 485 struct mac_link { 486 u32 speed_mask; 487 u32 speed10; 488 u32 speed100; 489 u32 speed1000; 490 u32 speed2500; 491 u32 duplex; 492 struct { 493 u32 speed2500; 494 u32 speed5000; 495 u32 speed10000; 496 } xgmii; 497 struct { 498 u32 speed25000; 499 u32 speed40000; 500 u32 speed50000; 501 u32 speed100000; 502 } xlgmii; 503 }; 504 505 struct mii_regs { 506 unsigned int addr; /* MII Address */ 507 unsigned int data; /* MII Data */ 508 unsigned int addr_shift; /* MII address shift */ 509 unsigned int reg_shift; /* MII reg shift */ 510 unsigned int addr_mask; /* MII address mask */ 511 unsigned int reg_mask; /* MII reg mask */ 512 unsigned int clk_csr_shift; 513 unsigned int clk_csr_mask; 514 }; 515 516 struct mac_device_info { 517 const struct stmmac_ops *mac; 518 const struct stmmac_desc_ops *desc; 519 const struct stmmac_dma_ops *dma; 520 const struct stmmac_mode_ops *mode; 521 const struct stmmac_hwtimestamp *ptp; 522 const struct stmmac_tc_ops *tc; 523 const struct stmmac_mmc_ops *mmc; 524 struct dw_xpcs *xpcs; 525 struct phylink_pcs *lynx_pcs; /* Lynx external PCS */ 526 struct mii_regs mii; /* MII register Addresses */ 527 struct mac_link link; 528 void __iomem *pcsr; /* vpointer to device CSRs */ 529 unsigned int multicast_filter_bins; 530 unsigned int unicast_filter_entries; 531 unsigned int mcast_bits_log2; 532 unsigned int rx_csum; 533 unsigned int pcs; 534 unsigned int pmt; 535 unsigned int ps; 536 unsigned int xlgmac; 537 unsigned int num_vlan; 538 u32 vlan_filter[32]; 539 bool vlan_fail_q_en; 540 u8 vlan_fail_q; 541 }; 542 543 struct stmmac_rx_routing { 544 u32 reg_mask; 545 u32 reg_shift; 546 }; 547 548 int dwmac100_setup(struct stmmac_priv *priv); 549 int dwmac1000_setup(struct stmmac_priv *priv); 550 int dwmac4_setup(struct stmmac_priv *priv); 551 int dwxgmac2_setup(struct stmmac_priv *priv); 552 int dwxlgmac2_setup(struct stmmac_priv *priv); 553 554 void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], 555 unsigned int high, unsigned int low); 556 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 557 unsigned int high, unsigned int low); 558 void stmmac_set_mac(void __iomem *ioaddr, bool enable); 559 560 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], 561 unsigned int high, unsigned int low); 562 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 563 unsigned int high, unsigned int low); 564 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable); 565 566 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr); 567 568 extern const struct stmmac_mode_ops ring_mode_ops; 569 extern const struct stmmac_mode_ops chain_mode_ops; 570 extern const struct stmmac_desc_ops dwmac4_desc_ops; 571 572 #endif /* __COMMON_H__ */ 573