17ac6653aSJeff Kirsherconfig STMMAC_ETH 27ac6653aSJeff Kirsher tristate "STMicroelectronics 10/100/1000 Ethernet driver" 37ac6653aSJeff Kirsher depends on HAS_IOMEM 4aaba215cSJeff Kirsher select NET_CORE 57ac6653aSJeff Kirsher select MII 67ac6653aSJeff Kirsher select PHYLIB 77ac6653aSJeff Kirsher select CRC32 87ac6653aSJeff Kirsher ---help--- 97ac6653aSJeff Kirsher This is the driver for the Ethernet IPs are built around a 107ac6653aSJeff Kirsher Synopsys IP Core and only tested on the STMicroelectronics 117ac6653aSJeff Kirsher platforms. 127ac6653aSJeff Kirsher 137ac6653aSJeff Kirsherif STMMAC_ETH 147ac6653aSJeff Kirsher 15bfab27a1SGiuseppe CAVALLAROconfig STMMAC_PLATFORM 16bfab27a1SGiuseppe CAVALLARO tristate "STMMAC platform bus support" 17bfab27a1SGiuseppe CAVALLARO depends on STMMAC_ETH 18bfab27a1SGiuseppe CAVALLARO default y 19bfab27a1SGiuseppe CAVALLARO ---help--- 20bfab27a1SGiuseppe CAVALLARO This selects the platform specific bus support for 21bfab27a1SGiuseppe CAVALLARO the stmmac device driver. This is the driver used 22bfab27a1SGiuseppe CAVALLARO on many embedded STM platforms based on ARM and SuperH 23bfab27a1SGiuseppe CAVALLARO processors. 24bfab27a1SGiuseppe CAVALLARO If you have a controller with this interface, say Y or M here. 25bfab27a1SGiuseppe CAVALLARO 26bfab27a1SGiuseppe CAVALLARO If unsure, say N. 27bfab27a1SGiuseppe CAVALLARO 28bfab27a1SGiuseppe CAVALLAROconfig STMMAC_PCI 29bfab27a1SGiuseppe CAVALLARO tristate "STMMAC support on PCI bus (EXPERIMENTAL)" 30bfab27a1SGiuseppe CAVALLARO depends on STMMAC_ETH && PCI && EXPERIMENTAL 31bfab27a1SGiuseppe CAVALLARO ---help--- 32bfab27a1SGiuseppe CAVALLARO This is to select the Synopsys DWMAC available on PCI devices, 33bfab27a1SGiuseppe CAVALLARO if you have a controller with this interface, say Y or M here. 34bfab27a1SGiuseppe CAVALLARO 35bfab27a1SGiuseppe CAVALLARO This PCI support is tested on XLINX XC2V3000 FF1152AMT0221 36bfab27a1SGiuseppe CAVALLARO D1215994A VIRTEX FPGA board. 37bfab27a1SGiuseppe CAVALLARO 38bfab27a1SGiuseppe CAVALLARO If unsure, say N. 39bfab27a1SGiuseppe CAVALLARO 407ac29055SGiuseppe CAVALLAROconfig STMMAC_DEBUG_FS 417ac29055SGiuseppe CAVALLARO bool "Enable monitoring via sysFS " 427ac29055SGiuseppe CAVALLARO default n 437ac29055SGiuseppe CAVALLARO depends on STMMAC_ETH && DEBUG_FS 44bfab27a1SGiuseppe CAVALLARO ---help--- 45e7434821SGiuseppe CAVALLARO The stmmac entry in /sys reports DMA TX/RX rings 46e7434821SGiuseppe CAVALLARO or (if supported) the HW cap register. 477ac29055SGiuseppe CAVALLARO 487ac6653aSJeff Kirsherconfig STMMAC_DA 497ac6653aSJeff Kirsher bool "STMMAC DMA arbitration scheme" 507ac6653aSJeff Kirsher default n 517ac6653aSJeff Kirsher ---help--- 527ac6653aSJeff Kirsher Selecting this option, rx has priority over Tx (only for Giga 537ac6653aSJeff Kirsher Ethernet device). 547ac6653aSJeff Kirsher By default, the DMA arbitration scheme is based on Round-robin 557ac6653aSJeff Kirsher (rx:tx priority is 1:1). 567ac6653aSJeff Kirsher 577ac6653aSJeff Kirsherconfig STMMAC_TIMER 587ac6653aSJeff Kirsher bool "STMMAC Timer optimisation" 597ac6653aSJeff Kirsher default n 607ac6653aSJeff Kirsher depends on RTC_HCTOSYS_DEVICE 617ac6653aSJeff Kirsher ---help--- 627ac6653aSJeff Kirsher Use an external timer for mitigating the number of network 637ac6653aSJeff Kirsher interrupts. Currently, for SH architectures, it is possible 647ac6653aSJeff Kirsher to use the TMU channel 2 and the SH-RTC device. 657ac6653aSJeff Kirsher 667ac6653aSJeff Kirsherchoice 677ac6653aSJeff Kirsher prompt "Select Timer device" 687ac6653aSJeff Kirsher depends on STMMAC_TIMER 697ac6653aSJeff Kirsher 707ac6653aSJeff Kirsherconfig STMMAC_TMU_TIMER 717ac6653aSJeff Kirsher bool "TMU channel 2" 727ac6653aSJeff Kirsher depends on CPU_SH4 737ac6653aSJeff Kirsher ---help--- 747ac6653aSJeff Kirsher 757ac6653aSJeff Kirsherconfig STMMAC_RTC_TIMER 767ac6653aSJeff Kirsher bool "Real time clock" 777ac6653aSJeff Kirsher depends on RTC_CLASS 787ac6653aSJeff Kirsher ---help--- 797ac6653aSJeff Kirsher 807ac6653aSJeff Kirsherendchoice 817ac6653aSJeff Kirsher 82286a8372SGiuseppe CAVALLAROchoice 83286a8372SGiuseppe CAVALLARO prompt "Select the DMA TX/RX descriptor operating modes" 84286a8372SGiuseppe CAVALLARO depends on STMMAC_ETH 85286a8372SGiuseppe CAVALLARO ---help--- 86286a8372SGiuseppe CAVALLARO This driver supports DMA descriptor to operate both in dual buffer 87286a8372SGiuseppe CAVALLARO (RING) and linked-list(CHAINED) mode. In RING mode each descriptor 88286a8372SGiuseppe CAVALLARO points to two data buffer pointers whereas in CHAINED mode they 89286a8372SGiuseppe CAVALLARO points to only one data buffer pointer. 90286a8372SGiuseppe CAVALLARO 91286a8372SGiuseppe CAVALLAROconfig STMMAC_RING 92286a8372SGiuseppe CAVALLARO bool "Enable Descriptor Ring Mode" 93286a8372SGiuseppe CAVALLARO 94286a8372SGiuseppe CAVALLAROconfig STMMAC_CHAINED 95286a8372SGiuseppe CAVALLARO bool "Enable Descriptor Chained Mode" 96286a8372SGiuseppe CAVALLARO 97286a8372SGiuseppe CAVALLAROendchoice 98286a8372SGiuseppe CAVALLARO 99286a8372SGiuseppe CAVALLARO 1007ac6653aSJeff Kirsherendif 101