1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * sni_ave.c - Socionext UniPhier AVE ethernet driver 4 * Copyright 2014 Panasonic Corporation 5 * Copyright 2015-2017 Socionext Inc. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/etherdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/mii.h> 16 #include <linux/module.h> 17 #include <linux/netdevice.h> 18 #include <linux/of_net.h> 19 #include <linux/of_mdio.h> 20 #include <linux/of_platform.h> 21 #include <linux/phy.h> 22 #include <linux/regmap.h> 23 #include <linux/reset.h> 24 #include <linux/types.h> 25 #include <linux/u64_stats_sync.h> 26 27 /* General Register Group */ 28 #define AVE_IDR 0x000 /* ID */ 29 #define AVE_VR 0x004 /* Version */ 30 #define AVE_GRR 0x008 /* Global Reset */ 31 #define AVE_CFGR 0x00c /* Configuration */ 32 33 /* Interrupt Register Group */ 34 #define AVE_GIMR 0x100 /* Global Interrupt Mask */ 35 #define AVE_GISR 0x104 /* Global Interrupt Status */ 36 37 /* MAC Register Group */ 38 #define AVE_TXCR 0x200 /* TX Setup */ 39 #define AVE_RXCR 0x204 /* RX Setup */ 40 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */ 41 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */ 42 #define AVE_MDIOCTR 0x214 /* MDIO Control */ 43 #define AVE_MDIOAR 0x218 /* MDIO Address */ 44 #define AVE_MDIOWDR 0x21c /* MDIO Data */ 45 #define AVE_MDIOSR 0x220 /* MDIO Status */ 46 #define AVE_MDIORDR 0x224 /* MDIO Rd Data */ 47 48 /* Descriptor Control Register Group */ 49 #define AVE_DESCC 0x300 /* Descriptor Control */ 50 #define AVE_TXDC 0x304 /* TX Descriptor Configuration */ 51 #define AVE_RXDC0 0x308 /* RX Descriptor Ring0 Configuration */ 52 #define AVE_IIRQC 0x34c /* Interval IRQ Control */ 53 54 /* Packet Filter Register Group */ 55 #define AVE_PKTF_BASE 0x800 /* PF Base Address */ 56 #define AVE_PFMBYTE_BASE 0xd00 /* PF Mask Byte Base Address */ 57 #define AVE_PFMBIT_BASE 0xe00 /* PF Mask Bit Base Address */ 58 #define AVE_PFSEL_BASE 0xf00 /* PF Selector Base Address */ 59 #define AVE_PFEN 0xffc /* Packet Filter Enable */ 60 #define AVE_PKTF(ent) (AVE_PKTF_BASE + (ent) * 0x40) 61 #define AVE_PFMBYTE(ent) (AVE_PFMBYTE_BASE + (ent) * 8) 62 #define AVE_PFMBIT(ent) (AVE_PFMBIT_BASE + (ent) * 4) 63 #define AVE_PFSEL(ent) (AVE_PFSEL_BASE + (ent) * 4) 64 65 /* 64bit descriptor memory */ 66 #define AVE_DESC_SIZE_64 12 /* Descriptor Size */ 67 68 #define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */ 69 #define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */ 70 71 #define AVE_TXDM_SIZE_64 0x0ba0 /* Tx Descriptor Memory Size 3KB */ 72 #define AVE_RXDM_SIZE_64 0x6000 /* Rx Descriptor Memory Size 24KB */ 73 74 /* 32bit descriptor memory */ 75 #define AVE_DESC_SIZE_32 8 /* Descriptor Size */ 76 77 #define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */ 78 #define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */ 79 80 #define AVE_TXDM_SIZE_32 0x07c0 /* Tx Descriptor Memory Size 2KB */ 81 #define AVE_RXDM_SIZE_32 0x4000 /* Rx Descriptor Memory Size 16KB */ 82 83 /* RMII Bridge Register Group */ 84 #define AVE_RSTCTRL 0x8028 /* Reset control */ 85 #define AVE_RSTCTRL_RMIIRST BIT(16) 86 #define AVE_LINKSEL 0x8034 /* Link speed setting */ 87 #define AVE_LINKSEL_100M BIT(0) 88 89 /* AVE_GRR */ 90 #define AVE_GRR_RXFFR BIT(5) /* Reset RxFIFO */ 91 #define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */ 92 #define AVE_GRR_GRST BIT(0) /* Reset all MAC */ 93 94 /* AVE_CFGR */ 95 #define AVE_CFGR_FLE BIT(31) /* Filter Function */ 96 #define AVE_CFGR_CHE BIT(30) /* Checksum Function */ 97 #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */ 98 #define AVE_CFGR_IPFCEN BIT(24) /* IP fragment sum Enable */ 99 100 /* AVE_GISR (common with GIMR) */ 101 #define AVE_GI_PHY BIT(24) /* PHY interrupt */ 102 #define AVE_GI_TX BIT(16) /* Tx complete */ 103 #define AVE_GI_RXERR BIT(8) /* Receive frame more than max size */ 104 #define AVE_GI_RXOVF BIT(7) /* Overflow at the RxFIFO */ 105 #define AVE_GI_RXDROP BIT(6) /* Drop packet */ 106 #define AVE_GI_RXIINT BIT(5) /* Interval interrupt */ 107 108 /* AVE_TXCR */ 109 #define AVE_TXCR_FLOCTR BIT(18) /* Flow control */ 110 #define AVE_TXCR_TXSPD_1G BIT(17) 111 #define AVE_TXCR_TXSPD_100 BIT(16) 112 113 /* AVE_RXCR */ 114 #define AVE_RXCR_RXEN BIT(30) /* Rx enable */ 115 #define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */ 116 #define AVE_RXCR_FLOCTR BIT(21) /* Flow control */ 117 #define AVE_RXCR_AFEN BIT(19) /* MAC address filter */ 118 #define AVE_RXCR_DRPEN BIT(18) /* Drop pause frame */ 119 #define AVE_RXCR_MPSIZ_MASK GENMASK(10, 0) 120 121 /* AVE_MDIOCTR */ 122 #define AVE_MDIOCTR_RREQ BIT(3) /* Read request */ 123 #define AVE_MDIOCTR_WREQ BIT(2) /* Write request */ 124 125 /* AVE_MDIOSR */ 126 #define AVE_MDIOSR_STS BIT(0) /* access status */ 127 128 /* AVE_DESCC */ 129 #define AVE_DESCC_STATUS_MASK GENMASK(31, 16) 130 #define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */ 131 #define AVE_DESCC_RDSTP BIT(4) /* Pause Rx descriptor */ 132 #define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */ 133 134 /* AVE_TXDC */ 135 #define AVE_TXDC_SIZE GENMASK(27, 16) /* Size of Tx descriptor */ 136 #define AVE_TXDC_ADDR GENMASK(11, 0) /* Start address */ 137 #define AVE_TXDC_ADDR_START 0 138 139 /* AVE_RXDC0 */ 140 #define AVE_RXDC0_SIZE GENMASK(30, 16) /* Size of Rx descriptor */ 141 #define AVE_RXDC0_ADDR GENMASK(14, 0) /* Start address */ 142 #define AVE_RXDC0_ADDR_START 0 143 144 /* AVE_IIRQC */ 145 #define AVE_IIRQC_EN0 BIT(27) /* Enable interval interrupt Ring0 */ 146 #define AVE_IIRQC_BSCK GENMASK(15, 0) /* Interval count unit */ 147 148 /* Command status for descriptor */ 149 #define AVE_STS_OWN BIT(31) /* Descriptor ownership */ 150 #define AVE_STS_INTR BIT(29) /* Request for interrupt */ 151 #define AVE_STS_OK BIT(27) /* Normal transmit */ 152 /* TX */ 153 #define AVE_STS_NOCSUM BIT(28) /* No use HW checksum */ 154 #define AVE_STS_1ST BIT(26) /* Head of buffer chain */ 155 #define AVE_STS_LAST BIT(25) /* Tail of buffer chain */ 156 #define AVE_STS_OWC BIT(21) /* Out of window,Late Collision */ 157 #define AVE_STS_EC BIT(20) /* Excess collision occurred */ 158 #define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0) 159 /* RX */ 160 #define AVE_STS_CSSV BIT(21) /* Checksum check performed */ 161 #define AVE_STS_CSER BIT(20) /* Checksum error detected */ 162 #define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0) 163 164 /* Packet filter */ 165 #define AVE_PFMBYTE_MASK0 (GENMASK(31, 8) | GENMASK(5, 0)) 166 #define AVE_PFMBYTE_MASK1 GENMASK(25, 0) 167 #define AVE_PFMBIT_MASK GENMASK(15, 0) 168 169 #define AVE_PF_SIZE 17 /* Number of all packet filter */ 170 #define AVE_PF_MULTICAST_SIZE 7 /* Number of multicast filter */ 171 172 #define AVE_PFNUM_FILTER 0 /* No.0 */ 173 #define AVE_PFNUM_UNICAST 1 /* No.1 */ 174 #define AVE_PFNUM_BROADCAST 2 /* No.2 */ 175 #define AVE_PFNUM_MULTICAST 11 /* No.11-17 */ 176 177 /* NETIF Message control */ 178 #define AVE_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 179 NETIF_MSG_PROBE | \ 180 NETIF_MSG_LINK | \ 181 NETIF_MSG_TIMER | \ 182 NETIF_MSG_IFDOWN | \ 183 NETIF_MSG_IFUP | \ 184 NETIF_MSG_RX_ERR | \ 185 NETIF_MSG_TX_ERR) 186 187 /* Parameter for descriptor */ 188 #define AVE_NR_TXDESC 64 /* Tx descriptor */ 189 #define AVE_NR_RXDESC 256 /* Rx descriptor */ 190 191 #define AVE_DESC_OFS_CMDSTS 0 192 #define AVE_DESC_OFS_ADDRL 4 193 #define AVE_DESC_OFS_ADDRU 8 194 195 /* Parameter for ethernet frame */ 196 #define AVE_MAX_ETHFRAME 1518 197 #define AVE_FRAME_HEADROOM 2 198 199 /* Parameter for interrupt */ 200 #define AVE_INTM_COUNT 20 201 #define AVE_FORCE_TXINTCNT 1 202 203 /* SG */ 204 #define SG_ETPINMODE 0x540 205 #define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */ 206 #define SG_ETPINMODE_RMII(ins) BIT(ins) 207 208 #define IS_DESC_64BIT(p) ((p)->data->is_desc_64bit) 209 210 #define AVE_MAX_CLKS 4 211 #define AVE_MAX_RSTS 2 212 213 enum desc_id { 214 AVE_DESCID_RX, 215 AVE_DESCID_TX, 216 }; 217 218 enum desc_state { 219 AVE_DESC_RX_PERMIT, 220 AVE_DESC_RX_SUSPEND, 221 AVE_DESC_START, 222 AVE_DESC_STOP, 223 }; 224 225 struct ave_desc { 226 struct sk_buff *skbs; 227 dma_addr_t skbs_dma; 228 size_t skbs_dmalen; 229 }; 230 231 struct ave_desc_info { 232 u32 ndesc; /* number of descriptor */ 233 u32 daddr; /* start address of descriptor */ 234 u32 proc_idx; /* index of processing packet */ 235 u32 done_idx; /* index of processed packet */ 236 struct ave_desc *desc; /* skb info related descriptor */ 237 }; 238 239 struct ave_stats { 240 struct u64_stats_sync syncp; 241 u64 packets; 242 u64 bytes; 243 u64 errors; 244 u64 dropped; 245 u64 collisions; 246 u64 fifo_errors; 247 }; 248 249 struct ave_private { 250 void __iomem *base; 251 int irq; 252 int phy_id; 253 unsigned int desc_size; 254 u32 msg_enable; 255 int nclks; 256 struct clk *clk[AVE_MAX_CLKS]; 257 int nrsts; 258 struct reset_control *rst[AVE_MAX_RSTS]; 259 phy_interface_t phy_mode; 260 struct phy_device *phydev; 261 struct mii_bus *mdio; 262 struct regmap *regmap; 263 unsigned int pinmode_mask; 264 unsigned int pinmode_val; 265 266 /* stats */ 267 struct ave_stats stats_rx; 268 struct ave_stats stats_tx; 269 270 /* NAPI support */ 271 struct net_device *ndev; 272 struct napi_struct napi_rx; 273 struct napi_struct napi_tx; 274 275 /* descriptor */ 276 struct ave_desc_info rx; 277 struct ave_desc_info tx; 278 279 /* flow control */ 280 int pause_auto; 281 int pause_rx; 282 int pause_tx; 283 284 const struct ave_soc_data *data; 285 }; 286 287 struct ave_soc_data { 288 bool is_desc_64bit; 289 const char *clock_names[AVE_MAX_CLKS]; 290 const char *reset_names[AVE_MAX_RSTS]; 291 int (*get_pinmode)(struct ave_private *priv, 292 phy_interface_t phy_mode, u32 arg); 293 }; 294 295 static u32 ave_desc_read(struct net_device *ndev, enum desc_id id, int entry, 296 int offset) 297 { 298 struct ave_private *priv = netdev_priv(ndev); 299 u32 addr; 300 301 addr = ((id == AVE_DESCID_TX) ? priv->tx.daddr : priv->rx.daddr) 302 + entry * priv->desc_size + offset; 303 304 return readl(priv->base + addr); 305 } 306 307 static u32 ave_desc_read_cmdsts(struct net_device *ndev, enum desc_id id, 308 int entry) 309 { 310 return ave_desc_read(ndev, id, entry, AVE_DESC_OFS_CMDSTS); 311 } 312 313 static void ave_desc_write(struct net_device *ndev, enum desc_id id, 314 int entry, int offset, u32 val) 315 { 316 struct ave_private *priv = netdev_priv(ndev); 317 u32 addr; 318 319 addr = ((id == AVE_DESCID_TX) ? priv->tx.daddr : priv->rx.daddr) 320 + entry * priv->desc_size + offset; 321 322 writel(val, priv->base + addr); 323 } 324 325 static void ave_desc_write_cmdsts(struct net_device *ndev, enum desc_id id, 326 int entry, u32 val) 327 { 328 ave_desc_write(ndev, id, entry, AVE_DESC_OFS_CMDSTS, val); 329 } 330 331 static void ave_desc_write_addr(struct net_device *ndev, enum desc_id id, 332 int entry, dma_addr_t paddr) 333 { 334 struct ave_private *priv = netdev_priv(ndev); 335 336 ave_desc_write(ndev, id, entry, AVE_DESC_OFS_ADDRL, 337 lower_32_bits(paddr)); 338 if (IS_DESC_64BIT(priv)) 339 ave_desc_write(ndev, id, 340 entry, AVE_DESC_OFS_ADDRU, 341 upper_32_bits(paddr)); 342 } 343 344 static u32 ave_irq_disable_all(struct net_device *ndev) 345 { 346 struct ave_private *priv = netdev_priv(ndev); 347 u32 ret; 348 349 ret = readl(priv->base + AVE_GIMR); 350 writel(0, priv->base + AVE_GIMR); 351 352 return ret; 353 } 354 355 static void ave_irq_restore(struct net_device *ndev, u32 val) 356 { 357 struct ave_private *priv = netdev_priv(ndev); 358 359 writel(val, priv->base + AVE_GIMR); 360 } 361 362 static void ave_irq_enable(struct net_device *ndev, u32 bitflag) 363 { 364 struct ave_private *priv = netdev_priv(ndev); 365 366 writel(readl(priv->base + AVE_GIMR) | bitflag, priv->base + AVE_GIMR); 367 writel(bitflag, priv->base + AVE_GISR); 368 } 369 370 static void ave_hw_write_macaddr(struct net_device *ndev, 371 const unsigned char *mac_addr, 372 int reg1, int reg2) 373 { 374 struct ave_private *priv = netdev_priv(ndev); 375 376 writel(mac_addr[0] | mac_addr[1] << 8 | 377 mac_addr[2] << 16 | mac_addr[3] << 24, priv->base + reg1); 378 writel(mac_addr[4] | mac_addr[5] << 8, priv->base + reg2); 379 } 380 381 static void ave_hw_read_version(struct net_device *ndev, char *buf, int len) 382 { 383 struct ave_private *priv = netdev_priv(ndev); 384 u32 major, minor, vr; 385 386 vr = readl(priv->base + AVE_VR); 387 major = (vr & GENMASK(15, 8)) >> 8; 388 minor = (vr & GENMASK(7, 0)); 389 snprintf(buf, len, "v%u.%u", major, minor); 390 } 391 392 static void ave_ethtool_get_drvinfo(struct net_device *ndev, 393 struct ethtool_drvinfo *info) 394 { 395 struct device *dev = ndev->dev.parent; 396 397 strlcpy(info->driver, dev->driver->name, sizeof(info->driver)); 398 strlcpy(info->bus_info, dev_name(dev), sizeof(info->bus_info)); 399 ave_hw_read_version(ndev, info->fw_version, sizeof(info->fw_version)); 400 } 401 402 static u32 ave_ethtool_get_msglevel(struct net_device *ndev) 403 { 404 struct ave_private *priv = netdev_priv(ndev); 405 406 return priv->msg_enable; 407 } 408 409 static void ave_ethtool_set_msglevel(struct net_device *ndev, u32 val) 410 { 411 struct ave_private *priv = netdev_priv(ndev); 412 413 priv->msg_enable = val; 414 } 415 416 static void ave_ethtool_get_wol(struct net_device *ndev, 417 struct ethtool_wolinfo *wol) 418 { 419 wol->supported = 0; 420 wol->wolopts = 0; 421 422 if (ndev->phydev) 423 phy_ethtool_get_wol(ndev->phydev, wol); 424 } 425 426 static int ave_ethtool_set_wol(struct net_device *ndev, 427 struct ethtool_wolinfo *wol) 428 { 429 int ret; 430 431 if (!ndev->phydev || 432 (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))) 433 return -EOPNOTSUPP; 434 435 ret = phy_ethtool_set_wol(ndev->phydev, wol); 436 if (!ret) 437 device_set_wakeup_enable(&ndev->dev, !!wol->wolopts); 438 439 return ret; 440 } 441 442 static void ave_ethtool_get_pauseparam(struct net_device *ndev, 443 struct ethtool_pauseparam *pause) 444 { 445 struct ave_private *priv = netdev_priv(ndev); 446 447 pause->autoneg = priv->pause_auto; 448 pause->rx_pause = priv->pause_rx; 449 pause->tx_pause = priv->pause_tx; 450 } 451 452 static int ave_ethtool_set_pauseparam(struct net_device *ndev, 453 struct ethtool_pauseparam *pause) 454 { 455 struct ave_private *priv = netdev_priv(ndev); 456 struct phy_device *phydev = ndev->phydev; 457 458 if (!phydev) 459 return -EINVAL; 460 461 priv->pause_auto = pause->autoneg; 462 priv->pause_rx = pause->rx_pause; 463 priv->pause_tx = pause->tx_pause; 464 465 phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause); 466 467 return 0; 468 } 469 470 static const struct ethtool_ops ave_ethtool_ops = { 471 .get_link_ksettings = phy_ethtool_get_link_ksettings, 472 .set_link_ksettings = phy_ethtool_set_link_ksettings, 473 .get_drvinfo = ave_ethtool_get_drvinfo, 474 .nway_reset = phy_ethtool_nway_reset, 475 .get_link = ethtool_op_get_link, 476 .get_msglevel = ave_ethtool_get_msglevel, 477 .set_msglevel = ave_ethtool_set_msglevel, 478 .get_wol = ave_ethtool_get_wol, 479 .set_wol = ave_ethtool_set_wol, 480 .get_pauseparam = ave_ethtool_get_pauseparam, 481 .set_pauseparam = ave_ethtool_set_pauseparam, 482 }; 483 484 static int ave_mdiobus_read(struct mii_bus *bus, int phyid, int regnum) 485 { 486 struct net_device *ndev = bus->priv; 487 struct ave_private *priv; 488 u32 mdioctl, mdiosr; 489 int ret; 490 491 priv = netdev_priv(ndev); 492 493 /* write address */ 494 writel((phyid << 8) | regnum, priv->base + AVE_MDIOAR); 495 496 /* read request */ 497 mdioctl = readl(priv->base + AVE_MDIOCTR); 498 writel((mdioctl | AVE_MDIOCTR_RREQ) & ~AVE_MDIOCTR_WREQ, 499 priv->base + AVE_MDIOCTR); 500 501 ret = readl_poll_timeout(priv->base + AVE_MDIOSR, mdiosr, 502 !(mdiosr & AVE_MDIOSR_STS), 20, 2000); 503 if (ret) { 504 netdev_err(ndev, "failed to read (phy:%d reg:%x)\n", 505 phyid, regnum); 506 return ret; 507 } 508 509 return readl(priv->base + AVE_MDIORDR) & GENMASK(15, 0); 510 } 511 512 static int ave_mdiobus_write(struct mii_bus *bus, int phyid, int regnum, 513 u16 val) 514 { 515 struct net_device *ndev = bus->priv; 516 struct ave_private *priv; 517 u32 mdioctl, mdiosr; 518 int ret; 519 520 priv = netdev_priv(ndev); 521 522 /* write address */ 523 writel((phyid << 8) | regnum, priv->base + AVE_MDIOAR); 524 525 /* write data */ 526 writel(val, priv->base + AVE_MDIOWDR); 527 528 /* write request */ 529 mdioctl = readl(priv->base + AVE_MDIOCTR); 530 writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ, 531 priv->base + AVE_MDIOCTR); 532 533 ret = readl_poll_timeout(priv->base + AVE_MDIOSR, mdiosr, 534 !(mdiosr & AVE_MDIOSR_STS), 20, 2000); 535 if (ret) 536 netdev_err(ndev, "failed to write (phy:%d reg:%x)\n", 537 phyid, regnum); 538 539 return ret; 540 } 541 542 static int ave_dma_map(struct net_device *ndev, struct ave_desc *desc, 543 void *ptr, size_t len, enum dma_data_direction dir, 544 dma_addr_t *paddr) 545 { 546 dma_addr_t map_addr; 547 548 map_addr = dma_map_single(ndev->dev.parent, ptr, len, dir); 549 if (unlikely(dma_mapping_error(ndev->dev.parent, map_addr))) 550 return -ENOMEM; 551 552 desc->skbs_dma = map_addr; 553 desc->skbs_dmalen = len; 554 *paddr = map_addr; 555 556 return 0; 557 } 558 559 static void ave_dma_unmap(struct net_device *ndev, struct ave_desc *desc, 560 enum dma_data_direction dir) 561 { 562 if (!desc->skbs_dma) 563 return; 564 565 dma_unmap_single(ndev->dev.parent, 566 desc->skbs_dma, desc->skbs_dmalen, dir); 567 desc->skbs_dma = 0; 568 } 569 570 /* Prepare Rx descriptor and memory */ 571 static int ave_rxdesc_prepare(struct net_device *ndev, int entry) 572 { 573 struct ave_private *priv = netdev_priv(ndev); 574 struct sk_buff *skb; 575 dma_addr_t paddr; 576 int ret; 577 578 skb = priv->rx.desc[entry].skbs; 579 if (!skb) { 580 skb = netdev_alloc_skb(ndev, AVE_MAX_ETHFRAME); 581 if (!skb) { 582 netdev_err(ndev, "can't allocate skb for Rx\n"); 583 return -ENOMEM; 584 } 585 skb->data += AVE_FRAME_HEADROOM; 586 skb->tail += AVE_FRAME_HEADROOM; 587 } 588 589 /* set disable to cmdsts */ 590 ave_desc_write_cmdsts(ndev, AVE_DESCID_RX, entry, 591 AVE_STS_INTR | AVE_STS_OWN); 592 593 /* map Rx buffer 594 * Rx buffer set to the Rx descriptor has two restrictions: 595 * - Rx buffer address is 4 byte aligned. 596 * - Rx buffer begins with 2 byte headroom, and data will be put from 597 * (buffer + 2). 598 * To satisfy this, specify the address to put back the buffer 599 * pointer advanced by AVE_FRAME_HEADROOM, and expand the map size 600 * by AVE_FRAME_HEADROOM. 601 */ 602 ret = ave_dma_map(ndev, &priv->rx.desc[entry], 603 skb->data - AVE_FRAME_HEADROOM, 604 AVE_MAX_ETHFRAME + AVE_FRAME_HEADROOM, 605 DMA_FROM_DEVICE, &paddr); 606 if (ret) { 607 netdev_err(ndev, "can't map skb for Rx\n"); 608 dev_kfree_skb_any(skb); 609 return ret; 610 } 611 priv->rx.desc[entry].skbs = skb; 612 613 /* set buffer pointer */ 614 ave_desc_write_addr(ndev, AVE_DESCID_RX, entry, paddr); 615 616 /* set enable to cmdsts */ 617 ave_desc_write_cmdsts(ndev, AVE_DESCID_RX, entry, 618 AVE_STS_INTR | AVE_MAX_ETHFRAME); 619 620 return ret; 621 } 622 623 /* Switch state of descriptor */ 624 static int ave_desc_switch(struct net_device *ndev, enum desc_state state) 625 { 626 struct ave_private *priv = netdev_priv(ndev); 627 int ret = 0; 628 u32 val; 629 630 switch (state) { 631 case AVE_DESC_START: 632 writel(AVE_DESCC_TD | AVE_DESCC_RD0, priv->base + AVE_DESCC); 633 break; 634 635 case AVE_DESC_STOP: 636 writel(0, priv->base + AVE_DESCC); 637 if (readl_poll_timeout(priv->base + AVE_DESCC, val, !val, 638 150, 15000)) { 639 netdev_err(ndev, "can't stop descriptor\n"); 640 ret = -EBUSY; 641 } 642 break; 643 644 case AVE_DESC_RX_SUSPEND: 645 val = readl(priv->base + AVE_DESCC); 646 val |= AVE_DESCC_RDSTP; 647 val &= ~AVE_DESCC_STATUS_MASK; 648 writel(val, priv->base + AVE_DESCC); 649 if (readl_poll_timeout(priv->base + AVE_DESCC, val, 650 val & (AVE_DESCC_RDSTP << 16), 651 150, 150000)) { 652 netdev_err(ndev, "can't suspend descriptor\n"); 653 ret = -EBUSY; 654 } 655 break; 656 657 case AVE_DESC_RX_PERMIT: 658 val = readl(priv->base + AVE_DESCC); 659 val &= ~AVE_DESCC_RDSTP; 660 val &= ~AVE_DESCC_STATUS_MASK; 661 writel(val, priv->base + AVE_DESCC); 662 break; 663 664 default: 665 ret = -EINVAL; 666 break; 667 } 668 669 return ret; 670 } 671 672 static int ave_tx_complete(struct net_device *ndev) 673 { 674 struct ave_private *priv = netdev_priv(ndev); 675 u32 proc_idx, done_idx, ndesc, cmdsts; 676 unsigned int nr_freebuf = 0; 677 unsigned int tx_packets = 0; 678 unsigned int tx_bytes = 0; 679 680 proc_idx = priv->tx.proc_idx; 681 done_idx = priv->tx.done_idx; 682 ndesc = priv->tx.ndesc; 683 684 /* free pre-stored skb from done_idx to proc_idx */ 685 while (proc_idx != done_idx) { 686 cmdsts = ave_desc_read_cmdsts(ndev, AVE_DESCID_TX, done_idx); 687 688 /* do nothing if owner is HW (==1 for Tx) */ 689 if (cmdsts & AVE_STS_OWN) 690 break; 691 692 /* check Tx status and updates statistics */ 693 if (cmdsts & AVE_STS_OK) { 694 tx_bytes += cmdsts & AVE_STS_PKTLEN_TX_MASK; 695 /* success */ 696 if (cmdsts & AVE_STS_LAST) 697 tx_packets++; 698 } else { 699 /* error */ 700 if (cmdsts & AVE_STS_LAST) { 701 priv->stats_tx.errors++; 702 if (cmdsts & (AVE_STS_OWC | AVE_STS_EC)) 703 priv->stats_tx.collisions++; 704 } 705 } 706 707 /* release skb */ 708 if (priv->tx.desc[done_idx].skbs) { 709 ave_dma_unmap(ndev, &priv->tx.desc[done_idx], 710 DMA_TO_DEVICE); 711 dev_consume_skb_any(priv->tx.desc[done_idx].skbs); 712 priv->tx.desc[done_idx].skbs = NULL; 713 nr_freebuf++; 714 } 715 done_idx = (done_idx + 1) % ndesc; 716 } 717 718 priv->tx.done_idx = done_idx; 719 720 /* update stats */ 721 u64_stats_update_begin(&priv->stats_tx.syncp); 722 priv->stats_tx.packets += tx_packets; 723 priv->stats_tx.bytes += tx_bytes; 724 u64_stats_update_end(&priv->stats_tx.syncp); 725 726 /* wake queue for freeing buffer */ 727 if (unlikely(netif_queue_stopped(ndev)) && nr_freebuf) 728 netif_wake_queue(ndev); 729 730 return nr_freebuf; 731 } 732 733 static int ave_rx_receive(struct net_device *ndev, int num) 734 { 735 struct ave_private *priv = netdev_priv(ndev); 736 unsigned int rx_packets = 0; 737 unsigned int rx_bytes = 0; 738 u32 proc_idx, done_idx; 739 struct sk_buff *skb; 740 unsigned int pktlen; 741 int restpkt, npkts; 742 u32 ndesc, cmdsts; 743 744 proc_idx = priv->rx.proc_idx; 745 done_idx = priv->rx.done_idx; 746 ndesc = priv->rx.ndesc; 747 restpkt = ((proc_idx + ndesc - 1) - done_idx) % ndesc; 748 749 for (npkts = 0; npkts < num; npkts++) { 750 /* we can't receive more packet, so fill desc quickly */ 751 if (--restpkt < 0) 752 break; 753 754 cmdsts = ave_desc_read_cmdsts(ndev, AVE_DESCID_RX, proc_idx); 755 756 /* do nothing if owner is HW (==0 for Rx) */ 757 if (!(cmdsts & AVE_STS_OWN)) 758 break; 759 760 if (!(cmdsts & AVE_STS_OK)) { 761 priv->stats_rx.errors++; 762 proc_idx = (proc_idx + 1) % ndesc; 763 continue; 764 } 765 766 pktlen = cmdsts & AVE_STS_PKTLEN_RX_MASK; 767 768 /* get skbuff for rx */ 769 skb = priv->rx.desc[proc_idx].skbs; 770 priv->rx.desc[proc_idx].skbs = NULL; 771 772 ave_dma_unmap(ndev, &priv->rx.desc[proc_idx], DMA_FROM_DEVICE); 773 774 skb->dev = ndev; 775 skb_put(skb, pktlen); 776 skb->protocol = eth_type_trans(skb, ndev); 777 778 if ((cmdsts & AVE_STS_CSSV) && (!(cmdsts & AVE_STS_CSER))) 779 skb->ip_summed = CHECKSUM_UNNECESSARY; 780 781 rx_packets++; 782 rx_bytes += pktlen; 783 784 netif_receive_skb(skb); 785 786 proc_idx = (proc_idx + 1) % ndesc; 787 } 788 789 priv->rx.proc_idx = proc_idx; 790 791 /* update stats */ 792 u64_stats_update_begin(&priv->stats_rx.syncp); 793 priv->stats_rx.packets += rx_packets; 794 priv->stats_rx.bytes += rx_bytes; 795 u64_stats_update_end(&priv->stats_rx.syncp); 796 797 /* refill the Rx buffers */ 798 while (proc_idx != done_idx) { 799 if (ave_rxdesc_prepare(ndev, done_idx)) 800 break; 801 done_idx = (done_idx + 1) % ndesc; 802 } 803 804 priv->rx.done_idx = done_idx; 805 806 return npkts; 807 } 808 809 static int ave_napi_poll_rx(struct napi_struct *napi, int budget) 810 { 811 struct ave_private *priv; 812 struct net_device *ndev; 813 int num; 814 815 priv = container_of(napi, struct ave_private, napi_rx); 816 ndev = priv->ndev; 817 818 num = ave_rx_receive(ndev, budget); 819 if (num < budget) { 820 napi_complete_done(napi, num); 821 822 /* enable Rx interrupt when NAPI finishes */ 823 ave_irq_enable(ndev, AVE_GI_RXIINT); 824 } 825 826 return num; 827 } 828 829 static int ave_napi_poll_tx(struct napi_struct *napi, int budget) 830 { 831 struct ave_private *priv; 832 struct net_device *ndev; 833 int num; 834 835 priv = container_of(napi, struct ave_private, napi_tx); 836 ndev = priv->ndev; 837 838 num = ave_tx_complete(ndev); 839 napi_complete(napi); 840 841 /* enable Tx interrupt when NAPI finishes */ 842 ave_irq_enable(ndev, AVE_GI_TX); 843 844 return num; 845 } 846 847 static void ave_global_reset(struct net_device *ndev) 848 { 849 struct ave_private *priv = netdev_priv(ndev); 850 u32 val; 851 852 /* set config register */ 853 val = AVE_CFGR_FLE | AVE_CFGR_IPFCEN | AVE_CFGR_CHE; 854 if (!phy_interface_mode_is_rgmii(priv->phy_mode)) 855 val |= AVE_CFGR_MII; 856 writel(val, priv->base + AVE_CFGR); 857 858 /* reset RMII register */ 859 val = readl(priv->base + AVE_RSTCTRL); 860 val &= ~AVE_RSTCTRL_RMIIRST; 861 writel(val, priv->base + AVE_RSTCTRL); 862 863 /* assert reset */ 864 writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->base + AVE_GRR); 865 msleep(20); 866 867 /* 1st, negate PHY reset only */ 868 writel(AVE_GRR_GRST, priv->base + AVE_GRR); 869 msleep(40); 870 871 /* negate reset */ 872 writel(0, priv->base + AVE_GRR); 873 msleep(40); 874 875 /* negate RMII register */ 876 val = readl(priv->base + AVE_RSTCTRL); 877 val |= AVE_RSTCTRL_RMIIRST; 878 writel(val, priv->base + AVE_RSTCTRL); 879 880 ave_irq_disable_all(ndev); 881 } 882 883 static void ave_rxfifo_reset(struct net_device *ndev) 884 { 885 struct ave_private *priv = netdev_priv(ndev); 886 u32 rxcr_org; 887 888 /* save and disable MAC receive op */ 889 rxcr_org = readl(priv->base + AVE_RXCR); 890 writel(rxcr_org & (~AVE_RXCR_RXEN), priv->base + AVE_RXCR); 891 892 /* suspend Rx descriptor */ 893 ave_desc_switch(ndev, AVE_DESC_RX_SUSPEND); 894 895 /* receive all packets before descriptor starts */ 896 ave_rx_receive(ndev, priv->rx.ndesc); 897 898 /* assert reset */ 899 writel(AVE_GRR_RXFFR, priv->base + AVE_GRR); 900 udelay(50); 901 902 /* negate reset */ 903 writel(0, priv->base + AVE_GRR); 904 udelay(20); 905 906 /* negate interrupt status */ 907 writel(AVE_GI_RXOVF, priv->base + AVE_GISR); 908 909 /* permit descriptor */ 910 ave_desc_switch(ndev, AVE_DESC_RX_PERMIT); 911 912 /* restore MAC reccieve op */ 913 writel(rxcr_org, priv->base + AVE_RXCR); 914 } 915 916 static irqreturn_t ave_irq_handler(int irq, void *netdev) 917 { 918 struct net_device *ndev = (struct net_device *)netdev; 919 struct ave_private *priv = netdev_priv(ndev); 920 u32 gimr_val, gisr_val; 921 922 gimr_val = ave_irq_disable_all(ndev); 923 924 /* get interrupt status */ 925 gisr_val = readl(priv->base + AVE_GISR); 926 927 /* PHY */ 928 if (gisr_val & AVE_GI_PHY) 929 writel(AVE_GI_PHY, priv->base + AVE_GISR); 930 931 /* check exceeding packet */ 932 if (gisr_val & AVE_GI_RXERR) { 933 writel(AVE_GI_RXERR, priv->base + AVE_GISR); 934 netdev_err(ndev, "receive a packet exceeding frame buffer\n"); 935 } 936 937 gisr_val &= gimr_val; 938 if (!gisr_val) 939 goto exit_isr; 940 941 /* RxFIFO overflow */ 942 if (gisr_val & AVE_GI_RXOVF) { 943 priv->stats_rx.fifo_errors++; 944 ave_rxfifo_reset(ndev); 945 goto exit_isr; 946 } 947 948 /* Rx drop */ 949 if (gisr_val & AVE_GI_RXDROP) { 950 priv->stats_rx.dropped++; 951 writel(AVE_GI_RXDROP, priv->base + AVE_GISR); 952 } 953 954 /* Rx interval */ 955 if (gisr_val & AVE_GI_RXIINT) { 956 napi_schedule(&priv->napi_rx); 957 /* still force to disable Rx interrupt until NAPI finishes */ 958 gimr_val &= ~AVE_GI_RXIINT; 959 } 960 961 /* Tx completed */ 962 if (gisr_val & AVE_GI_TX) { 963 napi_schedule(&priv->napi_tx); 964 /* still force to disable Tx interrupt until NAPI finishes */ 965 gimr_val &= ~AVE_GI_TX; 966 } 967 968 exit_isr: 969 ave_irq_restore(ndev, gimr_val); 970 971 return IRQ_HANDLED; 972 } 973 974 static int ave_pfsel_start(struct net_device *ndev, unsigned int entry) 975 { 976 struct ave_private *priv = netdev_priv(ndev); 977 u32 val; 978 979 if (WARN_ON(entry > AVE_PF_SIZE)) 980 return -EINVAL; 981 982 val = readl(priv->base + AVE_PFEN); 983 writel(val | BIT(entry), priv->base + AVE_PFEN); 984 985 return 0; 986 } 987 988 static int ave_pfsel_stop(struct net_device *ndev, unsigned int entry) 989 { 990 struct ave_private *priv = netdev_priv(ndev); 991 u32 val; 992 993 if (WARN_ON(entry > AVE_PF_SIZE)) 994 return -EINVAL; 995 996 val = readl(priv->base + AVE_PFEN); 997 writel(val & ~BIT(entry), priv->base + AVE_PFEN); 998 999 return 0; 1000 } 1001 1002 static int ave_pfsel_set_macaddr(struct net_device *ndev, 1003 unsigned int entry, 1004 const unsigned char *mac_addr, 1005 unsigned int set_size) 1006 { 1007 struct ave_private *priv = netdev_priv(ndev); 1008 1009 if (WARN_ON(entry > AVE_PF_SIZE)) 1010 return -EINVAL; 1011 if (WARN_ON(set_size > 6)) 1012 return -EINVAL; 1013 1014 ave_pfsel_stop(ndev, entry); 1015 1016 /* set MAC address for the filter */ 1017 ave_hw_write_macaddr(ndev, mac_addr, 1018 AVE_PKTF(entry), AVE_PKTF(entry) + 4); 1019 1020 /* set byte mask */ 1021 writel(GENMASK(31, set_size) & AVE_PFMBYTE_MASK0, 1022 priv->base + AVE_PFMBYTE(entry)); 1023 writel(AVE_PFMBYTE_MASK1, priv->base + AVE_PFMBYTE(entry) + 4); 1024 1025 /* set bit mask filter */ 1026 writel(AVE_PFMBIT_MASK, priv->base + AVE_PFMBIT(entry)); 1027 1028 /* set selector to ring 0 */ 1029 writel(0, priv->base + AVE_PFSEL(entry)); 1030 1031 /* restart filter */ 1032 ave_pfsel_start(ndev, entry); 1033 1034 return 0; 1035 } 1036 1037 static void ave_pfsel_set_promisc(struct net_device *ndev, 1038 unsigned int entry, u32 rxring) 1039 { 1040 struct ave_private *priv = netdev_priv(ndev); 1041 1042 if (WARN_ON(entry > AVE_PF_SIZE)) 1043 return; 1044 1045 ave_pfsel_stop(ndev, entry); 1046 1047 /* set byte mask */ 1048 writel(AVE_PFMBYTE_MASK0, priv->base + AVE_PFMBYTE(entry)); 1049 writel(AVE_PFMBYTE_MASK1, priv->base + AVE_PFMBYTE(entry) + 4); 1050 1051 /* set bit mask filter */ 1052 writel(AVE_PFMBIT_MASK, priv->base + AVE_PFMBIT(entry)); 1053 1054 /* set selector to rxring */ 1055 writel(rxring, priv->base + AVE_PFSEL(entry)); 1056 1057 ave_pfsel_start(ndev, entry); 1058 } 1059 1060 static void ave_pfsel_init(struct net_device *ndev) 1061 { 1062 unsigned char bcast_mac[ETH_ALEN]; 1063 int i; 1064 1065 eth_broadcast_addr(bcast_mac); 1066 1067 for (i = 0; i < AVE_PF_SIZE; i++) 1068 ave_pfsel_stop(ndev, i); 1069 1070 /* promiscious entry, select ring 0 */ 1071 ave_pfsel_set_promisc(ndev, AVE_PFNUM_FILTER, 0); 1072 1073 /* unicast entry */ 1074 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_UNICAST, ndev->dev_addr, 6); 1075 1076 /* broadcast entry */ 1077 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_BROADCAST, bcast_mac, 6); 1078 } 1079 1080 static void ave_phy_adjust_link(struct net_device *ndev) 1081 { 1082 struct ave_private *priv = netdev_priv(ndev); 1083 struct phy_device *phydev = ndev->phydev; 1084 u32 val, txcr, rxcr, rxcr_org; 1085 u16 rmt_adv = 0, lcl_adv = 0; 1086 u8 cap; 1087 1088 /* set RGMII speed */ 1089 val = readl(priv->base + AVE_TXCR); 1090 val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G); 1091 1092 if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000) 1093 val |= AVE_TXCR_TXSPD_1G; 1094 else if (phydev->speed == SPEED_100) 1095 val |= AVE_TXCR_TXSPD_100; 1096 1097 writel(val, priv->base + AVE_TXCR); 1098 1099 /* set RMII speed (100M/10M only) */ 1100 if (!phy_interface_is_rgmii(phydev)) { 1101 val = readl(priv->base + AVE_LINKSEL); 1102 if (phydev->speed == SPEED_10) 1103 val &= ~AVE_LINKSEL_100M; 1104 else 1105 val |= AVE_LINKSEL_100M; 1106 writel(val, priv->base + AVE_LINKSEL); 1107 } 1108 1109 /* check current RXCR/TXCR */ 1110 rxcr = readl(priv->base + AVE_RXCR); 1111 txcr = readl(priv->base + AVE_TXCR); 1112 rxcr_org = rxcr; 1113 1114 if (phydev->duplex) { 1115 rxcr |= AVE_RXCR_FDUPEN; 1116 1117 if (phydev->pause) 1118 rmt_adv |= LPA_PAUSE_CAP; 1119 if (phydev->asym_pause) 1120 rmt_adv |= LPA_PAUSE_ASYM; 1121 1122 lcl_adv = ethtool_adv_to_lcl_adv_t(phydev->advertising); 1123 cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 1124 if (cap & FLOW_CTRL_TX) 1125 txcr |= AVE_TXCR_FLOCTR; 1126 else 1127 txcr &= ~AVE_TXCR_FLOCTR; 1128 if (cap & FLOW_CTRL_RX) 1129 rxcr |= AVE_RXCR_FLOCTR; 1130 else 1131 rxcr &= ~AVE_RXCR_FLOCTR; 1132 } else { 1133 rxcr &= ~AVE_RXCR_FDUPEN; 1134 rxcr &= ~AVE_RXCR_FLOCTR; 1135 txcr &= ~AVE_TXCR_FLOCTR; 1136 } 1137 1138 if (rxcr_org != rxcr) { 1139 /* disable Rx mac */ 1140 writel(rxcr & ~AVE_RXCR_RXEN, priv->base + AVE_RXCR); 1141 /* change and enable TX/Rx mac */ 1142 writel(txcr, priv->base + AVE_TXCR); 1143 writel(rxcr, priv->base + AVE_RXCR); 1144 } 1145 1146 phy_print_status(phydev); 1147 } 1148 1149 static void ave_macaddr_init(struct net_device *ndev) 1150 { 1151 ave_hw_write_macaddr(ndev, ndev->dev_addr, AVE_RXMAC1R, AVE_RXMAC2R); 1152 1153 /* pfsel unicast entry */ 1154 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_UNICAST, ndev->dev_addr, 6); 1155 } 1156 1157 static int ave_init(struct net_device *ndev) 1158 { 1159 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1160 struct ave_private *priv = netdev_priv(ndev); 1161 struct device *dev = ndev->dev.parent; 1162 struct device_node *np = dev->of_node; 1163 struct device_node *mdio_np; 1164 struct phy_device *phydev; 1165 int nc, nr, ret; 1166 1167 /* enable clk because of hw access until ndo_open */ 1168 for (nc = 0; nc < priv->nclks; nc++) { 1169 ret = clk_prepare_enable(priv->clk[nc]); 1170 if (ret) { 1171 dev_err(dev, "can't enable clock\n"); 1172 goto out_clk_disable; 1173 } 1174 } 1175 1176 for (nr = 0; nr < priv->nrsts; nr++) { 1177 ret = reset_control_deassert(priv->rst[nr]); 1178 if (ret) { 1179 dev_err(dev, "can't deassert reset\n"); 1180 goto out_reset_assert; 1181 } 1182 } 1183 1184 ret = regmap_update_bits(priv->regmap, SG_ETPINMODE, 1185 priv->pinmode_mask, priv->pinmode_val); 1186 if (ret) 1187 return ret; 1188 1189 ave_global_reset(ndev); 1190 1191 mdio_np = of_get_child_by_name(np, "mdio"); 1192 if (!mdio_np) { 1193 dev_err(dev, "mdio node not found\n"); 1194 ret = -EINVAL; 1195 goto out_reset_assert; 1196 } 1197 ret = of_mdiobus_register(priv->mdio, mdio_np); 1198 of_node_put(mdio_np); 1199 if (ret) { 1200 dev_err(dev, "failed to register mdiobus\n"); 1201 goto out_reset_assert; 1202 } 1203 1204 phydev = of_phy_get_and_connect(ndev, np, ave_phy_adjust_link); 1205 if (!phydev) { 1206 dev_err(dev, "could not attach to PHY\n"); 1207 ret = -ENODEV; 1208 goto out_mdio_unregister; 1209 } 1210 1211 priv->phydev = phydev; 1212 1213 phy_ethtool_get_wol(phydev, &wol); 1214 device_set_wakeup_capable(&ndev->dev, !!wol.supported); 1215 1216 if (!phy_interface_is_rgmii(phydev)) 1217 phy_set_max_speed(phydev, SPEED_100); 1218 1219 phy_support_asym_pause(phydev); 1220 1221 phy_attached_info(phydev); 1222 1223 return 0; 1224 1225 out_mdio_unregister: 1226 mdiobus_unregister(priv->mdio); 1227 out_reset_assert: 1228 while (--nr >= 0) 1229 reset_control_assert(priv->rst[nr]); 1230 out_clk_disable: 1231 while (--nc >= 0) 1232 clk_disable_unprepare(priv->clk[nc]); 1233 1234 return ret; 1235 } 1236 1237 static void ave_uninit(struct net_device *ndev) 1238 { 1239 struct ave_private *priv = netdev_priv(ndev); 1240 int i; 1241 1242 phy_disconnect(priv->phydev); 1243 mdiobus_unregister(priv->mdio); 1244 1245 /* disable clk because of hw access after ndo_stop */ 1246 for (i = 0; i < priv->nrsts; i++) 1247 reset_control_assert(priv->rst[i]); 1248 for (i = 0; i < priv->nclks; i++) 1249 clk_disable_unprepare(priv->clk[i]); 1250 } 1251 1252 static int ave_open(struct net_device *ndev) 1253 { 1254 struct ave_private *priv = netdev_priv(ndev); 1255 int entry; 1256 int ret; 1257 u32 val; 1258 1259 ret = request_irq(priv->irq, ave_irq_handler, IRQF_SHARED, ndev->name, 1260 ndev); 1261 if (ret) 1262 return ret; 1263 1264 priv->tx.desc = kcalloc(priv->tx.ndesc, sizeof(*priv->tx.desc), 1265 GFP_KERNEL); 1266 if (!priv->tx.desc) { 1267 ret = -ENOMEM; 1268 goto out_free_irq; 1269 } 1270 1271 priv->rx.desc = kcalloc(priv->rx.ndesc, sizeof(*priv->rx.desc), 1272 GFP_KERNEL); 1273 if (!priv->rx.desc) { 1274 kfree(priv->tx.desc); 1275 ret = -ENOMEM; 1276 goto out_free_irq; 1277 } 1278 1279 /* initialize Tx work and descriptor */ 1280 priv->tx.proc_idx = 0; 1281 priv->tx.done_idx = 0; 1282 for (entry = 0; entry < priv->tx.ndesc; entry++) { 1283 ave_desc_write_cmdsts(ndev, AVE_DESCID_TX, entry, 0); 1284 ave_desc_write_addr(ndev, AVE_DESCID_TX, entry, 0); 1285 } 1286 writel(AVE_TXDC_ADDR_START | 1287 (((priv->tx.ndesc * priv->desc_size) << 16) & AVE_TXDC_SIZE), 1288 priv->base + AVE_TXDC); 1289 1290 /* initialize Rx work and descriptor */ 1291 priv->rx.proc_idx = 0; 1292 priv->rx.done_idx = 0; 1293 for (entry = 0; entry < priv->rx.ndesc; entry++) { 1294 if (ave_rxdesc_prepare(ndev, entry)) 1295 break; 1296 } 1297 writel(AVE_RXDC0_ADDR_START | 1298 (((priv->rx.ndesc * priv->desc_size) << 16) & AVE_RXDC0_SIZE), 1299 priv->base + AVE_RXDC0); 1300 1301 ave_desc_switch(ndev, AVE_DESC_START); 1302 1303 ave_pfsel_init(ndev); 1304 ave_macaddr_init(ndev); 1305 1306 /* set Rx configuration */ 1307 /* full duplex, enable pause drop, enalbe flow control */ 1308 val = AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_DRPEN | 1309 AVE_RXCR_FLOCTR | (AVE_MAX_ETHFRAME & AVE_RXCR_MPSIZ_MASK); 1310 writel(val, priv->base + AVE_RXCR); 1311 1312 /* set Tx configuration */ 1313 /* enable flow control, disable loopback */ 1314 writel(AVE_TXCR_FLOCTR, priv->base + AVE_TXCR); 1315 1316 /* enable timer, clear EN,INTM, and mask interval unit(BSCK) */ 1317 val = readl(priv->base + AVE_IIRQC) & AVE_IIRQC_BSCK; 1318 val |= AVE_IIRQC_EN0 | (AVE_INTM_COUNT << 16); 1319 writel(val, priv->base + AVE_IIRQC); 1320 1321 val = AVE_GI_RXIINT | AVE_GI_RXOVF | AVE_GI_TX | AVE_GI_RXDROP; 1322 ave_irq_restore(ndev, val); 1323 1324 napi_enable(&priv->napi_rx); 1325 napi_enable(&priv->napi_tx); 1326 1327 phy_start(ndev->phydev); 1328 phy_start_aneg(ndev->phydev); 1329 netif_start_queue(ndev); 1330 1331 return 0; 1332 1333 out_free_irq: 1334 disable_irq(priv->irq); 1335 free_irq(priv->irq, ndev); 1336 1337 return ret; 1338 } 1339 1340 static int ave_stop(struct net_device *ndev) 1341 { 1342 struct ave_private *priv = netdev_priv(ndev); 1343 int entry; 1344 1345 ave_irq_disable_all(ndev); 1346 disable_irq(priv->irq); 1347 free_irq(priv->irq, ndev); 1348 1349 netif_tx_disable(ndev); 1350 phy_stop(ndev->phydev); 1351 napi_disable(&priv->napi_tx); 1352 napi_disable(&priv->napi_rx); 1353 1354 ave_desc_switch(ndev, AVE_DESC_STOP); 1355 1356 /* free Tx buffer */ 1357 for (entry = 0; entry < priv->tx.ndesc; entry++) { 1358 if (!priv->tx.desc[entry].skbs) 1359 continue; 1360 1361 ave_dma_unmap(ndev, &priv->tx.desc[entry], DMA_TO_DEVICE); 1362 dev_kfree_skb_any(priv->tx.desc[entry].skbs); 1363 priv->tx.desc[entry].skbs = NULL; 1364 } 1365 priv->tx.proc_idx = 0; 1366 priv->tx.done_idx = 0; 1367 1368 /* free Rx buffer */ 1369 for (entry = 0; entry < priv->rx.ndesc; entry++) { 1370 if (!priv->rx.desc[entry].skbs) 1371 continue; 1372 1373 ave_dma_unmap(ndev, &priv->rx.desc[entry], DMA_FROM_DEVICE); 1374 dev_kfree_skb_any(priv->rx.desc[entry].skbs); 1375 priv->rx.desc[entry].skbs = NULL; 1376 } 1377 priv->rx.proc_idx = 0; 1378 priv->rx.done_idx = 0; 1379 1380 kfree(priv->tx.desc); 1381 kfree(priv->rx.desc); 1382 1383 return 0; 1384 } 1385 1386 static int ave_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1387 { 1388 struct ave_private *priv = netdev_priv(ndev); 1389 u32 proc_idx, done_idx, ndesc, cmdsts; 1390 int ret, freepkt; 1391 dma_addr_t paddr; 1392 1393 proc_idx = priv->tx.proc_idx; 1394 done_idx = priv->tx.done_idx; 1395 ndesc = priv->tx.ndesc; 1396 freepkt = ((done_idx + ndesc - 1) - proc_idx) % ndesc; 1397 1398 /* stop queue when not enough entry */ 1399 if (unlikely(freepkt < 1)) { 1400 netif_stop_queue(ndev); 1401 return NETDEV_TX_BUSY; 1402 } 1403 1404 /* add padding for short packet */ 1405 if (skb_put_padto(skb, ETH_ZLEN)) { 1406 priv->stats_tx.dropped++; 1407 return NETDEV_TX_OK; 1408 } 1409 1410 /* map Tx buffer 1411 * Tx buffer set to the Tx descriptor doesn't have any restriction. 1412 */ 1413 ret = ave_dma_map(ndev, &priv->tx.desc[proc_idx], 1414 skb->data, skb->len, DMA_TO_DEVICE, &paddr); 1415 if (ret) { 1416 dev_kfree_skb_any(skb); 1417 priv->stats_tx.dropped++; 1418 return NETDEV_TX_OK; 1419 } 1420 1421 priv->tx.desc[proc_idx].skbs = skb; 1422 1423 ave_desc_write_addr(ndev, AVE_DESCID_TX, proc_idx, paddr); 1424 1425 cmdsts = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST | 1426 (skb->len & AVE_STS_PKTLEN_TX_MASK); 1427 1428 /* set interrupt per AVE_FORCE_TXINTCNT or when queue is stopped */ 1429 if (!(proc_idx % AVE_FORCE_TXINTCNT) || netif_queue_stopped(ndev)) 1430 cmdsts |= AVE_STS_INTR; 1431 1432 /* disable checksum calculation when skb doesn't calurate checksum */ 1433 if (skb->ip_summed == CHECKSUM_NONE || 1434 skb->ip_summed == CHECKSUM_UNNECESSARY) 1435 cmdsts |= AVE_STS_NOCSUM; 1436 1437 ave_desc_write_cmdsts(ndev, AVE_DESCID_TX, proc_idx, cmdsts); 1438 1439 priv->tx.proc_idx = (proc_idx + 1) % ndesc; 1440 1441 return NETDEV_TX_OK; 1442 } 1443 1444 static int ave_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) 1445 { 1446 return phy_mii_ioctl(ndev->phydev, ifr, cmd); 1447 } 1448 1449 static const u8 v4multi_macadr[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 1450 static const u8 v6multi_macadr[] = { 0x33, 0x00, 0x00, 0x00, 0x00, 0x00 }; 1451 1452 static void ave_set_rx_mode(struct net_device *ndev) 1453 { 1454 struct ave_private *priv = netdev_priv(ndev); 1455 struct netdev_hw_addr *hw_adr; 1456 int count, mc_cnt; 1457 u32 val; 1458 1459 /* MAC addr filter enable for promiscious mode */ 1460 mc_cnt = netdev_mc_count(ndev); 1461 val = readl(priv->base + AVE_RXCR); 1462 if (ndev->flags & IFF_PROMISC || !mc_cnt) 1463 val &= ~AVE_RXCR_AFEN; 1464 else 1465 val |= AVE_RXCR_AFEN; 1466 writel(val, priv->base + AVE_RXCR); 1467 1468 /* set all multicast address */ 1469 if ((ndev->flags & IFF_ALLMULTI) || mc_cnt > AVE_PF_MULTICAST_SIZE) { 1470 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_MULTICAST, 1471 v4multi_macadr, 1); 1472 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_MULTICAST + 1, 1473 v6multi_macadr, 1); 1474 } else { 1475 /* stop all multicast filter */ 1476 for (count = 0; count < AVE_PF_MULTICAST_SIZE; count++) 1477 ave_pfsel_stop(ndev, AVE_PFNUM_MULTICAST + count); 1478 1479 /* set multicast addresses */ 1480 count = 0; 1481 netdev_for_each_mc_addr(hw_adr, ndev) { 1482 if (count == mc_cnt) 1483 break; 1484 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_MULTICAST + count, 1485 hw_adr->addr, 6); 1486 count++; 1487 } 1488 } 1489 } 1490 1491 static void ave_get_stats64(struct net_device *ndev, 1492 struct rtnl_link_stats64 *stats) 1493 { 1494 struct ave_private *priv = netdev_priv(ndev); 1495 unsigned int start; 1496 1497 do { 1498 start = u64_stats_fetch_begin_irq(&priv->stats_rx.syncp); 1499 stats->rx_packets = priv->stats_rx.packets; 1500 stats->rx_bytes = priv->stats_rx.bytes; 1501 } while (u64_stats_fetch_retry_irq(&priv->stats_rx.syncp, start)); 1502 1503 do { 1504 start = u64_stats_fetch_begin_irq(&priv->stats_tx.syncp); 1505 stats->tx_packets = priv->stats_tx.packets; 1506 stats->tx_bytes = priv->stats_tx.bytes; 1507 } while (u64_stats_fetch_retry_irq(&priv->stats_tx.syncp, start)); 1508 1509 stats->rx_errors = priv->stats_rx.errors; 1510 stats->tx_errors = priv->stats_tx.errors; 1511 stats->rx_dropped = priv->stats_rx.dropped; 1512 stats->tx_dropped = priv->stats_tx.dropped; 1513 stats->rx_fifo_errors = priv->stats_rx.fifo_errors; 1514 stats->collisions = priv->stats_tx.collisions; 1515 } 1516 1517 static int ave_set_mac_address(struct net_device *ndev, void *p) 1518 { 1519 int ret = eth_mac_addr(ndev, p); 1520 1521 if (ret) 1522 return ret; 1523 1524 ave_macaddr_init(ndev); 1525 1526 return 0; 1527 } 1528 1529 static const struct net_device_ops ave_netdev_ops = { 1530 .ndo_init = ave_init, 1531 .ndo_uninit = ave_uninit, 1532 .ndo_open = ave_open, 1533 .ndo_stop = ave_stop, 1534 .ndo_start_xmit = ave_start_xmit, 1535 .ndo_do_ioctl = ave_ioctl, 1536 .ndo_set_rx_mode = ave_set_rx_mode, 1537 .ndo_get_stats64 = ave_get_stats64, 1538 .ndo_set_mac_address = ave_set_mac_address, 1539 }; 1540 1541 static int ave_probe(struct platform_device *pdev) 1542 { 1543 const struct ave_soc_data *data; 1544 struct device *dev = &pdev->dev; 1545 char buf[ETHTOOL_FWVERS_LEN]; 1546 struct of_phandle_args args; 1547 phy_interface_t phy_mode; 1548 struct ave_private *priv; 1549 struct net_device *ndev; 1550 struct device_node *np; 1551 struct resource *res; 1552 const void *mac_addr; 1553 void __iomem *base; 1554 const char *name; 1555 int i, irq, ret; 1556 u64 dma_mask; 1557 u32 ave_id; 1558 1559 data = of_device_get_match_data(dev); 1560 if (WARN_ON(!data)) 1561 return -EINVAL; 1562 1563 np = dev->of_node; 1564 phy_mode = of_get_phy_mode(np); 1565 if (phy_mode < 0) { 1566 dev_err(dev, "phy-mode not found\n"); 1567 return -EINVAL; 1568 } 1569 1570 irq = platform_get_irq(pdev, 0); 1571 if (irq < 0) { 1572 dev_err(dev, "IRQ not found\n"); 1573 return irq; 1574 } 1575 1576 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1577 base = devm_ioremap_resource(dev, res); 1578 if (IS_ERR(base)) 1579 return PTR_ERR(base); 1580 1581 ndev = alloc_etherdev(sizeof(struct ave_private)); 1582 if (!ndev) { 1583 dev_err(dev, "can't allocate ethernet device\n"); 1584 return -ENOMEM; 1585 } 1586 1587 ndev->netdev_ops = &ave_netdev_ops; 1588 ndev->ethtool_ops = &ave_ethtool_ops; 1589 SET_NETDEV_DEV(ndev, dev); 1590 1591 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_RXCSUM); 1592 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_RXCSUM); 1593 1594 ndev->max_mtu = AVE_MAX_ETHFRAME - (ETH_HLEN + ETH_FCS_LEN); 1595 1596 mac_addr = of_get_mac_address(np); 1597 if (mac_addr) 1598 ether_addr_copy(ndev->dev_addr, mac_addr); 1599 1600 /* if the mac address is invalid, use random mac address */ 1601 if (!is_valid_ether_addr(ndev->dev_addr)) { 1602 eth_hw_addr_random(ndev); 1603 dev_warn(dev, "Using random MAC address: %pM\n", 1604 ndev->dev_addr); 1605 } 1606 1607 priv = netdev_priv(ndev); 1608 priv->base = base; 1609 priv->irq = irq; 1610 priv->ndev = ndev; 1611 priv->msg_enable = netif_msg_init(-1, AVE_DEFAULT_MSG_ENABLE); 1612 priv->phy_mode = phy_mode; 1613 priv->data = data; 1614 1615 if (IS_DESC_64BIT(priv)) { 1616 priv->desc_size = AVE_DESC_SIZE_64; 1617 priv->tx.daddr = AVE_TXDM_64; 1618 priv->rx.daddr = AVE_RXDM_64; 1619 dma_mask = DMA_BIT_MASK(64); 1620 } else { 1621 priv->desc_size = AVE_DESC_SIZE_32; 1622 priv->tx.daddr = AVE_TXDM_32; 1623 priv->rx.daddr = AVE_RXDM_32; 1624 dma_mask = DMA_BIT_MASK(32); 1625 } 1626 ret = dma_set_mask(dev, dma_mask); 1627 if (ret) 1628 goto out_free_netdev; 1629 1630 priv->tx.ndesc = AVE_NR_TXDESC; 1631 priv->rx.ndesc = AVE_NR_RXDESC; 1632 1633 u64_stats_init(&priv->stats_tx.syncp); 1634 u64_stats_init(&priv->stats_rx.syncp); 1635 1636 for (i = 0; i < AVE_MAX_CLKS; i++) { 1637 name = priv->data->clock_names[i]; 1638 if (!name) 1639 break; 1640 priv->clk[i] = devm_clk_get(dev, name); 1641 if (IS_ERR(priv->clk[i])) { 1642 ret = PTR_ERR(priv->clk[i]); 1643 goto out_free_netdev; 1644 } 1645 priv->nclks++; 1646 } 1647 1648 for (i = 0; i < AVE_MAX_RSTS; i++) { 1649 name = priv->data->reset_names[i]; 1650 if (!name) 1651 break; 1652 priv->rst[i] = devm_reset_control_get_shared(dev, name); 1653 if (IS_ERR(priv->rst[i])) { 1654 ret = PTR_ERR(priv->rst[i]); 1655 goto out_free_netdev; 1656 } 1657 priv->nrsts++; 1658 } 1659 1660 ret = of_parse_phandle_with_fixed_args(np, 1661 "socionext,syscon-phy-mode", 1662 1, 0, &args); 1663 if (ret) { 1664 netdev_err(ndev, "can't get syscon-phy-mode property\n"); 1665 goto out_free_netdev; 1666 } 1667 priv->regmap = syscon_node_to_regmap(args.np); 1668 of_node_put(args.np); 1669 if (IS_ERR(priv->regmap)) { 1670 netdev_err(ndev, "can't map syscon-phy-mode\n"); 1671 ret = PTR_ERR(priv->regmap); 1672 goto out_free_netdev; 1673 } 1674 ret = priv->data->get_pinmode(priv, phy_mode, args.args[0]); 1675 if (ret) { 1676 netdev_err(ndev, "invalid phy-mode setting\n"); 1677 goto out_free_netdev; 1678 } 1679 1680 priv->mdio = devm_mdiobus_alloc(dev); 1681 if (!priv->mdio) { 1682 ret = -ENOMEM; 1683 goto out_free_netdev; 1684 } 1685 priv->mdio->priv = ndev; 1686 priv->mdio->parent = dev; 1687 priv->mdio->read = ave_mdiobus_read; 1688 priv->mdio->write = ave_mdiobus_write; 1689 priv->mdio->name = "uniphier-mdio"; 1690 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%x", 1691 pdev->name, pdev->id); 1692 1693 /* Register as a NAPI supported driver */ 1694 netif_napi_add(ndev, &priv->napi_rx, ave_napi_poll_rx, 1695 NAPI_POLL_WEIGHT); 1696 netif_tx_napi_add(ndev, &priv->napi_tx, ave_napi_poll_tx, 1697 NAPI_POLL_WEIGHT); 1698 1699 platform_set_drvdata(pdev, ndev); 1700 1701 ret = register_netdev(ndev); 1702 if (ret) { 1703 dev_err(dev, "failed to register netdevice\n"); 1704 goto out_del_napi; 1705 } 1706 1707 /* get ID and version */ 1708 ave_id = readl(priv->base + AVE_IDR); 1709 ave_hw_read_version(ndev, buf, sizeof(buf)); 1710 1711 dev_info(dev, "Socionext %c%c%c%c Ethernet IP %s (irq=%d, phy=%s)\n", 1712 (ave_id >> 24) & 0xff, (ave_id >> 16) & 0xff, 1713 (ave_id >> 8) & 0xff, (ave_id >> 0) & 0xff, 1714 buf, priv->irq, phy_modes(phy_mode)); 1715 1716 return 0; 1717 1718 out_del_napi: 1719 netif_napi_del(&priv->napi_rx); 1720 netif_napi_del(&priv->napi_tx); 1721 out_free_netdev: 1722 free_netdev(ndev); 1723 1724 return ret; 1725 } 1726 1727 static int ave_remove(struct platform_device *pdev) 1728 { 1729 struct net_device *ndev = platform_get_drvdata(pdev); 1730 struct ave_private *priv = netdev_priv(ndev); 1731 1732 unregister_netdev(ndev); 1733 netif_napi_del(&priv->napi_rx); 1734 netif_napi_del(&priv->napi_tx); 1735 free_netdev(ndev); 1736 1737 return 0; 1738 } 1739 1740 static int ave_pro4_get_pinmode(struct ave_private *priv, 1741 phy_interface_t phy_mode, u32 arg) 1742 { 1743 if (arg > 0) 1744 return -EINVAL; 1745 1746 priv->pinmode_mask = SG_ETPINMODE_RMII(0); 1747 1748 switch (phy_mode) { 1749 case PHY_INTERFACE_MODE_RMII: 1750 priv->pinmode_val = SG_ETPINMODE_RMII(0); 1751 break; 1752 case PHY_INTERFACE_MODE_MII: 1753 case PHY_INTERFACE_MODE_RGMII: 1754 priv->pinmode_val = 0; 1755 break; 1756 default: 1757 return -EINVAL; 1758 } 1759 1760 return 0; 1761 } 1762 1763 static int ave_ld11_get_pinmode(struct ave_private *priv, 1764 phy_interface_t phy_mode, u32 arg) 1765 { 1766 if (arg > 0) 1767 return -EINVAL; 1768 1769 priv->pinmode_mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); 1770 1771 switch (phy_mode) { 1772 case PHY_INTERFACE_MODE_INTERNAL: 1773 priv->pinmode_val = 0; 1774 break; 1775 case PHY_INTERFACE_MODE_RMII: 1776 priv->pinmode_val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); 1777 break; 1778 default: 1779 return -EINVAL; 1780 } 1781 1782 return 0; 1783 } 1784 1785 static int ave_ld20_get_pinmode(struct ave_private *priv, 1786 phy_interface_t phy_mode, u32 arg) 1787 { 1788 if (arg > 0) 1789 return -EINVAL; 1790 1791 priv->pinmode_mask = SG_ETPINMODE_RMII(0); 1792 1793 switch (phy_mode) { 1794 case PHY_INTERFACE_MODE_RMII: 1795 priv->pinmode_val = SG_ETPINMODE_RMII(0); 1796 break; 1797 case PHY_INTERFACE_MODE_RGMII: 1798 priv->pinmode_val = 0; 1799 break; 1800 default: 1801 return -EINVAL; 1802 } 1803 1804 return 0; 1805 } 1806 1807 static int ave_pxs3_get_pinmode(struct ave_private *priv, 1808 phy_interface_t phy_mode, u32 arg) 1809 { 1810 if (arg > 1) 1811 return -EINVAL; 1812 1813 priv->pinmode_mask = SG_ETPINMODE_RMII(arg); 1814 1815 switch (phy_mode) { 1816 case PHY_INTERFACE_MODE_RMII: 1817 priv->pinmode_val = SG_ETPINMODE_RMII(arg); 1818 break; 1819 case PHY_INTERFACE_MODE_RGMII: 1820 priv->pinmode_val = 0; 1821 break; 1822 default: 1823 return -EINVAL; 1824 } 1825 1826 return 0; 1827 } 1828 1829 static const struct ave_soc_data ave_pro4_data = { 1830 .is_desc_64bit = false, 1831 .clock_names = { 1832 "gio", "ether", "ether-gb", "ether-phy", 1833 }, 1834 .reset_names = { 1835 "gio", "ether", 1836 }, 1837 .get_pinmode = ave_pro4_get_pinmode, 1838 }; 1839 1840 static const struct ave_soc_data ave_pxs2_data = { 1841 .is_desc_64bit = false, 1842 .clock_names = { 1843 "ether", 1844 }, 1845 .reset_names = { 1846 "ether", 1847 }, 1848 .get_pinmode = ave_pro4_get_pinmode, 1849 }; 1850 1851 static const struct ave_soc_data ave_ld11_data = { 1852 .is_desc_64bit = false, 1853 .clock_names = { 1854 "ether", 1855 }, 1856 .reset_names = { 1857 "ether", 1858 }, 1859 .get_pinmode = ave_ld11_get_pinmode, 1860 }; 1861 1862 static const struct ave_soc_data ave_ld20_data = { 1863 .is_desc_64bit = true, 1864 .clock_names = { 1865 "ether", 1866 }, 1867 .reset_names = { 1868 "ether", 1869 }, 1870 .get_pinmode = ave_ld20_get_pinmode, 1871 }; 1872 1873 static const struct ave_soc_data ave_pxs3_data = { 1874 .is_desc_64bit = false, 1875 .clock_names = { 1876 "ether", 1877 }, 1878 .reset_names = { 1879 "ether", 1880 }, 1881 .get_pinmode = ave_pxs3_get_pinmode, 1882 }; 1883 1884 static const struct of_device_id of_ave_match[] = { 1885 { 1886 .compatible = "socionext,uniphier-pro4-ave4", 1887 .data = &ave_pro4_data, 1888 }, 1889 { 1890 .compatible = "socionext,uniphier-pxs2-ave4", 1891 .data = &ave_pxs2_data, 1892 }, 1893 { 1894 .compatible = "socionext,uniphier-ld11-ave4", 1895 .data = &ave_ld11_data, 1896 }, 1897 { 1898 .compatible = "socionext,uniphier-ld20-ave4", 1899 .data = &ave_ld20_data, 1900 }, 1901 { 1902 .compatible = "socionext,uniphier-pxs3-ave4", 1903 .data = &ave_pxs3_data, 1904 }, 1905 { /* Sentinel */ } 1906 }; 1907 MODULE_DEVICE_TABLE(of, of_ave_match); 1908 1909 static struct platform_driver ave_driver = { 1910 .probe = ave_probe, 1911 .remove = ave_remove, 1912 .driver = { 1913 .name = "ave", 1914 .of_match_table = of_ave_match, 1915 }, 1916 }; 1917 module_platform_driver(ave_driver); 1918 1919 MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>"); 1920 MODULE_DESCRIPTION("Socionext UniPhier AVE ethernet driver"); 1921 MODULE_LICENSE("GPL v2"); 1922