1 // SPDX-License-Identifier: GPL-2.0+ 2 3 #include <linux/types.h> 4 #include <linux/clk.h> 5 #include <linux/platform_device.h> 6 #include <linux/pm_runtime.h> 7 #include <linux/acpi.h> 8 #include <linux/of_mdio.h> 9 #include <linux/of_net.h> 10 #include <linux/etherdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/netlink.h> 14 #include <linux/bpf.h> 15 #include <linux/bpf_trace.h> 16 17 #include <net/tcp.h> 18 #include <net/page_pool.h> 19 #include <net/ip6_checksum.h> 20 21 #define NETSEC_REG_SOFT_RST 0x104 22 #define NETSEC_REG_COM_INIT 0x120 23 24 #define NETSEC_REG_TOP_STATUS 0x200 25 #define NETSEC_IRQ_RX BIT(1) 26 #define NETSEC_IRQ_TX BIT(0) 27 28 #define NETSEC_REG_TOP_INTEN 0x204 29 #define NETSEC_REG_INTEN_SET 0x234 30 #define NETSEC_REG_INTEN_CLR 0x238 31 32 #define NETSEC_REG_NRM_TX_STATUS 0x400 33 #define NETSEC_REG_NRM_TX_INTEN 0x404 34 #define NETSEC_REG_NRM_TX_INTEN_SET 0x428 35 #define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c 36 #define NRM_TX_ST_NTOWNR BIT(17) 37 #define NRM_TX_ST_TR_ERR BIT(16) 38 #define NRM_TX_ST_TXDONE BIT(15) 39 #define NRM_TX_ST_TMREXP BIT(14) 40 41 #define NETSEC_REG_NRM_RX_STATUS 0x440 42 #define NETSEC_REG_NRM_RX_INTEN 0x444 43 #define NETSEC_REG_NRM_RX_INTEN_SET 0x468 44 #define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c 45 #define NRM_RX_ST_RC_ERR BIT(16) 46 #define NRM_RX_ST_PKTCNT BIT(15) 47 #define NRM_RX_ST_TMREXP BIT(14) 48 49 #define NETSEC_REG_PKT_CMD_BUF 0xd0 50 51 #define NETSEC_REG_CLK_EN 0x100 52 53 #define NETSEC_REG_PKT_CTRL 0x140 54 55 #define NETSEC_REG_DMA_TMR_CTRL 0x20c 56 #define NETSEC_REG_F_TAIKI_MC_VER 0x22c 57 #define NETSEC_REG_F_TAIKI_VER 0x230 58 #define NETSEC_REG_DMA_HM_CTRL 0x214 59 #define NETSEC_REG_DMA_MH_CTRL 0x220 60 #define NETSEC_REG_ADDR_DIS_CORE 0x218 61 #define NETSEC_REG_DMAC_HM_CMD_BUF 0x210 62 #define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c 63 64 #define NETSEC_REG_NRM_TX_PKTCNT 0x410 65 66 #define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414 67 #define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418 68 69 #define NETSEC_REG_NRM_TX_TMR 0x41c 70 71 #define NETSEC_REG_NRM_RX_PKTCNT 0x454 72 #define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458 73 #define NETSEC_REG_NRM_TX_TXINT_TMR 0x420 74 #define NETSEC_REG_NRM_RX_RXINT_TMR 0x460 75 76 #define NETSEC_REG_NRM_RX_TMR 0x45c 77 78 #define NETSEC_REG_NRM_TX_DESC_START_UP 0x434 79 #define NETSEC_REG_NRM_TX_DESC_START_LW 0x408 80 #define NETSEC_REG_NRM_RX_DESC_START_UP 0x474 81 #define NETSEC_REG_NRM_RX_DESC_START_LW 0x448 82 83 #define NETSEC_REG_NRM_TX_CONFIG 0x430 84 #define NETSEC_REG_NRM_RX_CONFIG 0x470 85 86 #define MAC_REG_STATUS 0x1024 87 #define MAC_REG_DATA 0x11c0 88 #define MAC_REG_CMD 0x11c4 89 #define MAC_REG_FLOW_TH 0x11cc 90 #define MAC_REG_INTF_SEL 0x11d4 91 #define MAC_REG_DESC_INIT 0x11fc 92 #define MAC_REG_DESC_SOFT_RST 0x1204 93 #define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500 94 95 #define GMAC_REG_MCR 0x0000 96 #define GMAC_REG_MFFR 0x0004 97 #define GMAC_REG_GAR 0x0010 98 #define GMAC_REG_GDR 0x0014 99 #define GMAC_REG_FCR 0x0018 100 #define GMAC_REG_BMR 0x1000 101 #define GMAC_REG_RDLAR 0x100c 102 #define GMAC_REG_TDLAR 0x1010 103 #define GMAC_REG_OMR 0x1018 104 105 #define MHZ(n) ((n) * 1000 * 1000) 106 107 #define NETSEC_TX_SHIFT_OWN_FIELD 31 108 #define NETSEC_TX_SHIFT_LD_FIELD 30 109 #define NETSEC_TX_SHIFT_DRID_FIELD 24 110 #define NETSEC_TX_SHIFT_PT_FIELD 21 111 #define NETSEC_TX_SHIFT_TDRID_FIELD 16 112 #define NETSEC_TX_SHIFT_CC_FIELD 15 113 #define NETSEC_TX_SHIFT_FS_FIELD 9 114 #define NETSEC_TX_LAST 8 115 #define NETSEC_TX_SHIFT_CO 7 116 #define NETSEC_TX_SHIFT_SO 6 117 #define NETSEC_TX_SHIFT_TRS_FIELD 4 118 119 #define NETSEC_RX_PKT_OWN_FIELD 31 120 #define NETSEC_RX_PKT_LD_FIELD 30 121 #define NETSEC_RX_PKT_SDRID_FIELD 24 122 #define NETSEC_RX_PKT_FR_FIELD 23 123 #define NETSEC_RX_PKT_ER_FIELD 21 124 #define NETSEC_RX_PKT_ERR_FIELD 16 125 #define NETSEC_RX_PKT_TDRID_FIELD 12 126 #define NETSEC_RX_PKT_FS_FIELD 9 127 #define NETSEC_RX_PKT_LS_FIELD 8 128 #define NETSEC_RX_PKT_CO_FIELD 6 129 130 #define NETSEC_RX_PKT_ERR_MASK 3 131 132 #define NETSEC_MAX_TX_PKT_LEN 1518 133 #define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018 134 135 #define NETSEC_RING_GMAC 15 136 #define NETSEC_RING_MAX 2 137 138 #define NETSEC_TCP_SEG_LEN_MAX 1460 139 #define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960 140 141 #define NETSEC_RX_CKSUM_NOTAVAIL 0 142 #define NETSEC_RX_CKSUM_OK 1 143 #define NETSEC_RX_CKSUM_NG 2 144 145 #define NETSEC_TOP_IRQ_REG_CODE_LOAD_END BIT(20) 146 #define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4) 147 148 #define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20) 149 #define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19) 150 151 #define NETSEC_INT_PKTCNT_MAX 2047 152 153 #define NETSEC_FLOW_START_TH_MAX 95 154 #define NETSEC_FLOW_STOP_TH_MAX 95 155 #define NETSEC_FLOW_PAUSE_TIME_MIN 5 156 157 #define NETSEC_CLK_EN_REG_DOM_ALL 0x3f 158 159 #define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28) 160 #define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27) 161 #define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3) 162 #define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2) 163 #define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1) 164 #define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0) 165 166 #define NETSEC_CLK_EN_REG_DOM_G BIT(5) 167 #define NETSEC_CLK_EN_REG_DOM_C BIT(1) 168 #define NETSEC_CLK_EN_REG_DOM_D BIT(0) 169 170 #define NETSEC_COM_INIT_REG_DB BIT(2) 171 #define NETSEC_COM_INIT_REG_CLS BIT(1) 172 #define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \ 173 NETSEC_COM_INIT_REG_DB) 174 175 #define NETSEC_SOFT_RST_REG_RESET 0 176 #define NETSEC_SOFT_RST_REG_RUN BIT(31) 177 178 #define NETSEC_DMA_CTRL_REG_STOP 1 179 #define MH_CTRL__MODE_TRANS BIT(20) 180 181 #define NETSEC_GMAC_CMD_ST_READ 0 182 #define NETSEC_GMAC_CMD_ST_WRITE BIT(28) 183 #define NETSEC_GMAC_CMD_ST_BUSY BIT(31) 184 185 #define NETSEC_GMAC_BMR_REG_COMMON 0x00412080 186 #define NETSEC_GMAC_BMR_REG_RESET 0x00020181 187 #define NETSEC_GMAC_BMR_REG_SWR 0x00000001 188 189 #define NETSEC_GMAC_OMR_REG_ST BIT(13) 190 #define NETSEC_GMAC_OMR_REG_SR BIT(1) 191 192 #define NETSEC_GMAC_MCR_REG_IBN BIT(30) 193 #define NETSEC_GMAC_MCR_REG_CST BIT(25) 194 #define NETSEC_GMAC_MCR_REG_JE BIT(20) 195 #define NETSEC_MCR_PS BIT(15) 196 #define NETSEC_GMAC_MCR_REG_FES BIT(14) 197 #define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c 198 #define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c 199 200 #define NETSEC_FCR_RFE BIT(2) 201 #define NETSEC_FCR_TFE BIT(1) 202 203 #define NETSEC_GMAC_GAR_REG_GW BIT(1) 204 #define NETSEC_GMAC_GAR_REG_GB BIT(0) 205 206 #define NETSEC_GMAC_GAR_REG_SHIFT_PA 11 207 #define NETSEC_GMAC_GAR_REG_SHIFT_GR 6 208 #define GMAC_REG_SHIFT_CR_GAR 2 209 210 #define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2 211 #define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3 212 #define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0 213 #define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1 214 #define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4 215 #define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5 216 217 #define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000 218 #define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000 219 220 #define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000 221 222 #define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31) 223 #define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30) 224 #define NETSEC_REG_DESC_TMR_MODE 4 225 #define NETSEC_REG_DESC_ENDIAN 0 226 227 #define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1 228 #define NETSEC_MAC_DESC_INIT_REG_INIT 1 229 230 #define NETSEC_EEPROM_MAC_ADDRESS 0x00 231 #define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08 232 #define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C 233 #define NETSEC_EEPROM_HM_ME_SIZE 0x10 234 #define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14 235 #define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18 236 #define NETSEC_EEPROM_MH_ME_SIZE 0x1C 237 #define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20 238 #define NETSEC_EEPROM_PKT_ME_SIZE 0x24 239 240 #define DESC_NUM 256 241 242 #define NETSEC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 243 #define NETSEC_RXBUF_HEADROOM (max(XDP_PACKET_HEADROOM, NET_SKB_PAD) + \ 244 NET_IP_ALIGN) 245 #define NETSEC_RX_BUF_NON_DATA (NETSEC_RXBUF_HEADROOM + \ 246 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 247 #define NETSEC_RX_BUF_SIZE (PAGE_SIZE - NETSEC_RX_BUF_NON_DATA) 248 249 #define DESC_SZ sizeof(struct netsec_de) 250 251 #define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000) 252 253 #define NETSEC_XDP_PASS 0 254 #define NETSEC_XDP_CONSUMED BIT(0) 255 #define NETSEC_XDP_TX BIT(1) 256 #define NETSEC_XDP_REDIR BIT(2) 257 258 enum ring_id { 259 NETSEC_RING_TX = 0, 260 NETSEC_RING_RX 261 }; 262 263 enum buf_type { 264 TYPE_NETSEC_SKB = 0, 265 TYPE_NETSEC_XDP_TX, 266 TYPE_NETSEC_XDP_NDO, 267 }; 268 269 struct netsec_desc { 270 union { 271 struct sk_buff *skb; 272 struct xdp_frame *xdpf; 273 }; 274 dma_addr_t dma_addr; 275 void *addr; 276 u16 len; 277 u8 buf_type; 278 }; 279 280 struct netsec_desc_ring { 281 dma_addr_t desc_dma; 282 struct netsec_desc *desc; 283 void *vaddr; 284 u16 head, tail; 285 u16 xdp_xmit; /* netsec_xdp_xmit packets */ 286 struct page_pool *page_pool; 287 struct xdp_rxq_info xdp_rxq; 288 spinlock_t lock; /* XDP tx queue locking */ 289 }; 290 291 struct netsec_priv { 292 struct netsec_desc_ring desc_ring[NETSEC_RING_MAX]; 293 struct ethtool_coalesce et_coalesce; 294 struct bpf_prog *xdp_prog; 295 spinlock_t reglock; /* protect reg access */ 296 struct napi_struct napi; 297 phy_interface_t phy_interface; 298 struct net_device *ndev; 299 struct device_node *phy_np; 300 struct phy_device *phydev; 301 struct mii_bus *mii_bus; 302 void __iomem *ioaddr; 303 void __iomem *eeprom_base; 304 struct device *dev; 305 struct clk *clk; 306 u32 msg_enable; 307 u32 freq; 308 u32 phy_addr; 309 bool rx_cksum_offload_flag; 310 }; 311 312 struct netsec_de { /* Netsec Descriptor layout */ 313 u32 attr; 314 u32 data_buf_addr_up; 315 u32 data_buf_addr_lw; 316 u32 buf_len_info; 317 }; 318 319 struct netsec_tx_pkt_ctrl { 320 u16 tcp_seg_len; 321 bool tcp_seg_offload_flag; 322 bool cksum_offload_flag; 323 }; 324 325 struct netsec_rx_pkt_info { 326 int rx_cksum_result; 327 int err_code; 328 bool err_flag; 329 }; 330 331 static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val) 332 { 333 writel(val, priv->ioaddr + reg_addr); 334 } 335 336 static u32 netsec_read(struct netsec_priv *priv, u32 reg_addr) 337 { 338 return readl(priv->ioaddr + reg_addr); 339 } 340 341 /************* MDIO BUS OPS FOLLOW *************/ 342 343 #define TIMEOUT_SPINS_MAC 1000 344 #define TIMEOUT_SECONDARY_MS_MAC 100 345 346 static u32 netsec_clk_type(u32 freq) 347 { 348 if (freq < MHZ(35)) 349 return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ; 350 if (freq < MHZ(60)) 351 return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ; 352 if (freq < MHZ(100)) 353 return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ; 354 if (freq < MHZ(150)) 355 return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ; 356 if (freq < MHZ(250)) 357 return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ; 358 359 return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ; 360 } 361 362 static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask) 363 { 364 u32 timeout = TIMEOUT_SPINS_MAC; 365 366 while (--timeout && netsec_read(priv, addr) & mask) 367 cpu_relax(); 368 if (timeout) 369 return 0; 370 371 timeout = TIMEOUT_SECONDARY_MS_MAC; 372 while (--timeout && netsec_read(priv, addr) & mask) 373 usleep_range(1000, 2000); 374 375 if (timeout) 376 return 0; 377 378 netdev_WARN(priv->ndev, "%s: timeout\n", __func__); 379 380 return -ETIMEDOUT; 381 } 382 383 static int netsec_mac_write(struct netsec_priv *priv, u32 addr, u32 value) 384 { 385 netsec_write(priv, MAC_REG_DATA, value); 386 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE); 387 return netsec_wait_while_busy(priv, 388 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); 389 } 390 391 static int netsec_mac_read(struct netsec_priv *priv, u32 addr, u32 *read) 392 { 393 int ret; 394 395 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ); 396 ret = netsec_wait_while_busy(priv, 397 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); 398 if (ret) 399 return ret; 400 401 *read = netsec_read(priv, MAC_REG_DATA); 402 403 return 0; 404 } 405 406 static int netsec_mac_wait_while_busy(struct netsec_priv *priv, 407 u32 addr, u32 mask) 408 { 409 u32 timeout = TIMEOUT_SPINS_MAC; 410 int ret, data; 411 412 do { 413 ret = netsec_mac_read(priv, addr, &data); 414 if (ret) 415 break; 416 cpu_relax(); 417 } while (--timeout && (data & mask)); 418 419 if (timeout) 420 return 0; 421 422 timeout = TIMEOUT_SECONDARY_MS_MAC; 423 do { 424 usleep_range(1000, 2000); 425 426 ret = netsec_mac_read(priv, addr, &data); 427 if (ret) 428 break; 429 cpu_relax(); 430 } while (--timeout && (data & mask)); 431 432 if (timeout && !ret) 433 return 0; 434 435 netdev_WARN(priv->ndev, "%s: timeout\n", __func__); 436 437 return -ETIMEDOUT; 438 } 439 440 static int netsec_mac_update_to_phy_state(struct netsec_priv *priv) 441 { 442 struct phy_device *phydev = priv->ndev->phydev; 443 u32 value = 0; 444 445 value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON : 446 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON; 447 448 if (phydev->speed != SPEED_1000) 449 value |= NETSEC_MCR_PS; 450 451 if (priv->phy_interface != PHY_INTERFACE_MODE_GMII && 452 phydev->speed == SPEED_100) 453 value |= NETSEC_GMAC_MCR_REG_FES; 454 455 value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE; 456 457 if (phy_interface_mode_is_rgmii(priv->phy_interface)) 458 value |= NETSEC_GMAC_MCR_REG_IBN; 459 460 if (netsec_mac_write(priv, GMAC_REG_MCR, value)) 461 return -ETIMEDOUT; 462 463 return 0; 464 } 465 466 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr); 467 468 static int netsec_phy_write(struct mii_bus *bus, 469 int phy_addr, int reg, u16 val) 470 { 471 int status; 472 struct netsec_priv *priv = bus->priv; 473 474 if (netsec_mac_write(priv, GMAC_REG_GDR, val)) 475 return -ETIMEDOUT; 476 if (netsec_mac_write(priv, GMAC_REG_GAR, 477 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | 478 reg << NETSEC_GMAC_GAR_REG_SHIFT_GR | 479 NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB | 480 (netsec_clk_type(priv->freq) << 481 GMAC_REG_SHIFT_CR_GAR))) 482 return -ETIMEDOUT; 483 484 status = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, 485 NETSEC_GMAC_GAR_REG_GB); 486 487 /* Developerbox implements RTL8211E PHY and there is 488 * a compatibility problem with F_GMAC4. 489 * RTL8211E expects MDC clock must be kept toggling for several 490 * clock cycle with MDIO high before entering the IDLE state. 491 * To meet this requirement, netsec driver needs to issue dummy 492 * read(e.g. read PHYID1(offset 0x2) register) right after write. 493 */ 494 netsec_phy_read(bus, phy_addr, MII_PHYSID1); 495 496 return status; 497 } 498 499 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr) 500 { 501 struct netsec_priv *priv = bus->priv; 502 u32 data; 503 int ret; 504 505 if (netsec_mac_write(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB | 506 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | 507 reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR | 508 (netsec_clk_type(priv->freq) << 509 GMAC_REG_SHIFT_CR_GAR))) 510 return -ETIMEDOUT; 511 512 ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, 513 NETSEC_GMAC_GAR_REG_GB); 514 if (ret) 515 return ret; 516 517 ret = netsec_mac_read(priv, GMAC_REG_GDR, &data); 518 if (ret) 519 return ret; 520 521 return data; 522 } 523 524 /************* ETHTOOL_OPS FOLLOW *************/ 525 526 static void netsec_et_get_drvinfo(struct net_device *net_device, 527 struct ethtool_drvinfo *info) 528 { 529 strlcpy(info->driver, "netsec", sizeof(info->driver)); 530 strlcpy(info->bus_info, dev_name(net_device->dev.parent), 531 sizeof(info->bus_info)); 532 } 533 534 static int netsec_et_get_coalesce(struct net_device *net_device, 535 struct ethtool_coalesce *et_coalesce) 536 { 537 struct netsec_priv *priv = netdev_priv(net_device); 538 539 *et_coalesce = priv->et_coalesce; 540 541 return 0; 542 } 543 544 static int netsec_et_set_coalesce(struct net_device *net_device, 545 struct ethtool_coalesce *et_coalesce) 546 { 547 struct netsec_priv *priv = netdev_priv(net_device); 548 549 priv->et_coalesce = *et_coalesce; 550 551 if (priv->et_coalesce.tx_coalesce_usecs < 50) 552 priv->et_coalesce.tx_coalesce_usecs = 50; 553 if (priv->et_coalesce.tx_max_coalesced_frames < 1) 554 priv->et_coalesce.tx_max_coalesced_frames = 1; 555 556 netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT, 557 priv->et_coalesce.tx_max_coalesced_frames); 558 netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR, 559 priv->et_coalesce.tx_coalesce_usecs); 560 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE); 561 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP); 562 563 if (priv->et_coalesce.rx_coalesce_usecs < 50) 564 priv->et_coalesce.rx_coalesce_usecs = 50; 565 if (priv->et_coalesce.rx_max_coalesced_frames < 1) 566 priv->et_coalesce.rx_max_coalesced_frames = 1; 567 568 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT, 569 priv->et_coalesce.rx_max_coalesced_frames); 570 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR, 571 priv->et_coalesce.rx_coalesce_usecs); 572 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT); 573 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP); 574 575 return 0; 576 } 577 578 static u32 netsec_et_get_msglevel(struct net_device *dev) 579 { 580 struct netsec_priv *priv = netdev_priv(dev); 581 582 return priv->msg_enable; 583 } 584 585 static void netsec_et_set_msglevel(struct net_device *dev, u32 datum) 586 { 587 struct netsec_priv *priv = netdev_priv(dev); 588 589 priv->msg_enable = datum; 590 } 591 592 static const struct ethtool_ops netsec_ethtool_ops = { 593 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 594 ETHTOOL_COALESCE_MAX_FRAMES, 595 .get_drvinfo = netsec_et_get_drvinfo, 596 .get_link_ksettings = phy_ethtool_get_link_ksettings, 597 .set_link_ksettings = phy_ethtool_set_link_ksettings, 598 .get_link = ethtool_op_get_link, 599 .get_coalesce = netsec_et_get_coalesce, 600 .set_coalesce = netsec_et_set_coalesce, 601 .get_msglevel = netsec_et_get_msglevel, 602 .set_msglevel = netsec_et_set_msglevel, 603 }; 604 605 /************* NETDEV_OPS FOLLOW *************/ 606 607 608 static void netsec_set_rx_de(struct netsec_priv *priv, 609 struct netsec_desc_ring *dring, u16 idx, 610 const struct netsec_desc *desc) 611 { 612 struct netsec_de *de = dring->vaddr + DESC_SZ * idx; 613 u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) | 614 (1 << NETSEC_RX_PKT_FS_FIELD) | 615 (1 << NETSEC_RX_PKT_LS_FIELD); 616 617 if (idx == DESC_NUM - 1) 618 attr |= (1 << NETSEC_RX_PKT_LD_FIELD); 619 620 de->data_buf_addr_up = upper_32_bits(desc->dma_addr); 621 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr); 622 de->buf_len_info = desc->len; 623 de->attr = attr; 624 dma_wmb(); 625 626 dring->desc[idx].dma_addr = desc->dma_addr; 627 dring->desc[idx].addr = desc->addr; 628 dring->desc[idx].len = desc->len; 629 } 630 631 static bool netsec_clean_tx_dring(struct netsec_priv *priv) 632 { 633 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 634 struct xdp_frame_bulk bq; 635 struct netsec_de *entry; 636 int tail = dring->tail; 637 unsigned int bytes; 638 int cnt = 0; 639 640 spin_lock(&dring->lock); 641 642 bytes = 0; 643 xdp_frame_bulk_init(&bq); 644 entry = dring->vaddr + DESC_SZ * tail; 645 646 rcu_read_lock(); /* need for xdp_return_frame_bulk */ 647 648 while (!(entry->attr & (1U << NETSEC_TX_SHIFT_OWN_FIELD)) && 649 cnt < DESC_NUM) { 650 struct netsec_desc *desc; 651 int eop; 652 653 desc = &dring->desc[tail]; 654 eop = (entry->attr >> NETSEC_TX_LAST) & 1; 655 dma_rmb(); 656 657 /* if buf_type is either TYPE_NETSEC_SKB or 658 * TYPE_NETSEC_XDP_NDO we mapped it 659 */ 660 if (desc->buf_type != TYPE_NETSEC_XDP_TX) 661 dma_unmap_single(priv->dev, desc->dma_addr, desc->len, 662 DMA_TO_DEVICE); 663 664 if (!eop) 665 goto next; 666 667 if (desc->buf_type == TYPE_NETSEC_SKB) { 668 bytes += desc->skb->len; 669 dev_kfree_skb(desc->skb); 670 } else { 671 bytes += desc->xdpf->len; 672 if (desc->buf_type == TYPE_NETSEC_XDP_TX) 673 xdp_return_frame_rx_napi(desc->xdpf); 674 else 675 xdp_return_frame_bulk(desc->xdpf, &bq); 676 } 677 next: 678 /* clean up so netsec_uninit_pkt_dring() won't free the skb 679 * again 680 */ 681 *desc = (struct netsec_desc){}; 682 683 /* entry->attr is not going to be accessed by the NIC until 684 * netsec_set_tx_de() is called. No need for a dma_wmb() here 685 */ 686 entry->attr = 1U << NETSEC_TX_SHIFT_OWN_FIELD; 687 /* move tail ahead */ 688 dring->tail = (tail + 1) % DESC_NUM; 689 690 tail = dring->tail; 691 entry = dring->vaddr + DESC_SZ * tail; 692 cnt++; 693 } 694 xdp_flush_frame_bulk(&bq); 695 696 rcu_read_unlock(); 697 698 spin_unlock(&dring->lock); 699 700 if (!cnt) 701 return false; 702 703 /* reading the register clears the irq */ 704 netsec_read(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT); 705 706 priv->ndev->stats.tx_packets += cnt; 707 priv->ndev->stats.tx_bytes += bytes; 708 709 netdev_completed_queue(priv->ndev, cnt, bytes); 710 711 return true; 712 } 713 714 static void netsec_process_tx(struct netsec_priv *priv) 715 { 716 struct net_device *ndev = priv->ndev; 717 bool cleaned; 718 719 cleaned = netsec_clean_tx_dring(priv); 720 721 if (cleaned && netif_queue_stopped(ndev)) { 722 /* Make sure we update the value, anyone stopping the queue 723 * after this will read the proper consumer idx 724 */ 725 smp_wmb(); 726 netif_wake_queue(ndev); 727 } 728 } 729 730 static void *netsec_alloc_rx_data(struct netsec_priv *priv, 731 dma_addr_t *dma_handle, u16 *desc_len) 732 733 { 734 735 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 736 struct page *page; 737 738 page = page_pool_dev_alloc_pages(dring->page_pool); 739 if (!page) 740 return NULL; 741 742 /* We allocate the same buffer length for XDP and non-XDP cases. 743 * page_pool API will map the whole page, skip what's needed for 744 * network payloads and/or XDP 745 */ 746 *dma_handle = page_pool_get_dma_addr(page) + NETSEC_RXBUF_HEADROOM; 747 /* Make sure the incoming payload fits in the page for XDP and non-XDP 748 * cases and reserve enough space for headroom + skb_shared_info 749 */ 750 *desc_len = NETSEC_RX_BUF_SIZE; 751 752 return page_address(page); 753 } 754 755 static void netsec_rx_fill(struct netsec_priv *priv, u16 from, u16 num) 756 { 757 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 758 u16 idx = from; 759 760 while (num) { 761 netsec_set_rx_de(priv, dring, idx, &dring->desc[idx]); 762 idx++; 763 if (idx >= DESC_NUM) 764 idx = 0; 765 num--; 766 } 767 } 768 769 static void netsec_xdp_ring_tx_db(struct netsec_priv *priv, u16 pkts) 770 { 771 if (likely(pkts)) 772 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, pkts); 773 } 774 775 static void netsec_finalize_xdp_rx(struct netsec_priv *priv, u32 xdp_res, 776 u16 pkts) 777 { 778 if (xdp_res & NETSEC_XDP_REDIR) 779 xdp_do_flush_map(); 780 781 if (xdp_res & NETSEC_XDP_TX) 782 netsec_xdp_ring_tx_db(priv, pkts); 783 } 784 785 static void netsec_set_tx_de(struct netsec_priv *priv, 786 struct netsec_desc_ring *dring, 787 const struct netsec_tx_pkt_ctrl *tx_ctrl, 788 const struct netsec_desc *desc, void *buf) 789 { 790 int idx = dring->head; 791 struct netsec_de *de; 792 u32 attr; 793 794 de = dring->vaddr + (DESC_SZ * idx); 795 796 attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) | 797 (1 << NETSEC_TX_SHIFT_PT_FIELD) | 798 (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) | 799 (1 << NETSEC_TX_SHIFT_FS_FIELD) | 800 (1 << NETSEC_TX_LAST) | 801 (tx_ctrl->cksum_offload_flag << NETSEC_TX_SHIFT_CO) | 802 (tx_ctrl->tcp_seg_offload_flag << NETSEC_TX_SHIFT_SO) | 803 (1 << NETSEC_TX_SHIFT_TRS_FIELD); 804 if (idx == DESC_NUM - 1) 805 attr |= (1 << NETSEC_TX_SHIFT_LD_FIELD); 806 807 de->data_buf_addr_up = upper_32_bits(desc->dma_addr); 808 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr); 809 de->buf_len_info = (tx_ctrl->tcp_seg_len << 16) | desc->len; 810 de->attr = attr; 811 812 dring->desc[idx] = *desc; 813 if (desc->buf_type == TYPE_NETSEC_SKB) 814 dring->desc[idx].skb = buf; 815 else if (desc->buf_type == TYPE_NETSEC_XDP_TX || 816 desc->buf_type == TYPE_NETSEC_XDP_NDO) 817 dring->desc[idx].xdpf = buf; 818 819 /* move head ahead */ 820 dring->head = (dring->head + 1) % DESC_NUM; 821 } 822 823 /* The current driver only supports 1 Txq, this should run under spin_lock() */ 824 static u32 netsec_xdp_queue_one(struct netsec_priv *priv, 825 struct xdp_frame *xdpf, bool is_ndo) 826 827 { 828 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX]; 829 struct page *page = virt_to_page(xdpf->data); 830 struct netsec_tx_pkt_ctrl tx_ctrl = {}; 831 struct netsec_desc tx_desc; 832 dma_addr_t dma_handle; 833 u16 filled; 834 835 if (tx_ring->head >= tx_ring->tail) 836 filled = tx_ring->head - tx_ring->tail; 837 else 838 filled = tx_ring->head + DESC_NUM - tx_ring->tail; 839 840 if (DESC_NUM - filled <= 1) 841 return NETSEC_XDP_CONSUMED; 842 843 if (is_ndo) { 844 /* this is for ndo_xdp_xmit, the buffer needs mapping before 845 * sending 846 */ 847 dma_handle = dma_map_single(priv->dev, xdpf->data, xdpf->len, 848 DMA_TO_DEVICE); 849 if (dma_mapping_error(priv->dev, dma_handle)) 850 return NETSEC_XDP_CONSUMED; 851 tx_desc.buf_type = TYPE_NETSEC_XDP_NDO; 852 } else { 853 /* This is the device Rx buffer from page_pool. No need to remap 854 * just sync and send it 855 */ 856 struct netsec_desc_ring *rx_ring = 857 &priv->desc_ring[NETSEC_RING_RX]; 858 enum dma_data_direction dma_dir = 859 page_pool_get_dma_dir(rx_ring->page_pool); 860 861 dma_handle = page_pool_get_dma_addr(page) + xdpf->headroom + 862 sizeof(*xdpf); 863 dma_sync_single_for_device(priv->dev, dma_handle, xdpf->len, 864 dma_dir); 865 tx_desc.buf_type = TYPE_NETSEC_XDP_TX; 866 } 867 868 tx_desc.dma_addr = dma_handle; 869 tx_desc.addr = xdpf->data; 870 tx_desc.len = xdpf->len; 871 872 netdev_sent_queue(priv->ndev, xdpf->len); 873 netsec_set_tx_de(priv, tx_ring, &tx_ctrl, &tx_desc, xdpf); 874 875 return NETSEC_XDP_TX; 876 } 877 878 static u32 netsec_xdp_xmit_back(struct netsec_priv *priv, struct xdp_buff *xdp) 879 { 880 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX]; 881 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 882 u32 ret; 883 884 if (unlikely(!xdpf)) 885 return NETSEC_XDP_CONSUMED; 886 887 spin_lock(&tx_ring->lock); 888 ret = netsec_xdp_queue_one(priv, xdpf, false); 889 spin_unlock(&tx_ring->lock); 890 891 return ret; 892 } 893 894 static u32 netsec_run_xdp(struct netsec_priv *priv, struct bpf_prog *prog, 895 struct xdp_buff *xdp) 896 { 897 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 898 unsigned int sync, len = xdp->data_end - xdp->data; 899 u32 ret = NETSEC_XDP_PASS; 900 struct page *page; 901 int err; 902 u32 act; 903 904 act = bpf_prog_run_xdp(prog, xdp); 905 906 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 907 sync = xdp->data_end - xdp->data_hard_start - NETSEC_RXBUF_HEADROOM; 908 sync = max(sync, len); 909 910 switch (act) { 911 case XDP_PASS: 912 ret = NETSEC_XDP_PASS; 913 break; 914 case XDP_TX: 915 ret = netsec_xdp_xmit_back(priv, xdp); 916 if (ret != NETSEC_XDP_TX) { 917 page = virt_to_head_page(xdp->data); 918 page_pool_put_page(dring->page_pool, page, sync, true); 919 } 920 break; 921 case XDP_REDIRECT: 922 err = xdp_do_redirect(priv->ndev, xdp, prog); 923 if (!err) { 924 ret = NETSEC_XDP_REDIR; 925 } else { 926 ret = NETSEC_XDP_CONSUMED; 927 page = virt_to_head_page(xdp->data); 928 page_pool_put_page(dring->page_pool, page, sync, true); 929 } 930 break; 931 default: 932 bpf_warn_invalid_xdp_action(act); 933 fallthrough; 934 case XDP_ABORTED: 935 trace_xdp_exception(priv->ndev, prog, act); 936 fallthrough; /* handle aborts by dropping packet */ 937 case XDP_DROP: 938 ret = NETSEC_XDP_CONSUMED; 939 page = virt_to_head_page(xdp->data); 940 page_pool_put_page(dring->page_pool, page, sync, true); 941 break; 942 } 943 944 return ret; 945 } 946 947 static int netsec_process_rx(struct netsec_priv *priv, int budget) 948 { 949 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 950 struct net_device *ndev = priv->ndev; 951 struct netsec_rx_pkt_info rx_info; 952 enum dma_data_direction dma_dir; 953 struct bpf_prog *xdp_prog; 954 struct xdp_buff xdp; 955 u16 xdp_xmit = 0; 956 u32 xdp_act = 0; 957 int done = 0; 958 959 xdp_init_buff(&xdp, PAGE_SIZE, &dring->xdp_rxq); 960 961 rcu_read_lock(); 962 xdp_prog = READ_ONCE(priv->xdp_prog); 963 dma_dir = page_pool_get_dma_dir(dring->page_pool); 964 965 while (done < budget) { 966 u16 idx = dring->tail; 967 struct netsec_de *de = dring->vaddr + (DESC_SZ * idx); 968 struct netsec_desc *desc = &dring->desc[idx]; 969 struct page *page = virt_to_page(desc->addr); 970 u32 xdp_result = NETSEC_XDP_PASS; 971 struct sk_buff *skb = NULL; 972 u16 pkt_len, desc_len; 973 dma_addr_t dma_handle; 974 void *buf_addr; 975 976 if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD)) { 977 /* reading the register clears the irq */ 978 netsec_read(priv, NETSEC_REG_NRM_RX_PKTCNT); 979 break; 980 } 981 982 /* This barrier is needed to keep us from reading 983 * any other fields out of the netsec_de until we have 984 * verified the descriptor has been written back 985 */ 986 dma_rmb(); 987 done++; 988 989 pkt_len = de->buf_len_info >> 16; 990 rx_info.err_code = (de->attr >> NETSEC_RX_PKT_ERR_FIELD) & 991 NETSEC_RX_PKT_ERR_MASK; 992 rx_info.err_flag = (de->attr >> NETSEC_RX_PKT_ER_FIELD) & 1; 993 if (rx_info.err_flag) { 994 netif_err(priv, drv, priv->ndev, 995 "%s: rx fail err(%d)\n", __func__, 996 rx_info.err_code); 997 ndev->stats.rx_dropped++; 998 dring->tail = (dring->tail + 1) % DESC_NUM; 999 /* reuse buffer page frag */ 1000 netsec_rx_fill(priv, idx, 1); 1001 continue; 1002 } 1003 rx_info.rx_cksum_result = 1004 (de->attr >> NETSEC_RX_PKT_CO_FIELD) & 3; 1005 1006 /* allocate a fresh buffer and map it to the hardware. 1007 * This will eventually replace the old buffer in the hardware 1008 */ 1009 buf_addr = netsec_alloc_rx_data(priv, &dma_handle, &desc_len); 1010 1011 if (unlikely(!buf_addr)) 1012 break; 1013 1014 dma_sync_single_for_cpu(priv->dev, desc->dma_addr, pkt_len, 1015 dma_dir); 1016 prefetch(desc->addr); 1017 1018 xdp_prepare_buff(&xdp, desc->addr, NETSEC_RXBUF_HEADROOM, 1019 pkt_len, false); 1020 1021 if (xdp_prog) { 1022 xdp_result = netsec_run_xdp(priv, xdp_prog, &xdp); 1023 if (xdp_result != NETSEC_XDP_PASS) { 1024 xdp_act |= xdp_result; 1025 if (xdp_result == NETSEC_XDP_TX) 1026 xdp_xmit++; 1027 goto next; 1028 } 1029 } 1030 skb = build_skb(desc->addr, desc->len + NETSEC_RX_BUF_NON_DATA); 1031 1032 if (unlikely(!skb)) { 1033 /* If skb fails recycle_direct will either unmap and 1034 * free the page or refill the cache depending on the 1035 * cache state. Since we paid the allocation cost if 1036 * building an skb fails try to put the page into cache 1037 */ 1038 page_pool_put_page(dring->page_pool, page, pkt_len, 1039 true); 1040 netif_err(priv, drv, priv->ndev, 1041 "rx failed to build skb\n"); 1042 break; 1043 } 1044 page_pool_release_page(dring->page_pool, page); 1045 1046 skb_reserve(skb, xdp.data - xdp.data_hard_start); 1047 skb_put(skb, xdp.data_end - xdp.data); 1048 skb->protocol = eth_type_trans(skb, priv->ndev); 1049 1050 if (priv->rx_cksum_offload_flag && 1051 rx_info.rx_cksum_result == NETSEC_RX_CKSUM_OK) 1052 skb->ip_summed = CHECKSUM_UNNECESSARY; 1053 1054 next: 1055 if (skb) 1056 napi_gro_receive(&priv->napi, skb); 1057 if (skb || xdp_result) { 1058 ndev->stats.rx_packets++; 1059 ndev->stats.rx_bytes += xdp.data_end - xdp.data; 1060 } 1061 1062 /* Update the descriptor with fresh buffers */ 1063 desc->len = desc_len; 1064 desc->dma_addr = dma_handle; 1065 desc->addr = buf_addr; 1066 1067 netsec_rx_fill(priv, idx, 1); 1068 dring->tail = (dring->tail + 1) % DESC_NUM; 1069 } 1070 netsec_finalize_xdp_rx(priv, xdp_act, xdp_xmit); 1071 1072 rcu_read_unlock(); 1073 1074 return done; 1075 } 1076 1077 static int netsec_napi_poll(struct napi_struct *napi, int budget) 1078 { 1079 struct netsec_priv *priv; 1080 int done; 1081 1082 priv = container_of(napi, struct netsec_priv, napi); 1083 1084 netsec_process_tx(priv); 1085 done = netsec_process_rx(priv, budget); 1086 1087 if (done < budget && napi_complete_done(napi, done)) { 1088 unsigned long flags; 1089 1090 spin_lock_irqsave(&priv->reglock, flags); 1091 netsec_write(priv, NETSEC_REG_INTEN_SET, 1092 NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1093 spin_unlock_irqrestore(&priv->reglock, flags); 1094 } 1095 1096 return done; 1097 } 1098 1099 1100 static int netsec_desc_used(struct netsec_desc_ring *dring) 1101 { 1102 int used; 1103 1104 if (dring->head >= dring->tail) 1105 used = dring->head - dring->tail; 1106 else 1107 used = dring->head + DESC_NUM - dring->tail; 1108 1109 return used; 1110 } 1111 1112 static int netsec_check_stop_tx(struct netsec_priv *priv, int used) 1113 { 1114 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 1115 1116 /* keep tail from touching the queue */ 1117 if (DESC_NUM - used < 2) { 1118 netif_stop_queue(priv->ndev); 1119 1120 /* Make sure we read the updated value in case 1121 * descriptors got freed 1122 */ 1123 smp_rmb(); 1124 1125 used = netsec_desc_used(dring); 1126 if (DESC_NUM - used < 2) 1127 return NETDEV_TX_BUSY; 1128 1129 netif_wake_queue(priv->ndev); 1130 } 1131 1132 return 0; 1133 } 1134 1135 static netdev_tx_t netsec_netdev_start_xmit(struct sk_buff *skb, 1136 struct net_device *ndev) 1137 { 1138 struct netsec_priv *priv = netdev_priv(ndev); 1139 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 1140 struct netsec_tx_pkt_ctrl tx_ctrl = {}; 1141 struct netsec_desc tx_desc; 1142 u16 tso_seg_len = 0; 1143 int filled; 1144 1145 spin_lock_bh(&dring->lock); 1146 filled = netsec_desc_used(dring); 1147 if (netsec_check_stop_tx(priv, filled)) { 1148 spin_unlock_bh(&dring->lock); 1149 net_warn_ratelimited("%s %s Tx queue full\n", 1150 dev_name(priv->dev), ndev->name); 1151 return NETDEV_TX_BUSY; 1152 } 1153 1154 if (skb->ip_summed == CHECKSUM_PARTIAL) 1155 tx_ctrl.cksum_offload_flag = true; 1156 1157 if (skb_is_gso(skb)) 1158 tso_seg_len = skb_shinfo(skb)->gso_size; 1159 1160 if (tso_seg_len > 0) { 1161 if (skb->protocol == htons(ETH_P_IP)) { 1162 ip_hdr(skb)->tot_len = 0; 1163 tcp_hdr(skb)->check = 1164 ~tcp_v4_check(0, ip_hdr(skb)->saddr, 1165 ip_hdr(skb)->daddr, 0); 1166 } else { 1167 tcp_v6_gso_csum_prep(skb); 1168 } 1169 1170 tx_ctrl.tcp_seg_offload_flag = true; 1171 tx_ctrl.tcp_seg_len = tso_seg_len; 1172 } 1173 1174 tx_desc.dma_addr = dma_map_single(priv->dev, skb->data, 1175 skb_headlen(skb), DMA_TO_DEVICE); 1176 if (dma_mapping_error(priv->dev, tx_desc.dma_addr)) { 1177 spin_unlock_bh(&dring->lock); 1178 netif_err(priv, drv, priv->ndev, 1179 "%s: DMA mapping failed\n", __func__); 1180 ndev->stats.tx_dropped++; 1181 dev_kfree_skb_any(skb); 1182 return NETDEV_TX_OK; 1183 } 1184 tx_desc.addr = skb->data; 1185 tx_desc.len = skb_headlen(skb); 1186 tx_desc.buf_type = TYPE_NETSEC_SKB; 1187 1188 skb_tx_timestamp(skb); 1189 netdev_sent_queue(priv->ndev, skb->len); 1190 1191 netsec_set_tx_de(priv, dring, &tx_ctrl, &tx_desc, skb); 1192 spin_unlock_bh(&dring->lock); 1193 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */ 1194 1195 return NETDEV_TX_OK; 1196 } 1197 1198 static void netsec_uninit_pkt_dring(struct netsec_priv *priv, int id) 1199 { 1200 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 1201 struct netsec_desc *desc; 1202 u16 idx; 1203 1204 if (!dring->vaddr || !dring->desc) 1205 return; 1206 for (idx = 0; idx < DESC_NUM; idx++) { 1207 desc = &dring->desc[idx]; 1208 if (!desc->addr) 1209 continue; 1210 1211 if (id == NETSEC_RING_RX) { 1212 struct page *page = virt_to_page(desc->addr); 1213 1214 page_pool_put_full_page(dring->page_pool, page, false); 1215 } else if (id == NETSEC_RING_TX) { 1216 dma_unmap_single(priv->dev, desc->dma_addr, desc->len, 1217 DMA_TO_DEVICE); 1218 dev_kfree_skb(desc->skb); 1219 } 1220 } 1221 1222 /* Rx is currently using page_pool */ 1223 if (id == NETSEC_RING_RX) { 1224 if (xdp_rxq_info_is_reg(&dring->xdp_rxq)) 1225 xdp_rxq_info_unreg(&dring->xdp_rxq); 1226 page_pool_destroy(dring->page_pool); 1227 } 1228 1229 memset(dring->desc, 0, sizeof(struct netsec_desc) * DESC_NUM); 1230 memset(dring->vaddr, 0, DESC_SZ * DESC_NUM); 1231 1232 dring->head = 0; 1233 dring->tail = 0; 1234 1235 if (id == NETSEC_RING_TX) 1236 netdev_reset_queue(priv->ndev); 1237 } 1238 1239 static void netsec_free_dring(struct netsec_priv *priv, int id) 1240 { 1241 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 1242 1243 if (dring->vaddr) { 1244 dma_free_coherent(priv->dev, DESC_SZ * DESC_NUM, 1245 dring->vaddr, dring->desc_dma); 1246 dring->vaddr = NULL; 1247 } 1248 1249 kfree(dring->desc); 1250 dring->desc = NULL; 1251 } 1252 1253 static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id) 1254 { 1255 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 1256 1257 dring->vaddr = dma_alloc_coherent(priv->dev, DESC_SZ * DESC_NUM, 1258 &dring->desc_dma, GFP_KERNEL); 1259 if (!dring->vaddr) 1260 goto err; 1261 1262 dring->desc = kcalloc(DESC_NUM, sizeof(*dring->desc), GFP_KERNEL); 1263 if (!dring->desc) 1264 goto err; 1265 1266 return 0; 1267 err: 1268 netsec_free_dring(priv, id); 1269 1270 return -ENOMEM; 1271 } 1272 1273 static void netsec_setup_tx_dring(struct netsec_priv *priv) 1274 { 1275 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 1276 int i; 1277 1278 for (i = 0; i < DESC_NUM; i++) { 1279 struct netsec_de *de; 1280 1281 de = dring->vaddr + (DESC_SZ * i); 1282 /* de->attr is not going to be accessed by the NIC 1283 * until netsec_set_tx_de() is called. 1284 * No need for a dma_wmb() here 1285 */ 1286 de->attr = 1U << NETSEC_TX_SHIFT_OWN_FIELD; 1287 } 1288 } 1289 1290 static int netsec_setup_rx_dring(struct netsec_priv *priv) 1291 { 1292 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 1293 struct bpf_prog *xdp_prog = READ_ONCE(priv->xdp_prog); 1294 struct page_pool_params pp_params = { 1295 .order = 0, 1296 /* internal DMA mapping in page_pool */ 1297 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1298 .pool_size = DESC_NUM, 1299 .nid = NUMA_NO_NODE, 1300 .dev = priv->dev, 1301 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 1302 .offset = NETSEC_RXBUF_HEADROOM, 1303 .max_len = NETSEC_RX_BUF_SIZE, 1304 }; 1305 int i, err; 1306 1307 dring->page_pool = page_pool_create(&pp_params); 1308 if (IS_ERR(dring->page_pool)) { 1309 err = PTR_ERR(dring->page_pool); 1310 dring->page_pool = NULL; 1311 goto err_out; 1312 } 1313 1314 err = xdp_rxq_info_reg(&dring->xdp_rxq, priv->ndev, 0, priv->napi.napi_id); 1315 if (err) 1316 goto err_out; 1317 1318 err = xdp_rxq_info_reg_mem_model(&dring->xdp_rxq, MEM_TYPE_PAGE_POOL, 1319 dring->page_pool); 1320 if (err) 1321 goto err_out; 1322 1323 for (i = 0; i < DESC_NUM; i++) { 1324 struct netsec_desc *desc = &dring->desc[i]; 1325 dma_addr_t dma_handle; 1326 void *buf; 1327 u16 len; 1328 1329 buf = netsec_alloc_rx_data(priv, &dma_handle, &len); 1330 1331 if (!buf) { 1332 err = -ENOMEM; 1333 goto err_out; 1334 } 1335 desc->dma_addr = dma_handle; 1336 desc->addr = buf; 1337 desc->len = len; 1338 } 1339 1340 netsec_rx_fill(priv, 0, DESC_NUM); 1341 1342 return 0; 1343 1344 err_out: 1345 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1346 return err; 1347 } 1348 1349 static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg, 1350 u32 addr_h, u32 addr_l, u32 size) 1351 { 1352 u64 base = (u64)addr_h << 32 | addr_l; 1353 void __iomem *ucode; 1354 u32 i; 1355 1356 ucode = ioremap(base, size * sizeof(u32)); 1357 if (!ucode) 1358 return -ENOMEM; 1359 1360 for (i = 0; i < size; i++) 1361 netsec_write(priv, reg, readl(ucode + i * 4)); 1362 1363 iounmap(ucode); 1364 return 0; 1365 } 1366 1367 static int netsec_netdev_load_microcode(struct netsec_priv *priv) 1368 { 1369 u32 addr_h, addr_l, size; 1370 int err; 1371 1372 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_H); 1373 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_L); 1374 size = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_SIZE); 1375 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF, 1376 addr_h, addr_l, size); 1377 if (err) 1378 return err; 1379 1380 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_H); 1381 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_L); 1382 size = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_SIZE); 1383 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF, 1384 addr_h, addr_l, size); 1385 if (err) 1386 return err; 1387 1388 addr_h = 0; 1389 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_ADDRESS); 1390 size = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_SIZE); 1391 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF, 1392 addr_h, addr_l, size); 1393 if (err) 1394 return err; 1395 1396 return 0; 1397 } 1398 1399 static int netsec_reset_hardware(struct netsec_priv *priv, 1400 bool load_ucode) 1401 { 1402 u32 value; 1403 int err; 1404 1405 /* stop DMA engines */ 1406 if (!netsec_read(priv, NETSEC_REG_ADDR_DIS_CORE)) { 1407 netsec_write(priv, NETSEC_REG_DMA_HM_CTRL, 1408 NETSEC_DMA_CTRL_REG_STOP); 1409 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, 1410 NETSEC_DMA_CTRL_REG_STOP); 1411 1412 while (netsec_read(priv, NETSEC_REG_DMA_HM_CTRL) & 1413 NETSEC_DMA_CTRL_REG_STOP) 1414 cpu_relax(); 1415 1416 while (netsec_read(priv, NETSEC_REG_DMA_MH_CTRL) & 1417 NETSEC_DMA_CTRL_REG_STOP) 1418 cpu_relax(); 1419 } 1420 1421 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET); 1422 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN); 1423 netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL); 1424 1425 while (netsec_read(priv, NETSEC_REG_COM_INIT) != 0) 1426 cpu_relax(); 1427 1428 /* set desc_start addr */ 1429 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP, 1430 upper_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); 1431 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW, 1432 lower_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); 1433 1434 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP, 1435 upper_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); 1436 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW, 1437 lower_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); 1438 1439 /* set normal tx dring ring config */ 1440 netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG, 1441 1 << NETSEC_REG_DESC_ENDIAN); 1442 netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG, 1443 1 << NETSEC_REG_DESC_ENDIAN); 1444 1445 if (load_ucode) { 1446 err = netsec_netdev_load_microcode(priv); 1447 if (err) { 1448 netif_err(priv, probe, priv->ndev, 1449 "%s: failed to load microcode (%d)\n", 1450 __func__, err); 1451 return err; 1452 } 1453 } 1454 1455 /* start DMA engines */ 1456 netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1); 1457 netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0); 1458 1459 usleep_range(1000, 2000); 1460 1461 if (!(netsec_read(priv, NETSEC_REG_TOP_STATUS) & 1462 NETSEC_TOP_IRQ_REG_CODE_LOAD_END)) { 1463 netif_err(priv, probe, priv->ndev, 1464 "microengine start failed\n"); 1465 return -ENXIO; 1466 } 1467 netsec_write(priv, NETSEC_REG_TOP_STATUS, 1468 NETSEC_TOP_IRQ_REG_CODE_LOAD_END); 1469 1470 value = NETSEC_PKT_CTRL_REG_MODE_NRM; 1471 if (priv->ndev->mtu > ETH_DATA_LEN) 1472 value |= NETSEC_PKT_CTRL_REG_EN_JUMBO; 1473 1474 /* change to normal mode */ 1475 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS); 1476 netsec_write(priv, NETSEC_REG_PKT_CTRL, value); 1477 1478 while ((netsec_read(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) & 1479 NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) 1480 cpu_relax(); 1481 1482 /* clear any pending EMPTY/ERR irq status */ 1483 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0); 1484 1485 /* Disable TX & RX intr */ 1486 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); 1487 1488 return 0; 1489 } 1490 1491 static int netsec_start_gmac(struct netsec_priv *priv) 1492 { 1493 struct phy_device *phydev = priv->ndev->phydev; 1494 u32 value = 0; 1495 int ret; 1496 1497 if (phydev->speed != SPEED_1000) 1498 value = (NETSEC_GMAC_MCR_REG_CST | 1499 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON); 1500 1501 if (netsec_mac_write(priv, GMAC_REG_MCR, value)) 1502 return -ETIMEDOUT; 1503 if (netsec_mac_write(priv, GMAC_REG_BMR, 1504 NETSEC_GMAC_BMR_REG_RESET)) 1505 return -ETIMEDOUT; 1506 1507 /* Wait soft reset */ 1508 usleep_range(1000, 5000); 1509 1510 ret = netsec_mac_read(priv, GMAC_REG_BMR, &value); 1511 if (ret) 1512 return ret; 1513 if (value & NETSEC_GMAC_BMR_REG_SWR) 1514 return -EAGAIN; 1515 1516 netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1); 1517 if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1)) 1518 return -ETIMEDOUT; 1519 1520 netsec_write(priv, MAC_REG_DESC_INIT, 1); 1521 if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1)) 1522 return -ETIMEDOUT; 1523 1524 if (netsec_mac_write(priv, GMAC_REG_BMR, 1525 NETSEC_GMAC_BMR_REG_COMMON)) 1526 return -ETIMEDOUT; 1527 if (netsec_mac_write(priv, GMAC_REG_RDLAR, 1528 NETSEC_GMAC_RDLAR_REG_COMMON)) 1529 return -ETIMEDOUT; 1530 if (netsec_mac_write(priv, GMAC_REG_TDLAR, 1531 NETSEC_GMAC_TDLAR_REG_COMMON)) 1532 return -ETIMEDOUT; 1533 if (netsec_mac_write(priv, GMAC_REG_MFFR, 0x80000001)) 1534 return -ETIMEDOUT; 1535 1536 ret = netsec_mac_update_to_phy_state(priv); 1537 if (ret) 1538 return ret; 1539 1540 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value); 1541 if (ret) 1542 return ret; 1543 1544 value |= NETSEC_GMAC_OMR_REG_SR; 1545 value |= NETSEC_GMAC_OMR_REG_ST; 1546 1547 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); 1548 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); 1549 1550 netsec_et_set_coalesce(priv->ndev, &priv->et_coalesce); 1551 1552 if (netsec_mac_write(priv, GMAC_REG_OMR, value)) 1553 return -ETIMEDOUT; 1554 1555 return 0; 1556 } 1557 1558 static int netsec_stop_gmac(struct netsec_priv *priv) 1559 { 1560 u32 value; 1561 int ret; 1562 1563 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value); 1564 if (ret) 1565 return ret; 1566 value &= ~NETSEC_GMAC_OMR_REG_SR; 1567 value &= ~NETSEC_GMAC_OMR_REG_ST; 1568 1569 /* disable all interrupts */ 1570 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); 1571 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); 1572 1573 return netsec_mac_write(priv, GMAC_REG_OMR, value); 1574 } 1575 1576 static void netsec_phy_adjust_link(struct net_device *ndev) 1577 { 1578 struct netsec_priv *priv = netdev_priv(ndev); 1579 1580 if (ndev->phydev->link) 1581 netsec_start_gmac(priv); 1582 else 1583 netsec_stop_gmac(priv); 1584 1585 phy_print_status(ndev->phydev); 1586 } 1587 1588 static irqreturn_t netsec_irq_handler(int irq, void *dev_id) 1589 { 1590 struct netsec_priv *priv = dev_id; 1591 u32 val, status = netsec_read(priv, NETSEC_REG_TOP_STATUS); 1592 unsigned long flags; 1593 1594 /* Disable interrupts */ 1595 if (status & NETSEC_IRQ_TX) { 1596 val = netsec_read(priv, NETSEC_REG_NRM_TX_STATUS); 1597 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val); 1598 } 1599 if (status & NETSEC_IRQ_RX) { 1600 val = netsec_read(priv, NETSEC_REG_NRM_RX_STATUS); 1601 netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val); 1602 } 1603 1604 spin_lock_irqsave(&priv->reglock, flags); 1605 netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1606 spin_unlock_irqrestore(&priv->reglock, flags); 1607 1608 napi_schedule(&priv->napi); 1609 1610 return IRQ_HANDLED; 1611 } 1612 1613 static int netsec_netdev_open(struct net_device *ndev) 1614 { 1615 struct netsec_priv *priv = netdev_priv(ndev); 1616 int ret; 1617 1618 pm_runtime_get_sync(priv->dev); 1619 1620 netsec_setup_tx_dring(priv); 1621 ret = netsec_setup_rx_dring(priv); 1622 if (ret) { 1623 netif_err(priv, probe, priv->ndev, 1624 "%s: fail setup ring\n", __func__); 1625 goto err1; 1626 } 1627 1628 ret = request_irq(priv->ndev->irq, netsec_irq_handler, 1629 IRQF_SHARED, "netsec", priv); 1630 if (ret) { 1631 netif_err(priv, drv, priv->ndev, "request_irq failed\n"); 1632 goto err2; 1633 } 1634 1635 if (dev_of_node(priv->dev)) { 1636 if (!of_phy_connect(priv->ndev, priv->phy_np, 1637 netsec_phy_adjust_link, 0, 1638 priv->phy_interface)) { 1639 netif_err(priv, link, priv->ndev, "missing PHY\n"); 1640 ret = -ENODEV; 1641 goto err3; 1642 } 1643 } else { 1644 ret = phy_connect_direct(priv->ndev, priv->phydev, 1645 netsec_phy_adjust_link, 1646 priv->phy_interface); 1647 if (ret) { 1648 netif_err(priv, link, priv->ndev, 1649 "phy_connect_direct() failed (%d)\n", ret); 1650 goto err3; 1651 } 1652 } 1653 1654 phy_start(ndev->phydev); 1655 1656 netsec_start_gmac(priv); 1657 napi_enable(&priv->napi); 1658 netif_start_queue(ndev); 1659 1660 /* Enable TX+RX intr. */ 1661 netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1662 1663 return 0; 1664 err3: 1665 free_irq(priv->ndev->irq, priv); 1666 err2: 1667 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1668 err1: 1669 pm_runtime_put_sync(priv->dev); 1670 return ret; 1671 } 1672 1673 static int netsec_netdev_stop(struct net_device *ndev) 1674 { 1675 int ret; 1676 struct netsec_priv *priv = netdev_priv(ndev); 1677 1678 netif_stop_queue(priv->ndev); 1679 dma_wmb(); 1680 1681 napi_disable(&priv->napi); 1682 1683 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); 1684 netsec_stop_gmac(priv); 1685 1686 free_irq(priv->ndev->irq, priv); 1687 1688 netsec_uninit_pkt_dring(priv, NETSEC_RING_TX); 1689 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1690 1691 phy_stop(ndev->phydev); 1692 phy_disconnect(ndev->phydev); 1693 1694 ret = netsec_reset_hardware(priv, false); 1695 1696 pm_runtime_put_sync(priv->dev); 1697 1698 return ret; 1699 } 1700 1701 static int netsec_netdev_init(struct net_device *ndev) 1702 { 1703 struct netsec_priv *priv = netdev_priv(ndev); 1704 int ret; 1705 u16 data; 1706 1707 BUILD_BUG_ON_NOT_POWER_OF_2(DESC_NUM); 1708 1709 ret = netsec_alloc_dring(priv, NETSEC_RING_TX); 1710 if (ret) 1711 return ret; 1712 1713 ret = netsec_alloc_dring(priv, NETSEC_RING_RX); 1714 if (ret) 1715 goto err1; 1716 1717 /* set phy power down */ 1718 data = netsec_phy_read(priv->mii_bus, priv->phy_addr, MII_BMCR); 1719 netsec_phy_write(priv->mii_bus, priv->phy_addr, MII_BMCR, 1720 data | BMCR_PDOWN); 1721 1722 ret = netsec_reset_hardware(priv, true); 1723 if (ret) 1724 goto err2; 1725 1726 /* Restore phy power state */ 1727 netsec_phy_write(priv->mii_bus, priv->phy_addr, MII_BMCR, data); 1728 1729 spin_lock_init(&priv->desc_ring[NETSEC_RING_TX].lock); 1730 spin_lock_init(&priv->desc_ring[NETSEC_RING_RX].lock); 1731 1732 return 0; 1733 err2: 1734 netsec_free_dring(priv, NETSEC_RING_RX); 1735 err1: 1736 netsec_free_dring(priv, NETSEC_RING_TX); 1737 return ret; 1738 } 1739 1740 static void netsec_netdev_uninit(struct net_device *ndev) 1741 { 1742 struct netsec_priv *priv = netdev_priv(ndev); 1743 1744 netsec_free_dring(priv, NETSEC_RING_RX); 1745 netsec_free_dring(priv, NETSEC_RING_TX); 1746 } 1747 1748 static int netsec_netdev_set_features(struct net_device *ndev, 1749 netdev_features_t features) 1750 { 1751 struct netsec_priv *priv = netdev_priv(ndev); 1752 1753 priv->rx_cksum_offload_flag = !!(features & NETIF_F_RXCSUM); 1754 1755 return 0; 1756 } 1757 1758 static int netsec_xdp_xmit(struct net_device *ndev, int n, 1759 struct xdp_frame **frames, u32 flags) 1760 { 1761 struct netsec_priv *priv = netdev_priv(ndev); 1762 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX]; 1763 int i, nxmit = 0; 1764 1765 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1766 return -EINVAL; 1767 1768 spin_lock(&tx_ring->lock); 1769 for (i = 0; i < n; i++) { 1770 struct xdp_frame *xdpf = frames[i]; 1771 int err; 1772 1773 err = netsec_xdp_queue_one(priv, xdpf, true); 1774 if (err != NETSEC_XDP_TX) 1775 break; 1776 1777 tx_ring->xdp_xmit++; 1778 nxmit++; 1779 } 1780 spin_unlock(&tx_ring->lock); 1781 1782 if (unlikely(flags & XDP_XMIT_FLUSH)) { 1783 netsec_xdp_ring_tx_db(priv, tx_ring->xdp_xmit); 1784 tx_ring->xdp_xmit = 0; 1785 } 1786 1787 return nxmit; 1788 } 1789 1790 static int netsec_xdp_setup(struct netsec_priv *priv, struct bpf_prog *prog, 1791 struct netlink_ext_ack *extack) 1792 { 1793 struct net_device *dev = priv->ndev; 1794 struct bpf_prog *old_prog; 1795 1796 /* For now just support only the usual MTU sized frames */ 1797 if (prog && dev->mtu > 1500) { 1798 NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP"); 1799 return -EOPNOTSUPP; 1800 } 1801 1802 if (netif_running(dev)) 1803 netsec_netdev_stop(dev); 1804 1805 /* Detach old prog, if any */ 1806 old_prog = xchg(&priv->xdp_prog, prog); 1807 if (old_prog) 1808 bpf_prog_put(old_prog); 1809 1810 if (netif_running(dev)) 1811 netsec_netdev_open(dev); 1812 1813 return 0; 1814 } 1815 1816 static int netsec_xdp(struct net_device *ndev, struct netdev_bpf *xdp) 1817 { 1818 struct netsec_priv *priv = netdev_priv(ndev); 1819 1820 switch (xdp->command) { 1821 case XDP_SETUP_PROG: 1822 return netsec_xdp_setup(priv, xdp->prog, xdp->extack); 1823 default: 1824 return -EINVAL; 1825 } 1826 } 1827 1828 static const struct net_device_ops netsec_netdev_ops = { 1829 .ndo_init = netsec_netdev_init, 1830 .ndo_uninit = netsec_netdev_uninit, 1831 .ndo_open = netsec_netdev_open, 1832 .ndo_stop = netsec_netdev_stop, 1833 .ndo_start_xmit = netsec_netdev_start_xmit, 1834 .ndo_set_features = netsec_netdev_set_features, 1835 .ndo_set_mac_address = eth_mac_addr, 1836 .ndo_validate_addr = eth_validate_addr, 1837 .ndo_do_ioctl = phy_do_ioctl, 1838 .ndo_xdp_xmit = netsec_xdp_xmit, 1839 .ndo_bpf = netsec_xdp, 1840 }; 1841 1842 static int netsec_of_probe(struct platform_device *pdev, 1843 struct netsec_priv *priv, u32 *phy_addr) 1844 { 1845 int err; 1846 1847 err = of_get_phy_mode(pdev->dev.of_node, &priv->phy_interface); 1848 if (err) { 1849 dev_err(&pdev->dev, "missing required property 'phy-mode'\n"); 1850 return err; 1851 } 1852 1853 priv->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); 1854 if (!priv->phy_np) { 1855 dev_err(&pdev->dev, "missing required property 'phy-handle'\n"); 1856 return -EINVAL; 1857 } 1858 1859 *phy_addr = of_mdio_parse_addr(&pdev->dev, priv->phy_np); 1860 1861 priv->clk = devm_clk_get(&pdev->dev, NULL); /* get by 'phy_ref_clk' */ 1862 if (IS_ERR(priv->clk)) { 1863 dev_err(&pdev->dev, "phy_ref_clk not found\n"); 1864 return PTR_ERR(priv->clk); 1865 } 1866 priv->freq = clk_get_rate(priv->clk); 1867 1868 return 0; 1869 } 1870 1871 static int netsec_acpi_probe(struct platform_device *pdev, 1872 struct netsec_priv *priv, u32 *phy_addr) 1873 { 1874 int ret; 1875 1876 if (!IS_ENABLED(CONFIG_ACPI)) 1877 return -ENODEV; 1878 1879 /* ACPI systems are assumed to configure the PHY in firmware, so 1880 * there is really no need to discover the PHY mode from the DSDT. 1881 * Since firmware is known to exist in the field that configures the 1882 * PHY correctly but passes the wrong mode string in the phy-mode 1883 * device property, we have no choice but to ignore it. 1884 */ 1885 priv->phy_interface = PHY_INTERFACE_MODE_NA; 1886 1887 ret = device_property_read_u32(&pdev->dev, "phy-channel", phy_addr); 1888 if (ret) { 1889 dev_err(&pdev->dev, 1890 "missing required property 'phy-channel'\n"); 1891 return ret; 1892 } 1893 1894 ret = device_property_read_u32(&pdev->dev, 1895 "socionext,phy-clock-frequency", 1896 &priv->freq); 1897 if (ret) 1898 dev_err(&pdev->dev, 1899 "missing required property 'socionext,phy-clock-frequency'\n"); 1900 return ret; 1901 } 1902 1903 static void netsec_unregister_mdio(struct netsec_priv *priv) 1904 { 1905 struct phy_device *phydev = priv->phydev; 1906 1907 if (!dev_of_node(priv->dev) && phydev) { 1908 phy_device_remove(phydev); 1909 phy_device_free(phydev); 1910 } 1911 1912 mdiobus_unregister(priv->mii_bus); 1913 } 1914 1915 static int netsec_register_mdio(struct netsec_priv *priv, u32 phy_addr) 1916 { 1917 struct mii_bus *bus; 1918 int ret; 1919 1920 bus = devm_mdiobus_alloc(priv->dev); 1921 if (!bus) 1922 return -ENOMEM; 1923 1924 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(priv->dev)); 1925 bus->priv = priv; 1926 bus->name = "SNI NETSEC MDIO"; 1927 bus->read = netsec_phy_read; 1928 bus->write = netsec_phy_write; 1929 bus->parent = priv->dev; 1930 priv->mii_bus = bus; 1931 1932 if (dev_of_node(priv->dev)) { 1933 struct device_node *mdio_node, *parent = dev_of_node(priv->dev); 1934 1935 mdio_node = of_get_child_by_name(parent, "mdio"); 1936 if (mdio_node) { 1937 parent = mdio_node; 1938 } else { 1939 /* older f/w doesn't populate the mdio subnode, 1940 * allow relaxed upgrade of f/w in due time. 1941 */ 1942 dev_info(priv->dev, "Upgrade f/w for mdio subnode!\n"); 1943 } 1944 1945 ret = of_mdiobus_register(bus, parent); 1946 of_node_put(mdio_node); 1947 1948 if (ret) { 1949 dev_err(priv->dev, "mdiobus register err(%d)\n", ret); 1950 return ret; 1951 } 1952 } else { 1953 /* Mask out all PHYs from auto probing. */ 1954 bus->phy_mask = ~0; 1955 ret = mdiobus_register(bus); 1956 if (ret) { 1957 dev_err(priv->dev, "mdiobus register err(%d)\n", ret); 1958 return ret; 1959 } 1960 1961 priv->phydev = get_phy_device(bus, phy_addr, false); 1962 if (IS_ERR(priv->phydev)) { 1963 ret = PTR_ERR(priv->phydev); 1964 dev_err(priv->dev, "get_phy_device err(%d)\n", ret); 1965 priv->phydev = NULL; 1966 return -ENODEV; 1967 } 1968 1969 ret = phy_device_register(priv->phydev); 1970 if (ret) { 1971 mdiobus_unregister(bus); 1972 dev_err(priv->dev, 1973 "phy_device_register err(%d)\n", ret); 1974 } 1975 } 1976 1977 return ret; 1978 } 1979 1980 static int netsec_probe(struct platform_device *pdev) 1981 { 1982 struct resource *mmio_res, *eeprom_res, *irq_res; 1983 u8 *mac, macbuf[ETH_ALEN]; 1984 struct netsec_priv *priv; 1985 u32 hw_ver, phy_addr = 0; 1986 struct net_device *ndev; 1987 int ret; 1988 1989 mmio_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1990 if (!mmio_res) { 1991 dev_err(&pdev->dev, "No MMIO resource found.\n"); 1992 return -ENODEV; 1993 } 1994 1995 eeprom_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1996 if (!eeprom_res) { 1997 dev_info(&pdev->dev, "No EEPROM resource found.\n"); 1998 return -ENODEV; 1999 } 2000 2001 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 2002 if (!irq_res) { 2003 dev_err(&pdev->dev, "No IRQ resource found.\n"); 2004 return -ENODEV; 2005 } 2006 2007 ndev = alloc_etherdev(sizeof(*priv)); 2008 if (!ndev) 2009 return -ENOMEM; 2010 2011 priv = netdev_priv(ndev); 2012 2013 spin_lock_init(&priv->reglock); 2014 SET_NETDEV_DEV(ndev, &pdev->dev); 2015 platform_set_drvdata(pdev, priv); 2016 ndev->irq = irq_res->start; 2017 priv->dev = &pdev->dev; 2018 priv->ndev = ndev; 2019 2020 priv->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | 2021 NETIF_MSG_LINK | NETIF_MSG_PROBE; 2022 2023 priv->ioaddr = devm_ioremap(&pdev->dev, mmio_res->start, 2024 resource_size(mmio_res)); 2025 if (!priv->ioaddr) { 2026 dev_err(&pdev->dev, "devm_ioremap() failed\n"); 2027 ret = -ENXIO; 2028 goto free_ndev; 2029 } 2030 2031 priv->eeprom_base = devm_ioremap(&pdev->dev, eeprom_res->start, 2032 resource_size(eeprom_res)); 2033 if (!priv->eeprom_base) { 2034 dev_err(&pdev->dev, "devm_ioremap() failed for EEPROM\n"); 2035 ret = -ENXIO; 2036 goto free_ndev; 2037 } 2038 2039 mac = device_get_mac_address(&pdev->dev, macbuf, sizeof(macbuf)); 2040 if (mac) 2041 ether_addr_copy(ndev->dev_addr, mac); 2042 2043 if (priv->eeprom_base && 2044 (!mac || !is_valid_ether_addr(ndev->dev_addr))) { 2045 void __iomem *macp = priv->eeprom_base + 2046 NETSEC_EEPROM_MAC_ADDRESS; 2047 2048 ndev->dev_addr[0] = readb(macp + 3); 2049 ndev->dev_addr[1] = readb(macp + 2); 2050 ndev->dev_addr[2] = readb(macp + 1); 2051 ndev->dev_addr[3] = readb(macp + 0); 2052 ndev->dev_addr[4] = readb(macp + 7); 2053 ndev->dev_addr[5] = readb(macp + 6); 2054 } 2055 2056 if (!is_valid_ether_addr(ndev->dev_addr)) { 2057 dev_warn(&pdev->dev, "No MAC address found, using random\n"); 2058 eth_hw_addr_random(ndev); 2059 } 2060 2061 if (dev_of_node(&pdev->dev)) 2062 ret = netsec_of_probe(pdev, priv, &phy_addr); 2063 else 2064 ret = netsec_acpi_probe(pdev, priv, &phy_addr); 2065 if (ret) 2066 goto free_ndev; 2067 2068 priv->phy_addr = phy_addr; 2069 2070 if (!priv->freq) { 2071 dev_err(&pdev->dev, "missing PHY reference clock frequency\n"); 2072 ret = -ENODEV; 2073 goto free_ndev; 2074 } 2075 2076 /* default for throughput */ 2077 priv->et_coalesce.rx_coalesce_usecs = 500; 2078 priv->et_coalesce.rx_max_coalesced_frames = 8; 2079 priv->et_coalesce.tx_coalesce_usecs = 500; 2080 priv->et_coalesce.tx_max_coalesced_frames = 8; 2081 2082 ret = device_property_read_u32(&pdev->dev, "max-frame-size", 2083 &ndev->max_mtu); 2084 if (ret < 0) 2085 ndev->max_mtu = ETH_DATA_LEN; 2086 2087 /* runtime_pm coverage just for probe, open/close also cover it */ 2088 pm_runtime_enable(&pdev->dev); 2089 pm_runtime_get_sync(&pdev->dev); 2090 2091 hw_ver = netsec_read(priv, NETSEC_REG_F_TAIKI_VER); 2092 /* this driver only supports F_TAIKI style NETSEC */ 2093 if (NETSEC_F_NETSEC_VER_MAJOR_NUM(hw_ver) != 2094 NETSEC_F_NETSEC_VER_MAJOR_NUM(NETSEC_REG_NETSEC_VER_F_TAIKI)) { 2095 ret = -ENODEV; 2096 goto pm_disable; 2097 } 2098 2099 dev_info(&pdev->dev, "hardware revision %d.%d\n", 2100 hw_ver >> 16, hw_ver & 0xffff); 2101 2102 netif_napi_add(ndev, &priv->napi, netsec_napi_poll, NAPI_POLL_WEIGHT); 2103 2104 ndev->netdev_ops = &netsec_netdev_ops; 2105 ndev->ethtool_ops = &netsec_ethtool_ops; 2106 2107 ndev->features |= NETIF_F_HIGHDMA | NETIF_F_RXCSUM | NETIF_F_GSO | 2108 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2109 ndev->hw_features = ndev->features; 2110 2111 priv->rx_cksum_offload_flag = true; 2112 2113 ret = netsec_register_mdio(priv, phy_addr); 2114 if (ret) 2115 goto unreg_napi; 2116 2117 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40))) 2118 dev_warn(&pdev->dev, "Failed to set DMA mask\n"); 2119 2120 ret = register_netdev(ndev); 2121 if (ret) { 2122 netif_err(priv, probe, ndev, "register_netdev() failed\n"); 2123 goto unreg_mii; 2124 } 2125 2126 pm_runtime_put_sync(&pdev->dev); 2127 return 0; 2128 2129 unreg_mii: 2130 netsec_unregister_mdio(priv); 2131 unreg_napi: 2132 netif_napi_del(&priv->napi); 2133 pm_disable: 2134 pm_runtime_put_sync(&pdev->dev); 2135 pm_runtime_disable(&pdev->dev); 2136 free_ndev: 2137 free_netdev(ndev); 2138 dev_err(&pdev->dev, "init failed\n"); 2139 2140 return ret; 2141 } 2142 2143 static int netsec_remove(struct platform_device *pdev) 2144 { 2145 struct netsec_priv *priv = platform_get_drvdata(pdev); 2146 2147 unregister_netdev(priv->ndev); 2148 2149 netsec_unregister_mdio(priv); 2150 2151 netif_napi_del(&priv->napi); 2152 2153 pm_runtime_disable(&pdev->dev); 2154 free_netdev(priv->ndev); 2155 2156 return 0; 2157 } 2158 2159 #ifdef CONFIG_PM 2160 static int netsec_runtime_suspend(struct device *dev) 2161 { 2162 struct netsec_priv *priv = dev_get_drvdata(dev); 2163 2164 netsec_write(priv, NETSEC_REG_CLK_EN, 0); 2165 2166 clk_disable_unprepare(priv->clk); 2167 2168 return 0; 2169 } 2170 2171 static int netsec_runtime_resume(struct device *dev) 2172 { 2173 struct netsec_priv *priv = dev_get_drvdata(dev); 2174 2175 clk_prepare_enable(priv->clk); 2176 2177 netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D | 2178 NETSEC_CLK_EN_REG_DOM_C | 2179 NETSEC_CLK_EN_REG_DOM_G); 2180 return 0; 2181 } 2182 #endif 2183 2184 static const struct dev_pm_ops netsec_pm_ops = { 2185 SET_RUNTIME_PM_OPS(netsec_runtime_suspend, netsec_runtime_resume, NULL) 2186 }; 2187 2188 static const struct of_device_id netsec_dt_ids[] = { 2189 { .compatible = "socionext,synquacer-netsec" }, 2190 { } 2191 }; 2192 MODULE_DEVICE_TABLE(of, netsec_dt_ids); 2193 2194 #ifdef CONFIG_ACPI 2195 static const struct acpi_device_id netsec_acpi_ids[] = { 2196 { "SCX0001" }, 2197 { } 2198 }; 2199 MODULE_DEVICE_TABLE(acpi, netsec_acpi_ids); 2200 #endif 2201 2202 static struct platform_driver netsec_driver = { 2203 .probe = netsec_probe, 2204 .remove = netsec_remove, 2205 .driver = { 2206 .name = "netsec", 2207 .pm = &netsec_pm_ops, 2208 .of_match_table = netsec_dt_ids, 2209 .acpi_match_table = ACPI_PTR(netsec_acpi_ids), 2210 }, 2211 }; 2212 module_platform_driver(netsec_driver); 2213 2214 MODULE_AUTHOR("Jassi Brar <jaswinder.singh@linaro.org>"); 2215 MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); 2216 MODULE_DESCRIPTION("NETSEC Ethernet driver"); 2217 MODULE_LICENSE("GPL"); 2218