1 // SPDX-License-Identifier: GPL-2.0+ 2 3 #include <linux/types.h> 4 #include <linux/clk.h> 5 #include <linux/platform_device.h> 6 #include <linux/pm_runtime.h> 7 #include <linux/acpi.h> 8 #include <linux/of_mdio.h> 9 #include <linux/etherdevice.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 13 #include <net/tcp.h> 14 #include <net/ip6_checksum.h> 15 16 #define NETSEC_REG_SOFT_RST 0x104 17 #define NETSEC_REG_COM_INIT 0x120 18 19 #define NETSEC_REG_TOP_STATUS 0x200 20 #define NETSEC_IRQ_RX BIT(1) 21 #define NETSEC_IRQ_TX BIT(0) 22 23 #define NETSEC_REG_TOP_INTEN 0x204 24 #define NETSEC_REG_INTEN_SET 0x234 25 #define NETSEC_REG_INTEN_CLR 0x238 26 27 #define NETSEC_REG_NRM_TX_STATUS 0x400 28 #define NETSEC_REG_NRM_TX_INTEN 0x404 29 #define NETSEC_REG_NRM_TX_INTEN_SET 0x428 30 #define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c 31 #define NRM_TX_ST_NTOWNR BIT(17) 32 #define NRM_TX_ST_TR_ERR BIT(16) 33 #define NRM_TX_ST_TXDONE BIT(15) 34 #define NRM_TX_ST_TMREXP BIT(14) 35 36 #define NETSEC_REG_NRM_RX_STATUS 0x440 37 #define NETSEC_REG_NRM_RX_INTEN 0x444 38 #define NETSEC_REG_NRM_RX_INTEN_SET 0x468 39 #define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c 40 #define NRM_RX_ST_RC_ERR BIT(16) 41 #define NRM_RX_ST_PKTCNT BIT(15) 42 #define NRM_RX_ST_TMREXP BIT(14) 43 44 #define NETSEC_REG_PKT_CMD_BUF 0xd0 45 46 #define NETSEC_REG_CLK_EN 0x100 47 48 #define NETSEC_REG_PKT_CTRL 0x140 49 50 #define NETSEC_REG_DMA_TMR_CTRL 0x20c 51 #define NETSEC_REG_F_TAIKI_MC_VER 0x22c 52 #define NETSEC_REG_F_TAIKI_VER 0x230 53 #define NETSEC_REG_DMA_HM_CTRL 0x214 54 #define NETSEC_REG_DMA_MH_CTRL 0x220 55 #define NETSEC_REG_ADDR_DIS_CORE 0x218 56 #define NETSEC_REG_DMAC_HM_CMD_BUF 0x210 57 #define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c 58 59 #define NETSEC_REG_NRM_TX_PKTCNT 0x410 60 61 #define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414 62 #define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418 63 64 #define NETSEC_REG_NRM_TX_TMR 0x41c 65 66 #define NETSEC_REG_NRM_RX_PKTCNT 0x454 67 #define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458 68 #define NETSEC_REG_NRM_TX_TXINT_TMR 0x420 69 #define NETSEC_REG_NRM_RX_RXINT_TMR 0x460 70 71 #define NETSEC_REG_NRM_RX_TMR 0x45c 72 73 #define NETSEC_REG_NRM_TX_DESC_START_UP 0x434 74 #define NETSEC_REG_NRM_TX_DESC_START_LW 0x408 75 #define NETSEC_REG_NRM_RX_DESC_START_UP 0x474 76 #define NETSEC_REG_NRM_RX_DESC_START_LW 0x448 77 78 #define NETSEC_REG_NRM_TX_CONFIG 0x430 79 #define NETSEC_REG_NRM_RX_CONFIG 0x470 80 81 #define MAC_REG_STATUS 0x1024 82 #define MAC_REG_DATA 0x11c0 83 #define MAC_REG_CMD 0x11c4 84 #define MAC_REG_FLOW_TH 0x11cc 85 #define MAC_REG_INTF_SEL 0x11d4 86 #define MAC_REG_DESC_INIT 0x11fc 87 #define MAC_REG_DESC_SOFT_RST 0x1204 88 #define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500 89 90 #define GMAC_REG_MCR 0x0000 91 #define GMAC_REG_MFFR 0x0004 92 #define GMAC_REG_GAR 0x0010 93 #define GMAC_REG_GDR 0x0014 94 #define GMAC_REG_FCR 0x0018 95 #define GMAC_REG_BMR 0x1000 96 #define GMAC_REG_RDLAR 0x100c 97 #define GMAC_REG_TDLAR 0x1010 98 #define GMAC_REG_OMR 0x1018 99 100 #define MHZ(n) ((n) * 1000 * 1000) 101 102 #define NETSEC_TX_SHIFT_OWN_FIELD 31 103 #define NETSEC_TX_SHIFT_LD_FIELD 30 104 #define NETSEC_TX_SHIFT_DRID_FIELD 24 105 #define NETSEC_TX_SHIFT_PT_FIELD 21 106 #define NETSEC_TX_SHIFT_TDRID_FIELD 16 107 #define NETSEC_TX_SHIFT_CC_FIELD 15 108 #define NETSEC_TX_SHIFT_FS_FIELD 9 109 #define NETSEC_TX_LAST 8 110 #define NETSEC_TX_SHIFT_CO 7 111 #define NETSEC_TX_SHIFT_SO 6 112 #define NETSEC_TX_SHIFT_TRS_FIELD 4 113 114 #define NETSEC_RX_PKT_OWN_FIELD 31 115 #define NETSEC_RX_PKT_LD_FIELD 30 116 #define NETSEC_RX_PKT_SDRID_FIELD 24 117 #define NETSEC_RX_PKT_FR_FIELD 23 118 #define NETSEC_RX_PKT_ER_FIELD 21 119 #define NETSEC_RX_PKT_ERR_FIELD 16 120 #define NETSEC_RX_PKT_TDRID_FIELD 12 121 #define NETSEC_RX_PKT_FS_FIELD 9 122 #define NETSEC_RX_PKT_LS_FIELD 8 123 #define NETSEC_RX_PKT_CO_FIELD 6 124 125 #define NETSEC_RX_PKT_ERR_MASK 3 126 127 #define NETSEC_MAX_TX_PKT_LEN 1518 128 #define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018 129 130 #define NETSEC_RING_GMAC 15 131 #define NETSEC_RING_MAX 2 132 133 #define NETSEC_TCP_SEG_LEN_MAX 1460 134 #define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960 135 136 #define NETSEC_RX_CKSUM_NOTAVAIL 0 137 #define NETSEC_RX_CKSUM_OK 1 138 #define NETSEC_RX_CKSUM_NG 2 139 140 #define NETSEC_TOP_IRQ_REG_CODE_LOAD_END BIT(20) 141 #define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4) 142 143 #define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20) 144 #define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19) 145 146 #define NETSEC_INT_PKTCNT_MAX 2047 147 148 #define NETSEC_FLOW_START_TH_MAX 95 149 #define NETSEC_FLOW_STOP_TH_MAX 95 150 #define NETSEC_FLOW_PAUSE_TIME_MIN 5 151 152 #define NETSEC_CLK_EN_REG_DOM_ALL 0x3f 153 154 #define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28) 155 #define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27) 156 #define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3) 157 #define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2) 158 #define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1) 159 #define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0) 160 161 #define NETSEC_CLK_EN_REG_DOM_G BIT(5) 162 #define NETSEC_CLK_EN_REG_DOM_C BIT(1) 163 #define NETSEC_CLK_EN_REG_DOM_D BIT(0) 164 165 #define NETSEC_COM_INIT_REG_DB BIT(2) 166 #define NETSEC_COM_INIT_REG_CLS BIT(1) 167 #define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \ 168 NETSEC_COM_INIT_REG_DB) 169 170 #define NETSEC_SOFT_RST_REG_RESET 0 171 #define NETSEC_SOFT_RST_REG_RUN BIT(31) 172 173 #define NETSEC_DMA_CTRL_REG_STOP 1 174 #define MH_CTRL__MODE_TRANS BIT(20) 175 176 #define NETSEC_GMAC_CMD_ST_READ 0 177 #define NETSEC_GMAC_CMD_ST_WRITE BIT(28) 178 #define NETSEC_GMAC_CMD_ST_BUSY BIT(31) 179 180 #define NETSEC_GMAC_BMR_REG_COMMON 0x00412080 181 #define NETSEC_GMAC_BMR_REG_RESET 0x00020181 182 #define NETSEC_GMAC_BMR_REG_SWR 0x00000001 183 184 #define NETSEC_GMAC_OMR_REG_ST BIT(13) 185 #define NETSEC_GMAC_OMR_REG_SR BIT(1) 186 187 #define NETSEC_GMAC_MCR_REG_IBN BIT(30) 188 #define NETSEC_GMAC_MCR_REG_CST BIT(25) 189 #define NETSEC_GMAC_MCR_REG_JE BIT(20) 190 #define NETSEC_MCR_PS BIT(15) 191 #define NETSEC_GMAC_MCR_REG_FES BIT(14) 192 #define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c 193 #define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c 194 195 #define NETSEC_FCR_RFE BIT(2) 196 #define NETSEC_FCR_TFE BIT(1) 197 198 #define NETSEC_GMAC_GAR_REG_GW BIT(1) 199 #define NETSEC_GMAC_GAR_REG_GB BIT(0) 200 201 #define NETSEC_GMAC_GAR_REG_SHIFT_PA 11 202 #define NETSEC_GMAC_GAR_REG_SHIFT_GR 6 203 #define GMAC_REG_SHIFT_CR_GAR 2 204 205 #define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2 206 #define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3 207 #define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0 208 #define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1 209 #define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4 210 #define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5 211 212 #define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000 213 #define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000 214 215 #define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000 216 217 #define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31) 218 #define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30) 219 #define NETSEC_REG_DESC_TMR_MODE 4 220 #define NETSEC_REG_DESC_ENDIAN 0 221 222 #define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1 223 #define NETSEC_MAC_DESC_INIT_REG_INIT 1 224 225 #define NETSEC_EEPROM_MAC_ADDRESS 0x00 226 #define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08 227 #define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C 228 #define NETSEC_EEPROM_HM_ME_SIZE 0x10 229 #define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14 230 #define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18 231 #define NETSEC_EEPROM_MH_ME_SIZE 0x1C 232 #define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20 233 #define NETSEC_EEPROM_PKT_ME_SIZE 0x24 234 235 #define DESC_NUM 128 236 #define NAPI_BUDGET (DESC_NUM / 2) 237 238 #define DESC_SZ sizeof(struct netsec_de) 239 240 #define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000) 241 242 enum ring_id { 243 NETSEC_RING_TX = 0, 244 NETSEC_RING_RX 245 }; 246 247 struct netsec_desc { 248 struct sk_buff *skb; 249 dma_addr_t dma_addr; 250 void *addr; 251 u16 len; 252 }; 253 254 struct netsec_desc_ring { 255 dma_addr_t desc_dma; 256 struct netsec_desc *desc; 257 void *vaddr; 258 u16 pkt_cnt; 259 u16 head, tail; 260 }; 261 262 struct netsec_priv { 263 struct netsec_desc_ring desc_ring[NETSEC_RING_MAX]; 264 struct ethtool_coalesce et_coalesce; 265 spinlock_t reglock; /* protect reg access */ 266 struct napi_struct napi; 267 phy_interface_t phy_interface; 268 struct net_device *ndev; 269 struct device_node *phy_np; 270 struct phy_device *phydev; 271 struct mii_bus *mii_bus; 272 void __iomem *ioaddr; 273 void __iomem *eeprom_base; 274 struct device *dev; 275 struct clk *clk; 276 u32 msg_enable; 277 u32 freq; 278 bool rx_cksum_offload_flag; 279 }; 280 281 struct netsec_de { /* Netsec Descriptor layout */ 282 u32 attr; 283 u32 data_buf_addr_up; 284 u32 data_buf_addr_lw; 285 u32 buf_len_info; 286 }; 287 288 struct netsec_tx_pkt_ctrl { 289 u16 tcp_seg_len; 290 bool tcp_seg_offload_flag; 291 bool cksum_offload_flag; 292 }; 293 294 struct netsec_rx_pkt_info { 295 int rx_cksum_result; 296 int err_code; 297 bool err_flag; 298 }; 299 300 static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val) 301 { 302 writel(val, priv->ioaddr + reg_addr); 303 } 304 305 static u32 netsec_read(struct netsec_priv *priv, u32 reg_addr) 306 { 307 return readl(priv->ioaddr + reg_addr); 308 } 309 310 /************* MDIO BUS OPS FOLLOW *************/ 311 312 #define TIMEOUT_SPINS_MAC 1000 313 #define TIMEOUT_SECONDARY_MS_MAC 100 314 315 static u32 netsec_clk_type(u32 freq) 316 { 317 if (freq < MHZ(35)) 318 return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ; 319 if (freq < MHZ(60)) 320 return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ; 321 if (freq < MHZ(100)) 322 return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ; 323 if (freq < MHZ(150)) 324 return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ; 325 if (freq < MHZ(250)) 326 return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ; 327 328 return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ; 329 } 330 331 static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask) 332 { 333 u32 timeout = TIMEOUT_SPINS_MAC; 334 335 while (--timeout && netsec_read(priv, addr) & mask) 336 cpu_relax(); 337 if (timeout) 338 return 0; 339 340 timeout = TIMEOUT_SECONDARY_MS_MAC; 341 while (--timeout && netsec_read(priv, addr) & mask) 342 usleep_range(1000, 2000); 343 344 if (timeout) 345 return 0; 346 347 netdev_WARN(priv->ndev, "%s: timeout\n", __func__); 348 349 return -ETIMEDOUT; 350 } 351 352 static int netsec_mac_write(struct netsec_priv *priv, u32 addr, u32 value) 353 { 354 netsec_write(priv, MAC_REG_DATA, value); 355 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE); 356 return netsec_wait_while_busy(priv, 357 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); 358 } 359 360 static int netsec_mac_read(struct netsec_priv *priv, u32 addr, u32 *read) 361 { 362 int ret; 363 364 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ); 365 ret = netsec_wait_while_busy(priv, 366 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); 367 if (ret) 368 return ret; 369 370 *read = netsec_read(priv, MAC_REG_DATA); 371 372 return 0; 373 } 374 375 static int netsec_mac_wait_while_busy(struct netsec_priv *priv, 376 u32 addr, u32 mask) 377 { 378 u32 timeout = TIMEOUT_SPINS_MAC; 379 int ret, data; 380 381 do { 382 ret = netsec_mac_read(priv, addr, &data); 383 if (ret) 384 break; 385 cpu_relax(); 386 } while (--timeout && (data & mask)); 387 388 if (timeout) 389 return 0; 390 391 timeout = TIMEOUT_SECONDARY_MS_MAC; 392 do { 393 usleep_range(1000, 2000); 394 395 ret = netsec_mac_read(priv, addr, &data); 396 if (ret) 397 break; 398 cpu_relax(); 399 } while (--timeout && (data & mask)); 400 401 if (timeout && !ret) 402 return 0; 403 404 netdev_WARN(priv->ndev, "%s: timeout\n", __func__); 405 406 return -ETIMEDOUT; 407 } 408 409 static int netsec_mac_update_to_phy_state(struct netsec_priv *priv) 410 { 411 struct phy_device *phydev = priv->ndev->phydev; 412 u32 value = 0; 413 414 value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON : 415 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON; 416 417 if (phydev->speed != SPEED_1000) 418 value |= NETSEC_MCR_PS; 419 420 if (priv->phy_interface != PHY_INTERFACE_MODE_GMII && 421 phydev->speed == SPEED_100) 422 value |= NETSEC_GMAC_MCR_REG_FES; 423 424 value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE; 425 426 if (phy_interface_mode_is_rgmii(priv->phy_interface)) 427 value |= NETSEC_GMAC_MCR_REG_IBN; 428 429 if (netsec_mac_write(priv, GMAC_REG_MCR, value)) 430 return -ETIMEDOUT; 431 432 return 0; 433 } 434 435 static int netsec_phy_write(struct mii_bus *bus, 436 int phy_addr, int reg, u16 val) 437 { 438 struct netsec_priv *priv = bus->priv; 439 440 if (netsec_mac_write(priv, GMAC_REG_GDR, val)) 441 return -ETIMEDOUT; 442 if (netsec_mac_write(priv, GMAC_REG_GAR, 443 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | 444 reg << NETSEC_GMAC_GAR_REG_SHIFT_GR | 445 NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB | 446 (netsec_clk_type(priv->freq) << 447 GMAC_REG_SHIFT_CR_GAR))) 448 return -ETIMEDOUT; 449 450 return netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, 451 NETSEC_GMAC_GAR_REG_GB); 452 } 453 454 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr) 455 { 456 struct netsec_priv *priv = bus->priv; 457 u32 data; 458 int ret; 459 460 if (netsec_mac_write(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB | 461 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | 462 reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR | 463 (netsec_clk_type(priv->freq) << 464 GMAC_REG_SHIFT_CR_GAR))) 465 return -ETIMEDOUT; 466 467 ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, 468 NETSEC_GMAC_GAR_REG_GB); 469 if (ret) 470 return ret; 471 472 ret = netsec_mac_read(priv, GMAC_REG_GDR, &data); 473 if (ret) 474 return ret; 475 476 return data; 477 } 478 479 /************* ETHTOOL_OPS FOLLOW *************/ 480 481 static void netsec_et_get_drvinfo(struct net_device *net_device, 482 struct ethtool_drvinfo *info) 483 { 484 strlcpy(info->driver, "netsec", sizeof(info->driver)); 485 strlcpy(info->bus_info, dev_name(net_device->dev.parent), 486 sizeof(info->bus_info)); 487 } 488 489 static int netsec_et_get_coalesce(struct net_device *net_device, 490 struct ethtool_coalesce *et_coalesce) 491 { 492 struct netsec_priv *priv = netdev_priv(net_device); 493 494 *et_coalesce = priv->et_coalesce; 495 496 return 0; 497 } 498 499 static int netsec_et_set_coalesce(struct net_device *net_device, 500 struct ethtool_coalesce *et_coalesce) 501 { 502 struct netsec_priv *priv = netdev_priv(net_device); 503 504 priv->et_coalesce = *et_coalesce; 505 506 if (priv->et_coalesce.tx_coalesce_usecs < 50) 507 priv->et_coalesce.tx_coalesce_usecs = 50; 508 if (priv->et_coalesce.tx_max_coalesced_frames < 1) 509 priv->et_coalesce.tx_max_coalesced_frames = 1; 510 511 netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT, 512 priv->et_coalesce.tx_max_coalesced_frames); 513 netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR, 514 priv->et_coalesce.tx_coalesce_usecs); 515 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE); 516 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP); 517 518 if (priv->et_coalesce.rx_coalesce_usecs < 50) 519 priv->et_coalesce.rx_coalesce_usecs = 50; 520 if (priv->et_coalesce.rx_max_coalesced_frames < 1) 521 priv->et_coalesce.rx_max_coalesced_frames = 1; 522 523 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT, 524 priv->et_coalesce.rx_max_coalesced_frames); 525 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR, 526 priv->et_coalesce.rx_coalesce_usecs); 527 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT); 528 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP); 529 530 return 0; 531 } 532 533 static u32 netsec_et_get_msglevel(struct net_device *dev) 534 { 535 struct netsec_priv *priv = netdev_priv(dev); 536 537 return priv->msg_enable; 538 } 539 540 static void netsec_et_set_msglevel(struct net_device *dev, u32 datum) 541 { 542 struct netsec_priv *priv = netdev_priv(dev); 543 544 priv->msg_enable = datum; 545 } 546 547 static const struct ethtool_ops netsec_ethtool_ops = { 548 .get_drvinfo = netsec_et_get_drvinfo, 549 .get_link_ksettings = phy_ethtool_get_link_ksettings, 550 .set_link_ksettings = phy_ethtool_set_link_ksettings, 551 .get_link = ethtool_op_get_link, 552 .get_coalesce = netsec_et_get_coalesce, 553 .set_coalesce = netsec_et_set_coalesce, 554 .get_msglevel = netsec_et_get_msglevel, 555 .set_msglevel = netsec_et_set_msglevel, 556 }; 557 558 /************* NETDEV_OPS FOLLOW *************/ 559 560 static struct sk_buff *netsec_alloc_skb(struct netsec_priv *priv, 561 struct netsec_desc *desc) 562 { 563 struct sk_buff *skb; 564 565 if (device_get_dma_attr(priv->dev) == DEV_DMA_COHERENT) { 566 skb = netdev_alloc_skb_ip_align(priv->ndev, desc->len); 567 } else { 568 desc->len = L1_CACHE_ALIGN(desc->len); 569 skb = netdev_alloc_skb(priv->ndev, desc->len); 570 } 571 if (!skb) 572 return NULL; 573 574 desc->addr = skb->data; 575 desc->dma_addr = dma_map_single(priv->dev, desc->addr, desc->len, 576 DMA_FROM_DEVICE); 577 if (dma_mapping_error(priv->dev, desc->dma_addr)) { 578 dev_kfree_skb_any(skb); 579 return NULL; 580 } 581 return skb; 582 } 583 584 static void netsec_set_rx_de(struct netsec_priv *priv, 585 struct netsec_desc_ring *dring, u16 idx, 586 const struct netsec_desc *desc, 587 struct sk_buff *skb) 588 { 589 struct netsec_de *de = dring->vaddr + DESC_SZ * idx; 590 u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) | 591 (1 << NETSEC_RX_PKT_FS_FIELD) | 592 (1 << NETSEC_RX_PKT_LS_FIELD); 593 594 if (idx == DESC_NUM - 1) 595 attr |= (1 << NETSEC_RX_PKT_LD_FIELD); 596 597 de->data_buf_addr_up = upper_32_bits(desc->dma_addr); 598 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr); 599 de->buf_len_info = desc->len; 600 de->attr = attr; 601 dma_wmb(); 602 603 dring->desc[idx].dma_addr = desc->dma_addr; 604 dring->desc[idx].addr = desc->addr; 605 dring->desc[idx].len = desc->len; 606 dring->desc[idx].skb = skb; 607 } 608 609 static struct sk_buff *netsec_get_rx_de(struct netsec_priv *priv, 610 struct netsec_desc_ring *dring, 611 u16 idx, 612 struct netsec_rx_pkt_info *rxpi, 613 struct netsec_desc *desc, u16 *len) 614 { 615 struct netsec_de de = {}; 616 617 memcpy(&de, dring->vaddr + DESC_SZ * idx, DESC_SZ); 618 619 *len = de.buf_len_info >> 16; 620 621 rxpi->err_flag = (de.attr >> NETSEC_RX_PKT_ER_FIELD) & 1; 622 rxpi->rx_cksum_result = (de.attr >> NETSEC_RX_PKT_CO_FIELD) & 3; 623 rxpi->err_code = (de.attr >> NETSEC_RX_PKT_ERR_FIELD) & 624 NETSEC_RX_PKT_ERR_MASK; 625 *desc = dring->desc[idx]; 626 return desc->skb; 627 } 628 629 static struct sk_buff *netsec_get_rx_pkt_data(struct netsec_priv *priv, 630 struct netsec_rx_pkt_info *rxpi, 631 struct netsec_desc *desc, 632 u16 *len) 633 { 634 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 635 struct sk_buff *tmp_skb, *skb = NULL; 636 struct netsec_desc td; 637 int tail; 638 639 *rxpi = (struct netsec_rx_pkt_info){}; 640 641 td.len = priv->ndev->mtu + 22; 642 643 tmp_skb = netsec_alloc_skb(priv, &td); 644 645 dma_rmb(); 646 647 tail = dring->tail; 648 649 if (!tmp_skb) { 650 netsec_set_rx_de(priv, dring, tail, &dring->desc[tail], 651 dring->desc[tail].skb); 652 } else { 653 skb = netsec_get_rx_de(priv, dring, tail, rxpi, desc, len); 654 netsec_set_rx_de(priv, dring, tail, &td, tmp_skb); 655 } 656 657 /* move tail ahead */ 658 dring->tail = (dring->tail + 1) % DESC_NUM; 659 660 dring->pkt_cnt--; 661 662 return skb; 663 } 664 665 static int netsec_clean_tx_dring(struct netsec_priv *priv, int budget) 666 { 667 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 668 unsigned int pkts, bytes; 669 670 dring->pkt_cnt += netsec_read(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT); 671 672 if (dring->pkt_cnt < budget) 673 budget = dring->pkt_cnt; 674 675 pkts = 0; 676 bytes = 0; 677 678 while (pkts < budget) { 679 struct netsec_desc *desc; 680 struct netsec_de *entry; 681 int tail, eop; 682 683 tail = dring->tail; 684 685 /* move tail ahead */ 686 dring->tail = (tail + 1) % DESC_NUM; 687 688 desc = &dring->desc[tail]; 689 entry = dring->vaddr + DESC_SZ * tail; 690 691 eop = (entry->attr >> NETSEC_TX_LAST) & 1; 692 693 dma_unmap_single(priv->dev, desc->dma_addr, desc->len, 694 DMA_TO_DEVICE); 695 if (eop) { 696 pkts++; 697 bytes += desc->skb->len; 698 dev_kfree_skb(desc->skb); 699 } 700 *desc = (struct netsec_desc){}; 701 } 702 dring->pkt_cnt -= budget; 703 704 priv->ndev->stats.tx_packets += budget; 705 priv->ndev->stats.tx_bytes += bytes; 706 707 netdev_completed_queue(priv->ndev, budget, bytes); 708 709 return budget; 710 } 711 712 static int netsec_process_tx(struct netsec_priv *priv, int budget) 713 { 714 struct net_device *ndev = priv->ndev; 715 int new, done = 0; 716 717 do { 718 new = netsec_clean_tx_dring(priv, budget); 719 done += new; 720 budget -= new; 721 } while (new); 722 723 if (done && netif_queue_stopped(ndev)) 724 netif_wake_queue(ndev); 725 726 return done; 727 } 728 729 static int netsec_process_rx(struct netsec_priv *priv, int budget) 730 { 731 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 732 struct net_device *ndev = priv->ndev; 733 struct netsec_rx_pkt_info rx_info; 734 int done = 0, rx_num = 0; 735 struct netsec_desc desc; 736 struct sk_buff *skb; 737 u16 len; 738 739 while (done < budget) { 740 if (!rx_num) { 741 rx_num = netsec_read(priv, NETSEC_REG_NRM_RX_PKTCNT); 742 dring->pkt_cnt += rx_num; 743 744 /* move head 'rx_num' */ 745 dring->head = (dring->head + rx_num) % DESC_NUM; 746 747 rx_num = dring->pkt_cnt; 748 if (!rx_num) 749 break; 750 } 751 done++; 752 rx_num--; 753 skb = netsec_get_rx_pkt_data(priv, &rx_info, &desc, &len); 754 if (unlikely(!skb) || rx_info.err_flag) { 755 netif_err(priv, drv, priv->ndev, 756 "%s: rx fail err(%d)\n", 757 __func__, rx_info.err_code); 758 ndev->stats.rx_dropped++; 759 continue; 760 } 761 762 dma_unmap_single(priv->dev, desc.dma_addr, desc.len, 763 DMA_FROM_DEVICE); 764 skb_put(skb, len); 765 skb->protocol = eth_type_trans(skb, priv->ndev); 766 767 if (priv->rx_cksum_offload_flag && 768 rx_info.rx_cksum_result == NETSEC_RX_CKSUM_OK) 769 skb->ip_summed = CHECKSUM_UNNECESSARY; 770 771 if (napi_gro_receive(&priv->napi, skb) != GRO_DROP) { 772 ndev->stats.rx_packets++; 773 ndev->stats.rx_bytes += len; 774 } 775 } 776 777 return done; 778 } 779 780 static int netsec_napi_poll(struct napi_struct *napi, int budget) 781 { 782 struct netsec_priv *priv; 783 int tx, rx, done, todo; 784 785 priv = container_of(napi, struct netsec_priv, napi); 786 787 todo = budget; 788 do { 789 if (!todo) 790 break; 791 792 tx = netsec_process_tx(priv, todo); 793 todo -= tx; 794 795 if (!todo) 796 break; 797 798 rx = netsec_process_rx(priv, todo); 799 todo -= rx; 800 } while (rx || tx); 801 802 done = budget - todo; 803 804 if (done < budget && napi_complete_done(napi, done)) { 805 unsigned long flags; 806 807 spin_lock_irqsave(&priv->reglock, flags); 808 netsec_write(priv, NETSEC_REG_INTEN_SET, 809 NETSEC_IRQ_RX | NETSEC_IRQ_TX); 810 spin_unlock_irqrestore(&priv->reglock, flags); 811 } 812 813 return done; 814 } 815 816 static void netsec_set_tx_de(struct netsec_priv *priv, 817 struct netsec_desc_ring *dring, 818 const struct netsec_tx_pkt_ctrl *tx_ctrl, 819 const struct netsec_desc *desc, 820 struct sk_buff *skb) 821 { 822 int idx = dring->head; 823 struct netsec_de *de; 824 u32 attr; 825 826 de = dring->vaddr + (DESC_SZ * idx); 827 828 attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) | 829 (1 << NETSEC_TX_SHIFT_PT_FIELD) | 830 (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) | 831 (1 << NETSEC_TX_SHIFT_FS_FIELD) | 832 (1 << NETSEC_TX_LAST) | 833 (tx_ctrl->cksum_offload_flag << NETSEC_TX_SHIFT_CO) | 834 (tx_ctrl->tcp_seg_offload_flag << NETSEC_TX_SHIFT_SO) | 835 (1 << NETSEC_TX_SHIFT_TRS_FIELD); 836 if (idx == DESC_NUM - 1) 837 attr |= (1 << NETSEC_TX_SHIFT_LD_FIELD); 838 839 de->data_buf_addr_up = upper_32_bits(desc->dma_addr); 840 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr); 841 de->buf_len_info = (tx_ctrl->tcp_seg_len << 16) | desc->len; 842 de->attr = attr; 843 dma_wmb(); 844 845 dring->desc[idx] = *desc; 846 dring->desc[idx].skb = skb; 847 848 /* move head ahead */ 849 dring->head = (dring->head + 1) % DESC_NUM; 850 } 851 852 static netdev_tx_t netsec_netdev_start_xmit(struct sk_buff *skb, 853 struct net_device *ndev) 854 { 855 struct netsec_priv *priv = netdev_priv(ndev); 856 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 857 struct netsec_tx_pkt_ctrl tx_ctrl = {}; 858 struct netsec_desc tx_desc; 859 u16 tso_seg_len = 0; 860 int filled; 861 862 /* differentiate between full/emtpy ring */ 863 if (dring->head >= dring->tail) 864 filled = dring->head - dring->tail; 865 else 866 filled = dring->head + DESC_NUM - dring->tail; 867 868 if (DESC_NUM - filled < 2) { /* if less than 2 available */ 869 netif_err(priv, drv, priv->ndev, "%s: TxQFull!\n", __func__); 870 netif_stop_queue(priv->ndev); 871 dma_wmb(); 872 return NETDEV_TX_BUSY; 873 } 874 875 if (skb->ip_summed == CHECKSUM_PARTIAL) 876 tx_ctrl.cksum_offload_flag = true; 877 878 if (skb_is_gso(skb)) 879 tso_seg_len = skb_shinfo(skb)->gso_size; 880 881 if (tso_seg_len > 0) { 882 if (skb->protocol == htons(ETH_P_IP)) { 883 ip_hdr(skb)->tot_len = 0; 884 tcp_hdr(skb)->check = 885 ~tcp_v4_check(0, ip_hdr(skb)->saddr, 886 ip_hdr(skb)->daddr, 0); 887 } else { 888 ipv6_hdr(skb)->payload_len = 0; 889 tcp_hdr(skb)->check = 890 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 891 &ipv6_hdr(skb)->daddr, 892 0, IPPROTO_TCP, 0); 893 } 894 895 tx_ctrl.tcp_seg_offload_flag = true; 896 tx_ctrl.tcp_seg_len = tso_seg_len; 897 } 898 899 tx_desc.dma_addr = dma_map_single(priv->dev, skb->data, 900 skb_headlen(skb), DMA_TO_DEVICE); 901 if (dma_mapping_error(priv->dev, tx_desc.dma_addr)) { 902 netif_err(priv, drv, priv->ndev, 903 "%s: DMA mapping failed\n", __func__); 904 ndev->stats.tx_dropped++; 905 dev_kfree_skb_any(skb); 906 return NETDEV_TX_OK; 907 } 908 tx_desc.addr = skb->data; 909 tx_desc.len = skb_headlen(skb); 910 911 skb_tx_timestamp(skb); 912 netdev_sent_queue(priv->ndev, skb->len); 913 914 netsec_set_tx_de(priv, dring, &tx_ctrl, &tx_desc, skb); 915 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */ 916 917 return NETDEV_TX_OK; 918 } 919 920 static void netsec_uninit_pkt_dring(struct netsec_priv *priv, int id) 921 { 922 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 923 struct netsec_desc *desc; 924 u16 idx; 925 926 if (!dring->vaddr || !dring->desc) 927 return; 928 929 for (idx = 0; idx < DESC_NUM; idx++) { 930 desc = &dring->desc[idx]; 931 if (!desc->addr) 932 continue; 933 934 dma_unmap_single(priv->dev, desc->dma_addr, desc->len, 935 id == NETSEC_RING_RX ? DMA_FROM_DEVICE : 936 DMA_TO_DEVICE); 937 dev_kfree_skb(desc->skb); 938 } 939 940 memset(dring->desc, 0, sizeof(struct netsec_desc) * DESC_NUM); 941 memset(dring->vaddr, 0, DESC_SZ * DESC_NUM); 942 943 dring->head = 0; 944 dring->tail = 0; 945 dring->pkt_cnt = 0; 946 } 947 948 static void netsec_free_dring(struct netsec_priv *priv, int id) 949 { 950 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 951 952 if (dring->vaddr) { 953 dma_free_coherent(priv->dev, DESC_SZ * DESC_NUM, 954 dring->vaddr, dring->desc_dma); 955 dring->vaddr = NULL; 956 } 957 958 kfree(dring->desc); 959 dring->desc = NULL; 960 } 961 962 static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id) 963 { 964 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 965 int ret = 0; 966 967 dring->vaddr = dma_zalloc_coherent(priv->dev, DESC_SZ * DESC_NUM, 968 &dring->desc_dma, GFP_KERNEL); 969 if (!dring->vaddr) { 970 ret = -ENOMEM; 971 goto err; 972 } 973 974 dring->desc = kcalloc(DESC_NUM, sizeof(*dring->desc), GFP_KERNEL); 975 if (!dring->desc) { 976 ret = -ENOMEM; 977 goto err; 978 } 979 980 return 0; 981 err: 982 netsec_free_dring(priv, id); 983 984 return ret; 985 } 986 987 static int netsec_setup_rx_dring(struct netsec_priv *priv) 988 { 989 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 990 struct netsec_desc desc; 991 struct sk_buff *skb; 992 int n; 993 994 desc.len = priv->ndev->mtu + 22; 995 996 for (n = 0; n < DESC_NUM; n++) { 997 skb = netsec_alloc_skb(priv, &desc); 998 if (!skb) { 999 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1000 return -ENOMEM; 1001 } 1002 netsec_set_rx_de(priv, dring, n, &desc, skb); 1003 } 1004 1005 return 0; 1006 } 1007 1008 static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg, 1009 u32 addr_h, u32 addr_l, u32 size) 1010 { 1011 u64 base = (u64)addr_h << 32 | addr_l; 1012 void __iomem *ucode; 1013 u32 i; 1014 1015 ucode = ioremap(base, size * sizeof(u32)); 1016 if (!ucode) 1017 return -ENOMEM; 1018 1019 for (i = 0; i < size; i++) 1020 netsec_write(priv, reg, readl(ucode + i * 4)); 1021 1022 iounmap(ucode); 1023 return 0; 1024 } 1025 1026 static int netsec_netdev_load_microcode(struct netsec_priv *priv) 1027 { 1028 u32 addr_h, addr_l, size; 1029 int err; 1030 1031 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_H); 1032 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_L); 1033 size = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_SIZE); 1034 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF, 1035 addr_h, addr_l, size); 1036 if (err) 1037 return err; 1038 1039 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_H); 1040 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_L); 1041 size = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_SIZE); 1042 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF, 1043 addr_h, addr_l, size); 1044 if (err) 1045 return err; 1046 1047 addr_h = 0; 1048 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_ADDRESS); 1049 size = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_SIZE); 1050 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF, 1051 addr_h, addr_l, size); 1052 if (err) 1053 return err; 1054 1055 return 0; 1056 } 1057 1058 static int netsec_reset_hardware(struct netsec_priv *priv, 1059 bool load_ucode) 1060 { 1061 u32 value; 1062 int err; 1063 1064 /* stop DMA engines */ 1065 if (!netsec_read(priv, NETSEC_REG_ADDR_DIS_CORE)) { 1066 netsec_write(priv, NETSEC_REG_DMA_HM_CTRL, 1067 NETSEC_DMA_CTRL_REG_STOP); 1068 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, 1069 NETSEC_DMA_CTRL_REG_STOP); 1070 1071 while (netsec_read(priv, NETSEC_REG_DMA_HM_CTRL) & 1072 NETSEC_DMA_CTRL_REG_STOP) 1073 cpu_relax(); 1074 1075 while (netsec_read(priv, NETSEC_REG_DMA_MH_CTRL) & 1076 NETSEC_DMA_CTRL_REG_STOP) 1077 cpu_relax(); 1078 } 1079 1080 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET); 1081 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN); 1082 netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL); 1083 1084 while (netsec_read(priv, NETSEC_REG_COM_INIT) != 0) 1085 cpu_relax(); 1086 1087 /* set desc_start addr */ 1088 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP, 1089 upper_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); 1090 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW, 1091 lower_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); 1092 1093 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP, 1094 upper_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); 1095 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW, 1096 lower_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); 1097 1098 /* set normal tx dring ring config */ 1099 netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG, 1100 1 << NETSEC_REG_DESC_ENDIAN); 1101 netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG, 1102 1 << NETSEC_REG_DESC_ENDIAN); 1103 1104 if (load_ucode) { 1105 err = netsec_netdev_load_microcode(priv); 1106 if (err) { 1107 netif_err(priv, probe, priv->ndev, 1108 "%s: failed to load microcode (%d)\n", 1109 __func__, err); 1110 return err; 1111 } 1112 } 1113 1114 /* start DMA engines */ 1115 netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1); 1116 netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0); 1117 1118 usleep_range(1000, 2000); 1119 1120 if (!(netsec_read(priv, NETSEC_REG_TOP_STATUS) & 1121 NETSEC_TOP_IRQ_REG_CODE_LOAD_END)) { 1122 netif_err(priv, probe, priv->ndev, 1123 "microengine start failed\n"); 1124 return -ENXIO; 1125 } 1126 netsec_write(priv, NETSEC_REG_TOP_STATUS, 1127 NETSEC_TOP_IRQ_REG_CODE_LOAD_END); 1128 1129 value = NETSEC_PKT_CTRL_REG_MODE_NRM; 1130 if (priv->ndev->mtu > ETH_DATA_LEN) 1131 value |= NETSEC_PKT_CTRL_REG_EN_JUMBO; 1132 1133 /* change to normal mode */ 1134 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS); 1135 netsec_write(priv, NETSEC_REG_PKT_CTRL, value); 1136 1137 while ((netsec_read(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) & 1138 NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) 1139 cpu_relax(); 1140 1141 /* clear any pending EMPTY/ERR irq status */ 1142 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0); 1143 1144 /* Disable TX & RX intr */ 1145 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); 1146 1147 return 0; 1148 } 1149 1150 static int netsec_start_gmac(struct netsec_priv *priv) 1151 { 1152 struct phy_device *phydev = priv->ndev->phydev; 1153 u32 value = 0; 1154 int ret; 1155 1156 if (phydev->speed != SPEED_1000) 1157 value = (NETSEC_GMAC_MCR_REG_CST | 1158 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON); 1159 1160 if (netsec_mac_write(priv, GMAC_REG_MCR, value)) 1161 return -ETIMEDOUT; 1162 if (netsec_mac_write(priv, GMAC_REG_BMR, 1163 NETSEC_GMAC_BMR_REG_RESET)) 1164 return -ETIMEDOUT; 1165 1166 /* Wait soft reset */ 1167 usleep_range(1000, 5000); 1168 1169 ret = netsec_mac_read(priv, GMAC_REG_BMR, &value); 1170 if (ret) 1171 return ret; 1172 if (value & NETSEC_GMAC_BMR_REG_SWR) 1173 return -EAGAIN; 1174 1175 netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1); 1176 if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1)) 1177 return -ETIMEDOUT; 1178 1179 netsec_write(priv, MAC_REG_DESC_INIT, 1); 1180 if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1)) 1181 return -ETIMEDOUT; 1182 1183 if (netsec_mac_write(priv, GMAC_REG_BMR, 1184 NETSEC_GMAC_BMR_REG_COMMON)) 1185 return -ETIMEDOUT; 1186 if (netsec_mac_write(priv, GMAC_REG_RDLAR, 1187 NETSEC_GMAC_RDLAR_REG_COMMON)) 1188 return -ETIMEDOUT; 1189 if (netsec_mac_write(priv, GMAC_REG_TDLAR, 1190 NETSEC_GMAC_TDLAR_REG_COMMON)) 1191 return -ETIMEDOUT; 1192 if (netsec_mac_write(priv, GMAC_REG_MFFR, 0x80000001)) 1193 return -ETIMEDOUT; 1194 1195 ret = netsec_mac_update_to_phy_state(priv); 1196 if (ret) 1197 return ret; 1198 1199 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value); 1200 if (ret) 1201 return ret; 1202 1203 value |= NETSEC_GMAC_OMR_REG_SR; 1204 value |= NETSEC_GMAC_OMR_REG_ST; 1205 1206 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); 1207 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); 1208 1209 netsec_et_set_coalesce(priv->ndev, &priv->et_coalesce); 1210 1211 if (netsec_mac_write(priv, GMAC_REG_OMR, value)) 1212 return -ETIMEDOUT; 1213 1214 return 0; 1215 } 1216 1217 static int netsec_stop_gmac(struct netsec_priv *priv) 1218 { 1219 u32 value; 1220 int ret; 1221 1222 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value); 1223 if (ret) 1224 return ret; 1225 value &= ~NETSEC_GMAC_OMR_REG_SR; 1226 value &= ~NETSEC_GMAC_OMR_REG_ST; 1227 1228 /* disable all interrupts */ 1229 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); 1230 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); 1231 1232 return netsec_mac_write(priv, GMAC_REG_OMR, value); 1233 } 1234 1235 static void netsec_phy_adjust_link(struct net_device *ndev) 1236 { 1237 struct netsec_priv *priv = netdev_priv(ndev); 1238 1239 if (ndev->phydev->link) 1240 netsec_start_gmac(priv); 1241 else 1242 netsec_stop_gmac(priv); 1243 1244 phy_print_status(ndev->phydev); 1245 } 1246 1247 static irqreturn_t netsec_irq_handler(int irq, void *dev_id) 1248 { 1249 struct netsec_priv *priv = dev_id; 1250 u32 val, status = netsec_read(priv, NETSEC_REG_TOP_STATUS); 1251 unsigned long flags; 1252 1253 /* Disable interrupts */ 1254 if (status & NETSEC_IRQ_TX) { 1255 val = netsec_read(priv, NETSEC_REG_NRM_TX_STATUS); 1256 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val); 1257 } 1258 if (status & NETSEC_IRQ_RX) { 1259 val = netsec_read(priv, NETSEC_REG_NRM_RX_STATUS); 1260 netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val); 1261 } 1262 1263 spin_lock_irqsave(&priv->reglock, flags); 1264 netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1265 spin_unlock_irqrestore(&priv->reglock, flags); 1266 1267 napi_schedule(&priv->napi); 1268 1269 return IRQ_HANDLED; 1270 } 1271 1272 static int netsec_netdev_open(struct net_device *ndev) 1273 { 1274 struct netsec_priv *priv = netdev_priv(ndev); 1275 int ret; 1276 1277 pm_runtime_get_sync(priv->dev); 1278 1279 ret = netsec_setup_rx_dring(priv); 1280 if (ret) { 1281 netif_err(priv, probe, priv->ndev, 1282 "%s: fail setup ring\n", __func__); 1283 goto err1; 1284 } 1285 1286 ret = request_irq(priv->ndev->irq, netsec_irq_handler, 1287 IRQF_SHARED, "netsec", priv); 1288 if (ret) { 1289 netif_err(priv, drv, priv->ndev, "request_irq failed\n"); 1290 goto err2; 1291 } 1292 1293 if (dev_of_node(priv->dev)) { 1294 if (!of_phy_connect(priv->ndev, priv->phy_np, 1295 netsec_phy_adjust_link, 0, 1296 priv->phy_interface)) { 1297 netif_err(priv, link, priv->ndev, "missing PHY\n"); 1298 ret = -ENODEV; 1299 goto err3; 1300 } 1301 } else { 1302 ret = phy_connect_direct(priv->ndev, priv->phydev, 1303 netsec_phy_adjust_link, 1304 priv->phy_interface); 1305 if (ret) { 1306 netif_err(priv, link, priv->ndev, 1307 "phy_connect_direct() failed (%d)\n", ret); 1308 goto err3; 1309 } 1310 } 1311 1312 phy_start(ndev->phydev); 1313 1314 netsec_start_gmac(priv); 1315 napi_enable(&priv->napi); 1316 netif_start_queue(ndev); 1317 1318 /* Enable TX+RX intr. */ 1319 netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1320 1321 return 0; 1322 err3: 1323 free_irq(priv->ndev->irq, priv); 1324 err2: 1325 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1326 err1: 1327 pm_runtime_put_sync(priv->dev); 1328 return ret; 1329 } 1330 1331 static int netsec_netdev_stop(struct net_device *ndev) 1332 { 1333 int ret; 1334 struct netsec_priv *priv = netdev_priv(ndev); 1335 1336 netif_stop_queue(priv->ndev); 1337 dma_wmb(); 1338 1339 napi_disable(&priv->napi); 1340 1341 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); 1342 netsec_stop_gmac(priv); 1343 1344 free_irq(priv->ndev->irq, priv); 1345 1346 netsec_uninit_pkt_dring(priv, NETSEC_RING_TX); 1347 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1348 1349 ret = netsec_reset_hardware(priv, false); 1350 1351 phy_stop(ndev->phydev); 1352 phy_disconnect(ndev->phydev); 1353 1354 pm_runtime_put_sync(priv->dev); 1355 1356 return ret; 1357 } 1358 1359 static int netsec_netdev_init(struct net_device *ndev) 1360 { 1361 struct netsec_priv *priv = netdev_priv(ndev); 1362 int ret; 1363 1364 ret = netsec_alloc_dring(priv, NETSEC_RING_TX); 1365 if (ret) 1366 return ret; 1367 1368 ret = netsec_alloc_dring(priv, NETSEC_RING_RX); 1369 if (ret) 1370 goto err1; 1371 1372 ret = netsec_reset_hardware(priv, true); 1373 if (ret) 1374 goto err2; 1375 1376 return 0; 1377 err2: 1378 netsec_free_dring(priv, NETSEC_RING_RX); 1379 err1: 1380 netsec_free_dring(priv, NETSEC_RING_TX); 1381 return ret; 1382 } 1383 1384 static void netsec_netdev_uninit(struct net_device *ndev) 1385 { 1386 struct netsec_priv *priv = netdev_priv(ndev); 1387 1388 netsec_free_dring(priv, NETSEC_RING_RX); 1389 netsec_free_dring(priv, NETSEC_RING_TX); 1390 } 1391 1392 static int netsec_netdev_set_features(struct net_device *ndev, 1393 netdev_features_t features) 1394 { 1395 struct netsec_priv *priv = netdev_priv(ndev); 1396 1397 priv->rx_cksum_offload_flag = !!(features & NETIF_F_RXCSUM); 1398 1399 return 0; 1400 } 1401 1402 static int netsec_netdev_ioctl(struct net_device *ndev, struct ifreq *ifr, 1403 int cmd) 1404 { 1405 return phy_mii_ioctl(ndev->phydev, ifr, cmd); 1406 } 1407 1408 static const struct net_device_ops netsec_netdev_ops = { 1409 .ndo_init = netsec_netdev_init, 1410 .ndo_uninit = netsec_netdev_uninit, 1411 .ndo_open = netsec_netdev_open, 1412 .ndo_stop = netsec_netdev_stop, 1413 .ndo_start_xmit = netsec_netdev_start_xmit, 1414 .ndo_set_features = netsec_netdev_set_features, 1415 .ndo_set_mac_address = eth_mac_addr, 1416 .ndo_validate_addr = eth_validate_addr, 1417 .ndo_do_ioctl = netsec_netdev_ioctl, 1418 }; 1419 1420 static int netsec_of_probe(struct platform_device *pdev, 1421 struct netsec_priv *priv) 1422 { 1423 priv->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); 1424 if (!priv->phy_np) { 1425 dev_err(&pdev->dev, "missing required property 'phy-handle'\n"); 1426 return -EINVAL; 1427 } 1428 1429 priv->clk = devm_clk_get(&pdev->dev, NULL); /* get by 'phy_ref_clk' */ 1430 if (IS_ERR(priv->clk)) { 1431 dev_err(&pdev->dev, "phy_ref_clk not found\n"); 1432 return PTR_ERR(priv->clk); 1433 } 1434 priv->freq = clk_get_rate(priv->clk); 1435 1436 return 0; 1437 } 1438 1439 static int netsec_acpi_probe(struct platform_device *pdev, 1440 struct netsec_priv *priv, u32 *phy_addr) 1441 { 1442 int ret; 1443 1444 if (!IS_ENABLED(CONFIG_ACPI)) 1445 return -ENODEV; 1446 1447 ret = device_property_read_u32(&pdev->dev, "phy-channel", phy_addr); 1448 if (ret) { 1449 dev_err(&pdev->dev, 1450 "missing required property 'phy-channel'\n"); 1451 return ret; 1452 } 1453 1454 ret = device_property_read_u32(&pdev->dev, 1455 "socionext,phy-clock-frequency", 1456 &priv->freq); 1457 if (ret) 1458 dev_err(&pdev->dev, 1459 "missing required property 'socionext,phy-clock-frequency'\n"); 1460 return ret; 1461 } 1462 1463 static void netsec_unregister_mdio(struct netsec_priv *priv) 1464 { 1465 struct phy_device *phydev = priv->phydev; 1466 1467 if (!dev_of_node(priv->dev) && phydev) { 1468 phy_device_remove(phydev); 1469 phy_device_free(phydev); 1470 } 1471 1472 mdiobus_unregister(priv->mii_bus); 1473 } 1474 1475 static int netsec_register_mdio(struct netsec_priv *priv, u32 phy_addr) 1476 { 1477 struct mii_bus *bus; 1478 int ret; 1479 1480 bus = devm_mdiobus_alloc(priv->dev); 1481 if (!bus) 1482 return -ENOMEM; 1483 1484 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(priv->dev)); 1485 bus->priv = priv; 1486 bus->name = "SNI NETSEC MDIO"; 1487 bus->read = netsec_phy_read; 1488 bus->write = netsec_phy_write; 1489 bus->parent = priv->dev; 1490 priv->mii_bus = bus; 1491 1492 if (dev_of_node(priv->dev)) { 1493 struct device_node *mdio_node, *parent = dev_of_node(priv->dev); 1494 1495 mdio_node = of_get_child_by_name(parent, "mdio"); 1496 if (mdio_node) { 1497 parent = mdio_node; 1498 } else { 1499 /* older f/w doesn't populate the mdio subnode, 1500 * allow relaxed upgrade of f/w in due time. 1501 */ 1502 dev_info(priv->dev, "Upgrade f/w for mdio subnode!\n"); 1503 } 1504 1505 ret = of_mdiobus_register(bus, parent); 1506 of_node_put(mdio_node); 1507 1508 if (ret) { 1509 dev_err(priv->dev, "mdiobus register err(%d)\n", ret); 1510 return ret; 1511 } 1512 } else { 1513 /* Mask out all PHYs from auto probing. */ 1514 bus->phy_mask = ~0; 1515 ret = mdiobus_register(bus); 1516 if (ret) { 1517 dev_err(priv->dev, "mdiobus register err(%d)\n", ret); 1518 return ret; 1519 } 1520 1521 priv->phydev = get_phy_device(bus, phy_addr, false); 1522 if (IS_ERR(priv->phydev)) { 1523 ret = PTR_ERR(priv->phydev); 1524 dev_err(priv->dev, "get_phy_device err(%d)\n", ret); 1525 priv->phydev = NULL; 1526 return -ENODEV; 1527 } 1528 1529 ret = phy_device_register(priv->phydev); 1530 if (ret) { 1531 mdiobus_unregister(bus); 1532 dev_err(priv->dev, 1533 "phy_device_register err(%d)\n", ret); 1534 } 1535 } 1536 1537 return ret; 1538 } 1539 1540 static int netsec_probe(struct platform_device *pdev) 1541 { 1542 struct resource *mmio_res, *eeprom_res, *irq_res; 1543 u8 *mac, macbuf[ETH_ALEN]; 1544 struct netsec_priv *priv; 1545 u32 hw_ver, phy_addr = 0; 1546 struct net_device *ndev; 1547 int ret; 1548 1549 mmio_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1550 if (!mmio_res) { 1551 dev_err(&pdev->dev, "No MMIO resource found.\n"); 1552 return -ENODEV; 1553 } 1554 1555 eeprom_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1556 if (!eeprom_res) { 1557 dev_info(&pdev->dev, "No EEPROM resource found.\n"); 1558 return -ENODEV; 1559 } 1560 1561 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1562 if (!irq_res) { 1563 dev_err(&pdev->dev, "No IRQ resource found.\n"); 1564 return -ENODEV; 1565 } 1566 1567 ndev = alloc_etherdev(sizeof(*priv)); 1568 if (!ndev) 1569 return -ENOMEM; 1570 1571 priv = netdev_priv(ndev); 1572 1573 spin_lock_init(&priv->reglock); 1574 SET_NETDEV_DEV(ndev, &pdev->dev); 1575 platform_set_drvdata(pdev, priv); 1576 ndev->irq = irq_res->start; 1577 priv->dev = &pdev->dev; 1578 priv->ndev = ndev; 1579 1580 priv->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | 1581 NETIF_MSG_LINK | NETIF_MSG_PROBE; 1582 1583 priv->phy_interface = device_get_phy_mode(&pdev->dev); 1584 if (priv->phy_interface < 0) { 1585 dev_err(&pdev->dev, "missing required property 'phy-mode'\n"); 1586 ret = -ENODEV; 1587 goto free_ndev; 1588 } 1589 1590 priv->ioaddr = devm_ioremap(&pdev->dev, mmio_res->start, 1591 resource_size(mmio_res)); 1592 if (!priv->ioaddr) { 1593 dev_err(&pdev->dev, "devm_ioremap() failed\n"); 1594 ret = -ENXIO; 1595 goto free_ndev; 1596 } 1597 1598 priv->eeprom_base = devm_ioremap(&pdev->dev, eeprom_res->start, 1599 resource_size(eeprom_res)); 1600 if (!priv->eeprom_base) { 1601 dev_err(&pdev->dev, "devm_ioremap() failed for EEPROM\n"); 1602 ret = -ENXIO; 1603 goto free_ndev; 1604 } 1605 1606 mac = device_get_mac_address(&pdev->dev, macbuf, sizeof(macbuf)); 1607 if (mac) 1608 ether_addr_copy(ndev->dev_addr, mac); 1609 1610 if (priv->eeprom_base && 1611 (!mac || !is_valid_ether_addr(ndev->dev_addr))) { 1612 void __iomem *macp = priv->eeprom_base + 1613 NETSEC_EEPROM_MAC_ADDRESS; 1614 1615 ndev->dev_addr[0] = readb(macp + 3); 1616 ndev->dev_addr[1] = readb(macp + 2); 1617 ndev->dev_addr[2] = readb(macp + 1); 1618 ndev->dev_addr[3] = readb(macp + 0); 1619 ndev->dev_addr[4] = readb(macp + 7); 1620 ndev->dev_addr[5] = readb(macp + 6); 1621 } 1622 1623 if (!is_valid_ether_addr(ndev->dev_addr)) { 1624 dev_warn(&pdev->dev, "No MAC address found, using random\n"); 1625 eth_hw_addr_random(ndev); 1626 } 1627 1628 if (dev_of_node(&pdev->dev)) 1629 ret = netsec_of_probe(pdev, priv); 1630 else 1631 ret = netsec_acpi_probe(pdev, priv, &phy_addr); 1632 if (ret) 1633 goto free_ndev; 1634 1635 if (!priv->freq) { 1636 dev_err(&pdev->dev, "missing PHY reference clock frequency\n"); 1637 ret = -ENODEV; 1638 goto free_ndev; 1639 } 1640 1641 /* default for throughput */ 1642 priv->et_coalesce.rx_coalesce_usecs = 500; 1643 priv->et_coalesce.rx_max_coalesced_frames = 8; 1644 priv->et_coalesce.tx_coalesce_usecs = 500; 1645 priv->et_coalesce.tx_max_coalesced_frames = 8; 1646 1647 ret = device_property_read_u32(&pdev->dev, "max-frame-size", 1648 &ndev->max_mtu); 1649 if (ret < 0) 1650 ndev->max_mtu = ETH_DATA_LEN; 1651 1652 /* runtime_pm coverage just for probe, open/close also cover it */ 1653 pm_runtime_enable(&pdev->dev); 1654 pm_runtime_get_sync(&pdev->dev); 1655 1656 hw_ver = netsec_read(priv, NETSEC_REG_F_TAIKI_VER); 1657 /* this driver only supports F_TAIKI style NETSEC */ 1658 if (NETSEC_F_NETSEC_VER_MAJOR_NUM(hw_ver) != 1659 NETSEC_F_NETSEC_VER_MAJOR_NUM(NETSEC_REG_NETSEC_VER_F_TAIKI)) { 1660 ret = -ENODEV; 1661 goto pm_disable; 1662 } 1663 1664 dev_info(&pdev->dev, "hardware revision %d.%d\n", 1665 hw_ver >> 16, hw_ver & 0xffff); 1666 1667 netif_napi_add(ndev, &priv->napi, netsec_napi_poll, NAPI_BUDGET); 1668 1669 ndev->netdev_ops = &netsec_netdev_ops; 1670 ndev->ethtool_ops = &netsec_ethtool_ops; 1671 1672 ndev->features |= NETIF_F_HIGHDMA | NETIF_F_RXCSUM | NETIF_F_GSO | 1673 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1674 ndev->hw_features = ndev->features; 1675 1676 priv->rx_cksum_offload_flag = true; 1677 1678 ret = netsec_register_mdio(priv, phy_addr); 1679 if (ret) 1680 goto unreg_napi; 1681 1682 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40))) 1683 dev_warn(&pdev->dev, "Failed to set DMA mask\n"); 1684 1685 ret = register_netdev(ndev); 1686 if (ret) { 1687 netif_err(priv, probe, ndev, "register_netdev() failed\n"); 1688 goto unreg_mii; 1689 } 1690 1691 pm_runtime_put_sync(&pdev->dev); 1692 return 0; 1693 1694 unreg_mii: 1695 netsec_unregister_mdio(priv); 1696 unreg_napi: 1697 netif_napi_del(&priv->napi); 1698 pm_disable: 1699 pm_runtime_put_sync(&pdev->dev); 1700 pm_runtime_disable(&pdev->dev); 1701 free_ndev: 1702 free_netdev(ndev); 1703 dev_err(&pdev->dev, "init failed\n"); 1704 1705 return ret; 1706 } 1707 1708 static int netsec_remove(struct platform_device *pdev) 1709 { 1710 struct netsec_priv *priv = platform_get_drvdata(pdev); 1711 1712 unregister_netdev(priv->ndev); 1713 1714 netsec_unregister_mdio(priv); 1715 1716 netif_napi_del(&priv->napi); 1717 1718 pm_runtime_disable(&pdev->dev); 1719 free_netdev(priv->ndev); 1720 1721 return 0; 1722 } 1723 1724 #ifdef CONFIG_PM 1725 static int netsec_runtime_suspend(struct device *dev) 1726 { 1727 struct netsec_priv *priv = dev_get_drvdata(dev); 1728 1729 netsec_write(priv, NETSEC_REG_CLK_EN, 0); 1730 1731 clk_disable_unprepare(priv->clk); 1732 1733 return 0; 1734 } 1735 1736 static int netsec_runtime_resume(struct device *dev) 1737 { 1738 struct netsec_priv *priv = dev_get_drvdata(dev); 1739 1740 clk_prepare_enable(priv->clk); 1741 1742 netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D | 1743 NETSEC_CLK_EN_REG_DOM_C | 1744 NETSEC_CLK_EN_REG_DOM_G); 1745 return 0; 1746 } 1747 #endif 1748 1749 static const struct dev_pm_ops netsec_pm_ops = { 1750 SET_RUNTIME_PM_OPS(netsec_runtime_suspend, netsec_runtime_resume, NULL) 1751 }; 1752 1753 static const struct of_device_id netsec_dt_ids[] = { 1754 { .compatible = "socionext,synquacer-netsec" }, 1755 { } 1756 }; 1757 MODULE_DEVICE_TABLE(of, netsec_dt_ids); 1758 1759 #ifdef CONFIG_ACPI 1760 static const struct acpi_device_id netsec_acpi_ids[] = { 1761 { "SCX0001" }, 1762 { } 1763 }; 1764 MODULE_DEVICE_TABLE(acpi, netsec_acpi_ids); 1765 #endif 1766 1767 static struct platform_driver netsec_driver = { 1768 .probe = netsec_probe, 1769 .remove = netsec_remove, 1770 .driver = { 1771 .name = "netsec", 1772 .pm = &netsec_pm_ops, 1773 .of_match_table = netsec_dt_ids, 1774 .acpi_match_table = ACPI_PTR(netsec_acpi_ids), 1775 }, 1776 }; 1777 module_platform_driver(netsec_driver); 1778 1779 MODULE_AUTHOR("Jassi Brar <jaswinder.singh@linaro.org>"); 1780 MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); 1781 MODULE_DESCRIPTION("NETSEC Ethernet driver"); 1782 MODULE_LICENSE("GPL"); 1783