1 /*************************************************************************** 2 * 3 * Copyright (C) 2007,2008 SMSC 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 18 * 19 *************************************************************************** 20 */ 21 22 #include <linux/interrupt.h> 23 #include <linux/kernel.h> 24 #include <linux/netdevice.h> 25 #include <linux/phy.h> 26 #include <linux/pci.h> 27 #include <linux/if_vlan.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/crc32.h> 30 #include <linux/slab.h> 31 #include <linux/module.h> 32 #include <asm/unaligned.h> 33 #include "smsc9420.h" 34 35 #define DRV_NAME "smsc9420" 36 #define PFX DRV_NAME ": " 37 #define DRV_MDIONAME "smsc9420-mdio" 38 #define DRV_DESCRIPTION "SMSC LAN9420 driver" 39 #define DRV_VERSION "1.01" 40 41 MODULE_LICENSE("GPL"); 42 MODULE_VERSION(DRV_VERSION); 43 44 struct smsc9420_dma_desc { 45 u32 status; 46 u32 length; 47 u32 buffer1; 48 u32 buffer2; 49 }; 50 51 struct smsc9420_ring_info { 52 struct sk_buff *skb; 53 dma_addr_t mapping; 54 }; 55 56 struct smsc9420_pdata { 57 void __iomem *ioaddr; 58 struct pci_dev *pdev; 59 struct net_device *dev; 60 61 struct smsc9420_dma_desc *rx_ring; 62 struct smsc9420_dma_desc *tx_ring; 63 struct smsc9420_ring_info *tx_buffers; 64 struct smsc9420_ring_info *rx_buffers; 65 dma_addr_t rx_dma_addr; 66 dma_addr_t tx_dma_addr; 67 int tx_ring_head, tx_ring_tail; 68 int rx_ring_head, rx_ring_tail; 69 70 spinlock_t int_lock; 71 spinlock_t phy_lock; 72 73 struct napi_struct napi; 74 75 bool software_irq_signal; 76 bool rx_csum; 77 u32 msg_enable; 78 79 struct phy_device *phy_dev; 80 struct mii_bus *mii_bus; 81 int phy_irq[PHY_MAX_ADDR]; 82 int last_duplex; 83 int last_carrier; 84 }; 85 86 static DEFINE_PCI_DEVICE_TABLE(smsc9420_id_table) = { 87 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, }, 88 { 0, } 89 }; 90 91 MODULE_DEVICE_TABLE(pci, smsc9420_id_table); 92 93 #define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 94 95 static uint smsc_debug; 96 static uint debug = -1; 97 module_param(debug, uint, 0); 98 MODULE_PARM_DESC(debug, "debug level"); 99 100 #define smsc_dbg(TYPE, f, a...) \ 101 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \ 102 printk(KERN_DEBUG PFX f "\n", ## a); \ 103 } while (0) 104 105 #define smsc_info(TYPE, f, a...) \ 106 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \ 107 printk(KERN_INFO PFX f "\n", ## a); \ 108 } while (0) 109 110 #define smsc_warn(TYPE, f, a...) \ 111 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \ 112 printk(KERN_WARNING PFX f "\n", ## a); \ 113 } while (0) 114 115 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset) 116 { 117 return ioread32(pd->ioaddr + offset); 118 } 119 120 static inline void 121 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value) 122 { 123 iowrite32(value, pd->ioaddr + offset); 124 } 125 126 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd) 127 { 128 /* to ensure PCI write completion, we must perform a PCI read */ 129 smsc9420_reg_read(pd, ID_REV); 130 } 131 132 static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx) 133 { 134 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv; 135 unsigned long flags; 136 u32 addr; 137 int i, reg = -EIO; 138 139 spin_lock_irqsave(&pd->phy_lock, flags); 140 141 /* confirm MII not busy */ 142 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) { 143 smsc_warn(DRV, "MII is busy???"); 144 goto out; 145 } 146 147 /* set the address, index & direction (read from PHY) */ 148 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | 149 MII_ACCESS_MII_READ_; 150 smsc9420_reg_write(pd, MII_ACCESS, addr); 151 152 /* wait for read to complete with 50us timeout */ 153 for (i = 0; i < 5; i++) { 154 if (!(smsc9420_reg_read(pd, MII_ACCESS) & 155 MII_ACCESS_MII_BUSY_)) { 156 reg = (u16)smsc9420_reg_read(pd, MII_DATA); 157 goto out; 158 } 159 udelay(10); 160 } 161 162 smsc_warn(DRV, "MII busy timeout!"); 163 164 out: 165 spin_unlock_irqrestore(&pd->phy_lock, flags); 166 return reg; 167 } 168 169 static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx, 170 u16 val) 171 { 172 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv; 173 unsigned long flags; 174 u32 addr; 175 int i, reg = -EIO; 176 177 spin_lock_irqsave(&pd->phy_lock, flags); 178 179 /* confirm MII not busy */ 180 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) { 181 smsc_warn(DRV, "MII is busy???"); 182 goto out; 183 } 184 185 /* put the data to write in the MAC */ 186 smsc9420_reg_write(pd, MII_DATA, (u32)val); 187 188 /* set the address, index & direction (write to PHY) */ 189 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | 190 MII_ACCESS_MII_WRITE_; 191 smsc9420_reg_write(pd, MII_ACCESS, addr); 192 193 /* wait for write to complete with 50us timeout */ 194 for (i = 0; i < 5; i++) { 195 if (!(smsc9420_reg_read(pd, MII_ACCESS) & 196 MII_ACCESS_MII_BUSY_)) { 197 reg = 0; 198 goto out; 199 } 200 udelay(10); 201 } 202 203 smsc_warn(DRV, "MII busy timeout!"); 204 205 out: 206 spin_unlock_irqrestore(&pd->phy_lock, flags); 207 return reg; 208 } 209 210 /* Returns hash bit number for given MAC address 211 * Example: 212 * 01 00 5E 00 00 01 -> returns bit number 31 */ 213 static u32 smsc9420_hash(u8 addr[ETH_ALEN]) 214 { 215 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; 216 } 217 218 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd) 219 { 220 int timeout = 100000; 221 222 BUG_ON(!pd); 223 224 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) { 225 smsc_dbg(DRV, "smsc9420_eeprom_reload: Eeprom busy"); 226 return -EIO; 227 } 228 229 smsc9420_reg_write(pd, E2P_CMD, 230 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_)); 231 232 do { 233 udelay(10); 234 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_)) 235 return 0; 236 } while (timeout--); 237 238 smsc_warn(DRV, "smsc9420_eeprom_reload: Eeprom timed out"); 239 return -EIO; 240 } 241 242 /* Standard ioctls for mii-tool */ 243 static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 244 { 245 struct smsc9420_pdata *pd = netdev_priv(dev); 246 247 if (!netif_running(dev) || !pd->phy_dev) 248 return -EINVAL; 249 250 return phy_mii_ioctl(pd->phy_dev, ifr, cmd); 251 } 252 253 static int smsc9420_ethtool_get_settings(struct net_device *dev, 254 struct ethtool_cmd *cmd) 255 { 256 struct smsc9420_pdata *pd = netdev_priv(dev); 257 258 if (!pd->phy_dev) 259 return -ENODEV; 260 261 cmd->maxtxpkt = 1; 262 cmd->maxrxpkt = 1; 263 return phy_ethtool_gset(pd->phy_dev, cmd); 264 } 265 266 static int smsc9420_ethtool_set_settings(struct net_device *dev, 267 struct ethtool_cmd *cmd) 268 { 269 struct smsc9420_pdata *pd = netdev_priv(dev); 270 271 if (!pd->phy_dev) 272 return -ENODEV; 273 274 return phy_ethtool_sset(pd->phy_dev, cmd); 275 } 276 277 static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev, 278 struct ethtool_drvinfo *drvinfo) 279 { 280 struct smsc9420_pdata *pd = netdev_priv(netdev); 281 282 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver)); 283 strlcpy(drvinfo->bus_info, pci_name(pd->pdev), 284 sizeof(drvinfo->bus_info)); 285 strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version)); 286 } 287 288 static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev) 289 { 290 struct smsc9420_pdata *pd = netdev_priv(netdev); 291 return pd->msg_enable; 292 } 293 294 static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data) 295 { 296 struct smsc9420_pdata *pd = netdev_priv(netdev); 297 pd->msg_enable = data; 298 } 299 300 static int smsc9420_ethtool_nway_reset(struct net_device *netdev) 301 { 302 struct smsc9420_pdata *pd = netdev_priv(netdev); 303 304 if (!pd->phy_dev) 305 return -ENODEV; 306 307 return phy_start_aneg(pd->phy_dev); 308 } 309 310 static int smsc9420_ethtool_getregslen(struct net_device *dev) 311 { 312 /* all smsc9420 registers plus all phy registers */ 313 return 0x100 + (32 * sizeof(u32)); 314 } 315 316 static void 317 smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs, 318 void *buf) 319 { 320 struct smsc9420_pdata *pd = netdev_priv(dev); 321 struct phy_device *phy_dev = pd->phy_dev; 322 unsigned int i, j = 0; 323 u32 *data = buf; 324 325 regs->version = smsc9420_reg_read(pd, ID_REV); 326 for (i = 0; i < 0x100; i += (sizeof(u32))) 327 data[j++] = smsc9420_reg_read(pd, i); 328 329 // cannot read phy registers if the net device is down 330 if (!phy_dev) 331 return; 332 333 for (i = 0; i <= 31; i++) 334 data[j++] = smsc9420_mii_read(phy_dev->bus, phy_dev->addr, i); 335 } 336 337 static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd) 338 { 339 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG); 340 temp &= ~GPIO_CFG_EEPR_EN_; 341 smsc9420_reg_write(pd, GPIO_CFG, temp); 342 msleep(1); 343 } 344 345 static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op) 346 { 347 int timeout = 100; 348 u32 e2cmd; 349 350 smsc_dbg(HW, "op 0x%08x", op); 351 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) { 352 smsc_warn(HW, "Busy at start"); 353 return -EBUSY; 354 } 355 356 e2cmd = op | E2P_CMD_EPC_BUSY_; 357 smsc9420_reg_write(pd, E2P_CMD, e2cmd); 358 359 do { 360 msleep(1); 361 e2cmd = smsc9420_reg_read(pd, E2P_CMD); 362 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout)); 363 364 if (!timeout) { 365 smsc_info(HW, "TIMED OUT"); 366 return -EAGAIN; 367 } 368 369 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) { 370 smsc_info(HW, "Error occurred during eeprom operation"); 371 return -EINVAL; 372 } 373 374 return 0; 375 } 376 377 static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd, 378 u8 address, u8 *data) 379 { 380 u32 op = E2P_CMD_EPC_CMD_READ_ | address; 381 int ret; 382 383 smsc_dbg(HW, "address 0x%x", address); 384 ret = smsc9420_eeprom_send_cmd(pd, op); 385 386 if (!ret) 387 data[address] = smsc9420_reg_read(pd, E2P_DATA); 388 389 return ret; 390 } 391 392 static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd, 393 u8 address, u8 data) 394 { 395 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address; 396 int ret; 397 398 smsc_dbg(HW, "address 0x%x, data 0x%x", address, data); 399 ret = smsc9420_eeprom_send_cmd(pd, op); 400 401 if (!ret) { 402 op = E2P_CMD_EPC_CMD_WRITE_ | address; 403 smsc9420_reg_write(pd, E2P_DATA, (u32)data); 404 ret = smsc9420_eeprom_send_cmd(pd, op); 405 } 406 407 return ret; 408 } 409 410 static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev) 411 { 412 return SMSC9420_EEPROM_SIZE; 413 } 414 415 static int smsc9420_ethtool_get_eeprom(struct net_device *dev, 416 struct ethtool_eeprom *eeprom, u8 *data) 417 { 418 struct smsc9420_pdata *pd = netdev_priv(dev); 419 u8 eeprom_data[SMSC9420_EEPROM_SIZE]; 420 int len, i; 421 422 smsc9420_eeprom_enable_access(pd); 423 424 len = min(eeprom->len, SMSC9420_EEPROM_SIZE); 425 for (i = 0; i < len; i++) { 426 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data); 427 if (ret < 0) { 428 eeprom->len = 0; 429 return ret; 430 } 431 } 432 433 memcpy(data, &eeprom_data[eeprom->offset], len); 434 eeprom->magic = SMSC9420_EEPROM_MAGIC; 435 eeprom->len = len; 436 return 0; 437 } 438 439 static int smsc9420_ethtool_set_eeprom(struct net_device *dev, 440 struct ethtool_eeprom *eeprom, u8 *data) 441 { 442 struct smsc9420_pdata *pd = netdev_priv(dev); 443 int ret; 444 445 if (eeprom->magic != SMSC9420_EEPROM_MAGIC) 446 return -EINVAL; 447 448 smsc9420_eeprom_enable_access(pd); 449 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_); 450 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data); 451 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_); 452 453 /* Single byte write, according to man page */ 454 eeprom->len = 1; 455 456 return ret; 457 } 458 459 static const struct ethtool_ops smsc9420_ethtool_ops = { 460 .get_settings = smsc9420_ethtool_get_settings, 461 .set_settings = smsc9420_ethtool_set_settings, 462 .get_drvinfo = smsc9420_ethtool_get_drvinfo, 463 .get_msglevel = smsc9420_ethtool_get_msglevel, 464 .set_msglevel = smsc9420_ethtool_set_msglevel, 465 .nway_reset = smsc9420_ethtool_nway_reset, 466 .get_link = ethtool_op_get_link, 467 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len, 468 .get_eeprom = smsc9420_ethtool_get_eeprom, 469 .set_eeprom = smsc9420_ethtool_set_eeprom, 470 .get_regs_len = smsc9420_ethtool_getregslen, 471 .get_regs = smsc9420_ethtool_getregs, 472 .get_ts_info = ethtool_op_get_ts_info, 473 }; 474 475 /* Sets the device MAC address to dev_addr */ 476 static void smsc9420_set_mac_address(struct net_device *dev) 477 { 478 struct smsc9420_pdata *pd = netdev_priv(dev); 479 u8 *dev_addr = dev->dev_addr; 480 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4]; 481 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | 482 (dev_addr[1] << 8) | dev_addr[0]; 483 484 smsc9420_reg_write(pd, ADDRH, mac_high16); 485 smsc9420_reg_write(pd, ADDRL, mac_low32); 486 } 487 488 static void smsc9420_check_mac_address(struct net_device *dev) 489 { 490 struct smsc9420_pdata *pd = netdev_priv(dev); 491 492 /* Check if mac address has been specified when bringing interface up */ 493 if (is_valid_ether_addr(dev->dev_addr)) { 494 smsc9420_set_mac_address(dev); 495 smsc_dbg(PROBE, "MAC Address is specified by configuration"); 496 } else { 497 /* Try reading mac address from device. if EEPROM is present 498 * it will already have been set */ 499 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH); 500 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL); 501 dev->dev_addr[0] = (u8)(mac_low32); 502 dev->dev_addr[1] = (u8)(mac_low32 >> 8); 503 dev->dev_addr[2] = (u8)(mac_low32 >> 16); 504 dev->dev_addr[3] = (u8)(mac_low32 >> 24); 505 dev->dev_addr[4] = (u8)(mac_high16); 506 dev->dev_addr[5] = (u8)(mac_high16 >> 8); 507 508 if (is_valid_ether_addr(dev->dev_addr)) { 509 /* eeprom values are valid so use them */ 510 smsc_dbg(PROBE, "Mac Address is read from EEPROM"); 511 } else { 512 /* eeprom values are invalid, generate random MAC */ 513 eth_hw_addr_random(dev); 514 smsc9420_set_mac_address(dev); 515 smsc_dbg(PROBE, "MAC Address is set to random"); 516 } 517 } 518 } 519 520 static void smsc9420_stop_tx(struct smsc9420_pdata *pd) 521 { 522 u32 dmac_control, mac_cr, dma_intr_ena; 523 int timeout = 1000; 524 525 /* disable TX DMAC */ 526 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); 527 dmac_control &= (~DMAC_CONTROL_ST_); 528 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); 529 530 /* Wait max 10ms for transmit process to stop */ 531 while (--timeout) { 532 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_) 533 break; 534 udelay(10); 535 } 536 537 if (!timeout) 538 smsc_warn(IFDOWN, "TX DMAC failed to stop"); 539 540 /* ACK Tx DMAC stop bit */ 541 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_); 542 543 /* mask TX DMAC interrupts */ 544 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 545 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_); 546 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 547 smsc9420_pci_flush_write(pd); 548 549 /* stop MAC TX */ 550 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_); 551 smsc9420_reg_write(pd, MAC_CR, mac_cr); 552 smsc9420_pci_flush_write(pd); 553 } 554 555 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd) 556 { 557 int i; 558 559 BUG_ON(!pd->tx_ring); 560 561 if (!pd->tx_buffers) 562 return; 563 564 for (i = 0; i < TX_RING_SIZE; i++) { 565 struct sk_buff *skb = pd->tx_buffers[i].skb; 566 567 if (skb) { 568 BUG_ON(!pd->tx_buffers[i].mapping); 569 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping, 570 skb->len, PCI_DMA_TODEVICE); 571 dev_kfree_skb_any(skb); 572 } 573 574 pd->tx_ring[i].status = 0; 575 pd->tx_ring[i].length = 0; 576 pd->tx_ring[i].buffer1 = 0; 577 pd->tx_ring[i].buffer2 = 0; 578 } 579 wmb(); 580 581 kfree(pd->tx_buffers); 582 pd->tx_buffers = NULL; 583 584 pd->tx_ring_head = 0; 585 pd->tx_ring_tail = 0; 586 } 587 588 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd) 589 { 590 int i; 591 592 BUG_ON(!pd->rx_ring); 593 594 if (!pd->rx_buffers) 595 return; 596 597 for (i = 0; i < RX_RING_SIZE; i++) { 598 if (pd->rx_buffers[i].skb) 599 dev_kfree_skb_any(pd->rx_buffers[i].skb); 600 601 if (pd->rx_buffers[i].mapping) 602 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping, 603 PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 604 605 pd->rx_ring[i].status = 0; 606 pd->rx_ring[i].length = 0; 607 pd->rx_ring[i].buffer1 = 0; 608 pd->rx_ring[i].buffer2 = 0; 609 } 610 wmb(); 611 612 kfree(pd->rx_buffers); 613 pd->rx_buffers = NULL; 614 615 pd->rx_ring_head = 0; 616 pd->rx_ring_tail = 0; 617 } 618 619 static void smsc9420_stop_rx(struct smsc9420_pdata *pd) 620 { 621 int timeout = 1000; 622 u32 mac_cr, dmac_control, dma_intr_ena; 623 624 /* mask RX DMAC interrupts */ 625 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 626 dma_intr_ena &= (~DMAC_INTR_ENA_RX_); 627 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 628 smsc9420_pci_flush_write(pd); 629 630 /* stop RX MAC prior to stoping DMA */ 631 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_); 632 smsc9420_reg_write(pd, MAC_CR, mac_cr); 633 smsc9420_pci_flush_write(pd); 634 635 /* stop RX DMAC */ 636 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); 637 dmac_control &= (~DMAC_CONTROL_SR_); 638 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); 639 smsc9420_pci_flush_write(pd); 640 641 /* wait up to 10ms for receive to stop */ 642 while (--timeout) { 643 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_) 644 break; 645 udelay(10); 646 } 647 648 if (!timeout) 649 smsc_warn(IFDOWN, "RX DMAC did not stop! timeout."); 650 651 /* ACK the Rx DMAC stop bit */ 652 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_); 653 } 654 655 static irqreturn_t smsc9420_isr(int irq, void *dev_id) 656 { 657 struct smsc9420_pdata *pd = dev_id; 658 u32 int_cfg, int_sts, int_ctl; 659 irqreturn_t ret = IRQ_NONE; 660 ulong flags; 661 662 BUG_ON(!pd); 663 BUG_ON(!pd->ioaddr); 664 665 int_cfg = smsc9420_reg_read(pd, INT_CFG); 666 667 /* check if it's our interrupt */ 668 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) != 669 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) 670 return IRQ_NONE; 671 672 int_sts = smsc9420_reg_read(pd, INT_STAT); 673 674 if (likely(INT_STAT_DMAC_INT_ & int_sts)) { 675 u32 status = smsc9420_reg_read(pd, DMAC_STATUS); 676 u32 ints_to_clear = 0; 677 678 if (status & DMAC_STS_TX_) { 679 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_); 680 netif_wake_queue(pd->dev); 681 } 682 683 if (status & DMAC_STS_RX_) { 684 /* mask RX DMAC interrupts */ 685 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 686 dma_intr_ena &= (~DMAC_INTR_ENA_RX_); 687 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 688 smsc9420_pci_flush_write(pd); 689 690 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_); 691 napi_schedule(&pd->napi); 692 } 693 694 if (ints_to_clear) 695 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear); 696 697 ret = IRQ_HANDLED; 698 } 699 700 if (unlikely(INT_STAT_SW_INT_ & int_sts)) { 701 /* mask software interrupt */ 702 spin_lock_irqsave(&pd->int_lock, flags); 703 int_ctl = smsc9420_reg_read(pd, INT_CTL); 704 int_ctl &= (~INT_CTL_SW_INT_EN_); 705 smsc9420_reg_write(pd, INT_CTL, int_ctl); 706 spin_unlock_irqrestore(&pd->int_lock, flags); 707 708 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_); 709 pd->software_irq_signal = true; 710 smp_wmb(); 711 712 ret = IRQ_HANDLED; 713 } 714 715 /* to ensure PCI write completion, we must perform a PCI read */ 716 smsc9420_pci_flush_write(pd); 717 718 return ret; 719 } 720 721 #ifdef CONFIG_NET_POLL_CONTROLLER 722 static void smsc9420_poll_controller(struct net_device *dev) 723 { 724 struct smsc9420_pdata *pd = netdev_priv(dev); 725 const int irq = pd->pdev->irq; 726 727 disable_irq(irq); 728 smsc9420_isr(0, dev); 729 enable_irq(irq); 730 } 731 #endif /* CONFIG_NET_POLL_CONTROLLER */ 732 733 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd) 734 { 735 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_); 736 smsc9420_reg_read(pd, BUS_MODE); 737 udelay(2); 738 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_) 739 smsc_warn(DRV, "Software reset not cleared"); 740 } 741 742 static int smsc9420_stop(struct net_device *dev) 743 { 744 struct smsc9420_pdata *pd = netdev_priv(dev); 745 u32 int_cfg; 746 ulong flags; 747 748 BUG_ON(!pd); 749 BUG_ON(!pd->phy_dev); 750 751 /* disable master interrupt */ 752 spin_lock_irqsave(&pd->int_lock, flags); 753 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); 754 smsc9420_reg_write(pd, INT_CFG, int_cfg); 755 spin_unlock_irqrestore(&pd->int_lock, flags); 756 757 netif_tx_disable(dev); 758 napi_disable(&pd->napi); 759 760 smsc9420_stop_tx(pd); 761 smsc9420_free_tx_ring(pd); 762 763 smsc9420_stop_rx(pd); 764 smsc9420_free_rx_ring(pd); 765 766 free_irq(pd->pdev->irq, pd); 767 768 smsc9420_dmac_soft_reset(pd); 769 770 phy_stop(pd->phy_dev); 771 772 phy_disconnect(pd->phy_dev); 773 pd->phy_dev = NULL; 774 mdiobus_unregister(pd->mii_bus); 775 mdiobus_free(pd->mii_bus); 776 777 return 0; 778 } 779 780 static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status) 781 { 782 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) { 783 dev->stats.rx_errors++; 784 if (desc_status & RDES0_DESCRIPTOR_ERROR_) 785 dev->stats.rx_over_errors++; 786 else if (desc_status & (RDES0_FRAME_TOO_LONG_ | 787 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_)) 788 dev->stats.rx_frame_errors++; 789 else if (desc_status & RDES0_CRC_ERROR_) 790 dev->stats.rx_crc_errors++; 791 } 792 793 if (unlikely(desc_status & RDES0_LENGTH_ERROR_)) 794 dev->stats.rx_length_errors++; 795 796 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) && 797 (desc_status & RDES0_FIRST_DESCRIPTOR_)))) 798 dev->stats.rx_length_errors++; 799 800 if (desc_status & RDES0_MULTICAST_FRAME_) 801 dev->stats.multicast++; 802 } 803 804 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index, 805 const u32 status) 806 { 807 struct net_device *dev = pd->dev; 808 struct sk_buff *skb; 809 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_) 810 >> RDES0_FRAME_LENGTH_SHFT_; 811 812 /* remove crc from packet lendth */ 813 packet_length -= 4; 814 815 if (pd->rx_csum) 816 packet_length -= 2; 817 818 dev->stats.rx_packets++; 819 dev->stats.rx_bytes += packet_length; 820 821 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping, 822 PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 823 pd->rx_buffers[index].mapping = 0; 824 825 skb = pd->rx_buffers[index].skb; 826 pd->rx_buffers[index].skb = NULL; 827 828 if (pd->rx_csum) { 829 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) + 830 NET_IP_ALIGN + packet_length + 4); 831 put_unaligned_le16(hw_csum, &skb->csum); 832 skb->ip_summed = CHECKSUM_COMPLETE; 833 } 834 835 skb_reserve(skb, NET_IP_ALIGN); 836 skb_put(skb, packet_length); 837 838 skb->protocol = eth_type_trans(skb, dev); 839 840 netif_receive_skb(skb); 841 } 842 843 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index) 844 { 845 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ); 846 dma_addr_t mapping; 847 848 BUG_ON(pd->rx_buffers[index].skb); 849 BUG_ON(pd->rx_buffers[index].mapping); 850 851 if (unlikely(!skb)) 852 return -ENOMEM; 853 854 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb), 855 PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 856 if (pci_dma_mapping_error(pd->pdev, mapping)) { 857 dev_kfree_skb_any(skb); 858 smsc_warn(RX_ERR, "pci_map_single failed!"); 859 return -ENOMEM; 860 } 861 862 pd->rx_buffers[index].skb = skb; 863 pd->rx_buffers[index].mapping = mapping; 864 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN; 865 pd->rx_ring[index].status = RDES0_OWN_; 866 wmb(); 867 868 return 0; 869 } 870 871 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd) 872 { 873 while (pd->rx_ring_tail != pd->rx_ring_head) { 874 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail)) 875 break; 876 877 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE; 878 } 879 } 880 881 static int smsc9420_rx_poll(struct napi_struct *napi, int budget) 882 { 883 struct smsc9420_pdata *pd = 884 container_of(napi, struct smsc9420_pdata, napi); 885 struct net_device *dev = pd->dev; 886 u32 drop_frame_cnt, dma_intr_ena, status; 887 int work_done; 888 889 for (work_done = 0; work_done < budget; work_done++) { 890 rmb(); 891 status = pd->rx_ring[pd->rx_ring_head].status; 892 893 /* stop if DMAC owns this dma descriptor */ 894 if (status & RDES0_OWN_) 895 break; 896 897 smsc9420_rx_count_stats(dev, status); 898 smsc9420_rx_handoff(pd, pd->rx_ring_head, status); 899 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE; 900 smsc9420_alloc_new_rx_buffers(pd); 901 } 902 903 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR); 904 dev->stats.rx_dropped += 905 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF); 906 907 /* Kick RXDMA */ 908 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1); 909 smsc9420_pci_flush_write(pd); 910 911 if (work_done < budget) { 912 napi_complete(&pd->napi); 913 914 /* re-enable RX DMA interrupts */ 915 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 916 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_); 917 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 918 smsc9420_pci_flush_write(pd); 919 } 920 return work_done; 921 } 922 923 static void 924 smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length) 925 { 926 if (unlikely(status & TDES0_ERROR_SUMMARY_)) { 927 dev->stats.tx_errors++; 928 if (status & (TDES0_EXCESSIVE_DEFERRAL_ | 929 TDES0_EXCESSIVE_COLLISIONS_)) 930 dev->stats.tx_aborted_errors++; 931 932 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_)) 933 dev->stats.tx_carrier_errors++; 934 } else { 935 dev->stats.tx_packets++; 936 dev->stats.tx_bytes += (length & 0x7FF); 937 } 938 939 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) { 940 dev->stats.collisions += 16; 941 } else { 942 dev->stats.collisions += 943 (status & TDES0_COLLISION_COUNT_MASK_) >> 944 TDES0_COLLISION_COUNT_SHFT_; 945 } 946 947 if (unlikely(status & TDES0_HEARTBEAT_FAIL_)) 948 dev->stats.tx_heartbeat_errors++; 949 } 950 951 /* Check for completed dma transfers, update stats and free skbs */ 952 static void smsc9420_complete_tx(struct net_device *dev) 953 { 954 struct smsc9420_pdata *pd = netdev_priv(dev); 955 956 while (pd->tx_ring_tail != pd->tx_ring_head) { 957 int index = pd->tx_ring_tail; 958 u32 status, length; 959 960 rmb(); 961 status = pd->tx_ring[index].status; 962 length = pd->tx_ring[index].length; 963 964 /* Check if DMA still owns this descriptor */ 965 if (unlikely(TDES0_OWN_ & status)) 966 break; 967 968 smsc9420_tx_update_stats(dev, status, length); 969 970 BUG_ON(!pd->tx_buffers[index].skb); 971 BUG_ON(!pd->tx_buffers[index].mapping); 972 973 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping, 974 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE); 975 pd->tx_buffers[index].mapping = 0; 976 977 dev_kfree_skb_any(pd->tx_buffers[index].skb); 978 pd->tx_buffers[index].skb = NULL; 979 980 pd->tx_ring[index].buffer1 = 0; 981 wmb(); 982 983 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE; 984 } 985 } 986 987 static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb, 988 struct net_device *dev) 989 { 990 struct smsc9420_pdata *pd = netdev_priv(dev); 991 dma_addr_t mapping; 992 int index = pd->tx_ring_head; 993 u32 tmp_desc1; 994 bool about_to_take_last_desc = 995 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail); 996 997 smsc9420_complete_tx(dev); 998 999 rmb(); 1000 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_); 1001 BUG_ON(pd->tx_buffers[index].skb); 1002 BUG_ON(pd->tx_buffers[index].mapping); 1003 1004 mapping = pci_map_single(pd->pdev, skb->data, 1005 skb->len, PCI_DMA_TODEVICE); 1006 if (pci_dma_mapping_error(pd->pdev, mapping)) { 1007 smsc_warn(TX_ERR, "pci_map_single failed, dropping packet"); 1008 return NETDEV_TX_BUSY; 1009 } 1010 1011 pd->tx_buffers[index].skb = skb; 1012 pd->tx_buffers[index].mapping = mapping; 1013 1014 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF)); 1015 if (unlikely(about_to_take_last_desc)) { 1016 tmp_desc1 |= TDES1_IC_; 1017 netif_stop_queue(pd->dev); 1018 } 1019 1020 /* check if we are at the last descriptor and need to set EOR */ 1021 if (unlikely(index == (TX_RING_SIZE - 1))) 1022 tmp_desc1 |= TDES1_TER_; 1023 1024 pd->tx_ring[index].buffer1 = mapping; 1025 pd->tx_ring[index].length = tmp_desc1; 1026 wmb(); 1027 1028 /* increment head */ 1029 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE; 1030 1031 /* assign ownership to DMAC */ 1032 pd->tx_ring[index].status = TDES0_OWN_; 1033 wmb(); 1034 1035 skb_tx_timestamp(skb); 1036 1037 /* kick the DMA */ 1038 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1); 1039 smsc9420_pci_flush_write(pd); 1040 1041 return NETDEV_TX_OK; 1042 } 1043 1044 static struct net_device_stats *smsc9420_get_stats(struct net_device *dev) 1045 { 1046 struct smsc9420_pdata *pd = netdev_priv(dev); 1047 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR); 1048 dev->stats.rx_dropped += 1049 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF); 1050 return &dev->stats; 1051 } 1052 1053 static void smsc9420_set_multicast_list(struct net_device *dev) 1054 { 1055 struct smsc9420_pdata *pd = netdev_priv(dev); 1056 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR); 1057 1058 if (dev->flags & IFF_PROMISC) { 1059 smsc_dbg(HW, "Promiscuous Mode Enabled"); 1060 mac_cr |= MAC_CR_PRMS_; 1061 mac_cr &= (~MAC_CR_MCPAS_); 1062 mac_cr &= (~MAC_CR_HPFILT_); 1063 } else if (dev->flags & IFF_ALLMULTI) { 1064 smsc_dbg(HW, "Receive all Multicast Enabled"); 1065 mac_cr &= (~MAC_CR_PRMS_); 1066 mac_cr |= MAC_CR_MCPAS_; 1067 mac_cr &= (~MAC_CR_HPFILT_); 1068 } else if (!netdev_mc_empty(dev)) { 1069 struct netdev_hw_addr *ha; 1070 u32 hash_lo = 0, hash_hi = 0; 1071 1072 smsc_dbg(HW, "Multicast filter enabled"); 1073 netdev_for_each_mc_addr(ha, dev) { 1074 u32 bit_num = smsc9420_hash(ha->addr); 1075 u32 mask = 1 << (bit_num & 0x1F); 1076 1077 if (bit_num & 0x20) 1078 hash_hi |= mask; 1079 else 1080 hash_lo |= mask; 1081 1082 } 1083 smsc9420_reg_write(pd, HASHH, hash_hi); 1084 smsc9420_reg_write(pd, HASHL, hash_lo); 1085 1086 mac_cr &= (~MAC_CR_PRMS_); 1087 mac_cr &= (~MAC_CR_MCPAS_); 1088 mac_cr |= MAC_CR_HPFILT_; 1089 } else { 1090 smsc_dbg(HW, "Receive own packets only."); 1091 smsc9420_reg_write(pd, HASHH, 0); 1092 smsc9420_reg_write(pd, HASHL, 0); 1093 1094 mac_cr &= (~MAC_CR_PRMS_); 1095 mac_cr &= (~MAC_CR_MCPAS_); 1096 mac_cr &= (~MAC_CR_HPFILT_); 1097 } 1098 1099 smsc9420_reg_write(pd, MAC_CR, mac_cr); 1100 smsc9420_pci_flush_write(pd); 1101 } 1102 1103 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd) 1104 { 1105 struct phy_device *phy_dev = pd->phy_dev; 1106 u32 flow; 1107 1108 if (phy_dev->duplex == DUPLEX_FULL) { 1109 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE); 1110 u16 rmtadv = phy_read(phy_dev, MII_LPA); 1111 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); 1112 1113 if (cap & FLOW_CTRL_RX) 1114 flow = 0xFFFF0002; 1115 else 1116 flow = 0; 1117 1118 smsc_info(LINK, "rx pause %s, tx pause %s", 1119 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"), 1120 (cap & FLOW_CTRL_TX ? "enabled" : "disabled")); 1121 } else { 1122 smsc_info(LINK, "half duplex"); 1123 flow = 0; 1124 } 1125 1126 smsc9420_reg_write(pd, FLOW, flow); 1127 } 1128 1129 /* Update link mode if anything has changed. Called periodically when the 1130 * PHY is in polling mode, even if nothing has changed. */ 1131 static void smsc9420_phy_adjust_link(struct net_device *dev) 1132 { 1133 struct smsc9420_pdata *pd = netdev_priv(dev); 1134 struct phy_device *phy_dev = pd->phy_dev; 1135 int carrier; 1136 1137 if (phy_dev->duplex != pd->last_duplex) { 1138 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR); 1139 if (phy_dev->duplex) { 1140 smsc_dbg(LINK, "full duplex mode"); 1141 mac_cr |= MAC_CR_FDPX_; 1142 } else { 1143 smsc_dbg(LINK, "half duplex mode"); 1144 mac_cr &= ~MAC_CR_FDPX_; 1145 } 1146 smsc9420_reg_write(pd, MAC_CR, mac_cr); 1147 1148 smsc9420_phy_update_flowcontrol(pd); 1149 pd->last_duplex = phy_dev->duplex; 1150 } 1151 1152 carrier = netif_carrier_ok(dev); 1153 if (carrier != pd->last_carrier) { 1154 if (carrier) 1155 smsc_dbg(LINK, "carrier OK"); 1156 else 1157 smsc_dbg(LINK, "no carrier"); 1158 pd->last_carrier = carrier; 1159 } 1160 } 1161 1162 static int smsc9420_mii_probe(struct net_device *dev) 1163 { 1164 struct smsc9420_pdata *pd = netdev_priv(dev); 1165 struct phy_device *phydev = NULL; 1166 1167 BUG_ON(pd->phy_dev); 1168 1169 /* Device only supports internal PHY at address 1 */ 1170 if (!pd->mii_bus->phy_map[1]) { 1171 pr_err("%s: no PHY found at address 1\n", dev->name); 1172 return -ENODEV; 1173 } 1174 1175 phydev = pd->mii_bus->phy_map[1]; 1176 smsc_info(PROBE, "PHY addr %d, phy_id 0x%08X", phydev->addr, 1177 phydev->phy_id); 1178 1179 phydev = phy_connect(dev, dev_name(&phydev->dev), 1180 smsc9420_phy_adjust_link, PHY_INTERFACE_MODE_MII); 1181 1182 if (IS_ERR(phydev)) { 1183 pr_err("%s: Could not attach to PHY\n", dev->name); 1184 return PTR_ERR(phydev); 1185 } 1186 1187 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1188 dev->name, phydev->drv->name, dev_name(&phydev->dev), phydev->irq); 1189 1190 /* mask with MAC supported features */ 1191 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause | 1192 SUPPORTED_Asym_Pause); 1193 phydev->advertising = phydev->supported; 1194 1195 pd->phy_dev = phydev; 1196 pd->last_duplex = -1; 1197 pd->last_carrier = -1; 1198 1199 return 0; 1200 } 1201 1202 static int smsc9420_mii_init(struct net_device *dev) 1203 { 1204 struct smsc9420_pdata *pd = netdev_priv(dev); 1205 int err = -ENXIO, i; 1206 1207 pd->mii_bus = mdiobus_alloc(); 1208 if (!pd->mii_bus) { 1209 err = -ENOMEM; 1210 goto err_out_1; 1211 } 1212 pd->mii_bus->name = DRV_MDIONAME; 1213 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x", 1214 (pd->pdev->bus->number << 8) | pd->pdev->devfn); 1215 pd->mii_bus->priv = pd; 1216 pd->mii_bus->read = smsc9420_mii_read; 1217 pd->mii_bus->write = smsc9420_mii_write; 1218 pd->mii_bus->irq = pd->phy_irq; 1219 for (i = 0; i < PHY_MAX_ADDR; ++i) 1220 pd->mii_bus->irq[i] = PHY_POLL; 1221 1222 /* Mask all PHYs except ID 1 (internal) */ 1223 pd->mii_bus->phy_mask = ~(1 << 1); 1224 1225 if (mdiobus_register(pd->mii_bus)) { 1226 smsc_warn(PROBE, "Error registering mii bus"); 1227 goto err_out_free_bus_2; 1228 } 1229 1230 if (smsc9420_mii_probe(dev) < 0) { 1231 smsc_warn(PROBE, "Error probing mii bus"); 1232 goto err_out_unregister_bus_3; 1233 } 1234 1235 return 0; 1236 1237 err_out_unregister_bus_3: 1238 mdiobus_unregister(pd->mii_bus); 1239 err_out_free_bus_2: 1240 mdiobus_free(pd->mii_bus); 1241 err_out_1: 1242 return err; 1243 } 1244 1245 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd) 1246 { 1247 int i; 1248 1249 BUG_ON(!pd->tx_ring); 1250 1251 pd->tx_buffers = kmalloc_array(TX_RING_SIZE, 1252 sizeof(struct smsc9420_ring_info), 1253 GFP_KERNEL); 1254 if (!pd->tx_buffers) 1255 return -ENOMEM; 1256 1257 /* Initialize the TX Ring */ 1258 for (i = 0; i < TX_RING_SIZE; i++) { 1259 pd->tx_buffers[i].skb = NULL; 1260 pd->tx_buffers[i].mapping = 0; 1261 pd->tx_ring[i].status = 0; 1262 pd->tx_ring[i].length = 0; 1263 pd->tx_ring[i].buffer1 = 0; 1264 pd->tx_ring[i].buffer2 = 0; 1265 } 1266 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_; 1267 wmb(); 1268 1269 pd->tx_ring_head = 0; 1270 pd->tx_ring_tail = 0; 1271 1272 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr); 1273 smsc9420_pci_flush_write(pd); 1274 1275 return 0; 1276 } 1277 1278 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd) 1279 { 1280 int i; 1281 1282 BUG_ON(!pd->rx_ring); 1283 1284 pd->rx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) * 1285 RX_RING_SIZE), GFP_KERNEL); 1286 if (pd->rx_buffers == NULL) { 1287 smsc_warn(IFUP, "Failed to allocated rx_buffers"); 1288 goto out; 1289 } 1290 1291 /* initialize the rx ring */ 1292 for (i = 0; i < RX_RING_SIZE; i++) { 1293 pd->rx_ring[i].status = 0; 1294 pd->rx_ring[i].length = PKT_BUF_SZ; 1295 pd->rx_ring[i].buffer2 = 0; 1296 pd->rx_buffers[i].skb = NULL; 1297 pd->rx_buffers[i].mapping = 0; 1298 } 1299 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_); 1300 1301 /* now allocate the entire ring of skbs */ 1302 for (i = 0; i < RX_RING_SIZE; i++) { 1303 if (smsc9420_alloc_rx_buffer(pd, i)) { 1304 smsc_warn(IFUP, "failed to allocate rx skb %d", i); 1305 goto out_free_rx_skbs; 1306 } 1307 } 1308 1309 pd->rx_ring_head = 0; 1310 pd->rx_ring_tail = 0; 1311 1312 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q); 1313 smsc_dbg(IFUP, "VLAN1 = 0x%08x", smsc9420_reg_read(pd, VLAN1)); 1314 1315 if (pd->rx_csum) { 1316 /* Enable RX COE */ 1317 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN; 1318 smsc9420_reg_write(pd, COE_CR, coe); 1319 smsc_dbg(IFUP, "COE_CR = 0x%08x", coe); 1320 } 1321 1322 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr); 1323 smsc9420_pci_flush_write(pd); 1324 1325 return 0; 1326 1327 out_free_rx_skbs: 1328 smsc9420_free_rx_ring(pd); 1329 out: 1330 return -ENOMEM; 1331 } 1332 1333 static int smsc9420_open(struct net_device *dev) 1334 { 1335 struct smsc9420_pdata *pd = netdev_priv(dev); 1336 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl; 1337 const int irq = pd->pdev->irq; 1338 unsigned long flags; 1339 int result = 0, timeout; 1340 1341 if (!is_valid_ether_addr(dev->dev_addr)) { 1342 smsc_warn(IFUP, "dev_addr is not a valid MAC address"); 1343 result = -EADDRNOTAVAIL; 1344 goto out_0; 1345 } 1346 1347 netif_carrier_off(dev); 1348 1349 /* disable, mask and acknowledge all interrupts */ 1350 spin_lock_irqsave(&pd->int_lock, flags); 1351 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); 1352 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1353 smsc9420_reg_write(pd, INT_CTL, 0); 1354 spin_unlock_irqrestore(&pd->int_lock, flags); 1355 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0); 1356 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF); 1357 smsc9420_pci_flush_write(pd); 1358 1359 result = request_irq(irq, smsc9420_isr, IRQF_SHARED | IRQF_DISABLED, 1360 DRV_NAME, pd); 1361 if (result) { 1362 smsc_warn(IFUP, "Unable to use IRQ = %d", irq); 1363 result = -ENODEV; 1364 goto out_0; 1365 } 1366 1367 smsc9420_dmac_soft_reset(pd); 1368 1369 /* make sure MAC_CR is sane */ 1370 smsc9420_reg_write(pd, MAC_CR, 0); 1371 1372 smsc9420_set_mac_address(dev); 1373 1374 /* Configure GPIO pins to drive LEDs */ 1375 smsc9420_reg_write(pd, GPIO_CFG, 1376 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_)); 1377 1378 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16; 1379 1380 #ifdef __BIG_ENDIAN 1381 bus_mode |= BUS_MODE_DBO_; 1382 #endif 1383 1384 smsc9420_reg_write(pd, BUS_MODE, bus_mode); 1385 1386 smsc9420_pci_flush_write(pd); 1387 1388 /* set bus master bridge arbitration priority for Rx and TX DMA */ 1389 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1); 1390 1391 smsc9420_reg_write(pd, DMAC_CONTROL, 1392 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_)); 1393 1394 smsc9420_pci_flush_write(pd); 1395 1396 /* test the IRQ connection to the ISR */ 1397 smsc_dbg(IFUP, "Testing ISR using IRQ %d", irq); 1398 pd->software_irq_signal = false; 1399 1400 spin_lock_irqsave(&pd->int_lock, flags); 1401 /* configure interrupt deassertion timer and enable interrupts */ 1402 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_; 1403 int_cfg &= ~(INT_CFG_INT_DEAS_MASK); 1404 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK); 1405 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1406 1407 /* unmask software interrupt */ 1408 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_; 1409 smsc9420_reg_write(pd, INT_CTL, int_ctl); 1410 spin_unlock_irqrestore(&pd->int_lock, flags); 1411 smsc9420_pci_flush_write(pd); 1412 1413 timeout = 1000; 1414 while (timeout--) { 1415 if (pd->software_irq_signal) 1416 break; 1417 msleep(1); 1418 } 1419 1420 /* disable interrupts */ 1421 spin_lock_irqsave(&pd->int_lock, flags); 1422 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); 1423 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1424 spin_unlock_irqrestore(&pd->int_lock, flags); 1425 1426 if (!pd->software_irq_signal) { 1427 smsc_warn(IFUP, "ISR failed signaling test"); 1428 result = -ENODEV; 1429 goto out_free_irq_1; 1430 } 1431 1432 smsc_dbg(IFUP, "ISR passed test using IRQ %d", irq); 1433 1434 result = smsc9420_alloc_tx_ring(pd); 1435 if (result) { 1436 smsc_warn(IFUP, "Failed to Initialize tx dma ring"); 1437 result = -ENOMEM; 1438 goto out_free_irq_1; 1439 } 1440 1441 result = smsc9420_alloc_rx_ring(pd); 1442 if (result) { 1443 smsc_warn(IFUP, "Failed to Initialize rx dma ring"); 1444 result = -ENOMEM; 1445 goto out_free_tx_ring_2; 1446 } 1447 1448 result = smsc9420_mii_init(dev); 1449 if (result) { 1450 smsc_warn(IFUP, "Failed to initialize Phy"); 1451 result = -ENODEV; 1452 goto out_free_rx_ring_3; 1453 } 1454 1455 /* Bring the PHY up */ 1456 phy_start(pd->phy_dev); 1457 1458 napi_enable(&pd->napi); 1459 1460 /* start tx and rx */ 1461 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_; 1462 smsc9420_reg_write(pd, MAC_CR, mac_cr); 1463 1464 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); 1465 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_; 1466 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); 1467 smsc9420_pci_flush_write(pd); 1468 1469 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 1470 dma_intr_ena |= 1471 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_); 1472 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 1473 smsc9420_pci_flush_write(pd); 1474 1475 netif_wake_queue(dev); 1476 1477 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1); 1478 1479 /* enable interrupts */ 1480 spin_lock_irqsave(&pd->int_lock, flags); 1481 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_; 1482 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1483 spin_unlock_irqrestore(&pd->int_lock, flags); 1484 1485 return 0; 1486 1487 out_free_rx_ring_3: 1488 smsc9420_free_rx_ring(pd); 1489 out_free_tx_ring_2: 1490 smsc9420_free_tx_ring(pd); 1491 out_free_irq_1: 1492 free_irq(irq, pd); 1493 out_0: 1494 return result; 1495 } 1496 1497 #ifdef CONFIG_PM 1498 1499 static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state) 1500 { 1501 struct net_device *dev = pci_get_drvdata(pdev); 1502 struct smsc9420_pdata *pd = netdev_priv(dev); 1503 u32 int_cfg; 1504 ulong flags; 1505 1506 /* disable interrupts */ 1507 spin_lock_irqsave(&pd->int_lock, flags); 1508 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); 1509 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1510 spin_unlock_irqrestore(&pd->int_lock, flags); 1511 1512 if (netif_running(dev)) { 1513 netif_tx_disable(dev); 1514 smsc9420_stop_tx(pd); 1515 smsc9420_free_tx_ring(pd); 1516 1517 napi_disable(&pd->napi); 1518 smsc9420_stop_rx(pd); 1519 smsc9420_free_rx_ring(pd); 1520 1521 free_irq(pd->pdev->irq, pd); 1522 1523 netif_device_detach(dev); 1524 } 1525 1526 pci_save_state(pdev); 1527 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); 1528 pci_disable_device(pdev); 1529 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1530 1531 return 0; 1532 } 1533 1534 static int smsc9420_resume(struct pci_dev *pdev) 1535 { 1536 struct net_device *dev = pci_get_drvdata(pdev); 1537 struct smsc9420_pdata *pd = netdev_priv(dev); 1538 int err; 1539 1540 pci_set_power_state(pdev, PCI_D0); 1541 pci_restore_state(pdev); 1542 1543 err = pci_enable_device(pdev); 1544 if (err) 1545 return err; 1546 1547 pci_set_master(pdev); 1548 1549 err = pci_enable_wake(pdev, 0, 0); 1550 if (err) 1551 smsc_warn(IFUP, "pci_enable_wake failed: %d", err); 1552 1553 if (netif_running(dev)) { 1554 /* FIXME: gross. It looks like ancient PM relic.*/ 1555 err = smsc9420_open(dev); 1556 netif_device_attach(dev); 1557 } 1558 return err; 1559 } 1560 1561 #endif /* CONFIG_PM */ 1562 1563 static const struct net_device_ops smsc9420_netdev_ops = { 1564 .ndo_open = smsc9420_open, 1565 .ndo_stop = smsc9420_stop, 1566 .ndo_start_xmit = smsc9420_hard_start_xmit, 1567 .ndo_get_stats = smsc9420_get_stats, 1568 .ndo_set_rx_mode = smsc9420_set_multicast_list, 1569 .ndo_do_ioctl = smsc9420_do_ioctl, 1570 .ndo_validate_addr = eth_validate_addr, 1571 .ndo_set_mac_address = eth_mac_addr, 1572 #ifdef CONFIG_NET_POLL_CONTROLLER 1573 .ndo_poll_controller = smsc9420_poll_controller, 1574 #endif /* CONFIG_NET_POLL_CONTROLLER */ 1575 }; 1576 1577 static int 1578 smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1579 { 1580 struct net_device *dev; 1581 struct smsc9420_pdata *pd; 1582 void __iomem *virt_addr; 1583 int result = 0; 1584 u32 id_rev; 1585 1586 printk(KERN_INFO DRV_DESCRIPTION " version " DRV_VERSION "\n"); 1587 1588 /* First do the PCI initialisation */ 1589 result = pci_enable_device(pdev); 1590 if (unlikely(result)) { 1591 printk(KERN_ERR "Cannot enable smsc9420\n"); 1592 goto out_0; 1593 } 1594 1595 pci_set_master(pdev); 1596 1597 dev = alloc_etherdev(sizeof(*pd)); 1598 if (!dev) 1599 goto out_disable_pci_device_1; 1600 1601 SET_NETDEV_DEV(dev, &pdev->dev); 1602 1603 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) { 1604 printk(KERN_ERR "Cannot find PCI device base address\n"); 1605 goto out_free_netdev_2; 1606 } 1607 1608 if ((pci_request_regions(pdev, DRV_NAME))) { 1609 printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n"); 1610 goto out_free_netdev_2; 1611 } 1612 1613 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 1614 printk(KERN_ERR "No usable DMA configuration, aborting.\n"); 1615 goto out_free_regions_3; 1616 } 1617 1618 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR), 1619 pci_resource_len(pdev, SMSC_BAR)); 1620 if (!virt_addr) { 1621 printk(KERN_ERR "Cannot map device registers, aborting.\n"); 1622 goto out_free_regions_3; 1623 } 1624 1625 /* registers are double mapped with 0 offset for LE and 0x200 for BE */ 1626 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET; 1627 1628 pd = netdev_priv(dev); 1629 1630 /* pci descriptors are created in the PCI consistent area */ 1631 pd->rx_ring = pci_alloc_consistent(pdev, 1632 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE + 1633 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE, 1634 &pd->rx_dma_addr); 1635 1636 if (!pd->rx_ring) 1637 goto out_free_io_4; 1638 1639 /* descriptors are aligned due to the nature of pci_alloc_consistent */ 1640 pd->tx_ring = (pd->rx_ring + RX_RING_SIZE); 1641 pd->tx_dma_addr = pd->rx_dma_addr + 1642 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE; 1643 1644 pd->pdev = pdev; 1645 pd->dev = dev; 1646 pd->ioaddr = virt_addr; 1647 pd->msg_enable = smsc_debug; 1648 pd->rx_csum = true; 1649 1650 smsc_dbg(PROBE, "lan_base=0x%08lx", (ulong)virt_addr); 1651 1652 id_rev = smsc9420_reg_read(pd, ID_REV); 1653 switch (id_rev & 0xFFFF0000) { 1654 case 0x94200000: 1655 smsc_info(PROBE, "LAN9420 identified, ID_REV=0x%08X", id_rev); 1656 break; 1657 default: 1658 smsc_warn(PROBE, "LAN9420 NOT identified"); 1659 smsc_warn(PROBE, "ID_REV=0x%08X", id_rev); 1660 goto out_free_dmadesc_5; 1661 } 1662 1663 smsc9420_dmac_soft_reset(pd); 1664 smsc9420_eeprom_reload(pd); 1665 smsc9420_check_mac_address(dev); 1666 1667 dev->netdev_ops = &smsc9420_netdev_ops; 1668 dev->ethtool_ops = &smsc9420_ethtool_ops; 1669 1670 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT); 1671 1672 result = register_netdev(dev); 1673 if (result) { 1674 smsc_warn(PROBE, "error %i registering device", result); 1675 goto out_free_dmadesc_5; 1676 } 1677 1678 pci_set_drvdata(pdev, dev); 1679 1680 spin_lock_init(&pd->int_lock); 1681 spin_lock_init(&pd->phy_lock); 1682 1683 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr); 1684 1685 return 0; 1686 1687 out_free_dmadesc_5: 1688 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) * 1689 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr); 1690 out_free_io_4: 1691 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET); 1692 out_free_regions_3: 1693 pci_release_regions(pdev); 1694 out_free_netdev_2: 1695 free_netdev(dev); 1696 out_disable_pci_device_1: 1697 pci_disable_device(pdev); 1698 out_0: 1699 return -ENODEV; 1700 } 1701 1702 static void smsc9420_remove(struct pci_dev *pdev) 1703 { 1704 struct net_device *dev; 1705 struct smsc9420_pdata *pd; 1706 1707 dev = pci_get_drvdata(pdev); 1708 if (!dev) 1709 return; 1710 1711 pci_set_drvdata(pdev, NULL); 1712 1713 pd = netdev_priv(dev); 1714 unregister_netdev(dev); 1715 1716 /* tx_buffers and rx_buffers are freed in stop */ 1717 BUG_ON(pd->tx_buffers); 1718 BUG_ON(pd->rx_buffers); 1719 1720 BUG_ON(!pd->tx_ring); 1721 BUG_ON(!pd->rx_ring); 1722 1723 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) * 1724 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr); 1725 1726 iounmap(pd->ioaddr - LAN9420_CPSR_ENDIAN_OFFSET); 1727 pci_release_regions(pdev); 1728 free_netdev(dev); 1729 pci_disable_device(pdev); 1730 } 1731 1732 static struct pci_driver smsc9420_driver = { 1733 .name = DRV_NAME, 1734 .id_table = smsc9420_id_table, 1735 .probe = smsc9420_probe, 1736 .remove = smsc9420_remove, 1737 #ifdef CONFIG_PM 1738 .suspend = smsc9420_suspend, 1739 .resume = smsc9420_resume, 1740 #endif /* CONFIG_PM */ 1741 }; 1742 1743 static int __init smsc9420_init_module(void) 1744 { 1745 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT); 1746 1747 return pci_register_driver(&smsc9420_driver); 1748 } 1749 1750 static void __exit smsc9420_exit_module(void) 1751 { 1752 pci_unregister_driver(&smsc9420_driver); 1753 } 1754 1755 module_init(smsc9420_init_module); 1756 module_exit(smsc9420_exit_module); 1757