1 // SPDX-License-Identifier: GPL-2.0-or-later
2  /***************************************************************************
3  *
4  * Copyright (C) 2007,2008  SMSC
5  *
6  ***************************************************************************
7  */
8 
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <linux/netdevice.h>
14 #include <linux/phy.h>
15 #include <linux/pci.h>
16 #include <linux/if_vlan.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/crc32.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <asm/unaligned.h>
22 #include "smsc9420.h"
23 
24 #define DRV_NAME		"smsc9420"
25 #define DRV_MDIONAME		"smsc9420-mdio"
26 #define DRV_DESCRIPTION		"SMSC LAN9420 driver"
27 #define DRV_VERSION		"1.01"
28 
29 MODULE_LICENSE("GPL");
30 MODULE_VERSION(DRV_VERSION);
31 
32 struct smsc9420_dma_desc {
33 	u32 status;
34 	u32 length;
35 	u32 buffer1;
36 	u32 buffer2;
37 };
38 
39 struct smsc9420_ring_info {
40 	struct sk_buff *skb;
41 	dma_addr_t mapping;
42 };
43 
44 struct smsc9420_pdata {
45 	void __iomem *ioaddr;
46 	struct pci_dev *pdev;
47 	struct net_device *dev;
48 
49 	struct smsc9420_dma_desc *rx_ring;
50 	struct smsc9420_dma_desc *tx_ring;
51 	struct smsc9420_ring_info *tx_buffers;
52 	struct smsc9420_ring_info *rx_buffers;
53 	dma_addr_t rx_dma_addr;
54 	dma_addr_t tx_dma_addr;
55 	int tx_ring_head, tx_ring_tail;
56 	int rx_ring_head, rx_ring_tail;
57 
58 	spinlock_t int_lock;
59 	spinlock_t phy_lock;
60 
61 	struct napi_struct napi;
62 
63 	bool software_irq_signal;
64 	bool rx_csum;
65 	u32 msg_enable;
66 
67 	struct mii_bus *mii_bus;
68 	int last_duplex;
69 	int last_carrier;
70 };
71 
72 static const struct pci_device_id smsc9420_id_table[] = {
73 	{ PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
74 	{ 0, }
75 };
76 
77 MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
78 
79 #define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
80 
81 static uint smsc_debug;
82 static uint debug = -1;
83 module_param(debug, uint, 0);
84 MODULE_PARM_DESC(debug, "debug level");
85 
86 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
87 {
88 	return ioread32(pd->ioaddr + offset);
89 }
90 
91 static inline void
92 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
93 {
94 	iowrite32(value, pd->ioaddr + offset);
95 }
96 
97 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
98 {
99 	/* to ensure PCI write completion, we must perform a PCI read */
100 	smsc9420_reg_read(pd, ID_REV);
101 }
102 
103 static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
104 {
105 	struct smsc9420_pdata *pd = bus->priv;
106 	unsigned long flags;
107 	u32 addr;
108 	int i, reg = -EIO;
109 
110 	spin_lock_irqsave(&pd->phy_lock, flags);
111 
112 	/*  confirm MII not busy */
113 	if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
114 		netif_warn(pd, drv, pd->dev, "MII is busy???\n");
115 		goto out;
116 	}
117 
118 	/* set the address, index & direction (read from PHY) */
119 	addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
120 		MII_ACCESS_MII_READ_;
121 	smsc9420_reg_write(pd, MII_ACCESS, addr);
122 
123 	/* wait for read to complete with 50us timeout */
124 	for (i = 0; i < 5; i++) {
125 		if (!(smsc9420_reg_read(pd, MII_ACCESS) &
126 			MII_ACCESS_MII_BUSY_)) {
127 			reg = (u16)smsc9420_reg_read(pd, MII_DATA);
128 			goto out;
129 		}
130 		udelay(10);
131 	}
132 
133 	netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
134 
135 out:
136 	spin_unlock_irqrestore(&pd->phy_lock, flags);
137 	return reg;
138 }
139 
140 static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
141 			   u16 val)
142 {
143 	struct smsc9420_pdata *pd = bus->priv;
144 	unsigned long flags;
145 	u32 addr;
146 	int i, reg = -EIO;
147 
148 	spin_lock_irqsave(&pd->phy_lock, flags);
149 
150 	/* confirm MII not busy */
151 	if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
152 		netif_warn(pd, drv, pd->dev, "MII is busy???\n");
153 		goto out;
154 	}
155 
156 	/* put the data to write in the MAC */
157 	smsc9420_reg_write(pd, MII_DATA, (u32)val);
158 
159 	/* set the address, index & direction (write to PHY) */
160 	addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
161 		MII_ACCESS_MII_WRITE_;
162 	smsc9420_reg_write(pd, MII_ACCESS, addr);
163 
164 	/* wait for write to complete with 50us timeout */
165 	for (i = 0; i < 5; i++) {
166 		if (!(smsc9420_reg_read(pd, MII_ACCESS) &
167 			MII_ACCESS_MII_BUSY_)) {
168 			reg = 0;
169 			goto out;
170 		}
171 		udelay(10);
172 	}
173 
174 	netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
175 
176 out:
177 	spin_unlock_irqrestore(&pd->phy_lock, flags);
178 	return reg;
179 }
180 
181 /* Returns hash bit number for given MAC address
182  * Example:
183  * 01 00 5E 00 00 01 -> returns bit number 31 */
184 static u32 smsc9420_hash(u8 addr[ETH_ALEN])
185 {
186 	return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
187 }
188 
189 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
190 {
191 	int timeout = 100000;
192 
193 	BUG_ON(!pd);
194 
195 	if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
196 		netif_dbg(pd, drv, pd->dev, "%s: Eeprom busy\n", __func__);
197 		return -EIO;
198 	}
199 
200 	smsc9420_reg_write(pd, E2P_CMD,
201 		(E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
202 
203 	do {
204 		udelay(10);
205 		if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
206 			return 0;
207 	} while (timeout--);
208 
209 	netif_warn(pd, drv, pd->dev, "%s: Eeprom timed out\n", __func__);
210 	return -EIO;
211 }
212 
213 static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
214 					 struct ethtool_drvinfo *drvinfo)
215 {
216 	struct smsc9420_pdata *pd = netdev_priv(netdev);
217 
218 	strscpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
219 	strscpy(drvinfo->bus_info, pci_name(pd->pdev),
220 		sizeof(drvinfo->bus_info));
221 	strscpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
222 }
223 
224 static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
225 {
226 	struct smsc9420_pdata *pd = netdev_priv(netdev);
227 	return pd->msg_enable;
228 }
229 
230 static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
231 {
232 	struct smsc9420_pdata *pd = netdev_priv(netdev);
233 	pd->msg_enable = data;
234 }
235 
236 static int smsc9420_ethtool_getregslen(struct net_device *dev)
237 {
238 	/* all smsc9420 registers plus all phy registers */
239 	return 0x100 + (32 * sizeof(u32));
240 }
241 
242 static void
243 smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
244 			 void *buf)
245 {
246 	struct smsc9420_pdata *pd = netdev_priv(dev);
247 	struct phy_device *phy_dev = dev->phydev;
248 	unsigned int i, j = 0;
249 	u32 *data = buf;
250 
251 	regs->version = smsc9420_reg_read(pd, ID_REV);
252 	for (i = 0; i < 0x100; i += (sizeof(u32)))
253 		data[j++] = smsc9420_reg_read(pd, i);
254 
255 	// cannot read phy registers if the net device is down
256 	if (!phy_dev)
257 		return;
258 
259 	for (i = 0; i <= 31; i++)
260 		data[j++] = smsc9420_mii_read(phy_dev->mdio.bus,
261 					      phy_dev->mdio.addr, i);
262 }
263 
264 static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
265 {
266 	unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
267 	temp &= ~GPIO_CFG_EEPR_EN_;
268 	smsc9420_reg_write(pd, GPIO_CFG, temp);
269 	msleep(1);
270 }
271 
272 static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
273 {
274 	int timeout = 100;
275 	u32 e2cmd;
276 
277 	netif_dbg(pd, hw, pd->dev, "op 0x%08x\n", op);
278 	if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
279 		netif_warn(pd, hw, pd->dev, "Busy at start\n");
280 		return -EBUSY;
281 	}
282 
283 	e2cmd = op | E2P_CMD_EPC_BUSY_;
284 	smsc9420_reg_write(pd, E2P_CMD, e2cmd);
285 
286 	do {
287 		msleep(1);
288 		e2cmd = smsc9420_reg_read(pd, E2P_CMD);
289 	} while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
290 
291 	if (!timeout) {
292 		netif_info(pd, hw, pd->dev, "TIMED OUT\n");
293 		return -EAGAIN;
294 	}
295 
296 	if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
297 		netif_info(pd, hw, pd->dev,
298 			   "Error occurred during eeprom operation\n");
299 		return -EINVAL;
300 	}
301 
302 	return 0;
303 }
304 
305 static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
306 					 u8 address, u8 *data)
307 {
308 	u32 op = E2P_CMD_EPC_CMD_READ_ | address;
309 	int ret;
310 
311 	netif_dbg(pd, hw, pd->dev, "address 0x%x\n", address);
312 	ret = smsc9420_eeprom_send_cmd(pd, op);
313 
314 	if (!ret)
315 		data[address] = smsc9420_reg_read(pd, E2P_DATA);
316 
317 	return ret;
318 }
319 
320 static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
321 					  u8 address, u8 data)
322 {
323 	u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
324 	int ret;
325 
326 	netif_dbg(pd, hw, pd->dev, "address 0x%x, data 0x%x\n", address, data);
327 	ret = smsc9420_eeprom_send_cmd(pd, op);
328 
329 	if (!ret) {
330 		op = E2P_CMD_EPC_CMD_WRITE_ | address;
331 		smsc9420_reg_write(pd, E2P_DATA, (u32)data);
332 		ret = smsc9420_eeprom_send_cmd(pd, op);
333 	}
334 
335 	return ret;
336 }
337 
338 static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev)
339 {
340 	return SMSC9420_EEPROM_SIZE;
341 }
342 
343 static int smsc9420_ethtool_get_eeprom(struct net_device *dev,
344 				       struct ethtool_eeprom *eeprom, u8 *data)
345 {
346 	struct smsc9420_pdata *pd = netdev_priv(dev);
347 	u8 eeprom_data[SMSC9420_EEPROM_SIZE];
348 	int len, i;
349 
350 	smsc9420_eeprom_enable_access(pd);
351 
352 	len = min(eeprom->len, SMSC9420_EEPROM_SIZE);
353 	for (i = 0; i < len; i++) {
354 		int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
355 		if (ret < 0) {
356 			eeprom->len = 0;
357 			return ret;
358 		}
359 	}
360 
361 	memcpy(data, &eeprom_data[eeprom->offset], len);
362 	eeprom->magic = SMSC9420_EEPROM_MAGIC;
363 	eeprom->len = len;
364 	return 0;
365 }
366 
367 static int smsc9420_ethtool_set_eeprom(struct net_device *dev,
368 				       struct ethtool_eeprom *eeprom, u8 *data)
369 {
370 	struct smsc9420_pdata *pd = netdev_priv(dev);
371 	int ret;
372 
373 	if (eeprom->magic != SMSC9420_EEPROM_MAGIC)
374 		return -EINVAL;
375 
376 	smsc9420_eeprom_enable_access(pd);
377 	smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
378 	ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
379 	smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
380 
381 	/* Single byte write, according to man page */
382 	eeprom->len = 1;
383 
384 	return ret;
385 }
386 
387 static const struct ethtool_ops smsc9420_ethtool_ops = {
388 	.get_drvinfo = smsc9420_ethtool_get_drvinfo,
389 	.get_msglevel = smsc9420_ethtool_get_msglevel,
390 	.set_msglevel = smsc9420_ethtool_set_msglevel,
391 	.nway_reset = phy_ethtool_nway_reset,
392 	.get_link = ethtool_op_get_link,
393 	.get_eeprom_len = smsc9420_ethtool_get_eeprom_len,
394 	.get_eeprom = smsc9420_ethtool_get_eeprom,
395 	.set_eeprom = smsc9420_ethtool_set_eeprom,
396 	.get_regs_len = smsc9420_ethtool_getregslen,
397 	.get_regs = smsc9420_ethtool_getregs,
398 	.get_ts_info = ethtool_op_get_ts_info,
399 	.get_link_ksettings = phy_ethtool_get_link_ksettings,
400 	.set_link_ksettings = phy_ethtool_set_link_ksettings,
401 };
402 
403 /* Sets the device MAC address to dev_addr */
404 static void smsc9420_set_mac_address(struct net_device *dev)
405 {
406 	struct smsc9420_pdata *pd = netdev_priv(dev);
407 	const u8 *dev_addr = dev->dev_addr;
408 	u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
409 	u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
410 	    (dev_addr[1] << 8) | dev_addr[0];
411 
412 	smsc9420_reg_write(pd, ADDRH, mac_high16);
413 	smsc9420_reg_write(pd, ADDRL, mac_low32);
414 }
415 
416 static void smsc9420_check_mac_address(struct net_device *dev)
417 {
418 	struct smsc9420_pdata *pd = netdev_priv(dev);
419 	u8 addr[ETH_ALEN];
420 
421 	/* Check if mac address has been specified when bringing interface up */
422 	if (is_valid_ether_addr(dev->dev_addr)) {
423 		smsc9420_set_mac_address(dev);
424 		netif_dbg(pd, probe, pd->dev,
425 			  "MAC Address is specified by configuration\n");
426 	} else {
427 		/* Try reading mac address from device. if EEPROM is present
428 		 * it will already have been set */
429 		u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
430 		u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
431 		addr[0] = (u8)(mac_low32);
432 		addr[1] = (u8)(mac_low32 >> 8);
433 		addr[2] = (u8)(mac_low32 >> 16);
434 		addr[3] = (u8)(mac_low32 >> 24);
435 		addr[4] = (u8)(mac_high16);
436 		addr[5] = (u8)(mac_high16 >> 8);
437 
438 		if (is_valid_ether_addr(addr)) {
439 			/* eeprom values are valid  so use them */
440 			eth_hw_addr_set(dev, addr);
441 			netif_dbg(pd, probe, pd->dev,
442 				  "Mac Address is read from EEPROM\n");
443 		} else {
444 			/* eeprom values are invalid, generate random MAC */
445 			eth_hw_addr_random(dev);
446 			smsc9420_set_mac_address(dev);
447 			netif_dbg(pd, probe, pd->dev,
448 				  "MAC Address is set to random\n");
449 		}
450 	}
451 }
452 
453 static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
454 {
455 	u32 dmac_control, mac_cr, dma_intr_ena;
456 	int timeout = 1000;
457 
458 	/* disable TX DMAC */
459 	dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
460 	dmac_control &= (~DMAC_CONTROL_ST_);
461 	smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
462 
463 	/* Wait max 10ms for transmit process to stop */
464 	while (--timeout) {
465 		if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
466 			break;
467 		udelay(10);
468 	}
469 
470 	if (!timeout)
471 		netif_warn(pd, ifdown, pd->dev, "TX DMAC failed to stop\n");
472 
473 	/* ACK Tx DMAC stop bit */
474 	smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
475 
476 	/* mask TX DMAC interrupts */
477 	dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
478 	dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
479 	smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
480 	smsc9420_pci_flush_write(pd);
481 
482 	/* stop MAC TX */
483 	mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
484 	smsc9420_reg_write(pd, MAC_CR, mac_cr);
485 	smsc9420_pci_flush_write(pd);
486 }
487 
488 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
489 {
490 	int i;
491 
492 	BUG_ON(!pd->tx_ring);
493 
494 	if (!pd->tx_buffers)
495 		return;
496 
497 	for (i = 0; i < TX_RING_SIZE; i++) {
498 		struct sk_buff *skb = pd->tx_buffers[i].skb;
499 
500 		if (skb) {
501 			BUG_ON(!pd->tx_buffers[i].mapping);
502 			dma_unmap_single(&pd->pdev->dev,
503 					 pd->tx_buffers[i].mapping, skb->len,
504 					 DMA_TO_DEVICE);
505 			dev_kfree_skb_any(skb);
506 		}
507 
508 		pd->tx_ring[i].status = 0;
509 		pd->tx_ring[i].length = 0;
510 		pd->tx_ring[i].buffer1 = 0;
511 		pd->tx_ring[i].buffer2 = 0;
512 	}
513 	wmb();
514 
515 	kfree(pd->tx_buffers);
516 	pd->tx_buffers = NULL;
517 
518 	pd->tx_ring_head = 0;
519 	pd->tx_ring_tail = 0;
520 }
521 
522 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
523 {
524 	int i;
525 
526 	BUG_ON(!pd->rx_ring);
527 
528 	if (!pd->rx_buffers)
529 		return;
530 
531 	for (i = 0; i < RX_RING_SIZE; i++) {
532 		if (pd->rx_buffers[i].skb)
533 			dev_kfree_skb_any(pd->rx_buffers[i].skb);
534 
535 		if (pd->rx_buffers[i].mapping)
536 			dma_unmap_single(&pd->pdev->dev,
537 					 pd->rx_buffers[i].mapping,
538 					 PKT_BUF_SZ, DMA_FROM_DEVICE);
539 
540 		pd->rx_ring[i].status = 0;
541 		pd->rx_ring[i].length = 0;
542 		pd->rx_ring[i].buffer1 = 0;
543 		pd->rx_ring[i].buffer2 = 0;
544 	}
545 	wmb();
546 
547 	kfree(pd->rx_buffers);
548 	pd->rx_buffers = NULL;
549 
550 	pd->rx_ring_head = 0;
551 	pd->rx_ring_tail = 0;
552 }
553 
554 static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
555 {
556 	int timeout = 1000;
557 	u32 mac_cr, dmac_control, dma_intr_ena;
558 
559 	/* mask RX DMAC interrupts */
560 	dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
561 	dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
562 	smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
563 	smsc9420_pci_flush_write(pd);
564 
565 	/* stop RX MAC prior to stoping DMA */
566 	mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
567 	smsc9420_reg_write(pd, MAC_CR, mac_cr);
568 	smsc9420_pci_flush_write(pd);
569 
570 	/* stop RX DMAC */
571 	dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
572 	dmac_control &= (~DMAC_CONTROL_SR_);
573 	smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
574 	smsc9420_pci_flush_write(pd);
575 
576 	/* wait up to 10ms for receive to stop */
577 	while (--timeout) {
578 		if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
579 			break;
580 		udelay(10);
581 	}
582 
583 	if (!timeout)
584 		netif_warn(pd, ifdown, pd->dev,
585 			   "RX DMAC did not stop! timeout\n");
586 
587 	/* ACK the Rx DMAC stop bit */
588 	smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
589 }
590 
591 static irqreturn_t smsc9420_isr(int irq, void *dev_id)
592 {
593 	struct smsc9420_pdata *pd = dev_id;
594 	u32 int_cfg, int_sts, int_ctl;
595 	irqreturn_t ret = IRQ_NONE;
596 	ulong flags;
597 
598 	BUG_ON(!pd);
599 	BUG_ON(!pd->ioaddr);
600 
601 	int_cfg = smsc9420_reg_read(pd, INT_CFG);
602 
603 	/* check if it's our interrupt */
604 	if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
605 	    (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
606 		return IRQ_NONE;
607 
608 	int_sts = smsc9420_reg_read(pd, INT_STAT);
609 
610 	if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
611 		u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
612 		u32 ints_to_clear = 0;
613 
614 		if (status & DMAC_STS_TX_) {
615 			ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
616 			netif_wake_queue(pd->dev);
617 		}
618 
619 		if (status & DMAC_STS_RX_) {
620 			/* mask RX DMAC interrupts */
621 			u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
622 			dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
623 			smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
624 			smsc9420_pci_flush_write(pd);
625 
626 			ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
627 			napi_schedule(&pd->napi);
628 		}
629 
630 		if (ints_to_clear)
631 			smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
632 
633 		ret = IRQ_HANDLED;
634 	}
635 
636 	if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
637 		/* mask software interrupt */
638 		spin_lock_irqsave(&pd->int_lock, flags);
639 		int_ctl = smsc9420_reg_read(pd, INT_CTL);
640 		int_ctl &= (~INT_CTL_SW_INT_EN_);
641 		smsc9420_reg_write(pd, INT_CTL, int_ctl);
642 		spin_unlock_irqrestore(&pd->int_lock, flags);
643 
644 		smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
645 		pd->software_irq_signal = true;
646 		smp_wmb();
647 
648 		ret = IRQ_HANDLED;
649 	}
650 
651 	/* to ensure PCI write completion, we must perform a PCI read */
652 	smsc9420_pci_flush_write(pd);
653 
654 	return ret;
655 }
656 
657 #ifdef CONFIG_NET_POLL_CONTROLLER
658 static void smsc9420_poll_controller(struct net_device *dev)
659 {
660 	struct smsc9420_pdata *pd = netdev_priv(dev);
661 	const int irq = pd->pdev->irq;
662 
663 	disable_irq(irq);
664 	smsc9420_isr(0, dev);
665 	enable_irq(irq);
666 }
667 #endif /* CONFIG_NET_POLL_CONTROLLER */
668 
669 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
670 {
671 	smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
672 	smsc9420_reg_read(pd, BUS_MODE);
673 	udelay(2);
674 	if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
675 		netif_warn(pd, drv, pd->dev, "Software reset not cleared\n");
676 }
677 
678 static int smsc9420_stop(struct net_device *dev)
679 {
680 	struct smsc9420_pdata *pd = netdev_priv(dev);
681 	u32 int_cfg;
682 	ulong flags;
683 
684 	BUG_ON(!pd);
685 	BUG_ON(!dev->phydev);
686 
687 	/* disable master interrupt */
688 	spin_lock_irqsave(&pd->int_lock, flags);
689 	int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
690 	smsc9420_reg_write(pd, INT_CFG, int_cfg);
691 	spin_unlock_irqrestore(&pd->int_lock, flags);
692 
693 	netif_tx_disable(dev);
694 	napi_disable(&pd->napi);
695 
696 	smsc9420_stop_tx(pd);
697 	smsc9420_free_tx_ring(pd);
698 
699 	smsc9420_stop_rx(pd);
700 	smsc9420_free_rx_ring(pd);
701 
702 	free_irq(pd->pdev->irq, pd);
703 
704 	smsc9420_dmac_soft_reset(pd);
705 
706 	phy_stop(dev->phydev);
707 
708 	phy_disconnect(dev->phydev);
709 	mdiobus_unregister(pd->mii_bus);
710 	mdiobus_free(pd->mii_bus);
711 
712 	return 0;
713 }
714 
715 static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
716 {
717 	if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
718 		dev->stats.rx_errors++;
719 		if (desc_status & RDES0_DESCRIPTOR_ERROR_)
720 			dev->stats.rx_over_errors++;
721 		else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
722 			RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
723 			dev->stats.rx_frame_errors++;
724 		else if (desc_status & RDES0_CRC_ERROR_)
725 			dev->stats.rx_crc_errors++;
726 	}
727 
728 	if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
729 		dev->stats.rx_length_errors++;
730 
731 	if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
732 		(desc_status & RDES0_FIRST_DESCRIPTOR_))))
733 		dev->stats.rx_length_errors++;
734 
735 	if (desc_status & RDES0_MULTICAST_FRAME_)
736 		dev->stats.multicast++;
737 }
738 
739 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
740 				const u32 status)
741 {
742 	struct net_device *dev = pd->dev;
743 	struct sk_buff *skb;
744 	u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
745 		>> RDES0_FRAME_LENGTH_SHFT_;
746 
747 	/* remove crc from packet lendth */
748 	packet_length -= 4;
749 
750 	if (pd->rx_csum)
751 		packet_length -= 2;
752 
753 	dev->stats.rx_packets++;
754 	dev->stats.rx_bytes += packet_length;
755 
756 	dma_unmap_single(&pd->pdev->dev, pd->rx_buffers[index].mapping,
757 			 PKT_BUF_SZ, DMA_FROM_DEVICE);
758 	pd->rx_buffers[index].mapping = 0;
759 
760 	skb = pd->rx_buffers[index].skb;
761 	pd->rx_buffers[index].skb = NULL;
762 
763 	if (pd->rx_csum) {
764 		u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
765 			NET_IP_ALIGN + packet_length + 4);
766 		put_unaligned_le16(hw_csum, &skb->csum);
767 		skb->ip_summed = CHECKSUM_COMPLETE;
768 	}
769 
770 	skb_reserve(skb, NET_IP_ALIGN);
771 	skb_put(skb, packet_length);
772 
773 	skb->protocol = eth_type_trans(skb, dev);
774 
775 	netif_receive_skb(skb);
776 }
777 
778 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
779 {
780 	struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
781 	dma_addr_t mapping;
782 
783 	BUG_ON(pd->rx_buffers[index].skb);
784 	BUG_ON(pd->rx_buffers[index].mapping);
785 
786 	if (unlikely(!skb))
787 		return -ENOMEM;
788 
789 	mapping = dma_map_single(&pd->pdev->dev, skb_tail_pointer(skb),
790 				 PKT_BUF_SZ, DMA_FROM_DEVICE);
791 	if (dma_mapping_error(&pd->pdev->dev, mapping)) {
792 		dev_kfree_skb_any(skb);
793 		netif_warn(pd, rx_err, pd->dev, "dma_map_single failed!\n");
794 		return -ENOMEM;
795 	}
796 
797 	pd->rx_buffers[index].skb = skb;
798 	pd->rx_buffers[index].mapping = mapping;
799 	pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
800 	pd->rx_ring[index].status = RDES0_OWN_;
801 	wmb();
802 
803 	return 0;
804 }
805 
806 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
807 {
808 	while (pd->rx_ring_tail != pd->rx_ring_head) {
809 		if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
810 			break;
811 
812 		pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
813 	}
814 }
815 
816 static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
817 {
818 	struct smsc9420_pdata *pd =
819 		container_of(napi, struct smsc9420_pdata, napi);
820 	struct net_device *dev = pd->dev;
821 	u32 drop_frame_cnt, dma_intr_ena, status;
822 	int work_done;
823 
824 	for (work_done = 0; work_done < budget; work_done++) {
825 		rmb();
826 		status = pd->rx_ring[pd->rx_ring_head].status;
827 
828 		/* stop if DMAC owns this dma descriptor */
829 		if (status & RDES0_OWN_)
830 			break;
831 
832 		smsc9420_rx_count_stats(dev, status);
833 		smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
834 		pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
835 		smsc9420_alloc_new_rx_buffers(pd);
836 	}
837 
838 	drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
839 	dev->stats.rx_dropped +=
840 	    (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
841 
842 	/* Kick RXDMA */
843 	smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
844 	smsc9420_pci_flush_write(pd);
845 
846 	if (work_done < budget) {
847 		napi_complete_done(&pd->napi, work_done);
848 
849 		/* re-enable RX DMA interrupts */
850 		dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
851 		dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
852 		smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
853 		smsc9420_pci_flush_write(pd);
854 	}
855 	return work_done;
856 }
857 
858 static void
859 smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
860 {
861 	if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
862 		dev->stats.tx_errors++;
863 		if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
864 			TDES0_EXCESSIVE_COLLISIONS_))
865 			dev->stats.tx_aborted_errors++;
866 
867 		if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
868 			dev->stats.tx_carrier_errors++;
869 	} else {
870 		dev->stats.tx_packets++;
871 		dev->stats.tx_bytes += (length & 0x7FF);
872 	}
873 
874 	if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
875 		dev->stats.collisions += 16;
876 	} else {
877 		dev->stats.collisions +=
878 			(status & TDES0_COLLISION_COUNT_MASK_) >>
879 			TDES0_COLLISION_COUNT_SHFT_;
880 	}
881 
882 	if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
883 		dev->stats.tx_heartbeat_errors++;
884 }
885 
886 /* Check for completed dma transfers, update stats and free skbs */
887 static void smsc9420_complete_tx(struct net_device *dev)
888 {
889 	struct smsc9420_pdata *pd = netdev_priv(dev);
890 
891 	while (pd->tx_ring_tail != pd->tx_ring_head) {
892 		int index = pd->tx_ring_tail;
893 		u32 status, length;
894 
895 		rmb();
896 		status = pd->tx_ring[index].status;
897 		length = pd->tx_ring[index].length;
898 
899 		/* Check if DMA still owns this descriptor */
900 		if (unlikely(TDES0_OWN_ & status))
901 			break;
902 
903 		smsc9420_tx_update_stats(dev, status, length);
904 
905 		BUG_ON(!pd->tx_buffers[index].skb);
906 		BUG_ON(!pd->tx_buffers[index].mapping);
907 
908 		dma_unmap_single(&pd->pdev->dev,
909 				 pd->tx_buffers[index].mapping,
910 				 pd->tx_buffers[index].skb->len,
911 				 DMA_TO_DEVICE);
912 		pd->tx_buffers[index].mapping = 0;
913 
914 		dev_kfree_skb_any(pd->tx_buffers[index].skb);
915 		pd->tx_buffers[index].skb = NULL;
916 
917 		pd->tx_ring[index].buffer1 = 0;
918 		wmb();
919 
920 		pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
921 	}
922 }
923 
924 static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb,
925 					    struct net_device *dev)
926 {
927 	struct smsc9420_pdata *pd = netdev_priv(dev);
928 	dma_addr_t mapping;
929 	int index = pd->tx_ring_head;
930 	u32 tmp_desc1;
931 	bool about_to_take_last_desc =
932 		(((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
933 
934 	smsc9420_complete_tx(dev);
935 
936 	rmb();
937 	BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
938 	BUG_ON(pd->tx_buffers[index].skb);
939 	BUG_ON(pd->tx_buffers[index].mapping);
940 
941 	mapping = dma_map_single(&pd->pdev->dev, skb->data, skb->len,
942 				 DMA_TO_DEVICE);
943 	if (dma_mapping_error(&pd->pdev->dev, mapping)) {
944 		netif_warn(pd, tx_err, pd->dev,
945 			   "dma_map_single failed, dropping packet\n");
946 		return NETDEV_TX_BUSY;
947 	}
948 
949 	pd->tx_buffers[index].skb = skb;
950 	pd->tx_buffers[index].mapping = mapping;
951 
952 	tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
953 	if (unlikely(about_to_take_last_desc)) {
954 		tmp_desc1 |= TDES1_IC_;
955 		netif_stop_queue(pd->dev);
956 	}
957 
958 	/* check if we are at the last descriptor and need to set EOR */
959 	if (unlikely(index == (TX_RING_SIZE - 1)))
960 		tmp_desc1 |= TDES1_TER_;
961 
962 	pd->tx_ring[index].buffer1 = mapping;
963 	pd->tx_ring[index].length = tmp_desc1;
964 	wmb();
965 
966 	/* increment head */
967 	pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
968 
969 	/* assign ownership to DMAC */
970 	pd->tx_ring[index].status = TDES0_OWN_;
971 	wmb();
972 
973 	skb_tx_timestamp(skb);
974 
975 	/* kick the DMA */
976 	smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
977 	smsc9420_pci_flush_write(pd);
978 
979 	return NETDEV_TX_OK;
980 }
981 
982 static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
983 {
984 	struct smsc9420_pdata *pd = netdev_priv(dev);
985 	u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
986 	dev->stats.rx_dropped +=
987 	    (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
988 	return &dev->stats;
989 }
990 
991 static void smsc9420_set_multicast_list(struct net_device *dev)
992 {
993 	struct smsc9420_pdata *pd = netdev_priv(dev);
994 	u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
995 
996 	if (dev->flags & IFF_PROMISC) {
997 		netif_dbg(pd, hw, pd->dev, "Promiscuous Mode Enabled\n");
998 		mac_cr |= MAC_CR_PRMS_;
999 		mac_cr &= (~MAC_CR_MCPAS_);
1000 		mac_cr &= (~MAC_CR_HPFILT_);
1001 	} else if (dev->flags & IFF_ALLMULTI) {
1002 		netif_dbg(pd, hw, pd->dev, "Receive all Multicast Enabled\n");
1003 		mac_cr &= (~MAC_CR_PRMS_);
1004 		mac_cr |= MAC_CR_MCPAS_;
1005 		mac_cr &= (~MAC_CR_HPFILT_);
1006 	} else if (!netdev_mc_empty(dev)) {
1007 		struct netdev_hw_addr *ha;
1008 		u32 hash_lo = 0, hash_hi = 0;
1009 
1010 		netif_dbg(pd, hw, pd->dev, "Multicast filter enabled\n");
1011 		netdev_for_each_mc_addr(ha, dev) {
1012 			u32 bit_num = smsc9420_hash(ha->addr);
1013 			u32 mask = 1 << (bit_num & 0x1F);
1014 
1015 			if (bit_num & 0x20)
1016 				hash_hi |= mask;
1017 			else
1018 				hash_lo |= mask;
1019 
1020 		}
1021 		smsc9420_reg_write(pd, HASHH, hash_hi);
1022 		smsc9420_reg_write(pd, HASHL, hash_lo);
1023 
1024 		mac_cr &= (~MAC_CR_PRMS_);
1025 		mac_cr &= (~MAC_CR_MCPAS_);
1026 		mac_cr |= MAC_CR_HPFILT_;
1027 	} else {
1028 		netif_dbg(pd, hw, pd->dev, "Receive own packets only\n");
1029 		smsc9420_reg_write(pd, HASHH, 0);
1030 		smsc9420_reg_write(pd, HASHL, 0);
1031 
1032 		mac_cr &= (~MAC_CR_PRMS_);
1033 		mac_cr &= (~MAC_CR_MCPAS_);
1034 		mac_cr &= (~MAC_CR_HPFILT_);
1035 	}
1036 
1037 	smsc9420_reg_write(pd, MAC_CR, mac_cr);
1038 	smsc9420_pci_flush_write(pd);
1039 }
1040 
1041 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1042 {
1043 	struct net_device *dev = pd->dev;
1044 	struct phy_device *phy_dev = dev->phydev;
1045 	u32 flow;
1046 
1047 	if (phy_dev->duplex == DUPLEX_FULL) {
1048 		u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
1049 		u16 rmtadv = phy_read(phy_dev, MII_LPA);
1050 		u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1051 
1052 		if (cap & FLOW_CTRL_RX)
1053 			flow = 0xFFFF0002;
1054 		else
1055 			flow = 0;
1056 
1057 		netif_info(pd, link, pd->dev, "rx pause %s, tx pause %s\n",
1058 			   cap & FLOW_CTRL_RX ? "enabled" : "disabled",
1059 			   cap & FLOW_CTRL_TX ? "enabled" : "disabled");
1060 	} else {
1061 		netif_info(pd, link, pd->dev, "half duplex\n");
1062 		flow = 0;
1063 	}
1064 
1065 	smsc9420_reg_write(pd, FLOW, flow);
1066 }
1067 
1068 /* Update link mode if anything has changed.  Called periodically when the
1069  * PHY is in polling mode, even if nothing has changed. */
1070 static void smsc9420_phy_adjust_link(struct net_device *dev)
1071 {
1072 	struct smsc9420_pdata *pd = netdev_priv(dev);
1073 	struct phy_device *phy_dev = dev->phydev;
1074 	int carrier;
1075 
1076 	if (phy_dev->duplex != pd->last_duplex) {
1077 		u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1078 		if (phy_dev->duplex) {
1079 			netif_dbg(pd, link, pd->dev, "full duplex mode\n");
1080 			mac_cr |= MAC_CR_FDPX_;
1081 		} else {
1082 			netif_dbg(pd, link, pd->dev, "half duplex mode\n");
1083 			mac_cr &= ~MAC_CR_FDPX_;
1084 		}
1085 		smsc9420_reg_write(pd, MAC_CR, mac_cr);
1086 
1087 		smsc9420_phy_update_flowcontrol(pd);
1088 		pd->last_duplex = phy_dev->duplex;
1089 	}
1090 
1091 	carrier = netif_carrier_ok(dev);
1092 	if (carrier != pd->last_carrier) {
1093 		if (carrier)
1094 			netif_dbg(pd, link, pd->dev, "carrier OK\n");
1095 		else
1096 			netif_dbg(pd, link, pd->dev, "no carrier\n");
1097 		pd->last_carrier = carrier;
1098 	}
1099 }
1100 
1101 static int smsc9420_mii_probe(struct net_device *dev)
1102 {
1103 	struct smsc9420_pdata *pd = netdev_priv(dev);
1104 	struct phy_device *phydev = NULL;
1105 
1106 	BUG_ON(dev->phydev);
1107 
1108 	/* Device only supports internal PHY at address 1 */
1109 	phydev = mdiobus_get_phy(pd->mii_bus, 1);
1110 	if (!phydev) {
1111 		netdev_err(dev, "no PHY found at address 1\n");
1112 		return -ENODEV;
1113 	}
1114 
1115 	phydev = phy_connect(dev, phydev_name(phydev),
1116 			     smsc9420_phy_adjust_link, PHY_INTERFACE_MODE_MII);
1117 
1118 	if (IS_ERR(phydev)) {
1119 		netdev_err(dev, "Could not attach to PHY\n");
1120 		return PTR_ERR(phydev);
1121 	}
1122 
1123 	phy_set_max_speed(phydev, SPEED_100);
1124 
1125 	/* mask with MAC supported features */
1126 	phy_support_asym_pause(phydev);
1127 
1128 	phy_attached_info(phydev);
1129 
1130 	pd->last_duplex = -1;
1131 	pd->last_carrier = -1;
1132 
1133 	return 0;
1134 }
1135 
1136 static int smsc9420_mii_init(struct net_device *dev)
1137 {
1138 	struct smsc9420_pdata *pd = netdev_priv(dev);
1139 	int err = -ENXIO;
1140 
1141 	pd->mii_bus = mdiobus_alloc();
1142 	if (!pd->mii_bus) {
1143 		err = -ENOMEM;
1144 		goto err_out_1;
1145 	}
1146 	pd->mii_bus->name = DRV_MDIONAME;
1147 	snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x", pci_dev_id(pd->pdev));
1148 	pd->mii_bus->priv = pd;
1149 	pd->mii_bus->read = smsc9420_mii_read;
1150 	pd->mii_bus->write = smsc9420_mii_write;
1151 
1152 	/* Mask all PHYs except ID 1 (internal) */
1153 	pd->mii_bus->phy_mask = ~(1 << 1);
1154 
1155 	if (mdiobus_register(pd->mii_bus)) {
1156 		netif_warn(pd, probe, pd->dev, "Error registering mii bus\n");
1157 		goto err_out_free_bus_2;
1158 	}
1159 
1160 	if (smsc9420_mii_probe(dev) < 0) {
1161 		netif_warn(pd, probe, pd->dev, "Error probing mii bus\n");
1162 		goto err_out_unregister_bus_3;
1163 	}
1164 
1165 	return 0;
1166 
1167 err_out_unregister_bus_3:
1168 	mdiobus_unregister(pd->mii_bus);
1169 err_out_free_bus_2:
1170 	mdiobus_free(pd->mii_bus);
1171 err_out_1:
1172 	return err;
1173 }
1174 
1175 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1176 {
1177 	int i;
1178 
1179 	BUG_ON(!pd->tx_ring);
1180 
1181 	pd->tx_buffers = kmalloc_array(TX_RING_SIZE,
1182 				       sizeof(struct smsc9420_ring_info),
1183 				       GFP_KERNEL);
1184 	if (!pd->tx_buffers)
1185 		return -ENOMEM;
1186 
1187 	/* Initialize the TX Ring */
1188 	for (i = 0; i < TX_RING_SIZE; i++) {
1189 		pd->tx_buffers[i].skb = NULL;
1190 		pd->tx_buffers[i].mapping = 0;
1191 		pd->tx_ring[i].status = 0;
1192 		pd->tx_ring[i].length = 0;
1193 		pd->tx_ring[i].buffer1 = 0;
1194 		pd->tx_ring[i].buffer2 = 0;
1195 	}
1196 	pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1197 	wmb();
1198 
1199 	pd->tx_ring_head = 0;
1200 	pd->tx_ring_tail = 0;
1201 
1202 	smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1203 	smsc9420_pci_flush_write(pd);
1204 
1205 	return 0;
1206 }
1207 
1208 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1209 {
1210 	int i;
1211 
1212 	BUG_ON(!pd->rx_ring);
1213 
1214 	pd->rx_buffers = kmalloc_array(RX_RING_SIZE,
1215 				       sizeof(struct smsc9420_ring_info),
1216 				       GFP_KERNEL);
1217 	if (pd->rx_buffers == NULL)
1218 		goto out;
1219 
1220 	/* initialize the rx ring */
1221 	for (i = 0; i < RX_RING_SIZE; i++) {
1222 		pd->rx_ring[i].status = 0;
1223 		pd->rx_ring[i].length = PKT_BUF_SZ;
1224 		pd->rx_ring[i].buffer2 = 0;
1225 		pd->rx_buffers[i].skb = NULL;
1226 		pd->rx_buffers[i].mapping = 0;
1227 	}
1228 	pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1229 
1230 	/* now allocate the entire ring of skbs */
1231 	for (i = 0; i < RX_RING_SIZE; i++) {
1232 		if (smsc9420_alloc_rx_buffer(pd, i)) {
1233 			netif_warn(pd, ifup, pd->dev,
1234 				   "failed to allocate rx skb %d\n", i);
1235 			goto out_free_rx_skbs;
1236 		}
1237 	}
1238 
1239 	pd->rx_ring_head = 0;
1240 	pd->rx_ring_tail = 0;
1241 
1242 	smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1243 	netif_dbg(pd, ifup, pd->dev, "VLAN1 = 0x%08x\n",
1244 		  smsc9420_reg_read(pd, VLAN1));
1245 
1246 	if (pd->rx_csum) {
1247 		/* Enable RX COE */
1248 		u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1249 		smsc9420_reg_write(pd, COE_CR, coe);
1250 		netif_dbg(pd, ifup, pd->dev, "COE_CR = 0x%08x\n", coe);
1251 	}
1252 
1253 	smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1254 	smsc9420_pci_flush_write(pd);
1255 
1256 	return 0;
1257 
1258 out_free_rx_skbs:
1259 	smsc9420_free_rx_ring(pd);
1260 out:
1261 	return -ENOMEM;
1262 }
1263 
1264 static int smsc9420_open(struct net_device *dev)
1265 {
1266 	struct smsc9420_pdata *pd = netdev_priv(dev);
1267 	u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
1268 	const int irq = pd->pdev->irq;
1269 	unsigned long flags;
1270 	int result = 0, timeout;
1271 
1272 	if (!is_valid_ether_addr(dev->dev_addr)) {
1273 		netif_warn(pd, ifup, pd->dev,
1274 			   "dev_addr is not a valid MAC address\n");
1275 		result = -EADDRNOTAVAIL;
1276 		goto out_0;
1277 	}
1278 
1279 	netif_carrier_off(dev);
1280 
1281 	/* disable, mask and acknowledge all interrupts */
1282 	spin_lock_irqsave(&pd->int_lock, flags);
1283 	int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1284 	smsc9420_reg_write(pd, INT_CFG, int_cfg);
1285 	smsc9420_reg_write(pd, INT_CTL, 0);
1286 	spin_unlock_irqrestore(&pd->int_lock, flags);
1287 	smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1288 	smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1289 	smsc9420_pci_flush_write(pd);
1290 
1291 	result = request_irq(irq, smsc9420_isr, IRQF_SHARED, DRV_NAME, pd);
1292 	if (result) {
1293 		netif_warn(pd, ifup, pd->dev, "Unable to use IRQ = %d\n", irq);
1294 		result = -ENODEV;
1295 		goto out_0;
1296 	}
1297 
1298 	smsc9420_dmac_soft_reset(pd);
1299 
1300 	/* make sure MAC_CR is sane */
1301 	smsc9420_reg_write(pd, MAC_CR, 0);
1302 
1303 	smsc9420_set_mac_address(dev);
1304 
1305 	/* Configure GPIO pins to drive LEDs */
1306 	smsc9420_reg_write(pd, GPIO_CFG,
1307 		(GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
1308 
1309 	bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
1310 
1311 #ifdef __BIG_ENDIAN
1312 	bus_mode |= BUS_MODE_DBO_;
1313 #endif
1314 
1315 	smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1316 
1317 	smsc9420_pci_flush_write(pd);
1318 
1319 	/* set bus master bridge arbitration priority for Rx and TX DMA */
1320 	smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1321 
1322 	smsc9420_reg_write(pd, DMAC_CONTROL,
1323 		(DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
1324 
1325 	smsc9420_pci_flush_write(pd);
1326 
1327 	/* test the IRQ connection to the ISR */
1328 	netif_dbg(pd, ifup, pd->dev, "Testing ISR using IRQ %d\n", irq);
1329 	pd->software_irq_signal = false;
1330 
1331 	spin_lock_irqsave(&pd->int_lock, flags);
1332 	/* configure interrupt deassertion timer and enable interrupts */
1333 	int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1334 	int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
1335 	int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
1336 	smsc9420_reg_write(pd, INT_CFG, int_cfg);
1337 
1338 	/* unmask software interrupt */
1339 	int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1340 	smsc9420_reg_write(pd, INT_CTL, int_ctl);
1341 	spin_unlock_irqrestore(&pd->int_lock, flags);
1342 	smsc9420_pci_flush_write(pd);
1343 
1344 	timeout = 1000;
1345 	while (timeout--) {
1346 		if (pd->software_irq_signal)
1347 			break;
1348 		msleep(1);
1349 	}
1350 
1351 	/* disable interrupts */
1352 	spin_lock_irqsave(&pd->int_lock, flags);
1353 	int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1354 	smsc9420_reg_write(pd, INT_CFG, int_cfg);
1355 	spin_unlock_irqrestore(&pd->int_lock, flags);
1356 
1357 	if (!pd->software_irq_signal) {
1358 		netif_warn(pd, ifup, pd->dev, "ISR failed signaling test\n");
1359 		result = -ENODEV;
1360 		goto out_free_irq_1;
1361 	}
1362 
1363 	netif_dbg(pd, ifup, pd->dev, "ISR passed test using IRQ %d\n", irq);
1364 
1365 	result = smsc9420_alloc_tx_ring(pd);
1366 	if (result) {
1367 		netif_warn(pd, ifup, pd->dev,
1368 			   "Failed to Initialize tx dma ring\n");
1369 		result = -ENOMEM;
1370 		goto out_free_irq_1;
1371 	}
1372 
1373 	result = smsc9420_alloc_rx_ring(pd);
1374 	if (result) {
1375 		netif_warn(pd, ifup, pd->dev,
1376 			   "Failed to Initialize rx dma ring\n");
1377 		result = -ENOMEM;
1378 		goto out_free_tx_ring_2;
1379 	}
1380 
1381 	result = smsc9420_mii_init(dev);
1382 	if (result) {
1383 		netif_warn(pd, ifup, pd->dev, "Failed to initialize Phy\n");
1384 		result = -ENODEV;
1385 		goto out_free_rx_ring_3;
1386 	}
1387 
1388 	/* Bring the PHY up */
1389 	phy_start(dev->phydev);
1390 
1391 	napi_enable(&pd->napi);
1392 
1393 	/* start tx and rx */
1394 	mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1395 	smsc9420_reg_write(pd, MAC_CR, mac_cr);
1396 
1397 	dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1398 	dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
1399 	smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1400 	smsc9420_pci_flush_write(pd);
1401 
1402 	dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1403 	dma_intr_ena |=
1404 		(DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
1405 	smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1406 	smsc9420_pci_flush_write(pd);
1407 
1408 	netif_wake_queue(dev);
1409 
1410 	smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1411 
1412 	/* enable interrupts */
1413 	spin_lock_irqsave(&pd->int_lock, flags);
1414 	int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1415 	smsc9420_reg_write(pd, INT_CFG, int_cfg);
1416 	spin_unlock_irqrestore(&pd->int_lock, flags);
1417 
1418 	return 0;
1419 
1420 out_free_rx_ring_3:
1421 	smsc9420_free_rx_ring(pd);
1422 out_free_tx_ring_2:
1423 	smsc9420_free_tx_ring(pd);
1424 out_free_irq_1:
1425 	free_irq(irq, pd);
1426 out_0:
1427 	return result;
1428 }
1429 
1430 static int __maybe_unused smsc9420_suspend(struct device *dev_d)
1431 {
1432 	struct net_device *dev = dev_get_drvdata(dev_d);
1433 	struct smsc9420_pdata *pd = netdev_priv(dev);
1434 	u32 int_cfg;
1435 	ulong flags;
1436 
1437 	/* disable interrupts */
1438 	spin_lock_irqsave(&pd->int_lock, flags);
1439 	int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1440 	smsc9420_reg_write(pd, INT_CFG, int_cfg);
1441 	spin_unlock_irqrestore(&pd->int_lock, flags);
1442 
1443 	if (netif_running(dev)) {
1444 		netif_tx_disable(dev);
1445 		smsc9420_stop_tx(pd);
1446 		smsc9420_free_tx_ring(pd);
1447 
1448 		napi_disable(&pd->napi);
1449 		smsc9420_stop_rx(pd);
1450 		smsc9420_free_rx_ring(pd);
1451 
1452 		free_irq(pd->pdev->irq, pd);
1453 
1454 		netif_device_detach(dev);
1455 	}
1456 
1457 	device_wakeup_disable(dev_d);
1458 
1459 	return 0;
1460 }
1461 
1462 static int __maybe_unused smsc9420_resume(struct device *dev_d)
1463 {
1464 	struct net_device *dev = dev_get_drvdata(dev_d);
1465 	int err;
1466 
1467 	pci_set_master(to_pci_dev(dev_d));
1468 
1469 	device_wakeup_disable(dev_d);
1470 
1471 	err = 0;
1472 	if (netif_running(dev)) {
1473 		/* FIXME: gross. It looks like ancient PM relic.*/
1474 		err = smsc9420_open(dev);
1475 		netif_device_attach(dev);
1476 	}
1477 	return err;
1478 }
1479 
1480 static const struct net_device_ops smsc9420_netdev_ops = {
1481 	.ndo_open		= smsc9420_open,
1482 	.ndo_stop		= smsc9420_stop,
1483 	.ndo_start_xmit		= smsc9420_hard_start_xmit,
1484 	.ndo_get_stats		= smsc9420_get_stats,
1485 	.ndo_set_rx_mode	= smsc9420_set_multicast_list,
1486 	.ndo_eth_ioctl		= phy_do_ioctl_running,
1487 	.ndo_validate_addr	= eth_validate_addr,
1488 	.ndo_set_mac_address 	= eth_mac_addr,
1489 #ifdef CONFIG_NET_POLL_CONTROLLER
1490 	.ndo_poll_controller	= smsc9420_poll_controller,
1491 #endif /* CONFIG_NET_POLL_CONTROLLER */
1492 };
1493 
1494 static int
1495 smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1496 {
1497 	struct net_device *dev;
1498 	struct smsc9420_pdata *pd;
1499 	void __iomem *virt_addr;
1500 	int result = 0;
1501 	u32 id_rev;
1502 
1503 	pr_info("%s version %s\n", DRV_DESCRIPTION, DRV_VERSION);
1504 
1505 	/* First do the PCI initialisation */
1506 	result = pci_enable_device(pdev);
1507 	if (unlikely(result)) {
1508 		pr_err("Cannot enable smsc9420\n");
1509 		goto out_0;
1510 	}
1511 
1512 	pci_set_master(pdev);
1513 
1514 	dev = alloc_etherdev(sizeof(*pd));
1515 	if (!dev)
1516 		goto out_disable_pci_device_1;
1517 
1518 	SET_NETDEV_DEV(dev, &pdev->dev);
1519 
1520 	if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
1521 		netdev_err(dev, "Cannot find PCI device base address\n");
1522 		goto out_free_netdev_2;
1523 	}
1524 
1525 	if ((pci_request_regions(pdev, DRV_NAME))) {
1526 		netdev_err(dev, "Cannot obtain PCI resources, aborting\n");
1527 		goto out_free_netdev_2;
1528 	}
1529 
1530 	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
1531 		netdev_err(dev, "No usable DMA configuration, aborting\n");
1532 		goto out_free_regions_3;
1533 	}
1534 
1535 	virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
1536 		pci_resource_len(pdev, SMSC_BAR));
1537 	if (!virt_addr) {
1538 		netdev_err(dev, "Cannot map device registers, aborting\n");
1539 		goto out_free_regions_3;
1540 	}
1541 
1542 	/* registers are double mapped with 0 offset for LE and 0x200 for BE */
1543 	virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
1544 
1545 	pd = netdev_priv(dev);
1546 
1547 	/* pci descriptors are created in the PCI consistent area */
1548 	pd->rx_ring = dma_alloc_coherent(&pdev->dev,
1549 		sizeof(struct smsc9420_dma_desc) * (RX_RING_SIZE + TX_RING_SIZE),
1550 		&pd->rx_dma_addr, GFP_KERNEL);
1551 
1552 	if (!pd->rx_ring)
1553 		goto out_free_io_4;
1554 
1555 	/* descriptors are aligned due to the nature of dma_alloc_coherent */
1556 	pd->tx_ring = (pd->rx_ring + RX_RING_SIZE);
1557 	pd->tx_dma_addr = pd->rx_dma_addr +
1558 	    sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
1559 
1560 	pd->pdev = pdev;
1561 	pd->dev = dev;
1562 	pd->ioaddr = virt_addr;
1563 	pd->msg_enable = smsc_debug;
1564 	pd->rx_csum = true;
1565 
1566 	netif_dbg(pd, probe, pd->dev, "lan_base=0x%08lx\n", (ulong)virt_addr);
1567 
1568 	id_rev = smsc9420_reg_read(pd, ID_REV);
1569 	switch (id_rev & 0xFFFF0000) {
1570 	case 0x94200000:
1571 		netif_info(pd, probe, pd->dev,
1572 			   "LAN9420 identified, ID_REV=0x%08X\n", id_rev);
1573 		break;
1574 	default:
1575 		netif_warn(pd, probe, pd->dev, "LAN9420 NOT identified\n");
1576 		netif_warn(pd, probe, pd->dev, "ID_REV=0x%08X\n", id_rev);
1577 		goto out_free_dmadesc_5;
1578 	}
1579 
1580 	smsc9420_dmac_soft_reset(pd);
1581 	smsc9420_eeprom_reload(pd);
1582 	smsc9420_check_mac_address(dev);
1583 
1584 	dev->netdev_ops = &smsc9420_netdev_ops;
1585 	dev->ethtool_ops = &smsc9420_ethtool_ops;
1586 
1587 	netif_napi_add(dev, &pd->napi, smsc9420_rx_poll);
1588 
1589 	result = register_netdev(dev);
1590 	if (result) {
1591 		netif_warn(pd, probe, pd->dev, "error %i registering device\n",
1592 			   result);
1593 		goto out_free_dmadesc_5;
1594 	}
1595 
1596 	pci_set_drvdata(pdev, dev);
1597 
1598 	spin_lock_init(&pd->int_lock);
1599 	spin_lock_init(&pd->phy_lock);
1600 
1601 	dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1602 
1603 	return 0;
1604 
1605 out_free_dmadesc_5:
1606 	dma_free_coherent(&pdev->dev,
1607 			  sizeof(struct smsc9420_dma_desc) * (RX_RING_SIZE + TX_RING_SIZE),
1608 			  pd->rx_ring, pd->rx_dma_addr);
1609 out_free_io_4:
1610 	iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1611 out_free_regions_3:
1612 	pci_release_regions(pdev);
1613 out_free_netdev_2:
1614 	free_netdev(dev);
1615 out_disable_pci_device_1:
1616 	pci_disable_device(pdev);
1617 out_0:
1618 	return -ENODEV;
1619 }
1620 
1621 static void smsc9420_remove(struct pci_dev *pdev)
1622 {
1623 	struct net_device *dev;
1624 	struct smsc9420_pdata *pd;
1625 
1626 	dev = pci_get_drvdata(pdev);
1627 	if (!dev)
1628 		return;
1629 
1630 	pd = netdev_priv(dev);
1631 	unregister_netdev(dev);
1632 
1633 	/* tx_buffers and rx_buffers are freed in stop */
1634 	BUG_ON(pd->tx_buffers);
1635 	BUG_ON(pd->rx_buffers);
1636 
1637 	BUG_ON(!pd->tx_ring);
1638 	BUG_ON(!pd->rx_ring);
1639 
1640 	dma_free_coherent(&pdev->dev,
1641 			  sizeof(struct smsc9420_dma_desc) * (RX_RING_SIZE + TX_RING_SIZE),
1642 			  pd->rx_ring, pd->rx_dma_addr);
1643 
1644 	iounmap(pd->ioaddr - LAN9420_CPSR_ENDIAN_OFFSET);
1645 	pci_release_regions(pdev);
1646 	free_netdev(dev);
1647 	pci_disable_device(pdev);
1648 }
1649 
1650 static SIMPLE_DEV_PM_OPS(smsc9420_pm_ops, smsc9420_suspend, smsc9420_resume);
1651 
1652 static struct pci_driver smsc9420_driver = {
1653 	.name = DRV_NAME,
1654 	.id_table = smsc9420_id_table,
1655 	.probe = smsc9420_probe,
1656 	.remove = smsc9420_remove,
1657 	.driver.pm = &smsc9420_pm_ops,
1658 };
1659 
1660 static int __init smsc9420_init_module(void)
1661 {
1662 	smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
1663 
1664 	return pci_register_driver(&smsc9420_driver);
1665 }
1666 
1667 static void __exit smsc9420_exit_module(void)
1668 {
1669 	pci_unregister_driver(&smsc9420_driver);
1670 }
1671 
1672 module_init(smsc9420_init_module);
1673 module_exit(smsc9420_exit_module);
1674