1 /*************************************************************************** 2 * 3 * Copyright (C) 2004-2008 SMSC 4 * Copyright (C) 2005-2008 ARM 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 * 19 ***************************************************************************/ 20 #ifndef __SMSC911X_H__ 21 #define __SMSC911X_H__ 22 23 #define TX_FIFO_LOW_THRESHOLD ((u32)1600) 24 #define SMSC911X_EEPROM_SIZE ((u32)128) 25 #define USE_DEBUG 0 26 27 /* This is the maximum number of packets to be received every 28 * NAPI poll */ 29 #define SMSC_NAPI_WEIGHT 16 30 31 /* implements a PHY loopback test at initialisation time, to ensure a packet 32 * can be successfully looped back */ 33 #define USE_PHY_WORK_AROUND 34 35 #if USE_DEBUG >= 1 36 #define SMSC_WARN(pdata, nlevel, fmt, args...) \ 37 netif_warn(pdata, nlevel, (pdata)->dev, \ 38 "%s: " fmt "\n", __func__, ##args) 39 #else 40 #define SMSC_WARN(pdata, nlevel, fmt, args...) \ 41 no_printk(fmt "\n", ##args) 42 #endif 43 44 #if USE_DEBUG >= 2 45 #define SMSC_TRACE(pdata, nlevel, fmt, args...) \ 46 netif_info(pdata, nlevel, pdata->dev, fmt "\n", ##args) 47 #else 48 #define SMSC_TRACE(pdata, nlevel, fmt, args...) \ 49 no_printk(fmt "\n", ##args) 50 #endif 51 52 #ifdef CONFIG_DEBUG_SPINLOCK 53 #define SMSC_ASSERT_MAC_LOCK(pdata) \ 54 WARN_ON(!spin_is_locked(&pdata->mac_lock)) 55 #else 56 #define SMSC_ASSERT_MAC_LOCK(pdata) do {} while (0) 57 #endif /* CONFIG_DEBUG_SPINLOCK */ 58 59 /* SMSC911x registers and bitfields */ 60 #define RX_DATA_FIFO 0x00 61 62 #define TX_DATA_FIFO 0x20 63 #define TX_CMD_A_ON_COMP_ 0x80000000 64 #define TX_CMD_A_BUF_END_ALGN_ 0x03000000 65 #define TX_CMD_A_4_BYTE_ALGN_ 0x00000000 66 #define TX_CMD_A_16_BYTE_ALGN_ 0x01000000 67 #define TX_CMD_A_32_BYTE_ALGN_ 0x02000000 68 #define TX_CMD_A_DATA_OFFSET_ 0x001F0000 69 #define TX_CMD_A_FIRST_SEG_ 0x00002000 70 #define TX_CMD_A_LAST_SEG_ 0x00001000 71 #define TX_CMD_A_BUF_SIZE_ 0x000007FF 72 #define TX_CMD_B_PKT_TAG_ 0xFFFF0000 73 #define TX_CMD_B_ADD_CRC_DISABLE_ 0x00002000 74 #define TX_CMD_B_DISABLE_PADDING_ 0x00001000 75 #define TX_CMD_B_PKT_BYTE_LENGTH_ 0x000007FF 76 77 #define RX_STATUS_FIFO 0x40 78 #define RX_STS_ES_ 0x00008000 79 #define RX_STS_LENGTH_ERR_ 0x00001000 80 #define RX_STS_MCAST_ 0x00000400 81 #define RX_STS_FRAME_TYPE_ 0x00000020 82 #define RX_STS_CRC_ERR_ 0x00000002 83 84 #define RX_STATUS_FIFO_PEEK 0x44 85 86 #define TX_STATUS_FIFO 0x48 87 #define TX_STS_ES_ 0x00008000 88 #define TX_STS_LOST_CARRIER_ 0x00000800 89 #define TX_STS_NO_CARRIER_ 0x00000400 90 #define TX_STS_LATE_COL_ 0x00000200 91 #define TX_STS_EXCESS_COL_ 0x00000100 92 93 #define TX_STATUS_FIFO_PEEK 0x4C 94 95 #define ID_REV 0x50 96 #define ID_REV_CHIP_ID_ 0xFFFF0000 97 #define ID_REV_REV_ID_ 0x0000FFFF 98 99 #define INT_CFG 0x54 100 #define INT_CFG_INT_DEAS_ 0xFF000000 101 #define INT_CFG_INT_DEAS_CLR_ 0x00004000 102 #define INT_CFG_INT_DEAS_STS_ 0x00002000 103 #define INT_CFG_IRQ_INT_ 0x00001000 104 #define INT_CFG_IRQ_EN_ 0x00000100 105 #define INT_CFG_IRQ_POL_ 0x00000010 106 #define INT_CFG_IRQ_TYPE_ 0x00000001 107 108 #define INT_STS 0x58 109 #define INT_STS_SW_INT_ 0x80000000 110 #define INT_STS_TXSTOP_INT_ 0x02000000 111 #define INT_STS_RXSTOP_INT_ 0x01000000 112 #define INT_STS_RXDFH_INT_ 0x00800000 113 #define INT_STS_RXDF_INT_ 0x00400000 114 #define INT_STS_TX_IOC_ 0x00200000 115 #define INT_STS_RXD_INT_ 0x00100000 116 #define INT_STS_GPT_INT_ 0x00080000 117 #define INT_STS_PHY_INT_ 0x00040000 118 #define INT_STS_PME_INT_ 0x00020000 119 #define INT_STS_TXSO_ 0x00010000 120 #define INT_STS_RWT_ 0x00008000 121 #define INT_STS_RXE_ 0x00004000 122 #define INT_STS_TXE_ 0x00002000 123 #define INT_STS_TDFU_ 0x00000800 124 #define INT_STS_TDFO_ 0x00000400 125 #define INT_STS_TDFA_ 0x00000200 126 #define INT_STS_TSFF_ 0x00000100 127 #define INT_STS_TSFL_ 0x00000080 128 #define INT_STS_RXDF_ 0x00000040 129 #define INT_STS_RDFL_ 0x00000020 130 #define INT_STS_RSFF_ 0x00000010 131 #define INT_STS_RSFL_ 0x00000008 132 #define INT_STS_GPIO2_INT_ 0x00000004 133 #define INT_STS_GPIO1_INT_ 0x00000002 134 #define INT_STS_GPIO0_INT_ 0x00000001 135 136 #define INT_EN 0x5C 137 #define INT_EN_SW_INT_EN_ 0x80000000 138 #define INT_EN_TXSTOP_INT_EN_ 0x02000000 139 #define INT_EN_RXSTOP_INT_EN_ 0x01000000 140 #define INT_EN_RXDFH_INT_EN_ 0x00800000 141 #define INT_EN_TIOC_INT_EN_ 0x00200000 142 #define INT_EN_RXD_INT_EN_ 0x00100000 143 #define INT_EN_GPT_INT_EN_ 0x00080000 144 #define INT_EN_PHY_INT_EN_ 0x00040000 145 #define INT_EN_PME_INT_EN_ 0x00020000 146 #define INT_EN_TXSO_EN_ 0x00010000 147 #define INT_EN_RWT_EN_ 0x00008000 148 #define INT_EN_RXE_EN_ 0x00004000 149 #define INT_EN_TXE_EN_ 0x00002000 150 #define INT_EN_TDFU_EN_ 0x00000800 151 #define INT_EN_TDFO_EN_ 0x00000400 152 #define INT_EN_TDFA_EN_ 0x00000200 153 #define INT_EN_TSFF_EN_ 0x00000100 154 #define INT_EN_TSFL_EN_ 0x00000080 155 #define INT_EN_RXDF_EN_ 0x00000040 156 #define INT_EN_RDFL_EN_ 0x00000020 157 #define INT_EN_RSFF_EN_ 0x00000010 158 #define INT_EN_RSFL_EN_ 0x00000008 159 #define INT_EN_GPIO2_INT_ 0x00000004 160 #define INT_EN_GPIO1_INT_ 0x00000002 161 #define INT_EN_GPIO0_INT_ 0x00000001 162 163 #define BYTE_TEST 0x64 164 165 #define FIFO_INT 0x68 166 #define FIFO_INT_TX_AVAIL_LEVEL_ 0xFF000000 167 #define FIFO_INT_TX_STS_LEVEL_ 0x00FF0000 168 #define FIFO_INT_RX_AVAIL_LEVEL_ 0x0000FF00 169 #define FIFO_INT_RX_STS_LEVEL_ 0x000000FF 170 171 #define RX_CFG 0x6C 172 #define RX_CFG_RX_END_ALGN_ 0xC0000000 173 #define RX_CFG_RX_END_ALGN4_ 0x00000000 174 #define RX_CFG_RX_END_ALGN16_ 0x40000000 175 #define RX_CFG_RX_END_ALGN32_ 0x80000000 176 #define RX_CFG_RX_DMA_CNT_ 0x0FFF0000 177 #define RX_CFG_RX_DUMP_ 0x00008000 178 #define RX_CFG_RXDOFF_ 0x00001F00 179 180 #define TX_CFG 0x70 181 #define TX_CFG_TXS_DUMP_ 0x00008000 182 #define TX_CFG_TXD_DUMP_ 0x00004000 183 #define TX_CFG_TXSAO_ 0x00000004 184 #define TX_CFG_TX_ON_ 0x00000002 185 #define TX_CFG_STOP_TX_ 0x00000001 186 187 #define HW_CFG 0x74 188 #define HW_CFG_TTM_ 0x00200000 189 #define HW_CFG_SF_ 0x00100000 190 #define HW_CFG_TX_FIF_SZ_ 0x000F0000 191 #define HW_CFG_TR_ 0x00003000 192 #define HW_CFG_SRST_ 0x00000001 193 194 /* only available on 115/117 */ 195 #define HW_CFG_PHY_CLK_SEL_ 0x00000060 196 #define HW_CFG_PHY_CLK_SEL_INT_PHY_ 0x00000000 197 #define HW_CFG_PHY_CLK_SEL_EXT_PHY_ 0x00000020 198 #define HW_CFG_PHY_CLK_SEL_CLK_DIS_ 0x00000040 199 #define HW_CFG_SMI_SEL_ 0x00000010 200 #define HW_CFG_EXT_PHY_DET_ 0x00000008 201 #define HW_CFG_EXT_PHY_EN_ 0x00000004 202 #define HW_CFG_SRST_TO_ 0x00000002 203 204 /* only available on 116/118 */ 205 #define HW_CFG_32_16_BIT_MODE_ 0x00000004 206 207 #define RX_DP_CTRL 0x78 208 #define RX_DP_CTRL_RX_FFWD_ 0x80000000 209 210 #define RX_FIFO_INF 0x7C 211 #define RX_FIFO_INF_RXSUSED_ 0x00FF0000 212 #define RX_FIFO_INF_RXDUSED_ 0x0000FFFF 213 214 #define TX_FIFO_INF 0x80 215 #define TX_FIFO_INF_TSUSED_ 0x00FF0000 216 #define TX_FIFO_INF_TDFREE_ 0x0000FFFF 217 218 #define PMT_CTRL 0x84 219 #define PMT_CTRL_PM_MODE_ 0x00003000 220 #define PMT_CTRL_PM_MODE_D0_ 0x00000000 221 #define PMT_CTRL_PM_MODE_D1_ 0x00001000 222 #define PMT_CTRL_PM_MODE_D2_ 0x00002000 223 #define PMT_CTRL_PM_MODE_D3_ 0x00003000 224 #define PMT_CTRL_PHY_RST_ 0x00000400 225 #define PMT_CTRL_WOL_EN_ 0x00000200 226 #define PMT_CTRL_ED_EN_ 0x00000100 227 #define PMT_CTRL_PME_TYPE_ 0x00000040 228 #define PMT_CTRL_WUPS_ 0x00000030 229 #define PMT_CTRL_WUPS_NOWAKE_ 0x00000000 230 #define PMT_CTRL_WUPS_ED_ 0x00000010 231 #define PMT_CTRL_WUPS_WOL_ 0x00000020 232 #define PMT_CTRL_WUPS_MULTI_ 0x00000030 233 #define PMT_CTRL_PME_IND_ 0x00000008 234 #define PMT_CTRL_PME_POL_ 0x00000004 235 #define PMT_CTRL_PME_EN_ 0x00000002 236 #define PMT_CTRL_READY_ 0x00000001 237 238 #define GPIO_CFG 0x88 239 #define GPIO_CFG_LED3_EN_ 0x40000000 240 #define GPIO_CFG_LED2_EN_ 0x20000000 241 #define GPIO_CFG_LED1_EN_ 0x10000000 242 #define GPIO_CFG_GPIO2_INT_POL_ 0x04000000 243 #define GPIO_CFG_GPIO1_INT_POL_ 0x02000000 244 #define GPIO_CFG_GPIO0_INT_POL_ 0x01000000 245 #define GPIO_CFG_EEPR_EN_ 0x00700000 246 #define GPIO_CFG_GPIOBUF2_ 0x00040000 247 #define GPIO_CFG_GPIOBUF1_ 0x00020000 248 #define GPIO_CFG_GPIOBUF0_ 0x00010000 249 #define GPIO_CFG_GPIODIR2_ 0x00000400 250 #define GPIO_CFG_GPIODIR1_ 0x00000200 251 #define GPIO_CFG_GPIODIR0_ 0x00000100 252 #define GPIO_CFG_GPIOD4_ 0x00000020 253 #define GPIO_CFG_GPIOD3_ 0x00000010 254 #define GPIO_CFG_GPIOD2_ 0x00000004 255 #define GPIO_CFG_GPIOD1_ 0x00000002 256 #define GPIO_CFG_GPIOD0_ 0x00000001 257 258 #define GPT_CFG 0x8C 259 #define GPT_CFG_TIMER_EN_ 0x20000000 260 #define GPT_CFG_GPT_LOAD_ 0x0000FFFF 261 262 #define GPT_CNT 0x90 263 #define GPT_CNT_GPT_CNT_ 0x0000FFFF 264 265 #define WORD_SWAP 0x98 266 267 #define FREE_RUN 0x9C 268 269 #define RX_DROP 0xA0 270 271 #define MAC_CSR_CMD 0xA4 272 #define MAC_CSR_CMD_CSR_BUSY_ 0x80000000 273 #define MAC_CSR_CMD_R_NOT_W_ 0x40000000 274 #define MAC_CSR_CMD_CSR_ADDR_ 0x000000FF 275 276 #define MAC_CSR_DATA 0xA8 277 278 #define AFC_CFG 0xAC 279 #define AFC_CFG_AFC_HI_ 0x00FF0000 280 #define AFC_CFG_AFC_LO_ 0x0000FF00 281 #define AFC_CFG_BACK_DUR_ 0x000000F0 282 #define AFC_CFG_FCMULT_ 0x00000008 283 #define AFC_CFG_FCBRD_ 0x00000004 284 #define AFC_CFG_FCADD_ 0x00000002 285 #define AFC_CFG_FCANY_ 0x00000001 286 287 #define E2P_CMD 0xB0 288 #define E2P_CMD_EPC_BUSY_ 0x80000000 289 #define E2P_CMD_EPC_CMD_ 0x70000000 290 #define E2P_CMD_EPC_CMD_READ_ 0x00000000 291 #define E2P_CMD_EPC_CMD_EWDS_ 0x10000000 292 #define E2P_CMD_EPC_CMD_EWEN_ 0x20000000 293 #define E2P_CMD_EPC_CMD_WRITE_ 0x30000000 294 #define E2P_CMD_EPC_CMD_WRAL_ 0x40000000 295 #define E2P_CMD_EPC_CMD_ERASE_ 0x50000000 296 #define E2P_CMD_EPC_CMD_ERAL_ 0x60000000 297 #define E2P_CMD_EPC_CMD_RELOAD_ 0x70000000 298 #define E2P_CMD_EPC_TIMEOUT_ 0x00000200 299 #define E2P_CMD_MAC_ADDR_LOADED_ 0x00000100 300 #define E2P_CMD_EPC_ADDR_ 0x000000FF 301 302 #define E2P_DATA 0xB4 303 #define E2P_DATA_EEPROM_DATA_ 0x000000FF 304 #define LAN_REGISTER_EXTENT 0x00000100 305 306 /* 307 * MAC Control and Status Register (Indirect Address) 308 * Offset (through the MAC_CSR CMD and DATA port) 309 */ 310 #define MAC_CR 0x01 311 #define MAC_CR_RXALL_ 0x80000000 312 #define MAC_CR_HBDIS_ 0x10000000 313 #define MAC_CR_RCVOWN_ 0x00800000 314 #define MAC_CR_LOOPBK_ 0x00200000 315 #define MAC_CR_FDPX_ 0x00100000 316 #define MAC_CR_MCPAS_ 0x00080000 317 #define MAC_CR_PRMS_ 0x00040000 318 #define MAC_CR_INVFILT_ 0x00020000 319 #define MAC_CR_PASSBAD_ 0x00010000 320 #define MAC_CR_HFILT_ 0x00008000 321 #define MAC_CR_HPFILT_ 0x00002000 322 #define MAC_CR_LCOLL_ 0x00001000 323 #define MAC_CR_BCAST_ 0x00000800 324 #define MAC_CR_DISRTY_ 0x00000400 325 #define MAC_CR_PADSTR_ 0x00000100 326 #define MAC_CR_BOLMT_MASK_ 0x000000C0 327 #define MAC_CR_DFCHK_ 0x00000020 328 #define MAC_CR_TXEN_ 0x00000008 329 #define MAC_CR_RXEN_ 0x00000004 330 331 #define ADDRH 0x02 332 333 #define ADDRL 0x03 334 335 #define HASHH 0x04 336 337 #define HASHL 0x05 338 339 #define MII_ACC 0x06 340 #define MII_ACC_PHY_ADDR_ 0x0000F800 341 #define MII_ACC_MIIRINDA_ 0x000007C0 342 #define MII_ACC_MII_WRITE_ 0x00000002 343 #define MII_ACC_MII_BUSY_ 0x00000001 344 345 #define MII_DATA 0x07 346 347 #define FLOW 0x08 348 #define FLOW_FCPT_ 0xFFFF0000 349 #define FLOW_FCPASS_ 0x00000004 350 #define FLOW_FCEN_ 0x00000002 351 #define FLOW_FCBSY_ 0x00000001 352 353 #define VLAN1 0x09 354 355 #define VLAN2 0x0A 356 357 #define WUFF 0x0B 358 359 #define WUCSR 0x0C 360 #define WUCSR_GUE_ 0x00000200 361 #define WUCSR_WUFR_ 0x00000040 362 #define WUCSR_MPR_ 0x00000020 363 #define WUCSR_WAKE_EN_ 0x00000004 364 #define WUCSR_MPEN_ 0x00000002 365 366 /* 367 * Phy definitions (vendor-specific) 368 */ 369 #define LAN9118_PHY_ID 0x00C0001C 370 371 #define MII_INTSTS 0x1D 372 373 #define MII_INTMSK 0x1E 374 #define PHY_INTMSK_AN_RCV_ (1 << 1) 375 #define PHY_INTMSK_PDFAULT_ (1 << 2) 376 #define PHY_INTMSK_AN_ACK_ (1 << 3) 377 #define PHY_INTMSK_LNKDOWN_ (1 << 4) 378 #define PHY_INTMSK_RFAULT_ (1 << 5) 379 #define PHY_INTMSK_AN_COMP_ (1 << 6) 380 #define PHY_INTMSK_ENERGYON_ (1 << 7) 381 #define PHY_INTMSK_DEFAULT_ (PHY_INTMSK_ENERGYON_ | \ 382 PHY_INTMSK_AN_COMP_ | \ 383 PHY_INTMSK_RFAULT_ | \ 384 PHY_INTMSK_LNKDOWN_) 385 386 #define ADVERTISE_PAUSE_ALL (ADVERTISE_PAUSE_CAP | \ 387 ADVERTISE_PAUSE_ASYM) 388 389 #define LPA_PAUSE_ALL (LPA_PAUSE_CAP | \ 390 LPA_PAUSE_ASYM) 391 392 /* 393 * Provide hooks to let the arch add to the initialisation procedure 394 * and to override the source of the MAC address. 395 */ 396 #define SMSC_INITIALIZE() do {} while (0) 397 #define smsc_get_mac(dev) smsc911x_read_mac_address((dev)) 398 399 #ifdef CONFIG_SMSC911X_ARCH_HOOKS 400 #include <asm/smsc911x.h> 401 #endif 402 403 #include <linux/smscphy.h> 404 405 #endif /* __SMSC911X_H__ */ 406