1 /*------------------------------------------------------------------------ 2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. 3 . 4 . Copyright (C) 1996 by Erik Stahlman 5 . Copyright (C) 2001 Standard Microsystems Corporation 6 . Developed by Simple Network Magic Corporation 7 . Copyright (C) 2003 Monta Vista Software, Inc. 8 . Unified SMC91x driver by Nicolas Pitre 9 . 10 . This program is free software; you can redistribute it and/or modify 11 . it under the terms of the GNU General Public License as published by 12 . the Free Software Foundation; either version 2 of the License, or 13 . (at your option) any later version. 14 . 15 . This program is distributed in the hope that it will be useful, 16 . but WITHOUT ANY WARRANTY; without even the implied warranty of 17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 . GNU General Public License for more details. 19 . 20 . You should have received a copy of the GNU General Public License 21 . along with this program; if not, see <http://www.gnu.org/licenses/>. 22 . 23 . Information contained in this file was obtained from the LAN91C111 24 . manual from SMC. To get a copy, if you really want one, you can find 25 . information under www.smsc.com. 26 . 27 . Authors 28 . Erik Stahlman <erik@vt.edu> 29 . Daris A Nevil <dnevil@snmc.com> 30 . Nicolas Pitre <nico@fluxnic.net> 31 . 32 ---------------------------------------------------------------------------*/ 33 #ifndef _SMC91X_H_ 34 #define _SMC91X_H_ 35 36 #include <linux/smc91x.h> 37 38 /* 39 * Define your architecture specific bus configuration parameters here. 40 */ 41 42 #if defined(CONFIG_ARCH_LUBBOCK) ||\ 43 defined(CONFIG_MACH_MAINSTONE) ||\ 44 defined(CONFIG_MACH_ZYLONITE) ||\ 45 defined(CONFIG_MACH_LITTLETON) ||\ 46 defined(CONFIG_MACH_ZYLONITE2) ||\ 47 defined(CONFIG_ARCH_VIPER) ||\ 48 defined(CONFIG_MACH_STARGATE2) ||\ 49 defined(CONFIG_ARCH_VERSATILE) 50 51 #include <asm/mach-types.h> 52 53 /* Now the bus width is specified in the platform data 54 * pretend here to support all I/O access types 55 */ 56 #define SMC_CAN_USE_8BIT 1 57 #define SMC_CAN_USE_16BIT 1 58 #define SMC_CAN_USE_32BIT 1 59 #define SMC_NOWAIT 1 60 61 #define SMC_IO_SHIFT (lp->io_shift) 62 63 #define SMC_inb(a, r) readb((a) + (r)) 64 #define SMC_inw(a, r) readw((a) + (r)) 65 #define SMC_inl(a, r) readl((a) + (r)) 66 #define SMC_outb(v, a, r) writeb(v, (a) + (r)) 67 #define SMC_outl(v, a, r) writel(v, (a) + (r)) 68 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 69 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 70 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) 71 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) 72 #define SMC_IRQ_FLAGS (-1) /* from resource */ 73 74 /* We actually can't write halfwords properly if not word aligned */ 75 static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg) 76 { 77 if ((machine_is_mainstone() || machine_is_stargate2()) && reg & 2) { 78 unsigned int v = val << 16; 79 v |= readl(ioaddr + (reg & ~2)) & 0xffff; 80 writel(v, ioaddr + (reg & ~2)); 81 } else { 82 writew(val, ioaddr + reg); 83 } 84 } 85 86 #elif defined(CONFIG_SA1100_PLEB) 87 /* We can only do 16-bit reads and writes in the static memory space. */ 88 #define SMC_CAN_USE_8BIT 1 89 #define SMC_CAN_USE_16BIT 1 90 #define SMC_CAN_USE_32BIT 0 91 #define SMC_IO_SHIFT 0 92 #define SMC_NOWAIT 1 93 94 #define SMC_inb(a, r) readb((a) + (r)) 95 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) 96 #define SMC_inw(a, r) readw((a) + (r)) 97 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 98 #define SMC_outb(v, a, r) writeb(v, (a) + (r)) 99 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) 100 #define SMC_outw(v, a, r) writew(v, (a) + (r)) 101 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 102 103 #define SMC_IRQ_FLAGS (-1) 104 105 #elif defined(CONFIG_SA1100_ASSABET) 106 107 #include <mach/neponset.h> 108 109 /* We can only do 8-bit reads and writes in the static memory space. */ 110 #define SMC_CAN_USE_8BIT 1 111 #define SMC_CAN_USE_16BIT 0 112 #define SMC_CAN_USE_32BIT 0 113 #define SMC_NOWAIT 1 114 115 /* The first two address lines aren't connected... */ 116 #define SMC_IO_SHIFT 2 117 118 #define SMC_inb(a, r) readb((a) + (r)) 119 #define SMC_outb(v, a, r) writeb(v, (a) + (r)) 120 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) 121 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) 122 #define SMC_IRQ_FLAGS (-1) /* from resource */ 123 124 #elif defined(CONFIG_MACH_LOGICPD_PXA270) || \ 125 defined(CONFIG_MACH_NOMADIK_8815NHK) 126 127 #define SMC_CAN_USE_8BIT 0 128 #define SMC_CAN_USE_16BIT 1 129 #define SMC_CAN_USE_32BIT 0 130 #define SMC_IO_SHIFT 0 131 #define SMC_NOWAIT 1 132 133 #define SMC_inw(a, r) readw((a) + (r)) 134 #define SMC_outw(v, a, r) writew(v, (a) + (r)) 135 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 136 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 137 138 #elif defined(CONFIG_ARCH_INNOKOM) || \ 139 defined(CONFIG_ARCH_PXA_IDP) || \ 140 defined(CONFIG_ARCH_RAMSES) || \ 141 defined(CONFIG_ARCH_PCM027) 142 143 #define SMC_CAN_USE_8BIT 1 144 #define SMC_CAN_USE_16BIT 1 145 #define SMC_CAN_USE_32BIT 1 146 #define SMC_IO_SHIFT 0 147 #define SMC_NOWAIT 1 148 #define SMC_USE_PXA_DMA 1 149 150 #define SMC_inb(a, r) readb((a) + (r)) 151 #define SMC_inw(a, r) readw((a) + (r)) 152 #define SMC_inl(a, r) readl((a) + (r)) 153 #define SMC_outb(v, a, r) writeb(v, (a) + (r)) 154 #define SMC_outl(v, a, r) writel(v, (a) + (r)) 155 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) 156 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) 157 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 158 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 159 #define SMC_IRQ_FLAGS (-1) /* from resource */ 160 161 /* We actually can't write halfwords properly if not word aligned */ 162 static inline void 163 SMC_outw(u16 val, void __iomem *ioaddr, int reg) 164 { 165 if (reg & 2) { 166 unsigned int v = val << 16; 167 v |= readl(ioaddr + (reg & ~2)) & 0xffff; 168 writel(v, ioaddr + (reg & ~2)); 169 } else { 170 writew(val, ioaddr + reg); 171 } 172 } 173 174 #elif defined(CONFIG_SH_SH4202_MICRODEV) 175 176 #define SMC_CAN_USE_8BIT 0 177 #define SMC_CAN_USE_16BIT 1 178 #define SMC_CAN_USE_32BIT 0 179 180 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) 181 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) 182 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000) 183 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) 184 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000) 185 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000) 186 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l) 187 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l) 188 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) 189 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) 190 191 #define SMC_IRQ_FLAGS (0) 192 193 #elif defined(CONFIG_M32R) 194 195 #define SMC_CAN_USE_8BIT 0 196 #define SMC_CAN_USE_16BIT 1 197 #define SMC_CAN_USE_32BIT 0 198 199 #define SMC_inb(a, r) inb(((u32)a) + (r)) 200 #define SMC_inw(a, r) inw(((u32)a) + (r)) 201 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r)) 202 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r)) 203 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l) 204 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l) 205 206 #define SMC_IRQ_FLAGS (0) 207 208 #define RPC_LSA_DEFAULT RPC_LED_TX_RX 209 #define RPC_LSB_DEFAULT RPC_LED_100_10 210 211 #elif defined(CONFIG_MN10300) 212 213 /* 214 * MN10300/AM33 configuration 215 */ 216 217 #include <unit/smc91111.h> 218 219 #elif defined(CONFIG_ATARI) 220 221 #define SMC_CAN_USE_8BIT 1 222 #define SMC_CAN_USE_16BIT 1 223 #define SMC_CAN_USE_32BIT 1 224 #define SMC_NOWAIT 1 225 226 #define SMC_inb(a, r) readb((a) + (r)) 227 #define SMC_inw(a, r) readw((a) + (r)) 228 #define SMC_inl(a, r) readl((a) + (r)) 229 #define SMC_outb(v, a, r) writeb(v, (a) + (r)) 230 #define SMC_outw(v, a, r) writew(v, (a) + (r)) 231 #define SMC_outl(v, a, r) writel(v, (a) + (r)) 232 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 233 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 234 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) 235 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) 236 237 #define RPC_LSA_DEFAULT RPC_LED_100_10 238 #define RPC_LSB_DEFAULT RPC_LED_TX_RX 239 240 #elif defined(CONFIG_ARCH_MSM) 241 242 #define SMC_CAN_USE_8BIT 0 243 #define SMC_CAN_USE_16BIT 1 244 #define SMC_CAN_USE_32BIT 0 245 #define SMC_NOWAIT 1 246 247 #define SMC_inw(a, r) readw((a) + (r)) 248 #define SMC_outw(v, a, r) writew(v, (a) + (r)) 249 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 250 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 251 252 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH 253 254 #elif defined(CONFIG_COLDFIRE) 255 256 #define SMC_CAN_USE_8BIT 0 257 #define SMC_CAN_USE_16BIT 1 258 #define SMC_CAN_USE_32BIT 0 259 #define SMC_NOWAIT 1 260 261 static inline void mcf_insw(void *a, unsigned char *p, int l) 262 { 263 u16 *wp = (u16 *) p; 264 while (l-- > 0) 265 *wp++ = readw(a); 266 } 267 268 static inline void mcf_outsw(void *a, unsigned char *p, int l) 269 { 270 u16 *wp = (u16 *) p; 271 while (l-- > 0) 272 writew(*wp++, a); 273 } 274 275 #define SMC_inw(a, r) _swapw(readw((a) + (r))) 276 #define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r)) 277 #define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l) 278 #define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l) 279 280 #define SMC_IRQ_FLAGS 0 281 282 #else 283 284 /* 285 * Default configuration 286 */ 287 288 #define SMC_CAN_USE_8BIT 1 289 #define SMC_CAN_USE_16BIT 1 290 #define SMC_CAN_USE_32BIT 1 291 #define SMC_NOWAIT 1 292 293 #define SMC_IO_SHIFT (lp->io_shift) 294 295 #define SMC_inb(a, r) ioread8((a) + (r)) 296 #define SMC_inw(a, r) ioread16((a) + (r)) 297 #define SMC_inl(a, r) ioread32((a) + (r)) 298 #define SMC_outb(v, a, r) iowrite8(v, (a) + (r)) 299 #define SMC_outw(v, a, r) iowrite16(v, (a) + (r)) 300 #define SMC_outl(v, a, r) iowrite32(v, (a) + (r)) 301 #define SMC_insw(a, r, p, l) ioread16_rep((a) + (r), p, l) 302 #define SMC_outsw(a, r, p, l) iowrite16_rep((a) + (r), p, l) 303 #define SMC_insl(a, r, p, l) ioread32_rep((a) + (r), p, l) 304 #define SMC_outsl(a, r, p, l) iowrite32_rep((a) + (r), p, l) 305 306 #define RPC_LSA_DEFAULT RPC_LED_100_10 307 #define RPC_LSB_DEFAULT RPC_LED_TX_RX 308 309 #endif 310 311 312 /* store this information for the driver.. */ 313 struct smc_local { 314 /* 315 * If I have to wait until memory is available to send a 316 * packet, I will store the skbuff here, until I get the 317 * desired memory. Then, I'll send it out and free it. 318 */ 319 struct sk_buff *pending_tx_skb; 320 struct tasklet_struct tx_task; 321 322 struct gpio_desc *power_gpio; 323 struct gpio_desc *reset_gpio; 324 325 /* version/revision of the SMC91x chip */ 326 int version; 327 328 /* Contains the current active transmission mode */ 329 int tcr_cur_mode; 330 331 /* Contains the current active receive mode */ 332 int rcr_cur_mode; 333 334 /* Contains the current active receive/phy mode */ 335 int rpc_cur_mode; 336 int ctl_rfduplx; 337 int ctl_rspeed; 338 339 u32 msg_enable; 340 u32 phy_type; 341 struct mii_if_info mii; 342 343 /* work queue */ 344 struct work_struct phy_configure; 345 struct net_device *dev; 346 int work_pending; 347 348 spinlock_t lock; 349 350 #ifdef CONFIG_ARCH_PXA 351 /* DMA needs the physical address of the chip */ 352 u_long physaddr; 353 struct device *device; 354 #endif 355 void __iomem *base; 356 void __iomem *datacs; 357 358 /* the low address lines on some platforms aren't connected... */ 359 int io_shift; 360 361 struct smc91x_platdata cfg; 362 }; 363 364 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT) 365 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT) 366 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT) 367 368 #ifdef CONFIG_ARCH_PXA 369 /* 370 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is 371 * always happening in irq context so no need to worry about races. TX is 372 * different and probably not worth it for that reason, and not as critical 373 * as RX which can overrun memory and lose packets. 374 */ 375 #include <linux/dma-mapping.h> 376 #include <mach/dma.h> 377 378 #ifdef SMC_insl 379 #undef SMC_insl 380 #define SMC_insl(a, r, p, l) \ 381 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l) 382 static inline void 383 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, 384 u_char *buf, int len) 385 { 386 u_long physaddr = lp->physaddr; 387 dma_addr_t dmabuf; 388 389 /* fallback if no DMA available */ 390 if (dma == (unsigned char)-1) { 391 readsl(ioaddr + reg, buf, len); 392 return; 393 } 394 395 /* 64 bit alignment is required for memory to memory DMA */ 396 if ((long)buf & 4) { 397 *((u32 *)buf) = SMC_inl(ioaddr, reg); 398 buf += 4; 399 len--; 400 } 401 402 len *= 4; 403 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); 404 DCSR(dma) = DCSR_NODESC; 405 DTADR(dma) = dmabuf; 406 DSADR(dma) = physaddr + reg; 407 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | 408 DCMD_WIDTH4 | (DCMD_LENGTH & len)); 409 DCSR(dma) = DCSR_NODESC | DCSR_RUN; 410 while (!(DCSR(dma) & DCSR_STOPSTATE)) 411 cpu_relax(); 412 DCSR(dma) = 0; 413 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); 414 } 415 #endif 416 417 #ifdef SMC_insw 418 #undef SMC_insw 419 #define SMC_insw(a, r, p, l) \ 420 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l) 421 static inline void 422 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, 423 u_char *buf, int len) 424 { 425 u_long physaddr = lp->physaddr; 426 dma_addr_t dmabuf; 427 428 /* fallback if no DMA available */ 429 if (dma == (unsigned char)-1) { 430 readsw(ioaddr + reg, buf, len); 431 return; 432 } 433 434 /* 64 bit alignment is required for memory to memory DMA */ 435 while ((long)buf & 6) { 436 *((u16 *)buf) = SMC_inw(ioaddr, reg); 437 buf += 2; 438 len--; 439 } 440 441 len *= 2; 442 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); 443 DCSR(dma) = DCSR_NODESC; 444 DTADR(dma) = dmabuf; 445 DSADR(dma) = physaddr + reg; 446 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | 447 DCMD_WIDTH2 | (DCMD_LENGTH & len)); 448 DCSR(dma) = DCSR_NODESC | DCSR_RUN; 449 while (!(DCSR(dma) & DCSR_STOPSTATE)) 450 cpu_relax(); 451 DCSR(dma) = 0; 452 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); 453 } 454 #endif 455 456 static void 457 smc_pxa_dma_irq(int dma, void *dummy) 458 { 459 DCSR(dma) = 0; 460 } 461 #endif /* CONFIG_ARCH_PXA */ 462 463 464 /* 465 * Everything a particular hardware setup needs should have been defined 466 * at this point. Add stubs for the undefined cases, mainly to avoid 467 * compilation warnings since they'll be optimized away, or to prevent buggy 468 * use of them. 469 */ 470 471 #if ! SMC_CAN_USE_32BIT 472 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; }) 473 #define SMC_outl(x, ioaddr, reg) BUG() 474 #define SMC_insl(a, r, p, l) BUG() 475 #define SMC_outsl(a, r, p, l) BUG() 476 #endif 477 478 #if !defined(SMC_insl) || !defined(SMC_outsl) 479 #define SMC_insl(a, r, p, l) BUG() 480 #define SMC_outsl(a, r, p, l) BUG() 481 #endif 482 483 #if ! SMC_CAN_USE_16BIT 484 485 /* 486 * Any 16-bit access is performed with two 8-bit accesses if the hardware 487 * can't do it directly. Most registers are 16-bit so those are mandatory. 488 */ 489 #define SMC_outw(x, ioaddr, reg) \ 490 do { \ 491 unsigned int __val16 = (x); \ 492 SMC_outb( __val16, ioaddr, reg ); \ 493 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\ 494 } while (0) 495 #define SMC_inw(ioaddr, reg) \ 496 ({ \ 497 unsigned int __val16; \ 498 __val16 = SMC_inb( ioaddr, reg ); \ 499 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \ 500 __val16; \ 501 }) 502 503 #define SMC_insw(a, r, p, l) BUG() 504 #define SMC_outsw(a, r, p, l) BUG() 505 506 #endif 507 508 #if !defined(SMC_insw) || !defined(SMC_outsw) 509 #define SMC_insw(a, r, p, l) BUG() 510 #define SMC_outsw(a, r, p, l) BUG() 511 #endif 512 513 #if ! SMC_CAN_USE_8BIT 514 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; }) 515 #define SMC_outb(x, ioaddr, reg) BUG() 516 #define SMC_insb(a, r, p, l) BUG() 517 #define SMC_outsb(a, r, p, l) BUG() 518 #endif 519 520 #if !defined(SMC_insb) || !defined(SMC_outsb) 521 #define SMC_insb(a, r, p, l) BUG() 522 #define SMC_outsb(a, r, p, l) BUG() 523 #endif 524 525 #ifndef SMC_CAN_USE_DATACS 526 #define SMC_CAN_USE_DATACS 0 527 #endif 528 529 #ifndef SMC_IO_SHIFT 530 #define SMC_IO_SHIFT 0 531 #endif 532 533 #ifndef SMC_IRQ_FLAGS 534 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING 535 #endif 536 537 #ifndef SMC_INTERRUPT_PREAMBLE 538 #define SMC_INTERRUPT_PREAMBLE 539 #endif 540 541 542 /* Because of bank switching, the LAN91x uses only 16 I/O ports */ 543 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) 544 #define SMC_DATA_EXTENT (4) 545 546 /* 547 . Bank Select Register: 548 . 549 . yyyy yyyy 0000 00xx 550 . xx = bank number 551 . yyyy yyyy = 0x33, for identification purposes. 552 */ 553 #define BANK_SELECT (14 << SMC_IO_SHIFT) 554 555 556 // Transmit Control Register 557 /* BANK 0 */ 558 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0) 559 #define TCR_ENABLE 0x0001 // When 1 we can transmit 560 #define TCR_LOOP 0x0002 // Controls output pin LBK 561 #define TCR_FORCOL 0x0004 // When 1 will force a collision 562 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0 563 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames 564 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier 565 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation 566 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error 567 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback 568 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode 569 570 #define TCR_CLEAR 0 /* do NOTHING */ 571 /* the default settings for the TCR register : */ 572 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN) 573 574 575 // EPH Status Register 576 /* BANK 0 */ 577 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0) 578 #define ES_TX_SUC 0x0001 // Last TX was successful 579 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx 580 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx 581 #define ES_LTX_MULT 0x0008 // Last tx was a multicast 582 #define ES_16COL 0x0010 // 16 Collisions Reached 583 #define ES_SQET 0x0020 // Signal Quality Error Test 584 #define ES_LTXBRD 0x0040 // Last tx was a broadcast 585 #define ES_TXDEFR 0x0080 // Transmit Deferred 586 #define ES_LATCOL 0x0200 // Late collision detected on last tx 587 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense 588 #define ES_EXC_DEF 0x0800 // Excessive Deferral 589 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication 590 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin 591 #define ES_TXUNRN 0x8000 // Tx Underrun 592 593 594 // Receive Control Register 595 /* BANK 0 */ 596 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0) 597 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted 598 #define RCR_PRMS 0x0002 // Enable promiscuous mode 599 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames 600 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets 601 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets 602 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision 603 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier 604 #define RCR_SOFTRST 0x8000 // resets the chip 605 606 /* the normal settings for the RCR register : */ 607 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) 608 #define RCR_CLEAR 0x0 // set it to a base state 609 610 611 // Counter Register 612 /* BANK 0 */ 613 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0) 614 615 616 // Memory Information Register 617 /* BANK 0 */ 618 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0) 619 620 621 // Receive/Phy Control Register 622 /* BANK 0 */ 623 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0) 624 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. 625 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode 626 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode 627 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb 628 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb 629 630 #ifndef RPC_LSA_DEFAULT 631 #define RPC_LSA_DEFAULT RPC_LED_100 632 #endif 633 #ifndef RPC_LSB_DEFAULT 634 #define RPC_LSB_DEFAULT RPC_LED_FD 635 #endif 636 637 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX) 638 639 640 /* Bank 0 0x0C is reserved */ 641 642 // Bank Select Register 643 /* All Banks */ 644 #define BSR_REG 0x000E 645 646 647 // Configuration Reg 648 /* BANK 1 */ 649 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1) 650 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy 651 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL 652 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus 653 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode. 654 655 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low 656 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) 657 658 659 // Base Address Register 660 /* BANK 1 */ 661 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1) 662 663 664 // Individual Address Registers 665 /* BANK 1 */ 666 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1) 667 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1) 668 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1) 669 670 671 // General Purpose Register 672 /* BANK 1 */ 673 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1) 674 675 676 // Control Register 677 /* BANK 1 */ 678 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1) 679 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received 680 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically 681 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt 682 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt 683 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt 684 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store 685 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers 686 #define CTL_STORE 0x0001 // When set stores registers into EEPROM 687 688 689 // MMU Command Register 690 /* BANK 2 */ 691 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2) 692 #define MC_BUSY 1 // When 1 the last release has not completed 693 #define MC_NOP (0<<5) // No Op 694 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets 695 #define MC_RESET (2<<5) // Reset MMU to initial state 696 #define MC_REMOVE (3<<5) // Remove the current rx packet 697 #define MC_RELEASE (4<<5) // Remove and release the current rx packet 698 #define MC_FREEPKT (5<<5) // Release packet in PNR register 699 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit 700 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs 701 702 703 // Packet Number Register 704 /* BANK 2 */ 705 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2) 706 707 708 // Allocation Result Register 709 /* BANK 2 */ 710 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2) 711 #define AR_FAILED 0x80 // Alocation Failed 712 713 714 // TX FIFO Ports Register 715 /* BANK 2 */ 716 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2) 717 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty 718 719 // RX FIFO Ports Register 720 /* BANK 2 */ 721 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2) 722 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty 723 724 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2) 725 726 // Pointer Register 727 /* BANK 2 */ 728 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2) 729 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area 730 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access 731 #define PTR_READ 0x2000 // When 1 the operation is a read 732 733 734 // Data Register 735 /* BANK 2 */ 736 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2) 737 738 739 // Interrupt Status/Acknowledge Register 740 /* BANK 2 */ 741 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2) 742 743 744 // Interrupt Mask Register 745 /* BANK 2 */ 746 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2) 747 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt 748 #define IM_ERCV_INT 0x40 // Early Receive Interrupt 749 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section 750 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns 751 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed 752 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty 753 #define IM_TX_INT 0x02 // Transmit Interrupt 754 #define IM_RCV_INT 0x01 // Receive Interrupt 755 756 757 // Multicast Table Registers 758 /* BANK 3 */ 759 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3) 760 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3) 761 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3) 762 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3) 763 764 765 // Management Interface Register (MII) 766 /* BANK 3 */ 767 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3) 768 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup 769 #define MII_MDOE 0x0008 // MII Output Enable 770 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK 771 #define MII_MDI 0x0002 // MII Input, pin MDI 772 #define MII_MDO 0x0001 // MII Output, pin MDO 773 774 775 // Revision Register 776 /* BANK 3 */ 777 /* ( hi: chip id low: rev # ) */ 778 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3) 779 780 781 // Early RCV Register 782 /* BANK 3 */ 783 /* this is NOT on SMC9192 */ 784 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3) 785 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received 786 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask 787 788 789 // External Register 790 /* BANK 7 */ 791 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7) 792 793 794 #define CHIP_9192 3 795 #define CHIP_9194 4 796 #define CHIP_9195 5 797 #define CHIP_9196 6 798 #define CHIP_91100 7 799 #define CHIP_91100FD 8 800 #define CHIP_91111FD 9 801 802 static const char * chip_ids[ 16 ] = { 803 NULL, NULL, NULL, 804 /* 3 */ "SMC91C90/91C92", 805 /* 4 */ "SMC91C94", 806 /* 5 */ "SMC91C95", 807 /* 6 */ "SMC91C96", 808 /* 7 */ "SMC91C100", 809 /* 8 */ "SMC91C100FD", 810 /* 9 */ "SMC91C11xFD", 811 NULL, NULL, NULL, 812 NULL, NULL, NULL}; 813 814 815 /* 816 . Receive status bits 817 */ 818 #define RS_ALGNERR 0x8000 819 #define RS_BRODCAST 0x4000 820 #define RS_BADCRC 0x2000 821 #define RS_ODDFRAME 0x1000 822 #define RS_TOOLONG 0x0800 823 #define RS_TOOSHORT 0x0400 824 #define RS_MULTICAST 0x0001 825 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 826 827 828 /* 829 * PHY IDs 830 * LAN83C183 == LAN91C111 Internal PHY 831 */ 832 #define PHY_LAN83C183 0x0016f840 833 #define PHY_LAN83C180 0x02821c50 834 835 /* 836 * PHY Register Addresses (LAN91C111 Internal PHY) 837 * 838 * Generic PHY registers can be found in <linux/mii.h> 839 * 840 * These phy registers are specific to our on-board phy. 841 */ 842 843 // PHY Configuration Register 1 844 #define PHY_CFG1_REG 0x10 845 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled 846 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled 847 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down 848 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler 849 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable 850 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled 851 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) 852 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db 853 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust 854 #define PHY_CFG1_TLVL_MASK 0x003C 855 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time 856 857 858 // PHY Configuration Register 2 859 #define PHY_CFG2_REG 0x11 860 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled 861 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled 862 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) 863 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo 864 865 // PHY Status Output (and Interrupt status) Register 866 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status) 867 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read 868 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected 869 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync 870 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx 871 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx 872 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx 873 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected 874 #define PHY_INT_JAB 0x0100 // 1=Jabber detected 875 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode 876 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex 877 878 // PHY Interrupt/Status Mask Register 879 #define PHY_MASK_REG 0x13 // Interrupt Mask 880 // Uses the same bit definitions as PHY_INT_REG 881 882 883 /* 884 * SMC91C96 ethernet config and status registers. 885 * These are in the "attribute" space. 886 */ 887 #define ECOR 0x8000 888 #define ECOR_RESET 0x80 889 #define ECOR_LEVEL_IRQ 0x40 890 #define ECOR_WR_ATTRIB 0x04 891 #define ECOR_ENABLE 0x01 892 893 #define ECSR 0x8002 894 #define ECSR_IOIS8 0x20 895 #define ECSR_PWRDWN 0x04 896 #define ECSR_INT 0x02 897 898 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT) 899 900 901 /* 902 * Macros to abstract register access according to the data bus 903 * capabilities. Please use those and not the in/out primitives. 904 * Note: the following macros do *not* select the bank -- this must 905 * be done separately as needed in the main code. The SMC_REG() macro 906 * only uses the bank argument for debugging purposes (when enabled). 907 * 908 * Note: despite inline functions being safer, everything leading to this 909 * should preferably be macros to let BUG() display the line number in 910 * the core source code since we're interested in the top call site 911 * not in any inline function location. 912 */ 913 914 #if SMC_DEBUG > 0 915 #define SMC_REG(lp, reg, bank) \ 916 ({ \ 917 int __b = SMC_CURRENT_BANK(lp); \ 918 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ 919 pr_err("%s: bank reg screwed (0x%04x)\n", \ 920 CARDNAME, __b); \ 921 BUG(); \ 922 } \ 923 reg<<SMC_IO_SHIFT; \ 924 }) 925 #else 926 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT) 927 #endif 928 929 /* 930 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not 931 * aligned to a 32 bit boundary. I tell you that does exist! 932 * Fortunately the affected register accesses can be easily worked around 933 * since we can write zeroes to the preceding 16 bits without adverse 934 * effects and use a 32-bit access. 935 * 936 * Enforce it on any 32-bit capable setup for now. 937 */ 938 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp) 939 940 #define SMC_GET_PN(lp) \ 941 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \ 942 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF)) 943 944 #define SMC_SET_PN(lp, x) \ 945 do { \ 946 if (SMC_MUST_ALIGN_WRITE(lp)) \ 947 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \ 948 else if (SMC_8BIT(lp)) \ 949 SMC_outb(x, ioaddr, PN_REG(lp)); \ 950 else \ 951 SMC_outw(x, ioaddr, PN_REG(lp)); \ 952 } while (0) 953 954 #define SMC_GET_AR(lp) \ 955 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \ 956 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8)) 957 958 #define SMC_GET_TXFIFO(lp) \ 959 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \ 960 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF)) 961 962 #define SMC_GET_RXFIFO(lp) \ 963 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \ 964 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8)) 965 966 #define SMC_GET_INT(lp) \ 967 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \ 968 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF)) 969 970 #define SMC_ACK_INT(lp, x) \ 971 do { \ 972 if (SMC_8BIT(lp)) \ 973 SMC_outb(x, ioaddr, INT_REG(lp)); \ 974 else { \ 975 unsigned long __flags; \ 976 int __mask; \ 977 local_irq_save(__flags); \ 978 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \ 979 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \ 980 local_irq_restore(__flags); \ 981 } \ 982 } while (0) 983 984 #define SMC_GET_INT_MASK(lp) \ 985 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \ 986 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8)) 987 988 #define SMC_SET_INT_MASK(lp, x) \ 989 do { \ 990 if (SMC_8BIT(lp)) \ 991 SMC_outb(x, ioaddr, IM_REG(lp)); \ 992 else \ 993 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \ 994 } while (0) 995 996 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT) 997 998 #define SMC_SELECT_BANK(lp, x) \ 999 do { \ 1000 if (SMC_MUST_ALIGN_WRITE(lp)) \ 1001 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \ 1002 else \ 1003 SMC_outw(x, ioaddr, BANK_SELECT); \ 1004 } while (0) 1005 1006 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp)) 1007 1008 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp)) 1009 1010 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp)) 1011 1012 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp)) 1013 1014 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp)) 1015 1016 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp)) 1017 1018 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp)) 1019 1020 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp)) 1021 1022 #define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp)) 1023 1024 #define SMC_SET_GP(lp, x) \ 1025 do { \ 1026 if (SMC_MUST_ALIGN_WRITE(lp)) \ 1027 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \ 1028 else \ 1029 SMC_outw(x, ioaddr, GP_REG(lp)); \ 1030 } while (0) 1031 1032 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp)) 1033 1034 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp)) 1035 1036 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp)) 1037 1038 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp)) 1039 1040 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp)) 1041 1042 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp)) 1043 1044 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp)) 1045 1046 #define SMC_SET_PTR(lp, x) \ 1047 do { \ 1048 if (SMC_MUST_ALIGN_WRITE(lp)) \ 1049 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \ 1050 else \ 1051 SMC_outw(x, ioaddr, PTR_REG(lp)); \ 1052 } while (0) 1053 1054 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp)) 1055 1056 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp)) 1057 1058 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp)) 1059 1060 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp)) 1061 1062 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp)) 1063 1064 #define SMC_SET_RPC(lp, x) \ 1065 do { \ 1066 if (SMC_MUST_ALIGN_WRITE(lp)) \ 1067 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \ 1068 else \ 1069 SMC_outw(x, ioaddr, RPC_REG(lp)); \ 1070 } while (0) 1071 1072 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp)) 1073 1074 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp)) 1075 1076 #ifndef SMC_GET_MAC_ADDR 1077 #define SMC_GET_MAC_ADDR(lp, addr) \ 1078 do { \ 1079 unsigned int __v; \ 1080 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \ 1081 addr[0] = __v; addr[1] = __v >> 8; \ 1082 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \ 1083 addr[2] = __v; addr[3] = __v >> 8; \ 1084 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \ 1085 addr[4] = __v; addr[5] = __v >> 8; \ 1086 } while (0) 1087 #endif 1088 1089 #define SMC_SET_MAC_ADDR(lp, addr) \ 1090 do { \ 1091 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \ 1092 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \ 1093 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \ 1094 } while (0) 1095 1096 #define SMC_SET_MCAST(lp, x) \ 1097 do { \ 1098 const unsigned char *mt = (x); \ 1099 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \ 1100 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \ 1101 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \ 1102 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \ 1103 } while (0) 1104 1105 #define SMC_PUT_PKT_HDR(lp, status, length) \ 1106 do { \ 1107 if (SMC_32BIT(lp)) \ 1108 SMC_outl((status) | (length)<<16, ioaddr, \ 1109 DATA_REG(lp)); \ 1110 else { \ 1111 SMC_outw(status, ioaddr, DATA_REG(lp)); \ 1112 SMC_outw(length, ioaddr, DATA_REG(lp)); \ 1113 } \ 1114 } while (0) 1115 1116 #define SMC_GET_PKT_HDR(lp, status, length) \ 1117 do { \ 1118 if (SMC_32BIT(lp)) { \ 1119 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \ 1120 (status) = __val & 0xffff; \ 1121 (length) = __val >> 16; \ 1122 } else { \ 1123 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \ 1124 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \ 1125 } \ 1126 } while (0) 1127 1128 #define SMC_PUSH_DATA(lp, p, l) \ 1129 do { \ 1130 if (SMC_32BIT(lp)) { \ 1131 void *__ptr = (p); \ 1132 int __len = (l); \ 1133 void __iomem *__ioaddr = ioaddr; \ 1134 if (__len >= 2 && (unsigned long)__ptr & 2) { \ 1135 __len -= 2; \ 1136 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \ 1137 __ptr += 2; \ 1138 } \ 1139 if (SMC_CAN_USE_DATACS && lp->datacs) \ 1140 __ioaddr = lp->datacs; \ 1141 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \ 1142 if (__len & 2) { \ 1143 __ptr += (__len & ~3); \ 1144 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \ 1145 } \ 1146 } else if (SMC_16BIT(lp)) \ 1147 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \ 1148 else if (SMC_8BIT(lp)) \ 1149 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \ 1150 } while (0) 1151 1152 #define SMC_PULL_DATA(lp, p, l) \ 1153 do { \ 1154 if (SMC_32BIT(lp)) { \ 1155 void *__ptr = (p); \ 1156 int __len = (l); \ 1157 void __iomem *__ioaddr = ioaddr; \ 1158 if ((unsigned long)__ptr & 2) { \ 1159 /* \ 1160 * We want 32bit alignment here. \ 1161 * Since some buses perform a full \ 1162 * 32bit fetch even for 16bit data \ 1163 * we can't use SMC_inw() here. \ 1164 * Back both source (on-chip) and \ 1165 * destination pointers of 2 bytes. \ 1166 * This is possible since the call to \ 1167 * SMC_GET_PKT_HDR() already advanced \ 1168 * the source pointer of 4 bytes, and \ 1169 * the skb_reserve(skb, 2) advanced \ 1170 * the destination pointer of 2 bytes. \ 1171 */ \ 1172 __ptr -= 2; \ 1173 __len += 2; \ 1174 SMC_SET_PTR(lp, \ 1175 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ 1176 } \ 1177 if (SMC_CAN_USE_DATACS && lp->datacs) \ 1178 __ioaddr = lp->datacs; \ 1179 __len += 2; \ 1180 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \ 1181 } else if (SMC_16BIT(lp)) \ 1182 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \ 1183 else if (SMC_8BIT(lp)) \ 1184 SMC_insb(ioaddr, DATA_REG(lp), p, l); \ 1185 } while (0) 1186 1187 #endif /* _SMC91X_H_ */ 1188