1 /*------------------------------------------------------------------------ 2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. 3 . 4 . Copyright (C) 1996 by Erik Stahlman 5 . Copyright (C) 2001 Standard Microsystems Corporation 6 . Developed by Simple Network Magic Corporation 7 . Copyright (C) 2003 Monta Vista Software, Inc. 8 . Unified SMC91x driver by Nicolas Pitre 9 . 10 . This program is free software; you can redistribute it and/or modify 11 . it under the terms of the GNU General Public License as published by 12 . the Free Software Foundation; either version 2 of the License, or 13 . (at your option) any later version. 14 . 15 . This program is distributed in the hope that it will be useful, 16 . but WITHOUT ANY WARRANTY; without even the implied warranty of 17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 . GNU General Public License for more details. 19 . 20 . You should have received a copy of the GNU General Public License 21 . along with this program; if not, see <http://www.gnu.org/licenses/>. 22 . 23 . Information contained in this file was obtained from the LAN91C111 24 . manual from SMC. To get a copy, if you really want one, you can find 25 . information under www.smsc.com. 26 . 27 . Authors 28 . Erik Stahlman <erik@vt.edu> 29 . Daris A Nevil <dnevil@snmc.com> 30 . Nicolas Pitre <nico@fluxnic.net> 31 . 32 ---------------------------------------------------------------------------*/ 33 #ifndef _SMC91X_H_ 34 #define _SMC91X_H_ 35 36 #include <linux/smc91x.h> 37 38 /* 39 * Define your architecture specific bus configuration parameters here. 40 */ 41 42 #if defined(CONFIG_ARCH_LUBBOCK) ||\ 43 defined(CONFIG_MACH_MAINSTONE) ||\ 44 defined(CONFIG_MACH_ZYLONITE) ||\ 45 defined(CONFIG_MACH_LITTLETON) ||\ 46 defined(CONFIG_MACH_ZYLONITE2) ||\ 47 defined(CONFIG_ARCH_VIPER) ||\ 48 defined(CONFIG_MACH_STARGATE2) ||\ 49 defined(CONFIG_ARCH_VERSATILE) 50 51 #include <asm/mach-types.h> 52 53 /* Now the bus width is specified in the platform data 54 * pretend here to support all I/O access types 55 */ 56 #define SMC_CAN_USE_8BIT 1 57 #define SMC_CAN_USE_16BIT 1 58 #define SMC_CAN_USE_32BIT 1 59 #define SMC_NOWAIT 1 60 61 #define SMC_IO_SHIFT (lp->io_shift) 62 63 #define SMC_inb(a, r) readb((a) + (r)) 64 #define SMC_inw(a, r) readw((a) + (r)) 65 #define SMC_inl(a, r) readl((a) + (r)) 66 #define SMC_outb(v, a, r) writeb(v, (a) + (r)) 67 #define SMC_outl(v, a, r) writel(v, (a) + (r)) 68 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 69 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 70 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) 71 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) 72 #define SMC_IRQ_FLAGS (-1) /* from resource */ 73 74 /* We actually can't write halfwords properly if not word aligned */ 75 static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg) 76 { 77 if ((machine_is_mainstone() || machine_is_stargate2()) && reg & 2) { 78 unsigned int v = val << 16; 79 v |= readl(ioaddr + (reg & ~2)) & 0xffff; 80 writel(v, ioaddr + (reg & ~2)); 81 } else { 82 writew(val, ioaddr + reg); 83 } 84 } 85 86 #elif defined(CONFIG_SA1100_PLEB) 87 /* We can only do 16-bit reads and writes in the static memory space. */ 88 #define SMC_CAN_USE_8BIT 1 89 #define SMC_CAN_USE_16BIT 1 90 #define SMC_CAN_USE_32BIT 0 91 #define SMC_IO_SHIFT 0 92 #define SMC_NOWAIT 1 93 94 #define SMC_inb(a, r) readb((a) + (r)) 95 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) 96 #define SMC_inw(a, r) readw((a) + (r)) 97 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 98 #define SMC_outb(v, a, r) writeb(v, (a) + (r)) 99 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) 100 #define SMC_outw(v, a, r) writew(v, (a) + (r)) 101 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 102 103 #define SMC_IRQ_FLAGS (-1) 104 105 #elif defined(CONFIG_SA1100_ASSABET) 106 107 #include <mach/neponset.h> 108 109 /* We can only do 8-bit reads and writes in the static memory space. */ 110 #define SMC_CAN_USE_8BIT 1 111 #define SMC_CAN_USE_16BIT 0 112 #define SMC_CAN_USE_32BIT 0 113 #define SMC_NOWAIT 1 114 115 /* The first two address lines aren't connected... */ 116 #define SMC_IO_SHIFT 2 117 118 #define SMC_inb(a, r) readb((a) + (r)) 119 #define SMC_outb(v, a, r) writeb(v, (a) + (r)) 120 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) 121 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) 122 #define SMC_IRQ_FLAGS (-1) /* from resource */ 123 124 #elif defined(CONFIG_MACH_LOGICPD_PXA270) || \ 125 defined(CONFIG_MACH_NOMADIK_8815NHK) 126 127 #define SMC_CAN_USE_8BIT 0 128 #define SMC_CAN_USE_16BIT 1 129 #define SMC_CAN_USE_32BIT 0 130 #define SMC_IO_SHIFT 0 131 #define SMC_NOWAIT 1 132 133 #define SMC_inw(a, r) readw((a) + (r)) 134 #define SMC_outw(v, a, r) writew(v, (a) + (r)) 135 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 136 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 137 138 #elif defined(CONFIG_ARCH_INNOKOM) || \ 139 defined(CONFIG_ARCH_PXA_IDP) || \ 140 defined(CONFIG_ARCH_RAMSES) || \ 141 defined(CONFIG_ARCH_PCM027) 142 143 #define SMC_CAN_USE_8BIT 1 144 #define SMC_CAN_USE_16BIT 1 145 #define SMC_CAN_USE_32BIT 1 146 #define SMC_IO_SHIFT 0 147 #define SMC_NOWAIT 1 148 #define SMC_USE_PXA_DMA 1 149 150 #define SMC_inb(a, r) readb((a) + (r)) 151 #define SMC_inw(a, r) readw((a) + (r)) 152 #define SMC_inl(a, r) readl((a) + (r)) 153 #define SMC_outb(v, a, r) writeb(v, (a) + (r)) 154 #define SMC_outl(v, a, r) writel(v, (a) + (r)) 155 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) 156 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) 157 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 158 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 159 #define SMC_IRQ_FLAGS (-1) /* from resource */ 160 161 /* We actually can't write halfwords properly if not word aligned */ 162 static inline void 163 SMC_outw(u16 val, void __iomem *ioaddr, int reg) 164 { 165 if (reg & 2) { 166 unsigned int v = val << 16; 167 v |= readl(ioaddr + (reg & ~2)) & 0xffff; 168 writel(v, ioaddr + (reg & ~2)); 169 } else { 170 writew(val, ioaddr + reg); 171 } 172 } 173 174 #elif defined(CONFIG_SH_SH4202_MICRODEV) 175 176 #define SMC_CAN_USE_8BIT 0 177 #define SMC_CAN_USE_16BIT 1 178 #define SMC_CAN_USE_32BIT 0 179 180 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) 181 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) 182 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000) 183 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) 184 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000) 185 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000) 186 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l) 187 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l) 188 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) 189 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) 190 191 #define SMC_IRQ_FLAGS (0) 192 193 #elif defined(CONFIG_M32R) 194 195 #define SMC_CAN_USE_8BIT 0 196 #define SMC_CAN_USE_16BIT 1 197 #define SMC_CAN_USE_32BIT 0 198 199 #define SMC_inb(a, r) inb(((u32)a) + (r)) 200 #define SMC_inw(a, r) inw(((u32)a) + (r)) 201 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r)) 202 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r)) 203 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l) 204 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l) 205 206 #define SMC_IRQ_FLAGS (0) 207 208 #define RPC_LSA_DEFAULT RPC_LED_TX_RX 209 #define RPC_LSB_DEFAULT RPC_LED_100_10 210 211 #elif defined(CONFIG_MN10300) 212 213 /* 214 * MN10300/AM33 configuration 215 */ 216 217 #include <unit/smc91111.h> 218 219 #elif defined(CONFIG_ARCH_MSM) 220 221 #define SMC_CAN_USE_8BIT 0 222 #define SMC_CAN_USE_16BIT 1 223 #define SMC_CAN_USE_32BIT 0 224 #define SMC_NOWAIT 1 225 226 #define SMC_inw(a, r) readw((a) + (r)) 227 #define SMC_outw(v, a, r) writew(v, (a) + (r)) 228 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 229 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 230 231 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH 232 233 #elif defined(CONFIG_COLDFIRE) 234 235 #define SMC_CAN_USE_8BIT 0 236 #define SMC_CAN_USE_16BIT 1 237 #define SMC_CAN_USE_32BIT 0 238 #define SMC_NOWAIT 1 239 240 static inline void mcf_insw(void *a, unsigned char *p, int l) 241 { 242 u16 *wp = (u16 *) p; 243 while (l-- > 0) 244 *wp++ = readw(a); 245 } 246 247 static inline void mcf_outsw(void *a, unsigned char *p, int l) 248 { 249 u16 *wp = (u16 *) p; 250 while (l-- > 0) 251 writew(*wp++, a); 252 } 253 254 #define SMC_inw(a, r) _swapw(readw((a) + (r))) 255 #define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r)) 256 #define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l) 257 #define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l) 258 259 #define SMC_IRQ_FLAGS 0 260 261 #else 262 263 /* 264 * Default configuration 265 */ 266 267 #define SMC_CAN_USE_8BIT 1 268 #define SMC_CAN_USE_16BIT 1 269 #define SMC_CAN_USE_32BIT 1 270 #define SMC_NOWAIT 1 271 272 #define SMC_IO_SHIFT (lp->io_shift) 273 274 #define SMC_inb(a, r) ioread8((a) + (r)) 275 #define SMC_inw(a, r) ioread16((a) + (r)) 276 #define SMC_inl(a, r) ioread32((a) + (r)) 277 #define SMC_outb(v, a, r) iowrite8(v, (a) + (r)) 278 #define SMC_outw(v, a, r) iowrite16(v, (a) + (r)) 279 #define SMC_outl(v, a, r) iowrite32(v, (a) + (r)) 280 #define SMC_insw(a, r, p, l) ioread16_rep((a) + (r), p, l) 281 #define SMC_outsw(a, r, p, l) iowrite16_rep((a) + (r), p, l) 282 #define SMC_insl(a, r, p, l) ioread32_rep((a) + (r), p, l) 283 #define SMC_outsl(a, r, p, l) iowrite32_rep((a) + (r), p, l) 284 285 #define RPC_LSA_DEFAULT RPC_LED_100_10 286 #define RPC_LSB_DEFAULT RPC_LED_TX_RX 287 288 #endif 289 290 291 /* store this information for the driver.. */ 292 struct smc_local { 293 /* 294 * If I have to wait until memory is available to send a 295 * packet, I will store the skbuff here, until I get the 296 * desired memory. Then, I'll send it out and free it. 297 */ 298 struct sk_buff *pending_tx_skb; 299 struct tasklet_struct tx_task; 300 301 /* version/revision of the SMC91x chip */ 302 int version; 303 304 /* Contains the current active transmission mode */ 305 int tcr_cur_mode; 306 307 /* Contains the current active receive mode */ 308 int rcr_cur_mode; 309 310 /* Contains the current active receive/phy mode */ 311 int rpc_cur_mode; 312 int ctl_rfduplx; 313 int ctl_rspeed; 314 315 u32 msg_enable; 316 u32 phy_type; 317 struct mii_if_info mii; 318 319 /* work queue */ 320 struct work_struct phy_configure; 321 struct net_device *dev; 322 int work_pending; 323 324 spinlock_t lock; 325 326 #ifdef CONFIG_ARCH_PXA 327 /* DMA needs the physical address of the chip */ 328 u_long physaddr; 329 struct device *device; 330 #endif 331 void __iomem *base; 332 void __iomem *datacs; 333 334 /* the low address lines on some platforms aren't connected... */ 335 int io_shift; 336 337 struct smc91x_platdata cfg; 338 }; 339 340 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT) 341 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT) 342 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT) 343 344 #ifdef CONFIG_ARCH_PXA 345 /* 346 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is 347 * always happening in irq context so no need to worry about races. TX is 348 * different and probably not worth it for that reason, and not as critical 349 * as RX which can overrun memory and lose packets. 350 */ 351 #include <linux/dma-mapping.h> 352 #include <mach/dma.h> 353 354 #ifdef SMC_insl 355 #undef SMC_insl 356 #define SMC_insl(a, r, p, l) \ 357 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l) 358 static inline void 359 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, 360 u_char *buf, int len) 361 { 362 u_long physaddr = lp->physaddr; 363 dma_addr_t dmabuf; 364 365 /* fallback if no DMA available */ 366 if (dma == (unsigned char)-1) { 367 readsl(ioaddr + reg, buf, len); 368 return; 369 } 370 371 /* 64 bit alignment is required for memory to memory DMA */ 372 if ((long)buf & 4) { 373 *((u32 *)buf) = SMC_inl(ioaddr, reg); 374 buf += 4; 375 len--; 376 } 377 378 len *= 4; 379 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); 380 DCSR(dma) = DCSR_NODESC; 381 DTADR(dma) = dmabuf; 382 DSADR(dma) = physaddr + reg; 383 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | 384 DCMD_WIDTH4 | (DCMD_LENGTH & len)); 385 DCSR(dma) = DCSR_NODESC | DCSR_RUN; 386 while (!(DCSR(dma) & DCSR_STOPSTATE)) 387 cpu_relax(); 388 DCSR(dma) = 0; 389 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); 390 } 391 #endif 392 393 #ifdef SMC_insw 394 #undef SMC_insw 395 #define SMC_insw(a, r, p, l) \ 396 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l) 397 static inline void 398 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, 399 u_char *buf, int len) 400 { 401 u_long physaddr = lp->physaddr; 402 dma_addr_t dmabuf; 403 404 /* fallback if no DMA available */ 405 if (dma == (unsigned char)-1) { 406 readsw(ioaddr + reg, buf, len); 407 return; 408 } 409 410 /* 64 bit alignment is required for memory to memory DMA */ 411 while ((long)buf & 6) { 412 *((u16 *)buf) = SMC_inw(ioaddr, reg); 413 buf += 2; 414 len--; 415 } 416 417 len *= 2; 418 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); 419 DCSR(dma) = DCSR_NODESC; 420 DTADR(dma) = dmabuf; 421 DSADR(dma) = physaddr + reg; 422 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | 423 DCMD_WIDTH2 | (DCMD_LENGTH & len)); 424 DCSR(dma) = DCSR_NODESC | DCSR_RUN; 425 while (!(DCSR(dma) & DCSR_STOPSTATE)) 426 cpu_relax(); 427 DCSR(dma) = 0; 428 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); 429 } 430 #endif 431 432 static void 433 smc_pxa_dma_irq(int dma, void *dummy) 434 { 435 DCSR(dma) = 0; 436 } 437 #endif /* CONFIG_ARCH_PXA */ 438 439 440 /* 441 * Everything a particular hardware setup needs should have been defined 442 * at this point. Add stubs for the undefined cases, mainly to avoid 443 * compilation warnings since they'll be optimized away, or to prevent buggy 444 * use of them. 445 */ 446 447 #if ! SMC_CAN_USE_32BIT 448 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; }) 449 #define SMC_outl(x, ioaddr, reg) BUG() 450 #define SMC_insl(a, r, p, l) BUG() 451 #define SMC_outsl(a, r, p, l) BUG() 452 #endif 453 454 #if !defined(SMC_insl) || !defined(SMC_outsl) 455 #define SMC_insl(a, r, p, l) BUG() 456 #define SMC_outsl(a, r, p, l) BUG() 457 #endif 458 459 #if ! SMC_CAN_USE_16BIT 460 461 /* 462 * Any 16-bit access is performed with two 8-bit accesses if the hardware 463 * can't do it directly. Most registers are 16-bit so those are mandatory. 464 */ 465 #define SMC_outw(x, ioaddr, reg) \ 466 do { \ 467 unsigned int __val16 = (x); \ 468 SMC_outb( __val16, ioaddr, reg ); \ 469 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\ 470 } while (0) 471 #define SMC_inw(ioaddr, reg) \ 472 ({ \ 473 unsigned int __val16; \ 474 __val16 = SMC_inb( ioaddr, reg ); \ 475 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \ 476 __val16; \ 477 }) 478 479 #define SMC_insw(a, r, p, l) BUG() 480 #define SMC_outsw(a, r, p, l) BUG() 481 482 #endif 483 484 #if !defined(SMC_insw) || !defined(SMC_outsw) 485 #define SMC_insw(a, r, p, l) BUG() 486 #define SMC_outsw(a, r, p, l) BUG() 487 #endif 488 489 #if ! SMC_CAN_USE_8BIT 490 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; }) 491 #define SMC_outb(x, ioaddr, reg) BUG() 492 #define SMC_insb(a, r, p, l) BUG() 493 #define SMC_outsb(a, r, p, l) BUG() 494 #endif 495 496 #if !defined(SMC_insb) || !defined(SMC_outsb) 497 #define SMC_insb(a, r, p, l) BUG() 498 #define SMC_outsb(a, r, p, l) BUG() 499 #endif 500 501 #ifndef SMC_CAN_USE_DATACS 502 #define SMC_CAN_USE_DATACS 0 503 #endif 504 505 #ifndef SMC_IO_SHIFT 506 #define SMC_IO_SHIFT 0 507 #endif 508 509 #ifndef SMC_IRQ_FLAGS 510 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING 511 #endif 512 513 #ifndef SMC_INTERRUPT_PREAMBLE 514 #define SMC_INTERRUPT_PREAMBLE 515 #endif 516 517 518 /* Because of bank switching, the LAN91x uses only 16 I/O ports */ 519 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) 520 #define SMC_DATA_EXTENT (4) 521 522 /* 523 . Bank Select Register: 524 . 525 . yyyy yyyy 0000 00xx 526 . xx = bank number 527 . yyyy yyyy = 0x33, for identification purposes. 528 */ 529 #define BANK_SELECT (14 << SMC_IO_SHIFT) 530 531 532 // Transmit Control Register 533 /* BANK 0 */ 534 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0) 535 #define TCR_ENABLE 0x0001 // When 1 we can transmit 536 #define TCR_LOOP 0x0002 // Controls output pin LBK 537 #define TCR_FORCOL 0x0004 // When 1 will force a collision 538 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0 539 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames 540 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier 541 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation 542 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error 543 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback 544 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode 545 546 #define TCR_CLEAR 0 /* do NOTHING */ 547 /* the default settings for the TCR register : */ 548 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN) 549 550 551 // EPH Status Register 552 /* BANK 0 */ 553 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0) 554 #define ES_TX_SUC 0x0001 // Last TX was successful 555 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx 556 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx 557 #define ES_LTX_MULT 0x0008 // Last tx was a multicast 558 #define ES_16COL 0x0010 // 16 Collisions Reached 559 #define ES_SQET 0x0020 // Signal Quality Error Test 560 #define ES_LTXBRD 0x0040 // Last tx was a broadcast 561 #define ES_TXDEFR 0x0080 // Transmit Deferred 562 #define ES_LATCOL 0x0200 // Late collision detected on last tx 563 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense 564 #define ES_EXC_DEF 0x0800 // Excessive Deferral 565 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication 566 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin 567 #define ES_TXUNRN 0x8000 // Tx Underrun 568 569 570 // Receive Control Register 571 /* BANK 0 */ 572 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0) 573 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted 574 #define RCR_PRMS 0x0002 // Enable promiscuous mode 575 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames 576 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets 577 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets 578 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision 579 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier 580 #define RCR_SOFTRST 0x8000 // resets the chip 581 582 /* the normal settings for the RCR register : */ 583 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) 584 #define RCR_CLEAR 0x0 // set it to a base state 585 586 587 // Counter Register 588 /* BANK 0 */ 589 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0) 590 591 592 // Memory Information Register 593 /* BANK 0 */ 594 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0) 595 596 597 // Receive/Phy Control Register 598 /* BANK 0 */ 599 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0) 600 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. 601 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode 602 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode 603 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb 604 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb 605 606 #ifndef RPC_LSA_DEFAULT 607 #define RPC_LSA_DEFAULT RPC_LED_100 608 #endif 609 #ifndef RPC_LSB_DEFAULT 610 #define RPC_LSB_DEFAULT RPC_LED_FD 611 #endif 612 613 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX) 614 615 616 /* Bank 0 0x0C is reserved */ 617 618 // Bank Select Register 619 /* All Banks */ 620 #define BSR_REG 0x000E 621 622 623 // Configuration Reg 624 /* BANK 1 */ 625 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1) 626 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy 627 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL 628 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus 629 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode. 630 631 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low 632 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) 633 634 635 // Base Address Register 636 /* BANK 1 */ 637 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1) 638 639 640 // Individual Address Registers 641 /* BANK 1 */ 642 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1) 643 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1) 644 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1) 645 646 647 // General Purpose Register 648 /* BANK 1 */ 649 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1) 650 651 652 // Control Register 653 /* BANK 1 */ 654 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1) 655 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received 656 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically 657 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt 658 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt 659 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt 660 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store 661 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers 662 #define CTL_STORE 0x0001 // When set stores registers into EEPROM 663 664 665 // MMU Command Register 666 /* BANK 2 */ 667 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2) 668 #define MC_BUSY 1 // When 1 the last release has not completed 669 #define MC_NOP (0<<5) // No Op 670 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets 671 #define MC_RESET (2<<5) // Reset MMU to initial state 672 #define MC_REMOVE (3<<5) // Remove the current rx packet 673 #define MC_RELEASE (4<<5) // Remove and release the current rx packet 674 #define MC_FREEPKT (5<<5) // Release packet in PNR register 675 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit 676 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs 677 678 679 // Packet Number Register 680 /* BANK 2 */ 681 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2) 682 683 684 // Allocation Result Register 685 /* BANK 2 */ 686 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2) 687 #define AR_FAILED 0x80 // Alocation Failed 688 689 690 // TX FIFO Ports Register 691 /* BANK 2 */ 692 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2) 693 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty 694 695 // RX FIFO Ports Register 696 /* BANK 2 */ 697 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2) 698 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty 699 700 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2) 701 702 // Pointer Register 703 /* BANK 2 */ 704 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2) 705 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area 706 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access 707 #define PTR_READ 0x2000 // When 1 the operation is a read 708 709 710 // Data Register 711 /* BANK 2 */ 712 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2) 713 714 715 // Interrupt Status/Acknowledge Register 716 /* BANK 2 */ 717 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2) 718 719 720 // Interrupt Mask Register 721 /* BANK 2 */ 722 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2) 723 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt 724 #define IM_ERCV_INT 0x40 // Early Receive Interrupt 725 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section 726 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns 727 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed 728 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty 729 #define IM_TX_INT 0x02 // Transmit Interrupt 730 #define IM_RCV_INT 0x01 // Receive Interrupt 731 732 733 // Multicast Table Registers 734 /* BANK 3 */ 735 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3) 736 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3) 737 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3) 738 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3) 739 740 741 // Management Interface Register (MII) 742 /* BANK 3 */ 743 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3) 744 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup 745 #define MII_MDOE 0x0008 // MII Output Enable 746 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK 747 #define MII_MDI 0x0002 // MII Input, pin MDI 748 #define MII_MDO 0x0001 // MII Output, pin MDO 749 750 751 // Revision Register 752 /* BANK 3 */ 753 /* ( hi: chip id low: rev # ) */ 754 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3) 755 756 757 // Early RCV Register 758 /* BANK 3 */ 759 /* this is NOT on SMC9192 */ 760 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3) 761 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received 762 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask 763 764 765 // External Register 766 /* BANK 7 */ 767 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7) 768 769 770 #define CHIP_9192 3 771 #define CHIP_9194 4 772 #define CHIP_9195 5 773 #define CHIP_9196 6 774 #define CHIP_91100 7 775 #define CHIP_91100FD 8 776 #define CHIP_91111FD 9 777 778 static const char * chip_ids[ 16 ] = { 779 NULL, NULL, NULL, 780 /* 3 */ "SMC91C90/91C92", 781 /* 4 */ "SMC91C94", 782 /* 5 */ "SMC91C95", 783 /* 6 */ "SMC91C96", 784 /* 7 */ "SMC91C100", 785 /* 8 */ "SMC91C100FD", 786 /* 9 */ "SMC91C11xFD", 787 NULL, NULL, NULL, 788 NULL, NULL, NULL}; 789 790 791 /* 792 . Receive status bits 793 */ 794 #define RS_ALGNERR 0x8000 795 #define RS_BRODCAST 0x4000 796 #define RS_BADCRC 0x2000 797 #define RS_ODDFRAME 0x1000 798 #define RS_TOOLONG 0x0800 799 #define RS_TOOSHORT 0x0400 800 #define RS_MULTICAST 0x0001 801 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 802 803 804 /* 805 * PHY IDs 806 * LAN83C183 == LAN91C111 Internal PHY 807 */ 808 #define PHY_LAN83C183 0x0016f840 809 #define PHY_LAN83C180 0x02821c50 810 811 /* 812 * PHY Register Addresses (LAN91C111 Internal PHY) 813 * 814 * Generic PHY registers can be found in <linux/mii.h> 815 * 816 * These phy registers are specific to our on-board phy. 817 */ 818 819 // PHY Configuration Register 1 820 #define PHY_CFG1_REG 0x10 821 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled 822 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled 823 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down 824 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler 825 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable 826 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled 827 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) 828 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db 829 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust 830 #define PHY_CFG1_TLVL_MASK 0x003C 831 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time 832 833 834 // PHY Configuration Register 2 835 #define PHY_CFG2_REG 0x11 836 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled 837 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled 838 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) 839 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo 840 841 // PHY Status Output (and Interrupt status) Register 842 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status) 843 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read 844 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected 845 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync 846 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx 847 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx 848 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx 849 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected 850 #define PHY_INT_JAB 0x0100 // 1=Jabber detected 851 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode 852 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex 853 854 // PHY Interrupt/Status Mask Register 855 #define PHY_MASK_REG 0x13 // Interrupt Mask 856 // Uses the same bit definitions as PHY_INT_REG 857 858 859 /* 860 * SMC91C96 ethernet config and status registers. 861 * These are in the "attribute" space. 862 */ 863 #define ECOR 0x8000 864 #define ECOR_RESET 0x80 865 #define ECOR_LEVEL_IRQ 0x40 866 #define ECOR_WR_ATTRIB 0x04 867 #define ECOR_ENABLE 0x01 868 869 #define ECSR 0x8002 870 #define ECSR_IOIS8 0x20 871 #define ECSR_PWRDWN 0x04 872 #define ECSR_INT 0x02 873 874 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT) 875 876 877 /* 878 * Macros to abstract register access according to the data bus 879 * capabilities. Please use those and not the in/out primitives. 880 * Note: the following macros do *not* select the bank -- this must 881 * be done separately as needed in the main code. The SMC_REG() macro 882 * only uses the bank argument for debugging purposes (when enabled). 883 * 884 * Note: despite inline functions being safer, everything leading to this 885 * should preferably be macros to let BUG() display the line number in 886 * the core source code since we're interested in the top call site 887 * not in any inline function location. 888 */ 889 890 #if SMC_DEBUG > 0 891 #define SMC_REG(lp, reg, bank) \ 892 ({ \ 893 int __b = SMC_CURRENT_BANK(lp); \ 894 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ 895 pr_err("%s: bank reg screwed (0x%04x)\n", \ 896 CARDNAME, __b); \ 897 BUG(); \ 898 } \ 899 reg<<SMC_IO_SHIFT; \ 900 }) 901 #else 902 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT) 903 #endif 904 905 /* 906 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not 907 * aligned to a 32 bit boundary. I tell you that does exist! 908 * Fortunately the affected register accesses can be easily worked around 909 * since we can write zeroes to the preceding 16 bits without adverse 910 * effects and use a 32-bit access. 911 * 912 * Enforce it on any 32-bit capable setup for now. 913 */ 914 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp) 915 916 #define SMC_GET_PN(lp) \ 917 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \ 918 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF)) 919 920 #define SMC_SET_PN(lp, x) \ 921 do { \ 922 if (SMC_MUST_ALIGN_WRITE(lp)) \ 923 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \ 924 else if (SMC_8BIT(lp)) \ 925 SMC_outb(x, ioaddr, PN_REG(lp)); \ 926 else \ 927 SMC_outw(x, ioaddr, PN_REG(lp)); \ 928 } while (0) 929 930 #define SMC_GET_AR(lp) \ 931 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \ 932 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8)) 933 934 #define SMC_GET_TXFIFO(lp) \ 935 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \ 936 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF)) 937 938 #define SMC_GET_RXFIFO(lp) \ 939 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \ 940 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8)) 941 942 #define SMC_GET_INT(lp) \ 943 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \ 944 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF)) 945 946 #define SMC_ACK_INT(lp, x) \ 947 do { \ 948 if (SMC_8BIT(lp)) \ 949 SMC_outb(x, ioaddr, INT_REG(lp)); \ 950 else { \ 951 unsigned long __flags; \ 952 int __mask; \ 953 local_irq_save(__flags); \ 954 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \ 955 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \ 956 local_irq_restore(__flags); \ 957 } \ 958 } while (0) 959 960 #define SMC_GET_INT_MASK(lp) \ 961 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \ 962 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8)) 963 964 #define SMC_SET_INT_MASK(lp, x) \ 965 do { \ 966 if (SMC_8BIT(lp)) \ 967 SMC_outb(x, ioaddr, IM_REG(lp)); \ 968 else \ 969 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \ 970 } while (0) 971 972 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT) 973 974 #define SMC_SELECT_BANK(lp, x) \ 975 do { \ 976 if (SMC_MUST_ALIGN_WRITE(lp)) \ 977 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \ 978 else \ 979 SMC_outw(x, ioaddr, BANK_SELECT); \ 980 } while (0) 981 982 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp)) 983 984 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp)) 985 986 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp)) 987 988 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp)) 989 990 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp)) 991 992 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp)) 993 994 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp)) 995 996 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp)) 997 998 #define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp)) 999 1000 #define SMC_SET_GP(lp, x) \ 1001 do { \ 1002 if (SMC_MUST_ALIGN_WRITE(lp)) \ 1003 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \ 1004 else \ 1005 SMC_outw(x, ioaddr, GP_REG(lp)); \ 1006 } while (0) 1007 1008 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp)) 1009 1010 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp)) 1011 1012 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp)) 1013 1014 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp)) 1015 1016 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp)) 1017 1018 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp)) 1019 1020 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp)) 1021 1022 #define SMC_SET_PTR(lp, x) \ 1023 do { \ 1024 if (SMC_MUST_ALIGN_WRITE(lp)) \ 1025 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \ 1026 else \ 1027 SMC_outw(x, ioaddr, PTR_REG(lp)); \ 1028 } while (0) 1029 1030 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp)) 1031 1032 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp)) 1033 1034 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp)) 1035 1036 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp)) 1037 1038 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp)) 1039 1040 #define SMC_SET_RPC(lp, x) \ 1041 do { \ 1042 if (SMC_MUST_ALIGN_WRITE(lp)) \ 1043 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \ 1044 else \ 1045 SMC_outw(x, ioaddr, RPC_REG(lp)); \ 1046 } while (0) 1047 1048 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp)) 1049 1050 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp)) 1051 1052 #ifndef SMC_GET_MAC_ADDR 1053 #define SMC_GET_MAC_ADDR(lp, addr) \ 1054 do { \ 1055 unsigned int __v; \ 1056 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \ 1057 addr[0] = __v; addr[1] = __v >> 8; \ 1058 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \ 1059 addr[2] = __v; addr[3] = __v >> 8; \ 1060 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \ 1061 addr[4] = __v; addr[5] = __v >> 8; \ 1062 } while (0) 1063 #endif 1064 1065 #define SMC_SET_MAC_ADDR(lp, addr) \ 1066 do { \ 1067 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \ 1068 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \ 1069 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \ 1070 } while (0) 1071 1072 #define SMC_SET_MCAST(lp, x) \ 1073 do { \ 1074 const unsigned char *mt = (x); \ 1075 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \ 1076 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \ 1077 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \ 1078 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \ 1079 } while (0) 1080 1081 #define SMC_PUT_PKT_HDR(lp, status, length) \ 1082 do { \ 1083 if (SMC_32BIT(lp)) \ 1084 SMC_outl((status) | (length)<<16, ioaddr, \ 1085 DATA_REG(lp)); \ 1086 else { \ 1087 SMC_outw(status, ioaddr, DATA_REG(lp)); \ 1088 SMC_outw(length, ioaddr, DATA_REG(lp)); \ 1089 } \ 1090 } while (0) 1091 1092 #define SMC_GET_PKT_HDR(lp, status, length) \ 1093 do { \ 1094 if (SMC_32BIT(lp)) { \ 1095 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \ 1096 (status) = __val & 0xffff; \ 1097 (length) = __val >> 16; \ 1098 } else { \ 1099 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \ 1100 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \ 1101 } \ 1102 } while (0) 1103 1104 #define SMC_PUSH_DATA(lp, p, l) \ 1105 do { \ 1106 if (SMC_32BIT(lp)) { \ 1107 void *__ptr = (p); \ 1108 int __len = (l); \ 1109 void __iomem *__ioaddr = ioaddr; \ 1110 if (__len >= 2 && (unsigned long)__ptr & 2) { \ 1111 __len -= 2; \ 1112 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \ 1113 __ptr += 2; \ 1114 } \ 1115 if (SMC_CAN_USE_DATACS && lp->datacs) \ 1116 __ioaddr = lp->datacs; \ 1117 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \ 1118 if (__len & 2) { \ 1119 __ptr += (__len & ~3); \ 1120 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \ 1121 } \ 1122 } else if (SMC_16BIT(lp)) \ 1123 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \ 1124 else if (SMC_8BIT(lp)) \ 1125 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \ 1126 } while (0) 1127 1128 #define SMC_PULL_DATA(lp, p, l) \ 1129 do { \ 1130 if (SMC_32BIT(lp)) { \ 1131 void *__ptr = (p); \ 1132 int __len = (l); \ 1133 void __iomem *__ioaddr = ioaddr; \ 1134 if ((unsigned long)__ptr & 2) { \ 1135 /* \ 1136 * We want 32bit alignment here. \ 1137 * Since some buses perform a full \ 1138 * 32bit fetch even for 16bit data \ 1139 * we can't use SMC_inw() here. \ 1140 * Back both source (on-chip) and \ 1141 * destination pointers of 2 bytes. \ 1142 * This is possible since the call to \ 1143 * SMC_GET_PKT_HDR() already advanced \ 1144 * the source pointer of 4 bytes, and \ 1145 * the skb_reserve(skb, 2) advanced \ 1146 * the destination pointer of 2 bytes. \ 1147 */ \ 1148 __ptr -= 2; \ 1149 __len += 2; \ 1150 SMC_SET_PTR(lp, \ 1151 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ 1152 } \ 1153 if (SMC_CAN_USE_DATACS && lp->datacs) \ 1154 __ioaddr = lp->datacs; \ 1155 __len += 2; \ 1156 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \ 1157 } else if (SMC_16BIT(lp)) \ 1158 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \ 1159 else if (SMC_8BIT(lp)) \ 1160 SMC_insb(ioaddr, DATA_REG(lp), p, l); \ 1161 } while (0) 1162 1163 #endif /* _SMC91X_H_ */ 1164