xref: /openbmc/linux/drivers/net/ethernet/smsc/smc91x.h (revision 6774def6)
1 /*------------------------------------------------------------------------
2  . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3  .
4  . Copyright (C) 1996 by Erik Stahlman
5  . Copyright (C) 2001 Standard Microsystems Corporation
6  .	Developed by Simple Network Magic Corporation
7  . Copyright (C) 2003 Monta Vista Software, Inc.
8  .	Unified SMC91x driver by Nicolas Pitre
9  .
10  . This program is free software; you can redistribute it and/or modify
11  . it under the terms of the GNU General Public License as published by
12  . the Free Software Foundation; either version 2 of the License, or
13  . (at your option) any later version.
14  .
15  . This program is distributed in the hope that it will be useful,
16  . but WITHOUT ANY WARRANTY; without even the implied warranty of
17  . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  . GNU General Public License for more details.
19  .
20  . You should have received a copy of the GNU General Public License
21  . along with this program; if not, see <http://www.gnu.org/licenses/>.
22  .
23  . Information contained in this file was obtained from the LAN91C111
24  . manual from SMC.  To get a copy, if you really want one, you can find
25  . information under www.smsc.com.
26  .
27  . Authors
28  .	Erik Stahlman		<erik@vt.edu>
29  .	Daris A Nevil		<dnevil@snmc.com>
30  .	Nicolas Pitre 		<nico@fluxnic.net>
31  .
32  ---------------------------------------------------------------------------*/
33 #ifndef _SMC91X_H_
34 #define _SMC91X_H_
35 
36 #include <linux/smc91x.h>
37 
38 /*
39  * Define your architecture specific bus configuration parameters here.
40  */
41 
42 #if defined(CONFIG_ARCH_LUBBOCK) ||\
43     defined(CONFIG_MACH_MAINSTONE) ||\
44     defined(CONFIG_MACH_ZYLONITE) ||\
45     defined(CONFIG_MACH_LITTLETON) ||\
46     defined(CONFIG_MACH_ZYLONITE2) ||\
47     defined(CONFIG_ARCH_VIPER) ||\
48     defined(CONFIG_MACH_STARGATE2) ||\
49     defined(CONFIG_ARCH_VERSATILE)
50 
51 #include <asm/mach-types.h>
52 
53 /* Now the bus width is specified in the platform data
54  * pretend here to support all I/O access types
55  */
56 #define SMC_CAN_USE_8BIT	1
57 #define SMC_CAN_USE_16BIT	1
58 #define SMC_CAN_USE_32BIT	1
59 #define SMC_NOWAIT		1
60 
61 #define SMC_IO_SHIFT		(lp->io_shift)
62 
63 #define SMC_inb(a, r)		readb((a) + (r))
64 #define SMC_inw(a, r)		readw((a) + (r))
65 #define SMC_inl(a, r)		readl((a) + (r))
66 #define SMC_outb(v, a, r)	writeb(v, (a) + (r))
67 #define SMC_outl(v, a, r)	writel(v, (a) + (r))
68 #define SMC_insw(a, r, p, l)	readsw((a) + (r), p, l)
69 #define SMC_outsw(a, r, p, l)	writesw((a) + (r), p, l)
70 #define SMC_insl(a, r, p, l)	readsl((a) + (r), p, l)
71 #define SMC_outsl(a, r, p, l)	writesl((a) + (r), p, l)
72 #define SMC_IRQ_FLAGS		(-1)	/* from resource */
73 
74 /* We actually can't write halfwords properly if not word aligned */
75 static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
76 {
77 	if ((machine_is_mainstone() || machine_is_stargate2()) && reg & 2) {
78 		unsigned int v = val << 16;
79 		v |= readl(ioaddr + (reg & ~2)) & 0xffff;
80 		writel(v, ioaddr + (reg & ~2));
81 	} else {
82 		writew(val, ioaddr + reg);
83 	}
84 }
85 
86 #elif defined(CONFIG_SA1100_PLEB)
87 /* We can only do 16-bit reads and writes in the static memory space. */
88 #define SMC_CAN_USE_8BIT	1
89 #define SMC_CAN_USE_16BIT	1
90 #define SMC_CAN_USE_32BIT	0
91 #define SMC_IO_SHIFT		0
92 #define SMC_NOWAIT		1
93 
94 #define SMC_inb(a, r)		readb((a) + (r))
95 #define SMC_insb(a, r, p, l)	readsb((a) + (r), p, (l))
96 #define SMC_inw(a, r)		readw((a) + (r))
97 #define SMC_insw(a, r, p, l)	readsw((a) + (r), p, l)
98 #define SMC_outb(v, a, r)	writeb(v, (a) + (r))
99 #define SMC_outsb(a, r, p, l)	writesb((a) + (r), p, (l))
100 #define SMC_outw(v, a, r)	writew(v, (a) + (r))
101 #define SMC_outsw(a, r, p, l)	writesw((a) + (r), p, l)
102 
103 #define SMC_IRQ_FLAGS		(-1)
104 
105 #elif defined(CONFIG_SA1100_ASSABET)
106 
107 #include <mach/neponset.h>
108 
109 /* We can only do 8-bit reads and writes in the static memory space. */
110 #define SMC_CAN_USE_8BIT	1
111 #define SMC_CAN_USE_16BIT	0
112 #define SMC_CAN_USE_32BIT	0
113 #define SMC_NOWAIT		1
114 
115 /* The first two address lines aren't connected... */
116 #define SMC_IO_SHIFT		2
117 
118 #define SMC_inb(a, r)		readb((a) + (r))
119 #define SMC_outb(v, a, r)	writeb(v, (a) + (r))
120 #define SMC_insb(a, r, p, l)	readsb((a) + (r), p, (l))
121 #define SMC_outsb(a, r, p, l)	writesb((a) + (r), p, (l))
122 #define SMC_IRQ_FLAGS		(-1)	/* from resource */
123 
124 #elif	defined(CONFIG_MACH_LOGICPD_PXA270) ||	\
125 	defined(CONFIG_MACH_NOMADIK_8815NHK)
126 
127 #define SMC_CAN_USE_8BIT	0
128 #define SMC_CAN_USE_16BIT	1
129 #define SMC_CAN_USE_32BIT	0
130 #define SMC_IO_SHIFT		0
131 #define SMC_NOWAIT		1
132 
133 #define SMC_inw(a, r)		readw((a) + (r))
134 #define SMC_outw(v, a, r)	writew(v, (a) + (r))
135 #define SMC_insw(a, r, p, l)	readsw((a) + (r), p, l)
136 #define SMC_outsw(a, r, p, l)	writesw((a) + (r), p, l)
137 
138 #elif	defined(CONFIG_ARCH_INNOKOM) || \
139 	defined(CONFIG_ARCH_PXA_IDP) || \
140 	defined(CONFIG_ARCH_RAMSES) || \
141 	defined(CONFIG_ARCH_PCM027)
142 
143 #define SMC_CAN_USE_8BIT	1
144 #define SMC_CAN_USE_16BIT	1
145 #define SMC_CAN_USE_32BIT	1
146 #define SMC_IO_SHIFT		0
147 #define SMC_NOWAIT		1
148 #define SMC_USE_PXA_DMA		1
149 
150 #define SMC_inb(a, r)		readb((a) + (r))
151 #define SMC_inw(a, r)		readw((a) + (r))
152 #define SMC_inl(a, r)		readl((a) + (r))
153 #define SMC_outb(v, a, r)	writeb(v, (a) + (r))
154 #define SMC_outl(v, a, r)	writel(v, (a) + (r))
155 #define SMC_insl(a, r, p, l)	readsl((a) + (r), p, l)
156 #define SMC_outsl(a, r, p, l)	writesl((a) + (r), p, l)
157 #define SMC_insw(a, r, p, l)	readsw((a) + (r), p, l)
158 #define SMC_outsw(a, r, p, l)	writesw((a) + (r), p, l)
159 #define SMC_IRQ_FLAGS		(-1)	/* from resource */
160 
161 /* We actually can't write halfwords properly if not word aligned */
162 static inline void
163 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
164 {
165 	if (reg & 2) {
166 		unsigned int v = val << 16;
167 		v |= readl(ioaddr + (reg & ~2)) & 0xffff;
168 		writel(v, ioaddr + (reg & ~2));
169 	} else {
170 		writew(val, ioaddr + reg);
171 	}
172 }
173 
174 #elif	defined(CONFIG_SH_SH4202_MICRODEV)
175 
176 #define SMC_CAN_USE_8BIT	0
177 #define SMC_CAN_USE_16BIT	1
178 #define SMC_CAN_USE_32BIT	0
179 
180 #define SMC_inb(a, r)		inb((a) + (r) - 0xa0000000)
181 #define SMC_inw(a, r)		inw((a) + (r) - 0xa0000000)
182 #define SMC_inl(a, r)		inl((a) + (r) - 0xa0000000)
183 #define SMC_outb(v, a, r)	outb(v, (a) + (r) - 0xa0000000)
184 #define SMC_outw(v, a, r)	outw(v, (a) + (r) - 0xa0000000)
185 #define SMC_outl(v, a, r)	outl(v, (a) + (r) - 0xa0000000)
186 #define SMC_insl(a, r, p, l)	insl((a) + (r) - 0xa0000000, p, l)
187 #define SMC_outsl(a, r, p, l)	outsl((a) + (r) - 0xa0000000, p, l)
188 #define SMC_insw(a, r, p, l)	insw((a) + (r) - 0xa0000000, p, l)
189 #define SMC_outsw(a, r, p, l)	outsw((a) + (r) - 0xa0000000, p, l)
190 
191 #define SMC_IRQ_FLAGS		(0)
192 
193 #elif   defined(CONFIG_M32R)
194 
195 #define SMC_CAN_USE_8BIT	0
196 #define SMC_CAN_USE_16BIT	1
197 #define SMC_CAN_USE_32BIT	0
198 
199 #define SMC_inb(a, r)		inb(((u32)a) + (r))
200 #define SMC_inw(a, r)		inw(((u32)a) + (r))
201 #define SMC_outb(v, a, r)	outb(v, ((u32)a) + (r))
202 #define SMC_outw(v, a, r)	outw(v, ((u32)a) + (r))
203 #define SMC_insw(a, r, p, l)	insw(((u32)a) + (r), p, l)
204 #define SMC_outsw(a, r, p, l)	outsw(((u32)a) + (r), p, l)
205 
206 #define SMC_IRQ_FLAGS		(0)
207 
208 #define RPC_LSA_DEFAULT		RPC_LED_TX_RX
209 #define RPC_LSB_DEFAULT		RPC_LED_100_10
210 
211 #elif defined(CONFIG_MN10300)
212 
213 /*
214  * MN10300/AM33 configuration
215  */
216 
217 #include <unit/smc91111.h>
218 
219 #elif defined(CONFIG_ARCH_MSM)
220 
221 #define SMC_CAN_USE_8BIT	0
222 #define SMC_CAN_USE_16BIT	1
223 #define SMC_CAN_USE_32BIT	0
224 #define SMC_NOWAIT		1
225 
226 #define SMC_inw(a, r)		readw((a) + (r))
227 #define SMC_outw(v, a, r)	writew(v, (a) + (r))
228 #define SMC_insw(a, r, p, l)	readsw((a) + (r), p, l)
229 #define SMC_outsw(a, r, p, l)	writesw((a) + (r), p, l)
230 
231 #define SMC_IRQ_FLAGS		IRQF_TRIGGER_HIGH
232 
233 #elif defined(CONFIG_COLDFIRE)
234 
235 #define SMC_CAN_USE_8BIT	0
236 #define SMC_CAN_USE_16BIT	1
237 #define SMC_CAN_USE_32BIT	0
238 #define SMC_NOWAIT		1
239 
240 static inline void mcf_insw(void *a, unsigned char *p, int l)
241 {
242 	u16 *wp = (u16 *) p;
243 	while (l-- > 0)
244 		*wp++ = readw(a);
245 }
246 
247 static inline void mcf_outsw(void *a, unsigned char *p, int l)
248 {
249 	u16 *wp = (u16 *) p;
250 	while (l-- > 0)
251 		writew(*wp++, a);
252 }
253 
254 #define SMC_inw(a, r)		_swapw(readw((a) + (r)))
255 #define SMC_outw(v, a, r)	writew(_swapw(v), (a) + (r))
256 #define SMC_insw(a, r, p, l)	mcf_insw(a + r, p, l)
257 #define SMC_outsw(a, r, p, l)	mcf_outsw(a + r, p, l)
258 
259 #define SMC_IRQ_FLAGS		0
260 
261 #else
262 
263 /*
264  * Default configuration
265  */
266 
267 #define SMC_CAN_USE_8BIT	1
268 #define SMC_CAN_USE_16BIT	1
269 #define SMC_CAN_USE_32BIT	1
270 #define SMC_NOWAIT		1
271 
272 #define SMC_IO_SHIFT		(lp->io_shift)
273 
274 #define SMC_inb(a, r)		ioread8((a) + (r))
275 #define SMC_inw(a, r)		ioread16((a) + (r))
276 #define SMC_inl(a, r)		ioread32((a) + (r))
277 #define SMC_outb(v, a, r)	iowrite8(v, (a) + (r))
278 #define SMC_outw(v, a, r)	iowrite16(v, (a) + (r))
279 #define SMC_outl(v, a, r)	iowrite32(v, (a) + (r))
280 #define SMC_insw(a, r, p, l)	ioread16_rep((a) + (r), p, l)
281 #define SMC_outsw(a, r, p, l)	iowrite16_rep((a) + (r), p, l)
282 #define SMC_insl(a, r, p, l)	ioread32_rep((a) + (r), p, l)
283 #define SMC_outsl(a, r, p, l)	iowrite32_rep((a) + (r), p, l)
284 
285 #define RPC_LSA_DEFAULT		RPC_LED_100_10
286 #define RPC_LSB_DEFAULT		RPC_LED_TX_RX
287 
288 #endif
289 
290 
291 /* store this information for the driver.. */
292 struct smc_local {
293 	/*
294 	 * If I have to wait until memory is available to send a
295 	 * packet, I will store the skbuff here, until I get the
296 	 * desired memory.  Then, I'll send it out and free it.
297 	 */
298 	struct sk_buff *pending_tx_skb;
299 	struct tasklet_struct tx_task;
300 
301 	struct gpio_desc *power_gpio;
302 	struct gpio_desc *reset_gpio;
303 
304 	/* version/revision of the SMC91x chip */
305 	int	version;
306 
307 	/* Contains the current active transmission mode */
308 	int	tcr_cur_mode;
309 
310 	/* Contains the current active receive mode */
311 	int	rcr_cur_mode;
312 
313 	/* Contains the current active receive/phy mode */
314 	int	rpc_cur_mode;
315 	int	ctl_rfduplx;
316 	int	ctl_rspeed;
317 
318 	u32	msg_enable;
319 	u32	phy_type;
320 	struct mii_if_info mii;
321 
322 	/* work queue */
323 	struct work_struct phy_configure;
324 	struct net_device *dev;
325 	int	work_pending;
326 
327 	spinlock_t lock;
328 
329 #ifdef CONFIG_ARCH_PXA
330 	/* DMA needs the physical address of the chip */
331 	u_long physaddr;
332 	struct device *device;
333 #endif
334 	void __iomem *base;
335 	void __iomem *datacs;
336 
337 	/* the low address lines on some platforms aren't connected... */
338 	int	io_shift;
339 
340 	struct smc91x_platdata cfg;
341 };
342 
343 #define SMC_8BIT(p)	((p)->cfg.flags & SMC91X_USE_8BIT)
344 #define SMC_16BIT(p)	((p)->cfg.flags & SMC91X_USE_16BIT)
345 #define SMC_32BIT(p)	((p)->cfg.flags & SMC91X_USE_32BIT)
346 
347 #ifdef CONFIG_ARCH_PXA
348 /*
349  * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
350  * always happening in irq context so no need to worry about races.  TX is
351  * different and probably not worth it for that reason, and not as critical
352  * as RX which can overrun memory and lose packets.
353  */
354 #include <linux/dma-mapping.h>
355 #include <mach/dma.h>
356 
357 #ifdef SMC_insl
358 #undef SMC_insl
359 #define SMC_insl(a, r, p, l) \
360 	smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
361 static inline void
362 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
363 		 u_char *buf, int len)
364 {
365 	u_long physaddr = lp->physaddr;
366 	dma_addr_t dmabuf;
367 
368 	/* fallback if no DMA available */
369 	if (dma == (unsigned char)-1) {
370 		readsl(ioaddr + reg, buf, len);
371 		return;
372 	}
373 
374 	/* 64 bit alignment is required for memory to memory DMA */
375 	if ((long)buf & 4) {
376 		*((u32 *)buf) = SMC_inl(ioaddr, reg);
377 		buf += 4;
378 		len--;
379 	}
380 
381 	len *= 4;
382 	dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
383 	DCSR(dma) = DCSR_NODESC;
384 	DTADR(dma) = dmabuf;
385 	DSADR(dma) = physaddr + reg;
386 	DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
387 		     DCMD_WIDTH4 | (DCMD_LENGTH & len));
388 	DCSR(dma) = DCSR_NODESC | DCSR_RUN;
389 	while (!(DCSR(dma) & DCSR_STOPSTATE))
390 		cpu_relax();
391 	DCSR(dma) = 0;
392 	dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
393 }
394 #endif
395 
396 #ifdef SMC_insw
397 #undef SMC_insw
398 #define SMC_insw(a, r, p, l) \
399 	smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
400 static inline void
401 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
402 		 u_char *buf, int len)
403 {
404 	u_long physaddr = lp->physaddr;
405 	dma_addr_t dmabuf;
406 
407 	/* fallback if no DMA available */
408 	if (dma == (unsigned char)-1) {
409 		readsw(ioaddr + reg, buf, len);
410 		return;
411 	}
412 
413 	/* 64 bit alignment is required for memory to memory DMA */
414 	while ((long)buf & 6) {
415 		*((u16 *)buf) = SMC_inw(ioaddr, reg);
416 		buf += 2;
417 		len--;
418 	}
419 
420 	len *= 2;
421 	dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
422 	DCSR(dma) = DCSR_NODESC;
423 	DTADR(dma) = dmabuf;
424 	DSADR(dma) = physaddr + reg;
425 	DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
426 		     DCMD_WIDTH2 | (DCMD_LENGTH & len));
427 	DCSR(dma) = DCSR_NODESC | DCSR_RUN;
428 	while (!(DCSR(dma) & DCSR_STOPSTATE))
429 		cpu_relax();
430 	DCSR(dma) = 0;
431 	dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
432 }
433 #endif
434 
435 static void
436 smc_pxa_dma_irq(int dma, void *dummy)
437 {
438 	DCSR(dma) = 0;
439 }
440 #endif  /* CONFIG_ARCH_PXA */
441 
442 
443 /*
444  * Everything a particular hardware setup needs should have been defined
445  * at this point.  Add stubs for the undefined cases, mainly to avoid
446  * compilation warnings since they'll be optimized away, or to prevent buggy
447  * use of them.
448  */
449 
450 #if ! SMC_CAN_USE_32BIT
451 #define SMC_inl(ioaddr, reg)		({ BUG(); 0; })
452 #define SMC_outl(x, ioaddr, reg)	BUG()
453 #define SMC_insl(a, r, p, l)		BUG()
454 #define SMC_outsl(a, r, p, l)		BUG()
455 #endif
456 
457 #if !defined(SMC_insl) || !defined(SMC_outsl)
458 #define SMC_insl(a, r, p, l)		BUG()
459 #define SMC_outsl(a, r, p, l)		BUG()
460 #endif
461 
462 #if ! SMC_CAN_USE_16BIT
463 
464 /*
465  * Any 16-bit access is performed with two 8-bit accesses if the hardware
466  * can't do it directly. Most registers are 16-bit so those are mandatory.
467  */
468 #define SMC_outw(x, ioaddr, reg)					\
469 	do {								\
470 		unsigned int __val16 = (x);				\
471 		SMC_outb( __val16, ioaddr, reg );			\
472 		SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
473 	} while (0)
474 #define SMC_inw(ioaddr, reg)						\
475 	({								\
476 		unsigned int __val16;					\
477 		__val16 =  SMC_inb( ioaddr, reg );			\
478 		__val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
479 		__val16;						\
480 	})
481 
482 #define SMC_insw(a, r, p, l)		BUG()
483 #define SMC_outsw(a, r, p, l)		BUG()
484 
485 #endif
486 
487 #if !defined(SMC_insw) || !defined(SMC_outsw)
488 #define SMC_insw(a, r, p, l)		BUG()
489 #define SMC_outsw(a, r, p, l)		BUG()
490 #endif
491 
492 #if ! SMC_CAN_USE_8BIT
493 #define SMC_inb(ioaddr, reg)		({ BUG(); 0; })
494 #define SMC_outb(x, ioaddr, reg)	BUG()
495 #define SMC_insb(a, r, p, l)		BUG()
496 #define SMC_outsb(a, r, p, l)		BUG()
497 #endif
498 
499 #if !defined(SMC_insb) || !defined(SMC_outsb)
500 #define SMC_insb(a, r, p, l)		BUG()
501 #define SMC_outsb(a, r, p, l)		BUG()
502 #endif
503 
504 #ifndef SMC_CAN_USE_DATACS
505 #define SMC_CAN_USE_DATACS	0
506 #endif
507 
508 #ifndef SMC_IO_SHIFT
509 #define SMC_IO_SHIFT	0
510 #endif
511 
512 #ifndef	SMC_IRQ_FLAGS
513 #define	SMC_IRQ_FLAGS		IRQF_TRIGGER_RISING
514 #endif
515 
516 #ifndef SMC_INTERRUPT_PREAMBLE
517 #define SMC_INTERRUPT_PREAMBLE
518 #endif
519 
520 
521 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
522 #define SMC_IO_EXTENT	(16 << SMC_IO_SHIFT)
523 #define SMC_DATA_EXTENT (4)
524 
525 /*
526  . Bank Select Register:
527  .
528  .		yyyy yyyy 0000 00xx
529  .		xx 		= bank number
530  .		yyyy yyyy	= 0x33, for identification purposes.
531 */
532 #define BANK_SELECT		(14 << SMC_IO_SHIFT)
533 
534 
535 // Transmit Control Register
536 /* BANK 0  */
537 #define TCR_REG(lp) 	SMC_REG(lp, 0x0000, 0)
538 #define TCR_ENABLE	0x0001	// When 1 we can transmit
539 #define TCR_LOOP	0x0002	// Controls output pin LBK
540 #define TCR_FORCOL	0x0004	// When 1 will force a collision
541 #define TCR_PAD_EN	0x0080	// When 1 will pad tx frames < 64 bytes w/0
542 #define TCR_NOCRC	0x0100	// When 1 will not append CRC to tx frames
543 #define TCR_MON_CSN	0x0400	// When 1 tx monitors carrier
544 #define TCR_FDUPLX    	0x0800  // When 1 enables full duplex operation
545 #define TCR_STP_SQET	0x1000	// When 1 stops tx if Signal Quality Error
546 #define TCR_EPH_LOOP	0x2000	// When 1 enables EPH block loopback
547 #define TCR_SWFDUP	0x8000	// When 1 enables Switched Full Duplex mode
548 
549 #define TCR_CLEAR	0	/* do NOTHING */
550 /* the default settings for the TCR register : */
551 #define TCR_DEFAULT	(TCR_ENABLE | TCR_PAD_EN)
552 
553 
554 // EPH Status Register
555 /* BANK 0  */
556 #define EPH_STATUS_REG(lp)	SMC_REG(lp, 0x0002, 0)
557 #define ES_TX_SUC	0x0001	// Last TX was successful
558 #define ES_SNGL_COL	0x0002	// Single collision detected for last tx
559 #define ES_MUL_COL	0x0004	// Multiple collisions detected for last tx
560 #define ES_LTX_MULT	0x0008	// Last tx was a multicast
561 #define ES_16COL	0x0010	// 16 Collisions Reached
562 #define ES_SQET		0x0020	// Signal Quality Error Test
563 #define ES_LTXBRD	0x0040	// Last tx was a broadcast
564 #define ES_TXDEFR	0x0080	// Transmit Deferred
565 #define ES_LATCOL	0x0200	// Late collision detected on last tx
566 #define ES_LOSTCARR	0x0400	// Lost Carrier Sense
567 #define ES_EXC_DEF	0x0800	// Excessive Deferral
568 #define ES_CTR_ROL	0x1000	// Counter Roll Over indication
569 #define ES_LINK_OK	0x4000	// Driven by inverted value of nLNK pin
570 #define ES_TXUNRN	0x8000	// Tx Underrun
571 
572 
573 // Receive Control Register
574 /* BANK 0  */
575 #define RCR_REG(lp)		SMC_REG(lp, 0x0004, 0)
576 #define RCR_RX_ABORT	0x0001	// Set if a rx frame was aborted
577 #define RCR_PRMS	0x0002	// Enable promiscuous mode
578 #define RCR_ALMUL	0x0004	// When set accepts all multicast frames
579 #define RCR_RXEN	0x0100	// IFF this is set, we can receive packets
580 #define RCR_STRIP_CRC	0x0200	// When set strips CRC from rx packets
581 #define RCR_ABORT_ENB	0x0200	// When set will abort rx on collision
582 #define RCR_FILT_CAR	0x0400	// When set filters leading 12 bit s of carrier
583 #define RCR_SOFTRST	0x8000 	// resets the chip
584 
585 /* the normal settings for the RCR register : */
586 #define RCR_DEFAULT	(RCR_STRIP_CRC | RCR_RXEN)
587 #define RCR_CLEAR	0x0	// set it to a base state
588 
589 
590 // Counter Register
591 /* BANK 0  */
592 #define COUNTER_REG(lp)	SMC_REG(lp, 0x0006, 0)
593 
594 
595 // Memory Information Register
596 /* BANK 0  */
597 #define MIR_REG(lp)		SMC_REG(lp, 0x0008, 0)
598 
599 
600 // Receive/Phy Control Register
601 /* BANK 0  */
602 #define RPC_REG(lp)		SMC_REG(lp, 0x000A, 0)
603 #define RPC_SPEED	0x2000	// When 1 PHY is in 100Mbps mode.
604 #define RPC_DPLX	0x1000	// When 1 PHY is in Full-Duplex Mode
605 #define RPC_ANEG	0x0800	// When 1 PHY is in Auto-Negotiate Mode
606 #define RPC_LSXA_SHFT	5	// Bits to shift LS2A,LS1A,LS0A to lsb
607 #define RPC_LSXB_SHFT	2	// Bits to get LS2B,LS1B,LS0B to lsb
608 
609 #ifndef RPC_LSA_DEFAULT
610 #define RPC_LSA_DEFAULT	RPC_LED_100
611 #endif
612 #ifndef RPC_LSB_DEFAULT
613 #define RPC_LSB_DEFAULT RPC_LED_FD
614 #endif
615 
616 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
617 
618 
619 /* Bank 0 0x0C is reserved */
620 
621 // Bank Select Register
622 /* All Banks */
623 #define BSR_REG		0x000E
624 
625 
626 // Configuration Reg
627 /* BANK 1 */
628 #define CONFIG_REG(lp)	SMC_REG(lp, 0x0000,	1)
629 #define CONFIG_EXT_PHY	0x0200	// 1=external MII, 0=internal Phy
630 #define CONFIG_GPCNTRL	0x0400	// Inverse value drives pin nCNTRL
631 #define CONFIG_NO_WAIT	0x1000	// When 1 no extra wait states on ISA bus
632 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
633 
634 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
635 #define CONFIG_DEFAULT	(CONFIG_EPH_POWER_EN)
636 
637 
638 // Base Address Register
639 /* BANK 1 */
640 #define BASE_REG(lp)	SMC_REG(lp, 0x0002, 1)
641 
642 
643 // Individual Address Registers
644 /* BANK 1 */
645 #define ADDR0_REG(lp)	SMC_REG(lp, 0x0004, 1)
646 #define ADDR1_REG(lp)	SMC_REG(lp, 0x0006, 1)
647 #define ADDR2_REG(lp)	SMC_REG(lp, 0x0008, 1)
648 
649 
650 // General Purpose Register
651 /* BANK 1 */
652 #define GP_REG(lp)		SMC_REG(lp, 0x000A, 1)
653 
654 
655 // Control Register
656 /* BANK 1 */
657 #define CTL_REG(lp)		SMC_REG(lp, 0x000C, 1)
658 #define CTL_RCV_BAD	0x4000 // When 1 bad CRC packets are received
659 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
660 #define CTL_LE_ENABLE	0x0080 // When 1 enables Link Error interrupt
661 #define CTL_CR_ENABLE	0x0040 // When 1 enables Counter Rollover interrupt
662 #define CTL_TE_ENABLE	0x0020 // When 1 enables Transmit Error interrupt
663 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
664 #define CTL_RELOAD	0x0002 // When set reads EEPROM into registers
665 #define CTL_STORE	0x0001 // When set stores registers into EEPROM
666 
667 
668 // MMU Command Register
669 /* BANK 2 */
670 #define MMU_CMD_REG(lp)	SMC_REG(lp, 0x0000, 2)
671 #define MC_BUSY		1	// When 1 the last release has not completed
672 #define MC_NOP		(0<<5)	// No Op
673 #define MC_ALLOC	(1<<5) 	// OR with number of 256 byte packets
674 #define MC_RESET	(2<<5)	// Reset MMU to initial state
675 #define MC_REMOVE	(3<<5) 	// Remove the current rx packet
676 #define MC_RELEASE  	(4<<5) 	// Remove and release the current rx packet
677 #define MC_FREEPKT  	(5<<5) 	// Release packet in PNR register
678 #define MC_ENQUEUE	(6<<5)	// Enqueue the packet for transmit
679 #define MC_RSTTXFIFO	(7<<5)	// Reset the TX FIFOs
680 
681 
682 // Packet Number Register
683 /* BANK 2 */
684 #define PN_REG(lp)		SMC_REG(lp, 0x0002, 2)
685 
686 
687 // Allocation Result Register
688 /* BANK 2 */
689 #define AR_REG(lp)		SMC_REG(lp, 0x0003, 2)
690 #define AR_FAILED	0x80	// Alocation Failed
691 
692 
693 // TX FIFO Ports Register
694 /* BANK 2 */
695 #define TXFIFO_REG(lp)	SMC_REG(lp, 0x0004, 2)
696 #define TXFIFO_TEMPTY	0x80	// TX FIFO Empty
697 
698 // RX FIFO Ports Register
699 /* BANK 2 */
700 #define RXFIFO_REG(lp)	SMC_REG(lp, 0x0005, 2)
701 #define RXFIFO_REMPTY	0x80	// RX FIFO Empty
702 
703 #define FIFO_REG(lp)	SMC_REG(lp, 0x0004, 2)
704 
705 // Pointer Register
706 /* BANK 2 */
707 #define PTR_REG(lp)		SMC_REG(lp, 0x0006, 2)
708 #define PTR_RCV		0x8000 // 1=Receive area, 0=Transmit area
709 #define PTR_AUTOINC 	0x4000 // Auto increment the pointer on each access
710 #define PTR_READ	0x2000 // When 1 the operation is a read
711 
712 
713 // Data Register
714 /* BANK 2 */
715 #define DATA_REG(lp)	SMC_REG(lp, 0x0008, 2)
716 
717 
718 // Interrupt Status/Acknowledge Register
719 /* BANK 2 */
720 #define INT_REG(lp)		SMC_REG(lp, 0x000C, 2)
721 
722 
723 // Interrupt Mask Register
724 /* BANK 2 */
725 #define IM_REG(lp)		SMC_REG(lp, 0x000D, 2)
726 #define IM_MDINT	0x80 // PHY MI Register 18 Interrupt
727 #define IM_ERCV_INT	0x40 // Early Receive Interrupt
728 #define IM_EPH_INT	0x20 // Set by Ethernet Protocol Handler section
729 #define IM_RX_OVRN_INT	0x10 // Set by Receiver Overruns
730 #define IM_ALLOC_INT	0x08 // Set when allocation request is completed
731 #define IM_TX_EMPTY_INT	0x04 // Set if the TX FIFO goes empty
732 #define IM_TX_INT	0x02 // Transmit Interrupt
733 #define IM_RCV_INT	0x01 // Receive Interrupt
734 
735 
736 // Multicast Table Registers
737 /* BANK 3 */
738 #define MCAST_REG1(lp)	SMC_REG(lp, 0x0000, 3)
739 #define MCAST_REG2(lp)	SMC_REG(lp, 0x0002, 3)
740 #define MCAST_REG3(lp)	SMC_REG(lp, 0x0004, 3)
741 #define MCAST_REG4(lp)	SMC_REG(lp, 0x0006, 3)
742 
743 
744 // Management Interface Register (MII)
745 /* BANK 3 */
746 #define MII_REG(lp)		SMC_REG(lp, 0x0008, 3)
747 #define MII_MSK_CRS100	0x4000 // Disables CRS100 detection during tx half dup
748 #define MII_MDOE	0x0008 // MII Output Enable
749 #define MII_MCLK	0x0004 // MII Clock, pin MDCLK
750 #define MII_MDI		0x0002 // MII Input, pin MDI
751 #define MII_MDO		0x0001 // MII Output, pin MDO
752 
753 
754 // Revision Register
755 /* BANK 3 */
756 /* ( hi: chip id   low: rev # ) */
757 #define REV_REG(lp)		SMC_REG(lp, 0x000A, 3)
758 
759 
760 // Early RCV Register
761 /* BANK 3 */
762 /* this is NOT on SMC9192 */
763 #define ERCV_REG(lp)	SMC_REG(lp, 0x000C, 3)
764 #define ERCV_RCV_DISCRD	0x0080 // When 1 discards a packet being received
765 #define ERCV_THRESHOLD	0x001F // ERCV Threshold Mask
766 
767 
768 // External Register
769 /* BANK 7 */
770 #define EXT_REG(lp)		SMC_REG(lp, 0x0000, 7)
771 
772 
773 #define CHIP_9192	3
774 #define CHIP_9194	4
775 #define CHIP_9195	5
776 #define CHIP_9196	6
777 #define CHIP_91100	7
778 #define CHIP_91100FD	8
779 #define CHIP_91111FD	9
780 
781 static const char * chip_ids[ 16 ] =  {
782 	NULL, NULL, NULL,
783 	/* 3 */ "SMC91C90/91C92",
784 	/* 4 */ "SMC91C94",
785 	/* 5 */ "SMC91C95",
786 	/* 6 */ "SMC91C96",
787 	/* 7 */ "SMC91C100",
788 	/* 8 */ "SMC91C100FD",
789 	/* 9 */ "SMC91C11xFD",
790 	NULL, NULL, NULL,
791 	NULL, NULL, NULL};
792 
793 
794 /*
795  . Receive status bits
796 */
797 #define RS_ALGNERR	0x8000
798 #define RS_BRODCAST	0x4000
799 #define RS_BADCRC	0x2000
800 #define RS_ODDFRAME	0x1000
801 #define RS_TOOLONG	0x0800
802 #define RS_TOOSHORT	0x0400
803 #define RS_MULTICAST	0x0001
804 #define RS_ERRORS	(RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
805 
806 
807 /*
808  * PHY IDs
809  *  LAN83C183 == LAN91C111 Internal PHY
810  */
811 #define PHY_LAN83C183	0x0016f840
812 #define PHY_LAN83C180	0x02821c50
813 
814 /*
815  * PHY Register Addresses (LAN91C111 Internal PHY)
816  *
817  * Generic PHY registers can be found in <linux/mii.h>
818  *
819  * These phy registers are specific to our on-board phy.
820  */
821 
822 // PHY Configuration Register 1
823 #define PHY_CFG1_REG		0x10
824 #define PHY_CFG1_LNKDIS		0x8000	// 1=Rx Link Detect Function disabled
825 #define PHY_CFG1_XMTDIS		0x4000	// 1=TP Transmitter Disabled
826 #define PHY_CFG1_XMTPDN		0x2000	// 1=TP Transmitter Powered Down
827 #define PHY_CFG1_BYPSCR		0x0400	// 1=Bypass scrambler/descrambler
828 #define PHY_CFG1_UNSCDS		0x0200	// 1=Unscramble Idle Reception Disable
829 #define PHY_CFG1_EQLZR		0x0100	// 1=Rx Equalizer Disabled
830 #define PHY_CFG1_CABLE		0x0080	// 1=STP(150ohm), 0=UTP(100ohm)
831 #define PHY_CFG1_RLVL0		0x0040	// 1=Rx Squelch level reduced by 4.5db
832 #define PHY_CFG1_TLVL_SHIFT	2	// Transmit Output Level Adjust
833 #define PHY_CFG1_TLVL_MASK	0x003C
834 #define PHY_CFG1_TRF_MASK	0x0003	// Transmitter Rise/Fall time
835 
836 
837 // PHY Configuration Register 2
838 #define PHY_CFG2_REG		0x11
839 #define PHY_CFG2_APOLDIS	0x0020	// 1=Auto Polarity Correction disabled
840 #define PHY_CFG2_JABDIS		0x0010	// 1=Jabber disabled
841 #define PHY_CFG2_MREG		0x0008	// 1=Multiple register access (MII mgt)
842 #define PHY_CFG2_INTMDIO	0x0004	// 1=Interrupt signaled with MDIO pulseo
843 
844 // PHY Status Output (and Interrupt status) Register
845 #define PHY_INT_REG		0x12	// Status Output (Interrupt Status)
846 #define PHY_INT_INT		0x8000	// 1=bits have changed since last read
847 #define PHY_INT_LNKFAIL		0x4000	// 1=Link Not detected
848 #define PHY_INT_LOSSSYNC	0x2000	// 1=Descrambler has lost sync
849 #define PHY_INT_CWRD		0x1000	// 1=Invalid 4B5B code detected on rx
850 #define PHY_INT_SSD		0x0800	// 1=No Start Of Stream detected on rx
851 #define PHY_INT_ESD		0x0400	// 1=No End Of Stream detected on rx
852 #define PHY_INT_RPOL		0x0200	// 1=Reverse Polarity detected
853 #define PHY_INT_JAB		0x0100	// 1=Jabber detected
854 #define PHY_INT_SPDDET		0x0080	// 1=100Base-TX mode, 0=10Base-T mode
855 #define PHY_INT_DPLXDET		0x0040	// 1=Device in Full Duplex
856 
857 // PHY Interrupt/Status Mask Register
858 #define PHY_MASK_REG		0x13	// Interrupt Mask
859 // Uses the same bit definitions as PHY_INT_REG
860 
861 
862 /*
863  * SMC91C96 ethernet config and status registers.
864  * These are in the "attribute" space.
865  */
866 #define ECOR			0x8000
867 #define ECOR_RESET		0x80
868 #define ECOR_LEVEL_IRQ		0x40
869 #define ECOR_WR_ATTRIB		0x04
870 #define ECOR_ENABLE		0x01
871 
872 #define ECSR			0x8002
873 #define ECSR_IOIS8		0x20
874 #define ECSR_PWRDWN		0x04
875 #define ECSR_INT		0x02
876 
877 #define ATTRIB_SIZE		((64*1024) << SMC_IO_SHIFT)
878 
879 
880 /*
881  * Macros to abstract register access according to the data bus
882  * capabilities.  Please use those and not the in/out primitives.
883  * Note: the following macros do *not* select the bank -- this must
884  * be done separately as needed in the main code.  The SMC_REG() macro
885  * only uses the bank argument for debugging purposes (when enabled).
886  *
887  * Note: despite inline functions being safer, everything leading to this
888  * should preferably be macros to let BUG() display the line number in
889  * the core source code since we're interested in the top call site
890  * not in any inline function location.
891  */
892 
893 #if SMC_DEBUG > 0
894 #define SMC_REG(lp, reg, bank)					\
895 	({								\
896 		int __b = SMC_CURRENT_BANK(lp);			\
897 		if (unlikely((__b & ~0xf0) != (0x3300 | bank))) {	\
898 			pr_err("%s: bank reg screwed (0x%04x)\n",	\
899 			       CARDNAME, __b);				\
900 			BUG();						\
901 		}							\
902 		reg<<SMC_IO_SHIFT;					\
903 	})
904 #else
905 #define SMC_REG(lp, reg, bank)	(reg<<SMC_IO_SHIFT)
906 #endif
907 
908 /*
909  * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
910  * aligned to a 32 bit boundary.  I tell you that does exist!
911  * Fortunately the affected register accesses can be easily worked around
912  * since we can write zeroes to the preceding 16 bits without adverse
913  * effects and use a 32-bit access.
914  *
915  * Enforce it on any 32-bit capable setup for now.
916  */
917 #define SMC_MUST_ALIGN_WRITE(lp)	SMC_32BIT(lp)
918 
919 #define SMC_GET_PN(lp)						\
920 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, PN_REG(lp)))	\
921 				: (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
922 
923 #define SMC_SET_PN(lp, x)						\
924 	do {								\
925 		if (SMC_MUST_ALIGN_WRITE(lp))				\
926 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2));	\
927 		else if (SMC_8BIT(lp))				\
928 			SMC_outb(x, ioaddr, PN_REG(lp));		\
929 		else							\
930 			SMC_outw(x, ioaddr, PN_REG(lp));		\
931 	} while (0)
932 
933 #define SMC_GET_AR(lp)						\
934 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, AR_REG(lp)))	\
935 				: (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
936 
937 #define SMC_GET_TXFIFO(lp)						\
938 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, TXFIFO_REG(lp)))	\
939 				: (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
940 
941 #define SMC_GET_RXFIFO(lp)						\
942 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, RXFIFO_REG(lp)))	\
943 				: (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
944 
945 #define SMC_GET_INT(lp)						\
946 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, INT_REG(lp)))	\
947 				: (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
948 
949 #define SMC_ACK_INT(lp, x)						\
950 	do {								\
951 		if (SMC_8BIT(lp))					\
952 			SMC_outb(x, ioaddr, INT_REG(lp));		\
953 		else {							\
954 			unsigned long __flags;				\
955 			int __mask;					\
956 			local_irq_save(__flags);			\
957 			__mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
958 			SMC_outw(__mask | (x), ioaddr, INT_REG(lp));	\
959 			local_irq_restore(__flags);			\
960 		}							\
961 	} while (0)
962 
963 #define SMC_GET_INT_MASK(lp)						\
964 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, IM_REG(lp)))	\
965 				: (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
966 
967 #define SMC_SET_INT_MASK(lp, x)					\
968 	do {								\
969 		if (SMC_8BIT(lp))					\
970 			SMC_outb(x, ioaddr, IM_REG(lp));		\
971 		else							\
972 			SMC_outw((x) << 8, ioaddr, INT_REG(lp));	\
973 	} while (0)
974 
975 #define SMC_CURRENT_BANK(lp)	SMC_inw(ioaddr, BANK_SELECT)
976 
977 #define SMC_SELECT_BANK(lp, x)					\
978 	do {								\
979 		if (SMC_MUST_ALIGN_WRITE(lp))				\
980 			SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT);	\
981 		else							\
982 			SMC_outw(x, ioaddr, BANK_SELECT);		\
983 	} while (0)
984 
985 #define SMC_GET_BASE(lp)		SMC_inw(ioaddr, BASE_REG(lp))
986 
987 #define SMC_SET_BASE(lp, x)		SMC_outw(x, ioaddr, BASE_REG(lp))
988 
989 #define SMC_GET_CONFIG(lp)	SMC_inw(ioaddr, CONFIG_REG(lp))
990 
991 #define SMC_SET_CONFIG(lp, x)	SMC_outw(x, ioaddr, CONFIG_REG(lp))
992 
993 #define SMC_GET_COUNTER(lp)	SMC_inw(ioaddr, COUNTER_REG(lp))
994 
995 #define SMC_GET_CTL(lp)		SMC_inw(ioaddr, CTL_REG(lp))
996 
997 #define SMC_SET_CTL(lp, x)		SMC_outw(x, ioaddr, CTL_REG(lp))
998 
999 #define SMC_GET_MII(lp)		SMC_inw(ioaddr, MII_REG(lp))
1000 
1001 #define SMC_GET_GP(lp)		SMC_inw(ioaddr, GP_REG(lp))
1002 
1003 #define SMC_SET_GP(lp, x)						\
1004 	do {								\
1005 		if (SMC_MUST_ALIGN_WRITE(lp))				\
1006 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1));	\
1007 		else							\
1008 			SMC_outw(x, ioaddr, GP_REG(lp));		\
1009 	} while (0)
1010 
1011 #define SMC_SET_MII(lp, x)		SMC_outw(x, ioaddr, MII_REG(lp))
1012 
1013 #define SMC_GET_MIR(lp)		SMC_inw(ioaddr, MIR_REG(lp))
1014 
1015 #define SMC_SET_MIR(lp, x)		SMC_outw(x, ioaddr, MIR_REG(lp))
1016 
1017 #define SMC_GET_MMU_CMD(lp)	SMC_inw(ioaddr, MMU_CMD_REG(lp))
1018 
1019 #define SMC_SET_MMU_CMD(lp, x)	SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1020 
1021 #define SMC_GET_FIFO(lp)		SMC_inw(ioaddr, FIFO_REG(lp))
1022 
1023 #define SMC_GET_PTR(lp)		SMC_inw(ioaddr, PTR_REG(lp))
1024 
1025 #define SMC_SET_PTR(lp, x)						\
1026 	do {								\
1027 		if (SMC_MUST_ALIGN_WRITE(lp))				\
1028 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2));	\
1029 		else							\
1030 			SMC_outw(x, ioaddr, PTR_REG(lp));		\
1031 	} while (0)
1032 
1033 #define SMC_GET_EPH_STATUS(lp)	SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1034 
1035 #define SMC_GET_RCR(lp)		SMC_inw(ioaddr, RCR_REG(lp))
1036 
1037 #define SMC_SET_RCR(lp, x)		SMC_outw(x, ioaddr, RCR_REG(lp))
1038 
1039 #define SMC_GET_REV(lp)		SMC_inw(ioaddr, REV_REG(lp))
1040 
1041 #define SMC_GET_RPC(lp)		SMC_inw(ioaddr, RPC_REG(lp))
1042 
1043 #define SMC_SET_RPC(lp, x)						\
1044 	do {								\
1045 		if (SMC_MUST_ALIGN_WRITE(lp))				\
1046 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0));	\
1047 		else							\
1048 			SMC_outw(x, ioaddr, RPC_REG(lp));		\
1049 	} while (0)
1050 
1051 #define SMC_GET_TCR(lp)		SMC_inw(ioaddr, TCR_REG(lp))
1052 
1053 #define SMC_SET_TCR(lp, x)		SMC_outw(x, ioaddr, TCR_REG(lp))
1054 
1055 #ifndef SMC_GET_MAC_ADDR
1056 #define SMC_GET_MAC_ADDR(lp, addr)					\
1057 	do {								\
1058 		unsigned int __v;					\
1059 		__v = SMC_inw(ioaddr, ADDR0_REG(lp));			\
1060 		addr[0] = __v; addr[1] = __v >> 8;			\
1061 		__v = SMC_inw(ioaddr, ADDR1_REG(lp));			\
1062 		addr[2] = __v; addr[3] = __v >> 8;			\
1063 		__v = SMC_inw(ioaddr, ADDR2_REG(lp));			\
1064 		addr[4] = __v; addr[5] = __v >> 8;			\
1065 	} while (0)
1066 #endif
1067 
1068 #define SMC_SET_MAC_ADDR(lp, addr)					\
1069 	do {								\
1070 		SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1071 		SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1072 		SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1073 	} while (0)
1074 
1075 #define SMC_SET_MCAST(lp, x)						\
1076 	do {								\
1077 		const unsigned char *mt = (x);				\
1078 		SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1079 		SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1080 		SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1081 		SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1082 	} while (0)
1083 
1084 #define SMC_PUT_PKT_HDR(lp, status, length)				\
1085 	do {								\
1086 		if (SMC_32BIT(lp))					\
1087 			SMC_outl((status) | (length)<<16, ioaddr,	\
1088 				 DATA_REG(lp));			\
1089 		else {							\
1090 			SMC_outw(status, ioaddr, DATA_REG(lp));	\
1091 			SMC_outw(length, ioaddr, DATA_REG(lp));	\
1092 		}							\
1093 	} while (0)
1094 
1095 #define SMC_GET_PKT_HDR(lp, status, length)				\
1096 	do {								\
1097 		if (SMC_32BIT(lp)) {				\
1098 			unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1099 			(status) = __val & 0xffff;			\
1100 			(length) = __val >> 16;				\
1101 		} else {						\
1102 			(status) = SMC_inw(ioaddr, DATA_REG(lp));	\
1103 			(length) = SMC_inw(ioaddr, DATA_REG(lp));	\
1104 		}							\
1105 	} while (0)
1106 
1107 #define SMC_PUSH_DATA(lp, p, l)					\
1108 	do {								\
1109 		if (SMC_32BIT(lp)) {				\
1110 			void *__ptr = (p);				\
1111 			int __len = (l);				\
1112 			void __iomem *__ioaddr = ioaddr;		\
1113 			if (__len >= 2 && (unsigned long)__ptr & 2) {	\
1114 				__len -= 2;				\
1115 				SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1116 				__ptr += 2;				\
1117 			}						\
1118 			if (SMC_CAN_USE_DATACS && lp->datacs)		\
1119 				__ioaddr = lp->datacs;			\
1120 			SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1121 			if (__len & 2) {				\
1122 				__ptr += (__len & ~3);			\
1123 				SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1124 			}						\
1125 		} else if (SMC_16BIT(lp))				\
1126 			SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1);	\
1127 		else if (SMC_8BIT(lp))				\
1128 			SMC_outsb(ioaddr, DATA_REG(lp), p, l);	\
1129 	} while (0)
1130 
1131 #define SMC_PULL_DATA(lp, p, l)					\
1132 	do {								\
1133 		if (SMC_32BIT(lp)) {				\
1134 			void *__ptr = (p);				\
1135 			int __len = (l);				\
1136 			void __iomem *__ioaddr = ioaddr;		\
1137 			if ((unsigned long)__ptr & 2) {			\
1138 				/*					\
1139 				 * We want 32bit alignment here.	\
1140 				 * Since some buses perform a full	\
1141 				 * 32bit fetch even for 16bit data	\
1142 				 * we can't use SMC_inw() here.		\
1143 				 * Back both source (on-chip) and	\
1144 				 * destination pointers of 2 bytes.	\
1145 				 * This is possible since the call to	\
1146 				 * SMC_GET_PKT_HDR() already advanced	\
1147 				 * the source pointer of 4 bytes, and	\
1148 				 * the skb_reserve(skb, 2) advanced	\
1149 				 * the destination pointer of 2 bytes.	\
1150 				 */					\
1151 				__ptr -= 2;				\
1152 				__len += 2;				\
1153 				SMC_SET_PTR(lp,			\
1154 					2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1155 			}						\
1156 			if (SMC_CAN_USE_DATACS && lp->datacs)		\
1157 				__ioaddr = lp->datacs;			\
1158 			__len += 2;					\
1159 			SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1160 		} else if (SMC_16BIT(lp))				\
1161 			SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1);	\
1162 		else if (SMC_8BIT(lp))				\
1163 			SMC_insb(ioaddr, DATA_REG(lp), p, l);		\
1164 	} while (0)
1165 
1166 #endif  /* _SMC91X_H_ */
1167