1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * smc91x.c 4 * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices. 5 * 6 * Copyright (C) 1996 by Erik Stahlman 7 * Copyright (C) 2001 Standard Microsystems Corporation 8 * Developed by Simple Network Magic Corporation 9 * Copyright (C) 2003 Monta Vista Software, Inc. 10 * Unified SMC91x driver by Nicolas Pitre 11 * 12 * Arguments: 13 * io = for the base address 14 * irq = for the IRQ 15 * nowait = 0 for normal wait states, 1 eliminates additional wait states 16 * 17 * original author: 18 * Erik Stahlman <erik@vt.edu> 19 * 20 * hardware multicast code: 21 * Peter Cammaert <pc@denkart.be> 22 * 23 * contributors: 24 * Daris A Nevil <dnevil@snmc.com> 25 * Nicolas Pitre <nico@fluxnic.net> 26 * Russell King <rmk@arm.linux.org.uk> 27 * 28 * History: 29 * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet 30 * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ" 31 * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111 32 * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111 33 * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111 34 * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support 35 * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races, 36 * more bus abstraction, big cleanup, etc. 37 * 29/09/03 Russell King - add driver model support 38 * - ethtool support 39 * - convert to use generic MII interface 40 * - add link up/down notification 41 * - don't try to handle full negotiation in 42 * smc_phy_configure 43 * - clean up (and fix stack overrun) in PHY 44 * MII read/write functions 45 * 22/09/04 Nicolas Pitre big update (see commit log for details) 46 */ 47 static const char version[] = 48 "smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>"; 49 50 /* Debugging level */ 51 #ifndef SMC_DEBUG 52 #define SMC_DEBUG 0 53 #endif 54 55 56 #include <linux/module.h> 57 #include <linux/kernel.h> 58 #include <linux/sched.h> 59 #include <linux/delay.h> 60 #include <linux/interrupt.h> 61 #include <linux/irq.h> 62 #include <linux/errno.h> 63 #include <linux/ioport.h> 64 #include <linux/crc32.h> 65 #include <linux/platform_device.h> 66 #include <linux/spinlock.h> 67 #include <linux/ethtool.h> 68 #include <linux/mii.h> 69 #include <linux/workqueue.h> 70 #include <linux/of.h> 71 #include <linux/of_device.h> 72 #include <linux/of_gpio.h> 73 74 #include <linux/netdevice.h> 75 #include <linux/etherdevice.h> 76 #include <linux/skbuff.h> 77 78 #include <asm/io.h> 79 80 #include "smc91x.h" 81 82 #if defined(CONFIG_ASSABET_NEPONSET) 83 #include <mach/assabet.h> 84 #include <mach/neponset.h> 85 #endif 86 87 #ifndef SMC_NOWAIT 88 # define SMC_NOWAIT 0 89 #endif 90 static int nowait = SMC_NOWAIT; 91 module_param(nowait, int, 0400); 92 MODULE_PARM_DESC(nowait, "set to 1 for no wait state"); 93 94 /* 95 * Transmit timeout, default 5 seconds. 96 */ 97 static int watchdog = 1000; 98 module_param(watchdog, int, 0400); 99 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); 100 101 MODULE_LICENSE("GPL"); 102 MODULE_ALIAS("platform:smc91x"); 103 104 /* 105 * The internal workings of the driver. If you are changing anything 106 * here with the SMC stuff, you should have the datasheet and know 107 * what you are doing. 108 */ 109 #define CARDNAME "smc91x" 110 111 /* 112 * Use power-down feature of the chip 113 */ 114 #define POWER_DOWN 1 115 116 /* 117 * Wait time for memory to be free. This probably shouldn't be 118 * tuned that much, as waiting for this means nothing else happens 119 * in the system 120 */ 121 #define MEMORY_WAIT_TIME 16 122 123 /* 124 * The maximum number of processing loops allowed for each call to the 125 * IRQ handler. 126 */ 127 #define MAX_IRQ_LOOPS 8 128 129 /* 130 * This selects whether TX packets are sent one by one to the SMC91x internal 131 * memory and throttled until transmission completes. This may prevent 132 * RX overruns a litle by keeping much of the memory free for RX packets 133 * but to the expense of reduced TX throughput and increased IRQ overhead. 134 * Note this is not a cure for a too slow data bus or too high IRQ latency. 135 */ 136 #define THROTTLE_TX_PKTS 0 137 138 /* 139 * The MII clock high/low times. 2x this number gives the MII clock period 140 * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!) 141 */ 142 #define MII_DELAY 1 143 144 #define DBG(n, dev, fmt, ...) \ 145 do { \ 146 if (SMC_DEBUG >= (n)) \ 147 netdev_dbg(dev, fmt, ##__VA_ARGS__); \ 148 } while (0) 149 150 #define PRINTK(dev, fmt, ...) \ 151 do { \ 152 if (SMC_DEBUG > 0) \ 153 netdev_info(dev, fmt, ##__VA_ARGS__); \ 154 else \ 155 netdev_dbg(dev, fmt, ##__VA_ARGS__); \ 156 } while (0) 157 158 #if SMC_DEBUG > 3 159 static void PRINT_PKT(u_char *buf, int length) 160 { 161 int i; 162 int remainder; 163 int lines; 164 165 lines = length / 16; 166 remainder = length % 16; 167 168 for (i = 0; i < lines ; i ++) { 169 int cur; 170 printk(KERN_DEBUG); 171 for (cur = 0; cur < 8; cur++) { 172 u_char a, b; 173 a = *buf++; 174 b = *buf++; 175 pr_cont("%02x%02x ", a, b); 176 } 177 pr_cont("\n"); 178 } 179 printk(KERN_DEBUG); 180 for (i = 0; i < remainder/2 ; i++) { 181 u_char a, b; 182 a = *buf++; 183 b = *buf++; 184 pr_cont("%02x%02x ", a, b); 185 } 186 pr_cont("\n"); 187 } 188 #else 189 static inline void PRINT_PKT(u_char *buf, int length) { } 190 #endif 191 192 193 /* this enables an interrupt in the interrupt mask register */ 194 #define SMC_ENABLE_INT(lp, x) do { \ 195 unsigned char mask; \ 196 unsigned long smc_enable_flags; \ 197 spin_lock_irqsave(&lp->lock, smc_enable_flags); \ 198 mask = SMC_GET_INT_MASK(lp); \ 199 mask |= (x); \ 200 SMC_SET_INT_MASK(lp, mask); \ 201 spin_unlock_irqrestore(&lp->lock, smc_enable_flags); \ 202 } while (0) 203 204 /* this disables an interrupt from the interrupt mask register */ 205 #define SMC_DISABLE_INT(lp, x) do { \ 206 unsigned char mask; \ 207 unsigned long smc_disable_flags; \ 208 spin_lock_irqsave(&lp->lock, smc_disable_flags); \ 209 mask = SMC_GET_INT_MASK(lp); \ 210 mask &= ~(x); \ 211 SMC_SET_INT_MASK(lp, mask); \ 212 spin_unlock_irqrestore(&lp->lock, smc_disable_flags); \ 213 } while (0) 214 215 /* 216 * Wait while MMU is busy. This is usually in the order of a few nanosecs 217 * if at all, but let's avoid deadlocking the system if the hardware 218 * decides to go south. 219 */ 220 #define SMC_WAIT_MMU_BUSY(lp) do { \ 221 if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \ 222 unsigned long timeout = jiffies + 2; \ 223 while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \ 224 if (time_after(jiffies, timeout)) { \ 225 netdev_dbg(dev, "timeout %s line %d\n", \ 226 __FILE__, __LINE__); \ 227 break; \ 228 } \ 229 cpu_relax(); \ 230 } \ 231 } \ 232 } while (0) 233 234 235 /* 236 * this does a soft reset on the device 237 */ 238 static void smc_reset(struct net_device *dev) 239 { 240 struct smc_local *lp = netdev_priv(dev); 241 void __iomem *ioaddr = lp->base; 242 unsigned int ctl, cfg; 243 struct sk_buff *pending_skb; 244 245 DBG(2, dev, "%s\n", __func__); 246 247 /* Disable all interrupts, block TX tasklet */ 248 spin_lock_irq(&lp->lock); 249 SMC_SELECT_BANK(lp, 2); 250 SMC_SET_INT_MASK(lp, 0); 251 pending_skb = lp->pending_tx_skb; 252 lp->pending_tx_skb = NULL; 253 spin_unlock_irq(&lp->lock); 254 255 /* free any pending tx skb */ 256 if (pending_skb) { 257 dev_kfree_skb(pending_skb); 258 dev->stats.tx_errors++; 259 dev->stats.tx_aborted_errors++; 260 } 261 262 /* 263 * This resets the registers mostly to defaults, but doesn't 264 * affect EEPROM. That seems unnecessary 265 */ 266 SMC_SELECT_BANK(lp, 0); 267 SMC_SET_RCR(lp, RCR_SOFTRST); 268 269 /* 270 * Setup the Configuration Register 271 * This is necessary because the CONFIG_REG is not affected 272 * by a soft reset 273 */ 274 SMC_SELECT_BANK(lp, 1); 275 276 cfg = CONFIG_DEFAULT; 277 278 /* 279 * Setup for fast accesses if requested. If the card/system 280 * can't handle it then there will be no recovery except for 281 * a hard reset or power cycle 282 */ 283 if (lp->cfg.flags & SMC91X_NOWAIT) 284 cfg |= CONFIG_NO_WAIT; 285 286 /* 287 * Release from possible power-down state 288 * Configuration register is not affected by Soft Reset 289 */ 290 cfg |= CONFIG_EPH_POWER_EN; 291 292 SMC_SET_CONFIG(lp, cfg); 293 294 /* this should pause enough for the chip to be happy */ 295 /* 296 * elaborate? What does the chip _need_? --jgarzik 297 * 298 * This seems to be undocumented, but something the original 299 * driver(s) have always done. Suspect undocumented timing 300 * info/determined empirically. --rmk 301 */ 302 udelay(1); 303 304 /* Disable transmit and receive functionality */ 305 SMC_SELECT_BANK(lp, 0); 306 SMC_SET_RCR(lp, RCR_CLEAR); 307 SMC_SET_TCR(lp, TCR_CLEAR); 308 309 SMC_SELECT_BANK(lp, 1); 310 ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE; 311 312 /* 313 * Set the control register to automatically release successfully 314 * transmitted packets, to make the best use out of our limited 315 * memory 316 */ 317 if(!THROTTLE_TX_PKTS) 318 ctl |= CTL_AUTO_RELEASE; 319 else 320 ctl &= ~CTL_AUTO_RELEASE; 321 SMC_SET_CTL(lp, ctl); 322 323 /* Reset the MMU */ 324 SMC_SELECT_BANK(lp, 2); 325 SMC_SET_MMU_CMD(lp, MC_RESET); 326 SMC_WAIT_MMU_BUSY(lp); 327 } 328 329 /* 330 * Enable Interrupts, Receive, and Transmit 331 */ 332 static void smc_enable(struct net_device *dev) 333 { 334 struct smc_local *lp = netdev_priv(dev); 335 void __iomem *ioaddr = lp->base; 336 int mask; 337 338 DBG(2, dev, "%s\n", __func__); 339 340 /* see the header file for options in TCR/RCR DEFAULT */ 341 SMC_SELECT_BANK(lp, 0); 342 SMC_SET_TCR(lp, lp->tcr_cur_mode); 343 SMC_SET_RCR(lp, lp->rcr_cur_mode); 344 345 SMC_SELECT_BANK(lp, 1); 346 SMC_SET_MAC_ADDR(lp, dev->dev_addr); 347 348 /* now, enable interrupts */ 349 mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT; 350 if (lp->version >= (CHIP_91100 << 4)) 351 mask |= IM_MDINT; 352 SMC_SELECT_BANK(lp, 2); 353 SMC_SET_INT_MASK(lp, mask); 354 355 /* 356 * From this point the register bank must _NOT_ be switched away 357 * to something else than bank 2 without proper locking against 358 * races with any tasklet or interrupt handlers until smc_shutdown() 359 * or smc_reset() is called. 360 */ 361 } 362 363 /* 364 * this puts the device in an inactive state 365 */ 366 static void smc_shutdown(struct net_device *dev) 367 { 368 struct smc_local *lp = netdev_priv(dev); 369 void __iomem *ioaddr = lp->base; 370 struct sk_buff *pending_skb; 371 372 DBG(2, dev, "%s: %s\n", CARDNAME, __func__); 373 374 /* no more interrupts for me */ 375 spin_lock_irq(&lp->lock); 376 SMC_SELECT_BANK(lp, 2); 377 SMC_SET_INT_MASK(lp, 0); 378 pending_skb = lp->pending_tx_skb; 379 lp->pending_tx_skb = NULL; 380 spin_unlock_irq(&lp->lock); 381 dev_kfree_skb(pending_skb); 382 383 /* and tell the card to stay away from that nasty outside world */ 384 SMC_SELECT_BANK(lp, 0); 385 SMC_SET_RCR(lp, RCR_CLEAR); 386 SMC_SET_TCR(lp, TCR_CLEAR); 387 388 #ifdef POWER_DOWN 389 /* finally, shut the chip down */ 390 SMC_SELECT_BANK(lp, 1); 391 SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN); 392 #endif 393 } 394 395 /* 396 * This is the procedure to handle the receipt of a packet. 397 */ 398 static inline void smc_rcv(struct net_device *dev) 399 { 400 struct smc_local *lp = netdev_priv(dev); 401 void __iomem *ioaddr = lp->base; 402 unsigned int packet_number, status, packet_len; 403 404 DBG(3, dev, "%s\n", __func__); 405 406 packet_number = SMC_GET_RXFIFO(lp); 407 if (unlikely(packet_number & RXFIFO_REMPTY)) { 408 PRINTK(dev, "smc_rcv with nothing on FIFO.\n"); 409 return; 410 } 411 412 /* read from start of packet */ 413 SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC); 414 415 /* First two words are status and packet length */ 416 SMC_GET_PKT_HDR(lp, status, packet_len); 417 packet_len &= 0x07ff; /* mask off top bits */ 418 DBG(2, dev, "RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n", 419 packet_number, status, packet_len, packet_len); 420 421 back: 422 if (unlikely(packet_len < 6 || status & RS_ERRORS)) { 423 if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) { 424 /* accept VLAN packets */ 425 status &= ~RS_TOOLONG; 426 goto back; 427 } 428 if (packet_len < 6) { 429 /* bloody hardware */ 430 netdev_err(dev, "fubar (rxlen %u status %x\n", 431 packet_len, status); 432 status |= RS_TOOSHORT; 433 } 434 SMC_WAIT_MMU_BUSY(lp); 435 SMC_SET_MMU_CMD(lp, MC_RELEASE); 436 dev->stats.rx_errors++; 437 if (status & RS_ALGNERR) 438 dev->stats.rx_frame_errors++; 439 if (status & (RS_TOOSHORT | RS_TOOLONG)) 440 dev->stats.rx_length_errors++; 441 if (status & RS_BADCRC) 442 dev->stats.rx_crc_errors++; 443 } else { 444 struct sk_buff *skb; 445 unsigned char *data; 446 unsigned int data_len; 447 448 /* set multicast stats */ 449 if (status & RS_MULTICAST) 450 dev->stats.multicast++; 451 452 /* 453 * Actual payload is packet_len - 6 (or 5 if odd byte). 454 * We want skb_reserve(2) and the final ctrl word 455 * (2 bytes, possibly containing the payload odd byte). 456 * Furthermore, we add 2 bytes to allow rounding up to 457 * multiple of 4 bytes on 32 bit buses. 458 * Hence packet_len - 6 + 2 + 2 + 2. 459 */ 460 skb = netdev_alloc_skb(dev, packet_len); 461 if (unlikely(skb == NULL)) { 462 SMC_WAIT_MMU_BUSY(lp); 463 SMC_SET_MMU_CMD(lp, MC_RELEASE); 464 dev->stats.rx_dropped++; 465 return; 466 } 467 468 /* Align IP header to 32 bits */ 469 skb_reserve(skb, 2); 470 471 /* BUG: the LAN91C111 rev A never sets this bit. Force it. */ 472 if (lp->version == 0x90) 473 status |= RS_ODDFRAME; 474 475 /* 476 * If odd length: packet_len - 5, 477 * otherwise packet_len - 6. 478 * With the trailing ctrl byte it's packet_len - 4. 479 */ 480 data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6); 481 data = skb_put(skb, data_len); 482 SMC_PULL_DATA(lp, data, packet_len - 4); 483 484 SMC_WAIT_MMU_BUSY(lp); 485 SMC_SET_MMU_CMD(lp, MC_RELEASE); 486 487 PRINT_PKT(data, packet_len - 4); 488 489 skb->protocol = eth_type_trans(skb, dev); 490 netif_rx(skb); 491 dev->stats.rx_packets++; 492 dev->stats.rx_bytes += data_len; 493 } 494 } 495 496 #ifdef CONFIG_SMP 497 /* 498 * On SMP we have the following problem: 499 * 500 * A = smc_hardware_send_pkt() 501 * B = smc_hard_start_xmit() 502 * C = smc_interrupt() 503 * 504 * A and B can never be executed simultaneously. However, at least on UP, 505 * it is possible (and even desirable) for C to interrupt execution of 506 * A or B in order to have better RX reliability and avoid overruns. 507 * C, just like A and B, must have exclusive access to the chip and 508 * each of them must lock against any other concurrent access. 509 * Unfortunately this is not possible to have C suspend execution of A or 510 * B taking place on another CPU. On UP this is no an issue since A and B 511 * are run from softirq context and C from hard IRQ context, and there is 512 * no other CPU where concurrent access can happen. 513 * If ever there is a way to force at least B and C to always be executed 514 * on the same CPU then we could use read/write locks to protect against 515 * any other concurrent access and C would always interrupt B. But life 516 * isn't that easy in a SMP world... 517 */ 518 #define smc_special_trylock(lock, flags) \ 519 ({ \ 520 int __ret; \ 521 local_irq_save(flags); \ 522 __ret = spin_trylock(lock); \ 523 if (!__ret) \ 524 local_irq_restore(flags); \ 525 __ret; \ 526 }) 527 #define smc_special_lock(lock, flags) spin_lock_irqsave(lock, flags) 528 #define smc_special_unlock(lock, flags) spin_unlock_irqrestore(lock, flags) 529 #else 530 #define smc_special_trylock(lock, flags) ((void)flags, true) 531 #define smc_special_lock(lock, flags) do { flags = 0; } while (0) 532 #define smc_special_unlock(lock, flags) do { flags = 0; } while (0) 533 #endif 534 535 /* 536 * This is called to actually send a packet to the chip. 537 */ 538 static void smc_hardware_send_pkt(unsigned long data) 539 { 540 struct net_device *dev = (struct net_device *)data; 541 struct smc_local *lp = netdev_priv(dev); 542 void __iomem *ioaddr = lp->base; 543 struct sk_buff *skb; 544 unsigned int packet_no, len; 545 unsigned char *buf; 546 unsigned long flags; 547 548 DBG(3, dev, "%s\n", __func__); 549 550 if (!smc_special_trylock(&lp->lock, flags)) { 551 netif_stop_queue(dev); 552 tasklet_schedule(&lp->tx_task); 553 return; 554 } 555 556 skb = lp->pending_tx_skb; 557 if (unlikely(!skb)) { 558 smc_special_unlock(&lp->lock, flags); 559 return; 560 } 561 lp->pending_tx_skb = NULL; 562 563 packet_no = SMC_GET_AR(lp); 564 if (unlikely(packet_no & AR_FAILED)) { 565 netdev_err(dev, "Memory allocation failed.\n"); 566 dev->stats.tx_errors++; 567 dev->stats.tx_fifo_errors++; 568 smc_special_unlock(&lp->lock, flags); 569 goto done; 570 } 571 572 /* point to the beginning of the packet */ 573 SMC_SET_PN(lp, packet_no); 574 SMC_SET_PTR(lp, PTR_AUTOINC); 575 576 buf = skb->data; 577 len = skb->len; 578 DBG(2, dev, "TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n", 579 packet_no, len, len, buf); 580 PRINT_PKT(buf, len); 581 582 /* 583 * Send the packet length (+6 for status words, length, and ctl. 584 * The card will pad to 64 bytes with zeroes if packet is too small. 585 */ 586 SMC_PUT_PKT_HDR(lp, 0, len + 6); 587 588 /* send the actual data */ 589 SMC_PUSH_DATA(lp, buf, len & ~1); 590 591 /* Send final ctl word with the last byte if there is one */ 592 SMC_outw(lp, ((len & 1) ? (0x2000 | buf[len - 1]) : 0), ioaddr, 593 DATA_REG(lp)); 594 595 /* 596 * If THROTTLE_TX_PKTS is set, we stop the queue here. This will 597 * have the effect of having at most one packet queued for TX 598 * in the chip's memory at all time. 599 * 600 * If THROTTLE_TX_PKTS is not set then the queue is stopped only 601 * when memory allocation (MC_ALLOC) does not succeed right away. 602 */ 603 if (THROTTLE_TX_PKTS) 604 netif_stop_queue(dev); 605 606 /* queue the packet for TX */ 607 SMC_SET_MMU_CMD(lp, MC_ENQUEUE); 608 smc_special_unlock(&lp->lock, flags); 609 610 netif_trans_update(dev); 611 dev->stats.tx_packets++; 612 dev->stats.tx_bytes += len; 613 614 SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT); 615 616 done: if (!THROTTLE_TX_PKTS) 617 netif_wake_queue(dev); 618 619 dev_consume_skb_any(skb); 620 } 621 622 /* 623 * Since I am not sure if I will have enough room in the chip's ram 624 * to store the packet, I call this routine which either sends it 625 * now, or set the card to generates an interrupt when ready 626 * for the packet. 627 */ 628 static netdev_tx_t 629 smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) 630 { 631 struct smc_local *lp = netdev_priv(dev); 632 void __iomem *ioaddr = lp->base; 633 unsigned int numPages, poll_count, status; 634 unsigned long flags; 635 636 DBG(3, dev, "%s\n", __func__); 637 638 BUG_ON(lp->pending_tx_skb != NULL); 639 640 /* 641 * The MMU wants the number of pages to be the number of 256 bytes 642 * 'pages', minus 1 (since a packet can't ever have 0 pages :)) 643 * 644 * The 91C111 ignores the size bits, but earlier models don't. 645 * 646 * Pkt size for allocating is data length +6 (for additional status 647 * words, length and ctl) 648 * 649 * If odd size then last byte is included in ctl word. 650 */ 651 numPages = ((skb->len & ~1) + (6 - 1)) >> 8; 652 if (unlikely(numPages > 7)) { 653 netdev_warn(dev, "Far too big packet error.\n"); 654 dev->stats.tx_errors++; 655 dev->stats.tx_dropped++; 656 dev_kfree_skb_any(skb); 657 return NETDEV_TX_OK; 658 } 659 660 smc_special_lock(&lp->lock, flags); 661 662 /* now, try to allocate the memory */ 663 SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages); 664 665 /* 666 * Poll the chip for a short amount of time in case the 667 * allocation succeeds quickly. 668 */ 669 poll_count = MEMORY_WAIT_TIME; 670 do { 671 status = SMC_GET_INT(lp); 672 if (status & IM_ALLOC_INT) { 673 SMC_ACK_INT(lp, IM_ALLOC_INT); 674 break; 675 } 676 } while (--poll_count); 677 678 smc_special_unlock(&lp->lock, flags); 679 680 lp->pending_tx_skb = skb; 681 if (!poll_count) { 682 /* oh well, wait until the chip finds memory later */ 683 netif_stop_queue(dev); 684 DBG(2, dev, "TX memory allocation deferred.\n"); 685 SMC_ENABLE_INT(lp, IM_ALLOC_INT); 686 } else { 687 /* 688 * Allocation succeeded: push packet to the chip's own memory 689 * immediately. 690 */ 691 smc_hardware_send_pkt((unsigned long)dev); 692 } 693 694 return NETDEV_TX_OK; 695 } 696 697 /* 698 * This handles a TX interrupt, which is only called when: 699 * - a TX error occurred, or 700 * - CTL_AUTO_RELEASE is not set and TX of a packet completed. 701 */ 702 static void smc_tx(struct net_device *dev) 703 { 704 struct smc_local *lp = netdev_priv(dev); 705 void __iomem *ioaddr = lp->base; 706 unsigned int saved_packet, packet_no, tx_status, pkt_len; 707 708 DBG(3, dev, "%s\n", __func__); 709 710 /* If the TX FIFO is empty then nothing to do */ 711 packet_no = SMC_GET_TXFIFO(lp); 712 if (unlikely(packet_no & TXFIFO_TEMPTY)) { 713 PRINTK(dev, "smc_tx with nothing on FIFO.\n"); 714 return; 715 } 716 717 /* select packet to read from */ 718 saved_packet = SMC_GET_PN(lp); 719 SMC_SET_PN(lp, packet_no); 720 721 /* read the first word (status word) from this packet */ 722 SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ); 723 SMC_GET_PKT_HDR(lp, tx_status, pkt_len); 724 DBG(2, dev, "TX STATUS 0x%04x PNR 0x%02x\n", 725 tx_status, packet_no); 726 727 if (!(tx_status & ES_TX_SUC)) 728 dev->stats.tx_errors++; 729 730 if (tx_status & ES_LOSTCARR) 731 dev->stats.tx_carrier_errors++; 732 733 if (tx_status & (ES_LATCOL | ES_16COL)) { 734 PRINTK(dev, "%s occurred on last xmit\n", 735 (tx_status & ES_LATCOL) ? 736 "late collision" : "too many collisions"); 737 dev->stats.tx_window_errors++; 738 if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) { 739 netdev_info(dev, "unexpectedly large number of bad collisions. Please check duplex setting.\n"); 740 } 741 } 742 743 /* kill the packet */ 744 SMC_WAIT_MMU_BUSY(lp); 745 SMC_SET_MMU_CMD(lp, MC_FREEPKT); 746 747 /* Don't restore Packet Number Reg until busy bit is cleared */ 748 SMC_WAIT_MMU_BUSY(lp); 749 SMC_SET_PN(lp, saved_packet); 750 751 /* re-enable transmit */ 752 SMC_SELECT_BANK(lp, 0); 753 SMC_SET_TCR(lp, lp->tcr_cur_mode); 754 SMC_SELECT_BANK(lp, 2); 755 } 756 757 758 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ 759 760 static void smc_mii_out(struct net_device *dev, unsigned int val, int bits) 761 { 762 struct smc_local *lp = netdev_priv(dev); 763 void __iomem *ioaddr = lp->base; 764 unsigned int mii_reg, mask; 765 766 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO); 767 mii_reg |= MII_MDOE; 768 769 for (mask = 1 << (bits - 1); mask; mask >>= 1) { 770 if (val & mask) 771 mii_reg |= MII_MDO; 772 else 773 mii_reg &= ~MII_MDO; 774 775 SMC_SET_MII(lp, mii_reg); 776 udelay(MII_DELAY); 777 SMC_SET_MII(lp, mii_reg | MII_MCLK); 778 udelay(MII_DELAY); 779 } 780 } 781 782 static unsigned int smc_mii_in(struct net_device *dev, int bits) 783 { 784 struct smc_local *lp = netdev_priv(dev); 785 void __iomem *ioaddr = lp->base; 786 unsigned int mii_reg, mask, val; 787 788 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO); 789 SMC_SET_MII(lp, mii_reg); 790 791 for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) { 792 if (SMC_GET_MII(lp) & MII_MDI) 793 val |= mask; 794 795 SMC_SET_MII(lp, mii_reg); 796 udelay(MII_DELAY); 797 SMC_SET_MII(lp, mii_reg | MII_MCLK); 798 udelay(MII_DELAY); 799 } 800 801 return val; 802 } 803 804 /* 805 * Reads a register from the MII Management serial interface 806 */ 807 static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg) 808 { 809 struct smc_local *lp = netdev_priv(dev); 810 void __iomem *ioaddr = lp->base; 811 unsigned int phydata; 812 813 SMC_SELECT_BANK(lp, 3); 814 815 /* Idle - 32 ones */ 816 smc_mii_out(dev, 0xffffffff, 32); 817 818 /* Start code (01) + read (10) + phyaddr + phyreg */ 819 smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14); 820 821 /* Turnaround (2bits) + phydata */ 822 phydata = smc_mii_in(dev, 18); 823 824 /* Return to idle state */ 825 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO)); 826 827 DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", 828 __func__, phyaddr, phyreg, phydata); 829 830 SMC_SELECT_BANK(lp, 2); 831 return phydata; 832 } 833 834 /* 835 * Writes a register to the MII Management serial interface 836 */ 837 static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg, 838 int phydata) 839 { 840 struct smc_local *lp = netdev_priv(dev); 841 void __iomem *ioaddr = lp->base; 842 843 SMC_SELECT_BANK(lp, 3); 844 845 /* Idle - 32 ones */ 846 smc_mii_out(dev, 0xffffffff, 32); 847 848 /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */ 849 smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32); 850 851 /* Return to idle state */ 852 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO)); 853 854 DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", 855 __func__, phyaddr, phyreg, phydata); 856 857 SMC_SELECT_BANK(lp, 2); 858 } 859 860 /* 861 * Finds and reports the PHY address 862 */ 863 static void smc_phy_detect(struct net_device *dev) 864 { 865 struct smc_local *lp = netdev_priv(dev); 866 int phyaddr; 867 868 DBG(2, dev, "%s\n", __func__); 869 870 lp->phy_type = 0; 871 872 /* 873 * Scan all 32 PHY addresses if necessary, starting at 874 * PHY#1 to PHY#31, and then PHY#0 last. 875 */ 876 for (phyaddr = 1; phyaddr < 33; ++phyaddr) { 877 unsigned int id1, id2; 878 879 /* Read the PHY identifiers */ 880 id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1); 881 id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2); 882 883 DBG(3, dev, "phy_id1=0x%x, phy_id2=0x%x\n", 884 id1, id2); 885 886 /* Make sure it is a valid identifier */ 887 if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 && 888 id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) { 889 /* Save the PHY's address */ 890 lp->mii.phy_id = phyaddr & 31; 891 lp->phy_type = id1 << 16 | id2; 892 break; 893 } 894 } 895 } 896 897 /* 898 * Sets the PHY to a configuration as determined by the user 899 */ 900 static int smc_phy_fixed(struct net_device *dev) 901 { 902 struct smc_local *lp = netdev_priv(dev); 903 void __iomem *ioaddr = lp->base; 904 int phyaddr = lp->mii.phy_id; 905 int bmcr, cfg1; 906 907 DBG(3, dev, "%s\n", __func__); 908 909 /* Enter Link Disable state */ 910 cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG); 911 cfg1 |= PHY_CFG1_LNKDIS; 912 smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1); 913 914 /* 915 * Set our fixed capabilities 916 * Disable auto-negotiation 917 */ 918 bmcr = 0; 919 920 if (lp->ctl_rfduplx) 921 bmcr |= BMCR_FULLDPLX; 922 923 if (lp->ctl_rspeed == 100) 924 bmcr |= BMCR_SPEED100; 925 926 /* Write our capabilities to the phy control register */ 927 smc_phy_write(dev, phyaddr, MII_BMCR, bmcr); 928 929 /* Re-Configure the Receive/Phy Control register */ 930 SMC_SELECT_BANK(lp, 0); 931 SMC_SET_RPC(lp, lp->rpc_cur_mode); 932 SMC_SELECT_BANK(lp, 2); 933 934 return 1; 935 } 936 937 /** 938 * smc_phy_reset - reset the phy 939 * @dev: net device 940 * @phy: phy address 941 * 942 * Issue a software reset for the specified PHY and 943 * wait up to 100ms for the reset to complete. We should 944 * not access the PHY for 50ms after issuing the reset. 945 * 946 * The time to wait appears to be dependent on the PHY. 947 * 948 * Must be called with lp->lock locked. 949 */ 950 static int smc_phy_reset(struct net_device *dev, int phy) 951 { 952 struct smc_local *lp = netdev_priv(dev); 953 unsigned int bmcr; 954 int timeout; 955 956 smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET); 957 958 for (timeout = 2; timeout; timeout--) { 959 spin_unlock_irq(&lp->lock); 960 msleep(50); 961 spin_lock_irq(&lp->lock); 962 963 bmcr = smc_phy_read(dev, phy, MII_BMCR); 964 if (!(bmcr & BMCR_RESET)) 965 break; 966 } 967 968 return bmcr & BMCR_RESET; 969 } 970 971 /** 972 * smc_phy_powerdown - powerdown phy 973 * @dev: net device 974 * 975 * Power down the specified PHY 976 */ 977 static void smc_phy_powerdown(struct net_device *dev) 978 { 979 struct smc_local *lp = netdev_priv(dev); 980 unsigned int bmcr; 981 int phy = lp->mii.phy_id; 982 983 if (lp->phy_type == 0) 984 return; 985 986 /* We need to ensure that no calls to smc_phy_configure are 987 pending. 988 */ 989 cancel_work_sync(&lp->phy_configure); 990 991 bmcr = smc_phy_read(dev, phy, MII_BMCR); 992 smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN); 993 } 994 995 /** 996 * smc_phy_check_media - check the media status and adjust TCR 997 * @dev: net device 998 * @init: set true for initialisation 999 * 1000 * Select duplex mode depending on negotiation state. This 1001 * also updates our carrier state. 1002 */ 1003 static void smc_phy_check_media(struct net_device *dev, int init) 1004 { 1005 struct smc_local *lp = netdev_priv(dev); 1006 void __iomem *ioaddr = lp->base; 1007 1008 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) { 1009 /* duplex state has changed */ 1010 if (lp->mii.full_duplex) { 1011 lp->tcr_cur_mode |= TCR_SWFDUP; 1012 } else { 1013 lp->tcr_cur_mode &= ~TCR_SWFDUP; 1014 } 1015 1016 SMC_SELECT_BANK(lp, 0); 1017 SMC_SET_TCR(lp, lp->tcr_cur_mode); 1018 } 1019 } 1020 1021 /* 1022 * Configures the specified PHY through the MII management interface 1023 * using Autonegotiation. 1024 * Calls smc_phy_fixed() if the user has requested a certain config. 1025 * If RPC ANEG bit is set, the media selection is dependent purely on 1026 * the selection by the MII (either in the MII BMCR reg or the result 1027 * of autonegotiation.) If the RPC ANEG bit is cleared, the selection 1028 * is controlled by the RPC SPEED and RPC DPLX bits. 1029 */ 1030 static void smc_phy_configure(struct work_struct *work) 1031 { 1032 struct smc_local *lp = 1033 container_of(work, struct smc_local, phy_configure); 1034 struct net_device *dev = lp->dev; 1035 void __iomem *ioaddr = lp->base; 1036 int phyaddr = lp->mii.phy_id; 1037 int my_phy_caps; /* My PHY capabilities */ 1038 int my_ad_caps; /* My Advertised capabilities */ 1039 int status; 1040 1041 DBG(3, dev, "smc_program_phy()\n"); 1042 1043 spin_lock_irq(&lp->lock); 1044 1045 /* 1046 * We should not be called if phy_type is zero. 1047 */ 1048 if (lp->phy_type == 0) 1049 goto smc_phy_configure_exit; 1050 1051 if (smc_phy_reset(dev, phyaddr)) { 1052 netdev_info(dev, "PHY reset timed out\n"); 1053 goto smc_phy_configure_exit; 1054 } 1055 1056 /* 1057 * Enable PHY Interrupts (for register 18) 1058 * Interrupts listed here are disabled 1059 */ 1060 smc_phy_write(dev, phyaddr, PHY_MASK_REG, 1061 PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD | 1062 PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB | 1063 PHY_INT_SPDDET | PHY_INT_DPLXDET); 1064 1065 /* Configure the Receive/Phy Control register */ 1066 SMC_SELECT_BANK(lp, 0); 1067 SMC_SET_RPC(lp, lp->rpc_cur_mode); 1068 1069 /* If the user requested no auto neg, then go set his request */ 1070 if (lp->mii.force_media) { 1071 smc_phy_fixed(dev); 1072 goto smc_phy_configure_exit; 1073 } 1074 1075 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */ 1076 my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR); 1077 1078 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) { 1079 netdev_info(dev, "Auto negotiation NOT supported\n"); 1080 smc_phy_fixed(dev); 1081 goto smc_phy_configure_exit; 1082 } 1083 1084 my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */ 1085 1086 if (my_phy_caps & BMSR_100BASE4) 1087 my_ad_caps |= ADVERTISE_100BASE4; 1088 if (my_phy_caps & BMSR_100FULL) 1089 my_ad_caps |= ADVERTISE_100FULL; 1090 if (my_phy_caps & BMSR_100HALF) 1091 my_ad_caps |= ADVERTISE_100HALF; 1092 if (my_phy_caps & BMSR_10FULL) 1093 my_ad_caps |= ADVERTISE_10FULL; 1094 if (my_phy_caps & BMSR_10HALF) 1095 my_ad_caps |= ADVERTISE_10HALF; 1096 1097 /* Disable capabilities not selected by our user */ 1098 if (lp->ctl_rspeed != 100) 1099 my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF); 1100 1101 if (!lp->ctl_rfduplx) 1102 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL); 1103 1104 /* Update our Auto-Neg Advertisement Register */ 1105 smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps); 1106 lp->mii.advertising = my_ad_caps; 1107 1108 /* 1109 * Read the register back. Without this, it appears that when 1110 * auto-negotiation is restarted, sometimes it isn't ready and 1111 * the link does not come up. 1112 */ 1113 status = smc_phy_read(dev, phyaddr, MII_ADVERTISE); 1114 1115 DBG(2, dev, "phy caps=%x\n", my_phy_caps); 1116 DBG(2, dev, "phy advertised caps=%x\n", my_ad_caps); 1117 1118 /* Restart auto-negotiation process in order to advertise my caps */ 1119 smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); 1120 1121 smc_phy_check_media(dev, 1); 1122 1123 smc_phy_configure_exit: 1124 SMC_SELECT_BANK(lp, 2); 1125 spin_unlock_irq(&lp->lock); 1126 } 1127 1128 /* 1129 * smc_phy_interrupt 1130 * 1131 * Purpose: Handle interrupts relating to PHY register 18. This is 1132 * called from the "hard" interrupt handler under our private spinlock. 1133 */ 1134 static void smc_phy_interrupt(struct net_device *dev) 1135 { 1136 struct smc_local *lp = netdev_priv(dev); 1137 int phyaddr = lp->mii.phy_id; 1138 int phy18; 1139 1140 DBG(2, dev, "%s\n", __func__); 1141 1142 if (lp->phy_type == 0) 1143 return; 1144 1145 for(;;) { 1146 smc_phy_check_media(dev, 0); 1147 1148 /* Read PHY Register 18, Status Output */ 1149 phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG); 1150 if ((phy18 & PHY_INT_INT) == 0) 1151 break; 1152 } 1153 } 1154 1155 /*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/ 1156 1157 static void smc_10bt_check_media(struct net_device *dev, int init) 1158 { 1159 struct smc_local *lp = netdev_priv(dev); 1160 void __iomem *ioaddr = lp->base; 1161 unsigned int old_carrier, new_carrier; 1162 1163 old_carrier = netif_carrier_ok(dev) ? 1 : 0; 1164 1165 SMC_SELECT_BANK(lp, 0); 1166 new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0; 1167 SMC_SELECT_BANK(lp, 2); 1168 1169 if (init || (old_carrier != new_carrier)) { 1170 if (!new_carrier) { 1171 netif_carrier_off(dev); 1172 } else { 1173 netif_carrier_on(dev); 1174 } 1175 if (netif_msg_link(lp)) 1176 netdev_info(dev, "link %s\n", 1177 new_carrier ? "up" : "down"); 1178 } 1179 } 1180 1181 static void smc_eph_interrupt(struct net_device *dev) 1182 { 1183 struct smc_local *lp = netdev_priv(dev); 1184 void __iomem *ioaddr = lp->base; 1185 unsigned int ctl; 1186 1187 smc_10bt_check_media(dev, 0); 1188 1189 SMC_SELECT_BANK(lp, 1); 1190 ctl = SMC_GET_CTL(lp); 1191 SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE); 1192 SMC_SET_CTL(lp, ctl); 1193 SMC_SELECT_BANK(lp, 2); 1194 } 1195 1196 /* 1197 * This is the main routine of the driver, to handle the device when 1198 * it needs some attention. 1199 */ 1200 static irqreturn_t smc_interrupt(int irq, void *dev_id) 1201 { 1202 struct net_device *dev = dev_id; 1203 struct smc_local *lp = netdev_priv(dev); 1204 void __iomem *ioaddr = lp->base; 1205 int status, mask, timeout, card_stats; 1206 int saved_pointer; 1207 1208 DBG(3, dev, "%s\n", __func__); 1209 1210 spin_lock(&lp->lock); 1211 1212 /* A preamble may be used when there is a potential race 1213 * between the interruptible transmit functions and this 1214 * ISR. */ 1215 SMC_INTERRUPT_PREAMBLE; 1216 1217 saved_pointer = SMC_GET_PTR(lp); 1218 mask = SMC_GET_INT_MASK(lp); 1219 SMC_SET_INT_MASK(lp, 0); 1220 1221 /* set a timeout value, so I don't stay here forever */ 1222 timeout = MAX_IRQ_LOOPS; 1223 1224 do { 1225 status = SMC_GET_INT(lp); 1226 1227 DBG(2, dev, "INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n", 1228 status, mask, 1229 ({ int meminfo; SMC_SELECT_BANK(lp, 0); 1230 meminfo = SMC_GET_MIR(lp); 1231 SMC_SELECT_BANK(lp, 2); meminfo; }), 1232 SMC_GET_FIFO(lp)); 1233 1234 status &= mask; 1235 if (!status) 1236 break; 1237 1238 if (status & IM_TX_INT) { 1239 /* do this before RX as it will free memory quickly */ 1240 DBG(3, dev, "TX int\n"); 1241 smc_tx(dev); 1242 SMC_ACK_INT(lp, IM_TX_INT); 1243 if (THROTTLE_TX_PKTS) 1244 netif_wake_queue(dev); 1245 } else if (status & IM_RCV_INT) { 1246 DBG(3, dev, "RX irq\n"); 1247 smc_rcv(dev); 1248 } else if (status & IM_ALLOC_INT) { 1249 DBG(3, dev, "Allocation irq\n"); 1250 tasklet_hi_schedule(&lp->tx_task); 1251 mask &= ~IM_ALLOC_INT; 1252 } else if (status & IM_TX_EMPTY_INT) { 1253 DBG(3, dev, "TX empty\n"); 1254 mask &= ~IM_TX_EMPTY_INT; 1255 1256 /* update stats */ 1257 SMC_SELECT_BANK(lp, 0); 1258 card_stats = SMC_GET_COUNTER(lp); 1259 SMC_SELECT_BANK(lp, 2); 1260 1261 /* single collisions */ 1262 dev->stats.collisions += card_stats & 0xF; 1263 card_stats >>= 4; 1264 1265 /* multiple collisions */ 1266 dev->stats.collisions += card_stats & 0xF; 1267 } else if (status & IM_RX_OVRN_INT) { 1268 DBG(1, dev, "RX overrun (EPH_ST 0x%04x)\n", 1269 ({ int eph_st; SMC_SELECT_BANK(lp, 0); 1270 eph_st = SMC_GET_EPH_STATUS(lp); 1271 SMC_SELECT_BANK(lp, 2); eph_st; })); 1272 SMC_ACK_INT(lp, IM_RX_OVRN_INT); 1273 dev->stats.rx_errors++; 1274 dev->stats.rx_fifo_errors++; 1275 } else if (status & IM_EPH_INT) { 1276 smc_eph_interrupt(dev); 1277 } else if (status & IM_MDINT) { 1278 SMC_ACK_INT(lp, IM_MDINT); 1279 smc_phy_interrupt(dev); 1280 } else if (status & IM_ERCV_INT) { 1281 SMC_ACK_INT(lp, IM_ERCV_INT); 1282 PRINTK(dev, "UNSUPPORTED: ERCV INTERRUPT\n"); 1283 } 1284 } while (--timeout); 1285 1286 /* restore register states */ 1287 SMC_SET_PTR(lp, saved_pointer); 1288 SMC_SET_INT_MASK(lp, mask); 1289 spin_unlock(&lp->lock); 1290 1291 #ifndef CONFIG_NET_POLL_CONTROLLER 1292 if (timeout == MAX_IRQ_LOOPS) 1293 PRINTK(dev, "spurious interrupt (mask = 0x%02x)\n", 1294 mask); 1295 #endif 1296 DBG(3, dev, "Interrupt done (%d loops)\n", 1297 MAX_IRQ_LOOPS - timeout); 1298 1299 /* 1300 * We return IRQ_HANDLED unconditionally here even if there was 1301 * nothing to do. There is a possibility that a packet might 1302 * get enqueued into the chip right after TX_EMPTY_INT is raised 1303 * but just before the CPU acknowledges the IRQ. 1304 * Better take an unneeded IRQ in some occasions than complexifying 1305 * the code for all cases. 1306 */ 1307 return IRQ_HANDLED; 1308 } 1309 1310 #ifdef CONFIG_NET_POLL_CONTROLLER 1311 /* 1312 * Polling receive - used by netconsole and other diagnostic tools 1313 * to allow network i/o with interrupts disabled. 1314 */ 1315 static void smc_poll_controller(struct net_device *dev) 1316 { 1317 disable_irq(dev->irq); 1318 smc_interrupt(dev->irq, dev); 1319 enable_irq(dev->irq); 1320 } 1321 #endif 1322 1323 /* Our watchdog timed out. Called by the networking layer */ 1324 static void smc_timeout(struct net_device *dev) 1325 { 1326 struct smc_local *lp = netdev_priv(dev); 1327 void __iomem *ioaddr = lp->base; 1328 int status, mask, eph_st, meminfo, fifo; 1329 1330 DBG(2, dev, "%s\n", __func__); 1331 1332 spin_lock_irq(&lp->lock); 1333 status = SMC_GET_INT(lp); 1334 mask = SMC_GET_INT_MASK(lp); 1335 fifo = SMC_GET_FIFO(lp); 1336 SMC_SELECT_BANK(lp, 0); 1337 eph_st = SMC_GET_EPH_STATUS(lp); 1338 meminfo = SMC_GET_MIR(lp); 1339 SMC_SELECT_BANK(lp, 2); 1340 spin_unlock_irq(&lp->lock); 1341 PRINTK(dev, "TX timeout (INT 0x%02x INTMASK 0x%02x MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n", 1342 status, mask, meminfo, fifo, eph_st); 1343 1344 smc_reset(dev); 1345 smc_enable(dev); 1346 1347 /* 1348 * Reconfiguring the PHY doesn't seem like a bad idea here, but 1349 * smc_phy_configure() calls msleep() which calls schedule_timeout() 1350 * which calls schedule(). Hence we use a work queue. 1351 */ 1352 if (lp->phy_type != 0) 1353 schedule_work(&lp->phy_configure); 1354 1355 /* We can accept TX packets again */ 1356 netif_trans_update(dev); /* prevent tx timeout */ 1357 netif_wake_queue(dev); 1358 } 1359 1360 /* 1361 * This routine will, depending on the values passed to it, 1362 * either make it accept multicast packets, go into 1363 * promiscuous mode (for TCPDUMP and cousins) or accept 1364 * a select set of multicast packets 1365 */ 1366 static void smc_set_multicast_list(struct net_device *dev) 1367 { 1368 struct smc_local *lp = netdev_priv(dev); 1369 void __iomem *ioaddr = lp->base; 1370 unsigned char multicast_table[8]; 1371 int update_multicast = 0; 1372 1373 DBG(2, dev, "%s\n", __func__); 1374 1375 if (dev->flags & IFF_PROMISC) { 1376 DBG(2, dev, "RCR_PRMS\n"); 1377 lp->rcr_cur_mode |= RCR_PRMS; 1378 } 1379 1380 /* BUG? I never disable promiscuous mode if multicasting was turned on. 1381 Now, I turn off promiscuous mode, but I don't do anything to multicasting 1382 when promiscuous mode is turned on. 1383 */ 1384 1385 /* 1386 * Here, I am setting this to accept all multicast packets. 1387 * I don't need to zero the multicast table, because the flag is 1388 * checked before the table is 1389 */ 1390 else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) { 1391 DBG(2, dev, "RCR_ALMUL\n"); 1392 lp->rcr_cur_mode |= RCR_ALMUL; 1393 } 1394 1395 /* 1396 * This sets the internal hardware table to filter out unwanted 1397 * multicast packets before they take up memory. 1398 * 1399 * The SMC chip uses a hash table where the high 6 bits of the CRC of 1400 * address are the offset into the table. If that bit is 1, then the 1401 * multicast packet is accepted. Otherwise, it's dropped silently. 1402 * 1403 * To use the 6 bits as an offset into the table, the high 3 bits are 1404 * the number of the 8 bit register, while the low 3 bits are the bit 1405 * within that register. 1406 */ 1407 else if (!netdev_mc_empty(dev)) { 1408 struct netdev_hw_addr *ha; 1409 1410 /* table for flipping the order of 3 bits */ 1411 static const unsigned char invert3[] = {0, 4, 2, 6, 1, 5, 3, 7}; 1412 1413 /* start with a table of all zeros: reject all */ 1414 memset(multicast_table, 0, sizeof(multicast_table)); 1415 1416 netdev_for_each_mc_addr(ha, dev) { 1417 int position; 1418 1419 /* only use the low order bits */ 1420 position = crc32_le(~0, ha->addr, 6) & 0x3f; 1421 1422 /* do some messy swapping to put the bit in the right spot */ 1423 multicast_table[invert3[position&7]] |= 1424 (1<<invert3[(position>>3)&7]); 1425 } 1426 1427 /* be sure I get rid of flags I might have set */ 1428 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); 1429 1430 /* now, the table can be loaded into the chipset */ 1431 update_multicast = 1; 1432 } else { 1433 DBG(2, dev, "~(RCR_PRMS|RCR_ALMUL)\n"); 1434 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); 1435 1436 /* 1437 * since I'm disabling all multicast entirely, I need to 1438 * clear the multicast list 1439 */ 1440 memset(multicast_table, 0, sizeof(multicast_table)); 1441 update_multicast = 1; 1442 } 1443 1444 spin_lock_irq(&lp->lock); 1445 SMC_SELECT_BANK(lp, 0); 1446 SMC_SET_RCR(lp, lp->rcr_cur_mode); 1447 if (update_multicast) { 1448 SMC_SELECT_BANK(lp, 3); 1449 SMC_SET_MCAST(lp, multicast_table); 1450 } 1451 SMC_SELECT_BANK(lp, 2); 1452 spin_unlock_irq(&lp->lock); 1453 } 1454 1455 1456 /* 1457 * Open and Initialize the board 1458 * 1459 * Set up everything, reset the card, etc.. 1460 */ 1461 static int 1462 smc_open(struct net_device *dev) 1463 { 1464 struct smc_local *lp = netdev_priv(dev); 1465 1466 DBG(2, dev, "%s\n", __func__); 1467 1468 /* Setup the default Register Modes */ 1469 lp->tcr_cur_mode = TCR_DEFAULT; 1470 lp->rcr_cur_mode = RCR_DEFAULT; 1471 lp->rpc_cur_mode = RPC_DEFAULT | 1472 lp->cfg.leda << RPC_LSXA_SHFT | 1473 lp->cfg.ledb << RPC_LSXB_SHFT; 1474 1475 /* 1476 * If we are not using a MII interface, we need to 1477 * monitor our own carrier signal to detect faults. 1478 */ 1479 if (lp->phy_type == 0) 1480 lp->tcr_cur_mode |= TCR_MON_CSN; 1481 1482 /* reset the hardware */ 1483 smc_reset(dev); 1484 smc_enable(dev); 1485 1486 /* Configure the PHY, initialize the link state */ 1487 if (lp->phy_type != 0) 1488 smc_phy_configure(&lp->phy_configure); 1489 else { 1490 spin_lock_irq(&lp->lock); 1491 smc_10bt_check_media(dev, 1); 1492 spin_unlock_irq(&lp->lock); 1493 } 1494 1495 netif_start_queue(dev); 1496 return 0; 1497 } 1498 1499 /* 1500 * smc_close 1501 * 1502 * this makes the board clean up everything that it can 1503 * and not talk to the outside world. Caused by 1504 * an 'ifconfig ethX down' 1505 */ 1506 static int smc_close(struct net_device *dev) 1507 { 1508 struct smc_local *lp = netdev_priv(dev); 1509 1510 DBG(2, dev, "%s\n", __func__); 1511 1512 netif_stop_queue(dev); 1513 netif_carrier_off(dev); 1514 1515 /* clear everything */ 1516 smc_shutdown(dev); 1517 tasklet_kill(&lp->tx_task); 1518 smc_phy_powerdown(dev); 1519 return 0; 1520 } 1521 1522 /* 1523 * Ethtool support 1524 */ 1525 static int 1526 smc_ethtool_get_link_ksettings(struct net_device *dev, 1527 struct ethtool_link_ksettings *cmd) 1528 { 1529 struct smc_local *lp = netdev_priv(dev); 1530 1531 if (lp->phy_type != 0) { 1532 spin_lock_irq(&lp->lock); 1533 mii_ethtool_get_link_ksettings(&lp->mii, cmd); 1534 spin_unlock_irq(&lp->lock); 1535 } else { 1536 u32 supported = SUPPORTED_10baseT_Half | 1537 SUPPORTED_10baseT_Full | 1538 SUPPORTED_TP | SUPPORTED_AUI; 1539 1540 if (lp->ctl_rspeed == 10) 1541 cmd->base.speed = SPEED_10; 1542 else if (lp->ctl_rspeed == 100) 1543 cmd->base.speed = SPEED_100; 1544 1545 cmd->base.autoneg = AUTONEG_DISABLE; 1546 cmd->base.port = 0; 1547 cmd->base.duplex = lp->tcr_cur_mode & TCR_SWFDUP ? 1548 DUPLEX_FULL : DUPLEX_HALF; 1549 1550 ethtool_convert_legacy_u32_to_link_mode( 1551 cmd->link_modes.supported, supported); 1552 } 1553 1554 return 0; 1555 } 1556 1557 static int 1558 smc_ethtool_set_link_ksettings(struct net_device *dev, 1559 const struct ethtool_link_ksettings *cmd) 1560 { 1561 struct smc_local *lp = netdev_priv(dev); 1562 int ret; 1563 1564 if (lp->phy_type != 0) { 1565 spin_lock_irq(&lp->lock); 1566 ret = mii_ethtool_set_link_ksettings(&lp->mii, cmd); 1567 spin_unlock_irq(&lp->lock); 1568 } else { 1569 if (cmd->base.autoneg != AUTONEG_DISABLE || 1570 cmd->base.speed != SPEED_10 || 1571 (cmd->base.duplex != DUPLEX_HALF && 1572 cmd->base.duplex != DUPLEX_FULL) || 1573 (cmd->base.port != PORT_TP && cmd->base.port != PORT_AUI)) 1574 return -EINVAL; 1575 1576 // lp->port = cmd->base.port; 1577 lp->ctl_rfduplx = cmd->base.duplex == DUPLEX_FULL; 1578 1579 // if (netif_running(dev)) 1580 // smc_set_port(dev); 1581 1582 ret = 0; 1583 } 1584 1585 return ret; 1586 } 1587 1588 static void 1589 smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1590 { 1591 strlcpy(info->driver, CARDNAME, sizeof(info->driver)); 1592 strlcpy(info->version, version, sizeof(info->version)); 1593 strlcpy(info->bus_info, dev_name(dev->dev.parent), 1594 sizeof(info->bus_info)); 1595 } 1596 1597 static int smc_ethtool_nwayreset(struct net_device *dev) 1598 { 1599 struct smc_local *lp = netdev_priv(dev); 1600 int ret = -EINVAL; 1601 1602 if (lp->phy_type != 0) { 1603 spin_lock_irq(&lp->lock); 1604 ret = mii_nway_restart(&lp->mii); 1605 spin_unlock_irq(&lp->lock); 1606 } 1607 1608 return ret; 1609 } 1610 1611 static u32 smc_ethtool_getmsglevel(struct net_device *dev) 1612 { 1613 struct smc_local *lp = netdev_priv(dev); 1614 return lp->msg_enable; 1615 } 1616 1617 static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level) 1618 { 1619 struct smc_local *lp = netdev_priv(dev); 1620 lp->msg_enable = level; 1621 } 1622 1623 static int smc_write_eeprom_word(struct net_device *dev, u16 addr, u16 word) 1624 { 1625 u16 ctl; 1626 struct smc_local *lp = netdev_priv(dev); 1627 void __iomem *ioaddr = lp->base; 1628 1629 spin_lock_irq(&lp->lock); 1630 /* load word into GP register */ 1631 SMC_SELECT_BANK(lp, 1); 1632 SMC_SET_GP(lp, word); 1633 /* set the address to put the data in EEPROM */ 1634 SMC_SELECT_BANK(lp, 2); 1635 SMC_SET_PTR(lp, addr); 1636 /* tell it to write */ 1637 SMC_SELECT_BANK(lp, 1); 1638 ctl = SMC_GET_CTL(lp); 1639 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE)); 1640 /* wait for it to finish */ 1641 do { 1642 udelay(1); 1643 } while (SMC_GET_CTL(lp) & CTL_STORE); 1644 /* clean up */ 1645 SMC_SET_CTL(lp, ctl); 1646 SMC_SELECT_BANK(lp, 2); 1647 spin_unlock_irq(&lp->lock); 1648 return 0; 1649 } 1650 1651 static int smc_read_eeprom_word(struct net_device *dev, u16 addr, u16 *word) 1652 { 1653 u16 ctl; 1654 struct smc_local *lp = netdev_priv(dev); 1655 void __iomem *ioaddr = lp->base; 1656 1657 spin_lock_irq(&lp->lock); 1658 /* set the EEPROM address to get the data from */ 1659 SMC_SELECT_BANK(lp, 2); 1660 SMC_SET_PTR(lp, addr | PTR_READ); 1661 /* tell it to load */ 1662 SMC_SELECT_BANK(lp, 1); 1663 SMC_SET_GP(lp, 0xffff); /* init to known */ 1664 ctl = SMC_GET_CTL(lp); 1665 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD)); 1666 /* wait for it to finish */ 1667 do { 1668 udelay(1); 1669 } while (SMC_GET_CTL(lp) & CTL_RELOAD); 1670 /* read word from GP register */ 1671 *word = SMC_GET_GP(lp); 1672 /* clean up */ 1673 SMC_SET_CTL(lp, ctl); 1674 SMC_SELECT_BANK(lp, 2); 1675 spin_unlock_irq(&lp->lock); 1676 return 0; 1677 } 1678 1679 static int smc_ethtool_geteeprom_len(struct net_device *dev) 1680 { 1681 return 0x23 * 2; 1682 } 1683 1684 static int smc_ethtool_geteeprom(struct net_device *dev, 1685 struct ethtool_eeprom *eeprom, u8 *data) 1686 { 1687 int i; 1688 int imax; 1689 1690 DBG(1, dev, "Reading %d bytes at %d(0x%x)\n", 1691 eeprom->len, eeprom->offset, eeprom->offset); 1692 imax = smc_ethtool_geteeprom_len(dev); 1693 for (i = 0; i < eeprom->len; i += 2) { 1694 int ret; 1695 u16 wbuf; 1696 int offset = i + eeprom->offset; 1697 if (offset > imax) 1698 break; 1699 ret = smc_read_eeprom_word(dev, offset >> 1, &wbuf); 1700 if (ret != 0) 1701 return ret; 1702 DBG(2, dev, "Read 0x%x from 0x%x\n", wbuf, offset >> 1); 1703 data[i] = (wbuf >> 8) & 0xff; 1704 data[i+1] = wbuf & 0xff; 1705 } 1706 return 0; 1707 } 1708 1709 static int smc_ethtool_seteeprom(struct net_device *dev, 1710 struct ethtool_eeprom *eeprom, u8 *data) 1711 { 1712 int i; 1713 int imax; 1714 1715 DBG(1, dev, "Writing %d bytes to %d(0x%x)\n", 1716 eeprom->len, eeprom->offset, eeprom->offset); 1717 imax = smc_ethtool_geteeprom_len(dev); 1718 for (i = 0; i < eeprom->len; i += 2) { 1719 int ret; 1720 u16 wbuf; 1721 int offset = i + eeprom->offset; 1722 if (offset > imax) 1723 break; 1724 wbuf = (data[i] << 8) | data[i + 1]; 1725 DBG(2, dev, "Writing 0x%x to 0x%x\n", wbuf, offset >> 1); 1726 ret = smc_write_eeprom_word(dev, offset >> 1, wbuf); 1727 if (ret != 0) 1728 return ret; 1729 } 1730 return 0; 1731 } 1732 1733 1734 static const struct ethtool_ops smc_ethtool_ops = { 1735 .get_drvinfo = smc_ethtool_getdrvinfo, 1736 1737 .get_msglevel = smc_ethtool_getmsglevel, 1738 .set_msglevel = smc_ethtool_setmsglevel, 1739 .nway_reset = smc_ethtool_nwayreset, 1740 .get_link = ethtool_op_get_link, 1741 .get_eeprom_len = smc_ethtool_geteeprom_len, 1742 .get_eeprom = smc_ethtool_geteeprom, 1743 .set_eeprom = smc_ethtool_seteeprom, 1744 .get_link_ksettings = smc_ethtool_get_link_ksettings, 1745 .set_link_ksettings = smc_ethtool_set_link_ksettings, 1746 }; 1747 1748 static const struct net_device_ops smc_netdev_ops = { 1749 .ndo_open = smc_open, 1750 .ndo_stop = smc_close, 1751 .ndo_start_xmit = smc_hard_start_xmit, 1752 .ndo_tx_timeout = smc_timeout, 1753 .ndo_set_rx_mode = smc_set_multicast_list, 1754 .ndo_validate_addr = eth_validate_addr, 1755 .ndo_set_mac_address = eth_mac_addr, 1756 #ifdef CONFIG_NET_POLL_CONTROLLER 1757 .ndo_poll_controller = smc_poll_controller, 1758 #endif 1759 }; 1760 1761 /* 1762 * smc_findirq 1763 * 1764 * This routine has a simple purpose -- make the SMC chip generate an 1765 * interrupt, so an auto-detect routine can detect it, and find the IRQ, 1766 */ 1767 /* 1768 * does this still work? 1769 * 1770 * I just deleted auto_irq.c, since it was never built... 1771 * --jgarzik 1772 */ 1773 static int smc_findirq(struct smc_local *lp) 1774 { 1775 void __iomem *ioaddr = lp->base; 1776 int timeout = 20; 1777 unsigned long cookie; 1778 1779 DBG(2, lp->dev, "%s: %s\n", CARDNAME, __func__); 1780 1781 cookie = probe_irq_on(); 1782 1783 /* 1784 * What I try to do here is trigger an ALLOC_INT. This is done 1785 * by allocating a small chunk of memory, which will give an interrupt 1786 * when done. 1787 */ 1788 /* enable ALLOCation interrupts ONLY */ 1789 SMC_SELECT_BANK(lp, 2); 1790 SMC_SET_INT_MASK(lp, IM_ALLOC_INT); 1791 1792 /* 1793 * Allocate 512 bytes of memory. Note that the chip was just 1794 * reset so all the memory is available 1795 */ 1796 SMC_SET_MMU_CMD(lp, MC_ALLOC | 1); 1797 1798 /* 1799 * Wait until positive that the interrupt has been generated 1800 */ 1801 do { 1802 int int_status; 1803 udelay(10); 1804 int_status = SMC_GET_INT(lp); 1805 if (int_status & IM_ALLOC_INT) 1806 break; /* got the interrupt */ 1807 } while (--timeout); 1808 1809 /* 1810 * there is really nothing that I can do here if timeout fails, 1811 * as autoirq_report will return a 0 anyway, which is what I 1812 * want in this case. Plus, the clean up is needed in both 1813 * cases. 1814 */ 1815 1816 /* and disable all interrupts again */ 1817 SMC_SET_INT_MASK(lp, 0); 1818 1819 /* and return what I found */ 1820 return probe_irq_off(cookie); 1821 } 1822 1823 /* 1824 * Function: smc_probe(unsigned long ioaddr) 1825 * 1826 * Purpose: 1827 * Tests to see if a given ioaddr points to an SMC91x chip. 1828 * Returns a 0 on success 1829 * 1830 * Algorithm: 1831 * (1) see if the high byte of BANK_SELECT is 0x33 1832 * (2) compare the ioaddr with the base register's address 1833 * (3) see if I recognize the chip ID in the appropriate register 1834 * 1835 * Here I do typical initialization tasks. 1836 * 1837 * o Initialize the structure if needed 1838 * o print out my vanity message if not done so already 1839 * o print out what type of hardware is detected 1840 * o print out the ethernet address 1841 * o find the IRQ 1842 * o set up my private data 1843 * o configure the dev structure with my subroutines 1844 * o actually GRAB the irq. 1845 * o GRAB the region 1846 */ 1847 static int smc_probe(struct net_device *dev, void __iomem *ioaddr, 1848 unsigned long irq_flags) 1849 { 1850 struct smc_local *lp = netdev_priv(dev); 1851 int retval; 1852 unsigned int val, revision_register; 1853 const char *version_string; 1854 1855 DBG(2, dev, "%s: %s\n", CARDNAME, __func__); 1856 1857 /* First, see if the high byte is 0x33 */ 1858 val = SMC_CURRENT_BANK(lp); 1859 DBG(2, dev, "%s: bank signature probe returned 0x%04x\n", 1860 CARDNAME, val); 1861 if ((val & 0xFF00) != 0x3300) { 1862 if ((val & 0xFF) == 0x33) { 1863 netdev_warn(dev, 1864 "%s: Detected possible byte-swapped interface at IOADDR %p\n", 1865 CARDNAME, ioaddr); 1866 } 1867 retval = -ENODEV; 1868 goto err_out; 1869 } 1870 1871 /* 1872 * The above MIGHT indicate a device, but I need to write to 1873 * further test this. 1874 */ 1875 SMC_SELECT_BANK(lp, 0); 1876 val = SMC_CURRENT_BANK(lp); 1877 if ((val & 0xFF00) != 0x3300) { 1878 retval = -ENODEV; 1879 goto err_out; 1880 } 1881 1882 /* 1883 * well, we've already written once, so hopefully another 1884 * time won't hurt. This time, I need to switch the bank 1885 * register to bank 1, so I can access the base address 1886 * register 1887 */ 1888 SMC_SELECT_BANK(lp, 1); 1889 val = SMC_GET_BASE(lp); 1890 val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT; 1891 if (((unsigned long)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) { 1892 netdev_warn(dev, "%s: IOADDR %p doesn't match configuration (%x).\n", 1893 CARDNAME, ioaddr, val); 1894 } 1895 1896 /* 1897 * check if the revision register is something that I 1898 * recognize. These might need to be added to later, 1899 * as future revisions could be added. 1900 */ 1901 SMC_SELECT_BANK(lp, 3); 1902 revision_register = SMC_GET_REV(lp); 1903 DBG(2, dev, "%s: revision = 0x%04x\n", CARDNAME, revision_register); 1904 version_string = chip_ids[ (revision_register >> 4) & 0xF]; 1905 if (!version_string || (revision_register & 0xff00) != 0x3300) { 1906 /* I don't recognize this chip, so... */ 1907 netdev_warn(dev, "%s: IO %p: Unrecognized revision register 0x%04x, Contact author.\n", 1908 CARDNAME, ioaddr, revision_register); 1909 1910 retval = -ENODEV; 1911 goto err_out; 1912 } 1913 1914 /* At this point I'll assume that the chip is an SMC91x. */ 1915 pr_info_once("%s\n", version); 1916 1917 /* fill in some of the fields */ 1918 dev->base_addr = (unsigned long)ioaddr; 1919 lp->base = ioaddr; 1920 lp->version = revision_register & 0xff; 1921 spin_lock_init(&lp->lock); 1922 1923 /* Get the MAC address */ 1924 SMC_SELECT_BANK(lp, 1); 1925 SMC_GET_MAC_ADDR(lp, dev->dev_addr); 1926 1927 /* now, reset the chip, and put it into a known state */ 1928 smc_reset(dev); 1929 1930 /* 1931 * If dev->irq is 0, then the device has to be banged on to see 1932 * what the IRQ is. 1933 * 1934 * This banging doesn't always detect the IRQ, for unknown reasons. 1935 * a workaround is to reset the chip and try again. 1936 * 1937 * Interestingly, the DOS packet driver *SETS* the IRQ on the card to 1938 * be what is requested on the command line. I don't do that, mostly 1939 * because the card that I have uses a non-standard method of accessing 1940 * the IRQs, and because this _should_ work in most configurations. 1941 * 1942 * Specifying an IRQ is done with the assumption that the user knows 1943 * what (s)he is doing. No checking is done!!!! 1944 */ 1945 if (dev->irq < 1) { 1946 int trials; 1947 1948 trials = 3; 1949 while (trials--) { 1950 dev->irq = smc_findirq(lp); 1951 if (dev->irq) 1952 break; 1953 /* kick the card and try again */ 1954 smc_reset(dev); 1955 } 1956 } 1957 if (dev->irq == 0) { 1958 netdev_warn(dev, "Couldn't autodetect your IRQ. Use irq=xx.\n"); 1959 retval = -ENODEV; 1960 goto err_out; 1961 } 1962 dev->irq = irq_canonicalize(dev->irq); 1963 1964 dev->watchdog_timeo = msecs_to_jiffies(watchdog); 1965 dev->netdev_ops = &smc_netdev_ops; 1966 dev->ethtool_ops = &smc_ethtool_ops; 1967 1968 tasklet_init(&lp->tx_task, smc_hardware_send_pkt, (unsigned long)dev); 1969 INIT_WORK(&lp->phy_configure, smc_phy_configure); 1970 lp->dev = dev; 1971 lp->mii.phy_id_mask = 0x1f; 1972 lp->mii.reg_num_mask = 0x1f; 1973 lp->mii.force_media = 0; 1974 lp->mii.full_duplex = 0; 1975 lp->mii.dev = dev; 1976 lp->mii.mdio_read = smc_phy_read; 1977 lp->mii.mdio_write = smc_phy_write; 1978 1979 /* 1980 * Locate the phy, if any. 1981 */ 1982 if (lp->version >= (CHIP_91100 << 4)) 1983 smc_phy_detect(dev); 1984 1985 /* then shut everything down to save power */ 1986 smc_shutdown(dev); 1987 smc_phy_powerdown(dev); 1988 1989 /* Set default parameters */ 1990 lp->msg_enable = NETIF_MSG_LINK; 1991 lp->ctl_rfduplx = 0; 1992 lp->ctl_rspeed = 10; 1993 1994 if (lp->version >= (CHIP_91100 << 4)) { 1995 lp->ctl_rfduplx = 1; 1996 lp->ctl_rspeed = 100; 1997 } 1998 1999 /* Grab the IRQ */ 2000 retval = request_irq(dev->irq, smc_interrupt, irq_flags, dev->name, dev); 2001 if (retval) 2002 goto err_out; 2003 2004 #ifdef CONFIG_ARCH_PXA 2005 # ifdef SMC_USE_PXA_DMA 2006 lp->cfg.flags |= SMC91X_USE_DMA; 2007 # endif 2008 if (lp->cfg.flags & SMC91X_USE_DMA) { 2009 dma_cap_mask_t mask; 2010 2011 dma_cap_zero(mask); 2012 dma_cap_set(DMA_SLAVE, mask); 2013 lp->dma_chan = dma_request_channel(mask, NULL, NULL); 2014 } 2015 #endif 2016 2017 retval = register_netdev(dev); 2018 if (retval == 0) { 2019 /* now, print out the card info, in a short format.. */ 2020 netdev_info(dev, "%s (rev %d) at %p IRQ %d", 2021 version_string, revision_register & 0x0f, 2022 lp->base, dev->irq); 2023 2024 if (lp->dma_chan) 2025 pr_cont(" DMA %p", lp->dma_chan); 2026 2027 pr_cont("%s%s\n", 2028 lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "", 2029 THROTTLE_TX_PKTS ? " [throttle_tx]" : ""); 2030 2031 if (!is_valid_ether_addr(dev->dev_addr)) { 2032 netdev_warn(dev, "Invalid ethernet MAC address. Please set using ifconfig\n"); 2033 } else { 2034 /* Print the Ethernet address */ 2035 netdev_info(dev, "Ethernet addr: %pM\n", 2036 dev->dev_addr); 2037 } 2038 2039 if (lp->phy_type == 0) { 2040 PRINTK(dev, "No PHY found\n"); 2041 } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) { 2042 PRINTK(dev, "PHY LAN83C183 (LAN91C111 Internal)\n"); 2043 } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) { 2044 PRINTK(dev, "PHY LAN83C180\n"); 2045 } 2046 } 2047 2048 err_out: 2049 #ifdef CONFIG_ARCH_PXA 2050 if (retval && lp->dma_chan) 2051 dma_release_channel(lp->dma_chan); 2052 #endif 2053 return retval; 2054 } 2055 2056 static int smc_enable_device(struct platform_device *pdev) 2057 { 2058 struct net_device *ndev = platform_get_drvdata(pdev); 2059 struct smc_local *lp = netdev_priv(ndev); 2060 unsigned long flags; 2061 unsigned char ecor, ecsr; 2062 void __iomem *addr; 2063 struct resource * res; 2064 2065 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2066 if (!res) 2067 return 0; 2068 2069 /* 2070 * Map the attribute space. This is overkill, but clean. 2071 */ 2072 addr = ioremap(res->start, ATTRIB_SIZE); 2073 if (!addr) 2074 return -ENOMEM; 2075 2076 /* 2077 * Reset the device. We must disable IRQs around this 2078 * since a reset causes the IRQ line become active. 2079 */ 2080 local_irq_save(flags); 2081 ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; 2082 writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); 2083 readb(addr + (ECOR << SMC_IO_SHIFT)); 2084 2085 /* 2086 * Wait 100us for the chip to reset. 2087 */ 2088 udelay(100); 2089 2090 /* 2091 * The device will ignore all writes to the enable bit while 2092 * reset is asserted, even if the reset bit is cleared in the 2093 * same write. Must clear reset first, then enable the device. 2094 */ 2095 writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); 2096 writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); 2097 2098 /* 2099 * Set the appropriate byte/word mode. 2100 */ 2101 ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; 2102 if (!SMC_16BIT(lp)) 2103 ecsr |= ECSR_IOIS8; 2104 writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); 2105 local_irq_restore(flags); 2106 2107 iounmap(addr); 2108 2109 /* 2110 * Wait for the chip to wake up. We could poll the control 2111 * register in the main register space, but that isn't mapped 2112 * yet. We know this is going to take 750us. 2113 */ 2114 msleep(1); 2115 2116 return 0; 2117 } 2118 2119 static int smc_request_attrib(struct platform_device *pdev, 2120 struct net_device *ndev) 2121 { 2122 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2123 struct smc_local *lp __maybe_unused = netdev_priv(ndev); 2124 2125 if (!res) 2126 return 0; 2127 2128 if (!request_mem_region(res->start, ATTRIB_SIZE, CARDNAME)) 2129 return -EBUSY; 2130 2131 return 0; 2132 } 2133 2134 static void smc_release_attrib(struct platform_device *pdev, 2135 struct net_device *ndev) 2136 { 2137 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2138 struct smc_local *lp __maybe_unused = netdev_priv(ndev); 2139 2140 if (res) 2141 release_mem_region(res->start, ATTRIB_SIZE); 2142 } 2143 2144 static inline void smc_request_datacs(struct platform_device *pdev, struct net_device *ndev) 2145 { 2146 if (SMC_CAN_USE_DATACS) { 2147 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32"); 2148 struct smc_local *lp = netdev_priv(ndev); 2149 2150 if (!res) 2151 return; 2152 2153 if(!request_mem_region(res->start, SMC_DATA_EXTENT, CARDNAME)) { 2154 netdev_info(ndev, "%s: failed to request datacs memory region.\n", 2155 CARDNAME); 2156 return; 2157 } 2158 2159 lp->datacs = ioremap(res->start, SMC_DATA_EXTENT); 2160 } 2161 } 2162 2163 static void smc_release_datacs(struct platform_device *pdev, struct net_device *ndev) 2164 { 2165 if (SMC_CAN_USE_DATACS) { 2166 struct smc_local *lp = netdev_priv(ndev); 2167 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32"); 2168 2169 if (lp->datacs) 2170 iounmap(lp->datacs); 2171 2172 lp->datacs = NULL; 2173 2174 if (res) 2175 release_mem_region(res->start, SMC_DATA_EXTENT); 2176 } 2177 } 2178 2179 static const struct acpi_device_id smc91x_acpi_match[] = { 2180 { "LNRO0003", 0 }, 2181 { } 2182 }; 2183 MODULE_DEVICE_TABLE(acpi, smc91x_acpi_match); 2184 2185 #if IS_BUILTIN(CONFIG_OF) 2186 static const struct of_device_id smc91x_match[] = { 2187 { .compatible = "smsc,lan91c94", }, 2188 { .compatible = "smsc,lan91c111", }, 2189 {}, 2190 }; 2191 MODULE_DEVICE_TABLE(of, smc91x_match); 2192 2193 /** 2194 * of_try_set_control_gpio - configure a gpio if it exists 2195 */ 2196 static int try_toggle_control_gpio(struct device *dev, 2197 struct gpio_desc **desc, 2198 const char *name, int index, 2199 int value, unsigned int nsdelay) 2200 { 2201 struct gpio_desc *gpio = *desc; 2202 enum gpiod_flags flags = value ? GPIOD_OUT_LOW : GPIOD_OUT_HIGH; 2203 2204 gpio = devm_gpiod_get_index_optional(dev, name, index, flags); 2205 if (IS_ERR(gpio)) 2206 return PTR_ERR(gpio); 2207 2208 if (gpio) { 2209 if (nsdelay) 2210 usleep_range(nsdelay, 2 * nsdelay); 2211 gpiod_set_value_cansleep(gpio, value); 2212 } 2213 *desc = gpio; 2214 2215 return 0; 2216 } 2217 #endif 2218 2219 /* 2220 * smc_init(void) 2221 * Input parameters: 2222 * dev->base_addr == 0, try to find all possible locations 2223 * dev->base_addr > 0x1ff, this is the address to check 2224 * dev->base_addr == <anything else>, return failure code 2225 * 2226 * Output: 2227 * 0 --> there is a device 2228 * anything else, error 2229 */ 2230 static int smc_drv_probe(struct platform_device *pdev) 2231 { 2232 struct smc91x_platdata *pd = dev_get_platdata(&pdev->dev); 2233 const struct of_device_id *match = NULL; 2234 struct smc_local *lp; 2235 struct net_device *ndev; 2236 struct resource *res; 2237 unsigned int __iomem *addr; 2238 unsigned long irq_flags = SMC_IRQ_FLAGS; 2239 unsigned long irq_resflags; 2240 int ret; 2241 2242 ndev = alloc_etherdev(sizeof(struct smc_local)); 2243 if (!ndev) { 2244 ret = -ENOMEM; 2245 goto out; 2246 } 2247 SET_NETDEV_DEV(ndev, &pdev->dev); 2248 2249 /* get configuration from platform data, only allow use of 2250 * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set. 2251 */ 2252 2253 lp = netdev_priv(ndev); 2254 lp->cfg.flags = 0; 2255 2256 if (pd) { 2257 memcpy(&lp->cfg, pd, sizeof(lp->cfg)); 2258 lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags); 2259 2260 if (!SMC_8BIT(lp) && !SMC_16BIT(lp)) { 2261 dev_err(&pdev->dev, 2262 "at least one of 8-bit or 16-bit access support is required.\n"); 2263 ret = -ENXIO; 2264 goto out_free_netdev; 2265 } 2266 } 2267 2268 #if IS_BUILTIN(CONFIG_OF) 2269 match = of_match_device(of_match_ptr(smc91x_match), &pdev->dev); 2270 if (match) { 2271 u32 val; 2272 2273 /* Optional pwrdwn GPIO configured? */ 2274 ret = try_toggle_control_gpio(&pdev->dev, &lp->power_gpio, 2275 "power", 0, 0, 100); 2276 if (ret) 2277 return ret; 2278 2279 /* 2280 * Optional reset GPIO configured? Minimum 100 ns reset needed 2281 * according to LAN91C96 datasheet page 14. 2282 */ 2283 ret = try_toggle_control_gpio(&pdev->dev, &lp->reset_gpio, 2284 "reset", 0, 0, 100); 2285 if (ret) 2286 return ret; 2287 2288 /* 2289 * Need to wait for optional EEPROM to load, max 750 us according 2290 * to LAN91C96 datasheet page 55. 2291 */ 2292 if (lp->reset_gpio) 2293 usleep_range(750, 1000); 2294 2295 /* Combination of IO widths supported, default to 16-bit */ 2296 if (!device_property_read_u32(&pdev->dev, "reg-io-width", 2297 &val)) { 2298 if (val & 1) 2299 lp->cfg.flags |= SMC91X_USE_8BIT; 2300 if ((val == 0) || (val & 2)) 2301 lp->cfg.flags |= SMC91X_USE_16BIT; 2302 if (val & 4) 2303 lp->cfg.flags |= SMC91X_USE_32BIT; 2304 } else { 2305 lp->cfg.flags |= SMC91X_USE_16BIT; 2306 } 2307 if (!device_property_read_u32(&pdev->dev, "reg-shift", 2308 &val)) 2309 lp->io_shift = val; 2310 lp->cfg.pxa_u16_align4 = 2311 device_property_read_bool(&pdev->dev, "pxa-u16-align4"); 2312 } 2313 #endif 2314 2315 if (!pd && !match) { 2316 lp->cfg.flags |= (SMC_CAN_USE_8BIT) ? SMC91X_USE_8BIT : 0; 2317 lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0; 2318 lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0; 2319 lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0; 2320 } 2321 2322 if (!lp->cfg.leda && !lp->cfg.ledb) { 2323 lp->cfg.leda = RPC_LSA_DEFAULT; 2324 lp->cfg.ledb = RPC_LSB_DEFAULT; 2325 } 2326 2327 ndev->dma = (unsigned char)-1; 2328 2329 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); 2330 if (!res) 2331 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2332 if (!res) { 2333 ret = -ENODEV; 2334 goto out_free_netdev; 2335 } 2336 2337 2338 if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) { 2339 ret = -EBUSY; 2340 goto out_free_netdev; 2341 } 2342 2343 ndev->irq = platform_get_irq(pdev, 0); 2344 if (ndev->irq < 0) { 2345 ret = ndev->irq; 2346 goto out_release_io; 2347 } 2348 /* 2349 * If this platform does not specify any special irqflags, or if 2350 * the resource supplies a trigger, override the irqflags with 2351 * the trigger flags from the resource. 2352 */ 2353 irq_resflags = irqd_get_trigger_type(irq_get_irq_data(ndev->irq)); 2354 if (irq_flags == -1 || irq_resflags & IRQF_TRIGGER_MASK) 2355 irq_flags = irq_resflags & IRQF_TRIGGER_MASK; 2356 2357 ret = smc_request_attrib(pdev, ndev); 2358 if (ret) 2359 goto out_release_io; 2360 #if defined(CONFIG_ASSABET_NEPONSET) 2361 if (machine_is_assabet() && machine_has_neponset()) 2362 neponset_ncr_set(NCR_ENET_OSC_EN); 2363 #endif 2364 platform_set_drvdata(pdev, ndev); 2365 ret = smc_enable_device(pdev); 2366 if (ret) 2367 goto out_release_attrib; 2368 2369 addr = ioremap(res->start, SMC_IO_EXTENT); 2370 if (!addr) { 2371 ret = -ENOMEM; 2372 goto out_release_attrib; 2373 } 2374 2375 #ifdef CONFIG_ARCH_PXA 2376 { 2377 struct smc_local *lp = netdev_priv(ndev); 2378 lp->device = &pdev->dev; 2379 lp->physaddr = res->start; 2380 2381 } 2382 #endif 2383 2384 ret = smc_probe(ndev, addr, irq_flags); 2385 if (ret != 0) 2386 goto out_iounmap; 2387 2388 smc_request_datacs(pdev, ndev); 2389 2390 return 0; 2391 2392 out_iounmap: 2393 iounmap(addr); 2394 out_release_attrib: 2395 smc_release_attrib(pdev, ndev); 2396 out_release_io: 2397 release_mem_region(res->start, SMC_IO_EXTENT); 2398 out_free_netdev: 2399 free_netdev(ndev); 2400 out: 2401 pr_info("%s: not found (%d).\n", CARDNAME, ret); 2402 2403 return ret; 2404 } 2405 2406 static int smc_drv_remove(struct platform_device *pdev) 2407 { 2408 struct net_device *ndev = platform_get_drvdata(pdev); 2409 struct smc_local *lp = netdev_priv(ndev); 2410 struct resource *res; 2411 2412 unregister_netdev(ndev); 2413 2414 free_irq(ndev->irq, ndev); 2415 2416 #ifdef CONFIG_ARCH_PXA 2417 if (lp->dma_chan) 2418 dma_release_channel(lp->dma_chan); 2419 #endif 2420 iounmap(lp->base); 2421 2422 smc_release_datacs(pdev,ndev); 2423 smc_release_attrib(pdev,ndev); 2424 2425 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); 2426 if (!res) 2427 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2428 release_mem_region(res->start, SMC_IO_EXTENT); 2429 2430 free_netdev(ndev); 2431 2432 return 0; 2433 } 2434 2435 static int smc_drv_suspend(struct device *dev) 2436 { 2437 struct net_device *ndev = dev_get_drvdata(dev); 2438 2439 if (ndev) { 2440 if (netif_running(ndev)) { 2441 netif_device_detach(ndev); 2442 smc_shutdown(ndev); 2443 smc_phy_powerdown(ndev); 2444 } 2445 } 2446 return 0; 2447 } 2448 2449 static int smc_drv_resume(struct device *dev) 2450 { 2451 struct platform_device *pdev = to_platform_device(dev); 2452 struct net_device *ndev = platform_get_drvdata(pdev); 2453 2454 if (ndev) { 2455 struct smc_local *lp = netdev_priv(ndev); 2456 smc_enable_device(pdev); 2457 if (netif_running(ndev)) { 2458 smc_reset(ndev); 2459 smc_enable(ndev); 2460 if (lp->phy_type != 0) 2461 smc_phy_configure(&lp->phy_configure); 2462 netif_device_attach(ndev); 2463 } 2464 } 2465 return 0; 2466 } 2467 2468 static const struct dev_pm_ops smc_drv_pm_ops = { 2469 .suspend = smc_drv_suspend, 2470 .resume = smc_drv_resume, 2471 }; 2472 2473 static struct platform_driver smc_driver = { 2474 .probe = smc_drv_probe, 2475 .remove = smc_drv_remove, 2476 .driver = { 2477 .name = CARDNAME, 2478 .pm = &smc_drv_pm_ops, 2479 .of_match_table = of_match_ptr(smc91x_match), 2480 .acpi_match_table = smc91x_acpi_match, 2481 }, 2482 }; 2483 2484 module_platform_driver(smc_driver); 2485