1 /* 2 * smc91x.c 3 * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices. 4 * 5 * Copyright (C) 1996 by Erik Stahlman 6 * Copyright (C) 2001 Standard Microsystems Corporation 7 * Developed by Simple Network Magic Corporation 8 * Copyright (C) 2003 Monta Vista Software, Inc. 9 * Unified SMC91x driver by Nicolas Pitre 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 24 * 25 * Arguments: 26 * io = for the base address 27 * irq = for the IRQ 28 * nowait = 0 for normal wait states, 1 eliminates additional wait states 29 * 30 * original author: 31 * Erik Stahlman <erik@vt.edu> 32 * 33 * hardware multicast code: 34 * Peter Cammaert <pc@denkart.be> 35 * 36 * contributors: 37 * Daris A Nevil <dnevil@snmc.com> 38 * Nicolas Pitre <nico@fluxnic.net> 39 * Russell King <rmk@arm.linux.org.uk> 40 * 41 * History: 42 * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet 43 * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ" 44 * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111 45 * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111 46 * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111 47 * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support 48 * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races, 49 * more bus abstraction, big cleanup, etc. 50 * 29/09/03 Russell King - add driver model support 51 * - ethtool support 52 * - convert to use generic MII interface 53 * - add link up/down notification 54 * - don't try to handle full negotiation in 55 * smc_phy_configure 56 * - clean up (and fix stack overrun) in PHY 57 * MII read/write functions 58 * 22/09/04 Nicolas Pitre big update (see commit log for details) 59 */ 60 static const char version[] = 61 "smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>\n"; 62 63 /* Debugging level */ 64 #ifndef SMC_DEBUG 65 #define SMC_DEBUG 0 66 #endif 67 68 69 #include <linux/init.h> 70 #include <linux/module.h> 71 #include <linux/kernel.h> 72 #include <linux/sched.h> 73 #include <linux/delay.h> 74 #include <linux/interrupt.h> 75 #include <linux/irq.h> 76 #include <linux/errno.h> 77 #include <linux/ioport.h> 78 #include <linux/crc32.h> 79 #include <linux/platform_device.h> 80 #include <linux/spinlock.h> 81 #include <linux/ethtool.h> 82 #include <linux/mii.h> 83 #include <linux/workqueue.h> 84 #include <linux/of.h> 85 86 #include <linux/netdevice.h> 87 #include <linux/etherdevice.h> 88 #include <linux/skbuff.h> 89 90 #include <asm/io.h> 91 92 #include "smc91x.h" 93 94 #ifndef SMC_NOWAIT 95 # define SMC_NOWAIT 0 96 #endif 97 static int nowait = SMC_NOWAIT; 98 module_param(nowait, int, 0400); 99 MODULE_PARM_DESC(nowait, "set to 1 for no wait state"); 100 101 /* 102 * Transmit timeout, default 5 seconds. 103 */ 104 static int watchdog = 1000; 105 module_param(watchdog, int, 0400); 106 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); 107 108 MODULE_LICENSE("GPL"); 109 MODULE_ALIAS("platform:smc91x"); 110 111 /* 112 * The internal workings of the driver. If you are changing anything 113 * here with the SMC stuff, you should have the datasheet and know 114 * what you are doing. 115 */ 116 #define CARDNAME "smc91x" 117 118 /* 119 * Use power-down feature of the chip 120 */ 121 #define POWER_DOWN 1 122 123 /* 124 * Wait time for memory to be free. This probably shouldn't be 125 * tuned that much, as waiting for this means nothing else happens 126 * in the system 127 */ 128 #define MEMORY_WAIT_TIME 16 129 130 /* 131 * The maximum number of processing loops allowed for each call to the 132 * IRQ handler. 133 */ 134 #define MAX_IRQ_LOOPS 8 135 136 /* 137 * This selects whether TX packets are sent one by one to the SMC91x internal 138 * memory and throttled until transmission completes. This may prevent 139 * RX overruns a litle by keeping much of the memory free for RX packets 140 * but to the expense of reduced TX throughput and increased IRQ overhead. 141 * Note this is not a cure for a too slow data bus or too high IRQ latency. 142 */ 143 #define THROTTLE_TX_PKTS 0 144 145 /* 146 * The MII clock high/low times. 2x this number gives the MII clock period 147 * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!) 148 */ 149 #define MII_DELAY 1 150 151 #if SMC_DEBUG > 0 152 #define DBG(n, args...) \ 153 do { \ 154 if (SMC_DEBUG >= (n)) \ 155 printk(args); \ 156 } while (0) 157 158 #define PRINTK(args...) printk(args) 159 #else 160 #define DBG(n, args...) do { } while(0) 161 #define PRINTK(args...) printk(KERN_DEBUG args) 162 #endif 163 164 #if SMC_DEBUG > 3 165 static void PRINT_PKT(u_char *buf, int length) 166 { 167 int i; 168 int remainder; 169 int lines; 170 171 lines = length / 16; 172 remainder = length % 16; 173 174 for (i = 0; i < lines ; i ++) { 175 int cur; 176 for (cur = 0; cur < 8; cur++) { 177 u_char a, b; 178 a = *buf++; 179 b = *buf++; 180 printk("%02x%02x ", a, b); 181 } 182 printk("\n"); 183 } 184 for (i = 0; i < remainder/2 ; i++) { 185 u_char a, b; 186 a = *buf++; 187 b = *buf++; 188 printk("%02x%02x ", a, b); 189 } 190 printk("\n"); 191 } 192 #else 193 #define PRINT_PKT(x...) do { } while(0) 194 #endif 195 196 197 /* this enables an interrupt in the interrupt mask register */ 198 #define SMC_ENABLE_INT(lp, x) do { \ 199 unsigned char mask; \ 200 unsigned long smc_enable_flags; \ 201 spin_lock_irqsave(&lp->lock, smc_enable_flags); \ 202 mask = SMC_GET_INT_MASK(lp); \ 203 mask |= (x); \ 204 SMC_SET_INT_MASK(lp, mask); \ 205 spin_unlock_irqrestore(&lp->lock, smc_enable_flags); \ 206 } while (0) 207 208 /* this disables an interrupt from the interrupt mask register */ 209 #define SMC_DISABLE_INT(lp, x) do { \ 210 unsigned char mask; \ 211 unsigned long smc_disable_flags; \ 212 spin_lock_irqsave(&lp->lock, smc_disable_flags); \ 213 mask = SMC_GET_INT_MASK(lp); \ 214 mask &= ~(x); \ 215 SMC_SET_INT_MASK(lp, mask); \ 216 spin_unlock_irqrestore(&lp->lock, smc_disable_flags); \ 217 } while (0) 218 219 /* 220 * Wait while MMU is busy. This is usually in the order of a few nanosecs 221 * if at all, but let's avoid deadlocking the system if the hardware 222 * decides to go south. 223 */ 224 #define SMC_WAIT_MMU_BUSY(lp) do { \ 225 if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \ 226 unsigned long timeout = jiffies + 2; \ 227 while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \ 228 if (time_after(jiffies, timeout)) { \ 229 printk("%s: timeout %s line %d\n", \ 230 dev->name, __FILE__, __LINE__); \ 231 break; \ 232 } \ 233 cpu_relax(); \ 234 } \ 235 } \ 236 } while (0) 237 238 239 /* 240 * this does a soft reset on the device 241 */ 242 static void smc_reset(struct net_device *dev) 243 { 244 struct smc_local *lp = netdev_priv(dev); 245 void __iomem *ioaddr = lp->base; 246 unsigned int ctl, cfg; 247 struct sk_buff *pending_skb; 248 249 DBG(2, "%s: %s\n", dev->name, __func__); 250 251 /* Disable all interrupts, block TX tasklet */ 252 spin_lock_irq(&lp->lock); 253 SMC_SELECT_BANK(lp, 2); 254 SMC_SET_INT_MASK(lp, 0); 255 pending_skb = lp->pending_tx_skb; 256 lp->pending_tx_skb = NULL; 257 spin_unlock_irq(&lp->lock); 258 259 /* free any pending tx skb */ 260 if (pending_skb) { 261 dev_kfree_skb(pending_skb); 262 dev->stats.tx_errors++; 263 dev->stats.tx_aborted_errors++; 264 } 265 266 /* 267 * This resets the registers mostly to defaults, but doesn't 268 * affect EEPROM. That seems unnecessary 269 */ 270 SMC_SELECT_BANK(lp, 0); 271 SMC_SET_RCR(lp, RCR_SOFTRST); 272 273 /* 274 * Setup the Configuration Register 275 * This is necessary because the CONFIG_REG is not affected 276 * by a soft reset 277 */ 278 SMC_SELECT_BANK(lp, 1); 279 280 cfg = CONFIG_DEFAULT; 281 282 /* 283 * Setup for fast accesses if requested. If the card/system 284 * can't handle it then there will be no recovery except for 285 * a hard reset or power cycle 286 */ 287 if (lp->cfg.flags & SMC91X_NOWAIT) 288 cfg |= CONFIG_NO_WAIT; 289 290 /* 291 * Release from possible power-down state 292 * Configuration register is not affected by Soft Reset 293 */ 294 cfg |= CONFIG_EPH_POWER_EN; 295 296 SMC_SET_CONFIG(lp, cfg); 297 298 /* this should pause enough for the chip to be happy */ 299 /* 300 * elaborate? What does the chip _need_? --jgarzik 301 * 302 * This seems to be undocumented, but something the original 303 * driver(s) have always done. Suspect undocumented timing 304 * info/determined empirically. --rmk 305 */ 306 udelay(1); 307 308 /* Disable transmit and receive functionality */ 309 SMC_SELECT_BANK(lp, 0); 310 SMC_SET_RCR(lp, RCR_CLEAR); 311 SMC_SET_TCR(lp, TCR_CLEAR); 312 313 SMC_SELECT_BANK(lp, 1); 314 ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE; 315 316 /* 317 * Set the control register to automatically release successfully 318 * transmitted packets, to make the best use out of our limited 319 * memory 320 */ 321 if(!THROTTLE_TX_PKTS) 322 ctl |= CTL_AUTO_RELEASE; 323 else 324 ctl &= ~CTL_AUTO_RELEASE; 325 SMC_SET_CTL(lp, ctl); 326 327 /* Reset the MMU */ 328 SMC_SELECT_BANK(lp, 2); 329 SMC_SET_MMU_CMD(lp, MC_RESET); 330 SMC_WAIT_MMU_BUSY(lp); 331 } 332 333 /* 334 * Enable Interrupts, Receive, and Transmit 335 */ 336 static void smc_enable(struct net_device *dev) 337 { 338 struct smc_local *lp = netdev_priv(dev); 339 void __iomem *ioaddr = lp->base; 340 int mask; 341 342 DBG(2, "%s: %s\n", dev->name, __func__); 343 344 /* see the header file for options in TCR/RCR DEFAULT */ 345 SMC_SELECT_BANK(lp, 0); 346 SMC_SET_TCR(lp, lp->tcr_cur_mode); 347 SMC_SET_RCR(lp, lp->rcr_cur_mode); 348 349 SMC_SELECT_BANK(lp, 1); 350 SMC_SET_MAC_ADDR(lp, dev->dev_addr); 351 352 /* now, enable interrupts */ 353 mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT; 354 if (lp->version >= (CHIP_91100 << 4)) 355 mask |= IM_MDINT; 356 SMC_SELECT_BANK(lp, 2); 357 SMC_SET_INT_MASK(lp, mask); 358 359 /* 360 * From this point the register bank must _NOT_ be switched away 361 * to something else than bank 2 without proper locking against 362 * races with any tasklet or interrupt handlers until smc_shutdown() 363 * or smc_reset() is called. 364 */ 365 } 366 367 /* 368 * this puts the device in an inactive state 369 */ 370 static void smc_shutdown(struct net_device *dev) 371 { 372 struct smc_local *lp = netdev_priv(dev); 373 void __iomem *ioaddr = lp->base; 374 struct sk_buff *pending_skb; 375 376 DBG(2, "%s: %s\n", CARDNAME, __func__); 377 378 /* no more interrupts for me */ 379 spin_lock_irq(&lp->lock); 380 SMC_SELECT_BANK(lp, 2); 381 SMC_SET_INT_MASK(lp, 0); 382 pending_skb = lp->pending_tx_skb; 383 lp->pending_tx_skb = NULL; 384 spin_unlock_irq(&lp->lock); 385 if (pending_skb) 386 dev_kfree_skb(pending_skb); 387 388 /* and tell the card to stay away from that nasty outside world */ 389 SMC_SELECT_BANK(lp, 0); 390 SMC_SET_RCR(lp, RCR_CLEAR); 391 SMC_SET_TCR(lp, TCR_CLEAR); 392 393 #ifdef POWER_DOWN 394 /* finally, shut the chip down */ 395 SMC_SELECT_BANK(lp, 1); 396 SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN); 397 #endif 398 } 399 400 /* 401 * This is the procedure to handle the receipt of a packet. 402 */ 403 static inline void smc_rcv(struct net_device *dev) 404 { 405 struct smc_local *lp = netdev_priv(dev); 406 void __iomem *ioaddr = lp->base; 407 unsigned int packet_number, status, packet_len; 408 409 DBG(3, "%s: %s\n", dev->name, __func__); 410 411 packet_number = SMC_GET_RXFIFO(lp); 412 if (unlikely(packet_number & RXFIFO_REMPTY)) { 413 PRINTK("%s: smc_rcv with nothing on FIFO.\n", dev->name); 414 return; 415 } 416 417 /* read from start of packet */ 418 SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC); 419 420 /* First two words are status and packet length */ 421 SMC_GET_PKT_HDR(lp, status, packet_len); 422 packet_len &= 0x07ff; /* mask off top bits */ 423 DBG(2, "%s: RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n", 424 dev->name, packet_number, status, 425 packet_len, packet_len); 426 427 back: 428 if (unlikely(packet_len < 6 || status & RS_ERRORS)) { 429 if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) { 430 /* accept VLAN packets */ 431 status &= ~RS_TOOLONG; 432 goto back; 433 } 434 if (packet_len < 6) { 435 /* bloody hardware */ 436 printk(KERN_ERR "%s: fubar (rxlen %u status %x\n", 437 dev->name, packet_len, status); 438 status |= RS_TOOSHORT; 439 } 440 SMC_WAIT_MMU_BUSY(lp); 441 SMC_SET_MMU_CMD(lp, MC_RELEASE); 442 dev->stats.rx_errors++; 443 if (status & RS_ALGNERR) 444 dev->stats.rx_frame_errors++; 445 if (status & (RS_TOOSHORT | RS_TOOLONG)) 446 dev->stats.rx_length_errors++; 447 if (status & RS_BADCRC) 448 dev->stats.rx_crc_errors++; 449 } else { 450 struct sk_buff *skb; 451 unsigned char *data; 452 unsigned int data_len; 453 454 /* set multicast stats */ 455 if (status & RS_MULTICAST) 456 dev->stats.multicast++; 457 458 /* 459 * Actual payload is packet_len - 6 (or 5 if odd byte). 460 * We want skb_reserve(2) and the final ctrl word 461 * (2 bytes, possibly containing the payload odd byte). 462 * Furthermore, we add 2 bytes to allow rounding up to 463 * multiple of 4 bytes on 32 bit buses. 464 * Hence packet_len - 6 + 2 + 2 + 2. 465 */ 466 skb = netdev_alloc_skb(dev, packet_len); 467 if (unlikely(skb == NULL)) { 468 SMC_WAIT_MMU_BUSY(lp); 469 SMC_SET_MMU_CMD(lp, MC_RELEASE); 470 dev->stats.rx_dropped++; 471 return; 472 } 473 474 /* Align IP header to 32 bits */ 475 skb_reserve(skb, 2); 476 477 /* BUG: the LAN91C111 rev A never sets this bit. Force it. */ 478 if (lp->version == 0x90) 479 status |= RS_ODDFRAME; 480 481 /* 482 * If odd length: packet_len - 5, 483 * otherwise packet_len - 6. 484 * With the trailing ctrl byte it's packet_len - 4. 485 */ 486 data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6); 487 data = skb_put(skb, data_len); 488 SMC_PULL_DATA(lp, data, packet_len - 4); 489 490 SMC_WAIT_MMU_BUSY(lp); 491 SMC_SET_MMU_CMD(lp, MC_RELEASE); 492 493 PRINT_PKT(data, packet_len - 4); 494 495 skb->protocol = eth_type_trans(skb, dev); 496 netif_rx(skb); 497 dev->stats.rx_packets++; 498 dev->stats.rx_bytes += data_len; 499 } 500 } 501 502 #ifdef CONFIG_SMP 503 /* 504 * On SMP we have the following problem: 505 * 506 * A = smc_hardware_send_pkt() 507 * B = smc_hard_start_xmit() 508 * C = smc_interrupt() 509 * 510 * A and B can never be executed simultaneously. However, at least on UP, 511 * it is possible (and even desirable) for C to interrupt execution of 512 * A or B in order to have better RX reliability and avoid overruns. 513 * C, just like A and B, must have exclusive access to the chip and 514 * each of them must lock against any other concurrent access. 515 * Unfortunately this is not possible to have C suspend execution of A or 516 * B taking place on another CPU. On UP this is no an issue since A and B 517 * are run from softirq context and C from hard IRQ context, and there is 518 * no other CPU where concurrent access can happen. 519 * If ever there is a way to force at least B and C to always be executed 520 * on the same CPU then we could use read/write locks to protect against 521 * any other concurrent access and C would always interrupt B. But life 522 * isn't that easy in a SMP world... 523 */ 524 #define smc_special_trylock(lock, flags) \ 525 ({ \ 526 int __ret; \ 527 local_irq_save(flags); \ 528 __ret = spin_trylock(lock); \ 529 if (!__ret) \ 530 local_irq_restore(flags); \ 531 __ret; \ 532 }) 533 #define smc_special_lock(lock, flags) spin_lock_irqsave(lock, flags) 534 #define smc_special_unlock(lock, flags) spin_unlock_irqrestore(lock, flags) 535 #else 536 #define smc_special_trylock(lock, flags) (flags == flags) 537 #define smc_special_lock(lock, flags) do { flags = 0; } while (0) 538 #define smc_special_unlock(lock, flags) do { flags = 0; } while (0) 539 #endif 540 541 /* 542 * This is called to actually send a packet to the chip. 543 */ 544 static void smc_hardware_send_pkt(unsigned long data) 545 { 546 struct net_device *dev = (struct net_device *)data; 547 struct smc_local *lp = netdev_priv(dev); 548 void __iomem *ioaddr = lp->base; 549 struct sk_buff *skb; 550 unsigned int packet_no, len; 551 unsigned char *buf; 552 unsigned long flags; 553 554 DBG(3, "%s: %s\n", dev->name, __func__); 555 556 if (!smc_special_trylock(&lp->lock, flags)) { 557 netif_stop_queue(dev); 558 tasklet_schedule(&lp->tx_task); 559 return; 560 } 561 562 skb = lp->pending_tx_skb; 563 if (unlikely(!skb)) { 564 smc_special_unlock(&lp->lock, flags); 565 return; 566 } 567 lp->pending_tx_skb = NULL; 568 569 packet_no = SMC_GET_AR(lp); 570 if (unlikely(packet_no & AR_FAILED)) { 571 printk("%s: Memory allocation failed.\n", dev->name); 572 dev->stats.tx_errors++; 573 dev->stats.tx_fifo_errors++; 574 smc_special_unlock(&lp->lock, flags); 575 goto done; 576 } 577 578 /* point to the beginning of the packet */ 579 SMC_SET_PN(lp, packet_no); 580 SMC_SET_PTR(lp, PTR_AUTOINC); 581 582 buf = skb->data; 583 len = skb->len; 584 DBG(2, "%s: TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n", 585 dev->name, packet_no, len, len, buf); 586 PRINT_PKT(buf, len); 587 588 /* 589 * Send the packet length (+6 for status words, length, and ctl. 590 * The card will pad to 64 bytes with zeroes if packet is too small. 591 */ 592 SMC_PUT_PKT_HDR(lp, 0, len + 6); 593 594 /* send the actual data */ 595 SMC_PUSH_DATA(lp, buf, len & ~1); 596 597 /* Send final ctl word with the last byte if there is one */ 598 SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG(lp)); 599 600 /* 601 * If THROTTLE_TX_PKTS is set, we stop the queue here. This will 602 * have the effect of having at most one packet queued for TX 603 * in the chip's memory at all time. 604 * 605 * If THROTTLE_TX_PKTS is not set then the queue is stopped only 606 * when memory allocation (MC_ALLOC) does not succeed right away. 607 */ 608 if (THROTTLE_TX_PKTS) 609 netif_stop_queue(dev); 610 611 /* queue the packet for TX */ 612 SMC_SET_MMU_CMD(lp, MC_ENQUEUE); 613 smc_special_unlock(&lp->lock, flags); 614 615 dev->trans_start = jiffies; 616 dev->stats.tx_packets++; 617 dev->stats.tx_bytes += len; 618 619 SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT); 620 621 done: if (!THROTTLE_TX_PKTS) 622 netif_wake_queue(dev); 623 624 dev_kfree_skb(skb); 625 } 626 627 /* 628 * Since I am not sure if I will have enough room in the chip's ram 629 * to store the packet, I call this routine which either sends it 630 * now, or set the card to generates an interrupt when ready 631 * for the packet. 632 */ 633 static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) 634 { 635 struct smc_local *lp = netdev_priv(dev); 636 void __iomem *ioaddr = lp->base; 637 unsigned int numPages, poll_count, status; 638 unsigned long flags; 639 640 DBG(3, "%s: %s\n", dev->name, __func__); 641 642 BUG_ON(lp->pending_tx_skb != NULL); 643 644 /* 645 * The MMU wants the number of pages to be the number of 256 bytes 646 * 'pages', minus 1 (since a packet can't ever have 0 pages :)) 647 * 648 * The 91C111 ignores the size bits, but earlier models don't. 649 * 650 * Pkt size for allocating is data length +6 (for additional status 651 * words, length and ctl) 652 * 653 * If odd size then last byte is included in ctl word. 654 */ 655 numPages = ((skb->len & ~1) + (6 - 1)) >> 8; 656 if (unlikely(numPages > 7)) { 657 printk("%s: Far too big packet error.\n", dev->name); 658 dev->stats.tx_errors++; 659 dev->stats.tx_dropped++; 660 dev_kfree_skb(skb); 661 return NETDEV_TX_OK; 662 } 663 664 smc_special_lock(&lp->lock, flags); 665 666 /* now, try to allocate the memory */ 667 SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages); 668 669 /* 670 * Poll the chip for a short amount of time in case the 671 * allocation succeeds quickly. 672 */ 673 poll_count = MEMORY_WAIT_TIME; 674 do { 675 status = SMC_GET_INT(lp); 676 if (status & IM_ALLOC_INT) { 677 SMC_ACK_INT(lp, IM_ALLOC_INT); 678 break; 679 } 680 } while (--poll_count); 681 682 smc_special_unlock(&lp->lock, flags); 683 684 lp->pending_tx_skb = skb; 685 if (!poll_count) { 686 /* oh well, wait until the chip finds memory later */ 687 netif_stop_queue(dev); 688 DBG(2, "%s: TX memory allocation deferred.\n", dev->name); 689 SMC_ENABLE_INT(lp, IM_ALLOC_INT); 690 } else { 691 /* 692 * Allocation succeeded: push packet to the chip's own memory 693 * immediately. 694 */ 695 smc_hardware_send_pkt((unsigned long)dev); 696 } 697 698 return NETDEV_TX_OK; 699 } 700 701 /* 702 * This handles a TX interrupt, which is only called when: 703 * - a TX error occurred, or 704 * - CTL_AUTO_RELEASE is not set and TX of a packet completed. 705 */ 706 static void smc_tx(struct net_device *dev) 707 { 708 struct smc_local *lp = netdev_priv(dev); 709 void __iomem *ioaddr = lp->base; 710 unsigned int saved_packet, packet_no, tx_status, pkt_len; 711 712 DBG(3, "%s: %s\n", dev->name, __func__); 713 714 /* If the TX FIFO is empty then nothing to do */ 715 packet_no = SMC_GET_TXFIFO(lp); 716 if (unlikely(packet_no & TXFIFO_TEMPTY)) { 717 PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name); 718 return; 719 } 720 721 /* select packet to read from */ 722 saved_packet = SMC_GET_PN(lp); 723 SMC_SET_PN(lp, packet_no); 724 725 /* read the first word (status word) from this packet */ 726 SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ); 727 SMC_GET_PKT_HDR(lp, tx_status, pkt_len); 728 DBG(2, "%s: TX STATUS 0x%04x PNR 0x%02x\n", 729 dev->name, tx_status, packet_no); 730 731 if (!(tx_status & ES_TX_SUC)) 732 dev->stats.tx_errors++; 733 734 if (tx_status & ES_LOSTCARR) 735 dev->stats.tx_carrier_errors++; 736 737 if (tx_status & (ES_LATCOL | ES_16COL)) { 738 PRINTK("%s: %s occurred on last xmit\n", dev->name, 739 (tx_status & ES_LATCOL) ? 740 "late collision" : "too many collisions"); 741 dev->stats.tx_window_errors++; 742 if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) { 743 printk(KERN_INFO "%s: unexpectedly large number of " 744 "bad collisions. Please check duplex " 745 "setting.\n", dev->name); 746 } 747 } 748 749 /* kill the packet */ 750 SMC_WAIT_MMU_BUSY(lp); 751 SMC_SET_MMU_CMD(lp, MC_FREEPKT); 752 753 /* Don't restore Packet Number Reg until busy bit is cleared */ 754 SMC_WAIT_MMU_BUSY(lp); 755 SMC_SET_PN(lp, saved_packet); 756 757 /* re-enable transmit */ 758 SMC_SELECT_BANK(lp, 0); 759 SMC_SET_TCR(lp, lp->tcr_cur_mode); 760 SMC_SELECT_BANK(lp, 2); 761 } 762 763 764 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ 765 766 static void smc_mii_out(struct net_device *dev, unsigned int val, int bits) 767 { 768 struct smc_local *lp = netdev_priv(dev); 769 void __iomem *ioaddr = lp->base; 770 unsigned int mii_reg, mask; 771 772 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO); 773 mii_reg |= MII_MDOE; 774 775 for (mask = 1 << (bits - 1); mask; mask >>= 1) { 776 if (val & mask) 777 mii_reg |= MII_MDO; 778 else 779 mii_reg &= ~MII_MDO; 780 781 SMC_SET_MII(lp, mii_reg); 782 udelay(MII_DELAY); 783 SMC_SET_MII(lp, mii_reg | MII_MCLK); 784 udelay(MII_DELAY); 785 } 786 } 787 788 static unsigned int smc_mii_in(struct net_device *dev, int bits) 789 { 790 struct smc_local *lp = netdev_priv(dev); 791 void __iomem *ioaddr = lp->base; 792 unsigned int mii_reg, mask, val; 793 794 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO); 795 SMC_SET_MII(lp, mii_reg); 796 797 for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) { 798 if (SMC_GET_MII(lp) & MII_MDI) 799 val |= mask; 800 801 SMC_SET_MII(lp, mii_reg); 802 udelay(MII_DELAY); 803 SMC_SET_MII(lp, mii_reg | MII_MCLK); 804 udelay(MII_DELAY); 805 } 806 807 return val; 808 } 809 810 /* 811 * Reads a register from the MII Management serial interface 812 */ 813 static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg) 814 { 815 struct smc_local *lp = netdev_priv(dev); 816 void __iomem *ioaddr = lp->base; 817 unsigned int phydata; 818 819 SMC_SELECT_BANK(lp, 3); 820 821 /* Idle - 32 ones */ 822 smc_mii_out(dev, 0xffffffff, 32); 823 824 /* Start code (01) + read (10) + phyaddr + phyreg */ 825 smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14); 826 827 /* Turnaround (2bits) + phydata */ 828 phydata = smc_mii_in(dev, 18); 829 830 /* Return to idle state */ 831 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO)); 832 833 DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", 834 __func__, phyaddr, phyreg, phydata); 835 836 SMC_SELECT_BANK(lp, 2); 837 return phydata; 838 } 839 840 /* 841 * Writes a register to the MII Management serial interface 842 */ 843 static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg, 844 int phydata) 845 { 846 struct smc_local *lp = netdev_priv(dev); 847 void __iomem *ioaddr = lp->base; 848 849 SMC_SELECT_BANK(lp, 3); 850 851 /* Idle - 32 ones */ 852 smc_mii_out(dev, 0xffffffff, 32); 853 854 /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */ 855 smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32); 856 857 /* Return to idle state */ 858 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO)); 859 860 DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", 861 __func__, phyaddr, phyreg, phydata); 862 863 SMC_SELECT_BANK(lp, 2); 864 } 865 866 /* 867 * Finds and reports the PHY address 868 */ 869 static void smc_phy_detect(struct net_device *dev) 870 { 871 struct smc_local *lp = netdev_priv(dev); 872 int phyaddr; 873 874 DBG(2, "%s: %s\n", dev->name, __func__); 875 876 lp->phy_type = 0; 877 878 /* 879 * Scan all 32 PHY addresses if necessary, starting at 880 * PHY#1 to PHY#31, and then PHY#0 last. 881 */ 882 for (phyaddr = 1; phyaddr < 33; ++phyaddr) { 883 unsigned int id1, id2; 884 885 /* Read the PHY identifiers */ 886 id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1); 887 id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2); 888 889 DBG(3, "%s: phy_id1=0x%x, phy_id2=0x%x\n", 890 dev->name, id1, id2); 891 892 /* Make sure it is a valid identifier */ 893 if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 && 894 id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) { 895 /* Save the PHY's address */ 896 lp->mii.phy_id = phyaddr & 31; 897 lp->phy_type = id1 << 16 | id2; 898 break; 899 } 900 } 901 } 902 903 /* 904 * Sets the PHY to a configuration as determined by the user 905 */ 906 static int smc_phy_fixed(struct net_device *dev) 907 { 908 struct smc_local *lp = netdev_priv(dev); 909 void __iomem *ioaddr = lp->base; 910 int phyaddr = lp->mii.phy_id; 911 int bmcr, cfg1; 912 913 DBG(3, "%s: %s\n", dev->name, __func__); 914 915 /* Enter Link Disable state */ 916 cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG); 917 cfg1 |= PHY_CFG1_LNKDIS; 918 smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1); 919 920 /* 921 * Set our fixed capabilities 922 * Disable auto-negotiation 923 */ 924 bmcr = 0; 925 926 if (lp->ctl_rfduplx) 927 bmcr |= BMCR_FULLDPLX; 928 929 if (lp->ctl_rspeed == 100) 930 bmcr |= BMCR_SPEED100; 931 932 /* Write our capabilities to the phy control register */ 933 smc_phy_write(dev, phyaddr, MII_BMCR, bmcr); 934 935 /* Re-Configure the Receive/Phy Control register */ 936 SMC_SELECT_BANK(lp, 0); 937 SMC_SET_RPC(lp, lp->rpc_cur_mode); 938 SMC_SELECT_BANK(lp, 2); 939 940 return 1; 941 } 942 943 /** 944 * smc_phy_reset - reset the phy 945 * @dev: net device 946 * @phy: phy address 947 * 948 * Issue a software reset for the specified PHY and 949 * wait up to 100ms for the reset to complete. We should 950 * not access the PHY for 50ms after issuing the reset. 951 * 952 * The time to wait appears to be dependent on the PHY. 953 * 954 * Must be called with lp->lock locked. 955 */ 956 static int smc_phy_reset(struct net_device *dev, int phy) 957 { 958 struct smc_local *lp = netdev_priv(dev); 959 unsigned int bmcr; 960 int timeout; 961 962 smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET); 963 964 for (timeout = 2; timeout; timeout--) { 965 spin_unlock_irq(&lp->lock); 966 msleep(50); 967 spin_lock_irq(&lp->lock); 968 969 bmcr = smc_phy_read(dev, phy, MII_BMCR); 970 if (!(bmcr & BMCR_RESET)) 971 break; 972 } 973 974 return bmcr & BMCR_RESET; 975 } 976 977 /** 978 * smc_phy_powerdown - powerdown phy 979 * @dev: net device 980 * 981 * Power down the specified PHY 982 */ 983 static void smc_phy_powerdown(struct net_device *dev) 984 { 985 struct smc_local *lp = netdev_priv(dev); 986 unsigned int bmcr; 987 int phy = lp->mii.phy_id; 988 989 if (lp->phy_type == 0) 990 return; 991 992 /* We need to ensure that no calls to smc_phy_configure are 993 pending. 994 */ 995 cancel_work_sync(&lp->phy_configure); 996 997 bmcr = smc_phy_read(dev, phy, MII_BMCR); 998 smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN); 999 } 1000 1001 /** 1002 * smc_phy_check_media - check the media status and adjust TCR 1003 * @dev: net device 1004 * @init: set true for initialisation 1005 * 1006 * Select duplex mode depending on negotiation state. This 1007 * also updates our carrier state. 1008 */ 1009 static void smc_phy_check_media(struct net_device *dev, int init) 1010 { 1011 struct smc_local *lp = netdev_priv(dev); 1012 void __iomem *ioaddr = lp->base; 1013 1014 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) { 1015 /* duplex state has changed */ 1016 if (lp->mii.full_duplex) { 1017 lp->tcr_cur_mode |= TCR_SWFDUP; 1018 } else { 1019 lp->tcr_cur_mode &= ~TCR_SWFDUP; 1020 } 1021 1022 SMC_SELECT_BANK(lp, 0); 1023 SMC_SET_TCR(lp, lp->tcr_cur_mode); 1024 } 1025 } 1026 1027 /* 1028 * Configures the specified PHY through the MII management interface 1029 * using Autonegotiation. 1030 * Calls smc_phy_fixed() if the user has requested a certain config. 1031 * If RPC ANEG bit is set, the media selection is dependent purely on 1032 * the selection by the MII (either in the MII BMCR reg or the result 1033 * of autonegotiation.) If the RPC ANEG bit is cleared, the selection 1034 * is controlled by the RPC SPEED and RPC DPLX bits. 1035 */ 1036 static void smc_phy_configure(struct work_struct *work) 1037 { 1038 struct smc_local *lp = 1039 container_of(work, struct smc_local, phy_configure); 1040 struct net_device *dev = lp->dev; 1041 void __iomem *ioaddr = lp->base; 1042 int phyaddr = lp->mii.phy_id; 1043 int my_phy_caps; /* My PHY capabilities */ 1044 int my_ad_caps; /* My Advertised capabilities */ 1045 int status; 1046 1047 DBG(3, "%s:smc_program_phy()\n", dev->name); 1048 1049 spin_lock_irq(&lp->lock); 1050 1051 /* 1052 * We should not be called if phy_type is zero. 1053 */ 1054 if (lp->phy_type == 0) 1055 goto smc_phy_configure_exit; 1056 1057 if (smc_phy_reset(dev, phyaddr)) { 1058 printk("%s: PHY reset timed out\n", dev->name); 1059 goto smc_phy_configure_exit; 1060 } 1061 1062 /* 1063 * Enable PHY Interrupts (for register 18) 1064 * Interrupts listed here are disabled 1065 */ 1066 smc_phy_write(dev, phyaddr, PHY_MASK_REG, 1067 PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD | 1068 PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB | 1069 PHY_INT_SPDDET | PHY_INT_DPLXDET); 1070 1071 /* Configure the Receive/Phy Control register */ 1072 SMC_SELECT_BANK(lp, 0); 1073 SMC_SET_RPC(lp, lp->rpc_cur_mode); 1074 1075 /* If the user requested no auto neg, then go set his request */ 1076 if (lp->mii.force_media) { 1077 smc_phy_fixed(dev); 1078 goto smc_phy_configure_exit; 1079 } 1080 1081 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */ 1082 my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR); 1083 1084 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) { 1085 printk(KERN_INFO "Auto negotiation NOT supported\n"); 1086 smc_phy_fixed(dev); 1087 goto smc_phy_configure_exit; 1088 } 1089 1090 my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */ 1091 1092 if (my_phy_caps & BMSR_100BASE4) 1093 my_ad_caps |= ADVERTISE_100BASE4; 1094 if (my_phy_caps & BMSR_100FULL) 1095 my_ad_caps |= ADVERTISE_100FULL; 1096 if (my_phy_caps & BMSR_100HALF) 1097 my_ad_caps |= ADVERTISE_100HALF; 1098 if (my_phy_caps & BMSR_10FULL) 1099 my_ad_caps |= ADVERTISE_10FULL; 1100 if (my_phy_caps & BMSR_10HALF) 1101 my_ad_caps |= ADVERTISE_10HALF; 1102 1103 /* Disable capabilities not selected by our user */ 1104 if (lp->ctl_rspeed != 100) 1105 my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF); 1106 1107 if (!lp->ctl_rfduplx) 1108 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL); 1109 1110 /* Update our Auto-Neg Advertisement Register */ 1111 smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps); 1112 lp->mii.advertising = my_ad_caps; 1113 1114 /* 1115 * Read the register back. Without this, it appears that when 1116 * auto-negotiation is restarted, sometimes it isn't ready and 1117 * the link does not come up. 1118 */ 1119 status = smc_phy_read(dev, phyaddr, MII_ADVERTISE); 1120 1121 DBG(2, "%s: phy caps=%x\n", dev->name, my_phy_caps); 1122 DBG(2, "%s: phy advertised caps=%x\n", dev->name, my_ad_caps); 1123 1124 /* Restart auto-negotiation process in order to advertise my caps */ 1125 smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); 1126 1127 smc_phy_check_media(dev, 1); 1128 1129 smc_phy_configure_exit: 1130 SMC_SELECT_BANK(lp, 2); 1131 spin_unlock_irq(&lp->lock); 1132 } 1133 1134 /* 1135 * smc_phy_interrupt 1136 * 1137 * Purpose: Handle interrupts relating to PHY register 18. This is 1138 * called from the "hard" interrupt handler under our private spinlock. 1139 */ 1140 static void smc_phy_interrupt(struct net_device *dev) 1141 { 1142 struct smc_local *lp = netdev_priv(dev); 1143 int phyaddr = lp->mii.phy_id; 1144 int phy18; 1145 1146 DBG(2, "%s: %s\n", dev->name, __func__); 1147 1148 if (lp->phy_type == 0) 1149 return; 1150 1151 for(;;) { 1152 smc_phy_check_media(dev, 0); 1153 1154 /* Read PHY Register 18, Status Output */ 1155 phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG); 1156 if ((phy18 & PHY_INT_INT) == 0) 1157 break; 1158 } 1159 } 1160 1161 /*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/ 1162 1163 static void smc_10bt_check_media(struct net_device *dev, int init) 1164 { 1165 struct smc_local *lp = netdev_priv(dev); 1166 void __iomem *ioaddr = lp->base; 1167 unsigned int old_carrier, new_carrier; 1168 1169 old_carrier = netif_carrier_ok(dev) ? 1 : 0; 1170 1171 SMC_SELECT_BANK(lp, 0); 1172 new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0; 1173 SMC_SELECT_BANK(lp, 2); 1174 1175 if (init || (old_carrier != new_carrier)) { 1176 if (!new_carrier) { 1177 netif_carrier_off(dev); 1178 } else { 1179 netif_carrier_on(dev); 1180 } 1181 if (netif_msg_link(lp)) 1182 printk(KERN_INFO "%s: link %s\n", dev->name, 1183 new_carrier ? "up" : "down"); 1184 } 1185 } 1186 1187 static void smc_eph_interrupt(struct net_device *dev) 1188 { 1189 struct smc_local *lp = netdev_priv(dev); 1190 void __iomem *ioaddr = lp->base; 1191 unsigned int ctl; 1192 1193 smc_10bt_check_media(dev, 0); 1194 1195 SMC_SELECT_BANK(lp, 1); 1196 ctl = SMC_GET_CTL(lp); 1197 SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE); 1198 SMC_SET_CTL(lp, ctl); 1199 SMC_SELECT_BANK(lp, 2); 1200 } 1201 1202 /* 1203 * This is the main routine of the driver, to handle the device when 1204 * it needs some attention. 1205 */ 1206 static irqreturn_t smc_interrupt(int irq, void *dev_id) 1207 { 1208 struct net_device *dev = dev_id; 1209 struct smc_local *lp = netdev_priv(dev); 1210 void __iomem *ioaddr = lp->base; 1211 int status, mask, timeout, card_stats; 1212 int saved_pointer; 1213 1214 DBG(3, "%s: %s\n", dev->name, __func__); 1215 1216 spin_lock(&lp->lock); 1217 1218 /* A preamble may be used when there is a potential race 1219 * between the interruptible transmit functions and this 1220 * ISR. */ 1221 SMC_INTERRUPT_PREAMBLE; 1222 1223 saved_pointer = SMC_GET_PTR(lp); 1224 mask = SMC_GET_INT_MASK(lp); 1225 SMC_SET_INT_MASK(lp, 0); 1226 1227 /* set a timeout value, so I don't stay here forever */ 1228 timeout = MAX_IRQ_LOOPS; 1229 1230 do { 1231 status = SMC_GET_INT(lp); 1232 1233 DBG(2, "%s: INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n", 1234 dev->name, status, mask, 1235 ({ int meminfo; SMC_SELECT_BANK(lp, 0); 1236 meminfo = SMC_GET_MIR(lp); 1237 SMC_SELECT_BANK(lp, 2); meminfo; }), 1238 SMC_GET_FIFO(lp)); 1239 1240 status &= mask; 1241 if (!status) 1242 break; 1243 1244 if (status & IM_TX_INT) { 1245 /* do this before RX as it will free memory quickly */ 1246 DBG(3, "%s: TX int\n", dev->name); 1247 smc_tx(dev); 1248 SMC_ACK_INT(lp, IM_TX_INT); 1249 if (THROTTLE_TX_PKTS) 1250 netif_wake_queue(dev); 1251 } else if (status & IM_RCV_INT) { 1252 DBG(3, "%s: RX irq\n", dev->name); 1253 smc_rcv(dev); 1254 } else if (status & IM_ALLOC_INT) { 1255 DBG(3, "%s: Allocation irq\n", dev->name); 1256 tasklet_hi_schedule(&lp->tx_task); 1257 mask &= ~IM_ALLOC_INT; 1258 } else if (status & IM_TX_EMPTY_INT) { 1259 DBG(3, "%s: TX empty\n", dev->name); 1260 mask &= ~IM_TX_EMPTY_INT; 1261 1262 /* update stats */ 1263 SMC_SELECT_BANK(lp, 0); 1264 card_stats = SMC_GET_COUNTER(lp); 1265 SMC_SELECT_BANK(lp, 2); 1266 1267 /* single collisions */ 1268 dev->stats.collisions += card_stats & 0xF; 1269 card_stats >>= 4; 1270 1271 /* multiple collisions */ 1272 dev->stats.collisions += card_stats & 0xF; 1273 } else if (status & IM_RX_OVRN_INT) { 1274 DBG(1, "%s: RX overrun (EPH_ST 0x%04x)\n", dev->name, 1275 ({ int eph_st; SMC_SELECT_BANK(lp, 0); 1276 eph_st = SMC_GET_EPH_STATUS(lp); 1277 SMC_SELECT_BANK(lp, 2); eph_st; })); 1278 SMC_ACK_INT(lp, IM_RX_OVRN_INT); 1279 dev->stats.rx_errors++; 1280 dev->stats.rx_fifo_errors++; 1281 } else if (status & IM_EPH_INT) { 1282 smc_eph_interrupt(dev); 1283 } else if (status & IM_MDINT) { 1284 SMC_ACK_INT(lp, IM_MDINT); 1285 smc_phy_interrupt(dev); 1286 } else if (status & IM_ERCV_INT) { 1287 SMC_ACK_INT(lp, IM_ERCV_INT); 1288 PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT\n", dev->name); 1289 } 1290 } while (--timeout); 1291 1292 /* restore register states */ 1293 SMC_SET_PTR(lp, saved_pointer); 1294 SMC_SET_INT_MASK(lp, mask); 1295 spin_unlock(&lp->lock); 1296 1297 #ifndef CONFIG_NET_POLL_CONTROLLER 1298 if (timeout == MAX_IRQ_LOOPS) 1299 PRINTK("%s: spurious interrupt (mask = 0x%02x)\n", 1300 dev->name, mask); 1301 #endif 1302 DBG(3, "%s: Interrupt done (%d loops)\n", 1303 dev->name, MAX_IRQ_LOOPS - timeout); 1304 1305 /* 1306 * We return IRQ_HANDLED unconditionally here even if there was 1307 * nothing to do. There is a possibility that a packet might 1308 * get enqueued into the chip right after TX_EMPTY_INT is raised 1309 * but just before the CPU acknowledges the IRQ. 1310 * Better take an unneeded IRQ in some occasions than complexifying 1311 * the code for all cases. 1312 */ 1313 return IRQ_HANDLED; 1314 } 1315 1316 #ifdef CONFIG_NET_POLL_CONTROLLER 1317 /* 1318 * Polling receive - used by netconsole and other diagnostic tools 1319 * to allow network i/o with interrupts disabled. 1320 */ 1321 static void smc_poll_controller(struct net_device *dev) 1322 { 1323 disable_irq(dev->irq); 1324 smc_interrupt(dev->irq, dev); 1325 enable_irq(dev->irq); 1326 } 1327 #endif 1328 1329 /* Our watchdog timed out. Called by the networking layer */ 1330 static void smc_timeout(struct net_device *dev) 1331 { 1332 struct smc_local *lp = netdev_priv(dev); 1333 void __iomem *ioaddr = lp->base; 1334 int status, mask, eph_st, meminfo, fifo; 1335 1336 DBG(2, "%s: %s\n", dev->name, __func__); 1337 1338 spin_lock_irq(&lp->lock); 1339 status = SMC_GET_INT(lp); 1340 mask = SMC_GET_INT_MASK(lp); 1341 fifo = SMC_GET_FIFO(lp); 1342 SMC_SELECT_BANK(lp, 0); 1343 eph_st = SMC_GET_EPH_STATUS(lp); 1344 meminfo = SMC_GET_MIR(lp); 1345 SMC_SELECT_BANK(lp, 2); 1346 spin_unlock_irq(&lp->lock); 1347 PRINTK( "%s: TX timeout (INT 0x%02x INTMASK 0x%02x " 1348 "MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n", 1349 dev->name, status, mask, meminfo, fifo, eph_st ); 1350 1351 smc_reset(dev); 1352 smc_enable(dev); 1353 1354 /* 1355 * Reconfiguring the PHY doesn't seem like a bad idea here, but 1356 * smc_phy_configure() calls msleep() which calls schedule_timeout() 1357 * which calls schedule(). Hence we use a work queue. 1358 */ 1359 if (lp->phy_type != 0) 1360 schedule_work(&lp->phy_configure); 1361 1362 /* We can accept TX packets again */ 1363 dev->trans_start = jiffies; /* prevent tx timeout */ 1364 netif_wake_queue(dev); 1365 } 1366 1367 /* 1368 * This routine will, depending on the values passed to it, 1369 * either make it accept multicast packets, go into 1370 * promiscuous mode (for TCPDUMP and cousins) or accept 1371 * a select set of multicast packets 1372 */ 1373 static void smc_set_multicast_list(struct net_device *dev) 1374 { 1375 struct smc_local *lp = netdev_priv(dev); 1376 void __iomem *ioaddr = lp->base; 1377 unsigned char multicast_table[8]; 1378 int update_multicast = 0; 1379 1380 DBG(2, "%s: %s\n", dev->name, __func__); 1381 1382 if (dev->flags & IFF_PROMISC) { 1383 DBG(2, "%s: RCR_PRMS\n", dev->name); 1384 lp->rcr_cur_mode |= RCR_PRMS; 1385 } 1386 1387 /* BUG? I never disable promiscuous mode if multicasting was turned on. 1388 Now, I turn off promiscuous mode, but I don't do anything to multicasting 1389 when promiscuous mode is turned on. 1390 */ 1391 1392 /* 1393 * Here, I am setting this to accept all multicast packets. 1394 * I don't need to zero the multicast table, because the flag is 1395 * checked before the table is 1396 */ 1397 else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) { 1398 DBG(2, "%s: RCR_ALMUL\n", dev->name); 1399 lp->rcr_cur_mode |= RCR_ALMUL; 1400 } 1401 1402 /* 1403 * This sets the internal hardware table to filter out unwanted 1404 * multicast packets before they take up memory. 1405 * 1406 * The SMC chip uses a hash table where the high 6 bits of the CRC of 1407 * address are the offset into the table. If that bit is 1, then the 1408 * multicast packet is accepted. Otherwise, it's dropped silently. 1409 * 1410 * To use the 6 bits as an offset into the table, the high 3 bits are 1411 * the number of the 8 bit register, while the low 3 bits are the bit 1412 * within that register. 1413 */ 1414 else if (!netdev_mc_empty(dev)) { 1415 struct netdev_hw_addr *ha; 1416 1417 /* table for flipping the order of 3 bits */ 1418 static const unsigned char invert3[] = {0, 4, 2, 6, 1, 5, 3, 7}; 1419 1420 /* start with a table of all zeros: reject all */ 1421 memset(multicast_table, 0, sizeof(multicast_table)); 1422 1423 netdev_for_each_mc_addr(ha, dev) { 1424 int position; 1425 1426 /* only use the low order bits */ 1427 position = crc32_le(~0, ha->addr, 6) & 0x3f; 1428 1429 /* do some messy swapping to put the bit in the right spot */ 1430 multicast_table[invert3[position&7]] |= 1431 (1<<invert3[(position>>3)&7]); 1432 } 1433 1434 /* be sure I get rid of flags I might have set */ 1435 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); 1436 1437 /* now, the table can be loaded into the chipset */ 1438 update_multicast = 1; 1439 } else { 1440 DBG(2, "%s: ~(RCR_PRMS|RCR_ALMUL)\n", dev->name); 1441 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); 1442 1443 /* 1444 * since I'm disabling all multicast entirely, I need to 1445 * clear the multicast list 1446 */ 1447 memset(multicast_table, 0, sizeof(multicast_table)); 1448 update_multicast = 1; 1449 } 1450 1451 spin_lock_irq(&lp->lock); 1452 SMC_SELECT_BANK(lp, 0); 1453 SMC_SET_RCR(lp, lp->rcr_cur_mode); 1454 if (update_multicast) { 1455 SMC_SELECT_BANK(lp, 3); 1456 SMC_SET_MCAST(lp, multicast_table); 1457 } 1458 SMC_SELECT_BANK(lp, 2); 1459 spin_unlock_irq(&lp->lock); 1460 } 1461 1462 1463 /* 1464 * Open and Initialize the board 1465 * 1466 * Set up everything, reset the card, etc.. 1467 */ 1468 static int 1469 smc_open(struct net_device *dev) 1470 { 1471 struct smc_local *lp = netdev_priv(dev); 1472 1473 DBG(2, "%s: %s\n", dev->name, __func__); 1474 1475 /* Setup the default Register Modes */ 1476 lp->tcr_cur_mode = TCR_DEFAULT; 1477 lp->rcr_cur_mode = RCR_DEFAULT; 1478 lp->rpc_cur_mode = RPC_DEFAULT | 1479 lp->cfg.leda << RPC_LSXA_SHFT | 1480 lp->cfg.ledb << RPC_LSXB_SHFT; 1481 1482 /* 1483 * If we are not using a MII interface, we need to 1484 * monitor our own carrier signal to detect faults. 1485 */ 1486 if (lp->phy_type == 0) 1487 lp->tcr_cur_mode |= TCR_MON_CSN; 1488 1489 /* reset the hardware */ 1490 smc_reset(dev); 1491 smc_enable(dev); 1492 1493 /* Configure the PHY, initialize the link state */ 1494 if (lp->phy_type != 0) 1495 smc_phy_configure(&lp->phy_configure); 1496 else { 1497 spin_lock_irq(&lp->lock); 1498 smc_10bt_check_media(dev, 1); 1499 spin_unlock_irq(&lp->lock); 1500 } 1501 1502 netif_start_queue(dev); 1503 return 0; 1504 } 1505 1506 /* 1507 * smc_close 1508 * 1509 * this makes the board clean up everything that it can 1510 * and not talk to the outside world. Caused by 1511 * an 'ifconfig ethX down' 1512 */ 1513 static int smc_close(struct net_device *dev) 1514 { 1515 struct smc_local *lp = netdev_priv(dev); 1516 1517 DBG(2, "%s: %s\n", dev->name, __func__); 1518 1519 netif_stop_queue(dev); 1520 netif_carrier_off(dev); 1521 1522 /* clear everything */ 1523 smc_shutdown(dev); 1524 tasklet_kill(&lp->tx_task); 1525 smc_phy_powerdown(dev); 1526 return 0; 1527 } 1528 1529 /* 1530 * Ethtool support 1531 */ 1532 static int 1533 smc_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) 1534 { 1535 struct smc_local *lp = netdev_priv(dev); 1536 int ret; 1537 1538 cmd->maxtxpkt = 1; 1539 cmd->maxrxpkt = 1; 1540 1541 if (lp->phy_type != 0) { 1542 spin_lock_irq(&lp->lock); 1543 ret = mii_ethtool_gset(&lp->mii, cmd); 1544 spin_unlock_irq(&lp->lock); 1545 } else { 1546 cmd->supported = SUPPORTED_10baseT_Half | 1547 SUPPORTED_10baseT_Full | 1548 SUPPORTED_TP | SUPPORTED_AUI; 1549 1550 if (lp->ctl_rspeed == 10) 1551 ethtool_cmd_speed_set(cmd, SPEED_10); 1552 else if (lp->ctl_rspeed == 100) 1553 ethtool_cmd_speed_set(cmd, SPEED_100); 1554 1555 cmd->autoneg = AUTONEG_DISABLE; 1556 cmd->transceiver = XCVR_INTERNAL; 1557 cmd->port = 0; 1558 cmd->duplex = lp->tcr_cur_mode & TCR_SWFDUP ? DUPLEX_FULL : DUPLEX_HALF; 1559 1560 ret = 0; 1561 } 1562 1563 return ret; 1564 } 1565 1566 static int 1567 smc_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) 1568 { 1569 struct smc_local *lp = netdev_priv(dev); 1570 int ret; 1571 1572 if (lp->phy_type != 0) { 1573 spin_lock_irq(&lp->lock); 1574 ret = mii_ethtool_sset(&lp->mii, cmd); 1575 spin_unlock_irq(&lp->lock); 1576 } else { 1577 if (cmd->autoneg != AUTONEG_DISABLE || 1578 cmd->speed != SPEED_10 || 1579 (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) || 1580 (cmd->port != PORT_TP && cmd->port != PORT_AUI)) 1581 return -EINVAL; 1582 1583 // lp->port = cmd->port; 1584 lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL; 1585 1586 // if (netif_running(dev)) 1587 // smc_set_port(dev); 1588 1589 ret = 0; 1590 } 1591 1592 return ret; 1593 } 1594 1595 static void 1596 smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1597 { 1598 strlcpy(info->driver, CARDNAME, sizeof(info->driver)); 1599 strlcpy(info->version, version, sizeof(info->version)); 1600 strlcpy(info->bus_info, dev_name(dev->dev.parent), 1601 sizeof(info->bus_info)); 1602 } 1603 1604 static int smc_ethtool_nwayreset(struct net_device *dev) 1605 { 1606 struct smc_local *lp = netdev_priv(dev); 1607 int ret = -EINVAL; 1608 1609 if (lp->phy_type != 0) { 1610 spin_lock_irq(&lp->lock); 1611 ret = mii_nway_restart(&lp->mii); 1612 spin_unlock_irq(&lp->lock); 1613 } 1614 1615 return ret; 1616 } 1617 1618 static u32 smc_ethtool_getmsglevel(struct net_device *dev) 1619 { 1620 struct smc_local *lp = netdev_priv(dev); 1621 return lp->msg_enable; 1622 } 1623 1624 static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level) 1625 { 1626 struct smc_local *lp = netdev_priv(dev); 1627 lp->msg_enable = level; 1628 } 1629 1630 static int smc_write_eeprom_word(struct net_device *dev, u16 addr, u16 word) 1631 { 1632 u16 ctl; 1633 struct smc_local *lp = netdev_priv(dev); 1634 void __iomem *ioaddr = lp->base; 1635 1636 spin_lock_irq(&lp->lock); 1637 /* load word into GP register */ 1638 SMC_SELECT_BANK(lp, 1); 1639 SMC_SET_GP(lp, word); 1640 /* set the address to put the data in EEPROM */ 1641 SMC_SELECT_BANK(lp, 2); 1642 SMC_SET_PTR(lp, addr); 1643 /* tell it to write */ 1644 SMC_SELECT_BANK(lp, 1); 1645 ctl = SMC_GET_CTL(lp); 1646 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE)); 1647 /* wait for it to finish */ 1648 do { 1649 udelay(1); 1650 } while (SMC_GET_CTL(lp) & CTL_STORE); 1651 /* clean up */ 1652 SMC_SET_CTL(lp, ctl); 1653 SMC_SELECT_BANK(lp, 2); 1654 spin_unlock_irq(&lp->lock); 1655 return 0; 1656 } 1657 1658 static int smc_read_eeprom_word(struct net_device *dev, u16 addr, u16 *word) 1659 { 1660 u16 ctl; 1661 struct smc_local *lp = netdev_priv(dev); 1662 void __iomem *ioaddr = lp->base; 1663 1664 spin_lock_irq(&lp->lock); 1665 /* set the EEPROM address to get the data from */ 1666 SMC_SELECT_BANK(lp, 2); 1667 SMC_SET_PTR(lp, addr | PTR_READ); 1668 /* tell it to load */ 1669 SMC_SELECT_BANK(lp, 1); 1670 SMC_SET_GP(lp, 0xffff); /* init to known */ 1671 ctl = SMC_GET_CTL(lp); 1672 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD)); 1673 /* wait for it to finish */ 1674 do { 1675 udelay(1); 1676 } while (SMC_GET_CTL(lp) & CTL_RELOAD); 1677 /* read word from GP register */ 1678 *word = SMC_GET_GP(lp); 1679 /* clean up */ 1680 SMC_SET_CTL(lp, ctl); 1681 SMC_SELECT_BANK(lp, 2); 1682 spin_unlock_irq(&lp->lock); 1683 return 0; 1684 } 1685 1686 static int smc_ethtool_geteeprom_len(struct net_device *dev) 1687 { 1688 return 0x23 * 2; 1689 } 1690 1691 static int smc_ethtool_geteeprom(struct net_device *dev, 1692 struct ethtool_eeprom *eeprom, u8 *data) 1693 { 1694 int i; 1695 int imax; 1696 1697 DBG(1, "Reading %d bytes at %d(0x%x)\n", 1698 eeprom->len, eeprom->offset, eeprom->offset); 1699 imax = smc_ethtool_geteeprom_len(dev); 1700 for (i = 0; i < eeprom->len; i += 2) { 1701 int ret; 1702 u16 wbuf; 1703 int offset = i + eeprom->offset; 1704 if (offset > imax) 1705 break; 1706 ret = smc_read_eeprom_word(dev, offset >> 1, &wbuf); 1707 if (ret != 0) 1708 return ret; 1709 DBG(2, "Read 0x%x from 0x%x\n", wbuf, offset >> 1); 1710 data[i] = (wbuf >> 8) & 0xff; 1711 data[i+1] = wbuf & 0xff; 1712 } 1713 return 0; 1714 } 1715 1716 static int smc_ethtool_seteeprom(struct net_device *dev, 1717 struct ethtool_eeprom *eeprom, u8 *data) 1718 { 1719 int i; 1720 int imax; 1721 1722 DBG(1, "Writing %d bytes to %d(0x%x)\n", 1723 eeprom->len, eeprom->offset, eeprom->offset); 1724 imax = smc_ethtool_geteeprom_len(dev); 1725 for (i = 0; i < eeprom->len; i += 2) { 1726 int ret; 1727 u16 wbuf; 1728 int offset = i + eeprom->offset; 1729 if (offset > imax) 1730 break; 1731 wbuf = (data[i] << 8) | data[i + 1]; 1732 DBG(2, "Writing 0x%x to 0x%x\n", wbuf, offset >> 1); 1733 ret = smc_write_eeprom_word(dev, offset >> 1, wbuf); 1734 if (ret != 0) 1735 return ret; 1736 } 1737 return 0; 1738 } 1739 1740 1741 static const struct ethtool_ops smc_ethtool_ops = { 1742 .get_settings = smc_ethtool_getsettings, 1743 .set_settings = smc_ethtool_setsettings, 1744 .get_drvinfo = smc_ethtool_getdrvinfo, 1745 1746 .get_msglevel = smc_ethtool_getmsglevel, 1747 .set_msglevel = smc_ethtool_setmsglevel, 1748 .nway_reset = smc_ethtool_nwayreset, 1749 .get_link = ethtool_op_get_link, 1750 .get_eeprom_len = smc_ethtool_geteeprom_len, 1751 .get_eeprom = smc_ethtool_geteeprom, 1752 .set_eeprom = smc_ethtool_seteeprom, 1753 }; 1754 1755 static const struct net_device_ops smc_netdev_ops = { 1756 .ndo_open = smc_open, 1757 .ndo_stop = smc_close, 1758 .ndo_start_xmit = smc_hard_start_xmit, 1759 .ndo_tx_timeout = smc_timeout, 1760 .ndo_set_rx_mode = smc_set_multicast_list, 1761 .ndo_change_mtu = eth_change_mtu, 1762 .ndo_validate_addr = eth_validate_addr, 1763 .ndo_set_mac_address = eth_mac_addr, 1764 #ifdef CONFIG_NET_POLL_CONTROLLER 1765 .ndo_poll_controller = smc_poll_controller, 1766 #endif 1767 }; 1768 1769 /* 1770 * smc_findirq 1771 * 1772 * This routine has a simple purpose -- make the SMC chip generate an 1773 * interrupt, so an auto-detect routine can detect it, and find the IRQ, 1774 */ 1775 /* 1776 * does this still work? 1777 * 1778 * I just deleted auto_irq.c, since it was never built... 1779 * --jgarzik 1780 */ 1781 static int smc_findirq(struct smc_local *lp) 1782 { 1783 void __iomem *ioaddr = lp->base; 1784 int timeout = 20; 1785 unsigned long cookie; 1786 1787 DBG(2, "%s: %s\n", CARDNAME, __func__); 1788 1789 cookie = probe_irq_on(); 1790 1791 /* 1792 * What I try to do here is trigger an ALLOC_INT. This is done 1793 * by allocating a small chunk of memory, which will give an interrupt 1794 * when done. 1795 */ 1796 /* enable ALLOCation interrupts ONLY */ 1797 SMC_SELECT_BANK(lp, 2); 1798 SMC_SET_INT_MASK(lp, IM_ALLOC_INT); 1799 1800 /* 1801 * Allocate 512 bytes of memory. Note that the chip was just 1802 * reset so all the memory is available 1803 */ 1804 SMC_SET_MMU_CMD(lp, MC_ALLOC | 1); 1805 1806 /* 1807 * Wait until positive that the interrupt has been generated 1808 */ 1809 do { 1810 int int_status; 1811 udelay(10); 1812 int_status = SMC_GET_INT(lp); 1813 if (int_status & IM_ALLOC_INT) 1814 break; /* got the interrupt */ 1815 } while (--timeout); 1816 1817 /* 1818 * there is really nothing that I can do here if timeout fails, 1819 * as autoirq_report will return a 0 anyway, which is what I 1820 * want in this case. Plus, the clean up is needed in both 1821 * cases. 1822 */ 1823 1824 /* and disable all interrupts again */ 1825 SMC_SET_INT_MASK(lp, 0); 1826 1827 /* and return what I found */ 1828 return probe_irq_off(cookie); 1829 } 1830 1831 /* 1832 * Function: smc_probe(unsigned long ioaddr) 1833 * 1834 * Purpose: 1835 * Tests to see if a given ioaddr points to an SMC91x chip. 1836 * Returns a 0 on success 1837 * 1838 * Algorithm: 1839 * (1) see if the high byte of BANK_SELECT is 0x33 1840 * (2) compare the ioaddr with the base register's address 1841 * (3) see if I recognize the chip ID in the appropriate register 1842 * 1843 * Here I do typical initialization tasks. 1844 * 1845 * o Initialize the structure if needed 1846 * o print out my vanity message if not done so already 1847 * o print out what type of hardware is detected 1848 * o print out the ethernet address 1849 * o find the IRQ 1850 * o set up my private data 1851 * o configure the dev structure with my subroutines 1852 * o actually GRAB the irq. 1853 * o GRAB the region 1854 */ 1855 static int smc_probe(struct net_device *dev, void __iomem *ioaddr, 1856 unsigned long irq_flags) 1857 { 1858 struct smc_local *lp = netdev_priv(dev); 1859 static int version_printed = 0; 1860 int retval; 1861 unsigned int val, revision_register; 1862 const char *version_string; 1863 1864 DBG(2, "%s: %s\n", CARDNAME, __func__); 1865 1866 /* First, see if the high byte is 0x33 */ 1867 val = SMC_CURRENT_BANK(lp); 1868 DBG(2, "%s: bank signature probe returned 0x%04x\n", CARDNAME, val); 1869 if ((val & 0xFF00) != 0x3300) { 1870 if ((val & 0xFF) == 0x33) { 1871 printk(KERN_WARNING 1872 "%s: Detected possible byte-swapped interface" 1873 " at IOADDR %p\n", CARDNAME, ioaddr); 1874 } 1875 retval = -ENODEV; 1876 goto err_out; 1877 } 1878 1879 /* 1880 * The above MIGHT indicate a device, but I need to write to 1881 * further test this. 1882 */ 1883 SMC_SELECT_BANK(lp, 0); 1884 val = SMC_CURRENT_BANK(lp); 1885 if ((val & 0xFF00) != 0x3300) { 1886 retval = -ENODEV; 1887 goto err_out; 1888 } 1889 1890 /* 1891 * well, we've already written once, so hopefully another 1892 * time won't hurt. This time, I need to switch the bank 1893 * register to bank 1, so I can access the base address 1894 * register 1895 */ 1896 SMC_SELECT_BANK(lp, 1); 1897 val = SMC_GET_BASE(lp); 1898 val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT; 1899 if (((unsigned int)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) { 1900 printk("%s: IOADDR %p doesn't match configuration (%x).\n", 1901 CARDNAME, ioaddr, val); 1902 } 1903 1904 /* 1905 * check if the revision register is something that I 1906 * recognize. These might need to be added to later, 1907 * as future revisions could be added. 1908 */ 1909 SMC_SELECT_BANK(lp, 3); 1910 revision_register = SMC_GET_REV(lp); 1911 DBG(2, "%s: revision = 0x%04x\n", CARDNAME, revision_register); 1912 version_string = chip_ids[ (revision_register >> 4) & 0xF]; 1913 if (!version_string || (revision_register & 0xff00) != 0x3300) { 1914 /* I don't recognize this chip, so... */ 1915 printk("%s: IO %p: Unrecognized revision register 0x%04x" 1916 ", Contact author.\n", CARDNAME, 1917 ioaddr, revision_register); 1918 1919 retval = -ENODEV; 1920 goto err_out; 1921 } 1922 1923 /* At this point I'll assume that the chip is an SMC91x. */ 1924 if (version_printed++ == 0) 1925 printk("%s", version); 1926 1927 /* fill in some of the fields */ 1928 dev->base_addr = (unsigned long)ioaddr; 1929 lp->base = ioaddr; 1930 lp->version = revision_register & 0xff; 1931 spin_lock_init(&lp->lock); 1932 1933 /* Get the MAC address */ 1934 SMC_SELECT_BANK(lp, 1); 1935 SMC_GET_MAC_ADDR(lp, dev->dev_addr); 1936 1937 /* now, reset the chip, and put it into a known state */ 1938 smc_reset(dev); 1939 1940 /* 1941 * If dev->irq is 0, then the device has to be banged on to see 1942 * what the IRQ is. 1943 * 1944 * This banging doesn't always detect the IRQ, for unknown reasons. 1945 * a workaround is to reset the chip and try again. 1946 * 1947 * Interestingly, the DOS packet driver *SETS* the IRQ on the card to 1948 * be what is requested on the command line. I don't do that, mostly 1949 * because the card that I have uses a non-standard method of accessing 1950 * the IRQs, and because this _should_ work in most configurations. 1951 * 1952 * Specifying an IRQ is done with the assumption that the user knows 1953 * what (s)he is doing. No checking is done!!!! 1954 */ 1955 if (dev->irq < 1) { 1956 int trials; 1957 1958 trials = 3; 1959 while (trials--) { 1960 dev->irq = smc_findirq(lp); 1961 if (dev->irq) 1962 break; 1963 /* kick the card and try again */ 1964 smc_reset(dev); 1965 } 1966 } 1967 if (dev->irq == 0) { 1968 printk("%s: Couldn't autodetect your IRQ. Use irq=xx.\n", 1969 dev->name); 1970 retval = -ENODEV; 1971 goto err_out; 1972 } 1973 dev->irq = irq_canonicalize(dev->irq); 1974 1975 /* Fill in the fields of the device structure with ethernet values. */ 1976 ether_setup(dev); 1977 1978 dev->watchdog_timeo = msecs_to_jiffies(watchdog); 1979 dev->netdev_ops = &smc_netdev_ops; 1980 dev->ethtool_ops = &smc_ethtool_ops; 1981 1982 tasklet_init(&lp->tx_task, smc_hardware_send_pkt, (unsigned long)dev); 1983 INIT_WORK(&lp->phy_configure, smc_phy_configure); 1984 lp->dev = dev; 1985 lp->mii.phy_id_mask = 0x1f; 1986 lp->mii.reg_num_mask = 0x1f; 1987 lp->mii.force_media = 0; 1988 lp->mii.full_duplex = 0; 1989 lp->mii.dev = dev; 1990 lp->mii.mdio_read = smc_phy_read; 1991 lp->mii.mdio_write = smc_phy_write; 1992 1993 /* 1994 * Locate the phy, if any. 1995 */ 1996 if (lp->version >= (CHIP_91100 << 4)) 1997 smc_phy_detect(dev); 1998 1999 /* then shut everything down to save power */ 2000 smc_shutdown(dev); 2001 smc_phy_powerdown(dev); 2002 2003 /* Set default parameters */ 2004 lp->msg_enable = NETIF_MSG_LINK; 2005 lp->ctl_rfduplx = 0; 2006 lp->ctl_rspeed = 10; 2007 2008 if (lp->version >= (CHIP_91100 << 4)) { 2009 lp->ctl_rfduplx = 1; 2010 lp->ctl_rspeed = 100; 2011 } 2012 2013 /* Grab the IRQ */ 2014 retval = request_irq(dev->irq, smc_interrupt, irq_flags, dev->name, dev); 2015 if (retval) 2016 goto err_out; 2017 2018 #ifdef CONFIG_ARCH_PXA 2019 # ifdef SMC_USE_PXA_DMA 2020 lp->cfg.flags |= SMC91X_USE_DMA; 2021 # endif 2022 if (lp->cfg.flags & SMC91X_USE_DMA) { 2023 int dma = pxa_request_dma(dev->name, DMA_PRIO_LOW, 2024 smc_pxa_dma_irq, NULL); 2025 if (dma >= 0) 2026 dev->dma = dma; 2027 } 2028 #endif 2029 2030 retval = register_netdev(dev); 2031 if (retval == 0) { 2032 /* now, print out the card info, in a short format.. */ 2033 printk("%s: %s (rev %d) at %p IRQ %d", 2034 dev->name, version_string, revision_register & 0x0f, 2035 lp->base, dev->irq); 2036 2037 if (dev->dma != (unsigned char)-1) 2038 printk(" DMA %d", dev->dma); 2039 2040 printk("%s%s\n", 2041 lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "", 2042 THROTTLE_TX_PKTS ? " [throttle_tx]" : ""); 2043 2044 if (!is_valid_ether_addr(dev->dev_addr)) { 2045 printk("%s: Invalid ethernet MAC address. Please " 2046 "set using ifconfig\n", dev->name); 2047 } else { 2048 /* Print the Ethernet address */ 2049 printk("%s: Ethernet addr: %pM\n", 2050 dev->name, dev->dev_addr); 2051 } 2052 2053 if (lp->phy_type == 0) { 2054 PRINTK("%s: No PHY found\n", dev->name); 2055 } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) { 2056 PRINTK("%s: PHY LAN83C183 (LAN91C111 Internal)\n", dev->name); 2057 } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) { 2058 PRINTK("%s: PHY LAN83C180\n", dev->name); 2059 } 2060 } 2061 2062 err_out: 2063 #ifdef CONFIG_ARCH_PXA 2064 if (retval && dev->dma != (unsigned char)-1) 2065 pxa_free_dma(dev->dma); 2066 #endif 2067 return retval; 2068 } 2069 2070 static int smc_enable_device(struct platform_device *pdev) 2071 { 2072 struct net_device *ndev = platform_get_drvdata(pdev); 2073 struct smc_local *lp = netdev_priv(ndev); 2074 unsigned long flags; 2075 unsigned char ecor, ecsr; 2076 void __iomem *addr; 2077 struct resource * res; 2078 2079 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2080 if (!res) 2081 return 0; 2082 2083 /* 2084 * Map the attribute space. This is overkill, but clean. 2085 */ 2086 addr = ioremap(res->start, ATTRIB_SIZE); 2087 if (!addr) 2088 return -ENOMEM; 2089 2090 /* 2091 * Reset the device. We must disable IRQs around this 2092 * since a reset causes the IRQ line become active. 2093 */ 2094 local_irq_save(flags); 2095 ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; 2096 writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); 2097 readb(addr + (ECOR << SMC_IO_SHIFT)); 2098 2099 /* 2100 * Wait 100us for the chip to reset. 2101 */ 2102 udelay(100); 2103 2104 /* 2105 * The device will ignore all writes to the enable bit while 2106 * reset is asserted, even if the reset bit is cleared in the 2107 * same write. Must clear reset first, then enable the device. 2108 */ 2109 writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); 2110 writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); 2111 2112 /* 2113 * Set the appropriate byte/word mode. 2114 */ 2115 ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; 2116 if (!SMC_16BIT(lp)) 2117 ecsr |= ECSR_IOIS8; 2118 writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); 2119 local_irq_restore(flags); 2120 2121 iounmap(addr); 2122 2123 /* 2124 * Wait for the chip to wake up. We could poll the control 2125 * register in the main register space, but that isn't mapped 2126 * yet. We know this is going to take 750us. 2127 */ 2128 msleep(1); 2129 2130 return 0; 2131 } 2132 2133 static int smc_request_attrib(struct platform_device *pdev, 2134 struct net_device *ndev) 2135 { 2136 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2137 struct smc_local *lp __maybe_unused = netdev_priv(ndev); 2138 2139 if (!res) 2140 return 0; 2141 2142 if (!request_mem_region(res->start, ATTRIB_SIZE, CARDNAME)) 2143 return -EBUSY; 2144 2145 return 0; 2146 } 2147 2148 static void smc_release_attrib(struct platform_device *pdev, 2149 struct net_device *ndev) 2150 { 2151 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2152 struct smc_local *lp __maybe_unused = netdev_priv(ndev); 2153 2154 if (res) 2155 release_mem_region(res->start, ATTRIB_SIZE); 2156 } 2157 2158 static inline void smc_request_datacs(struct platform_device *pdev, struct net_device *ndev) 2159 { 2160 if (SMC_CAN_USE_DATACS) { 2161 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32"); 2162 struct smc_local *lp = netdev_priv(ndev); 2163 2164 if (!res) 2165 return; 2166 2167 if(!request_mem_region(res->start, SMC_DATA_EXTENT, CARDNAME)) { 2168 printk(KERN_INFO "%s: failed to request datacs memory region.\n", CARDNAME); 2169 return; 2170 } 2171 2172 lp->datacs = ioremap(res->start, SMC_DATA_EXTENT); 2173 } 2174 } 2175 2176 static void smc_release_datacs(struct platform_device *pdev, struct net_device *ndev) 2177 { 2178 if (SMC_CAN_USE_DATACS) { 2179 struct smc_local *lp = netdev_priv(ndev); 2180 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32"); 2181 2182 if (lp->datacs) 2183 iounmap(lp->datacs); 2184 2185 lp->datacs = NULL; 2186 2187 if (res) 2188 release_mem_region(res->start, SMC_DATA_EXTENT); 2189 } 2190 } 2191 2192 /* 2193 * smc_init(void) 2194 * Input parameters: 2195 * dev->base_addr == 0, try to find all possible locations 2196 * dev->base_addr > 0x1ff, this is the address to check 2197 * dev->base_addr == <anything else>, return failure code 2198 * 2199 * Output: 2200 * 0 --> there is a device 2201 * anything else, error 2202 */ 2203 static int smc_drv_probe(struct platform_device *pdev) 2204 { 2205 struct smc91x_platdata *pd = dev_get_platdata(&pdev->dev); 2206 struct smc_local *lp; 2207 struct net_device *ndev; 2208 struct resource *res, *ires; 2209 unsigned int __iomem *addr; 2210 unsigned long irq_flags = SMC_IRQ_FLAGS; 2211 int ret; 2212 2213 ndev = alloc_etherdev(sizeof(struct smc_local)); 2214 if (!ndev) { 2215 ret = -ENOMEM; 2216 goto out; 2217 } 2218 SET_NETDEV_DEV(ndev, &pdev->dev); 2219 2220 /* get configuration from platform data, only allow use of 2221 * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set. 2222 */ 2223 2224 lp = netdev_priv(ndev); 2225 2226 if (pd) { 2227 memcpy(&lp->cfg, pd, sizeof(lp->cfg)); 2228 lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags); 2229 } else { 2230 lp->cfg.flags |= (SMC_CAN_USE_8BIT) ? SMC91X_USE_8BIT : 0; 2231 lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0; 2232 lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0; 2233 lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0; 2234 } 2235 2236 if (!lp->cfg.leda && !lp->cfg.ledb) { 2237 lp->cfg.leda = RPC_LSA_DEFAULT; 2238 lp->cfg.ledb = RPC_LSB_DEFAULT; 2239 } 2240 2241 ndev->dma = (unsigned char)-1; 2242 2243 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); 2244 if (!res) 2245 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2246 if (!res) { 2247 ret = -ENODEV; 2248 goto out_free_netdev; 2249 } 2250 2251 2252 if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) { 2253 ret = -EBUSY; 2254 goto out_free_netdev; 2255 } 2256 2257 ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 2258 if (!ires) { 2259 ret = -ENODEV; 2260 goto out_release_io; 2261 } 2262 2263 ndev->irq = ires->start; 2264 2265 if (irq_flags == -1 || ires->flags & IRQF_TRIGGER_MASK) 2266 irq_flags = ires->flags & IRQF_TRIGGER_MASK; 2267 2268 ret = smc_request_attrib(pdev, ndev); 2269 if (ret) 2270 goto out_release_io; 2271 #if defined(CONFIG_SA1100_ASSABET) 2272 neponset_ncr_set(NCR_ENET_OSC_EN); 2273 #endif 2274 platform_set_drvdata(pdev, ndev); 2275 ret = smc_enable_device(pdev); 2276 if (ret) 2277 goto out_release_attrib; 2278 2279 addr = ioremap(res->start, SMC_IO_EXTENT); 2280 if (!addr) { 2281 ret = -ENOMEM; 2282 goto out_release_attrib; 2283 } 2284 2285 #ifdef CONFIG_ARCH_PXA 2286 { 2287 struct smc_local *lp = netdev_priv(ndev); 2288 lp->device = &pdev->dev; 2289 lp->physaddr = res->start; 2290 } 2291 #endif 2292 2293 ret = smc_probe(ndev, addr, irq_flags); 2294 if (ret != 0) 2295 goto out_iounmap; 2296 2297 smc_request_datacs(pdev, ndev); 2298 2299 return 0; 2300 2301 out_iounmap: 2302 iounmap(addr); 2303 out_release_attrib: 2304 smc_release_attrib(pdev, ndev); 2305 out_release_io: 2306 release_mem_region(res->start, SMC_IO_EXTENT); 2307 out_free_netdev: 2308 free_netdev(ndev); 2309 out: 2310 printk("%s: not found (%d).\n", CARDNAME, ret); 2311 2312 return ret; 2313 } 2314 2315 static int smc_drv_remove(struct platform_device *pdev) 2316 { 2317 struct net_device *ndev = platform_get_drvdata(pdev); 2318 struct smc_local *lp = netdev_priv(ndev); 2319 struct resource *res; 2320 2321 unregister_netdev(ndev); 2322 2323 free_irq(ndev->irq, ndev); 2324 2325 #ifdef CONFIG_ARCH_PXA 2326 if (ndev->dma != (unsigned char)-1) 2327 pxa_free_dma(ndev->dma); 2328 #endif 2329 iounmap(lp->base); 2330 2331 smc_release_datacs(pdev,ndev); 2332 smc_release_attrib(pdev,ndev); 2333 2334 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); 2335 if (!res) 2336 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2337 release_mem_region(res->start, SMC_IO_EXTENT); 2338 2339 free_netdev(ndev); 2340 2341 return 0; 2342 } 2343 2344 static int smc_drv_suspend(struct device *dev) 2345 { 2346 struct platform_device *pdev = to_platform_device(dev); 2347 struct net_device *ndev = platform_get_drvdata(pdev); 2348 2349 if (ndev) { 2350 if (netif_running(ndev)) { 2351 netif_device_detach(ndev); 2352 smc_shutdown(ndev); 2353 smc_phy_powerdown(ndev); 2354 } 2355 } 2356 return 0; 2357 } 2358 2359 static int smc_drv_resume(struct device *dev) 2360 { 2361 struct platform_device *pdev = to_platform_device(dev); 2362 struct net_device *ndev = platform_get_drvdata(pdev); 2363 2364 if (ndev) { 2365 struct smc_local *lp = netdev_priv(ndev); 2366 smc_enable_device(pdev); 2367 if (netif_running(ndev)) { 2368 smc_reset(ndev); 2369 smc_enable(ndev); 2370 if (lp->phy_type != 0) 2371 smc_phy_configure(&lp->phy_configure); 2372 netif_device_attach(ndev); 2373 } 2374 } 2375 return 0; 2376 } 2377 2378 #ifdef CONFIG_OF 2379 static const struct of_device_id smc91x_match[] = { 2380 { .compatible = "smsc,lan91c94", }, 2381 { .compatible = "smsc,lan91c111", }, 2382 {}, 2383 }; 2384 MODULE_DEVICE_TABLE(of, smc91x_match); 2385 #endif 2386 2387 static struct dev_pm_ops smc_drv_pm_ops = { 2388 .suspend = smc_drv_suspend, 2389 .resume = smc_drv_resume, 2390 }; 2391 2392 static struct platform_driver smc_driver = { 2393 .probe = smc_drv_probe, 2394 .remove = smc_drv_remove, 2395 .driver = { 2396 .name = CARDNAME, 2397 .owner = THIS_MODULE, 2398 .pm = &smc_drv_pm_ops, 2399 .of_match_table = of_match_ptr(smc91x_match), 2400 }, 2401 }; 2402 2403 module_platform_driver(smc_driver); 2404