1 /* Silan SC92031 PCI Fast Ethernet Adapter driver 2 * 3 * Based on vendor drivers: 4 * Silan Fast Ethernet Netcard Driver: 5 * MODULE_AUTHOR ("gaoyonghong"); 6 * MODULE_DESCRIPTION ("SILAN Fast Ethernet driver"); 7 * MODULE_LICENSE("GPL"); 8 * 8139D Fast Ethernet driver: 9 * (C) 2002 by gaoyonghong 10 * MODULE_AUTHOR ("gaoyonghong"); 11 * MODULE_DESCRIPTION ("Rsltek 8139D PCI Fast Ethernet Adapter driver"); 12 * MODULE_LICENSE("GPL"); 13 * Both are almost identical and seem to be based on pci-skeleton.c 14 * 15 * Rewritten for 2.6 by Cesar Eduardo Barros 16 * 17 * A datasheet for this chip can be found at 18 * http://www.silan.com.cn/english/product/pdf/SC92031AY.pdf 19 */ 20 21 /* Note about set_mac_address: I don't know how to change the hardware 22 * matching, so you need to enable IFF_PROMISC when using it. 23 */ 24 25 #include <linux/interrupt.h> 26 #include <linux/module.h> 27 #include <linux/kernel.h> 28 #include <linux/delay.h> 29 #include <linux/pci.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/netdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/ethtool.h> 34 #include <linux/mii.h> 35 #include <linux/crc32.h> 36 37 #include <asm/irq.h> 38 39 #define SC92031_NAME "sc92031" 40 41 /* BAR 0 is MMIO, BAR 1 is PIO */ 42 #define SC92031_USE_PIO 0 43 44 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */ 45 static int multicast_filter_limit = 64; 46 module_param(multicast_filter_limit, int, 0); 47 MODULE_PARM_DESC(multicast_filter_limit, 48 "Maximum number of filtered multicast addresses"); 49 50 static int media; 51 module_param(media, int, 0); 52 MODULE_PARM_DESC(media, "Media type (0x00 = autodetect," 53 " 0x01 = 10M half, 0x02 = 10M full," 54 " 0x04 = 100M half, 0x08 = 100M full)"); 55 56 /* Size of the in-memory receive ring. */ 57 #define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K ,4==128K*/ 58 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX) 59 60 /* Number of Tx descriptor registers. */ 61 #define NUM_TX_DESC 4 62 63 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/ 64 #define MAX_ETH_FRAME_SIZE 1536 65 66 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */ 67 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE 68 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC) 69 70 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */ 71 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */ 72 73 /* Time in jiffies before concluding the transmitter is hung. */ 74 #define TX_TIMEOUT (4*HZ) 75 76 #define SILAN_STATS_NUM 2 /* number of ETHTOOL_GSTATS */ 77 78 /* media options */ 79 #define AUTOSELECT 0x00 80 #define M10_HALF 0x01 81 #define M10_FULL 0x02 82 #define M100_HALF 0x04 83 #define M100_FULL 0x08 84 85 /* Symbolic offsets to registers. */ 86 enum silan_registers { 87 Config0 = 0x00, // Config0 88 Config1 = 0x04, // Config1 89 RxBufWPtr = 0x08, // Rx buffer writer poiter 90 IntrStatus = 0x0C, // Interrupt status 91 IntrMask = 0x10, // Interrupt mask 92 RxbufAddr = 0x14, // Rx buffer start address 93 RxBufRPtr = 0x18, // Rx buffer read pointer 94 Txstatusall = 0x1C, // Transmit status of all descriptors 95 TxStatus0 = 0x20, // Transmit status (Four 32bit registers). 96 TxAddr0 = 0x30, // Tx descriptors (also four 32bit). 97 RxConfig = 0x40, // Rx configuration 98 MAC0 = 0x44, // Ethernet hardware address. 99 MAR0 = 0x4C, // Multicast filter. 100 RxStatus0 = 0x54, // Rx status 101 TxConfig = 0x5C, // Tx configuration 102 PhyCtrl = 0x60, // physical control 103 FlowCtrlConfig = 0x64, // flow control 104 Miicmd0 = 0x68, // Mii command0 register 105 Miicmd1 = 0x6C, // Mii command1 register 106 Miistatus = 0x70, // Mii status register 107 Timercnt = 0x74, // Timer counter register 108 TimerIntr = 0x78, // Timer interrupt register 109 PMConfig = 0x7C, // Power Manager configuration 110 CRC0 = 0x80, // Power Manager CRC ( Two 32bit regisers) 111 Wakeup0 = 0x88, // power Manager wakeup( Eight 64bit regiser) 112 LSBCRC0 = 0xC8, // power Manager LSBCRC(Two 32bit regiser) 113 TestD0 = 0xD0, 114 TestD4 = 0xD4, 115 TestD8 = 0xD8, 116 }; 117 118 #define MII_JAB 16 119 #define MII_OutputStatus 24 120 121 #define PHY_16_JAB_ENB 0x1000 122 #define PHY_16_PORT_ENB 0x1 123 124 enum IntrStatusBits { 125 LinkFail = 0x80000000, 126 LinkOK = 0x40000000, 127 TimeOut = 0x20000000, 128 RxOverflow = 0x0040, 129 RxOK = 0x0020, 130 TxOK = 0x0001, 131 IntrBits = LinkFail|LinkOK|TimeOut|RxOverflow|RxOK|TxOK, 132 }; 133 134 enum TxStatusBits { 135 TxCarrierLost = 0x20000000, 136 TxAborted = 0x10000000, 137 TxOutOfWindow = 0x08000000, 138 TxNccShift = 22, 139 EarlyTxThresShift = 16, 140 TxStatOK = 0x8000, 141 TxUnderrun = 0x4000, 142 TxOwn = 0x2000, 143 }; 144 145 enum RxStatusBits { 146 RxStatesOK = 0x80000, 147 RxBadAlign = 0x40000, 148 RxHugeFrame = 0x20000, 149 RxSmallFrame = 0x10000, 150 RxCRCOK = 0x8000, 151 RxCrlFrame = 0x4000, 152 Rx_Broadcast = 0x2000, 153 Rx_Multicast = 0x1000, 154 RxAddrMatch = 0x0800, 155 MiiErr = 0x0400, 156 }; 157 158 enum RxConfigBits { 159 RxFullDx = 0x80000000, 160 RxEnb = 0x40000000, 161 RxSmall = 0x20000000, 162 RxHuge = 0x10000000, 163 RxErr = 0x08000000, 164 RxAllphys = 0x04000000, 165 RxMulticast = 0x02000000, 166 RxBroadcast = 0x01000000, 167 RxLoopBack = (1 << 23) | (1 << 22), 168 LowThresholdShift = 12, 169 HighThresholdShift = 2, 170 }; 171 172 enum TxConfigBits { 173 TxFullDx = 0x80000000, 174 TxEnb = 0x40000000, 175 TxEnbPad = 0x20000000, 176 TxEnbHuge = 0x10000000, 177 TxEnbFCS = 0x08000000, 178 TxNoBackOff = 0x04000000, 179 TxEnbPrem = 0x02000000, 180 TxCareLostCrs = 0x1000000, 181 TxExdCollNum = 0xf00000, 182 TxDataRate = 0x80000, 183 }; 184 185 enum PhyCtrlconfigbits { 186 PhyCtrlAne = 0x80000000, 187 PhyCtrlSpd100 = 0x40000000, 188 PhyCtrlSpd10 = 0x20000000, 189 PhyCtrlPhyBaseAddr = 0x1f000000, 190 PhyCtrlDux = 0x800000, 191 PhyCtrlReset = 0x400000, 192 }; 193 194 enum FlowCtrlConfigBits { 195 FlowCtrlFullDX = 0x80000000, 196 FlowCtrlEnb = 0x40000000, 197 }; 198 199 enum Config0Bits { 200 Cfg0_Reset = 0x80000000, 201 Cfg0_Anaoff = 0x40000000, 202 Cfg0_LDPS = 0x20000000, 203 }; 204 205 enum Config1Bits { 206 Cfg1_EarlyRx = 1 << 31, 207 Cfg1_EarlyTx = 1 << 30, 208 209 //rx buffer size 210 Cfg1_Rcv8K = 0x0, 211 Cfg1_Rcv16K = 0x1, 212 Cfg1_Rcv32K = 0x3, 213 Cfg1_Rcv64K = 0x7, 214 Cfg1_Rcv128K = 0xf, 215 }; 216 217 enum MiiCmd0Bits { 218 Mii_Divider = 0x20000000, 219 Mii_WRITE = 0x400000, 220 Mii_READ = 0x200000, 221 Mii_SCAN = 0x100000, 222 Mii_Tamod = 0x80000, 223 Mii_Drvmod = 0x40000, 224 Mii_mdc = 0x20000, 225 Mii_mdoen = 0x10000, 226 Mii_mdo = 0x8000, 227 Mii_mdi = 0x4000, 228 }; 229 230 enum MiiStatusBits { 231 Mii_StatusBusy = 0x80000000, 232 }; 233 234 enum PMConfigBits { 235 PM_Enable = 1 << 31, 236 PM_LongWF = 1 << 30, 237 PM_Magic = 1 << 29, 238 PM_LANWake = 1 << 28, 239 PM_LWPTN = (1 << 27 | 1<< 26), 240 PM_LinkUp = 1 << 25, 241 PM_WakeUp = 1 << 24, 242 }; 243 244 /* Locking rules: 245 * priv->lock protects most of the fields of priv and most of the 246 * hardware registers. It does not have to protect against softirqs 247 * between sc92031_disable_interrupts and sc92031_enable_interrupts; 248 * it also does not need to be used in ->open and ->stop while the 249 * device interrupts are off. 250 * Not having to protect against softirqs is very useful due to heavy 251 * use of mdelay() at _sc92031_reset. 252 * Functions prefixed with _sc92031_ must be called with the lock held; 253 * functions prefixed with sc92031_ must be called without the lock held. 254 */ 255 256 /* Locking rules for the interrupt: 257 * - the interrupt and the tasklet never run at the same time 258 * - neither run between sc92031_disable_interrupts and 259 * sc92031_enable_interrupt 260 */ 261 262 struct sc92031_priv { 263 spinlock_t lock; 264 /* iomap.h cookie */ 265 void __iomem *port_base; 266 /* pci device structure */ 267 struct pci_dev *pdev; 268 /* tasklet */ 269 struct tasklet_struct tasklet; 270 271 /* CPU address of rx ring */ 272 void *rx_ring; 273 /* PCI address of rx ring */ 274 dma_addr_t rx_ring_dma_addr; 275 /* PCI address of rx ring read pointer */ 276 dma_addr_t rx_ring_tail; 277 278 /* tx ring write index */ 279 unsigned tx_head; 280 /* tx ring read index */ 281 unsigned tx_tail; 282 /* CPU address of tx bounce buffer */ 283 void *tx_bufs; 284 /* PCI address of tx bounce buffer */ 285 dma_addr_t tx_bufs_dma_addr; 286 287 /* copies of some hardware registers */ 288 u32 intr_status; 289 atomic_t intr_mask; 290 u32 rx_config; 291 u32 tx_config; 292 u32 pm_config; 293 294 /* copy of some flags from dev->flags */ 295 unsigned int mc_flags; 296 297 /* for ETHTOOL_GSTATS */ 298 u64 tx_timeouts; 299 u64 rx_loss; 300 301 /* for dev->get_stats */ 302 long rx_value; 303 }; 304 305 /* I don't know which registers can be safely read; however, I can guess 306 * MAC0 is one of them. */ 307 static inline void _sc92031_dummy_read(void __iomem *port_base) 308 { 309 ioread32(port_base + MAC0); 310 } 311 312 static u32 _sc92031_mii_wait(void __iomem *port_base) 313 { 314 u32 mii_status; 315 316 do { 317 udelay(10); 318 mii_status = ioread32(port_base + Miistatus); 319 } while (mii_status & Mii_StatusBusy); 320 321 return mii_status; 322 } 323 324 static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1) 325 { 326 iowrite32(Mii_Divider, port_base + Miicmd0); 327 328 _sc92031_mii_wait(port_base); 329 330 iowrite32(cmd1, port_base + Miicmd1); 331 iowrite32(Mii_Divider | cmd0, port_base + Miicmd0); 332 333 return _sc92031_mii_wait(port_base); 334 } 335 336 static void _sc92031_mii_scan(void __iomem *port_base) 337 { 338 _sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6); 339 } 340 341 static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg) 342 { 343 return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13; 344 } 345 346 static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val) 347 { 348 _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11)); 349 } 350 351 static void sc92031_disable_interrupts(struct net_device *dev) 352 { 353 struct sc92031_priv *priv = netdev_priv(dev); 354 void __iomem *port_base = priv->port_base; 355 356 /* tell the tasklet/interrupt not to enable interrupts */ 357 atomic_set(&priv->intr_mask, 0); 358 wmb(); 359 360 /* stop interrupts */ 361 iowrite32(0, port_base + IntrMask); 362 _sc92031_dummy_read(port_base); 363 364 /* wait for any concurrent interrupt/tasklet to finish */ 365 synchronize_irq(priv->pdev->irq); 366 tasklet_disable(&priv->tasklet); 367 } 368 369 static void sc92031_enable_interrupts(struct net_device *dev) 370 { 371 struct sc92031_priv *priv = netdev_priv(dev); 372 void __iomem *port_base = priv->port_base; 373 374 tasklet_enable(&priv->tasklet); 375 376 atomic_set(&priv->intr_mask, IntrBits); 377 wmb(); 378 379 iowrite32(IntrBits, port_base + IntrMask); 380 } 381 382 static void _sc92031_disable_tx_rx(struct net_device *dev) 383 { 384 struct sc92031_priv *priv = netdev_priv(dev); 385 void __iomem *port_base = priv->port_base; 386 387 priv->rx_config &= ~RxEnb; 388 priv->tx_config &= ~TxEnb; 389 iowrite32(priv->rx_config, port_base + RxConfig); 390 iowrite32(priv->tx_config, port_base + TxConfig); 391 } 392 393 static void _sc92031_enable_tx_rx(struct net_device *dev) 394 { 395 struct sc92031_priv *priv = netdev_priv(dev); 396 void __iomem *port_base = priv->port_base; 397 398 priv->rx_config |= RxEnb; 399 priv->tx_config |= TxEnb; 400 iowrite32(priv->rx_config, port_base + RxConfig); 401 iowrite32(priv->tx_config, port_base + TxConfig); 402 } 403 404 static void _sc92031_tx_clear(struct net_device *dev) 405 { 406 struct sc92031_priv *priv = netdev_priv(dev); 407 408 while (priv->tx_head - priv->tx_tail > 0) { 409 priv->tx_tail++; 410 dev->stats.tx_dropped++; 411 } 412 priv->tx_head = priv->tx_tail = 0; 413 } 414 415 static void _sc92031_set_mar(struct net_device *dev) 416 { 417 struct sc92031_priv *priv = netdev_priv(dev); 418 void __iomem *port_base = priv->port_base; 419 u32 mar0 = 0, mar1 = 0; 420 421 if ((dev->flags & IFF_PROMISC) || 422 netdev_mc_count(dev) > multicast_filter_limit || 423 (dev->flags & IFF_ALLMULTI)) 424 mar0 = mar1 = 0xffffffff; 425 else if (dev->flags & IFF_MULTICAST) { 426 struct netdev_hw_addr *ha; 427 428 netdev_for_each_mc_addr(ha, dev) { 429 u32 crc; 430 unsigned bit = 0; 431 432 crc = ~ether_crc(ETH_ALEN, ha->addr); 433 crc >>= 24; 434 435 if (crc & 0x01) bit |= 0x02; 436 if (crc & 0x02) bit |= 0x01; 437 if (crc & 0x10) bit |= 0x20; 438 if (crc & 0x20) bit |= 0x10; 439 if (crc & 0x40) bit |= 0x08; 440 if (crc & 0x80) bit |= 0x04; 441 442 if (bit > 31) 443 mar0 |= 0x1 << (bit - 32); 444 else 445 mar1 |= 0x1 << bit; 446 } 447 } 448 449 iowrite32(mar0, port_base + MAR0); 450 iowrite32(mar1, port_base + MAR0 + 4); 451 } 452 453 static void _sc92031_set_rx_config(struct net_device *dev) 454 { 455 struct sc92031_priv *priv = netdev_priv(dev); 456 void __iomem *port_base = priv->port_base; 457 unsigned int old_mc_flags; 458 u32 rx_config_bits = 0; 459 460 old_mc_flags = priv->mc_flags; 461 462 if (dev->flags & IFF_PROMISC) 463 rx_config_bits |= RxSmall | RxHuge | RxErr | RxBroadcast 464 | RxMulticast | RxAllphys; 465 466 if (dev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 467 rx_config_bits |= RxMulticast; 468 469 if (dev->flags & IFF_BROADCAST) 470 rx_config_bits |= RxBroadcast; 471 472 priv->rx_config &= ~(RxSmall | RxHuge | RxErr | RxBroadcast 473 | RxMulticast | RxAllphys); 474 priv->rx_config |= rx_config_bits; 475 476 priv->mc_flags = dev->flags & (IFF_PROMISC | IFF_ALLMULTI 477 | IFF_MULTICAST | IFF_BROADCAST); 478 479 if (netif_carrier_ok(dev) && priv->mc_flags != old_mc_flags) 480 iowrite32(priv->rx_config, port_base + RxConfig); 481 } 482 483 static bool _sc92031_check_media(struct net_device *dev) 484 { 485 struct sc92031_priv *priv = netdev_priv(dev); 486 void __iomem *port_base = priv->port_base; 487 u16 bmsr; 488 489 bmsr = _sc92031_mii_read(port_base, MII_BMSR); 490 rmb(); 491 if (bmsr & BMSR_LSTATUS) { 492 bool speed_100, duplex_full; 493 u32 flow_ctrl_config = 0; 494 u16 output_status = _sc92031_mii_read(port_base, 495 MII_OutputStatus); 496 _sc92031_mii_scan(port_base); 497 498 speed_100 = output_status & 0x2; 499 duplex_full = output_status & 0x4; 500 501 /* Initial Tx/Rx configuration */ 502 priv->rx_config = (0x40 << LowThresholdShift) | (0x1c0 << HighThresholdShift); 503 priv->tx_config = 0x48800000; 504 505 /* NOTE: vendor driver had dead code here to enable tx padding */ 506 507 if (!speed_100) 508 priv->tx_config |= 0x80000; 509 510 // configure rx mode 511 _sc92031_set_rx_config(dev); 512 513 if (duplex_full) { 514 priv->rx_config |= RxFullDx; 515 priv->tx_config |= TxFullDx; 516 flow_ctrl_config = FlowCtrlFullDX | FlowCtrlEnb; 517 } else { 518 priv->rx_config &= ~RxFullDx; 519 priv->tx_config &= ~TxFullDx; 520 } 521 522 _sc92031_set_mar(dev); 523 _sc92031_set_rx_config(dev); 524 _sc92031_enable_tx_rx(dev); 525 iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig); 526 527 netif_carrier_on(dev); 528 529 if (printk_ratelimit()) 530 printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n", 531 dev->name, 532 speed_100 ? "100" : "10", 533 duplex_full ? "full" : "half"); 534 return true; 535 } else { 536 _sc92031_mii_scan(port_base); 537 538 netif_carrier_off(dev); 539 540 _sc92031_disable_tx_rx(dev); 541 542 if (printk_ratelimit()) 543 printk(KERN_INFO "%s: link down\n", dev->name); 544 return false; 545 } 546 } 547 548 static void _sc92031_phy_reset(struct net_device *dev) 549 { 550 struct sc92031_priv *priv = netdev_priv(dev); 551 void __iomem *port_base = priv->port_base; 552 u32 phy_ctrl; 553 554 phy_ctrl = ioread32(port_base + PhyCtrl); 555 phy_ctrl &= ~(PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10); 556 phy_ctrl |= PhyCtrlAne | PhyCtrlReset; 557 558 switch (media) { 559 default: 560 case AUTOSELECT: 561 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10; 562 break; 563 case M10_HALF: 564 phy_ctrl |= PhyCtrlSpd10; 565 break; 566 case M10_FULL: 567 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd10; 568 break; 569 case M100_HALF: 570 phy_ctrl |= PhyCtrlSpd100; 571 break; 572 case M100_FULL: 573 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100; 574 break; 575 } 576 577 iowrite32(phy_ctrl, port_base + PhyCtrl); 578 mdelay(10); 579 580 phy_ctrl &= ~PhyCtrlReset; 581 iowrite32(phy_ctrl, port_base + PhyCtrl); 582 mdelay(1); 583 584 _sc92031_mii_write(port_base, MII_JAB, 585 PHY_16_JAB_ENB | PHY_16_PORT_ENB); 586 _sc92031_mii_scan(port_base); 587 588 netif_carrier_off(dev); 589 netif_stop_queue(dev); 590 } 591 592 static void _sc92031_reset(struct net_device *dev) 593 { 594 struct sc92031_priv *priv = netdev_priv(dev); 595 void __iomem *port_base = priv->port_base; 596 597 /* disable PM */ 598 iowrite32(0, port_base + PMConfig); 599 600 /* soft reset the chip */ 601 iowrite32(Cfg0_Reset, port_base + Config0); 602 mdelay(200); 603 604 iowrite32(0, port_base + Config0); 605 mdelay(10); 606 607 /* disable interrupts */ 608 iowrite32(0, port_base + IntrMask); 609 610 /* clear multicast address */ 611 iowrite32(0, port_base + MAR0); 612 iowrite32(0, port_base + MAR0 + 4); 613 614 /* init rx ring */ 615 iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr); 616 priv->rx_ring_tail = priv->rx_ring_dma_addr; 617 618 /* init tx ring */ 619 _sc92031_tx_clear(dev); 620 621 /* clear old register values */ 622 priv->intr_status = 0; 623 atomic_set(&priv->intr_mask, 0); 624 priv->rx_config = 0; 625 priv->tx_config = 0; 626 priv->mc_flags = 0; 627 628 /* configure rx buffer size */ 629 /* NOTE: vendor driver had dead code here to enable early tx/rx */ 630 iowrite32(Cfg1_Rcv64K, port_base + Config1); 631 632 _sc92031_phy_reset(dev); 633 _sc92031_check_media(dev); 634 635 /* calculate rx fifo overflow */ 636 priv->rx_value = 0; 637 638 /* enable PM */ 639 iowrite32(priv->pm_config, port_base + PMConfig); 640 641 /* clear intr register */ 642 ioread32(port_base + IntrStatus); 643 } 644 645 static void _sc92031_tx_tasklet(struct net_device *dev) 646 { 647 struct sc92031_priv *priv = netdev_priv(dev); 648 void __iomem *port_base = priv->port_base; 649 650 unsigned old_tx_tail; 651 unsigned entry; 652 u32 tx_status; 653 654 old_tx_tail = priv->tx_tail; 655 while (priv->tx_head - priv->tx_tail > 0) { 656 entry = priv->tx_tail % NUM_TX_DESC; 657 tx_status = ioread32(port_base + TxStatus0 + entry * 4); 658 659 if (!(tx_status & (TxStatOK | TxUnderrun | TxAborted))) 660 break; 661 662 priv->tx_tail++; 663 664 if (tx_status & TxStatOK) { 665 dev->stats.tx_bytes += tx_status & 0x1fff; 666 dev->stats.tx_packets++; 667 /* Note: TxCarrierLost is always asserted at 100mbps. */ 668 dev->stats.collisions += (tx_status >> 22) & 0xf; 669 } 670 671 if (tx_status & (TxOutOfWindow | TxAborted)) { 672 dev->stats.tx_errors++; 673 674 if (tx_status & TxAborted) 675 dev->stats.tx_aborted_errors++; 676 677 if (tx_status & TxCarrierLost) 678 dev->stats.tx_carrier_errors++; 679 680 if (tx_status & TxOutOfWindow) 681 dev->stats.tx_window_errors++; 682 } 683 684 if (tx_status & TxUnderrun) 685 dev->stats.tx_fifo_errors++; 686 } 687 688 if (priv->tx_tail != old_tx_tail) 689 if (netif_queue_stopped(dev)) 690 netif_wake_queue(dev); 691 } 692 693 static void _sc92031_rx_tasklet_error(struct net_device *dev, 694 u32 rx_status, unsigned rx_size) 695 { 696 if(rx_size > (MAX_ETH_FRAME_SIZE + 4) || rx_size < 16) { 697 dev->stats.rx_errors++; 698 dev->stats.rx_length_errors++; 699 } 700 701 if (!(rx_status & RxStatesOK)) { 702 dev->stats.rx_errors++; 703 704 if (rx_status & (RxHugeFrame | RxSmallFrame)) 705 dev->stats.rx_length_errors++; 706 707 if (rx_status & RxBadAlign) 708 dev->stats.rx_frame_errors++; 709 710 if (!(rx_status & RxCRCOK)) 711 dev->stats.rx_crc_errors++; 712 } else { 713 struct sc92031_priv *priv = netdev_priv(dev); 714 priv->rx_loss++; 715 } 716 } 717 718 static void _sc92031_rx_tasklet(struct net_device *dev) 719 { 720 struct sc92031_priv *priv = netdev_priv(dev); 721 void __iomem *port_base = priv->port_base; 722 723 dma_addr_t rx_ring_head; 724 unsigned rx_len; 725 unsigned rx_ring_offset; 726 void *rx_ring = priv->rx_ring; 727 728 rx_ring_head = ioread32(port_base + RxBufWPtr); 729 rmb(); 730 731 /* rx_ring_head is only 17 bits in the RxBufWPtr register. 732 * we need to change it to 32 bits physical address 733 */ 734 rx_ring_head &= (dma_addr_t)(RX_BUF_LEN - 1); 735 rx_ring_head |= priv->rx_ring_dma_addr & ~(dma_addr_t)(RX_BUF_LEN - 1); 736 if (rx_ring_head < priv->rx_ring_dma_addr) 737 rx_ring_head += RX_BUF_LEN; 738 739 if (rx_ring_head >= priv->rx_ring_tail) 740 rx_len = rx_ring_head - priv->rx_ring_tail; 741 else 742 rx_len = RX_BUF_LEN - (priv->rx_ring_tail - rx_ring_head); 743 744 if (!rx_len) 745 return; 746 747 if (unlikely(rx_len > RX_BUF_LEN)) { 748 if (printk_ratelimit()) 749 printk(KERN_ERR "%s: rx packets length > rx buffer\n", 750 dev->name); 751 return; 752 } 753 754 rx_ring_offset = (priv->rx_ring_tail - priv->rx_ring_dma_addr) % RX_BUF_LEN; 755 756 while (rx_len) { 757 u32 rx_status; 758 unsigned rx_size, rx_size_align, pkt_size; 759 struct sk_buff *skb; 760 761 rx_status = le32_to_cpup((__le32 *)(rx_ring + rx_ring_offset)); 762 rmb(); 763 764 rx_size = rx_status >> 20; 765 rx_size_align = (rx_size + 3) & ~3; // for 4 bytes aligned 766 pkt_size = rx_size - 4; // Omit the four octet CRC from the length. 767 768 rx_ring_offset = (rx_ring_offset + 4) % RX_BUF_LEN; 769 770 if (unlikely(rx_status == 0 || 771 rx_size > (MAX_ETH_FRAME_SIZE + 4) || 772 rx_size < 16 || 773 !(rx_status & RxStatesOK))) { 774 _sc92031_rx_tasklet_error(dev, rx_status, rx_size); 775 break; 776 } 777 778 if (unlikely(rx_size_align + 4 > rx_len)) { 779 if (printk_ratelimit()) 780 printk(KERN_ERR "%s: rx_len is too small\n", dev->name); 781 break; 782 } 783 784 rx_len -= rx_size_align + 4; 785 786 skb = netdev_alloc_skb_ip_align(dev, pkt_size); 787 if (unlikely(!skb)) { 788 if (printk_ratelimit()) 789 printk(KERN_ERR "%s: Couldn't allocate a skb_buff for a packet of size %u\n", 790 dev->name, pkt_size); 791 goto next; 792 } 793 794 if ((rx_ring_offset + pkt_size) > RX_BUF_LEN) { 795 skb_put_data(skb, rx_ring + rx_ring_offset, 796 RX_BUF_LEN - rx_ring_offset); 797 skb_put_data(skb, rx_ring, 798 pkt_size - (RX_BUF_LEN - rx_ring_offset)); 799 } else { 800 skb_put_data(skb, rx_ring + rx_ring_offset, pkt_size); 801 } 802 803 skb->protocol = eth_type_trans(skb, dev); 804 netif_rx(skb); 805 806 dev->stats.rx_bytes += pkt_size; 807 dev->stats.rx_packets++; 808 809 if (rx_status & Rx_Multicast) 810 dev->stats.multicast++; 811 812 next: 813 rx_ring_offset = (rx_ring_offset + rx_size_align) % RX_BUF_LEN; 814 } 815 mb(); 816 817 priv->rx_ring_tail = rx_ring_head; 818 iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr); 819 } 820 821 static void _sc92031_link_tasklet(struct net_device *dev) 822 { 823 if (_sc92031_check_media(dev)) 824 netif_wake_queue(dev); 825 else { 826 netif_stop_queue(dev); 827 dev->stats.tx_carrier_errors++; 828 } 829 } 830 831 static void sc92031_tasklet(unsigned long data) 832 { 833 struct net_device *dev = (struct net_device *)data; 834 struct sc92031_priv *priv = netdev_priv(dev); 835 void __iomem *port_base = priv->port_base; 836 u32 intr_status, intr_mask; 837 838 intr_status = priv->intr_status; 839 840 spin_lock(&priv->lock); 841 842 if (unlikely(!netif_running(dev))) 843 goto out; 844 845 if (intr_status & TxOK) 846 _sc92031_tx_tasklet(dev); 847 848 if (intr_status & RxOK) 849 _sc92031_rx_tasklet(dev); 850 851 if (intr_status & RxOverflow) 852 dev->stats.rx_errors++; 853 854 if (intr_status & TimeOut) { 855 dev->stats.rx_errors++; 856 dev->stats.rx_length_errors++; 857 } 858 859 if (intr_status & (LinkFail | LinkOK)) 860 _sc92031_link_tasklet(dev); 861 862 out: 863 intr_mask = atomic_read(&priv->intr_mask); 864 rmb(); 865 866 iowrite32(intr_mask, port_base + IntrMask); 867 868 spin_unlock(&priv->lock); 869 } 870 871 static irqreturn_t sc92031_interrupt(int irq, void *dev_id) 872 { 873 struct net_device *dev = dev_id; 874 struct sc92031_priv *priv = netdev_priv(dev); 875 void __iomem *port_base = priv->port_base; 876 u32 intr_status, intr_mask; 877 878 /* mask interrupts before clearing IntrStatus */ 879 iowrite32(0, port_base + IntrMask); 880 _sc92031_dummy_read(port_base); 881 882 intr_status = ioread32(port_base + IntrStatus); 883 if (unlikely(intr_status == 0xffffffff)) 884 return IRQ_NONE; // hardware has gone missing 885 886 intr_status &= IntrBits; 887 if (!intr_status) 888 goto out_none; 889 890 priv->intr_status = intr_status; 891 tasklet_schedule(&priv->tasklet); 892 893 return IRQ_HANDLED; 894 895 out_none: 896 intr_mask = atomic_read(&priv->intr_mask); 897 rmb(); 898 899 iowrite32(intr_mask, port_base + IntrMask); 900 901 return IRQ_NONE; 902 } 903 904 static struct net_device_stats *sc92031_get_stats(struct net_device *dev) 905 { 906 struct sc92031_priv *priv = netdev_priv(dev); 907 void __iomem *port_base = priv->port_base; 908 909 // FIXME I do not understand what is this trying to do. 910 if (netif_running(dev)) { 911 int temp; 912 913 spin_lock_bh(&priv->lock); 914 915 /* Update the error count. */ 916 temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff; 917 918 if (temp == 0xffff) { 919 priv->rx_value += temp; 920 dev->stats.rx_fifo_errors = priv->rx_value; 921 } else 922 dev->stats.rx_fifo_errors = temp + priv->rx_value; 923 924 spin_unlock_bh(&priv->lock); 925 } 926 927 return &dev->stats; 928 } 929 930 static netdev_tx_t sc92031_start_xmit(struct sk_buff *skb, 931 struct net_device *dev) 932 { 933 struct sc92031_priv *priv = netdev_priv(dev); 934 void __iomem *port_base = priv->port_base; 935 unsigned len; 936 unsigned entry; 937 u32 tx_status; 938 939 if (unlikely(skb->len > TX_BUF_SIZE)) { 940 dev->stats.tx_dropped++; 941 goto out; 942 } 943 944 spin_lock(&priv->lock); 945 946 if (unlikely(!netif_carrier_ok(dev))) { 947 dev->stats.tx_dropped++; 948 goto out_unlock; 949 } 950 951 BUG_ON(priv->tx_head - priv->tx_tail >= NUM_TX_DESC); 952 953 entry = priv->tx_head++ % NUM_TX_DESC; 954 955 skb_copy_and_csum_dev(skb, priv->tx_bufs + entry * TX_BUF_SIZE); 956 957 len = skb->len; 958 if (len < ETH_ZLEN) { 959 memset(priv->tx_bufs + entry * TX_BUF_SIZE + len, 960 0, ETH_ZLEN - len); 961 len = ETH_ZLEN; 962 } 963 964 wmb(); 965 966 if (len < 100) 967 tx_status = len; 968 else if (len < 300) 969 tx_status = 0x30000 | len; 970 else 971 tx_status = 0x50000 | len; 972 973 iowrite32(priv->tx_bufs_dma_addr + entry * TX_BUF_SIZE, 974 port_base + TxAddr0 + entry * 4); 975 iowrite32(tx_status, port_base + TxStatus0 + entry * 4); 976 977 if (priv->tx_head - priv->tx_tail >= NUM_TX_DESC) 978 netif_stop_queue(dev); 979 980 out_unlock: 981 spin_unlock(&priv->lock); 982 983 out: 984 dev_consume_skb_any(skb); 985 986 return NETDEV_TX_OK; 987 } 988 989 static int sc92031_open(struct net_device *dev) 990 { 991 int err; 992 struct sc92031_priv *priv = netdev_priv(dev); 993 struct pci_dev *pdev = priv->pdev; 994 995 priv->rx_ring = pci_alloc_consistent(pdev, RX_BUF_LEN, 996 &priv->rx_ring_dma_addr); 997 if (unlikely(!priv->rx_ring)) { 998 err = -ENOMEM; 999 goto out_alloc_rx_ring; 1000 } 1001 1002 priv->tx_bufs = pci_alloc_consistent(pdev, TX_BUF_TOT_LEN, 1003 &priv->tx_bufs_dma_addr); 1004 if (unlikely(!priv->tx_bufs)) { 1005 err = -ENOMEM; 1006 goto out_alloc_tx_bufs; 1007 } 1008 priv->tx_head = priv->tx_tail = 0; 1009 1010 err = request_irq(pdev->irq, sc92031_interrupt, 1011 IRQF_SHARED, dev->name, dev); 1012 if (unlikely(err < 0)) 1013 goto out_request_irq; 1014 1015 priv->pm_config = 0; 1016 1017 /* Interrupts already disabled by sc92031_stop or sc92031_probe */ 1018 spin_lock_bh(&priv->lock); 1019 1020 _sc92031_reset(dev); 1021 1022 spin_unlock_bh(&priv->lock); 1023 sc92031_enable_interrupts(dev); 1024 1025 if (netif_carrier_ok(dev)) 1026 netif_start_queue(dev); 1027 else 1028 netif_tx_disable(dev); 1029 1030 return 0; 1031 1032 out_request_irq: 1033 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs, 1034 priv->tx_bufs_dma_addr); 1035 out_alloc_tx_bufs: 1036 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring, 1037 priv->rx_ring_dma_addr); 1038 out_alloc_rx_ring: 1039 return err; 1040 } 1041 1042 static int sc92031_stop(struct net_device *dev) 1043 { 1044 struct sc92031_priv *priv = netdev_priv(dev); 1045 struct pci_dev *pdev = priv->pdev; 1046 1047 netif_tx_disable(dev); 1048 1049 /* Disable interrupts, stop Tx and Rx. */ 1050 sc92031_disable_interrupts(dev); 1051 1052 spin_lock_bh(&priv->lock); 1053 1054 _sc92031_disable_tx_rx(dev); 1055 _sc92031_tx_clear(dev); 1056 1057 spin_unlock_bh(&priv->lock); 1058 1059 free_irq(pdev->irq, dev); 1060 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs, 1061 priv->tx_bufs_dma_addr); 1062 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring, 1063 priv->rx_ring_dma_addr); 1064 1065 return 0; 1066 } 1067 1068 static void sc92031_set_multicast_list(struct net_device *dev) 1069 { 1070 struct sc92031_priv *priv = netdev_priv(dev); 1071 1072 spin_lock_bh(&priv->lock); 1073 1074 _sc92031_set_mar(dev); 1075 _sc92031_set_rx_config(dev); 1076 1077 spin_unlock_bh(&priv->lock); 1078 } 1079 1080 static void sc92031_tx_timeout(struct net_device *dev) 1081 { 1082 struct sc92031_priv *priv = netdev_priv(dev); 1083 1084 /* Disable interrupts by clearing the interrupt mask.*/ 1085 sc92031_disable_interrupts(dev); 1086 1087 spin_lock(&priv->lock); 1088 1089 priv->tx_timeouts++; 1090 1091 _sc92031_reset(dev); 1092 1093 spin_unlock(&priv->lock); 1094 1095 /* enable interrupts */ 1096 sc92031_enable_interrupts(dev); 1097 1098 if (netif_carrier_ok(dev)) 1099 netif_wake_queue(dev); 1100 } 1101 1102 #ifdef CONFIG_NET_POLL_CONTROLLER 1103 static void sc92031_poll_controller(struct net_device *dev) 1104 { 1105 struct sc92031_priv *priv = netdev_priv(dev); 1106 const int irq = priv->pdev->irq; 1107 1108 disable_irq(irq); 1109 if (sc92031_interrupt(irq, dev) != IRQ_NONE) 1110 sc92031_tasklet((unsigned long)dev); 1111 enable_irq(irq); 1112 } 1113 #endif 1114 1115 static int 1116 sc92031_ethtool_get_link_ksettings(struct net_device *dev, 1117 struct ethtool_link_ksettings *cmd) 1118 { 1119 struct sc92031_priv *priv = netdev_priv(dev); 1120 void __iomem *port_base = priv->port_base; 1121 u8 phy_address; 1122 u32 phy_ctrl; 1123 u16 output_status; 1124 u32 supported, advertising; 1125 1126 spin_lock_bh(&priv->lock); 1127 1128 phy_address = ioread32(port_base + Miicmd1) >> 27; 1129 phy_ctrl = ioread32(port_base + PhyCtrl); 1130 1131 output_status = _sc92031_mii_read(port_base, MII_OutputStatus); 1132 _sc92031_mii_scan(port_base); 1133 1134 spin_unlock_bh(&priv->lock); 1135 1136 supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full 1137 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full 1138 | SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII; 1139 1140 advertising = ADVERTISED_TP | ADVERTISED_MII; 1141 1142 if ((phy_ctrl & (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10)) 1143 == (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10)) 1144 advertising |= ADVERTISED_Autoneg; 1145 1146 if ((phy_ctrl & PhyCtrlSpd10) == PhyCtrlSpd10) 1147 advertising |= ADVERTISED_10baseT_Half; 1148 1149 if ((phy_ctrl & (PhyCtrlSpd10 | PhyCtrlDux)) 1150 == (PhyCtrlSpd10 | PhyCtrlDux)) 1151 advertising |= ADVERTISED_10baseT_Full; 1152 1153 if ((phy_ctrl & PhyCtrlSpd100) == PhyCtrlSpd100) 1154 advertising |= ADVERTISED_100baseT_Half; 1155 1156 if ((phy_ctrl & (PhyCtrlSpd100 | PhyCtrlDux)) 1157 == (PhyCtrlSpd100 | PhyCtrlDux)) 1158 advertising |= ADVERTISED_100baseT_Full; 1159 1160 if (phy_ctrl & PhyCtrlAne) 1161 advertising |= ADVERTISED_Autoneg; 1162 1163 cmd->base.speed = (output_status & 0x2) ? SPEED_100 : SPEED_10; 1164 cmd->base.duplex = (output_status & 0x4) ? DUPLEX_FULL : DUPLEX_HALF; 1165 cmd->base.port = PORT_MII; 1166 cmd->base.phy_address = phy_address; 1167 cmd->base.autoneg = (phy_ctrl & PhyCtrlAne) ? 1168 AUTONEG_ENABLE : AUTONEG_DISABLE; 1169 1170 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 1171 supported); 1172 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 1173 advertising); 1174 1175 return 0; 1176 } 1177 1178 static int 1179 sc92031_ethtool_set_link_ksettings(struct net_device *dev, 1180 const struct ethtool_link_ksettings *cmd) 1181 { 1182 struct sc92031_priv *priv = netdev_priv(dev); 1183 void __iomem *port_base = priv->port_base; 1184 u32 speed = cmd->base.speed; 1185 u32 phy_ctrl; 1186 u32 old_phy_ctrl; 1187 u32 advertising; 1188 1189 ethtool_convert_link_mode_to_legacy_u32(&advertising, 1190 cmd->link_modes.advertising); 1191 1192 if (!(speed == SPEED_10 || speed == SPEED_100)) 1193 return -EINVAL; 1194 if (!(cmd->base.duplex == DUPLEX_HALF || 1195 cmd->base.duplex == DUPLEX_FULL)) 1196 return -EINVAL; 1197 if (!(cmd->base.port == PORT_MII)) 1198 return -EINVAL; 1199 if (!(cmd->base.phy_address == 0x1f)) 1200 return -EINVAL; 1201 if (!(cmd->base.autoneg == AUTONEG_DISABLE || 1202 cmd->base.autoneg == AUTONEG_ENABLE)) 1203 return -EINVAL; 1204 1205 if (cmd->base.autoneg == AUTONEG_ENABLE) { 1206 if (!(advertising & (ADVERTISED_Autoneg 1207 | ADVERTISED_100baseT_Full 1208 | ADVERTISED_100baseT_Half 1209 | ADVERTISED_10baseT_Full 1210 | ADVERTISED_10baseT_Half))) 1211 return -EINVAL; 1212 1213 phy_ctrl = PhyCtrlAne; 1214 1215 // FIXME: I'm not sure what the original code was trying to do 1216 if (advertising & ADVERTISED_Autoneg) 1217 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10; 1218 if (advertising & ADVERTISED_100baseT_Full) 1219 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100; 1220 if (advertising & ADVERTISED_100baseT_Half) 1221 phy_ctrl |= PhyCtrlSpd100; 1222 if (advertising & ADVERTISED_10baseT_Full) 1223 phy_ctrl |= PhyCtrlSpd10 | PhyCtrlDux; 1224 if (advertising & ADVERTISED_10baseT_Half) 1225 phy_ctrl |= PhyCtrlSpd10; 1226 } else { 1227 // FIXME: Whole branch guessed 1228 phy_ctrl = 0; 1229 1230 if (speed == SPEED_10) 1231 phy_ctrl |= PhyCtrlSpd10; 1232 else /* cmd->speed == SPEED_100 */ 1233 phy_ctrl |= PhyCtrlSpd100; 1234 1235 if (cmd->base.duplex == DUPLEX_FULL) 1236 phy_ctrl |= PhyCtrlDux; 1237 } 1238 1239 spin_lock_bh(&priv->lock); 1240 1241 old_phy_ctrl = ioread32(port_base + PhyCtrl); 1242 phy_ctrl |= old_phy_ctrl & ~(PhyCtrlAne | PhyCtrlDux 1243 | PhyCtrlSpd100 | PhyCtrlSpd10); 1244 if (phy_ctrl != old_phy_ctrl) 1245 iowrite32(phy_ctrl, port_base + PhyCtrl); 1246 1247 spin_unlock_bh(&priv->lock); 1248 1249 return 0; 1250 } 1251 1252 static void sc92031_ethtool_get_wol(struct net_device *dev, 1253 struct ethtool_wolinfo *wolinfo) 1254 { 1255 struct sc92031_priv *priv = netdev_priv(dev); 1256 void __iomem *port_base = priv->port_base; 1257 u32 pm_config; 1258 1259 spin_lock_bh(&priv->lock); 1260 pm_config = ioread32(port_base + PMConfig); 1261 spin_unlock_bh(&priv->lock); 1262 1263 // FIXME: Guessed 1264 wolinfo->supported = WAKE_PHY | WAKE_MAGIC 1265 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; 1266 wolinfo->wolopts = 0; 1267 1268 if (pm_config & PM_LinkUp) 1269 wolinfo->wolopts |= WAKE_PHY; 1270 1271 if (pm_config & PM_Magic) 1272 wolinfo->wolopts |= WAKE_MAGIC; 1273 1274 if (pm_config & PM_WakeUp) 1275 // FIXME: Guessed 1276 wolinfo->wolopts |= WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; 1277 } 1278 1279 static int sc92031_ethtool_set_wol(struct net_device *dev, 1280 struct ethtool_wolinfo *wolinfo) 1281 { 1282 struct sc92031_priv *priv = netdev_priv(dev); 1283 void __iomem *port_base = priv->port_base; 1284 u32 pm_config; 1285 1286 spin_lock_bh(&priv->lock); 1287 1288 pm_config = ioread32(port_base + PMConfig) 1289 & ~(PM_LinkUp | PM_Magic | PM_WakeUp); 1290 1291 if (wolinfo->wolopts & WAKE_PHY) 1292 pm_config |= PM_LinkUp; 1293 1294 if (wolinfo->wolopts & WAKE_MAGIC) 1295 pm_config |= PM_Magic; 1296 1297 // FIXME: Guessed 1298 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)) 1299 pm_config |= PM_WakeUp; 1300 1301 priv->pm_config = pm_config; 1302 iowrite32(pm_config, port_base + PMConfig); 1303 1304 spin_unlock_bh(&priv->lock); 1305 1306 return 0; 1307 } 1308 1309 static int sc92031_ethtool_nway_reset(struct net_device *dev) 1310 { 1311 int err = 0; 1312 struct sc92031_priv *priv = netdev_priv(dev); 1313 void __iomem *port_base = priv->port_base; 1314 u16 bmcr; 1315 1316 spin_lock_bh(&priv->lock); 1317 1318 bmcr = _sc92031_mii_read(port_base, MII_BMCR); 1319 if (!(bmcr & BMCR_ANENABLE)) { 1320 err = -EINVAL; 1321 goto out; 1322 } 1323 1324 _sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART); 1325 1326 out: 1327 _sc92031_mii_scan(port_base); 1328 1329 spin_unlock_bh(&priv->lock); 1330 1331 return err; 1332 } 1333 1334 static const char sc92031_ethtool_stats_strings[SILAN_STATS_NUM][ETH_GSTRING_LEN] = { 1335 "tx_timeout", 1336 "rx_loss", 1337 }; 1338 1339 static void sc92031_ethtool_get_strings(struct net_device *dev, 1340 u32 stringset, u8 *data) 1341 { 1342 if (stringset == ETH_SS_STATS) 1343 memcpy(data, sc92031_ethtool_stats_strings, 1344 SILAN_STATS_NUM * ETH_GSTRING_LEN); 1345 } 1346 1347 static int sc92031_ethtool_get_sset_count(struct net_device *dev, int sset) 1348 { 1349 switch (sset) { 1350 case ETH_SS_STATS: 1351 return SILAN_STATS_NUM; 1352 default: 1353 return -EOPNOTSUPP; 1354 } 1355 } 1356 1357 static void sc92031_ethtool_get_ethtool_stats(struct net_device *dev, 1358 struct ethtool_stats *stats, u64 *data) 1359 { 1360 struct sc92031_priv *priv = netdev_priv(dev); 1361 1362 spin_lock_bh(&priv->lock); 1363 data[0] = priv->tx_timeouts; 1364 data[1] = priv->rx_loss; 1365 spin_unlock_bh(&priv->lock); 1366 } 1367 1368 static const struct ethtool_ops sc92031_ethtool_ops = { 1369 .get_wol = sc92031_ethtool_get_wol, 1370 .set_wol = sc92031_ethtool_set_wol, 1371 .nway_reset = sc92031_ethtool_nway_reset, 1372 .get_link = ethtool_op_get_link, 1373 .get_strings = sc92031_ethtool_get_strings, 1374 .get_sset_count = sc92031_ethtool_get_sset_count, 1375 .get_ethtool_stats = sc92031_ethtool_get_ethtool_stats, 1376 .get_link_ksettings = sc92031_ethtool_get_link_ksettings, 1377 .set_link_ksettings = sc92031_ethtool_set_link_ksettings, 1378 }; 1379 1380 1381 static const struct net_device_ops sc92031_netdev_ops = { 1382 .ndo_get_stats = sc92031_get_stats, 1383 .ndo_start_xmit = sc92031_start_xmit, 1384 .ndo_open = sc92031_open, 1385 .ndo_stop = sc92031_stop, 1386 .ndo_set_rx_mode = sc92031_set_multicast_list, 1387 .ndo_validate_addr = eth_validate_addr, 1388 .ndo_set_mac_address = eth_mac_addr, 1389 .ndo_tx_timeout = sc92031_tx_timeout, 1390 #ifdef CONFIG_NET_POLL_CONTROLLER 1391 .ndo_poll_controller = sc92031_poll_controller, 1392 #endif 1393 }; 1394 1395 static int sc92031_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1396 { 1397 int err; 1398 void __iomem* port_base; 1399 struct net_device *dev; 1400 struct sc92031_priv *priv; 1401 u32 mac0, mac1; 1402 1403 err = pci_enable_device(pdev); 1404 if (unlikely(err < 0)) 1405 goto out_enable_device; 1406 1407 pci_set_master(pdev); 1408 1409 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1410 if (unlikely(err < 0)) 1411 goto out_set_dma_mask; 1412 1413 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1414 if (unlikely(err < 0)) 1415 goto out_set_dma_mask; 1416 1417 err = pci_request_regions(pdev, SC92031_NAME); 1418 if (unlikely(err < 0)) 1419 goto out_request_regions; 1420 1421 port_base = pci_iomap(pdev, SC92031_USE_PIO, 0); 1422 if (unlikely(!port_base)) { 1423 err = -EIO; 1424 goto out_iomap; 1425 } 1426 1427 dev = alloc_etherdev(sizeof(struct sc92031_priv)); 1428 if (unlikely(!dev)) { 1429 err = -ENOMEM; 1430 goto out_alloc_etherdev; 1431 } 1432 1433 pci_set_drvdata(pdev, dev); 1434 SET_NETDEV_DEV(dev, &pdev->dev); 1435 1436 /* faked with skb_copy_and_csum_dev */ 1437 dev->features = NETIF_F_SG | NETIF_F_HIGHDMA | 1438 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1439 1440 dev->netdev_ops = &sc92031_netdev_ops; 1441 dev->watchdog_timeo = TX_TIMEOUT; 1442 dev->ethtool_ops = &sc92031_ethtool_ops; 1443 1444 priv = netdev_priv(dev); 1445 spin_lock_init(&priv->lock); 1446 priv->port_base = port_base; 1447 priv->pdev = pdev; 1448 tasklet_init(&priv->tasklet, sc92031_tasklet, (unsigned long)dev); 1449 /* Fudge tasklet count so the call to sc92031_enable_interrupts at 1450 * sc92031_open will work correctly */ 1451 tasklet_disable_nosync(&priv->tasklet); 1452 1453 /* PCI PM Wakeup */ 1454 iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig); 1455 1456 mac0 = ioread32(port_base + MAC0); 1457 mac1 = ioread32(port_base + MAC0 + 4); 1458 dev->dev_addr[0] = mac0 >> 24; 1459 dev->dev_addr[1] = mac0 >> 16; 1460 dev->dev_addr[2] = mac0 >> 8; 1461 dev->dev_addr[3] = mac0; 1462 dev->dev_addr[4] = mac1 >> 8; 1463 dev->dev_addr[5] = mac1; 1464 1465 err = register_netdev(dev); 1466 if (err < 0) 1467 goto out_register_netdev; 1468 1469 printk(KERN_INFO "%s: SC92031 at 0x%lx, %pM, IRQ %d\n", dev->name, 1470 (long)pci_resource_start(pdev, SC92031_USE_PIO), dev->dev_addr, 1471 pdev->irq); 1472 1473 return 0; 1474 1475 out_register_netdev: 1476 free_netdev(dev); 1477 out_alloc_etherdev: 1478 pci_iounmap(pdev, port_base); 1479 out_iomap: 1480 pci_release_regions(pdev); 1481 out_request_regions: 1482 out_set_dma_mask: 1483 pci_disable_device(pdev); 1484 out_enable_device: 1485 return err; 1486 } 1487 1488 static void sc92031_remove(struct pci_dev *pdev) 1489 { 1490 struct net_device *dev = pci_get_drvdata(pdev); 1491 struct sc92031_priv *priv = netdev_priv(dev); 1492 void __iomem* port_base = priv->port_base; 1493 1494 unregister_netdev(dev); 1495 free_netdev(dev); 1496 pci_iounmap(pdev, port_base); 1497 pci_release_regions(pdev); 1498 pci_disable_device(pdev); 1499 } 1500 1501 static int sc92031_suspend(struct pci_dev *pdev, pm_message_t state) 1502 { 1503 struct net_device *dev = pci_get_drvdata(pdev); 1504 struct sc92031_priv *priv = netdev_priv(dev); 1505 1506 pci_save_state(pdev); 1507 1508 if (!netif_running(dev)) 1509 goto out; 1510 1511 netif_device_detach(dev); 1512 1513 /* Disable interrupts, stop Tx and Rx. */ 1514 sc92031_disable_interrupts(dev); 1515 1516 spin_lock_bh(&priv->lock); 1517 1518 _sc92031_disable_tx_rx(dev); 1519 _sc92031_tx_clear(dev); 1520 1521 spin_unlock_bh(&priv->lock); 1522 1523 out: 1524 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1525 1526 return 0; 1527 } 1528 1529 static int sc92031_resume(struct pci_dev *pdev) 1530 { 1531 struct net_device *dev = pci_get_drvdata(pdev); 1532 struct sc92031_priv *priv = netdev_priv(dev); 1533 1534 pci_restore_state(pdev); 1535 pci_set_power_state(pdev, PCI_D0); 1536 1537 if (!netif_running(dev)) 1538 goto out; 1539 1540 /* Interrupts already disabled by sc92031_suspend */ 1541 spin_lock_bh(&priv->lock); 1542 1543 _sc92031_reset(dev); 1544 1545 spin_unlock_bh(&priv->lock); 1546 sc92031_enable_interrupts(dev); 1547 1548 netif_device_attach(dev); 1549 1550 if (netif_carrier_ok(dev)) 1551 netif_wake_queue(dev); 1552 else 1553 netif_tx_disable(dev); 1554 1555 out: 1556 return 0; 1557 } 1558 1559 static const struct pci_device_id sc92031_pci_device_id_table[] = { 1560 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x2031) }, 1561 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x8139) }, 1562 { PCI_DEVICE(0x1088, 0x2031) }, 1563 { 0, } 1564 }; 1565 MODULE_DEVICE_TABLE(pci, sc92031_pci_device_id_table); 1566 1567 static struct pci_driver sc92031_pci_driver = { 1568 .name = SC92031_NAME, 1569 .id_table = sc92031_pci_device_id_table, 1570 .probe = sc92031_probe, 1571 .remove = sc92031_remove, 1572 .suspend = sc92031_suspend, 1573 .resume = sc92031_resume, 1574 }; 1575 1576 module_pci_driver(sc92031_pci_driver); 1577 MODULE_LICENSE("GPL"); 1578 MODULE_AUTHOR("Cesar Eduardo Barros <cesarb@cesarb.net>"); 1579 MODULE_DESCRIPTION("Silan SC92031 PCI Fast Ethernet Adapter driver"); 1580