1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2006-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #ifndef EFX_NIC_H 12 #define EFX_NIC_H 13 14 #include <linux/net_tstamp.h> 15 #include <linux/i2c-algo-bit.h> 16 #include "net_driver.h" 17 #include "efx.h" 18 #include "mcdi.h" 19 20 enum { 21 EFX_REV_FALCON_A0 = 0, 22 EFX_REV_FALCON_A1 = 1, 23 EFX_REV_FALCON_B0 = 2, 24 EFX_REV_SIENA_A0 = 3, 25 EFX_REV_HUNT_A0 = 4, 26 }; 27 28 static inline int efx_nic_rev(struct efx_nic *efx) 29 { 30 return efx->type->revision; 31 } 32 33 u32 efx_farch_fpga_ver(struct efx_nic *efx); 34 35 /* NIC has two interlinked PCI functions for the same port. */ 36 static inline bool efx_nic_is_dual_func(struct efx_nic *efx) 37 { 38 return efx_nic_rev(efx) < EFX_REV_FALCON_B0; 39 } 40 41 /* Read the current event from the event queue */ 42 static inline efx_qword_t *efx_event(struct efx_channel *channel, 43 unsigned int index) 44 { 45 return ((efx_qword_t *) (channel->eventq.buf.addr)) + 46 (index & channel->eventq_mask); 47 } 48 49 /* See if an event is present 50 * 51 * We check both the high and low dword of the event for all ones. We 52 * wrote all ones when we cleared the event, and no valid event can 53 * have all ones in either its high or low dwords. This approach is 54 * robust against reordering. 55 * 56 * Note that using a single 64-bit comparison is incorrect; even 57 * though the CPU read will be atomic, the DMA write may not be. 58 */ 59 static inline int efx_event_present(efx_qword_t *event) 60 { 61 return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | 62 EFX_DWORD_IS_ALL_ONES(event->dword[1])); 63 } 64 65 /* Returns a pointer to the specified transmit descriptor in the TX 66 * descriptor queue belonging to the specified channel. 67 */ 68 static inline efx_qword_t * 69 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index) 70 { 71 return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index; 72 } 73 74 /* Report whether the NIC considers this TX queue empty, given the 75 * write_count used for the last doorbell push. May return false 76 * negative. 77 */ 78 static inline bool __efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue, 79 unsigned int write_count) 80 { 81 unsigned int empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count); 82 83 if (empty_read_count == 0) 84 return false; 85 86 return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0; 87 } 88 89 static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue) 90 { 91 return __efx_nic_tx_is_empty(tx_queue, tx_queue->write_count); 92 } 93 94 /* Decide whether to push a TX descriptor to the NIC vs merely writing 95 * the doorbell. This can reduce latency when we are adding a single 96 * descriptor to an empty queue, but is otherwise pointless. Further, 97 * Falcon and Siena have hardware bugs (SF bug 33851) that may be 98 * triggered if we don't check this. 99 */ 100 static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue, 101 unsigned int write_count) 102 { 103 bool was_empty = __efx_nic_tx_is_empty(tx_queue, write_count); 104 105 tx_queue->empty_read_count = 0; 106 return was_empty && tx_queue->write_count - write_count == 1; 107 } 108 109 /* Returns a pointer to the specified descriptor in the RX descriptor queue */ 110 static inline efx_qword_t * 111 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 112 { 113 return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index; 114 } 115 116 enum { 117 PHY_TYPE_NONE = 0, 118 PHY_TYPE_TXC43128 = 1, 119 PHY_TYPE_88E1111 = 2, 120 PHY_TYPE_SFX7101 = 3, 121 PHY_TYPE_QT2022C2 = 4, 122 PHY_TYPE_PM8358 = 6, 123 PHY_TYPE_SFT9001A = 8, 124 PHY_TYPE_QT2025C = 9, 125 PHY_TYPE_SFT9001B = 10, 126 }; 127 128 #define FALCON_XMAC_LOOPBACKS \ 129 ((1 << LOOPBACK_XGMII) | \ 130 (1 << LOOPBACK_XGXS) | \ 131 (1 << LOOPBACK_XAUI)) 132 133 /* Alignment of PCIe DMA boundaries (4KB) */ 134 #define EFX_PAGE_SIZE 4096 135 /* Size and alignment of buffer table entries (same) */ 136 #define EFX_BUF_SIZE EFX_PAGE_SIZE 137 138 /* NIC-generic software stats */ 139 enum { 140 GENERIC_STAT_rx_noskb_drops, 141 GENERIC_STAT_rx_nodesc_trunc, 142 GENERIC_STAT_COUNT 143 }; 144 145 /** 146 * struct falcon_board_type - board operations and type information 147 * @id: Board type id, as found in NVRAM 148 * @init: Allocate resources and initialise peripheral hardware 149 * @init_phy: Do board-specific PHY initialisation 150 * @fini: Shut down hardware and free resources 151 * @set_id_led: Set state of identifying LED or revert to automatic function 152 * @monitor: Board-specific health check function 153 */ 154 struct falcon_board_type { 155 u8 id; 156 int (*init) (struct efx_nic *nic); 157 void (*init_phy) (struct efx_nic *efx); 158 void (*fini) (struct efx_nic *nic); 159 void (*set_id_led) (struct efx_nic *efx, enum efx_led_mode mode); 160 int (*monitor) (struct efx_nic *nic); 161 }; 162 163 /** 164 * struct falcon_board - board information 165 * @type: Type of board 166 * @major: Major rev. ('A', 'B' ...) 167 * @minor: Minor rev. (0, 1, ...) 168 * @i2c_adap: I2C adapter for on-board peripherals 169 * @i2c_data: Data for bit-banging algorithm 170 * @hwmon_client: I2C client for hardware monitor 171 * @ioexp_client: I2C client for power/port control 172 */ 173 struct falcon_board { 174 const struct falcon_board_type *type; 175 int major; 176 int minor; 177 struct i2c_adapter i2c_adap; 178 struct i2c_algo_bit_data i2c_data; 179 struct i2c_client *hwmon_client, *ioexp_client; 180 }; 181 182 /** 183 * struct falcon_spi_device - a Falcon SPI (Serial Peripheral Interface) device 184 * @device_id: Controller's id for the device 185 * @size: Size (in bytes) 186 * @addr_len: Number of address bytes in read/write commands 187 * @munge_address: Flag whether addresses should be munged. 188 * Some devices with 9-bit addresses (e.g. AT25040A EEPROM) 189 * use bit 3 of the command byte as address bit A8, rather 190 * than having a two-byte address. If this flag is set, then 191 * commands should be munged in this way. 192 * @erase_command: Erase command (or 0 if sector erase not needed). 193 * @erase_size: Erase sector size (in bytes) 194 * Erase commands affect sectors with this size and alignment. 195 * This must be a power of two. 196 * @block_size: Write block size (in bytes). 197 * Write commands are limited to blocks with this size and alignment. 198 */ 199 struct falcon_spi_device { 200 int device_id; 201 unsigned int size; 202 unsigned int addr_len; 203 unsigned int munge_address:1; 204 u8 erase_command; 205 unsigned int erase_size; 206 unsigned int block_size; 207 }; 208 209 static inline bool falcon_spi_present(const struct falcon_spi_device *spi) 210 { 211 return spi->size != 0; 212 } 213 214 enum { 215 FALCON_STAT_tx_bytes = GENERIC_STAT_COUNT, 216 FALCON_STAT_tx_packets, 217 FALCON_STAT_tx_pause, 218 FALCON_STAT_tx_control, 219 FALCON_STAT_tx_unicast, 220 FALCON_STAT_tx_multicast, 221 FALCON_STAT_tx_broadcast, 222 FALCON_STAT_tx_lt64, 223 FALCON_STAT_tx_64, 224 FALCON_STAT_tx_65_to_127, 225 FALCON_STAT_tx_128_to_255, 226 FALCON_STAT_tx_256_to_511, 227 FALCON_STAT_tx_512_to_1023, 228 FALCON_STAT_tx_1024_to_15xx, 229 FALCON_STAT_tx_15xx_to_jumbo, 230 FALCON_STAT_tx_gtjumbo, 231 FALCON_STAT_tx_non_tcpudp, 232 FALCON_STAT_tx_mac_src_error, 233 FALCON_STAT_tx_ip_src_error, 234 FALCON_STAT_rx_bytes, 235 FALCON_STAT_rx_good_bytes, 236 FALCON_STAT_rx_bad_bytes, 237 FALCON_STAT_rx_packets, 238 FALCON_STAT_rx_good, 239 FALCON_STAT_rx_bad, 240 FALCON_STAT_rx_pause, 241 FALCON_STAT_rx_control, 242 FALCON_STAT_rx_unicast, 243 FALCON_STAT_rx_multicast, 244 FALCON_STAT_rx_broadcast, 245 FALCON_STAT_rx_lt64, 246 FALCON_STAT_rx_64, 247 FALCON_STAT_rx_65_to_127, 248 FALCON_STAT_rx_128_to_255, 249 FALCON_STAT_rx_256_to_511, 250 FALCON_STAT_rx_512_to_1023, 251 FALCON_STAT_rx_1024_to_15xx, 252 FALCON_STAT_rx_15xx_to_jumbo, 253 FALCON_STAT_rx_gtjumbo, 254 FALCON_STAT_rx_bad_lt64, 255 FALCON_STAT_rx_bad_gtjumbo, 256 FALCON_STAT_rx_overflow, 257 FALCON_STAT_rx_symbol_error, 258 FALCON_STAT_rx_align_error, 259 FALCON_STAT_rx_length_error, 260 FALCON_STAT_rx_internal_error, 261 FALCON_STAT_rx_nodesc_drop_cnt, 262 FALCON_STAT_COUNT 263 }; 264 265 /** 266 * struct falcon_nic_data - Falcon NIC state 267 * @pci_dev2: Secondary function of Falcon A 268 * @board: Board state and functions 269 * @stats: Hardware statistics 270 * @stats_disable_count: Nest count for disabling statistics fetches 271 * @stats_pending: Is there a pending DMA of MAC statistics. 272 * @stats_timer: A timer for regularly fetching MAC statistics. 273 * @spi_flash: SPI flash device 274 * @spi_eeprom: SPI EEPROM device 275 * @spi_lock: SPI bus lock 276 * @mdio_lock: MDIO bus lock 277 * @xmac_poll_required: XMAC link state needs polling 278 */ 279 struct falcon_nic_data { 280 struct pci_dev *pci_dev2; 281 struct falcon_board board; 282 u64 stats[FALCON_STAT_COUNT]; 283 unsigned int stats_disable_count; 284 bool stats_pending; 285 struct timer_list stats_timer; 286 struct falcon_spi_device spi_flash; 287 struct falcon_spi_device spi_eeprom; 288 struct mutex spi_lock; 289 struct mutex mdio_lock; 290 bool xmac_poll_required; 291 }; 292 293 static inline struct falcon_board *falcon_board(struct efx_nic *efx) 294 { 295 struct falcon_nic_data *data = efx->nic_data; 296 return &data->board; 297 } 298 299 enum { 300 SIENA_STAT_tx_bytes = GENERIC_STAT_COUNT, 301 SIENA_STAT_tx_good_bytes, 302 SIENA_STAT_tx_bad_bytes, 303 SIENA_STAT_tx_packets, 304 SIENA_STAT_tx_bad, 305 SIENA_STAT_tx_pause, 306 SIENA_STAT_tx_control, 307 SIENA_STAT_tx_unicast, 308 SIENA_STAT_tx_multicast, 309 SIENA_STAT_tx_broadcast, 310 SIENA_STAT_tx_lt64, 311 SIENA_STAT_tx_64, 312 SIENA_STAT_tx_65_to_127, 313 SIENA_STAT_tx_128_to_255, 314 SIENA_STAT_tx_256_to_511, 315 SIENA_STAT_tx_512_to_1023, 316 SIENA_STAT_tx_1024_to_15xx, 317 SIENA_STAT_tx_15xx_to_jumbo, 318 SIENA_STAT_tx_gtjumbo, 319 SIENA_STAT_tx_collision, 320 SIENA_STAT_tx_single_collision, 321 SIENA_STAT_tx_multiple_collision, 322 SIENA_STAT_tx_excessive_collision, 323 SIENA_STAT_tx_deferred, 324 SIENA_STAT_tx_late_collision, 325 SIENA_STAT_tx_excessive_deferred, 326 SIENA_STAT_tx_non_tcpudp, 327 SIENA_STAT_tx_mac_src_error, 328 SIENA_STAT_tx_ip_src_error, 329 SIENA_STAT_rx_bytes, 330 SIENA_STAT_rx_good_bytes, 331 SIENA_STAT_rx_bad_bytes, 332 SIENA_STAT_rx_packets, 333 SIENA_STAT_rx_good, 334 SIENA_STAT_rx_bad, 335 SIENA_STAT_rx_pause, 336 SIENA_STAT_rx_control, 337 SIENA_STAT_rx_unicast, 338 SIENA_STAT_rx_multicast, 339 SIENA_STAT_rx_broadcast, 340 SIENA_STAT_rx_lt64, 341 SIENA_STAT_rx_64, 342 SIENA_STAT_rx_65_to_127, 343 SIENA_STAT_rx_128_to_255, 344 SIENA_STAT_rx_256_to_511, 345 SIENA_STAT_rx_512_to_1023, 346 SIENA_STAT_rx_1024_to_15xx, 347 SIENA_STAT_rx_15xx_to_jumbo, 348 SIENA_STAT_rx_gtjumbo, 349 SIENA_STAT_rx_bad_gtjumbo, 350 SIENA_STAT_rx_overflow, 351 SIENA_STAT_rx_false_carrier, 352 SIENA_STAT_rx_symbol_error, 353 SIENA_STAT_rx_align_error, 354 SIENA_STAT_rx_length_error, 355 SIENA_STAT_rx_internal_error, 356 SIENA_STAT_rx_nodesc_drop_cnt, 357 SIENA_STAT_COUNT 358 }; 359 360 /** 361 * struct siena_nic_data - Siena NIC state 362 * @wol_filter_id: Wake-on-LAN packet filter id 363 * @stats: Hardware statistics 364 */ 365 struct siena_nic_data { 366 int wol_filter_id; 367 u64 stats[SIENA_STAT_COUNT]; 368 }; 369 370 enum { 371 EF10_STAT_tx_bytes = GENERIC_STAT_COUNT, 372 EF10_STAT_tx_packets, 373 EF10_STAT_tx_pause, 374 EF10_STAT_tx_control, 375 EF10_STAT_tx_unicast, 376 EF10_STAT_tx_multicast, 377 EF10_STAT_tx_broadcast, 378 EF10_STAT_tx_lt64, 379 EF10_STAT_tx_64, 380 EF10_STAT_tx_65_to_127, 381 EF10_STAT_tx_128_to_255, 382 EF10_STAT_tx_256_to_511, 383 EF10_STAT_tx_512_to_1023, 384 EF10_STAT_tx_1024_to_15xx, 385 EF10_STAT_tx_15xx_to_jumbo, 386 EF10_STAT_rx_bytes, 387 EF10_STAT_rx_bytes_minus_good_bytes, 388 EF10_STAT_rx_good_bytes, 389 EF10_STAT_rx_bad_bytes, 390 EF10_STAT_rx_packets, 391 EF10_STAT_rx_good, 392 EF10_STAT_rx_bad, 393 EF10_STAT_rx_pause, 394 EF10_STAT_rx_control, 395 EF10_STAT_rx_unicast, 396 EF10_STAT_rx_multicast, 397 EF10_STAT_rx_broadcast, 398 EF10_STAT_rx_lt64, 399 EF10_STAT_rx_64, 400 EF10_STAT_rx_65_to_127, 401 EF10_STAT_rx_128_to_255, 402 EF10_STAT_rx_256_to_511, 403 EF10_STAT_rx_512_to_1023, 404 EF10_STAT_rx_1024_to_15xx, 405 EF10_STAT_rx_15xx_to_jumbo, 406 EF10_STAT_rx_gtjumbo, 407 EF10_STAT_rx_bad_gtjumbo, 408 EF10_STAT_rx_overflow, 409 EF10_STAT_rx_align_error, 410 EF10_STAT_rx_length_error, 411 EF10_STAT_rx_nodesc_drops, 412 EF10_STAT_rx_pm_trunc_bb_overflow, 413 EF10_STAT_rx_pm_discard_bb_overflow, 414 EF10_STAT_rx_pm_trunc_vfifo_full, 415 EF10_STAT_rx_pm_discard_vfifo_full, 416 EF10_STAT_rx_pm_trunc_qbb, 417 EF10_STAT_rx_pm_discard_qbb, 418 EF10_STAT_rx_pm_discard_mapping, 419 EF10_STAT_rx_dp_q_disabled_packets, 420 EF10_STAT_rx_dp_di_dropped_packets, 421 EF10_STAT_rx_dp_streaming_packets, 422 EF10_STAT_rx_dp_hlb_fetch, 423 EF10_STAT_rx_dp_hlb_wait, 424 EF10_STAT_COUNT 425 }; 426 427 /* Maximum number of TX PIO buffers we may allocate to a function. 428 * This matches the total number of buffers on each SFC9100-family 429 * controller. 430 */ 431 #define EF10_TX_PIOBUF_COUNT 16 432 433 /** 434 * struct efx_ef10_nic_data - EF10 architecture NIC state 435 * @mcdi_buf: DMA buffer for MCDI 436 * @warm_boot_count: Last seen MC warm boot count 437 * @vi_base: Absolute index of first VI in this function 438 * @n_allocated_vis: Number of VIs allocated to this function 439 * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot 440 * @must_restore_filters: Flag: filters have yet to be restored after MC reboot 441 * @n_piobufs: Number of PIO buffers allocated to this function 442 * @wc_membase: Base address of write-combining mapping of the memory BAR 443 * @pio_write_base: Base address for writing PIO buffers 444 * @pio_write_vi_base: Relative VI number for @pio_write_base 445 * @piobuf_handle: Handle of each PIO buffer allocated 446 * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC 447 * reboot 448 * @rx_rss_context: Firmware handle for our RSS context 449 * @stats: Hardware statistics 450 * @workaround_35388: Flag: firmware supports workaround for bug 35388 451 * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated 452 * after MC reboot 453 * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of 454 * %MC_CMD_GET_CAPABILITIES response) 455 */ 456 struct efx_ef10_nic_data { 457 struct efx_buffer mcdi_buf; 458 u16 warm_boot_count; 459 unsigned int vi_base; 460 unsigned int n_allocated_vis; 461 bool must_realloc_vis; 462 bool must_restore_filters; 463 unsigned int n_piobufs; 464 void __iomem *wc_membase, *pio_write_base; 465 unsigned int pio_write_vi_base; 466 unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT]; 467 bool must_restore_piobufs; 468 u32 rx_rss_context; 469 u64 stats[EF10_STAT_COUNT]; 470 bool workaround_35388; 471 bool must_check_datapath_caps; 472 u32 datapath_caps; 473 }; 474 475 /* 476 * On the SFC9000 family each port is associated with 1 PCI physical 477 * function (PF) handled by sfc and a configurable number of virtual 478 * functions (VFs) that may be handled by some other driver, often in 479 * a VM guest. The queue pointer registers are mapped in both PF and 480 * VF BARs such that an 8K region provides access to a single RX, TX 481 * and event queue (collectively a Virtual Interface, VI or VNIC). 482 * 483 * The PF has access to all 1024 VIs while VFs are mapped to VIs 484 * according to VI_BASE and VI_SCALE: VF i has access to VIs numbered 485 * in range [VI_BASE + i << VI_SCALE, VI_BASE + i + 1 << VI_SCALE). 486 * The number of VIs and the VI_SCALE value are configurable but must 487 * be established at boot time by firmware. 488 */ 489 490 /* Maximum VI_SCALE parameter supported by Siena */ 491 #define EFX_VI_SCALE_MAX 6 492 /* Base VI to use for SR-IOV. Must be aligned to (1 << EFX_VI_SCALE_MAX), 493 * so this is the smallest allowed value. */ 494 #define EFX_VI_BASE 128U 495 /* Maximum number of VFs allowed */ 496 #define EFX_VF_COUNT_MAX 127 497 /* Limit EVQs on VFs to be only 8k to reduce buffer table reservation */ 498 #define EFX_MAX_VF_EVQ_SIZE 8192UL 499 /* The number of buffer table entries reserved for each VI on a VF */ 500 #define EFX_VF_BUFTBL_PER_VI \ 501 ((EFX_MAX_VF_EVQ_SIZE + 2 * EFX_MAX_DMAQ_SIZE) * \ 502 sizeof(efx_qword_t) / EFX_BUF_SIZE) 503 504 #ifdef CONFIG_SFC_SRIOV 505 506 static inline bool efx_sriov_wanted(struct efx_nic *efx) 507 { 508 return efx->vf_count != 0; 509 } 510 static inline bool efx_sriov_enabled(struct efx_nic *efx) 511 { 512 return efx->vf_init_count != 0; 513 } 514 static inline unsigned int efx_vf_size(struct efx_nic *efx) 515 { 516 return 1 << efx->vi_scale; 517 } 518 519 int efx_init_sriov(void); 520 void efx_sriov_probe(struct efx_nic *efx); 521 int efx_sriov_init(struct efx_nic *efx); 522 void efx_sriov_mac_address_changed(struct efx_nic *efx); 523 void efx_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event); 524 void efx_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event); 525 void efx_sriov_event(struct efx_channel *channel, efx_qword_t *event); 526 void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq); 527 void efx_sriov_flr(struct efx_nic *efx, unsigned flr); 528 void efx_sriov_reset(struct efx_nic *efx); 529 void efx_sriov_fini(struct efx_nic *efx); 530 void efx_fini_sriov(void); 531 532 #else 533 534 static inline bool efx_sriov_wanted(struct efx_nic *efx) { return false; } 535 static inline bool efx_sriov_enabled(struct efx_nic *efx) { return false; } 536 static inline unsigned int efx_vf_size(struct efx_nic *efx) { return 0; } 537 538 static inline int efx_init_sriov(void) { return 0; } 539 static inline void efx_sriov_probe(struct efx_nic *efx) {} 540 static inline int efx_sriov_init(struct efx_nic *efx) { return -EOPNOTSUPP; } 541 static inline void efx_sriov_mac_address_changed(struct efx_nic *efx) {} 542 static inline void efx_sriov_tx_flush_done(struct efx_nic *efx, 543 efx_qword_t *event) {} 544 static inline void efx_sriov_rx_flush_done(struct efx_nic *efx, 545 efx_qword_t *event) {} 546 static inline void efx_sriov_event(struct efx_channel *channel, 547 efx_qword_t *event) {} 548 static inline void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq) {} 549 static inline void efx_sriov_flr(struct efx_nic *efx, unsigned flr) {} 550 static inline void efx_sriov_reset(struct efx_nic *efx) {} 551 static inline void efx_sriov_fini(struct efx_nic *efx) {} 552 static inline void efx_fini_sriov(void) {} 553 554 #endif 555 556 int efx_sriov_set_vf_mac(struct net_device *dev, int vf, u8 *mac); 557 int efx_sriov_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos); 558 int efx_sriov_get_vf_config(struct net_device *dev, int vf, 559 struct ifla_vf_info *ivf); 560 int efx_sriov_set_vf_spoofchk(struct net_device *net_dev, int vf, 561 bool spoofchk); 562 563 struct ethtool_ts_info; 564 int efx_ptp_probe(struct efx_nic *efx, struct efx_channel *channel); 565 void efx_ptp_defer_probe_with_channel(struct efx_nic *efx); 566 void efx_ptp_remove(struct efx_nic *efx); 567 int efx_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr); 568 int efx_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr); 569 void efx_ptp_get_ts_info(struct efx_nic *efx, struct ethtool_ts_info *ts_info); 570 bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb); 571 int efx_ptp_get_mode(struct efx_nic *efx); 572 int efx_ptp_change_mode(struct efx_nic *efx, bool enable_wanted, 573 unsigned int new_mode); 574 int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb); 575 void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev); 576 size_t efx_ptp_describe_stats(struct efx_nic *efx, u8 *strings); 577 size_t efx_ptp_update_stats(struct efx_nic *efx, u64 *stats); 578 void efx_time_sync_event(struct efx_channel *channel, efx_qword_t *ev); 579 void __efx_rx_skb_attach_timestamp(struct efx_channel *channel, 580 struct sk_buff *skb); 581 static inline void efx_rx_skb_attach_timestamp(struct efx_channel *channel, 582 struct sk_buff *skb) 583 { 584 if (channel->sync_events_state == SYNC_EVENTS_VALID) 585 __efx_rx_skb_attach_timestamp(channel, skb); 586 } 587 void efx_ptp_start_datapath(struct efx_nic *efx); 588 void efx_ptp_stop_datapath(struct efx_nic *efx); 589 590 extern const struct efx_nic_type falcon_a1_nic_type; 591 extern const struct efx_nic_type falcon_b0_nic_type; 592 extern const struct efx_nic_type siena_a0_nic_type; 593 extern const struct efx_nic_type efx_hunt_a0_nic_type; 594 595 /************************************************************************** 596 * 597 * Externs 598 * 599 ************************************************************************** 600 */ 601 602 int falcon_probe_board(struct efx_nic *efx, u16 revision_info); 603 604 /* TX data path */ 605 static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue) 606 { 607 return tx_queue->efx->type->tx_probe(tx_queue); 608 } 609 static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue) 610 { 611 tx_queue->efx->type->tx_init(tx_queue); 612 } 613 static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue) 614 { 615 tx_queue->efx->type->tx_remove(tx_queue); 616 } 617 static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue) 618 { 619 tx_queue->efx->type->tx_write(tx_queue); 620 } 621 622 /* RX data path */ 623 static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue) 624 { 625 return rx_queue->efx->type->rx_probe(rx_queue); 626 } 627 static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue) 628 { 629 rx_queue->efx->type->rx_init(rx_queue); 630 } 631 static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue) 632 { 633 rx_queue->efx->type->rx_remove(rx_queue); 634 } 635 static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue) 636 { 637 rx_queue->efx->type->rx_write(rx_queue); 638 } 639 static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue) 640 { 641 rx_queue->efx->type->rx_defer_refill(rx_queue); 642 } 643 644 /* Event data path */ 645 static inline int efx_nic_probe_eventq(struct efx_channel *channel) 646 { 647 return channel->efx->type->ev_probe(channel); 648 } 649 static inline int efx_nic_init_eventq(struct efx_channel *channel) 650 { 651 return channel->efx->type->ev_init(channel); 652 } 653 static inline void efx_nic_fini_eventq(struct efx_channel *channel) 654 { 655 channel->efx->type->ev_fini(channel); 656 } 657 static inline void efx_nic_remove_eventq(struct efx_channel *channel) 658 { 659 channel->efx->type->ev_remove(channel); 660 } 661 static inline int 662 efx_nic_process_eventq(struct efx_channel *channel, int quota) 663 { 664 return channel->efx->type->ev_process(channel, quota); 665 } 666 static inline void efx_nic_eventq_read_ack(struct efx_channel *channel) 667 { 668 channel->efx->type->ev_read_ack(channel); 669 } 670 void efx_nic_event_test_start(struct efx_channel *channel); 671 672 /* Falcon/Siena queue operations */ 673 int efx_farch_tx_probe(struct efx_tx_queue *tx_queue); 674 void efx_farch_tx_init(struct efx_tx_queue *tx_queue); 675 void efx_farch_tx_fini(struct efx_tx_queue *tx_queue); 676 void efx_farch_tx_remove(struct efx_tx_queue *tx_queue); 677 void efx_farch_tx_write(struct efx_tx_queue *tx_queue); 678 int efx_farch_rx_probe(struct efx_rx_queue *rx_queue); 679 void efx_farch_rx_init(struct efx_rx_queue *rx_queue); 680 void efx_farch_rx_fini(struct efx_rx_queue *rx_queue); 681 void efx_farch_rx_remove(struct efx_rx_queue *rx_queue); 682 void efx_farch_rx_write(struct efx_rx_queue *rx_queue); 683 void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue); 684 int efx_farch_ev_probe(struct efx_channel *channel); 685 int efx_farch_ev_init(struct efx_channel *channel); 686 void efx_farch_ev_fini(struct efx_channel *channel); 687 void efx_farch_ev_remove(struct efx_channel *channel); 688 int efx_farch_ev_process(struct efx_channel *channel, int quota); 689 void efx_farch_ev_read_ack(struct efx_channel *channel); 690 void efx_farch_ev_test_generate(struct efx_channel *channel); 691 692 /* Falcon/Siena filter operations */ 693 int efx_farch_filter_table_probe(struct efx_nic *efx); 694 void efx_farch_filter_table_restore(struct efx_nic *efx); 695 void efx_farch_filter_table_remove(struct efx_nic *efx); 696 void efx_farch_filter_update_rx_scatter(struct efx_nic *efx); 697 s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec, 698 bool replace); 699 int efx_farch_filter_remove_safe(struct efx_nic *efx, 700 enum efx_filter_priority priority, 701 u32 filter_id); 702 int efx_farch_filter_get_safe(struct efx_nic *efx, 703 enum efx_filter_priority priority, u32 filter_id, 704 struct efx_filter_spec *); 705 int efx_farch_filter_clear_rx(struct efx_nic *efx, 706 enum efx_filter_priority priority); 707 u32 efx_farch_filter_count_rx_used(struct efx_nic *efx, 708 enum efx_filter_priority priority); 709 u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx); 710 s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx, 711 enum efx_filter_priority priority, u32 *buf, 712 u32 size); 713 #ifdef CONFIG_RFS_ACCEL 714 s32 efx_farch_filter_rfs_insert(struct efx_nic *efx, 715 struct efx_filter_spec *spec); 716 bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, 717 unsigned int index); 718 #endif 719 void efx_farch_filter_sync_rx_mode(struct efx_nic *efx); 720 721 bool efx_nic_event_present(struct efx_channel *channel); 722 723 /* Some statistics are computed as A - B where A and B each increase 724 * linearly with some hardware counter(s) and the counters are read 725 * asynchronously. If the counters contributing to B are always read 726 * after those contributing to A, the computed value may be lower than 727 * the true value by some variable amount, and may decrease between 728 * subsequent computations. 729 * 730 * We should never allow statistics to decrease or to exceed the true 731 * value. Since the computed value will never be greater than the 732 * true value, we can achieve this by only storing the computed value 733 * when it increases. 734 */ 735 static inline void efx_update_diff_stat(u64 *stat, u64 diff) 736 { 737 if ((s64)(diff - *stat) > 0) 738 *stat = diff; 739 } 740 741 /* Interrupts */ 742 int efx_nic_init_interrupt(struct efx_nic *efx); 743 void efx_nic_irq_test_start(struct efx_nic *efx); 744 void efx_nic_fini_interrupt(struct efx_nic *efx); 745 746 /* Falcon/Siena interrupts */ 747 void efx_farch_irq_enable_master(struct efx_nic *efx); 748 void efx_farch_irq_test_generate(struct efx_nic *efx); 749 void efx_farch_irq_disable_master(struct efx_nic *efx); 750 irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id); 751 irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id); 752 irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx); 753 754 static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel) 755 { 756 return ACCESS_ONCE(channel->event_test_cpu); 757 } 758 static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx) 759 { 760 return ACCESS_ONCE(efx->last_irq_cpu); 761 } 762 763 /* Global Resources */ 764 int efx_nic_flush_queues(struct efx_nic *efx); 765 void siena_prepare_flush(struct efx_nic *efx); 766 int efx_farch_fini_dmaq(struct efx_nic *efx); 767 void efx_farch_finish_flr(struct efx_nic *efx); 768 void siena_finish_flush(struct efx_nic *efx); 769 void falcon_start_nic_stats(struct efx_nic *efx); 770 void falcon_stop_nic_stats(struct efx_nic *efx); 771 int falcon_reset_xaui(struct efx_nic *efx); 772 void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw); 773 void efx_farch_init_common(struct efx_nic *efx); 774 void efx_ef10_handle_drain_event(struct efx_nic *efx); 775 void efx_farch_rx_push_indir_table(struct efx_nic *efx); 776 777 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, 778 unsigned int len, gfp_t gfp_flags); 779 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer); 780 781 /* Tests */ 782 struct efx_farch_register_test { 783 unsigned address; 784 efx_oword_t mask; 785 }; 786 int efx_farch_test_registers(struct efx_nic *efx, 787 const struct efx_farch_register_test *regs, 788 size_t n_regs); 789 790 size_t efx_nic_get_regs_len(struct efx_nic *efx); 791 void efx_nic_get_regs(struct efx_nic *efx, void *buf); 792 793 size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count, 794 const unsigned long *mask, u8 *names); 795 void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count, 796 const unsigned long *mask, u64 *stats, 797 const void *dma_buf, bool accumulate); 798 void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat); 799 800 #define EFX_MAX_FLUSH_TIME 5000 801 802 void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq, 803 efx_qword_t *event); 804 805 #endif /* EFX_NIC_H */ 806