1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2006-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #ifndef EFX_NIC_H 12 #define EFX_NIC_H 13 14 #include <linux/net_tstamp.h> 15 #include <linux/i2c-algo-bit.h> 16 #include "net_driver.h" 17 #include "efx.h" 18 #include "mcdi.h" 19 20 enum { 21 EFX_REV_FALCON_A0 = 0, 22 EFX_REV_FALCON_A1 = 1, 23 EFX_REV_FALCON_B0 = 2, 24 EFX_REV_SIENA_A0 = 3, 25 EFX_REV_HUNT_A0 = 4, 26 }; 27 28 static inline int efx_nic_rev(struct efx_nic *efx) 29 { 30 return efx->type->revision; 31 } 32 33 u32 efx_farch_fpga_ver(struct efx_nic *efx); 34 35 /* NIC has two interlinked PCI functions for the same port. */ 36 static inline bool efx_nic_is_dual_func(struct efx_nic *efx) 37 { 38 return efx_nic_rev(efx) < EFX_REV_FALCON_B0; 39 } 40 41 /* Read the current event from the event queue */ 42 static inline efx_qword_t *efx_event(struct efx_channel *channel, 43 unsigned int index) 44 { 45 return ((efx_qword_t *) (channel->eventq.buf.addr)) + 46 (index & channel->eventq_mask); 47 } 48 49 /* See if an event is present 50 * 51 * We check both the high and low dword of the event for all ones. We 52 * wrote all ones when we cleared the event, and no valid event can 53 * have all ones in either its high or low dwords. This approach is 54 * robust against reordering. 55 * 56 * Note that using a single 64-bit comparison is incorrect; even 57 * though the CPU read will be atomic, the DMA write may not be. 58 */ 59 static inline int efx_event_present(efx_qword_t *event) 60 { 61 return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | 62 EFX_DWORD_IS_ALL_ONES(event->dword[1])); 63 } 64 65 /* Returns a pointer to the specified transmit descriptor in the TX 66 * descriptor queue belonging to the specified channel. 67 */ 68 static inline efx_qword_t * 69 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index) 70 { 71 return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index; 72 } 73 74 /* Report whether the NIC considers this TX queue empty, given the 75 * write_count used for the last doorbell push. May return false 76 * negative. 77 */ 78 static inline bool __efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue, 79 unsigned int write_count) 80 { 81 unsigned int empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count); 82 83 if (empty_read_count == 0) 84 return false; 85 86 return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0; 87 } 88 89 static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue) 90 { 91 return __efx_nic_tx_is_empty(tx_queue, tx_queue->write_count); 92 } 93 94 /* Decide whether to push a TX descriptor to the NIC vs merely writing 95 * the doorbell. This can reduce latency when we are adding a single 96 * descriptor to an empty queue, but is otherwise pointless. Further, 97 * Falcon and Siena have hardware bugs (SF bug 33851) that may be 98 * triggered if we don't check this. 99 */ 100 static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue, 101 unsigned int write_count) 102 { 103 bool was_empty = __efx_nic_tx_is_empty(tx_queue, write_count); 104 105 tx_queue->empty_read_count = 0; 106 return was_empty && tx_queue->write_count - write_count == 1; 107 } 108 109 /* Returns a pointer to the specified descriptor in the RX descriptor queue */ 110 static inline efx_qword_t * 111 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 112 { 113 return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index; 114 } 115 116 enum { 117 PHY_TYPE_NONE = 0, 118 PHY_TYPE_TXC43128 = 1, 119 PHY_TYPE_88E1111 = 2, 120 PHY_TYPE_SFX7101 = 3, 121 PHY_TYPE_QT2022C2 = 4, 122 PHY_TYPE_PM8358 = 6, 123 PHY_TYPE_SFT9001A = 8, 124 PHY_TYPE_QT2025C = 9, 125 PHY_TYPE_SFT9001B = 10, 126 }; 127 128 #define FALCON_XMAC_LOOPBACKS \ 129 ((1 << LOOPBACK_XGMII) | \ 130 (1 << LOOPBACK_XGXS) | \ 131 (1 << LOOPBACK_XAUI)) 132 133 /* Alignment of PCIe DMA boundaries (4KB) */ 134 #define EFX_PAGE_SIZE 4096 135 /* Size and alignment of buffer table entries (same) */ 136 #define EFX_BUF_SIZE EFX_PAGE_SIZE 137 138 /** 139 * struct falcon_board_type - board operations and type information 140 * @id: Board type id, as found in NVRAM 141 * @init: Allocate resources and initialise peripheral hardware 142 * @init_phy: Do board-specific PHY initialisation 143 * @fini: Shut down hardware and free resources 144 * @set_id_led: Set state of identifying LED or revert to automatic function 145 * @monitor: Board-specific health check function 146 */ 147 struct falcon_board_type { 148 u8 id; 149 int (*init) (struct efx_nic *nic); 150 void (*init_phy) (struct efx_nic *efx); 151 void (*fini) (struct efx_nic *nic); 152 void (*set_id_led) (struct efx_nic *efx, enum efx_led_mode mode); 153 int (*monitor) (struct efx_nic *nic); 154 }; 155 156 /** 157 * struct falcon_board - board information 158 * @type: Type of board 159 * @major: Major rev. ('A', 'B' ...) 160 * @minor: Minor rev. (0, 1, ...) 161 * @i2c_adap: I2C adapter for on-board peripherals 162 * @i2c_data: Data for bit-banging algorithm 163 * @hwmon_client: I2C client for hardware monitor 164 * @ioexp_client: I2C client for power/port control 165 */ 166 struct falcon_board { 167 const struct falcon_board_type *type; 168 int major; 169 int minor; 170 struct i2c_adapter i2c_adap; 171 struct i2c_algo_bit_data i2c_data; 172 struct i2c_client *hwmon_client, *ioexp_client; 173 }; 174 175 /** 176 * struct falcon_spi_device - a Falcon SPI (Serial Peripheral Interface) device 177 * @device_id: Controller's id for the device 178 * @size: Size (in bytes) 179 * @addr_len: Number of address bytes in read/write commands 180 * @munge_address: Flag whether addresses should be munged. 181 * Some devices with 9-bit addresses (e.g. AT25040A EEPROM) 182 * use bit 3 of the command byte as address bit A8, rather 183 * than having a two-byte address. If this flag is set, then 184 * commands should be munged in this way. 185 * @erase_command: Erase command (or 0 if sector erase not needed). 186 * @erase_size: Erase sector size (in bytes) 187 * Erase commands affect sectors with this size and alignment. 188 * This must be a power of two. 189 * @block_size: Write block size (in bytes). 190 * Write commands are limited to blocks with this size and alignment. 191 */ 192 struct falcon_spi_device { 193 int device_id; 194 unsigned int size; 195 unsigned int addr_len; 196 unsigned int munge_address:1; 197 u8 erase_command; 198 unsigned int erase_size; 199 unsigned int block_size; 200 }; 201 202 static inline bool falcon_spi_present(const struct falcon_spi_device *spi) 203 { 204 return spi->size != 0; 205 } 206 207 enum { 208 FALCON_STAT_tx_bytes, 209 FALCON_STAT_tx_packets, 210 FALCON_STAT_tx_pause, 211 FALCON_STAT_tx_control, 212 FALCON_STAT_tx_unicast, 213 FALCON_STAT_tx_multicast, 214 FALCON_STAT_tx_broadcast, 215 FALCON_STAT_tx_lt64, 216 FALCON_STAT_tx_64, 217 FALCON_STAT_tx_65_to_127, 218 FALCON_STAT_tx_128_to_255, 219 FALCON_STAT_tx_256_to_511, 220 FALCON_STAT_tx_512_to_1023, 221 FALCON_STAT_tx_1024_to_15xx, 222 FALCON_STAT_tx_15xx_to_jumbo, 223 FALCON_STAT_tx_gtjumbo, 224 FALCON_STAT_tx_non_tcpudp, 225 FALCON_STAT_tx_mac_src_error, 226 FALCON_STAT_tx_ip_src_error, 227 FALCON_STAT_rx_bytes, 228 FALCON_STAT_rx_good_bytes, 229 FALCON_STAT_rx_bad_bytes, 230 FALCON_STAT_rx_packets, 231 FALCON_STAT_rx_good, 232 FALCON_STAT_rx_bad, 233 FALCON_STAT_rx_pause, 234 FALCON_STAT_rx_control, 235 FALCON_STAT_rx_unicast, 236 FALCON_STAT_rx_multicast, 237 FALCON_STAT_rx_broadcast, 238 FALCON_STAT_rx_lt64, 239 FALCON_STAT_rx_64, 240 FALCON_STAT_rx_65_to_127, 241 FALCON_STAT_rx_128_to_255, 242 FALCON_STAT_rx_256_to_511, 243 FALCON_STAT_rx_512_to_1023, 244 FALCON_STAT_rx_1024_to_15xx, 245 FALCON_STAT_rx_15xx_to_jumbo, 246 FALCON_STAT_rx_gtjumbo, 247 FALCON_STAT_rx_bad_lt64, 248 FALCON_STAT_rx_bad_gtjumbo, 249 FALCON_STAT_rx_overflow, 250 FALCON_STAT_rx_symbol_error, 251 FALCON_STAT_rx_align_error, 252 FALCON_STAT_rx_length_error, 253 FALCON_STAT_rx_internal_error, 254 FALCON_STAT_rx_nodesc_drop_cnt, 255 FALCON_STAT_COUNT 256 }; 257 258 /** 259 * struct falcon_nic_data - Falcon NIC state 260 * @pci_dev2: Secondary function of Falcon A 261 * @board: Board state and functions 262 * @stats: Hardware statistics 263 * @stats_disable_count: Nest count for disabling statistics fetches 264 * @stats_pending: Is there a pending DMA of MAC statistics. 265 * @stats_timer: A timer for regularly fetching MAC statistics. 266 * @spi_flash: SPI flash device 267 * @spi_eeprom: SPI EEPROM device 268 * @spi_lock: SPI bus lock 269 * @mdio_lock: MDIO bus lock 270 * @xmac_poll_required: XMAC link state needs polling 271 */ 272 struct falcon_nic_data { 273 struct pci_dev *pci_dev2; 274 struct falcon_board board; 275 u64 stats[FALCON_STAT_COUNT]; 276 unsigned int stats_disable_count; 277 bool stats_pending; 278 struct timer_list stats_timer; 279 struct falcon_spi_device spi_flash; 280 struct falcon_spi_device spi_eeprom; 281 struct mutex spi_lock; 282 struct mutex mdio_lock; 283 bool xmac_poll_required; 284 }; 285 286 static inline struct falcon_board *falcon_board(struct efx_nic *efx) 287 { 288 struct falcon_nic_data *data = efx->nic_data; 289 return &data->board; 290 } 291 292 enum { 293 SIENA_STAT_tx_bytes, 294 SIENA_STAT_tx_good_bytes, 295 SIENA_STAT_tx_bad_bytes, 296 SIENA_STAT_tx_packets, 297 SIENA_STAT_tx_bad, 298 SIENA_STAT_tx_pause, 299 SIENA_STAT_tx_control, 300 SIENA_STAT_tx_unicast, 301 SIENA_STAT_tx_multicast, 302 SIENA_STAT_tx_broadcast, 303 SIENA_STAT_tx_lt64, 304 SIENA_STAT_tx_64, 305 SIENA_STAT_tx_65_to_127, 306 SIENA_STAT_tx_128_to_255, 307 SIENA_STAT_tx_256_to_511, 308 SIENA_STAT_tx_512_to_1023, 309 SIENA_STAT_tx_1024_to_15xx, 310 SIENA_STAT_tx_15xx_to_jumbo, 311 SIENA_STAT_tx_gtjumbo, 312 SIENA_STAT_tx_collision, 313 SIENA_STAT_tx_single_collision, 314 SIENA_STAT_tx_multiple_collision, 315 SIENA_STAT_tx_excessive_collision, 316 SIENA_STAT_tx_deferred, 317 SIENA_STAT_tx_late_collision, 318 SIENA_STAT_tx_excessive_deferred, 319 SIENA_STAT_tx_non_tcpudp, 320 SIENA_STAT_tx_mac_src_error, 321 SIENA_STAT_tx_ip_src_error, 322 SIENA_STAT_rx_bytes, 323 SIENA_STAT_rx_good_bytes, 324 SIENA_STAT_rx_bad_bytes, 325 SIENA_STAT_rx_packets, 326 SIENA_STAT_rx_good, 327 SIENA_STAT_rx_bad, 328 SIENA_STAT_rx_pause, 329 SIENA_STAT_rx_control, 330 SIENA_STAT_rx_unicast, 331 SIENA_STAT_rx_multicast, 332 SIENA_STAT_rx_broadcast, 333 SIENA_STAT_rx_lt64, 334 SIENA_STAT_rx_64, 335 SIENA_STAT_rx_65_to_127, 336 SIENA_STAT_rx_128_to_255, 337 SIENA_STAT_rx_256_to_511, 338 SIENA_STAT_rx_512_to_1023, 339 SIENA_STAT_rx_1024_to_15xx, 340 SIENA_STAT_rx_15xx_to_jumbo, 341 SIENA_STAT_rx_gtjumbo, 342 SIENA_STAT_rx_bad_gtjumbo, 343 SIENA_STAT_rx_overflow, 344 SIENA_STAT_rx_false_carrier, 345 SIENA_STAT_rx_symbol_error, 346 SIENA_STAT_rx_align_error, 347 SIENA_STAT_rx_length_error, 348 SIENA_STAT_rx_internal_error, 349 SIENA_STAT_rx_nodesc_drop_cnt, 350 SIENA_STAT_COUNT 351 }; 352 353 /** 354 * struct siena_nic_data - Siena NIC state 355 * @wol_filter_id: Wake-on-LAN packet filter id 356 * @stats: Hardware statistics 357 */ 358 struct siena_nic_data { 359 int wol_filter_id; 360 u64 stats[SIENA_STAT_COUNT]; 361 }; 362 363 enum { 364 EF10_STAT_tx_bytes, 365 EF10_STAT_tx_packets, 366 EF10_STAT_tx_pause, 367 EF10_STAT_tx_control, 368 EF10_STAT_tx_unicast, 369 EF10_STAT_tx_multicast, 370 EF10_STAT_tx_broadcast, 371 EF10_STAT_tx_lt64, 372 EF10_STAT_tx_64, 373 EF10_STAT_tx_65_to_127, 374 EF10_STAT_tx_128_to_255, 375 EF10_STAT_tx_256_to_511, 376 EF10_STAT_tx_512_to_1023, 377 EF10_STAT_tx_1024_to_15xx, 378 EF10_STAT_tx_15xx_to_jumbo, 379 EF10_STAT_rx_bytes, 380 EF10_STAT_rx_bytes_minus_good_bytes, 381 EF10_STAT_rx_good_bytes, 382 EF10_STAT_rx_bad_bytes, 383 EF10_STAT_rx_packets, 384 EF10_STAT_rx_good, 385 EF10_STAT_rx_bad, 386 EF10_STAT_rx_pause, 387 EF10_STAT_rx_control, 388 EF10_STAT_rx_unicast, 389 EF10_STAT_rx_multicast, 390 EF10_STAT_rx_broadcast, 391 EF10_STAT_rx_lt64, 392 EF10_STAT_rx_64, 393 EF10_STAT_rx_65_to_127, 394 EF10_STAT_rx_128_to_255, 395 EF10_STAT_rx_256_to_511, 396 EF10_STAT_rx_512_to_1023, 397 EF10_STAT_rx_1024_to_15xx, 398 EF10_STAT_rx_15xx_to_jumbo, 399 EF10_STAT_rx_gtjumbo, 400 EF10_STAT_rx_bad_gtjumbo, 401 EF10_STAT_rx_overflow, 402 EF10_STAT_rx_align_error, 403 EF10_STAT_rx_length_error, 404 EF10_STAT_rx_nodesc_drops, 405 EF10_STAT_rx_pm_trunc_bb_overflow, 406 EF10_STAT_rx_pm_discard_bb_overflow, 407 EF10_STAT_rx_pm_trunc_vfifo_full, 408 EF10_STAT_rx_pm_discard_vfifo_full, 409 EF10_STAT_rx_pm_trunc_qbb, 410 EF10_STAT_rx_pm_discard_qbb, 411 EF10_STAT_rx_pm_discard_mapping, 412 EF10_STAT_rx_dp_q_disabled_packets, 413 EF10_STAT_rx_dp_di_dropped_packets, 414 EF10_STAT_rx_dp_streaming_packets, 415 EF10_STAT_rx_dp_emerg_fetch, 416 EF10_STAT_rx_dp_emerg_wait, 417 EF10_STAT_COUNT 418 }; 419 420 /* Maximum number of TX PIO buffers we may allocate to a function. 421 * This matches the total number of buffers on each SFC9100-family 422 * controller. 423 */ 424 #define EF10_TX_PIOBUF_COUNT 16 425 426 /** 427 * struct efx_ef10_nic_data - EF10 architecture NIC state 428 * @mcdi_buf: DMA buffer for MCDI 429 * @warm_boot_count: Last seen MC warm boot count 430 * @vi_base: Absolute index of first VI in this function 431 * @n_allocated_vis: Number of VIs allocated to this function 432 * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot 433 * @must_restore_filters: Flag: filters have yet to be restored after MC reboot 434 * @n_piobufs: Number of PIO buffers allocated to this function 435 * @wc_membase: Base address of write-combining mapping of the memory BAR 436 * @pio_write_base: Base address for writing PIO buffers 437 * @pio_write_vi_base: Relative VI number for @pio_write_base 438 * @piobuf_handle: Handle of each PIO buffer allocated 439 * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC 440 * reboot 441 * @rx_rss_context: Firmware handle for our RSS context 442 * @stats: Hardware statistics 443 * @workaround_35388: Flag: firmware supports workaround for bug 35388 444 * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated 445 * after MC reboot 446 * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of 447 * %MC_CMD_GET_CAPABILITIES response) 448 */ 449 struct efx_ef10_nic_data { 450 struct efx_buffer mcdi_buf; 451 u16 warm_boot_count; 452 unsigned int vi_base; 453 unsigned int n_allocated_vis; 454 bool must_realloc_vis; 455 bool must_restore_filters; 456 unsigned int n_piobufs; 457 void __iomem *wc_membase, *pio_write_base; 458 unsigned int pio_write_vi_base; 459 unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT]; 460 bool must_restore_piobufs; 461 u32 rx_rss_context; 462 u64 stats[EF10_STAT_COUNT]; 463 bool workaround_35388; 464 bool must_check_datapath_caps; 465 u32 datapath_caps; 466 }; 467 468 /* 469 * On the SFC9000 family each port is associated with 1 PCI physical 470 * function (PF) handled by sfc and a configurable number of virtual 471 * functions (VFs) that may be handled by some other driver, often in 472 * a VM guest. The queue pointer registers are mapped in both PF and 473 * VF BARs such that an 8K region provides access to a single RX, TX 474 * and event queue (collectively a Virtual Interface, VI or VNIC). 475 * 476 * The PF has access to all 1024 VIs while VFs are mapped to VIs 477 * according to VI_BASE and VI_SCALE: VF i has access to VIs numbered 478 * in range [VI_BASE + i << VI_SCALE, VI_BASE + i + 1 << VI_SCALE). 479 * The number of VIs and the VI_SCALE value are configurable but must 480 * be established at boot time by firmware. 481 */ 482 483 /* Maximum VI_SCALE parameter supported by Siena */ 484 #define EFX_VI_SCALE_MAX 6 485 /* Base VI to use for SR-IOV. Must be aligned to (1 << EFX_VI_SCALE_MAX), 486 * so this is the smallest allowed value. */ 487 #define EFX_VI_BASE 128U 488 /* Maximum number of VFs allowed */ 489 #define EFX_VF_COUNT_MAX 127 490 /* Limit EVQs on VFs to be only 8k to reduce buffer table reservation */ 491 #define EFX_MAX_VF_EVQ_SIZE 8192UL 492 /* The number of buffer table entries reserved for each VI on a VF */ 493 #define EFX_VF_BUFTBL_PER_VI \ 494 ((EFX_MAX_VF_EVQ_SIZE + 2 * EFX_MAX_DMAQ_SIZE) * \ 495 sizeof(efx_qword_t) / EFX_BUF_SIZE) 496 497 #ifdef CONFIG_SFC_SRIOV 498 499 static inline bool efx_sriov_wanted(struct efx_nic *efx) 500 { 501 return efx->vf_count != 0; 502 } 503 static inline bool efx_sriov_enabled(struct efx_nic *efx) 504 { 505 return efx->vf_init_count != 0; 506 } 507 static inline unsigned int efx_vf_size(struct efx_nic *efx) 508 { 509 return 1 << efx->vi_scale; 510 } 511 512 int efx_init_sriov(void); 513 void efx_sriov_probe(struct efx_nic *efx); 514 int efx_sriov_init(struct efx_nic *efx); 515 void efx_sriov_mac_address_changed(struct efx_nic *efx); 516 void efx_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event); 517 void efx_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event); 518 void efx_sriov_event(struct efx_channel *channel, efx_qword_t *event); 519 void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq); 520 void efx_sriov_flr(struct efx_nic *efx, unsigned flr); 521 void efx_sriov_reset(struct efx_nic *efx); 522 void efx_sriov_fini(struct efx_nic *efx); 523 void efx_fini_sriov(void); 524 525 #else 526 527 static inline bool efx_sriov_wanted(struct efx_nic *efx) { return false; } 528 static inline bool efx_sriov_enabled(struct efx_nic *efx) { return false; } 529 static inline unsigned int efx_vf_size(struct efx_nic *efx) { return 0; } 530 531 static inline int efx_init_sriov(void) { return 0; } 532 static inline void efx_sriov_probe(struct efx_nic *efx) {} 533 static inline int efx_sriov_init(struct efx_nic *efx) { return -EOPNOTSUPP; } 534 static inline void efx_sriov_mac_address_changed(struct efx_nic *efx) {} 535 static inline void efx_sriov_tx_flush_done(struct efx_nic *efx, 536 efx_qword_t *event) {} 537 static inline void efx_sriov_rx_flush_done(struct efx_nic *efx, 538 efx_qword_t *event) {} 539 static inline void efx_sriov_event(struct efx_channel *channel, 540 efx_qword_t *event) {} 541 static inline void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq) {} 542 static inline void efx_sriov_flr(struct efx_nic *efx, unsigned flr) {} 543 static inline void efx_sriov_reset(struct efx_nic *efx) {} 544 static inline void efx_sriov_fini(struct efx_nic *efx) {} 545 static inline void efx_fini_sriov(void) {} 546 547 #endif 548 549 int efx_sriov_set_vf_mac(struct net_device *dev, int vf, u8 *mac); 550 int efx_sriov_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos); 551 int efx_sriov_get_vf_config(struct net_device *dev, int vf, 552 struct ifla_vf_info *ivf); 553 int efx_sriov_set_vf_spoofchk(struct net_device *net_dev, int vf, 554 bool spoofchk); 555 556 struct ethtool_ts_info; 557 void efx_ptp_probe(struct efx_nic *efx); 558 int efx_ptp_ioctl(struct efx_nic *efx, struct ifreq *ifr, int cmd); 559 void efx_ptp_get_ts_info(struct efx_nic *efx, struct ethtool_ts_info *ts_info); 560 bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb); 561 int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb); 562 void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev); 563 void efx_ptp_start_datapath(struct efx_nic *efx); 564 void efx_ptp_stop_datapath(struct efx_nic *efx); 565 566 extern const struct efx_nic_type falcon_a1_nic_type; 567 extern const struct efx_nic_type falcon_b0_nic_type; 568 extern const struct efx_nic_type siena_a0_nic_type; 569 extern const struct efx_nic_type efx_hunt_a0_nic_type; 570 571 /************************************************************************** 572 * 573 * Externs 574 * 575 ************************************************************************** 576 */ 577 578 int falcon_probe_board(struct efx_nic *efx, u16 revision_info); 579 580 /* TX data path */ 581 static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue) 582 { 583 return tx_queue->efx->type->tx_probe(tx_queue); 584 } 585 static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue) 586 { 587 tx_queue->efx->type->tx_init(tx_queue); 588 } 589 static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue) 590 { 591 tx_queue->efx->type->tx_remove(tx_queue); 592 } 593 static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue) 594 { 595 tx_queue->efx->type->tx_write(tx_queue); 596 } 597 598 /* RX data path */ 599 static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue) 600 { 601 return rx_queue->efx->type->rx_probe(rx_queue); 602 } 603 static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue) 604 { 605 rx_queue->efx->type->rx_init(rx_queue); 606 } 607 static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue) 608 { 609 rx_queue->efx->type->rx_remove(rx_queue); 610 } 611 static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue) 612 { 613 rx_queue->efx->type->rx_write(rx_queue); 614 } 615 static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue) 616 { 617 rx_queue->efx->type->rx_defer_refill(rx_queue); 618 } 619 620 /* Event data path */ 621 static inline int efx_nic_probe_eventq(struct efx_channel *channel) 622 { 623 return channel->efx->type->ev_probe(channel); 624 } 625 static inline int efx_nic_init_eventq(struct efx_channel *channel) 626 { 627 return channel->efx->type->ev_init(channel); 628 } 629 static inline void efx_nic_fini_eventq(struct efx_channel *channel) 630 { 631 channel->efx->type->ev_fini(channel); 632 } 633 static inline void efx_nic_remove_eventq(struct efx_channel *channel) 634 { 635 channel->efx->type->ev_remove(channel); 636 } 637 static inline int 638 efx_nic_process_eventq(struct efx_channel *channel, int quota) 639 { 640 return channel->efx->type->ev_process(channel, quota); 641 } 642 static inline void efx_nic_eventq_read_ack(struct efx_channel *channel) 643 { 644 channel->efx->type->ev_read_ack(channel); 645 } 646 void efx_nic_event_test_start(struct efx_channel *channel); 647 648 /* Falcon/Siena queue operations */ 649 int efx_farch_tx_probe(struct efx_tx_queue *tx_queue); 650 void efx_farch_tx_init(struct efx_tx_queue *tx_queue); 651 void efx_farch_tx_fini(struct efx_tx_queue *tx_queue); 652 void efx_farch_tx_remove(struct efx_tx_queue *tx_queue); 653 void efx_farch_tx_write(struct efx_tx_queue *tx_queue); 654 int efx_farch_rx_probe(struct efx_rx_queue *rx_queue); 655 void efx_farch_rx_init(struct efx_rx_queue *rx_queue); 656 void efx_farch_rx_fini(struct efx_rx_queue *rx_queue); 657 void efx_farch_rx_remove(struct efx_rx_queue *rx_queue); 658 void efx_farch_rx_write(struct efx_rx_queue *rx_queue); 659 void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue); 660 int efx_farch_ev_probe(struct efx_channel *channel); 661 int efx_farch_ev_init(struct efx_channel *channel); 662 void efx_farch_ev_fini(struct efx_channel *channel); 663 void efx_farch_ev_remove(struct efx_channel *channel); 664 int efx_farch_ev_process(struct efx_channel *channel, int quota); 665 void efx_farch_ev_read_ack(struct efx_channel *channel); 666 void efx_farch_ev_test_generate(struct efx_channel *channel); 667 668 /* Falcon/Siena filter operations */ 669 int efx_farch_filter_table_probe(struct efx_nic *efx); 670 void efx_farch_filter_table_restore(struct efx_nic *efx); 671 void efx_farch_filter_table_remove(struct efx_nic *efx); 672 void efx_farch_filter_update_rx_scatter(struct efx_nic *efx); 673 s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec, 674 bool replace); 675 int efx_farch_filter_remove_safe(struct efx_nic *efx, 676 enum efx_filter_priority priority, 677 u32 filter_id); 678 int efx_farch_filter_get_safe(struct efx_nic *efx, 679 enum efx_filter_priority priority, u32 filter_id, 680 struct efx_filter_spec *); 681 void efx_farch_filter_clear_rx(struct efx_nic *efx, 682 enum efx_filter_priority priority); 683 u32 efx_farch_filter_count_rx_used(struct efx_nic *efx, 684 enum efx_filter_priority priority); 685 u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx); 686 s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx, 687 enum efx_filter_priority priority, u32 *buf, 688 u32 size); 689 #ifdef CONFIG_RFS_ACCEL 690 s32 efx_farch_filter_rfs_insert(struct efx_nic *efx, 691 struct efx_filter_spec *spec); 692 bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, 693 unsigned int index); 694 #endif 695 void efx_farch_filter_sync_rx_mode(struct efx_nic *efx); 696 697 bool efx_nic_event_present(struct efx_channel *channel); 698 699 /* Some statistics are computed as A - B where A and B each increase 700 * linearly with some hardware counter(s) and the counters are read 701 * asynchronously. If the counters contributing to B are always read 702 * after those contributing to A, the computed value may be lower than 703 * the true value by some variable amount, and may decrease between 704 * subsequent computations. 705 * 706 * We should never allow statistics to decrease or to exceed the true 707 * value. Since the computed value will never be greater than the 708 * true value, we can achieve this by only storing the computed value 709 * when it increases. 710 */ 711 static inline void efx_update_diff_stat(u64 *stat, u64 diff) 712 { 713 if ((s64)(diff - *stat) > 0) 714 *stat = diff; 715 } 716 717 /* Interrupts */ 718 int efx_nic_init_interrupt(struct efx_nic *efx); 719 void efx_nic_irq_test_start(struct efx_nic *efx); 720 void efx_nic_fini_interrupt(struct efx_nic *efx); 721 722 /* Falcon/Siena interrupts */ 723 void efx_farch_irq_enable_master(struct efx_nic *efx); 724 void efx_farch_irq_test_generate(struct efx_nic *efx); 725 void efx_farch_irq_disable_master(struct efx_nic *efx); 726 irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id); 727 irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id); 728 irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx); 729 730 static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel) 731 { 732 return ACCESS_ONCE(channel->event_test_cpu); 733 } 734 static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx) 735 { 736 return ACCESS_ONCE(efx->last_irq_cpu); 737 } 738 739 /* Global Resources */ 740 int efx_nic_flush_queues(struct efx_nic *efx); 741 void siena_prepare_flush(struct efx_nic *efx); 742 int efx_farch_fini_dmaq(struct efx_nic *efx); 743 void siena_finish_flush(struct efx_nic *efx); 744 void falcon_start_nic_stats(struct efx_nic *efx); 745 void falcon_stop_nic_stats(struct efx_nic *efx); 746 int falcon_reset_xaui(struct efx_nic *efx); 747 void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw); 748 void efx_farch_init_common(struct efx_nic *efx); 749 void efx_ef10_handle_drain_event(struct efx_nic *efx); 750 static inline void efx_nic_push_rx_indir_table(struct efx_nic *efx) 751 { 752 efx->type->rx_push_indir_table(efx); 753 } 754 void efx_farch_rx_push_indir_table(struct efx_nic *efx); 755 756 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, 757 unsigned int len, gfp_t gfp_flags); 758 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer); 759 760 /* Tests */ 761 struct efx_farch_register_test { 762 unsigned address; 763 efx_oword_t mask; 764 }; 765 int efx_farch_test_registers(struct efx_nic *efx, 766 const struct efx_farch_register_test *regs, 767 size_t n_regs); 768 769 size_t efx_nic_get_regs_len(struct efx_nic *efx); 770 void efx_nic_get_regs(struct efx_nic *efx, void *buf); 771 772 size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count, 773 const unsigned long *mask, u8 *names); 774 void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count, 775 const unsigned long *mask, u64 *stats, 776 const void *dma_buf, bool accumulate); 777 778 #define EFX_MAX_FLUSH_TIME 5000 779 780 void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq, 781 efx_qword_t *event); 782 783 #endif /* EFX_NIC_H */ 784