1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2874aeea5SJeff Kirsher /**************************************************************************** 3f7a6d2c4SBen Hutchings * Driver for Solarflare network controllers and boards 4874aeea5SJeff Kirsher * Copyright 2005-2006 Fen Systems Ltd. 5f7a6d2c4SBen Hutchings * Copyright 2006-2013 Solarflare Communications Inc. 6874aeea5SJeff Kirsher */ 7874aeea5SJeff Kirsher 8874aeea5SJeff Kirsher #ifndef EFX_NIC_H 9874aeea5SJeff Kirsher #define EFX_NIC_H 10874aeea5SJeff Kirsher 119043f48fSEdward Cree #include "nic_common.h" 12874aeea5SJeff Kirsher #include "efx.h" 13874aeea5SJeff Kirsher 14874aeea5SJeff Kirsher enum { 15874aeea5SJeff Kirsher PHY_TYPE_NONE = 0, 16874aeea5SJeff Kirsher PHY_TYPE_TXC43128 = 1, 17874aeea5SJeff Kirsher PHY_TYPE_88E1111 = 2, 18874aeea5SJeff Kirsher PHY_TYPE_SFX7101 = 3, 19874aeea5SJeff Kirsher PHY_TYPE_QT2022C2 = 4, 20874aeea5SJeff Kirsher PHY_TYPE_PM8358 = 6, 21874aeea5SJeff Kirsher PHY_TYPE_SFT9001A = 8, 22874aeea5SJeff Kirsher PHY_TYPE_QT2025C = 9, 23874aeea5SJeff Kirsher PHY_TYPE_SFT9001B = 10, 24874aeea5SJeff Kirsher }; 25874aeea5SJeff Kirsher 26cd0ecc9aSBen Hutchings enum { 27e80ca013SDaniel Pieczko EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT, 28e80ca013SDaniel Pieczko EF10_STAT_port_tx_packets, 29e80ca013SDaniel Pieczko EF10_STAT_port_tx_pause, 30e80ca013SDaniel Pieczko EF10_STAT_port_tx_control, 31e80ca013SDaniel Pieczko EF10_STAT_port_tx_unicast, 32e80ca013SDaniel Pieczko EF10_STAT_port_tx_multicast, 33e80ca013SDaniel Pieczko EF10_STAT_port_tx_broadcast, 34e80ca013SDaniel Pieczko EF10_STAT_port_tx_lt64, 35e80ca013SDaniel Pieczko EF10_STAT_port_tx_64, 36e80ca013SDaniel Pieczko EF10_STAT_port_tx_65_to_127, 37e80ca013SDaniel Pieczko EF10_STAT_port_tx_128_to_255, 38e80ca013SDaniel Pieczko EF10_STAT_port_tx_256_to_511, 39e80ca013SDaniel Pieczko EF10_STAT_port_tx_512_to_1023, 40e80ca013SDaniel Pieczko EF10_STAT_port_tx_1024_to_15xx, 41e80ca013SDaniel Pieczko EF10_STAT_port_tx_15xx_to_jumbo, 42e80ca013SDaniel Pieczko EF10_STAT_port_rx_bytes, 43e80ca013SDaniel Pieczko EF10_STAT_port_rx_bytes_minus_good_bytes, 44e80ca013SDaniel Pieczko EF10_STAT_port_rx_good_bytes, 45e80ca013SDaniel Pieczko EF10_STAT_port_rx_bad_bytes, 46e80ca013SDaniel Pieczko EF10_STAT_port_rx_packets, 47e80ca013SDaniel Pieczko EF10_STAT_port_rx_good, 48e80ca013SDaniel Pieczko EF10_STAT_port_rx_bad, 49e80ca013SDaniel Pieczko EF10_STAT_port_rx_pause, 50e80ca013SDaniel Pieczko EF10_STAT_port_rx_control, 51e80ca013SDaniel Pieczko EF10_STAT_port_rx_unicast, 52e80ca013SDaniel Pieczko EF10_STAT_port_rx_multicast, 53e80ca013SDaniel Pieczko EF10_STAT_port_rx_broadcast, 54e80ca013SDaniel Pieczko EF10_STAT_port_rx_lt64, 55e80ca013SDaniel Pieczko EF10_STAT_port_rx_64, 56e80ca013SDaniel Pieczko EF10_STAT_port_rx_65_to_127, 57e80ca013SDaniel Pieczko EF10_STAT_port_rx_128_to_255, 58e80ca013SDaniel Pieczko EF10_STAT_port_rx_256_to_511, 59e80ca013SDaniel Pieczko EF10_STAT_port_rx_512_to_1023, 60e80ca013SDaniel Pieczko EF10_STAT_port_rx_1024_to_15xx, 61e80ca013SDaniel Pieczko EF10_STAT_port_rx_15xx_to_jumbo, 62e80ca013SDaniel Pieczko EF10_STAT_port_rx_gtjumbo, 63e80ca013SDaniel Pieczko EF10_STAT_port_rx_bad_gtjumbo, 64e80ca013SDaniel Pieczko EF10_STAT_port_rx_overflow, 65e80ca013SDaniel Pieczko EF10_STAT_port_rx_align_error, 66e80ca013SDaniel Pieczko EF10_STAT_port_rx_length_error, 67e80ca013SDaniel Pieczko EF10_STAT_port_rx_nodesc_drops, 68e80ca013SDaniel Pieczko EF10_STAT_port_rx_pm_trunc_bb_overflow, 69e80ca013SDaniel Pieczko EF10_STAT_port_rx_pm_discard_bb_overflow, 70e80ca013SDaniel Pieczko EF10_STAT_port_rx_pm_trunc_vfifo_full, 71e80ca013SDaniel Pieczko EF10_STAT_port_rx_pm_discard_vfifo_full, 72e80ca013SDaniel Pieczko EF10_STAT_port_rx_pm_trunc_qbb, 73e80ca013SDaniel Pieczko EF10_STAT_port_rx_pm_discard_qbb, 74e80ca013SDaniel Pieczko EF10_STAT_port_rx_pm_discard_mapping, 75e80ca013SDaniel Pieczko EF10_STAT_port_rx_dp_q_disabled_packets, 76e80ca013SDaniel Pieczko EF10_STAT_port_rx_dp_di_dropped_packets, 77e80ca013SDaniel Pieczko EF10_STAT_port_rx_dp_streaming_packets, 78e80ca013SDaniel Pieczko EF10_STAT_port_rx_dp_hlb_fetch, 79e80ca013SDaniel Pieczko EF10_STAT_port_rx_dp_hlb_wait, 803c36a2adSDaniel Pieczko EF10_STAT_rx_unicast, 813c36a2adSDaniel Pieczko EF10_STAT_rx_unicast_bytes, 823c36a2adSDaniel Pieczko EF10_STAT_rx_multicast, 833c36a2adSDaniel Pieczko EF10_STAT_rx_multicast_bytes, 843c36a2adSDaniel Pieczko EF10_STAT_rx_broadcast, 853c36a2adSDaniel Pieczko EF10_STAT_rx_broadcast_bytes, 863c36a2adSDaniel Pieczko EF10_STAT_rx_bad, 873c36a2adSDaniel Pieczko EF10_STAT_rx_bad_bytes, 883c36a2adSDaniel Pieczko EF10_STAT_rx_overflow, 893c36a2adSDaniel Pieczko EF10_STAT_tx_unicast, 903c36a2adSDaniel Pieczko EF10_STAT_tx_unicast_bytes, 913c36a2adSDaniel Pieczko EF10_STAT_tx_multicast, 923c36a2adSDaniel Pieczko EF10_STAT_tx_multicast_bytes, 933c36a2adSDaniel Pieczko EF10_STAT_tx_broadcast, 943c36a2adSDaniel Pieczko EF10_STAT_tx_broadcast_bytes, 953c36a2adSDaniel Pieczko EF10_STAT_tx_bad, 963c36a2adSDaniel Pieczko EF10_STAT_tx_bad_bytes, 973c36a2adSDaniel Pieczko EF10_STAT_tx_overflow, 98f411b54dSEdward Cree EF10_STAT_V1_COUNT, 99f411b54dSEdward Cree EF10_STAT_fec_uncorrected_errors = EF10_STAT_V1_COUNT, 100f411b54dSEdward Cree EF10_STAT_fec_corrected_errors, 101f411b54dSEdward Cree EF10_STAT_fec_corrected_symbols_lane0, 102f411b54dSEdward Cree EF10_STAT_fec_corrected_symbols_lane1, 103f411b54dSEdward Cree EF10_STAT_fec_corrected_symbols_lane2, 104f411b54dSEdward Cree EF10_STAT_fec_corrected_symbols_lane3, 1052c0b6ee8SBert Kenward EF10_STAT_ctpio_vi_busy_fallback, 1062c0b6ee8SBert Kenward EF10_STAT_ctpio_long_write_success, 1072c0b6ee8SBert Kenward EF10_STAT_ctpio_missing_dbell_fail, 1082c0b6ee8SBert Kenward EF10_STAT_ctpio_overflow_fail, 1092c0b6ee8SBert Kenward EF10_STAT_ctpio_underflow_fail, 1102c0b6ee8SBert Kenward EF10_STAT_ctpio_timeout_fail, 1112c0b6ee8SBert Kenward EF10_STAT_ctpio_noncontig_wr_fail, 1122c0b6ee8SBert Kenward EF10_STAT_ctpio_frm_clobber_fail, 1132c0b6ee8SBert Kenward EF10_STAT_ctpio_invalid_wr_fail, 1142c0b6ee8SBert Kenward EF10_STAT_ctpio_vi_clobber_fallback, 1152c0b6ee8SBert Kenward EF10_STAT_ctpio_unqualified_fallback, 1162c0b6ee8SBert Kenward EF10_STAT_ctpio_runt_fallback, 1172c0b6ee8SBert Kenward EF10_STAT_ctpio_success, 1182c0b6ee8SBert Kenward EF10_STAT_ctpio_fallback, 1192c0b6ee8SBert Kenward EF10_STAT_ctpio_poison, 1202c0b6ee8SBert Kenward EF10_STAT_ctpio_erase, 1218127d661SBen Hutchings EF10_STAT_COUNT 1228127d661SBen Hutchings }; 1238127d661SBen Hutchings 124183233beSBen Hutchings /* Maximum number of TX PIO buffers we may allocate to a function. 125183233beSBen Hutchings * This matches the total number of buffers on each SFC9100-family 126183233beSBen Hutchings * controller. 127183233beSBen Hutchings */ 128183233beSBen Hutchings #define EF10_TX_PIOBUF_COUNT 16 129183233beSBen Hutchings 1308127d661SBen Hutchings /** 1318127d661SBen Hutchings * struct efx_ef10_nic_data - EF10 architecture NIC state 1328127d661SBen Hutchings * @mcdi_buf: DMA buffer for MCDI 1338127d661SBen Hutchings * @warm_boot_count: Last seen MC warm boot count 1348127d661SBen Hutchings * @vi_base: Absolute index of first VI in this function 1358127d661SBen Hutchings * @n_allocated_vis: Number of VIs allocated to this function 136183233beSBen Hutchings * @n_piobufs: Number of PIO buffers allocated to this function 137183233beSBen Hutchings * @wc_membase: Base address of write-combining mapping of the memory BAR 138183233beSBen Hutchings * @pio_write_base: Base address for writing PIO buffers 139183233beSBen Hutchings * @pio_write_vi_base: Relative VI number for @pio_write_base 140183233beSBen Hutchings * @piobuf_handle: Handle of each PIO buffer allocated 141c634700fSEdward Cree * @piobuf_size: size of a single PIO buffer 142183233beSBen Hutchings * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC 143183233beSBen Hutchings * reboot 144d3142c19SEdward Cree * @mc_stats: Scratch buffer for converting statistics to the kernel's format 1458127d661SBen Hutchings * @stats: Hardware statistics 1468127d661SBen Hutchings * @workaround_35388: Flag: firmware supports workaround for bug 35388 14746e612b0SDaniel Pieczko * @workaround_26807: Flag: firmware supports workaround for bug 26807 148539de7c5SBert Kenward * @workaround_61265: Flag: firmware supports workaround for bug 61265 149a915ccc9SBen Hutchings * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated 150a915ccc9SBen Hutchings * after MC reboot 1518127d661SBen Hutchings * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of 1528127d661SBen Hutchings * %MC_CMD_GET_CAPABILITIES response) 153ca889a05SBert Kenward * @datapath_caps2: Further Capabilities of datapath firmware (FLAGS2 field of 154ca889a05SBert Kenward * %MC_CMD_GET_CAPABILITIES response) 1558d9f9dd4SDaniel Pieczko * @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU 1568d9f9dd4SDaniel Pieczko * @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU 1576d8aaaf6SDaniel Pieczko * @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot 1581cd9ecbbSDaniel Pieczko * @pf_index: The number for this PF, or the parent PF if this is a VF 1593c5eb876SShradha Shah #ifdef CONFIG_SFC_SRIOV 1603c5eb876SShradha Shah * @vf: Pointer to VF data structure 1613c5eb876SShradha Shah #endif 16234813fe2SAndrew Rybchenko * @vport_mac: The MAC address on the vport, only for PFs; VFs will be zero 16334813fe2SAndrew Rybchenko * @vlan_list: List of VLANs added over the interface. Serialised by vlan_lock. 16434813fe2SAndrew Rybchenko * @vlan_lock: Lock to serialize access to vlan_list. 165e5fbd977SJon Cooper * @udp_tunnels: UDP tunnel port numbers and types. 166e5fbd977SJon Cooper * @udp_tunnels_dirty: flag indicating a reboot occurred while pushing 167e5fbd977SJon Cooper * @udp_tunnels to hardware and thus the push must be re-done. 168e5fbd977SJon Cooper * @udp_tunnels_lock: Serialises writes to @udp_tunnels and @udp_tunnels_dirty. 1698127d661SBen Hutchings */ 1708127d661SBen Hutchings struct efx_ef10_nic_data { 1718127d661SBen Hutchings struct efx_buffer mcdi_buf; 1728127d661SBen Hutchings u16 warm_boot_count; 1738127d661SBen Hutchings unsigned int vi_base; 1748127d661SBen Hutchings unsigned int n_allocated_vis; 175183233beSBen Hutchings unsigned int n_piobufs; 176183233beSBen Hutchings void __iomem *wc_membase, *pio_write_base; 177183233beSBen Hutchings unsigned int pio_write_vi_base; 178183233beSBen Hutchings unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT]; 179c634700fSEdward Cree u16 piobuf_size; 180183233beSBen Hutchings bool must_restore_piobufs; 181d3142c19SEdward Cree __le64 *mc_stats; 1828127d661SBen Hutchings u64 stats[EF10_STAT_COUNT]; 1838127d661SBen Hutchings bool workaround_35388; 18446e612b0SDaniel Pieczko bool workaround_26807; 185539de7c5SBert Kenward bool workaround_61265; 186a915ccc9SBen Hutchings bool must_check_datapath_caps; 1878127d661SBen Hutchings u32 datapath_caps; 188ca889a05SBert Kenward u32 datapath_caps2; 1898d9f9dd4SDaniel Pieczko unsigned int rx_dpcpu_fw_id; 1908d9f9dd4SDaniel Pieczko unsigned int tx_dpcpu_fw_id; 1916d8aaaf6SDaniel Pieczko bool must_probe_vswitching; 1921cd9ecbbSDaniel Pieczko unsigned int pf_index; 1931d051e00SShradha Shah u8 port_id[ETH_ALEN]; 1943c5eb876SShradha Shah #ifdef CONFIG_SFC_SRIOV 19588a37de6SShradha Shah unsigned int vf_index; 1963c5eb876SShradha Shah struct ef10_vf *vf; 1973c5eb876SShradha Shah #endif 1983c5eb876SShradha Shah u8 vport_mac[ETH_ALEN]; 19934813fe2SAndrew Rybchenko struct list_head vlan_list; 20034813fe2SAndrew Rybchenko struct mutex vlan_lock; 201e5fbd977SJon Cooper struct efx_udp_tunnel udp_tunnels[16]; 202e5fbd977SJon Cooper bool udp_tunnels_dirty; 203e5fbd977SJon Cooper struct mutex udp_tunnels_lock; 20450663fe1SMartin Habets u64 licensed_features; 2058127d661SBen Hutchings }; 2068127d661SBen Hutchings 2071679c72cSEdward Cree /* TSOv2 */ 2081679c72cSEdward Cree int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb, 2091679c72cSEdward Cree bool *data_mapped); 2101679c72cSEdward Cree 2118127d661SBen Hutchings extern const struct efx_nic_type efx_hunt_a0_nic_type; 21202246a7fSShradha Shah extern const struct efx_nic_type efx_hunt_a0_vf_nic_type; 213874aeea5SJeff Kirsher 214874aeea5SJeff Kirsher #endif /* EFX_NIC_H */ 215