1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2005-2006 Fen Systems Ltd. 5 * Copyright 2006-2013 Solarflare Communications Inc. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/delay.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/module.h> 13 #include <linux/seq_file.h> 14 #include <linux/cpu_rmap.h> 15 #include "net_driver.h" 16 #include "bitfield.h" 17 #include "efx.h" 18 #include "nic.h" 19 #include "ef10_regs.h" 20 #include "farch_regs.h" 21 #include "io.h" 22 #include "workarounds.h" 23 #include "mcdi_port_common.h" 24 #include "mcdi_pcol.h" 25 26 /************************************************************************** 27 * 28 * Generic buffer handling 29 * These buffers are used for interrupt status, MAC stats, etc. 30 * 31 **************************************************************************/ 32 33 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, 34 unsigned int len, gfp_t gfp_flags) 35 { 36 buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len, 37 &buffer->dma_addr, gfp_flags); 38 if (!buffer->addr) 39 return -ENOMEM; 40 buffer->len = len; 41 return 0; 42 } 43 44 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer) 45 { 46 if (buffer->addr) { 47 dma_free_coherent(&efx->pci_dev->dev, buffer->len, 48 buffer->addr, buffer->dma_addr); 49 buffer->addr = NULL; 50 } 51 } 52 53 /* Check whether an event is present in the eventq at the current 54 * read pointer. Only useful for self-test. 55 */ 56 bool efx_nic_event_present(struct efx_channel *channel) 57 { 58 return efx_event_present(efx_event(channel, channel->eventq_read_ptr)); 59 } 60 61 void efx_nic_event_test_start(struct efx_channel *channel) 62 { 63 channel->event_test_cpu = -1; 64 smp_wmb(); 65 channel->efx->type->ev_test_generate(channel); 66 } 67 68 int efx_nic_irq_test_start(struct efx_nic *efx) 69 { 70 efx->last_irq_cpu = -1; 71 smp_wmb(); 72 return efx->type->irq_test_generate(efx); 73 } 74 75 /* Hook interrupt handler(s) 76 * Try MSI and then legacy interrupts. 77 */ 78 int efx_nic_init_interrupt(struct efx_nic *efx) 79 { 80 struct efx_channel *channel; 81 unsigned int n_irqs; 82 int rc; 83 84 if (!EFX_INT_MODE_USE_MSI(efx)) { 85 rc = request_irq(efx->legacy_irq, 86 efx->type->irq_handle_legacy, IRQF_SHARED, 87 efx->name, efx); 88 if (rc) { 89 netif_err(efx, drv, efx->net_dev, 90 "failed to hook legacy IRQ %d\n", 91 efx->pci_dev->irq); 92 goto fail1; 93 } 94 return 0; 95 } 96 97 #ifdef CONFIG_RFS_ACCEL 98 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { 99 efx->net_dev->rx_cpu_rmap = 100 alloc_irq_cpu_rmap(efx->n_rx_channels); 101 if (!efx->net_dev->rx_cpu_rmap) { 102 rc = -ENOMEM; 103 goto fail1; 104 } 105 } 106 #endif 107 108 /* Hook MSI or MSI-X interrupt */ 109 n_irqs = 0; 110 efx_for_each_channel(channel, efx) { 111 rc = request_irq(channel->irq, efx->type->irq_handle_msi, 112 IRQF_PROBE_SHARED, /* Not shared */ 113 efx->msi_context[channel->channel].name, 114 &efx->msi_context[channel->channel]); 115 if (rc) { 116 netif_err(efx, drv, efx->net_dev, 117 "failed to hook IRQ %d\n", channel->irq); 118 goto fail2; 119 } 120 ++n_irqs; 121 122 #ifdef CONFIG_RFS_ACCEL 123 if (efx->interrupt_mode == EFX_INT_MODE_MSIX && 124 channel->channel < efx->n_rx_channels) { 125 rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap, 126 channel->irq); 127 if (rc) 128 goto fail2; 129 } 130 #endif 131 } 132 133 return 0; 134 135 fail2: 136 #ifdef CONFIG_RFS_ACCEL 137 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); 138 efx->net_dev->rx_cpu_rmap = NULL; 139 #endif 140 efx_for_each_channel(channel, efx) { 141 if (n_irqs-- == 0) 142 break; 143 free_irq(channel->irq, &efx->msi_context[channel->channel]); 144 } 145 fail1: 146 return rc; 147 } 148 149 void efx_nic_fini_interrupt(struct efx_nic *efx) 150 { 151 struct efx_channel *channel; 152 153 #ifdef CONFIG_RFS_ACCEL 154 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); 155 efx->net_dev->rx_cpu_rmap = NULL; 156 #endif 157 158 if (EFX_INT_MODE_USE_MSI(efx)) { 159 /* Disable MSI/MSI-X interrupts */ 160 efx_for_each_channel(channel, efx) 161 free_irq(channel->irq, 162 &efx->msi_context[channel->channel]); 163 } else { 164 /* Disable legacy interrupt */ 165 free_irq(efx->legacy_irq, efx); 166 } 167 } 168 169 /* Register dump */ 170 171 #define REGISTER_REVISION_FA 1 172 #define REGISTER_REVISION_FB 2 173 #define REGISTER_REVISION_FC 3 174 #define REGISTER_REVISION_FZ 3 /* last Falcon arch revision */ 175 #define REGISTER_REVISION_ED 4 176 #define REGISTER_REVISION_EZ 4 /* latest EF10 revision */ 177 178 struct efx_nic_reg { 179 u32 offset:24; 180 u32 min_revision:3, max_revision:3; 181 }; 182 183 #define REGISTER(name, arch, min_rev, max_rev) { \ 184 arch ## R_ ## min_rev ## max_rev ## _ ## name, \ 185 REGISTER_REVISION_ ## arch ## min_rev, \ 186 REGISTER_REVISION_ ## arch ## max_rev \ 187 } 188 #define REGISTER_AA(name) REGISTER(name, F, A, A) 189 #define REGISTER_AB(name) REGISTER(name, F, A, B) 190 #define REGISTER_AZ(name) REGISTER(name, F, A, Z) 191 #define REGISTER_BB(name) REGISTER(name, F, B, B) 192 #define REGISTER_BZ(name) REGISTER(name, F, B, Z) 193 #define REGISTER_CZ(name) REGISTER(name, F, C, Z) 194 #define REGISTER_DZ(name) REGISTER(name, E, D, Z) 195 196 static const struct efx_nic_reg efx_nic_regs[] = { 197 REGISTER_AZ(ADR_REGION), 198 REGISTER_AZ(INT_EN_KER), 199 REGISTER_BZ(INT_EN_CHAR), 200 REGISTER_AZ(INT_ADR_KER), 201 REGISTER_BZ(INT_ADR_CHAR), 202 /* INT_ACK_KER is WO */ 203 /* INT_ISR0 is RC */ 204 REGISTER_AZ(HW_INIT), 205 REGISTER_CZ(USR_EV_CFG), 206 REGISTER_AB(EE_SPI_HCMD), 207 REGISTER_AB(EE_SPI_HADR), 208 REGISTER_AB(EE_SPI_HDATA), 209 REGISTER_AB(EE_BASE_PAGE), 210 REGISTER_AB(EE_VPD_CFG0), 211 /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */ 212 /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */ 213 /* PCIE_CORE_INDIRECT is indirect */ 214 REGISTER_AB(NIC_STAT), 215 REGISTER_AB(GPIO_CTL), 216 REGISTER_AB(GLB_CTL), 217 /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */ 218 REGISTER_BZ(DP_CTRL), 219 REGISTER_AZ(MEM_STAT), 220 REGISTER_AZ(CS_DEBUG), 221 REGISTER_AZ(ALTERA_BUILD), 222 REGISTER_AZ(CSR_SPARE), 223 REGISTER_AB(PCIE_SD_CTL0123), 224 REGISTER_AB(PCIE_SD_CTL45), 225 REGISTER_AB(PCIE_PCS_CTL_STAT), 226 /* DEBUG_DATA_OUT is not used */ 227 /* DRV_EV is WO */ 228 REGISTER_AZ(EVQ_CTL), 229 REGISTER_AZ(EVQ_CNT1), 230 REGISTER_AZ(EVQ_CNT2), 231 REGISTER_AZ(BUF_TBL_CFG), 232 REGISTER_AZ(SRM_RX_DC_CFG), 233 REGISTER_AZ(SRM_TX_DC_CFG), 234 REGISTER_AZ(SRM_CFG), 235 /* BUF_TBL_UPD is WO */ 236 REGISTER_AZ(SRM_UPD_EVQ), 237 REGISTER_AZ(SRAM_PARITY), 238 REGISTER_AZ(RX_CFG), 239 REGISTER_BZ(RX_FILTER_CTL), 240 /* RX_FLUSH_DESCQ is WO */ 241 REGISTER_AZ(RX_DC_CFG), 242 REGISTER_AZ(RX_DC_PF_WM), 243 REGISTER_BZ(RX_RSS_TKEY), 244 /* RX_NODESC_DROP is RC */ 245 REGISTER_AA(RX_SELF_RST), 246 /* RX_DEBUG, RX_PUSH_DROP are not used */ 247 REGISTER_CZ(RX_RSS_IPV6_REG1), 248 REGISTER_CZ(RX_RSS_IPV6_REG2), 249 REGISTER_CZ(RX_RSS_IPV6_REG3), 250 /* TX_FLUSH_DESCQ is WO */ 251 REGISTER_AZ(TX_DC_CFG), 252 REGISTER_AA(TX_CHKSM_CFG), 253 REGISTER_AZ(TX_CFG), 254 /* TX_PUSH_DROP is not used */ 255 REGISTER_AZ(TX_RESERVED), 256 REGISTER_BZ(TX_PACE), 257 /* TX_PACE_DROP_QID is RC */ 258 REGISTER_BB(TX_VLAN), 259 REGISTER_BZ(TX_IPFIL_PORTEN), 260 REGISTER_AB(MD_TXD), 261 REGISTER_AB(MD_RXD), 262 REGISTER_AB(MD_CS), 263 REGISTER_AB(MD_PHY_ADR), 264 REGISTER_AB(MD_ID), 265 /* MD_STAT is RC */ 266 REGISTER_AB(MAC_STAT_DMA), 267 REGISTER_AB(MAC_CTRL), 268 REGISTER_BB(GEN_MODE), 269 REGISTER_AB(MAC_MC_HASH_REG0), 270 REGISTER_AB(MAC_MC_HASH_REG1), 271 REGISTER_AB(GM_CFG1), 272 REGISTER_AB(GM_CFG2), 273 /* GM_IPG and GM_HD are not used */ 274 REGISTER_AB(GM_MAX_FLEN), 275 /* GM_TEST is not used */ 276 REGISTER_AB(GM_ADR1), 277 REGISTER_AB(GM_ADR2), 278 REGISTER_AB(GMF_CFG0), 279 REGISTER_AB(GMF_CFG1), 280 REGISTER_AB(GMF_CFG2), 281 REGISTER_AB(GMF_CFG3), 282 REGISTER_AB(GMF_CFG4), 283 REGISTER_AB(GMF_CFG5), 284 REGISTER_BB(TX_SRC_MAC_CTL), 285 REGISTER_AB(XM_ADR_LO), 286 REGISTER_AB(XM_ADR_HI), 287 REGISTER_AB(XM_GLB_CFG), 288 REGISTER_AB(XM_TX_CFG), 289 REGISTER_AB(XM_RX_CFG), 290 REGISTER_AB(XM_MGT_INT_MASK), 291 REGISTER_AB(XM_FC), 292 REGISTER_AB(XM_PAUSE_TIME), 293 REGISTER_AB(XM_TX_PARAM), 294 REGISTER_AB(XM_RX_PARAM), 295 /* XM_MGT_INT_MSK (note no 'A') is RC */ 296 REGISTER_AB(XX_PWR_RST), 297 REGISTER_AB(XX_SD_CTL), 298 REGISTER_AB(XX_TXDRV_CTL), 299 /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */ 300 /* XX_CORE_STAT is partly RC */ 301 REGISTER_DZ(BIU_HW_REV_ID), 302 REGISTER_DZ(MC_DB_LWRD), 303 REGISTER_DZ(MC_DB_HWRD), 304 }; 305 306 struct efx_nic_reg_table { 307 u32 offset:24; 308 u32 min_revision:3, max_revision:3; 309 u32 step:6, rows:21; 310 }; 311 312 #define REGISTER_TABLE_DIMENSIONS(_, offset, arch, min_rev, max_rev, step, rows) { \ 313 offset, \ 314 REGISTER_REVISION_ ## arch ## min_rev, \ 315 REGISTER_REVISION_ ## arch ## max_rev, \ 316 step, rows \ 317 } 318 #define REGISTER_TABLE(name, arch, min_rev, max_rev) \ 319 REGISTER_TABLE_DIMENSIONS( \ 320 name, arch ## R_ ## min_rev ## max_rev ## _ ## name, \ 321 arch, min_rev, max_rev, \ 322 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _STEP, \ 323 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _ROWS) 324 #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, F, A, A) 325 #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, F, A, Z) 326 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, F, B, B) 327 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, F, B, Z) 328 #define REGISTER_TABLE_BB_CZ(name) \ 329 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, B, B, \ 330 FR_BZ_ ## name ## _STEP, \ 331 FR_BB_ ## name ## _ROWS), \ 332 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, C, Z, \ 333 FR_BZ_ ## name ## _STEP, \ 334 FR_CZ_ ## name ## _ROWS) 335 #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, F, C, Z) 336 #define REGISTER_TABLE_DZ(name) REGISTER_TABLE(name, E, D, Z) 337 338 static const struct efx_nic_reg_table efx_nic_reg_tables[] = { 339 /* DRIVER is not used */ 340 /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */ 341 REGISTER_TABLE_BB(TX_IPFIL_TBL), 342 REGISTER_TABLE_BB(TX_SRC_MAC_TBL), 343 REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER), 344 REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL), 345 REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER), 346 REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL), 347 REGISTER_TABLE_AA(EVQ_PTR_TBL_KER), 348 REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL), 349 /* We can't reasonably read all of the buffer table (up to 8MB!). 350 * However this driver will only use a few entries. Reading 351 * 1K entries allows for some expansion of queue count and 352 * size before we need to change the version. */ 353 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER, 354 F, A, A, 8, 1024), 355 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL, 356 F, B, Z, 8, 1024), 357 REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0), 358 REGISTER_TABLE_BB_CZ(TIMER_TBL), 359 REGISTER_TABLE_BB_CZ(TX_PACE_TBL), 360 REGISTER_TABLE_BZ(RX_INDIRECTION_TBL), 361 /* TX_FILTER_TBL0 is huge and not used by this driver */ 362 REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0), 363 REGISTER_TABLE_CZ(MC_TREG_SMEM), 364 /* MSIX_PBA_TABLE is not mapped */ 365 /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */ 366 REGISTER_TABLE_BZ(RX_FILTER_TBL0), 367 REGISTER_TABLE_DZ(BIU_MC_SFT_STATUS), 368 }; 369 370 size_t efx_nic_get_regs_len(struct efx_nic *efx) 371 { 372 const struct efx_nic_reg *reg; 373 const struct efx_nic_reg_table *table; 374 size_t len = 0; 375 376 for (reg = efx_nic_regs; 377 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs); 378 reg++) 379 if (efx->type->revision >= reg->min_revision && 380 efx->type->revision <= reg->max_revision) 381 len += sizeof(efx_oword_t); 382 383 for (table = efx_nic_reg_tables; 384 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables); 385 table++) 386 if (efx->type->revision >= table->min_revision && 387 efx->type->revision <= table->max_revision) 388 len += table->rows * min_t(size_t, table->step, 16); 389 390 return len; 391 } 392 393 void efx_nic_get_regs(struct efx_nic *efx, void *buf) 394 { 395 const struct efx_nic_reg *reg; 396 const struct efx_nic_reg_table *table; 397 398 for (reg = efx_nic_regs; 399 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs); 400 reg++) { 401 if (efx->type->revision >= reg->min_revision && 402 efx->type->revision <= reg->max_revision) { 403 efx_reado(efx, (efx_oword_t *)buf, reg->offset); 404 buf += sizeof(efx_oword_t); 405 } 406 } 407 408 for (table = efx_nic_reg_tables; 409 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables); 410 table++) { 411 size_t size, i; 412 413 if (!(efx->type->revision >= table->min_revision && 414 efx->type->revision <= table->max_revision)) 415 continue; 416 417 size = min_t(size_t, table->step, 16); 418 419 for (i = 0; i < table->rows; i++) { 420 switch (table->step) { 421 case 4: /* 32-bit SRAM */ 422 efx_readd(efx, buf, table->offset + 4 * i); 423 break; 424 case 8: /* 64-bit SRAM */ 425 efx_sram_readq(efx, 426 efx->membase + table->offset, 427 buf, i); 428 break; 429 case 16: /* 128-bit-readable register */ 430 efx_reado_table(efx, buf, table->offset, i); 431 break; 432 case 32: /* 128-bit register, interleaved */ 433 efx_reado_table(efx, buf, table->offset, 2 * i); 434 break; 435 default: 436 WARN_ON(1); 437 return; 438 } 439 buf += size; 440 } 441 } 442 } 443 444 /** 445 * efx_nic_describe_stats - Describe supported statistics for ethtool 446 * @desc: Array of &struct efx_hw_stat_desc describing the statistics 447 * @count: Length of the @desc array 448 * @mask: Bitmask of which elements of @desc are enabled 449 * @names: Buffer to copy names to, or %NULL. The names are copied 450 * starting at intervals of %ETH_GSTRING_LEN bytes. 451 * 452 * Returns the number of visible statistics, i.e. the number of set 453 * bits in the first @count bits of @mask for which a name is defined. 454 */ 455 size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count, 456 const unsigned long *mask, u8 *names) 457 { 458 size_t visible = 0; 459 size_t index; 460 461 for_each_set_bit(index, mask, count) { 462 if (desc[index].name) { 463 if (names) { 464 strlcpy(names, desc[index].name, 465 ETH_GSTRING_LEN); 466 names += ETH_GSTRING_LEN; 467 } 468 ++visible; 469 } 470 } 471 472 return visible; 473 } 474 475 /** 476 * efx_nic_copy_stats - Copy stats from the DMA buffer in to an 477 * intermediate buffer. This is used to get a consistent 478 * set of stats while the DMA buffer can be written at any time 479 * by the NIC. 480 * @efx: The associated NIC. 481 * @dest: Destination buffer. Must be the same size as the DMA buffer. 482 */ 483 int efx_nic_copy_stats(struct efx_nic *efx, __le64 *dest) 484 { 485 __le64 *dma_stats = efx->stats_buffer.addr; 486 __le64 generation_start, generation_end; 487 int rc = 0, retry; 488 489 if (!dest) 490 return 0; 491 492 if (!dma_stats) 493 goto return_zeroes; 494 495 /* If we're unlucky enough to read statistics during the DMA, wait 496 * up to 10ms for it to finish (typically takes <500us) 497 */ 498 for (retry = 0; retry < 100; ++retry) { 499 generation_end = dma_stats[efx->num_mac_stats - 1]; 500 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) 501 goto return_zeroes; 502 rmb(); 503 memcpy(dest, dma_stats, efx->num_mac_stats * sizeof(__le64)); 504 rmb(); 505 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 506 if (generation_end == generation_start) 507 return 0; /* return good data */ 508 udelay(100); 509 } 510 511 rc = -EIO; 512 513 return_zeroes: 514 memset(dest, 0, efx->num_mac_stats * sizeof(u64)); 515 return rc; 516 } 517 518 /** 519 * efx_nic_update_stats - Convert statistics DMA buffer to array of u64 520 * @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer 521 * layout. DMA widths of 0, 16, 32 and 64 are supported; where 522 * the width is specified as 0 the corresponding element of 523 * @stats is not updated. 524 * @count: Length of the @desc array 525 * @mask: Bitmask of which elements of @desc are enabled 526 * @stats: Buffer to update with the converted statistics. The length 527 * of this array must be at least @count. 528 * @dma_buf: DMA buffer containing hardware statistics 529 * @accumulate: If set, the converted values will be added rather than 530 * directly stored to the corresponding elements of @stats 531 */ 532 void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count, 533 const unsigned long *mask, 534 u64 *stats, const void *dma_buf, bool accumulate) 535 { 536 size_t index; 537 538 for_each_set_bit(index, mask, count) { 539 if (desc[index].dma_width) { 540 const void *addr = dma_buf + desc[index].offset; 541 u64 val; 542 543 switch (desc[index].dma_width) { 544 case 16: 545 val = le16_to_cpup((__le16 *)addr); 546 break; 547 case 32: 548 val = le32_to_cpup((__le32 *)addr); 549 break; 550 case 64: 551 val = le64_to_cpup((__le64 *)addr); 552 break; 553 default: 554 WARN_ON(1); 555 val = 0; 556 break; 557 } 558 559 if (accumulate) 560 stats[index] += val; 561 else 562 stats[index] = val; 563 } 564 } 565 } 566 567 void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *rx_nodesc_drops) 568 { 569 /* if down, or this is the first update after coming up */ 570 if (!(efx->net_dev->flags & IFF_UP) || !efx->rx_nodesc_drops_prev_state) 571 efx->rx_nodesc_drops_while_down += 572 *rx_nodesc_drops - efx->rx_nodesc_drops_total; 573 efx->rx_nodesc_drops_total = *rx_nodesc_drops; 574 efx->rx_nodesc_drops_prev_state = !!(efx->net_dev->flags & IFF_UP); 575 *rx_nodesc_drops -= efx->rx_nodesc_drops_while_down; 576 } 577