1 /**************************************************************************** 2 * Driver for Solarflare Solarstorm network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2006-2011 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/delay.h> 13 #include <linux/interrupt.h> 14 #include <linux/pci.h> 15 #include <linux/module.h> 16 #include <linux/seq_file.h> 17 #include <linux/cpu_rmap.h> 18 #include "net_driver.h" 19 #include "bitfield.h" 20 #include "efx.h" 21 #include "nic.h" 22 #include "farch_regs.h" 23 #include "io.h" 24 #include "workarounds.h" 25 26 /************************************************************************** 27 * 28 * Generic buffer handling 29 * These buffers are used for interrupt status, MAC stats, etc. 30 * 31 **************************************************************************/ 32 33 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, 34 unsigned int len, gfp_t gfp_flags) 35 { 36 buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len, 37 &buffer->dma_addr, 38 gfp_flags | __GFP_ZERO); 39 if (!buffer->addr) 40 return -ENOMEM; 41 buffer->len = len; 42 return 0; 43 } 44 45 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer) 46 { 47 if (buffer->addr) { 48 dma_free_coherent(&efx->pci_dev->dev, buffer->len, 49 buffer->addr, buffer->dma_addr); 50 buffer->addr = NULL; 51 } 52 } 53 54 /* Check whether an event is present in the eventq at the current 55 * read pointer. Only useful for self-test. 56 */ 57 bool efx_nic_event_present(struct efx_channel *channel) 58 { 59 return efx_event_present(efx_event(channel, channel->eventq_read_ptr)); 60 } 61 62 void efx_nic_event_test_start(struct efx_channel *channel) 63 { 64 channel->event_test_cpu = -1; 65 smp_wmb(); 66 channel->efx->type->ev_test_generate(channel); 67 } 68 69 void efx_nic_irq_test_start(struct efx_nic *efx) 70 { 71 efx->last_irq_cpu = -1; 72 smp_wmb(); 73 efx->type->irq_test_generate(efx); 74 } 75 76 /* Hook interrupt handler(s) 77 * Try MSI and then legacy interrupts. 78 */ 79 int efx_nic_init_interrupt(struct efx_nic *efx) 80 { 81 struct efx_channel *channel; 82 unsigned int n_irqs; 83 int rc; 84 85 if (!EFX_INT_MODE_USE_MSI(efx)) { 86 rc = request_irq(efx->legacy_irq, 87 efx->type->irq_handle_legacy, IRQF_SHARED, 88 efx->name, efx); 89 if (rc) { 90 netif_err(efx, drv, efx->net_dev, 91 "failed to hook legacy IRQ %d\n", 92 efx->pci_dev->irq); 93 goto fail1; 94 } 95 return 0; 96 } 97 98 #ifdef CONFIG_RFS_ACCEL 99 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { 100 efx->net_dev->rx_cpu_rmap = 101 alloc_irq_cpu_rmap(efx->n_rx_channels); 102 if (!efx->net_dev->rx_cpu_rmap) { 103 rc = -ENOMEM; 104 goto fail1; 105 } 106 } 107 #endif 108 109 /* Hook MSI or MSI-X interrupt */ 110 n_irqs = 0; 111 efx_for_each_channel(channel, efx) { 112 rc = request_irq(channel->irq, efx->type->irq_handle_msi, 113 IRQF_PROBE_SHARED, /* Not shared */ 114 efx->msi_context[channel->channel].name, 115 &efx->msi_context[channel->channel]); 116 if (rc) { 117 netif_err(efx, drv, efx->net_dev, 118 "failed to hook IRQ %d\n", channel->irq); 119 goto fail2; 120 } 121 ++n_irqs; 122 123 #ifdef CONFIG_RFS_ACCEL 124 if (efx->interrupt_mode == EFX_INT_MODE_MSIX && 125 channel->channel < efx->n_rx_channels) { 126 rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap, 127 channel->irq); 128 if (rc) 129 goto fail2; 130 } 131 #endif 132 } 133 134 return 0; 135 136 fail2: 137 #ifdef CONFIG_RFS_ACCEL 138 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); 139 efx->net_dev->rx_cpu_rmap = NULL; 140 #endif 141 efx_for_each_channel(channel, efx) { 142 if (n_irqs-- == 0) 143 break; 144 free_irq(channel->irq, &efx->msi_context[channel->channel]); 145 } 146 fail1: 147 return rc; 148 } 149 150 void efx_nic_fini_interrupt(struct efx_nic *efx) 151 { 152 struct efx_channel *channel; 153 154 #ifdef CONFIG_RFS_ACCEL 155 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); 156 efx->net_dev->rx_cpu_rmap = NULL; 157 #endif 158 159 /* Disable MSI/MSI-X interrupts */ 160 efx_for_each_channel(channel, efx) 161 free_irq(channel->irq, &efx->msi_context[channel->channel]); 162 163 /* Disable legacy interrupt */ 164 if (efx->legacy_irq) 165 free_irq(efx->legacy_irq, efx); 166 } 167 168 /* Register dump */ 169 170 #define REGISTER_REVISION_A 1 171 #define REGISTER_REVISION_B 2 172 #define REGISTER_REVISION_C 3 173 #define REGISTER_REVISION_Z 3 /* latest revision */ 174 175 struct efx_nic_reg { 176 u32 offset:24; 177 u32 min_revision:2, max_revision:2; 178 }; 179 180 #define REGISTER(name, min_rev, max_rev) { \ 181 FR_ ## min_rev ## max_rev ## _ ## name, \ 182 REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev \ 183 } 184 #define REGISTER_AA(name) REGISTER(name, A, A) 185 #define REGISTER_AB(name) REGISTER(name, A, B) 186 #define REGISTER_AZ(name) REGISTER(name, A, Z) 187 #define REGISTER_BB(name) REGISTER(name, B, B) 188 #define REGISTER_BZ(name) REGISTER(name, B, Z) 189 #define REGISTER_CZ(name) REGISTER(name, C, Z) 190 191 static const struct efx_nic_reg efx_nic_regs[] = { 192 REGISTER_AZ(ADR_REGION), 193 REGISTER_AZ(INT_EN_KER), 194 REGISTER_BZ(INT_EN_CHAR), 195 REGISTER_AZ(INT_ADR_KER), 196 REGISTER_BZ(INT_ADR_CHAR), 197 /* INT_ACK_KER is WO */ 198 /* INT_ISR0 is RC */ 199 REGISTER_AZ(HW_INIT), 200 REGISTER_CZ(USR_EV_CFG), 201 REGISTER_AB(EE_SPI_HCMD), 202 REGISTER_AB(EE_SPI_HADR), 203 REGISTER_AB(EE_SPI_HDATA), 204 REGISTER_AB(EE_BASE_PAGE), 205 REGISTER_AB(EE_VPD_CFG0), 206 /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */ 207 /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */ 208 /* PCIE_CORE_INDIRECT is indirect */ 209 REGISTER_AB(NIC_STAT), 210 REGISTER_AB(GPIO_CTL), 211 REGISTER_AB(GLB_CTL), 212 /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */ 213 REGISTER_BZ(DP_CTRL), 214 REGISTER_AZ(MEM_STAT), 215 REGISTER_AZ(CS_DEBUG), 216 REGISTER_AZ(ALTERA_BUILD), 217 REGISTER_AZ(CSR_SPARE), 218 REGISTER_AB(PCIE_SD_CTL0123), 219 REGISTER_AB(PCIE_SD_CTL45), 220 REGISTER_AB(PCIE_PCS_CTL_STAT), 221 /* DEBUG_DATA_OUT is not used */ 222 /* DRV_EV is WO */ 223 REGISTER_AZ(EVQ_CTL), 224 REGISTER_AZ(EVQ_CNT1), 225 REGISTER_AZ(EVQ_CNT2), 226 REGISTER_AZ(BUF_TBL_CFG), 227 REGISTER_AZ(SRM_RX_DC_CFG), 228 REGISTER_AZ(SRM_TX_DC_CFG), 229 REGISTER_AZ(SRM_CFG), 230 /* BUF_TBL_UPD is WO */ 231 REGISTER_AZ(SRM_UPD_EVQ), 232 REGISTER_AZ(SRAM_PARITY), 233 REGISTER_AZ(RX_CFG), 234 REGISTER_BZ(RX_FILTER_CTL), 235 /* RX_FLUSH_DESCQ is WO */ 236 REGISTER_AZ(RX_DC_CFG), 237 REGISTER_AZ(RX_DC_PF_WM), 238 REGISTER_BZ(RX_RSS_TKEY), 239 /* RX_NODESC_DROP is RC */ 240 REGISTER_AA(RX_SELF_RST), 241 /* RX_DEBUG, RX_PUSH_DROP are not used */ 242 REGISTER_CZ(RX_RSS_IPV6_REG1), 243 REGISTER_CZ(RX_RSS_IPV6_REG2), 244 REGISTER_CZ(RX_RSS_IPV6_REG3), 245 /* TX_FLUSH_DESCQ is WO */ 246 REGISTER_AZ(TX_DC_CFG), 247 REGISTER_AA(TX_CHKSM_CFG), 248 REGISTER_AZ(TX_CFG), 249 /* TX_PUSH_DROP is not used */ 250 REGISTER_AZ(TX_RESERVED), 251 REGISTER_BZ(TX_PACE), 252 /* TX_PACE_DROP_QID is RC */ 253 REGISTER_BB(TX_VLAN), 254 REGISTER_BZ(TX_IPFIL_PORTEN), 255 REGISTER_AB(MD_TXD), 256 REGISTER_AB(MD_RXD), 257 REGISTER_AB(MD_CS), 258 REGISTER_AB(MD_PHY_ADR), 259 REGISTER_AB(MD_ID), 260 /* MD_STAT is RC */ 261 REGISTER_AB(MAC_STAT_DMA), 262 REGISTER_AB(MAC_CTRL), 263 REGISTER_BB(GEN_MODE), 264 REGISTER_AB(MAC_MC_HASH_REG0), 265 REGISTER_AB(MAC_MC_HASH_REG1), 266 REGISTER_AB(GM_CFG1), 267 REGISTER_AB(GM_CFG2), 268 /* GM_IPG and GM_HD are not used */ 269 REGISTER_AB(GM_MAX_FLEN), 270 /* GM_TEST is not used */ 271 REGISTER_AB(GM_ADR1), 272 REGISTER_AB(GM_ADR2), 273 REGISTER_AB(GMF_CFG0), 274 REGISTER_AB(GMF_CFG1), 275 REGISTER_AB(GMF_CFG2), 276 REGISTER_AB(GMF_CFG3), 277 REGISTER_AB(GMF_CFG4), 278 REGISTER_AB(GMF_CFG5), 279 REGISTER_BB(TX_SRC_MAC_CTL), 280 REGISTER_AB(XM_ADR_LO), 281 REGISTER_AB(XM_ADR_HI), 282 REGISTER_AB(XM_GLB_CFG), 283 REGISTER_AB(XM_TX_CFG), 284 REGISTER_AB(XM_RX_CFG), 285 REGISTER_AB(XM_MGT_INT_MASK), 286 REGISTER_AB(XM_FC), 287 REGISTER_AB(XM_PAUSE_TIME), 288 REGISTER_AB(XM_TX_PARAM), 289 REGISTER_AB(XM_RX_PARAM), 290 /* XM_MGT_INT_MSK (note no 'A') is RC */ 291 REGISTER_AB(XX_PWR_RST), 292 REGISTER_AB(XX_SD_CTL), 293 REGISTER_AB(XX_TXDRV_CTL), 294 /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */ 295 /* XX_CORE_STAT is partly RC */ 296 }; 297 298 struct efx_nic_reg_table { 299 u32 offset:24; 300 u32 min_revision:2, max_revision:2; 301 u32 step:6, rows:21; 302 }; 303 304 #define REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) { \ 305 offset, \ 306 REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev, \ 307 step, rows \ 308 } 309 #define REGISTER_TABLE(name, min_rev, max_rev) \ 310 REGISTER_TABLE_DIMENSIONS( \ 311 name, FR_ ## min_rev ## max_rev ## _ ## name, \ 312 min_rev, max_rev, \ 313 FR_ ## min_rev ## max_rev ## _ ## name ## _STEP, \ 314 FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS) 315 #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A) 316 #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z) 317 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B) 318 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z) 319 #define REGISTER_TABLE_BB_CZ(name) \ 320 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B, \ 321 FR_BZ_ ## name ## _STEP, \ 322 FR_BB_ ## name ## _ROWS), \ 323 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z, \ 324 FR_BZ_ ## name ## _STEP, \ 325 FR_CZ_ ## name ## _ROWS) 326 #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z) 327 328 static const struct efx_nic_reg_table efx_nic_reg_tables[] = { 329 /* DRIVER is not used */ 330 /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */ 331 REGISTER_TABLE_BB(TX_IPFIL_TBL), 332 REGISTER_TABLE_BB(TX_SRC_MAC_TBL), 333 REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER), 334 REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL), 335 REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER), 336 REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL), 337 REGISTER_TABLE_AA(EVQ_PTR_TBL_KER), 338 REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL), 339 /* We can't reasonably read all of the buffer table (up to 8MB!). 340 * However this driver will only use a few entries. Reading 341 * 1K entries allows for some expansion of queue count and 342 * size before we need to change the version. */ 343 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER, 344 A, A, 8, 1024), 345 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL, 346 B, Z, 8, 1024), 347 REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0), 348 REGISTER_TABLE_BB_CZ(TIMER_TBL), 349 REGISTER_TABLE_BB_CZ(TX_PACE_TBL), 350 REGISTER_TABLE_BZ(RX_INDIRECTION_TBL), 351 /* TX_FILTER_TBL0 is huge and not used by this driver */ 352 REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0), 353 REGISTER_TABLE_CZ(MC_TREG_SMEM), 354 /* MSIX_PBA_TABLE is not mapped */ 355 /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */ 356 REGISTER_TABLE_BZ(RX_FILTER_TBL0), 357 }; 358 359 size_t efx_nic_get_regs_len(struct efx_nic *efx) 360 { 361 const struct efx_nic_reg *reg; 362 const struct efx_nic_reg_table *table; 363 size_t len = 0; 364 365 for (reg = efx_nic_regs; 366 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs); 367 reg++) 368 if (efx->type->revision >= reg->min_revision && 369 efx->type->revision <= reg->max_revision) 370 len += sizeof(efx_oword_t); 371 372 for (table = efx_nic_reg_tables; 373 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables); 374 table++) 375 if (efx->type->revision >= table->min_revision && 376 efx->type->revision <= table->max_revision) 377 len += table->rows * min_t(size_t, table->step, 16); 378 379 return len; 380 } 381 382 void efx_nic_get_regs(struct efx_nic *efx, void *buf) 383 { 384 const struct efx_nic_reg *reg; 385 const struct efx_nic_reg_table *table; 386 387 for (reg = efx_nic_regs; 388 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs); 389 reg++) { 390 if (efx->type->revision >= reg->min_revision && 391 efx->type->revision <= reg->max_revision) { 392 efx_reado(efx, (efx_oword_t *)buf, reg->offset); 393 buf += sizeof(efx_oword_t); 394 } 395 } 396 397 for (table = efx_nic_reg_tables; 398 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables); 399 table++) { 400 size_t size, i; 401 402 if (!(efx->type->revision >= table->min_revision && 403 efx->type->revision <= table->max_revision)) 404 continue; 405 406 size = min_t(size_t, table->step, 16); 407 408 for (i = 0; i < table->rows; i++) { 409 switch (table->step) { 410 case 4: /* 32-bit SRAM */ 411 efx_readd(efx, buf, table->offset + 4 * i); 412 break; 413 case 8: /* 64-bit SRAM */ 414 efx_sram_readq(efx, 415 efx->membase + table->offset, 416 buf, i); 417 break; 418 case 16: /* 128-bit-readable register */ 419 efx_reado_table(efx, buf, table->offset, i); 420 break; 421 case 32: /* 128-bit register, interleaved */ 422 efx_reado_table(efx, buf, table->offset, 2 * i); 423 break; 424 default: 425 WARN_ON(1); 426 return; 427 } 428 buf += size; 429 } 430 } 431 } 432 433 /** 434 * efx_nic_describe_stats - Describe supported statistics for ethtool 435 * @desc: Array of &struct efx_hw_stat_desc describing the statistics 436 * @count: Length of the @desc array 437 * @mask: Bitmask of which elements of @desc are enabled 438 * @names: Buffer to copy names to, or %NULL. The names are copied 439 * starting at intervals of %ETH_GSTRING_LEN bytes. 440 * 441 * Returns the number of visible statistics, i.e. the number of set 442 * bits in the first @count bits of @mask for which a name is defined. 443 */ 444 size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count, 445 const unsigned long *mask, u8 *names) 446 { 447 size_t visible = 0; 448 size_t index; 449 450 for_each_set_bit(index, mask, count) { 451 if (desc[index].name) { 452 if (names) { 453 strlcpy(names, desc[index].name, 454 ETH_GSTRING_LEN); 455 names += ETH_GSTRING_LEN; 456 } 457 ++visible; 458 } 459 } 460 461 return visible; 462 } 463 464 /** 465 * efx_nic_update_stats - Convert statistics DMA buffer to array of u64 466 * @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer 467 * layout. DMA widths of 0, 16, 32 and 64 are supported; where 468 * the width is specified as 0 the corresponding element of 469 * @stats is not updated. 470 * @count: Length of the @desc array 471 * @mask: Bitmask of which elements of @desc are enabled 472 * @stats: Buffer to update with the converted statistics. The length 473 * of this array must be at least the number of set bits in the 474 * first @count bits of @mask. 475 * @dma_buf: DMA buffer containing hardware statistics 476 * @accumulate: If set, the converted values will be added rather than 477 * directly stored to the corresponding elements of @stats 478 */ 479 void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count, 480 const unsigned long *mask, 481 u64 *stats, const void *dma_buf, bool accumulate) 482 { 483 size_t index; 484 485 for_each_set_bit(index, mask, count) { 486 if (desc[index].dma_width) { 487 const void *addr = dma_buf + desc[index].offset; 488 u64 val; 489 490 switch (desc[index].dma_width) { 491 case 16: 492 val = le16_to_cpup((__le16 *)addr); 493 break; 494 case 32: 495 val = le32_to_cpup((__le32 *)addr); 496 break; 497 case 64: 498 val = le64_to_cpup((__le64 *)addr); 499 break; 500 default: 501 WARN_ON(1); 502 val = 0; 503 break; 504 } 505 506 if (accumulate) 507 *stats += val; 508 else 509 *stats = val; 510 } 511 512 ++stats; 513 } 514 } 515