1 /**************************************************************************** 2 * Driver for Solarflare Solarstorm network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2006-2011 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/delay.h> 13 #include <linux/interrupt.h> 14 #include <linux/pci.h> 15 #include <linux/module.h> 16 #include <linux/seq_file.h> 17 #include "net_driver.h" 18 #include "bitfield.h" 19 #include "efx.h" 20 #include "nic.h" 21 #include "regs.h" 22 #include "io.h" 23 #include "workarounds.h" 24 25 /************************************************************************** 26 * 27 * Configurable values 28 * 29 ************************************************************************** 30 */ 31 32 /* This is set to 16 for a good reason. In summary, if larger than 33 * 16, the descriptor cache holds more than a default socket 34 * buffer's worth of packets (for UDP we can only have at most one 35 * socket buffer's worth outstanding). This combined with the fact 36 * that we only get 1 TX event per descriptor cache means the NIC 37 * goes idle. 38 */ 39 #define TX_DC_ENTRIES 16 40 #define TX_DC_ENTRIES_ORDER 1 41 42 #define RX_DC_ENTRIES 64 43 #define RX_DC_ENTRIES_ORDER 3 44 45 /* If EFX_MAX_INT_ERRORS internal errors occur within 46 * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and 47 * disable it. 48 */ 49 #define EFX_INT_ERROR_EXPIRE 3600 50 #define EFX_MAX_INT_ERRORS 5 51 52 /* Depth of RX flush request fifo */ 53 #define EFX_RX_FLUSH_COUNT 4 54 55 /* Driver generated events */ 56 #define _EFX_CHANNEL_MAGIC_TEST 0x000101 57 #define _EFX_CHANNEL_MAGIC_FILL 0x000102 58 #define _EFX_CHANNEL_MAGIC_RX_DRAIN 0x000103 59 #define _EFX_CHANNEL_MAGIC_TX_DRAIN 0x000104 60 61 #define _EFX_CHANNEL_MAGIC(_code, _data) ((_code) << 8 | (_data)) 62 #define _EFX_CHANNEL_MAGIC_CODE(_magic) ((_magic) >> 8) 63 64 #define EFX_CHANNEL_MAGIC_TEST(_channel) \ 65 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TEST, (_channel)->channel) 66 #define EFX_CHANNEL_MAGIC_FILL(_rx_queue) \ 67 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_FILL, \ 68 efx_rx_queue_index(_rx_queue)) 69 #define EFX_CHANNEL_MAGIC_RX_DRAIN(_rx_queue) \ 70 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_RX_DRAIN, \ 71 efx_rx_queue_index(_rx_queue)) 72 #define EFX_CHANNEL_MAGIC_TX_DRAIN(_tx_queue) \ 73 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TX_DRAIN, \ 74 (_tx_queue)->queue) 75 76 /************************************************************************** 77 * 78 * Solarstorm hardware access 79 * 80 **************************************************************************/ 81 82 static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value, 83 unsigned int index) 84 { 85 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base, 86 value, index); 87 } 88 89 /* Read the current event from the event queue */ 90 static inline efx_qword_t *efx_event(struct efx_channel *channel, 91 unsigned int index) 92 { 93 return ((efx_qword_t *) (channel->eventq.addr)) + 94 (index & channel->eventq_mask); 95 } 96 97 /* See if an event is present 98 * 99 * We check both the high and low dword of the event for all ones. We 100 * wrote all ones when we cleared the event, and no valid event can 101 * have all ones in either its high or low dwords. This approach is 102 * robust against reordering. 103 * 104 * Note that using a single 64-bit comparison is incorrect; even 105 * though the CPU read will be atomic, the DMA write may not be. 106 */ 107 static inline int efx_event_present(efx_qword_t *event) 108 { 109 return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | 110 EFX_DWORD_IS_ALL_ONES(event->dword[1])); 111 } 112 113 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b, 114 const efx_oword_t *mask) 115 { 116 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) || 117 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]); 118 } 119 120 int efx_nic_test_registers(struct efx_nic *efx, 121 const struct efx_nic_register_test *regs, 122 size_t n_regs) 123 { 124 unsigned address = 0, i, j; 125 efx_oword_t mask, imask, original, reg, buf; 126 127 for (i = 0; i < n_regs; ++i) { 128 address = regs[i].address; 129 mask = imask = regs[i].mask; 130 EFX_INVERT_OWORD(imask); 131 132 efx_reado(efx, &original, address); 133 134 /* bit sweep on and off */ 135 for (j = 0; j < 128; j++) { 136 if (!EFX_EXTRACT_OWORD32(mask, j, j)) 137 continue; 138 139 /* Test this testable bit can be set in isolation */ 140 EFX_AND_OWORD(reg, original, mask); 141 EFX_SET_OWORD32(reg, j, j, 1); 142 143 efx_writeo(efx, ®, address); 144 efx_reado(efx, &buf, address); 145 146 if (efx_masked_compare_oword(®, &buf, &mask)) 147 goto fail; 148 149 /* Test this testable bit can be cleared in isolation */ 150 EFX_OR_OWORD(reg, original, mask); 151 EFX_SET_OWORD32(reg, j, j, 0); 152 153 efx_writeo(efx, ®, address); 154 efx_reado(efx, &buf, address); 155 156 if (efx_masked_compare_oword(®, &buf, &mask)) 157 goto fail; 158 } 159 160 efx_writeo(efx, &original, address); 161 } 162 163 return 0; 164 165 fail: 166 netif_err(efx, hw, efx->net_dev, 167 "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT 168 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg), 169 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask)); 170 return -EIO; 171 } 172 173 /************************************************************************** 174 * 175 * Special buffer handling 176 * Special buffers are used for event queues and the TX and RX 177 * descriptor rings. 178 * 179 *************************************************************************/ 180 181 /* 182 * Initialise a special buffer 183 * 184 * This will define a buffer (previously allocated via 185 * efx_alloc_special_buffer()) in the buffer table, allowing 186 * it to be used for event queues, descriptor rings etc. 187 */ 188 static void 189 efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer) 190 { 191 efx_qword_t buf_desc; 192 unsigned int index; 193 dma_addr_t dma_addr; 194 int i; 195 196 EFX_BUG_ON_PARANOID(!buffer->addr); 197 198 /* Write buffer descriptors to NIC */ 199 for (i = 0; i < buffer->entries; i++) { 200 index = buffer->index + i; 201 dma_addr = buffer->dma_addr + (i * EFX_BUF_SIZE); 202 netif_dbg(efx, probe, efx->net_dev, 203 "mapping special buffer %d at %llx\n", 204 index, (unsigned long long)dma_addr); 205 EFX_POPULATE_QWORD_3(buf_desc, 206 FRF_AZ_BUF_ADR_REGION, 0, 207 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12, 208 FRF_AZ_BUF_OWNER_ID_FBUF, 0); 209 efx_write_buf_tbl(efx, &buf_desc, index); 210 } 211 } 212 213 /* Unmaps a buffer and clears the buffer table entries */ 214 static void 215 efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer) 216 { 217 efx_oword_t buf_tbl_upd; 218 unsigned int start = buffer->index; 219 unsigned int end = (buffer->index + buffer->entries - 1); 220 221 if (!buffer->entries) 222 return; 223 224 netif_dbg(efx, hw, efx->net_dev, "unmapping special buffers %d-%d\n", 225 buffer->index, buffer->index + buffer->entries - 1); 226 227 EFX_POPULATE_OWORD_4(buf_tbl_upd, 228 FRF_AZ_BUF_UPD_CMD, 0, 229 FRF_AZ_BUF_CLR_CMD, 1, 230 FRF_AZ_BUF_CLR_END_ID, end, 231 FRF_AZ_BUF_CLR_START_ID, start); 232 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD); 233 } 234 235 /* 236 * Allocate a new special buffer 237 * 238 * This allocates memory for a new buffer, clears it and allocates a 239 * new buffer ID range. It does not write into the buffer table. 240 * 241 * This call will allocate 4KB buffers, since 8KB buffers can't be 242 * used for event queues and descriptor rings. 243 */ 244 static int efx_alloc_special_buffer(struct efx_nic *efx, 245 struct efx_special_buffer *buffer, 246 unsigned int len) 247 { 248 len = ALIGN(len, EFX_BUF_SIZE); 249 250 buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len, 251 &buffer->dma_addr, GFP_KERNEL); 252 if (!buffer->addr) 253 return -ENOMEM; 254 buffer->len = len; 255 buffer->entries = len / EFX_BUF_SIZE; 256 BUG_ON(buffer->dma_addr & (EFX_BUF_SIZE - 1)); 257 258 /* Select new buffer ID */ 259 buffer->index = efx->next_buffer_table; 260 efx->next_buffer_table += buffer->entries; 261 #ifdef CONFIG_SFC_SRIOV 262 BUG_ON(efx_sriov_enabled(efx) && 263 efx->vf_buftbl_base < efx->next_buffer_table); 264 #endif 265 266 netif_dbg(efx, probe, efx->net_dev, 267 "allocating special buffers %d-%d at %llx+%x " 268 "(virt %p phys %llx)\n", buffer->index, 269 buffer->index + buffer->entries - 1, 270 (u64)buffer->dma_addr, len, 271 buffer->addr, (u64)virt_to_phys(buffer->addr)); 272 273 return 0; 274 } 275 276 static void 277 efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer) 278 { 279 if (!buffer->addr) 280 return; 281 282 netif_dbg(efx, hw, efx->net_dev, 283 "deallocating special buffers %d-%d at %llx+%x " 284 "(virt %p phys %llx)\n", buffer->index, 285 buffer->index + buffer->entries - 1, 286 (u64)buffer->dma_addr, buffer->len, 287 buffer->addr, (u64)virt_to_phys(buffer->addr)); 288 289 dma_free_coherent(&efx->pci_dev->dev, buffer->len, buffer->addr, 290 buffer->dma_addr); 291 buffer->addr = NULL; 292 buffer->entries = 0; 293 } 294 295 /************************************************************************** 296 * 297 * Generic buffer handling 298 * These buffers are used for interrupt status, MAC stats, etc. 299 * 300 **************************************************************************/ 301 302 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, 303 unsigned int len) 304 { 305 buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len, 306 &buffer->dma_addr, GFP_ATOMIC); 307 if (!buffer->addr) 308 return -ENOMEM; 309 buffer->len = len; 310 memset(buffer->addr, 0, len); 311 return 0; 312 } 313 314 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer) 315 { 316 if (buffer->addr) { 317 dma_free_coherent(&efx->pci_dev->dev, buffer->len, 318 buffer->addr, buffer->dma_addr); 319 buffer->addr = NULL; 320 } 321 } 322 323 /************************************************************************** 324 * 325 * TX path 326 * 327 **************************************************************************/ 328 329 /* Returns a pointer to the specified transmit descriptor in the TX 330 * descriptor queue belonging to the specified channel. 331 */ 332 static inline efx_qword_t * 333 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index) 334 { 335 return ((efx_qword_t *) (tx_queue->txd.addr)) + index; 336 } 337 338 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 339 static inline void efx_notify_tx_desc(struct efx_tx_queue *tx_queue) 340 { 341 unsigned write_ptr; 342 efx_dword_t reg; 343 344 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 345 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr); 346 efx_writed_page(tx_queue->efx, ®, 347 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue); 348 } 349 350 /* Write pointer and first descriptor for TX descriptor ring */ 351 static inline void efx_push_tx_desc(struct efx_tx_queue *tx_queue, 352 const efx_qword_t *txd) 353 { 354 unsigned write_ptr; 355 efx_oword_t reg; 356 357 BUILD_BUG_ON(FRF_AZ_TX_DESC_LBN != 0); 358 BUILD_BUG_ON(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0); 359 360 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 361 EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true, 362 FRF_AZ_TX_DESC_WPTR, write_ptr); 363 reg.qword[0] = *txd; 364 efx_writeo_page(tx_queue->efx, ®, 365 FR_BZ_TX_DESC_UPD_P0, tx_queue->queue); 366 } 367 368 static inline bool 369 efx_may_push_tx_desc(struct efx_tx_queue *tx_queue, unsigned int write_count) 370 { 371 unsigned empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count); 372 373 if (empty_read_count == 0) 374 return false; 375 376 tx_queue->empty_read_count = 0; 377 return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0; 378 } 379 380 /* For each entry inserted into the software descriptor ring, create a 381 * descriptor in the hardware TX descriptor ring (in host memory), and 382 * write a doorbell. 383 */ 384 void efx_nic_push_buffers(struct efx_tx_queue *tx_queue) 385 { 386 387 struct efx_tx_buffer *buffer; 388 efx_qword_t *txd; 389 unsigned write_ptr; 390 unsigned old_write_count = tx_queue->write_count; 391 392 BUG_ON(tx_queue->write_count == tx_queue->insert_count); 393 394 do { 395 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 396 buffer = &tx_queue->buffer[write_ptr]; 397 txd = efx_tx_desc(tx_queue, write_ptr); 398 ++tx_queue->write_count; 399 400 /* Create TX descriptor ring entry */ 401 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 402 EFX_POPULATE_QWORD_4(*txd, 403 FSF_AZ_TX_KER_CONT, 404 buffer->flags & EFX_TX_BUF_CONT, 405 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len, 406 FSF_AZ_TX_KER_BUF_REGION, 0, 407 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr); 408 } while (tx_queue->write_count != tx_queue->insert_count); 409 410 wmb(); /* Ensure descriptors are written before they are fetched */ 411 412 if (efx_may_push_tx_desc(tx_queue, old_write_count)) { 413 txd = efx_tx_desc(tx_queue, 414 old_write_count & tx_queue->ptr_mask); 415 efx_push_tx_desc(tx_queue, txd); 416 ++tx_queue->pushes; 417 } else { 418 efx_notify_tx_desc(tx_queue); 419 } 420 } 421 422 /* Allocate hardware resources for a TX queue */ 423 int efx_nic_probe_tx(struct efx_tx_queue *tx_queue) 424 { 425 struct efx_nic *efx = tx_queue->efx; 426 unsigned entries; 427 428 entries = tx_queue->ptr_mask + 1; 429 return efx_alloc_special_buffer(efx, &tx_queue->txd, 430 entries * sizeof(efx_qword_t)); 431 } 432 433 void efx_nic_init_tx(struct efx_tx_queue *tx_queue) 434 { 435 struct efx_nic *efx = tx_queue->efx; 436 efx_oword_t reg; 437 438 /* Pin TX descriptor ring */ 439 efx_init_special_buffer(efx, &tx_queue->txd); 440 441 /* Push TX descriptor ring to card */ 442 EFX_POPULATE_OWORD_10(reg, 443 FRF_AZ_TX_DESCQ_EN, 1, 444 FRF_AZ_TX_ISCSI_DDIG_EN, 0, 445 FRF_AZ_TX_ISCSI_HDIG_EN, 0, 446 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index, 447 FRF_AZ_TX_DESCQ_EVQ_ID, 448 tx_queue->channel->channel, 449 FRF_AZ_TX_DESCQ_OWNER_ID, 0, 450 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue, 451 FRF_AZ_TX_DESCQ_SIZE, 452 __ffs(tx_queue->txd.entries), 453 FRF_AZ_TX_DESCQ_TYPE, 0, 454 FRF_BZ_TX_NON_IP_DROP_DIS, 1); 455 456 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { 457 int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; 458 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum); 459 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS, 460 !csum); 461 } 462 463 efx_writeo_table(efx, ®, efx->type->txd_ptr_tbl_base, 464 tx_queue->queue); 465 466 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) { 467 /* Only 128 bits in this register */ 468 BUILD_BUG_ON(EFX_MAX_TX_QUEUES > 128); 469 470 efx_reado(efx, ®, FR_AA_TX_CHKSM_CFG); 471 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) 472 __clear_bit_le(tx_queue->queue, ®); 473 else 474 __set_bit_le(tx_queue->queue, ®); 475 efx_writeo(efx, ®, FR_AA_TX_CHKSM_CFG); 476 } 477 478 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { 479 EFX_POPULATE_OWORD_1(reg, 480 FRF_BZ_TX_PACE, 481 (tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ? 482 FFE_BZ_TX_PACE_OFF : 483 FFE_BZ_TX_PACE_RESERVED); 484 efx_writeo_table(efx, ®, FR_BZ_TX_PACE_TBL, 485 tx_queue->queue); 486 } 487 } 488 489 static void efx_flush_tx_queue(struct efx_tx_queue *tx_queue) 490 { 491 struct efx_nic *efx = tx_queue->efx; 492 efx_oword_t tx_flush_descq; 493 494 EFX_POPULATE_OWORD_2(tx_flush_descq, 495 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1, 496 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue); 497 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ); 498 } 499 500 void efx_nic_fini_tx(struct efx_tx_queue *tx_queue) 501 { 502 struct efx_nic *efx = tx_queue->efx; 503 efx_oword_t tx_desc_ptr; 504 505 /* Remove TX descriptor ring from card */ 506 EFX_ZERO_OWORD(tx_desc_ptr); 507 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, 508 tx_queue->queue); 509 510 /* Unpin TX descriptor ring */ 511 efx_fini_special_buffer(efx, &tx_queue->txd); 512 } 513 514 /* Free buffers backing TX queue */ 515 void efx_nic_remove_tx(struct efx_tx_queue *tx_queue) 516 { 517 efx_free_special_buffer(tx_queue->efx, &tx_queue->txd); 518 } 519 520 /************************************************************************** 521 * 522 * RX path 523 * 524 **************************************************************************/ 525 526 /* Returns a pointer to the specified descriptor in the RX descriptor queue */ 527 static inline efx_qword_t * 528 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 529 { 530 return ((efx_qword_t *) (rx_queue->rxd.addr)) + index; 531 } 532 533 /* This creates an entry in the RX descriptor queue */ 534 static inline void 535 efx_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index) 536 { 537 struct efx_rx_buffer *rx_buf; 538 efx_qword_t *rxd; 539 540 rxd = efx_rx_desc(rx_queue, index); 541 rx_buf = efx_rx_buffer(rx_queue, index); 542 EFX_POPULATE_QWORD_3(*rxd, 543 FSF_AZ_RX_KER_BUF_SIZE, 544 rx_buf->len - 545 rx_queue->efx->type->rx_buffer_padding, 546 FSF_AZ_RX_KER_BUF_REGION, 0, 547 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 548 } 549 550 /* This writes to the RX_DESC_WPTR register for the specified receive 551 * descriptor ring. 552 */ 553 void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue) 554 { 555 struct efx_nic *efx = rx_queue->efx; 556 efx_dword_t reg; 557 unsigned write_ptr; 558 559 while (rx_queue->notified_count != rx_queue->added_count) { 560 efx_build_rx_desc( 561 rx_queue, 562 rx_queue->notified_count & rx_queue->ptr_mask); 563 ++rx_queue->notified_count; 564 } 565 566 wmb(); 567 write_ptr = rx_queue->added_count & rx_queue->ptr_mask; 568 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr); 569 efx_writed_page(efx, ®, FR_AZ_RX_DESC_UPD_DWORD_P0, 570 efx_rx_queue_index(rx_queue)); 571 } 572 573 int efx_nic_probe_rx(struct efx_rx_queue *rx_queue) 574 { 575 struct efx_nic *efx = rx_queue->efx; 576 unsigned entries; 577 578 entries = rx_queue->ptr_mask + 1; 579 return efx_alloc_special_buffer(efx, &rx_queue->rxd, 580 entries * sizeof(efx_qword_t)); 581 } 582 583 void efx_nic_init_rx(struct efx_rx_queue *rx_queue) 584 { 585 efx_oword_t rx_desc_ptr; 586 struct efx_nic *efx = rx_queue->efx; 587 bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0; 588 bool iscsi_digest_en = is_b0; 589 590 netif_dbg(efx, hw, efx->net_dev, 591 "RX queue %d ring in special buffers %d-%d\n", 592 efx_rx_queue_index(rx_queue), rx_queue->rxd.index, 593 rx_queue->rxd.index + rx_queue->rxd.entries - 1); 594 595 /* Pin RX descriptor ring */ 596 efx_init_special_buffer(efx, &rx_queue->rxd); 597 598 /* Push RX descriptor ring to card */ 599 EFX_POPULATE_OWORD_10(rx_desc_ptr, 600 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en, 601 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en, 602 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index, 603 FRF_AZ_RX_DESCQ_EVQ_ID, 604 efx_rx_queue_channel(rx_queue)->channel, 605 FRF_AZ_RX_DESCQ_OWNER_ID, 0, 606 FRF_AZ_RX_DESCQ_LABEL, 607 efx_rx_queue_index(rx_queue), 608 FRF_AZ_RX_DESCQ_SIZE, 609 __ffs(rx_queue->rxd.entries), 610 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ , 611 /* For >=B0 this is scatter so disable */ 612 FRF_AZ_RX_DESCQ_JUMBO, !is_b0, 613 FRF_AZ_RX_DESCQ_EN, 1); 614 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, 615 efx_rx_queue_index(rx_queue)); 616 } 617 618 static void efx_flush_rx_queue(struct efx_rx_queue *rx_queue) 619 { 620 struct efx_nic *efx = rx_queue->efx; 621 efx_oword_t rx_flush_descq; 622 623 EFX_POPULATE_OWORD_2(rx_flush_descq, 624 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1, 625 FRF_AZ_RX_FLUSH_DESCQ, 626 efx_rx_queue_index(rx_queue)); 627 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ); 628 } 629 630 void efx_nic_fini_rx(struct efx_rx_queue *rx_queue) 631 { 632 efx_oword_t rx_desc_ptr; 633 struct efx_nic *efx = rx_queue->efx; 634 635 /* Remove RX descriptor ring from card */ 636 EFX_ZERO_OWORD(rx_desc_ptr); 637 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, 638 efx_rx_queue_index(rx_queue)); 639 640 /* Unpin RX descriptor ring */ 641 efx_fini_special_buffer(efx, &rx_queue->rxd); 642 } 643 644 /* Free buffers backing RX queue */ 645 void efx_nic_remove_rx(struct efx_rx_queue *rx_queue) 646 { 647 efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd); 648 } 649 650 /************************************************************************** 651 * 652 * Flush handling 653 * 654 **************************************************************************/ 655 656 /* efx_nic_flush_queues() must be woken up when all flushes are completed, 657 * or more RX flushes can be kicked off. 658 */ 659 static bool efx_flush_wake(struct efx_nic *efx) 660 { 661 /* Ensure that all updates are visible to efx_nic_flush_queues() */ 662 smp_mb(); 663 664 return (atomic_read(&efx->drain_pending) == 0 || 665 (atomic_read(&efx->rxq_flush_outstanding) < EFX_RX_FLUSH_COUNT 666 && atomic_read(&efx->rxq_flush_pending) > 0)); 667 } 668 669 /* Flush all the transmit queues, and continue flushing receive queues until 670 * they're all flushed. Wait for the DRAIN events to be recieved so that there 671 * are no more RX and TX events left on any channel. */ 672 int efx_nic_flush_queues(struct efx_nic *efx) 673 { 674 unsigned timeout = msecs_to_jiffies(5000); /* 5s for all flushes and drains */ 675 struct efx_channel *channel; 676 struct efx_rx_queue *rx_queue; 677 struct efx_tx_queue *tx_queue; 678 int rc = 0; 679 680 efx->type->prepare_flush(efx); 681 682 efx_for_each_channel(channel, efx) { 683 efx_for_each_channel_tx_queue(tx_queue, channel) { 684 atomic_inc(&efx->drain_pending); 685 efx_flush_tx_queue(tx_queue); 686 } 687 efx_for_each_channel_rx_queue(rx_queue, channel) { 688 atomic_inc(&efx->drain_pending); 689 rx_queue->flush_pending = true; 690 atomic_inc(&efx->rxq_flush_pending); 691 } 692 } 693 694 while (timeout && atomic_read(&efx->drain_pending) > 0) { 695 /* If SRIOV is enabled, then offload receive queue flushing to 696 * the firmware (though we will still have to poll for 697 * completion). If that fails, fall back to the old scheme. 698 */ 699 if (efx_sriov_enabled(efx)) { 700 rc = efx_mcdi_flush_rxqs(efx); 701 if (!rc) 702 goto wait; 703 } 704 705 /* The hardware supports four concurrent rx flushes, each of 706 * which may need to be retried if there is an outstanding 707 * descriptor fetch 708 */ 709 efx_for_each_channel(channel, efx) { 710 efx_for_each_channel_rx_queue(rx_queue, channel) { 711 if (atomic_read(&efx->rxq_flush_outstanding) >= 712 EFX_RX_FLUSH_COUNT) 713 break; 714 715 if (rx_queue->flush_pending) { 716 rx_queue->flush_pending = false; 717 atomic_dec(&efx->rxq_flush_pending); 718 atomic_inc(&efx->rxq_flush_outstanding); 719 efx_flush_rx_queue(rx_queue); 720 } 721 } 722 } 723 724 wait: 725 timeout = wait_event_timeout(efx->flush_wq, efx_flush_wake(efx), 726 timeout); 727 } 728 729 if (atomic_read(&efx->drain_pending)) { 730 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues " 731 "(rx %d+%d)\n", atomic_read(&efx->drain_pending), 732 atomic_read(&efx->rxq_flush_outstanding), 733 atomic_read(&efx->rxq_flush_pending)); 734 rc = -ETIMEDOUT; 735 736 atomic_set(&efx->drain_pending, 0); 737 atomic_set(&efx->rxq_flush_pending, 0); 738 atomic_set(&efx->rxq_flush_outstanding, 0); 739 } 740 741 efx->type->finish_flush(efx); 742 743 return rc; 744 } 745 746 /************************************************************************** 747 * 748 * Event queue processing 749 * Event queues are processed by per-channel tasklets. 750 * 751 **************************************************************************/ 752 753 /* Update a channel's event queue's read pointer (RPTR) register 754 * 755 * This writes the EVQ_RPTR_REG register for the specified channel's 756 * event queue. 757 */ 758 void efx_nic_eventq_read_ack(struct efx_channel *channel) 759 { 760 efx_dword_t reg; 761 struct efx_nic *efx = channel->efx; 762 763 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, 764 channel->eventq_read_ptr & channel->eventq_mask); 765 766 /* For Falcon A1, EVQ_RPTR_KER is documented as having a step size 767 * of 4 bytes, but it is really 16 bytes just like later revisions. 768 */ 769 efx_writed(efx, ®, 770 efx->type->evq_rptr_tbl_base + 771 FR_BZ_EVQ_RPTR_STEP * channel->channel); 772 } 773 774 /* Use HW to insert a SW defined event */ 775 void efx_generate_event(struct efx_nic *efx, unsigned int evq, 776 efx_qword_t *event) 777 { 778 efx_oword_t drv_ev_reg; 779 780 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 || 781 FRF_AZ_DRV_EV_DATA_WIDTH != 64); 782 drv_ev_reg.u32[0] = event->u32[0]; 783 drv_ev_reg.u32[1] = event->u32[1]; 784 drv_ev_reg.u32[2] = 0; 785 drv_ev_reg.u32[3] = 0; 786 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, evq); 787 efx_writeo(efx, &drv_ev_reg, FR_AZ_DRV_EV); 788 } 789 790 static void efx_magic_event(struct efx_channel *channel, u32 magic) 791 { 792 efx_qword_t event; 793 794 EFX_POPULATE_QWORD_2(event, FSF_AZ_EV_CODE, 795 FSE_AZ_EV_CODE_DRV_GEN_EV, 796 FSF_AZ_DRV_GEN_EV_MAGIC, magic); 797 efx_generate_event(channel->efx, channel->channel, &event); 798 } 799 800 /* Handle a transmit completion event 801 * 802 * The NIC batches TX completion events; the message we receive is of 803 * the form "complete all TX events up to this index". 804 */ 805 static int 806 efx_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 807 { 808 unsigned int tx_ev_desc_ptr; 809 unsigned int tx_ev_q_label; 810 struct efx_tx_queue *tx_queue; 811 struct efx_nic *efx = channel->efx; 812 int tx_packets = 0; 813 814 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 815 return 0; 816 817 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) { 818 /* Transmit completion */ 819 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR); 820 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); 821 tx_queue = efx_channel_get_tx_queue( 822 channel, tx_ev_q_label % EFX_TXQ_TYPES); 823 tx_packets = ((tx_ev_desc_ptr - tx_queue->read_count) & 824 tx_queue->ptr_mask); 825 efx_xmit_done(tx_queue, tx_ev_desc_ptr); 826 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) { 827 /* Rewrite the FIFO write pointer */ 828 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); 829 tx_queue = efx_channel_get_tx_queue( 830 channel, tx_ev_q_label % EFX_TXQ_TYPES); 831 832 netif_tx_lock(efx->net_dev); 833 efx_notify_tx_desc(tx_queue); 834 netif_tx_unlock(efx->net_dev); 835 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) && 836 EFX_WORKAROUND_10727(efx)) { 837 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); 838 } else { 839 netif_err(efx, tx_err, efx->net_dev, 840 "channel %d unexpected TX event " 841 EFX_QWORD_FMT"\n", channel->channel, 842 EFX_QWORD_VAL(*event)); 843 } 844 845 return tx_packets; 846 } 847 848 /* Detect errors included in the rx_evt_pkt_ok bit. */ 849 static u16 efx_handle_rx_not_ok(struct efx_rx_queue *rx_queue, 850 const efx_qword_t *event) 851 { 852 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 853 struct efx_nic *efx = rx_queue->efx; 854 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err; 855 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err; 856 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc; 857 bool rx_ev_other_err, rx_ev_pause_frm; 858 bool rx_ev_hdr_type, rx_ev_mcast_pkt; 859 unsigned rx_ev_pkt_type; 860 861 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); 862 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); 863 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC); 864 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE); 865 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event, 866 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR); 867 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event, 868 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR); 869 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event, 870 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR); 871 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR); 872 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC); 873 rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ? 874 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB)); 875 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR); 876 877 /* Every error apart from tobe_disc and pause_frm */ 878 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err | 879 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err | 880 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err); 881 882 /* Count errors that are not in MAC stats. Ignore expected 883 * checksum errors during self-test. */ 884 if (rx_ev_frm_trunc) 885 ++channel->n_rx_frm_trunc; 886 else if (rx_ev_tobe_disc) 887 ++channel->n_rx_tobe_disc; 888 else if (!efx->loopback_selftest) { 889 if (rx_ev_ip_hdr_chksum_err) 890 ++channel->n_rx_ip_hdr_chksum_err; 891 else if (rx_ev_tcp_udp_chksum_err) 892 ++channel->n_rx_tcp_udp_chksum_err; 893 } 894 895 /* TOBE_DISC is expected on unicast mismatches; don't print out an 896 * error message. FRM_TRUNC indicates RXDP dropped the packet due 897 * to a FIFO overflow. 898 */ 899 #ifdef DEBUG 900 if (rx_ev_other_err && net_ratelimit()) { 901 netif_dbg(efx, rx_err, efx->net_dev, 902 " RX queue %d unexpected RX event " 903 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n", 904 efx_rx_queue_index(rx_queue), EFX_QWORD_VAL(*event), 905 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "", 906 rx_ev_ip_hdr_chksum_err ? 907 " [IP_HDR_CHKSUM_ERR]" : "", 908 rx_ev_tcp_udp_chksum_err ? 909 " [TCP_UDP_CHKSUM_ERR]" : "", 910 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "", 911 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "", 912 rx_ev_drib_nib ? " [DRIB_NIB]" : "", 913 rx_ev_tobe_disc ? " [TOBE_DISC]" : "", 914 rx_ev_pause_frm ? " [PAUSE]" : ""); 915 } 916 #endif 917 918 /* The frame must be discarded if any of these are true. */ 919 return (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib | 920 rx_ev_tobe_disc | rx_ev_pause_frm) ? 921 EFX_RX_PKT_DISCARD : 0; 922 } 923 924 /* Handle receive events that are not in-order. */ 925 static void 926 efx_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index) 927 { 928 struct efx_nic *efx = rx_queue->efx; 929 unsigned expected, dropped; 930 931 expected = rx_queue->removed_count & rx_queue->ptr_mask; 932 dropped = (index - expected) & rx_queue->ptr_mask; 933 netif_info(efx, rx_err, efx->net_dev, 934 "dropped %d events (index=%d expected=%d)\n", 935 dropped, index, expected); 936 937 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ? 938 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); 939 } 940 941 /* Handle a packet received event 942 * 943 * The NIC gives a "discard" flag if it's a unicast packet with the 944 * wrong destination address 945 * Also "is multicast" and "matches multicast filter" flags can be used to 946 * discard non-matching multicast packets. 947 */ 948 static void 949 efx_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event) 950 { 951 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt; 952 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt; 953 unsigned expected_ptr; 954 bool rx_ev_pkt_ok; 955 u16 flags; 956 struct efx_rx_queue *rx_queue; 957 struct efx_nic *efx = channel->efx; 958 959 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 960 return; 961 962 /* Basic packet information */ 963 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT); 964 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK); 965 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); 966 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT)); 967 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1); 968 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) != 969 channel->channel); 970 971 rx_queue = efx_channel_get_rx_queue(channel); 972 973 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR); 974 expected_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 975 if (unlikely(rx_ev_desc_ptr != expected_ptr)) 976 efx_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr); 977 978 if (likely(rx_ev_pkt_ok)) { 979 /* If packet is marked as OK and packet type is TCP/IP or 980 * UDP/IP, then we can rely on the hardware checksum. 981 */ 982 flags = (rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP || 983 rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP) ? 984 EFX_RX_PKT_CSUMMED : 0; 985 } else { 986 flags = efx_handle_rx_not_ok(rx_queue, event); 987 } 988 989 /* Detect multicast packets that didn't match the filter */ 990 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); 991 if (rx_ev_mcast_pkt) { 992 unsigned int rx_ev_mcast_hash_match = 993 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH); 994 995 if (unlikely(!rx_ev_mcast_hash_match)) { 996 ++channel->n_rx_mcast_mismatch; 997 flags |= EFX_RX_PKT_DISCARD; 998 } 999 } 1000 1001 channel->irq_mod_score += 2; 1002 1003 /* Handle received packet */ 1004 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt, flags); 1005 } 1006 1007 /* If this flush done event corresponds to a &struct efx_tx_queue, then 1008 * send an %EFX_CHANNEL_MAGIC_TX_DRAIN event to drain the event queue 1009 * of all transmit completions. 1010 */ 1011 static void 1012 efx_handle_tx_flush_done(struct efx_nic *efx, efx_qword_t *event) 1013 { 1014 struct efx_tx_queue *tx_queue; 1015 int qid; 1016 1017 qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA); 1018 if (qid < EFX_TXQ_TYPES * efx->n_tx_channels) { 1019 tx_queue = efx_get_tx_queue(efx, qid / EFX_TXQ_TYPES, 1020 qid % EFX_TXQ_TYPES); 1021 1022 efx_magic_event(tx_queue->channel, 1023 EFX_CHANNEL_MAGIC_TX_DRAIN(tx_queue)); 1024 } 1025 } 1026 1027 /* If this flush done event corresponds to a &struct efx_rx_queue: If the flush 1028 * was succesful then send an %EFX_CHANNEL_MAGIC_RX_DRAIN, otherwise add 1029 * the RX queue back to the mask of RX queues in need of flushing. 1030 */ 1031 static void 1032 efx_handle_rx_flush_done(struct efx_nic *efx, efx_qword_t *event) 1033 { 1034 struct efx_channel *channel; 1035 struct efx_rx_queue *rx_queue; 1036 int qid; 1037 bool failed; 1038 1039 qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); 1040 failed = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); 1041 if (qid >= efx->n_channels) 1042 return; 1043 channel = efx_get_channel(efx, qid); 1044 if (!efx_channel_has_rx_queue(channel)) 1045 return; 1046 rx_queue = efx_channel_get_rx_queue(channel); 1047 1048 if (failed) { 1049 netif_info(efx, hw, efx->net_dev, 1050 "RXQ %d flush retry\n", qid); 1051 rx_queue->flush_pending = true; 1052 atomic_inc(&efx->rxq_flush_pending); 1053 } else { 1054 efx_magic_event(efx_rx_queue_channel(rx_queue), 1055 EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue)); 1056 } 1057 atomic_dec(&efx->rxq_flush_outstanding); 1058 if (efx_flush_wake(efx)) 1059 wake_up(&efx->flush_wq); 1060 } 1061 1062 static void 1063 efx_handle_drain_event(struct efx_channel *channel) 1064 { 1065 struct efx_nic *efx = channel->efx; 1066 1067 WARN_ON(atomic_read(&efx->drain_pending) == 0); 1068 atomic_dec(&efx->drain_pending); 1069 if (efx_flush_wake(efx)) 1070 wake_up(&efx->flush_wq); 1071 } 1072 1073 static void 1074 efx_handle_generated_event(struct efx_channel *channel, efx_qword_t *event) 1075 { 1076 struct efx_nic *efx = channel->efx; 1077 struct efx_rx_queue *rx_queue = 1078 efx_channel_has_rx_queue(channel) ? 1079 efx_channel_get_rx_queue(channel) : NULL; 1080 unsigned magic, code; 1081 1082 magic = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC); 1083 code = _EFX_CHANNEL_MAGIC_CODE(magic); 1084 1085 if (magic == EFX_CHANNEL_MAGIC_TEST(channel)) { 1086 channel->event_test_cpu = raw_smp_processor_id(); 1087 } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_FILL(rx_queue)) { 1088 /* The queue must be empty, so we won't receive any rx 1089 * events, so efx_process_channel() won't refill the 1090 * queue. Refill it here */ 1091 efx_fast_push_rx_descriptors(rx_queue); 1092 } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue)) { 1093 rx_queue->enabled = false; 1094 efx_handle_drain_event(channel); 1095 } else if (code == _EFX_CHANNEL_MAGIC_TX_DRAIN) { 1096 efx_handle_drain_event(channel); 1097 } else { 1098 netif_dbg(efx, hw, efx->net_dev, "channel %d received " 1099 "generated event "EFX_QWORD_FMT"\n", 1100 channel->channel, EFX_QWORD_VAL(*event)); 1101 } 1102 } 1103 1104 static void 1105 efx_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 1106 { 1107 struct efx_nic *efx = channel->efx; 1108 unsigned int ev_sub_code; 1109 unsigned int ev_sub_data; 1110 1111 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE); 1112 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA); 1113 1114 switch (ev_sub_code) { 1115 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: 1116 netif_vdbg(efx, hw, efx->net_dev, "channel %d TXQ %d flushed\n", 1117 channel->channel, ev_sub_data); 1118 efx_handle_tx_flush_done(efx, event); 1119 efx_sriov_tx_flush_done(efx, event); 1120 break; 1121 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: 1122 netif_vdbg(efx, hw, efx->net_dev, "channel %d RXQ %d flushed\n", 1123 channel->channel, ev_sub_data); 1124 efx_handle_rx_flush_done(efx, event); 1125 efx_sriov_rx_flush_done(efx, event); 1126 break; 1127 case FSE_AZ_EVQ_INIT_DONE_EV: 1128 netif_dbg(efx, hw, efx->net_dev, 1129 "channel %d EVQ %d initialised\n", 1130 channel->channel, ev_sub_data); 1131 break; 1132 case FSE_AZ_SRM_UPD_DONE_EV: 1133 netif_vdbg(efx, hw, efx->net_dev, 1134 "channel %d SRAM update done\n", channel->channel); 1135 break; 1136 case FSE_AZ_WAKE_UP_EV: 1137 netif_vdbg(efx, hw, efx->net_dev, 1138 "channel %d RXQ %d wakeup event\n", 1139 channel->channel, ev_sub_data); 1140 break; 1141 case FSE_AZ_TIMER_EV: 1142 netif_vdbg(efx, hw, efx->net_dev, 1143 "channel %d RX queue %d timer expired\n", 1144 channel->channel, ev_sub_data); 1145 break; 1146 case FSE_AA_RX_RECOVER_EV: 1147 netif_err(efx, rx_err, efx->net_dev, 1148 "channel %d seen DRIVER RX_RESET event. " 1149 "Resetting.\n", channel->channel); 1150 atomic_inc(&efx->rx_reset); 1151 efx_schedule_reset(efx, 1152 EFX_WORKAROUND_6555(efx) ? 1153 RESET_TYPE_RX_RECOVERY : 1154 RESET_TYPE_DISABLE); 1155 break; 1156 case FSE_BZ_RX_DSC_ERROR_EV: 1157 if (ev_sub_data < EFX_VI_BASE) { 1158 netif_err(efx, rx_err, efx->net_dev, 1159 "RX DMA Q %d reports descriptor fetch error." 1160 " RX Q %d is disabled.\n", ev_sub_data, 1161 ev_sub_data); 1162 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH); 1163 } else 1164 efx_sriov_desc_fetch_err(efx, ev_sub_data); 1165 break; 1166 case FSE_BZ_TX_DSC_ERROR_EV: 1167 if (ev_sub_data < EFX_VI_BASE) { 1168 netif_err(efx, tx_err, efx->net_dev, 1169 "TX DMA Q %d reports descriptor fetch error." 1170 " TX Q %d is disabled.\n", ev_sub_data, 1171 ev_sub_data); 1172 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); 1173 } else 1174 efx_sriov_desc_fetch_err(efx, ev_sub_data); 1175 break; 1176 default: 1177 netif_vdbg(efx, hw, efx->net_dev, 1178 "channel %d unknown driver event code %d " 1179 "data %04x\n", channel->channel, ev_sub_code, 1180 ev_sub_data); 1181 break; 1182 } 1183 } 1184 1185 int efx_nic_process_eventq(struct efx_channel *channel, int budget) 1186 { 1187 struct efx_nic *efx = channel->efx; 1188 unsigned int read_ptr; 1189 efx_qword_t event, *p_event; 1190 int ev_code; 1191 int tx_packets = 0; 1192 int spent = 0; 1193 1194 read_ptr = channel->eventq_read_ptr; 1195 1196 for (;;) { 1197 p_event = efx_event(channel, read_ptr); 1198 event = *p_event; 1199 1200 if (!efx_event_present(&event)) 1201 /* End of events */ 1202 break; 1203 1204 netif_vdbg(channel->efx, intr, channel->efx->net_dev, 1205 "channel %d event is "EFX_QWORD_FMT"\n", 1206 channel->channel, EFX_QWORD_VAL(event)); 1207 1208 /* Clear this event by marking it all ones */ 1209 EFX_SET_QWORD(*p_event); 1210 1211 ++read_ptr; 1212 1213 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE); 1214 1215 switch (ev_code) { 1216 case FSE_AZ_EV_CODE_RX_EV: 1217 efx_handle_rx_event(channel, &event); 1218 if (++spent == budget) 1219 goto out; 1220 break; 1221 case FSE_AZ_EV_CODE_TX_EV: 1222 tx_packets += efx_handle_tx_event(channel, &event); 1223 if (tx_packets > efx->txq_entries) { 1224 spent = budget; 1225 goto out; 1226 } 1227 break; 1228 case FSE_AZ_EV_CODE_DRV_GEN_EV: 1229 efx_handle_generated_event(channel, &event); 1230 break; 1231 case FSE_AZ_EV_CODE_DRIVER_EV: 1232 efx_handle_driver_event(channel, &event); 1233 break; 1234 case FSE_CZ_EV_CODE_USER_EV: 1235 efx_sriov_event(channel, &event); 1236 break; 1237 case FSE_CZ_EV_CODE_MCDI_EV: 1238 efx_mcdi_process_event(channel, &event); 1239 break; 1240 case FSE_AZ_EV_CODE_GLOBAL_EV: 1241 if (efx->type->handle_global_event && 1242 efx->type->handle_global_event(channel, &event)) 1243 break; 1244 /* else fall through */ 1245 default: 1246 netif_err(channel->efx, hw, channel->efx->net_dev, 1247 "channel %d unknown event type %d (data " 1248 EFX_QWORD_FMT ")\n", channel->channel, 1249 ev_code, EFX_QWORD_VAL(event)); 1250 } 1251 } 1252 1253 out: 1254 channel->eventq_read_ptr = read_ptr; 1255 return spent; 1256 } 1257 1258 /* Check whether an event is present in the eventq at the current 1259 * read pointer. Only useful for self-test. 1260 */ 1261 bool efx_nic_event_present(struct efx_channel *channel) 1262 { 1263 return efx_event_present(efx_event(channel, channel->eventq_read_ptr)); 1264 } 1265 1266 /* Allocate buffer table entries for event queue */ 1267 int efx_nic_probe_eventq(struct efx_channel *channel) 1268 { 1269 struct efx_nic *efx = channel->efx; 1270 unsigned entries; 1271 1272 entries = channel->eventq_mask + 1; 1273 return efx_alloc_special_buffer(efx, &channel->eventq, 1274 entries * sizeof(efx_qword_t)); 1275 } 1276 1277 void efx_nic_init_eventq(struct efx_channel *channel) 1278 { 1279 efx_oword_t reg; 1280 struct efx_nic *efx = channel->efx; 1281 1282 netif_dbg(efx, hw, efx->net_dev, 1283 "channel %d event queue in special buffers %d-%d\n", 1284 channel->channel, channel->eventq.index, 1285 channel->eventq.index + channel->eventq.entries - 1); 1286 1287 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) { 1288 EFX_POPULATE_OWORD_3(reg, 1289 FRF_CZ_TIMER_Q_EN, 1, 1290 FRF_CZ_HOST_NOTIFY_MODE, 0, 1291 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS); 1292 efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, channel->channel); 1293 } 1294 1295 /* Pin event queue buffer */ 1296 efx_init_special_buffer(efx, &channel->eventq); 1297 1298 /* Fill event queue with all ones (i.e. empty events) */ 1299 memset(channel->eventq.addr, 0xff, channel->eventq.len); 1300 1301 /* Push event queue to card */ 1302 EFX_POPULATE_OWORD_3(reg, 1303 FRF_AZ_EVQ_EN, 1, 1304 FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries), 1305 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index); 1306 efx_writeo_table(efx, ®, efx->type->evq_ptr_tbl_base, 1307 channel->channel); 1308 1309 efx->type->push_irq_moderation(channel); 1310 } 1311 1312 void efx_nic_fini_eventq(struct efx_channel *channel) 1313 { 1314 efx_oword_t reg; 1315 struct efx_nic *efx = channel->efx; 1316 1317 /* Remove event queue from card */ 1318 EFX_ZERO_OWORD(reg); 1319 efx_writeo_table(efx, ®, efx->type->evq_ptr_tbl_base, 1320 channel->channel); 1321 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) 1322 efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, channel->channel); 1323 1324 /* Unpin event queue */ 1325 efx_fini_special_buffer(efx, &channel->eventq); 1326 } 1327 1328 /* Free buffers backing event queue */ 1329 void efx_nic_remove_eventq(struct efx_channel *channel) 1330 { 1331 efx_free_special_buffer(channel->efx, &channel->eventq); 1332 } 1333 1334 1335 void efx_nic_event_test_start(struct efx_channel *channel) 1336 { 1337 channel->event_test_cpu = -1; 1338 smp_wmb(); 1339 efx_magic_event(channel, EFX_CHANNEL_MAGIC_TEST(channel)); 1340 } 1341 1342 void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue) 1343 { 1344 efx_magic_event(efx_rx_queue_channel(rx_queue), 1345 EFX_CHANNEL_MAGIC_FILL(rx_queue)); 1346 } 1347 1348 /************************************************************************** 1349 * 1350 * Hardware interrupts 1351 * The hardware interrupt handler does very little work; all the event 1352 * queue processing is carried out by per-channel tasklets. 1353 * 1354 **************************************************************************/ 1355 1356 /* Enable/disable/generate interrupts */ 1357 static inline void efx_nic_interrupts(struct efx_nic *efx, 1358 bool enabled, bool force) 1359 { 1360 efx_oword_t int_en_reg_ker; 1361 1362 EFX_POPULATE_OWORD_3(int_en_reg_ker, 1363 FRF_AZ_KER_INT_LEVE_SEL, efx->irq_level, 1364 FRF_AZ_KER_INT_KER, force, 1365 FRF_AZ_DRV_INT_EN_KER, enabled); 1366 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER); 1367 } 1368 1369 void efx_nic_enable_interrupts(struct efx_nic *efx) 1370 { 1371 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr)); 1372 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */ 1373 1374 efx_nic_interrupts(efx, true, false); 1375 } 1376 1377 void efx_nic_disable_interrupts(struct efx_nic *efx) 1378 { 1379 /* Disable interrupts */ 1380 efx_nic_interrupts(efx, false, false); 1381 } 1382 1383 /* Generate a test interrupt 1384 * Interrupt must already have been enabled, otherwise nasty things 1385 * may happen. 1386 */ 1387 void efx_nic_irq_test_start(struct efx_nic *efx) 1388 { 1389 efx->last_irq_cpu = -1; 1390 smp_wmb(); 1391 efx_nic_interrupts(efx, true, true); 1392 } 1393 1394 /* Process a fatal interrupt 1395 * Disable bus mastering ASAP and schedule a reset 1396 */ 1397 irqreturn_t efx_nic_fatal_interrupt(struct efx_nic *efx) 1398 { 1399 struct falcon_nic_data *nic_data = efx->nic_data; 1400 efx_oword_t *int_ker = efx->irq_status.addr; 1401 efx_oword_t fatal_intr; 1402 int error, mem_perr; 1403 1404 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER); 1405 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR); 1406 1407 netif_err(efx, hw, efx->net_dev, "SYSTEM ERROR "EFX_OWORD_FMT" status " 1408 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker), 1409 EFX_OWORD_VAL(fatal_intr), 1410 error ? "disabling bus mastering" : "no recognised error"); 1411 1412 /* If this is a memory parity error dump which blocks are offending */ 1413 mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) || 1414 EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER)); 1415 if (mem_perr) { 1416 efx_oword_t reg; 1417 efx_reado(efx, ®, FR_AZ_MEM_STAT); 1418 netif_err(efx, hw, efx->net_dev, 1419 "SYSTEM ERROR: memory parity error "EFX_OWORD_FMT"\n", 1420 EFX_OWORD_VAL(reg)); 1421 } 1422 1423 /* Disable both devices */ 1424 pci_clear_master(efx->pci_dev); 1425 if (efx_nic_is_dual_func(efx)) 1426 pci_clear_master(nic_data->pci_dev2); 1427 efx_nic_disable_interrupts(efx); 1428 1429 /* Count errors and reset or disable the NIC accordingly */ 1430 if (efx->int_error_count == 0 || 1431 time_after(jiffies, efx->int_error_expire)) { 1432 efx->int_error_count = 0; 1433 efx->int_error_expire = 1434 jiffies + EFX_INT_ERROR_EXPIRE * HZ; 1435 } 1436 if (++efx->int_error_count < EFX_MAX_INT_ERRORS) { 1437 netif_err(efx, hw, efx->net_dev, 1438 "SYSTEM ERROR - reset scheduled\n"); 1439 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR); 1440 } else { 1441 netif_err(efx, hw, efx->net_dev, 1442 "SYSTEM ERROR - max number of errors seen." 1443 "NIC will be disabled\n"); 1444 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 1445 } 1446 1447 return IRQ_HANDLED; 1448 } 1449 1450 /* Handle a legacy interrupt 1451 * Acknowledges the interrupt and schedule event queue processing. 1452 */ 1453 static irqreturn_t efx_legacy_interrupt(int irq, void *dev_id) 1454 { 1455 struct efx_nic *efx = dev_id; 1456 efx_oword_t *int_ker = efx->irq_status.addr; 1457 irqreturn_t result = IRQ_NONE; 1458 struct efx_channel *channel; 1459 efx_dword_t reg; 1460 u32 queues; 1461 int syserr; 1462 1463 /* Could this be ours? If interrupts are disabled then the 1464 * channel state may not be valid. 1465 */ 1466 if (!efx->legacy_irq_enabled) 1467 return result; 1468 1469 /* Read the ISR which also ACKs the interrupts */ 1470 efx_readd(efx, ®, FR_BZ_INT_ISR0); 1471 queues = EFX_EXTRACT_DWORD(reg, 0, 31); 1472 1473 /* Handle non-event-queue sources */ 1474 if (queues & (1U << efx->irq_level)) { 1475 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); 1476 if (unlikely(syserr)) 1477 return efx_nic_fatal_interrupt(efx); 1478 efx->last_irq_cpu = raw_smp_processor_id(); 1479 } 1480 1481 if (queues != 0) { 1482 if (EFX_WORKAROUND_15783(efx)) 1483 efx->irq_zero_count = 0; 1484 1485 /* Schedule processing of any interrupting queues */ 1486 efx_for_each_channel(channel, efx) { 1487 if (queues & 1) 1488 efx_schedule_channel_irq(channel); 1489 queues >>= 1; 1490 } 1491 result = IRQ_HANDLED; 1492 1493 } else if (EFX_WORKAROUND_15783(efx)) { 1494 efx_qword_t *event; 1495 1496 /* We can't return IRQ_HANDLED more than once on seeing ISR=0 1497 * because this might be a shared interrupt. */ 1498 if (efx->irq_zero_count++ == 0) 1499 result = IRQ_HANDLED; 1500 1501 /* Ensure we schedule or rearm all event queues */ 1502 efx_for_each_channel(channel, efx) { 1503 event = efx_event(channel, channel->eventq_read_ptr); 1504 if (efx_event_present(event)) 1505 efx_schedule_channel_irq(channel); 1506 else 1507 efx_nic_eventq_read_ack(channel); 1508 } 1509 } 1510 1511 if (result == IRQ_HANDLED) 1512 netif_vdbg(efx, intr, efx->net_dev, 1513 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 1514 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 1515 1516 return result; 1517 } 1518 1519 /* Handle an MSI interrupt 1520 * 1521 * Handle an MSI hardware interrupt. This routine schedules event 1522 * queue processing. No interrupt acknowledgement cycle is necessary. 1523 * Also, we never need to check that the interrupt is for us, since 1524 * MSI interrupts cannot be shared. 1525 */ 1526 static irqreturn_t efx_msi_interrupt(int irq, void *dev_id) 1527 { 1528 struct efx_channel *channel = *(struct efx_channel **)dev_id; 1529 struct efx_nic *efx = channel->efx; 1530 efx_oword_t *int_ker = efx->irq_status.addr; 1531 int syserr; 1532 1533 netif_vdbg(efx, intr, efx->net_dev, 1534 "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", 1535 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); 1536 1537 /* Handle non-event-queue sources */ 1538 if (channel->channel == efx->irq_level) { 1539 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); 1540 if (unlikely(syserr)) 1541 return efx_nic_fatal_interrupt(efx); 1542 efx->last_irq_cpu = raw_smp_processor_id(); 1543 } 1544 1545 /* Schedule processing of the channel */ 1546 efx_schedule_channel_irq(channel); 1547 1548 return IRQ_HANDLED; 1549 } 1550 1551 1552 /* Setup RSS indirection table. 1553 * This maps from the hash value of the packet to RXQ 1554 */ 1555 void efx_nic_push_rx_indir_table(struct efx_nic *efx) 1556 { 1557 size_t i = 0; 1558 efx_dword_t dword; 1559 1560 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) 1561 return; 1562 1563 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) != 1564 FR_BZ_RX_INDIRECTION_TBL_ROWS); 1565 1566 for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) { 1567 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE, 1568 efx->rx_indir_table[i]); 1569 efx_writed(efx, &dword, 1570 FR_BZ_RX_INDIRECTION_TBL + 1571 FR_BZ_RX_INDIRECTION_TBL_STEP * i); 1572 } 1573 } 1574 1575 /* Hook interrupt handler(s) 1576 * Try MSI and then legacy interrupts. 1577 */ 1578 int efx_nic_init_interrupt(struct efx_nic *efx) 1579 { 1580 struct efx_channel *channel; 1581 int rc; 1582 1583 if (!EFX_INT_MODE_USE_MSI(efx)) { 1584 irq_handler_t handler; 1585 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) 1586 handler = efx_legacy_interrupt; 1587 else 1588 handler = falcon_legacy_interrupt_a1; 1589 1590 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED, 1591 efx->name, efx); 1592 if (rc) { 1593 netif_err(efx, drv, efx->net_dev, 1594 "failed to hook legacy IRQ %d\n", 1595 efx->pci_dev->irq); 1596 goto fail1; 1597 } 1598 return 0; 1599 } 1600 1601 /* Hook MSI or MSI-X interrupt */ 1602 efx_for_each_channel(channel, efx) { 1603 rc = request_irq(channel->irq, efx_msi_interrupt, 1604 IRQF_PROBE_SHARED, /* Not shared */ 1605 efx->channel_name[channel->channel], 1606 &efx->channel[channel->channel]); 1607 if (rc) { 1608 netif_err(efx, drv, efx->net_dev, 1609 "failed to hook IRQ %d\n", channel->irq); 1610 goto fail2; 1611 } 1612 } 1613 1614 return 0; 1615 1616 fail2: 1617 efx_for_each_channel(channel, efx) 1618 free_irq(channel->irq, &efx->channel[channel->channel]); 1619 fail1: 1620 return rc; 1621 } 1622 1623 void efx_nic_fini_interrupt(struct efx_nic *efx) 1624 { 1625 struct efx_channel *channel; 1626 efx_oword_t reg; 1627 1628 /* Disable MSI/MSI-X interrupts */ 1629 efx_for_each_channel(channel, efx) { 1630 if (channel->irq) 1631 free_irq(channel->irq, &efx->channel[channel->channel]); 1632 } 1633 1634 /* ACK legacy interrupt */ 1635 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) 1636 efx_reado(efx, ®, FR_BZ_INT_ISR0); 1637 else 1638 falcon_irq_ack_a1(efx); 1639 1640 /* Disable legacy interrupt */ 1641 if (efx->legacy_irq) 1642 free_irq(efx->legacy_irq, efx); 1643 } 1644 1645 /* Looks at available SRAM resources and works out how many queues we 1646 * can support, and where things like descriptor caches should live. 1647 * 1648 * SRAM is split up as follows: 1649 * 0 buftbl entries for channels 1650 * efx->vf_buftbl_base buftbl entries for SR-IOV 1651 * efx->rx_dc_base RX descriptor caches 1652 * efx->tx_dc_base TX descriptor caches 1653 */ 1654 void efx_nic_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw) 1655 { 1656 unsigned vi_count, buftbl_min; 1657 1658 /* Account for the buffer table entries backing the datapath channels 1659 * and the descriptor caches for those channels. 1660 */ 1661 buftbl_min = ((efx->n_rx_channels * EFX_MAX_DMAQ_SIZE + 1662 efx->n_tx_channels * EFX_TXQ_TYPES * EFX_MAX_DMAQ_SIZE + 1663 efx->n_channels * EFX_MAX_EVQ_SIZE) 1664 * sizeof(efx_qword_t) / EFX_BUF_SIZE); 1665 vi_count = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES); 1666 1667 #ifdef CONFIG_SFC_SRIOV 1668 if (efx_sriov_wanted(efx)) { 1669 unsigned vi_dc_entries, buftbl_free, entries_per_vf, vf_limit; 1670 1671 efx->vf_buftbl_base = buftbl_min; 1672 1673 vi_dc_entries = RX_DC_ENTRIES + TX_DC_ENTRIES; 1674 vi_count = max(vi_count, EFX_VI_BASE); 1675 buftbl_free = (sram_lim_qw - buftbl_min - 1676 vi_count * vi_dc_entries); 1677 1678 entries_per_vf = ((vi_dc_entries + EFX_VF_BUFTBL_PER_VI) * 1679 efx_vf_size(efx)); 1680 vf_limit = min(buftbl_free / entries_per_vf, 1681 (1024U - EFX_VI_BASE) >> efx->vi_scale); 1682 1683 if (efx->vf_count > vf_limit) { 1684 netif_err(efx, probe, efx->net_dev, 1685 "Reducing VF count from from %d to %d\n", 1686 efx->vf_count, vf_limit); 1687 efx->vf_count = vf_limit; 1688 } 1689 vi_count += efx->vf_count * efx_vf_size(efx); 1690 } 1691 #endif 1692 1693 efx->tx_dc_base = sram_lim_qw - vi_count * TX_DC_ENTRIES; 1694 efx->rx_dc_base = efx->tx_dc_base - vi_count * RX_DC_ENTRIES; 1695 } 1696 1697 u32 efx_nic_fpga_ver(struct efx_nic *efx) 1698 { 1699 efx_oword_t altera_build; 1700 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD); 1701 return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER); 1702 } 1703 1704 void efx_nic_init_common(struct efx_nic *efx) 1705 { 1706 efx_oword_t temp; 1707 1708 /* Set positions of descriptor caches in SRAM. */ 1709 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, efx->tx_dc_base); 1710 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG); 1711 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, efx->rx_dc_base); 1712 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG); 1713 1714 /* Set TX descriptor cache size. */ 1715 BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER)); 1716 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER); 1717 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG); 1718 1719 /* Set RX descriptor cache size. Set low watermark to size-8, as 1720 * this allows most efficient prefetching. 1721 */ 1722 BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER)); 1723 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER); 1724 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG); 1725 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8); 1726 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM); 1727 1728 /* Program INT_KER address */ 1729 EFX_POPULATE_OWORD_2(temp, 1730 FRF_AZ_NORM_INT_VEC_DIS_KER, 1731 EFX_INT_MODE_USE_MSI(efx), 1732 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr); 1733 efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER); 1734 1735 if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx)) 1736 /* Use an interrupt level unused by event queues */ 1737 efx->irq_level = 0x1f; 1738 else 1739 /* Use a valid MSI-X vector */ 1740 efx->irq_level = 0; 1741 1742 /* Enable all the genuinely fatal interrupts. (They are still 1743 * masked by the overall interrupt mask, controlled by 1744 * falcon_interrupts()). 1745 * 1746 * Note: All other fatal interrupts are enabled 1747 */ 1748 EFX_POPULATE_OWORD_3(temp, 1749 FRF_AZ_ILL_ADR_INT_KER_EN, 1, 1750 FRF_AZ_RBUF_OWN_INT_KER_EN, 1, 1751 FRF_AZ_TBUF_OWN_INT_KER_EN, 1); 1752 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) 1753 EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1); 1754 EFX_INVERT_OWORD(temp); 1755 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER); 1756 1757 efx_nic_push_rx_indir_table(efx); 1758 1759 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be 1760 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q. 1761 */ 1762 efx_reado(efx, &temp, FR_AZ_TX_RESERVED); 1763 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe); 1764 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1); 1765 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1); 1766 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 1); 1767 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1); 1768 /* Enable SW_EV to inherit in char driver - assume harmless here */ 1769 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1); 1770 /* Prefetch threshold 2 => fetch when descriptor cache half empty */ 1771 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2); 1772 /* Disable hardware watchdog which can misfire */ 1773 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff); 1774 /* Squash TX of packets of 16 bytes or less */ 1775 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) 1776 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); 1777 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED); 1778 1779 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { 1780 EFX_POPULATE_OWORD_4(temp, 1781 /* Default values */ 1782 FRF_BZ_TX_PACE_SB_NOT_AF, 0x15, 1783 FRF_BZ_TX_PACE_SB_AF, 0xb, 1784 FRF_BZ_TX_PACE_FB_BASE, 0, 1785 /* Allow large pace values in the 1786 * fast bin. */ 1787 FRF_BZ_TX_PACE_BIN_TH, 1788 FFE_BZ_TX_PACE_RESERVED); 1789 efx_writeo(efx, &temp, FR_BZ_TX_PACE); 1790 } 1791 } 1792 1793 /* Register dump */ 1794 1795 #define REGISTER_REVISION_A 1 1796 #define REGISTER_REVISION_B 2 1797 #define REGISTER_REVISION_C 3 1798 #define REGISTER_REVISION_Z 3 /* latest revision */ 1799 1800 struct efx_nic_reg { 1801 u32 offset:24; 1802 u32 min_revision:2, max_revision:2; 1803 }; 1804 1805 #define REGISTER(name, min_rev, max_rev) { \ 1806 FR_ ## min_rev ## max_rev ## _ ## name, \ 1807 REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev \ 1808 } 1809 #define REGISTER_AA(name) REGISTER(name, A, A) 1810 #define REGISTER_AB(name) REGISTER(name, A, B) 1811 #define REGISTER_AZ(name) REGISTER(name, A, Z) 1812 #define REGISTER_BB(name) REGISTER(name, B, B) 1813 #define REGISTER_BZ(name) REGISTER(name, B, Z) 1814 #define REGISTER_CZ(name) REGISTER(name, C, Z) 1815 1816 static const struct efx_nic_reg efx_nic_regs[] = { 1817 REGISTER_AZ(ADR_REGION), 1818 REGISTER_AZ(INT_EN_KER), 1819 REGISTER_BZ(INT_EN_CHAR), 1820 REGISTER_AZ(INT_ADR_KER), 1821 REGISTER_BZ(INT_ADR_CHAR), 1822 /* INT_ACK_KER is WO */ 1823 /* INT_ISR0 is RC */ 1824 REGISTER_AZ(HW_INIT), 1825 REGISTER_CZ(USR_EV_CFG), 1826 REGISTER_AB(EE_SPI_HCMD), 1827 REGISTER_AB(EE_SPI_HADR), 1828 REGISTER_AB(EE_SPI_HDATA), 1829 REGISTER_AB(EE_BASE_PAGE), 1830 REGISTER_AB(EE_VPD_CFG0), 1831 /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */ 1832 /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */ 1833 /* PCIE_CORE_INDIRECT is indirect */ 1834 REGISTER_AB(NIC_STAT), 1835 REGISTER_AB(GPIO_CTL), 1836 REGISTER_AB(GLB_CTL), 1837 /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */ 1838 REGISTER_BZ(DP_CTRL), 1839 REGISTER_AZ(MEM_STAT), 1840 REGISTER_AZ(CS_DEBUG), 1841 REGISTER_AZ(ALTERA_BUILD), 1842 REGISTER_AZ(CSR_SPARE), 1843 REGISTER_AB(PCIE_SD_CTL0123), 1844 REGISTER_AB(PCIE_SD_CTL45), 1845 REGISTER_AB(PCIE_PCS_CTL_STAT), 1846 /* DEBUG_DATA_OUT is not used */ 1847 /* DRV_EV is WO */ 1848 REGISTER_AZ(EVQ_CTL), 1849 REGISTER_AZ(EVQ_CNT1), 1850 REGISTER_AZ(EVQ_CNT2), 1851 REGISTER_AZ(BUF_TBL_CFG), 1852 REGISTER_AZ(SRM_RX_DC_CFG), 1853 REGISTER_AZ(SRM_TX_DC_CFG), 1854 REGISTER_AZ(SRM_CFG), 1855 /* BUF_TBL_UPD is WO */ 1856 REGISTER_AZ(SRM_UPD_EVQ), 1857 REGISTER_AZ(SRAM_PARITY), 1858 REGISTER_AZ(RX_CFG), 1859 REGISTER_BZ(RX_FILTER_CTL), 1860 /* RX_FLUSH_DESCQ is WO */ 1861 REGISTER_AZ(RX_DC_CFG), 1862 REGISTER_AZ(RX_DC_PF_WM), 1863 REGISTER_BZ(RX_RSS_TKEY), 1864 /* RX_NODESC_DROP is RC */ 1865 REGISTER_AA(RX_SELF_RST), 1866 /* RX_DEBUG, RX_PUSH_DROP are not used */ 1867 REGISTER_CZ(RX_RSS_IPV6_REG1), 1868 REGISTER_CZ(RX_RSS_IPV6_REG2), 1869 REGISTER_CZ(RX_RSS_IPV6_REG3), 1870 /* TX_FLUSH_DESCQ is WO */ 1871 REGISTER_AZ(TX_DC_CFG), 1872 REGISTER_AA(TX_CHKSM_CFG), 1873 REGISTER_AZ(TX_CFG), 1874 /* TX_PUSH_DROP is not used */ 1875 REGISTER_AZ(TX_RESERVED), 1876 REGISTER_BZ(TX_PACE), 1877 /* TX_PACE_DROP_QID is RC */ 1878 REGISTER_BB(TX_VLAN), 1879 REGISTER_BZ(TX_IPFIL_PORTEN), 1880 REGISTER_AB(MD_TXD), 1881 REGISTER_AB(MD_RXD), 1882 REGISTER_AB(MD_CS), 1883 REGISTER_AB(MD_PHY_ADR), 1884 REGISTER_AB(MD_ID), 1885 /* MD_STAT is RC */ 1886 REGISTER_AB(MAC_STAT_DMA), 1887 REGISTER_AB(MAC_CTRL), 1888 REGISTER_BB(GEN_MODE), 1889 REGISTER_AB(MAC_MC_HASH_REG0), 1890 REGISTER_AB(MAC_MC_HASH_REG1), 1891 REGISTER_AB(GM_CFG1), 1892 REGISTER_AB(GM_CFG2), 1893 /* GM_IPG and GM_HD are not used */ 1894 REGISTER_AB(GM_MAX_FLEN), 1895 /* GM_TEST is not used */ 1896 REGISTER_AB(GM_ADR1), 1897 REGISTER_AB(GM_ADR2), 1898 REGISTER_AB(GMF_CFG0), 1899 REGISTER_AB(GMF_CFG1), 1900 REGISTER_AB(GMF_CFG2), 1901 REGISTER_AB(GMF_CFG3), 1902 REGISTER_AB(GMF_CFG4), 1903 REGISTER_AB(GMF_CFG5), 1904 REGISTER_BB(TX_SRC_MAC_CTL), 1905 REGISTER_AB(XM_ADR_LO), 1906 REGISTER_AB(XM_ADR_HI), 1907 REGISTER_AB(XM_GLB_CFG), 1908 REGISTER_AB(XM_TX_CFG), 1909 REGISTER_AB(XM_RX_CFG), 1910 REGISTER_AB(XM_MGT_INT_MASK), 1911 REGISTER_AB(XM_FC), 1912 REGISTER_AB(XM_PAUSE_TIME), 1913 REGISTER_AB(XM_TX_PARAM), 1914 REGISTER_AB(XM_RX_PARAM), 1915 /* XM_MGT_INT_MSK (note no 'A') is RC */ 1916 REGISTER_AB(XX_PWR_RST), 1917 REGISTER_AB(XX_SD_CTL), 1918 REGISTER_AB(XX_TXDRV_CTL), 1919 /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */ 1920 /* XX_CORE_STAT is partly RC */ 1921 }; 1922 1923 struct efx_nic_reg_table { 1924 u32 offset:24; 1925 u32 min_revision:2, max_revision:2; 1926 u32 step:6, rows:21; 1927 }; 1928 1929 #define REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) { \ 1930 offset, \ 1931 REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev, \ 1932 step, rows \ 1933 } 1934 #define REGISTER_TABLE(name, min_rev, max_rev) \ 1935 REGISTER_TABLE_DIMENSIONS( \ 1936 name, FR_ ## min_rev ## max_rev ## _ ## name, \ 1937 min_rev, max_rev, \ 1938 FR_ ## min_rev ## max_rev ## _ ## name ## _STEP, \ 1939 FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS) 1940 #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A) 1941 #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z) 1942 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B) 1943 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z) 1944 #define REGISTER_TABLE_BB_CZ(name) \ 1945 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B, \ 1946 FR_BZ_ ## name ## _STEP, \ 1947 FR_BB_ ## name ## _ROWS), \ 1948 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z, \ 1949 FR_BZ_ ## name ## _STEP, \ 1950 FR_CZ_ ## name ## _ROWS) 1951 #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z) 1952 1953 static const struct efx_nic_reg_table efx_nic_reg_tables[] = { 1954 /* DRIVER is not used */ 1955 /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */ 1956 REGISTER_TABLE_BB(TX_IPFIL_TBL), 1957 REGISTER_TABLE_BB(TX_SRC_MAC_TBL), 1958 REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER), 1959 REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL), 1960 REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER), 1961 REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL), 1962 REGISTER_TABLE_AA(EVQ_PTR_TBL_KER), 1963 REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL), 1964 /* We can't reasonably read all of the buffer table (up to 8MB!). 1965 * However this driver will only use a few entries. Reading 1966 * 1K entries allows for some expansion of queue count and 1967 * size before we need to change the version. */ 1968 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER, 1969 A, A, 8, 1024), 1970 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL, 1971 B, Z, 8, 1024), 1972 REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0), 1973 REGISTER_TABLE_BB_CZ(TIMER_TBL), 1974 REGISTER_TABLE_BB_CZ(TX_PACE_TBL), 1975 REGISTER_TABLE_BZ(RX_INDIRECTION_TBL), 1976 /* TX_FILTER_TBL0 is huge and not used by this driver */ 1977 REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0), 1978 REGISTER_TABLE_CZ(MC_TREG_SMEM), 1979 /* MSIX_PBA_TABLE is not mapped */ 1980 /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */ 1981 REGISTER_TABLE_BZ(RX_FILTER_TBL0), 1982 }; 1983 1984 size_t efx_nic_get_regs_len(struct efx_nic *efx) 1985 { 1986 const struct efx_nic_reg *reg; 1987 const struct efx_nic_reg_table *table; 1988 size_t len = 0; 1989 1990 for (reg = efx_nic_regs; 1991 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs); 1992 reg++) 1993 if (efx->type->revision >= reg->min_revision && 1994 efx->type->revision <= reg->max_revision) 1995 len += sizeof(efx_oword_t); 1996 1997 for (table = efx_nic_reg_tables; 1998 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables); 1999 table++) 2000 if (efx->type->revision >= table->min_revision && 2001 efx->type->revision <= table->max_revision) 2002 len += table->rows * min_t(size_t, table->step, 16); 2003 2004 return len; 2005 } 2006 2007 void efx_nic_get_regs(struct efx_nic *efx, void *buf) 2008 { 2009 const struct efx_nic_reg *reg; 2010 const struct efx_nic_reg_table *table; 2011 2012 for (reg = efx_nic_regs; 2013 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs); 2014 reg++) { 2015 if (efx->type->revision >= reg->min_revision && 2016 efx->type->revision <= reg->max_revision) { 2017 efx_reado(efx, (efx_oword_t *)buf, reg->offset); 2018 buf += sizeof(efx_oword_t); 2019 } 2020 } 2021 2022 for (table = efx_nic_reg_tables; 2023 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables); 2024 table++) { 2025 size_t size, i; 2026 2027 if (!(efx->type->revision >= table->min_revision && 2028 efx->type->revision <= table->max_revision)) 2029 continue; 2030 2031 size = min_t(size_t, table->step, 16); 2032 2033 for (i = 0; i < table->rows; i++) { 2034 switch (table->step) { 2035 case 4: /* 32-bit SRAM */ 2036 efx_readd(efx, buf, table->offset + 4 * i); 2037 break; 2038 case 8: /* 64-bit SRAM */ 2039 efx_sram_readq(efx, 2040 efx->membase + table->offset, 2041 buf, i); 2042 break; 2043 case 16: /* 128-bit-readable register */ 2044 efx_reado_table(efx, buf, table->offset, i); 2045 break; 2046 case 32: /* 128-bit register, interleaved */ 2047 efx_reado_table(efx, buf, table->offset, 2 * i); 2048 break; 2049 default: 2050 WARN_ON(1); 2051 return; 2052 } 2053 buf += size; 2054 } 2055 } 2056 } 2057