1 /**************************************************************************** 2 * Driver for Solarflare Solarstorm network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2006-2011 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/delay.h> 13 #include <linux/interrupt.h> 14 #include <linux/pci.h> 15 #include <linux/module.h> 16 #include <linux/seq_file.h> 17 #include "net_driver.h" 18 #include "bitfield.h" 19 #include "efx.h" 20 #include "nic.h" 21 #include "regs.h" 22 #include "io.h" 23 #include "workarounds.h" 24 25 /************************************************************************** 26 * 27 * Configurable values 28 * 29 ************************************************************************** 30 */ 31 32 /* This is set to 16 for a good reason. In summary, if larger than 33 * 16, the descriptor cache holds more than a default socket 34 * buffer's worth of packets (for UDP we can only have at most one 35 * socket buffer's worth outstanding). This combined with the fact 36 * that we only get 1 TX event per descriptor cache means the NIC 37 * goes idle. 38 */ 39 #define TX_DC_ENTRIES 16 40 #define TX_DC_ENTRIES_ORDER 1 41 42 #define RX_DC_ENTRIES 64 43 #define RX_DC_ENTRIES_ORDER 3 44 45 /* If EFX_MAX_INT_ERRORS internal errors occur within 46 * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and 47 * disable it. 48 */ 49 #define EFX_INT_ERROR_EXPIRE 3600 50 #define EFX_MAX_INT_ERRORS 5 51 52 /* Depth of RX flush request fifo */ 53 #define EFX_RX_FLUSH_COUNT 4 54 55 /* Driver generated events */ 56 #define _EFX_CHANNEL_MAGIC_TEST 0x000101 57 #define _EFX_CHANNEL_MAGIC_FILL 0x000102 58 #define _EFX_CHANNEL_MAGIC_RX_DRAIN 0x000103 59 #define _EFX_CHANNEL_MAGIC_TX_DRAIN 0x000104 60 61 #define _EFX_CHANNEL_MAGIC(_code, _data) ((_code) << 8 | (_data)) 62 #define _EFX_CHANNEL_MAGIC_CODE(_magic) ((_magic) >> 8) 63 64 #define EFX_CHANNEL_MAGIC_TEST(_channel) \ 65 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TEST, (_channel)->channel) 66 #define EFX_CHANNEL_MAGIC_FILL(_rx_queue) \ 67 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_FILL, \ 68 efx_rx_queue_index(_rx_queue)) 69 #define EFX_CHANNEL_MAGIC_RX_DRAIN(_rx_queue) \ 70 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_RX_DRAIN, \ 71 efx_rx_queue_index(_rx_queue)) 72 #define EFX_CHANNEL_MAGIC_TX_DRAIN(_tx_queue) \ 73 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TX_DRAIN, \ 74 (_tx_queue)->queue) 75 76 /************************************************************************** 77 * 78 * Solarstorm hardware access 79 * 80 **************************************************************************/ 81 82 static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value, 83 unsigned int index) 84 { 85 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base, 86 value, index); 87 } 88 89 /* Read the current event from the event queue */ 90 static inline efx_qword_t *efx_event(struct efx_channel *channel, 91 unsigned int index) 92 { 93 return ((efx_qword_t *) (channel->eventq.addr)) + 94 (index & channel->eventq_mask); 95 } 96 97 /* See if an event is present 98 * 99 * We check both the high and low dword of the event for all ones. We 100 * wrote all ones when we cleared the event, and no valid event can 101 * have all ones in either its high or low dwords. This approach is 102 * robust against reordering. 103 * 104 * Note that using a single 64-bit comparison is incorrect; even 105 * though the CPU read will be atomic, the DMA write may not be. 106 */ 107 static inline int efx_event_present(efx_qword_t *event) 108 { 109 return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | 110 EFX_DWORD_IS_ALL_ONES(event->dword[1])); 111 } 112 113 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b, 114 const efx_oword_t *mask) 115 { 116 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) || 117 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]); 118 } 119 120 int efx_nic_test_registers(struct efx_nic *efx, 121 const struct efx_nic_register_test *regs, 122 size_t n_regs) 123 { 124 unsigned address = 0, i, j; 125 efx_oword_t mask, imask, original, reg, buf; 126 127 /* Falcon should be in loopback to isolate the XMAC from the PHY */ 128 WARN_ON(!LOOPBACK_INTERNAL(efx)); 129 130 for (i = 0; i < n_regs; ++i) { 131 address = regs[i].address; 132 mask = imask = regs[i].mask; 133 EFX_INVERT_OWORD(imask); 134 135 efx_reado(efx, &original, address); 136 137 /* bit sweep on and off */ 138 for (j = 0; j < 128; j++) { 139 if (!EFX_EXTRACT_OWORD32(mask, j, j)) 140 continue; 141 142 /* Test this testable bit can be set in isolation */ 143 EFX_AND_OWORD(reg, original, mask); 144 EFX_SET_OWORD32(reg, j, j, 1); 145 146 efx_writeo(efx, ®, address); 147 efx_reado(efx, &buf, address); 148 149 if (efx_masked_compare_oword(®, &buf, &mask)) 150 goto fail; 151 152 /* Test this testable bit can be cleared in isolation */ 153 EFX_OR_OWORD(reg, original, mask); 154 EFX_SET_OWORD32(reg, j, j, 0); 155 156 efx_writeo(efx, ®, address); 157 efx_reado(efx, &buf, address); 158 159 if (efx_masked_compare_oword(®, &buf, &mask)) 160 goto fail; 161 } 162 163 efx_writeo(efx, &original, address); 164 } 165 166 return 0; 167 168 fail: 169 netif_err(efx, hw, efx->net_dev, 170 "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT 171 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg), 172 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask)); 173 return -EIO; 174 } 175 176 /************************************************************************** 177 * 178 * Special buffer handling 179 * Special buffers are used for event queues and the TX and RX 180 * descriptor rings. 181 * 182 *************************************************************************/ 183 184 /* 185 * Initialise a special buffer 186 * 187 * This will define a buffer (previously allocated via 188 * efx_alloc_special_buffer()) in the buffer table, allowing 189 * it to be used for event queues, descriptor rings etc. 190 */ 191 static void 192 efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer) 193 { 194 efx_qword_t buf_desc; 195 int index; 196 dma_addr_t dma_addr; 197 int i; 198 199 EFX_BUG_ON_PARANOID(!buffer->addr); 200 201 /* Write buffer descriptors to NIC */ 202 for (i = 0; i < buffer->entries; i++) { 203 index = buffer->index + i; 204 dma_addr = buffer->dma_addr + (i * EFX_BUF_SIZE); 205 netif_dbg(efx, probe, efx->net_dev, 206 "mapping special buffer %d at %llx\n", 207 index, (unsigned long long)dma_addr); 208 EFX_POPULATE_QWORD_3(buf_desc, 209 FRF_AZ_BUF_ADR_REGION, 0, 210 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12, 211 FRF_AZ_BUF_OWNER_ID_FBUF, 0); 212 efx_write_buf_tbl(efx, &buf_desc, index); 213 } 214 } 215 216 /* Unmaps a buffer and clears the buffer table entries */ 217 static void 218 efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer) 219 { 220 efx_oword_t buf_tbl_upd; 221 unsigned int start = buffer->index; 222 unsigned int end = (buffer->index + buffer->entries - 1); 223 224 if (!buffer->entries) 225 return; 226 227 netif_dbg(efx, hw, efx->net_dev, "unmapping special buffers %d-%d\n", 228 buffer->index, buffer->index + buffer->entries - 1); 229 230 EFX_POPULATE_OWORD_4(buf_tbl_upd, 231 FRF_AZ_BUF_UPD_CMD, 0, 232 FRF_AZ_BUF_CLR_CMD, 1, 233 FRF_AZ_BUF_CLR_END_ID, end, 234 FRF_AZ_BUF_CLR_START_ID, start); 235 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD); 236 } 237 238 /* 239 * Allocate a new special buffer 240 * 241 * This allocates memory for a new buffer, clears it and allocates a 242 * new buffer ID range. It does not write into the buffer table. 243 * 244 * This call will allocate 4KB buffers, since 8KB buffers can't be 245 * used for event queues and descriptor rings. 246 */ 247 static int efx_alloc_special_buffer(struct efx_nic *efx, 248 struct efx_special_buffer *buffer, 249 unsigned int len) 250 { 251 len = ALIGN(len, EFX_BUF_SIZE); 252 253 buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len, 254 &buffer->dma_addr, GFP_KERNEL); 255 if (!buffer->addr) 256 return -ENOMEM; 257 buffer->len = len; 258 buffer->entries = len / EFX_BUF_SIZE; 259 BUG_ON(buffer->dma_addr & (EFX_BUF_SIZE - 1)); 260 261 /* All zeros is a potentially valid event so memset to 0xff */ 262 memset(buffer->addr, 0xff, len); 263 264 /* Select new buffer ID */ 265 buffer->index = efx->next_buffer_table; 266 efx->next_buffer_table += buffer->entries; 267 268 netif_dbg(efx, probe, efx->net_dev, 269 "allocating special buffers %d-%d at %llx+%x " 270 "(virt %p phys %llx)\n", buffer->index, 271 buffer->index + buffer->entries - 1, 272 (u64)buffer->dma_addr, len, 273 buffer->addr, (u64)virt_to_phys(buffer->addr)); 274 275 return 0; 276 } 277 278 static void 279 efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer) 280 { 281 if (!buffer->addr) 282 return; 283 284 netif_dbg(efx, hw, efx->net_dev, 285 "deallocating special buffers %d-%d at %llx+%x " 286 "(virt %p phys %llx)\n", buffer->index, 287 buffer->index + buffer->entries - 1, 288 (u64)buffer->dma_addr, buffer->len, 289 buffer->addr, (u64)virt_to_phys(buffer->addr)); 290 291 dma_free_coherent(&efx->pci_dev->dev, buffer->len, buffer->addr, 292 buffer->dma_addr); 293 buffer->addr = NULL; 294 buffer->entries = 0; 295 } 296 297 /************************************************************************** 298 * 299 * Generic buffer handling 300 * These buffers are used for interrupt status and MAC stats 301 * 302 **************************************************************************/ 303 304 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, 305 unsigned int len) 306 { 307 buffer->addr = pci_alloc_consistent(efx->pci_dev, len, 308 &buffer->dma_addr); 309 if (!buffer->addr) 310 return -ENOMEM; 311 buffer->len = len; 312 memset(buffer->addr, 0, len); 313 return 0; 314 } 315 316 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer) 317 { 318 if (buffer->addr) { 319 pci_free_consistent(efx->pci_dev, buffer->len, 320 buffer->addr, buffer->dma_addr); 321 buffer->addr = NULL; 322 } 323 } 324 325 /************************************************************************** 326 * 327 * TX path 328 * 329 **************************************************************************/ 330 331 /* Returns a pointer to the specified transmit descriptor in the TX 332 * descriptor queue belonging to the specified channel. 333 */ 334 static inline efx_qword_t * 335 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index) 336 { 337 return ((efx_qword_t *) (tx_queue->txd.addr)) + index; 338 } 339 340 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 341 static inline void efx_notify_tx_desc(struct efx_tx_queue *tx_queue) 342 { 343 unsigned write_ptr; 344 efx_dword_t reg; 345 346 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 347 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr); 348 efx_writed_page(tx_queue->efx, ®, 349 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue); 350 } 351 352 /* Write pointer and first descriptor for TX descriptor ring */ 353 static inline void efx_push_tx_desc(struct efx_tx_queue *tx_queue, 354 const efx_qword_t *txd) 355 { 356 unsigned write_ptr; 357 efx_oword_t reg; 358 359 BUILD_BUG_ON(FRF_AZ_TX_DESC_LBN != 0); 360 BUILD_BUG_ON(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0); 361 362 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 363 EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true, 364 FRF_AZ_TX_DESC_WPTR, write_ptr); 365 reg.qword[0] = *txd; 366 efx_writeo_page(tx_queue->efx, ®, 367 FR_BZ_TX_DESC_UPD_P0, tx_queue->queue); 368 } 369 370 static inline bool 371 efx_may_push_tx_desc(struct efx_tx_queue *tx_queue, unsigned int write_count) 372 { 373 unsigned empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count); 374 375 if (empty_read_count == 0) 376 return false; 377 378 tx_queue->empty_read_count = 0; 379 return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0; 380 } 381 382 /* For each entry inserted into the software descriptor ring, create a 383 * descriptor in the hardware TX descriptor ring (in host memory), and 384 * write a doorbell. 385 */ 386 void efx_nic_push_buffers(struct efx_tx_queue *tx_queue) 387 { 388 389 struct efx_tx_buffer *buffer; 390 efx_qword_t *txd; 391 unsigned write_ptr; 392 unsigned old_write_count = tx_queue->write_count; 393 394 BUG_ON(tx_queue->write_count == tx_queue->insert_count); 395 396 do { 397 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 398 buffer = &tx_queue->buffer[write_ptr]; 399 txd = efx_tx_desc(tx_queue, write_ptr); 400 ++tx_queue->write_count; 401 402 /* Create TX descriptor ring entry */ 403 EFX_POPULATE_QWORD_4(*txd, 404 FSF_AZ_TX_KER_CONT, buffer->continuation, 405 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len, 406 FSF_AZ_TX_KER_BUF_REGION, 0, 407 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr); 408 } while (tx_queue->write_count != tx_queue->insert_count); 409 410 wmb(); /* Ensure descriptors are written before they are fetched */ 411 412 if (efx_may_push_tx_desc(tx_queue, old_write_count)) { 413 txd = efx_tx_desc(tx_queue, 414 old_write_count & tx_queue->ptr_mask); 415 efx_push_tx_desc(tx_queue, txd); 416 ++tx_queue->pushes; 417 } else { 418 efx_notify_tx_desc(tx_queue); 419 } 420 } 421 422 /* Allocate hardware resources for a TX queue */ 423 int efx_nic_probe_tx(struct efx_tx_queue *tx_queue) 424 { 425 struct efx_nic *efx = tx_queue->efx; 426 unsigned entries; 427 428 entries = tx_queue->ptr_mask + 1; 429 return efx_alloc_special_buffer(efx, &tx_queue->txd, 430 entries * sizeof(efx_qword_t)); 431 } 432 433 void efx_nic_init_tx(struct efx_tx_queue *tx_queue) 434 { 435 struct efx_nic *efx = tx_queue->efx; 436 efx_oword_t reg; 437 438 /* Pin TX descriptor ring */ 439 efx_init_special_buffer(efx, &tx_queue->txd); 440 441 /* Push TX descriptor ring to card */ 442 EFX_POPULATE_OWORD_10(reg, 443 FRF_AZ_TX_DESCQ_EN, 1, 444 FRF_AZ_TX_ISCSI_DDIG_EN, 0, 445 FRF_AZ_TX_ISCSI_HDIG_EN, 0, 446 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index, 447 FRF_AZ_TX_DESCQ_EVQ_ID, 448 tx_queue->channel->channel, 449 FRF_AZ_TX_DESCQ_OWNER_ID, 0, 450 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue, 451 FRF_AZ_TX_DESCQ_SIZE, 452 __ffs(tx_queue->txd.entries), 453 FRF_AZ_TX_DESCQ_TYPE, 0, 454 FRF_BZ_TX_NON_IP_DROP_DIS, 1); 455 456 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { 457 int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; 458 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum); 459 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS, 460 !csum); 461 } 462 463 efx_writeo_table(efx, ®, efx->type->txd_ptr_tbl_base, 464 tx_queue->queue); 465 466 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) { 467 /* Only 128 bits in this register */ 468 BUILD_BUG_ON(EFX_MAX_TX_QUEUES > 128); 469 470 efx_reado(efx, ®, FR_AA_TX_CHKSM_CFG); 471 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) 472 clear_bit_le(tx_queue->queue, (void *)®); 473 else 474 set_bit_le(tx_queue->queue, (void *)®); 475 efx_writeo(efx, ®, FR_AA_TX_CHKSM_CFG); 476 } 477 478 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { 479 EFX_POPULATE_OWORD_1(reg, 480 FRF_BZ_TX_PACE, 481 (tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ? 482 FFE_BZ_TX_PACE_OFF : 483 FFE_BZ_TX_PACE_RESERVED); 484 efx_writeo_table(efx, ®, FR_BZ_TX_PACE_TBL, 485 tx_queue->queue); 486 } 487 } 488 489 static void efx_flush_tx_queue(struct efx_tx_queue *tx_queue) 490 { 491 struct efx_nic *efx = tx_queue->efx; 492 efx_oword_t tx_flush_descq; 493 494 EFX_POPULATE_OWORD_2(tx_flush_descq, 495 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1, 496 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue); 497 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ); 498 } 499 500 void efx_nic_fini_tx(struct efx_tx_queue *tx_queue) 501 { 502 struct efx_nic *efx = tx_queue->efx; 503 efx_oword_t tx_desc_ptr; 504 505 /* Remove TX descriptor ring from card */ 506 EFX_ZERO_OWORD(tx_desc_ptr); 507 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, 508 tx_queue->queue); 509 510 /* Unpin TX descriptor ring */ 511 efx_fini_special_buffer(efx, &tx_queue->txd); 512 } 513 514 /* Free buffers backing TX queue */ 515 void efx_nic_remove_tx(struct efx_tx_queue *tx_queue) 516 { 517 efx_free_special_buffer(tx_queue->efx, &tx_queue->txd); 518 } 519 520 /************************************************************************** 521 * 522 * RX path 523 * 524 **************************************************************************/ 525 526 /* Returns a pointer to the specified descriptor in the RX descriptor queue */ 527 static inline efx_qword_t * 528 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 529 { 530 return ((efx_qword_t *) (rx_queue->rxd.addr)) + index; 531 } 532 533 /* This creates an entry in the RX descriptor queue */ 534 static inline void 535 efx_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index) 536 { 537 struct efx_rx_buffer *rx_buf; 538 efx_qword_t *rxd; 539 540 rxd = efx_rx_desc(rx_queue, index); 541 rx_buf = efx_rx_buffer(rx_queue, index); 542 EFX_POPULATE_QWORD_3(*rxd, 543 FSF_AZ_RX_KER_BUF_SIZE, 544 rx_buf->len - 545 rx_queue->efx->type->rx_buffer_padding, 546 FSF_AZ_RX_KER_BUF_REGION, 0, 547 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 548 } 549 550 /* This writes to the RX_DESC_WPTR register for the specified receive 551 * descriptor ring. 552 */ 553 void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue) 554 { 555 struct efx_nic *efx = rx_queue->efx; 556 efx_dword_t reg; 557 unsigned write_ptr; 558 559 while (rx_queue->notified_count != rx_queue->added_count) { 560 efx_build_rx_desc( 561 rx_queue, 562 rx_queue->notified_count & rx_queue->ptr_mask); 563 ++rx_queue->notified_count; 564 } 565 566 wmb(); 567 write_ptr = rx_queue->added_count & rx_queue->ptr_mask; 568 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr); 569 efx_writed_page(efx, ®, FR_AZ_RX_DESC_UPD_DWORD_P0, 570 efx_rx_queue_index(rx_queue)); 571 } 572 573 int efx_nic_probe_rx(struct efx_rx_queue *rx_queue) 574 { 575 struct efx_nic *efx = rx_queue->efx; 576 unsigned entries; 577 578 entries = rx_queue->ptr_mask + 1; 579 return efx_alloc_special_buffer(efx, &rx_queue->rxd, 580 entries * sizeof(efx_qword_t)); 581 } 582 583 void efx_nic_init_rx(struct efx_rx_queue *rx_queue) 584 { 585 efx_oword_t rx_desc_ptr; 586 struct efx_nic *efx = rx_queue->efx; 587 bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0; 588 bool iscsi_digest_en = is_b0; 589 590 netif_dbg(efx, hw, efx->net_dev, 591 "RX queue %d ring in special buffers %d-%d\n", 592 efx_rx_queue_index(rx_queue), rx_queue->rxd.index, 593 rx_queue->rxd.index + rx_queue->rxd.entries - 1); 594 595 /* Pin RX descriptor ring */ 596 efx_init_special_buffer(efx, &rx_queue->rxd); 597 598 /* Push RX descriptor ring to card */ 599 EFX_POPULATE_OWORD_10(rx_desc_ptr, 600 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en, 601 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en, 602 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index, 603 FRF_AZ_RX_DESCQ_EVQ_ID, 604 efx_rx_queue_channel(rx_queue)->channel, 605 FRF_AZ_RX_DESCQ_OWNER_ID, 0, 606 FRF_AZ_RX_DESCQ_LABEL, 607 efx_rx_queue_index(rx_queue), 608 FRF_AZ_RX_DESCQ_SIZE, 609 __ffs(rx_queue->rxd.entries), 610 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ , 611 /* For >=B0 this is scatter so disable */ 612 FRF_AZ_RX_DESCQ_JUMBO, !is_b0, 613 FRF_AZ_RX_DESCQ_EN, 1); 614 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, 615 efx_rx_queue_index(rx_queue)); 616 } 617 618 static void efx_flush_rx_queue(struct efx_rx_queue *rx_queue) 619 { 620 struct efx_nic *efx = rx_queue->efx; 621 efx_oword_t rx_flush_descq; 622 623 EFX_POPULATE_OWORD_2(rx_flush_descq, 624 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1, 625 FRF_AZ_RX_FLUSH_DESCQ, 626 efx_rx_queue_index(rx_queue)); 627 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ); 628 } 629 630 void efx_nic_fini_rx(struct efx_rx_queue *rx_queue) 631 { 632 efx_oword_t rx_desc_ptr; 633 struct efx_nic *efx = rx_queue->efx; 634 635 /* Remove RX descriptor ring from card */ 636 EFX_ZERO_OWORD(rx_desc_ptr); 637 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, 638 efx_rx_queue_index(rx_queue)); 639 640 /* Unpin RX descriptor ring */ 641 efx_fini_special_buffer(efx, &rx_queue->rxd); 642 } 643 644 /* Free buffers backing RX queue */ 645 void efx_nic_remove_rx(struct efx_rx_queue *rx_queue) 646 { 647 efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd); 648 } 649 650 /************************************************************************** 651 * 652 * Flush handling 653 * 654 **************************************************************************/ 655 656 /* efx_nic_flush_queues() must be woken up when all flushes are completed, 657 * or more RX flushes can be kicked off. 658 */ 659 static bool efx_flush_wake(struct efx_nic *efx) 660 { 661 /* Ensure that all updates are visible to efx_nic_flush_queues() */ 662 smp_mb(); 663 664 return (atomic_read(&efx->drain_pending) == 0 || 665 (atomic_read(&efx->rxq_flush_outstanding) < EFX_RX_FLUSH_COUNT 666 && atomic_read(&efx->rxq_flush_pending) > 0)); 667 } 668 669 /* Flush all the transmit queues, and continue flushing receive queues until 670 * they're all flushed. Wait for the DRAIN events to be recieved so that there 671 * are no more RX and TX events left on any channel. */ 672 int efx_nic_flush_queues(struct efx_nic *efx) 673 { 674 unsigned timeout = msecs_to_jiffies(5000); /* 5s for all flushes and drains */ 675 struct efx_channel *channel; 676 struct efx_rx_queue *rx_queue; 677 struct efx_tx_queue *tx_queue; 678 int rc = 0; 679 680 efx->type->prepare_flush(efx); 681 682 efx_for_each_channel(channel, efx) { 683 efx_for_each_channel_tx_queue(tx_queue, channel) { 684 atomic_inc(&efx->drain_pending); 685 efx_flush_tx_queue(tx_queue); 686 } 687 efx_for_each_channel_rx_queue(rx_queue, channel) { 688 atomic_inc(&efx->drain_pending); 689 rx_queue->flush_pending = true; 690 atomic_inc(&efx->rxq_flush_pending); 691 } 692 } 693 694 while (timeout && atomic_read(&efx->drain_pending) > 0) { 695 /* The hardware supports four concurrent rx flushes, each of 696 * which may need to be retried if there is an outstanding 697 * descriptor fetch 698 */ 699 efx_for_each_channel(channel, efx) { 700 efx_for_each_channel_rx_queue(rx_queue, channel) { 701 if (atomic_read(&efx->rxq_flush_outstanding) >= 702 EFX_RX_FLUSH_COUNT) 703 break; 704 705 if (rx_queue->flush_pending) { 706 rx_queue->flush_pending = false; 707 atomic_dec(&efx->rxq_flush_pending); 708 atomic_inc(&efx->rxq_flush_outstanding); 709 efx_flush_rx_queue(rx_queue); 710 } 711 } 712 } 713 714 timeout = wait_event_timeout(efx->flush_wq, efx_flush_wake(efx), 715 timeout); 716 } 717 718 if (atomic_read(&efx->drain_pending)) { 719 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues " 720 "(rx %d+%d)\n", atomic_read(&efx->drain_pending), 721 atomic_read(&efx->rxq_flush_outstanding), 722 atomic_read(&efx->rxq_flush_pending)); 723 rc = -ETIMEDOUT; 724 725 atomic_set(&efx->drain_pending, 0); 726 atomic_set(&efx->rxq_flush_pending, 0); 727 atomic_set(&efx->rxq_flush_outstanding, 0); 728 } 729 730 return rc; 731 } 732 733 /************************************************************************** 734 * 735 * Event queue processing 736 * Event queues are processed by per-channel tasklets. 737 * 738 **************************************************************************/ 739 740 /* Update a channel's event queue's read pointer (RPTR) register 741 * 742 * This writes the EVQ_RPTR_REG register for the specified channel's 743 * event queue. 744 */ 745 void efx_nic_eventq_read_ack(struct efx_channel *channel) 746 { 747 efx_dword_t reg; 748 struct efx_nic *efx = channel->efx; 749 750 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, 751 channel->eventq_read_ptr & channel->eventq_mask); 752 efx_writed_table(efx, ®, efx->type->evq_rptr_tbl_base, 753 channel->channel); 754 } 755 756 /* Use HW to insert a SW defined event */ 757 static void efx_generate_event(struct efx_channel *channel, efx_qword_t *event) 758 { 759 efx_oword_t drv_ev_reg; 760 761 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 || 762 FRF_AZ_DRV_EV_DATA_WIDTH != 64); 763 drv_ev_reg.u32[0] = event->u32[0]; 764 drv_ev_reg.u32[1] = event->u32[1]; 765 drv_ev_reg.u32[2] = 0; 766 drv_ev_reg.u32[3] = 0; 767 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel); 768 efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV); 769 } 770 771 static void efx_magic_event(struct efx_channel *channel, u32 magic) 772 { 773 efx_qword_t event; 774 775 EFX_POPULATE_QWORD_2(event, FSF_AZ_EV_CODE, 776 FSE_AZ_EV_CODE_DRV_GEN_EV, 777 FSF_AZ_DRV_GEN_EV_MAGIC, magic); 778 efx_generate_event(channel, &event); 779 } 780 781 /* Handle a transmit completion event 782 * 783 * The NIC batches TX completion events; the message we receive is of 784 * the form "complete all TX events up to this index". 785 */ 786 static int 787 efx_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 788 { 789 unsigned int tx_ev_desc_ptr; 790 unsigned int tx_ev_q_label; 791 struct efx_tx_queue *tx_queue; 792 struct efx_nic *efx = channel->efx; 793 int tx_packets = 0; 794 795 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 796 return 0; 797 798 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) { 799 /* Transmit completion */ 800 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR); 801 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); 802 tx_queue = efx_channel_get_tx_queue( 803 channel, tx_ev_q_label % EFX_TXQ_TYPES); 804 tx_packets = ((tx_ev_desc_ptr - tx_queue->read_count) & 805 tx_queue->ptr_mask); 806 channel->irq_mod_score += tx_packets; 807 efx_xmit_done(tx_queue, tx_ev_desc_ptr); 808 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) { 809 /* Rewrite the FIFO write pointer */ 810 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); 811 tx_queue = efx_channel_get_tx_queue( 812 channel, tx_ev_q_label % EFX_TXQ_TYPES); 813 814 netif_tx_lock(efx->net_dev); 815 efx_notify_tx_desc(tx_queue); 816 netif_tx_unlock(efx->net_dev); 817 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) && 818 EFX_WORKAROUND_10727(efx)) { 819 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); 820 } else { 821 netif_err(efx, tx_err, efx->net_dev, 822 "channel %d unexpected TX event " 823 EFX_QWORD_FMT"\n", channel->channel, 824 EFX_QWORD_VAL(*event)); 825 } 826 827 return tx_packets; 828 } 829 830 /* Detect errors included in the rx_evt_pkt_ok bit. */ 831 static u16 efx_handle_rx_not_ok(struct efx_rx_queue *rx_queue, 832 const efx_qword_t *event) 833 { 834 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 835 struct efx_nic *efx = rx_queue->efx; 836 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err; 837 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err; 838 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc; 839 bool rx_ev_other_err, rx_ev_pause_frm; 840 bool rx_ev_hdr_type, rx_ev_mcast_pkt; 841 unsigned rx_ev_pkt_type; 842 843 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); 844 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); 845 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC); 846 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE); 847 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event, 848 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR); 849 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event, 850 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR); 851 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event, 852 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR); 853 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR); 854 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC); 855 rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ? 856 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB)); 857 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR); 858 859 /* Every error apart from tobe_disc and pause_frm */ 860 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err | 861 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err | 862 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err); 863 864 /* Count errors that are not in MAC stats. Ignore expected 865 * checksum errors during self-test. */ 866 if (rx_ev_frm_trunc) 867 ++channel->n_rx_frm_trunc; 868 else if (rx_ev_tobe_disc) 869 ++channel->n_rx_tobe_disc; 870 else if (!efx->loopback_selftest) { 871 if (rx_ev_ip_hdr_chksum_err) 872 ++channel->n_rx_ip_hdr_chksum_err; 873 else if (rx_ev_tcp_udp_chksum_err) 874 ++channel->n_rx_tcp_udp_chksum_err; 875 } 876 877 /* TOBE_DISC is expected on unicast mismatches; don't print out an 878 * error message. FRM_TRUNC indicates RXDP dropped the packet due 879 * to a FIFO overflow. 880 */ 881 #ifdef DEBUG 882 if (rx_ev_other_err && net_ratelimit()) { 883 netif_dbg(efx, rx_err, efx->net_dev, 884 " RX queue %d unexpected RX event " 885 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n", 886 efx_rx_queue_index(rx_queue), EFX_QWORD_VAL(*event), 887 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "", 888 rx_ev_ip_hdr_chksum_err ? 889 " [IP_HDR_CHKSUM_ERR]" : "", 890 rx_ev_tcp_udp_chksum_err ? 891 " [TCP_UDP_CHKSUM_ERR]" : "", 892 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "", 893 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "", 894 rx_ev_drib_nib ? " [DRIB_NIB]" : "", 895 rx_ev_tobe_disc ? " [TOBE_DISC]" : "", 896 rx_ev_pause_frm ? " [PAUSE]" : ""); 897 } 898 #endif 899 900 /* The frame must be discarded if any of these are true. */ 901 return (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib | 902 rx_ev_tobe_disc | rx_ev_pause_frm) ? 903 EFX_RX_PKT_DISCARD : 0; 904 } 905 906 /* Handle receive events that are not in-order. */ 907 static void 908 efx_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index) 909 { 910 struct efx_nic *efx = rx_queue->efx; 911 unsigned expected, dropped; 912 913 expected = rx_queue->removed_count & rx_queue->ptr_mask; 914 dropped = (index - expected) & rx_queue->ptr_mask; 915 netif_info(efx, rx_err, efx->net_dev, 916 "dropped %d events (index=%d expected=%d)\n", 917 dropped, index, expected); 918 919 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ? 920 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); 921 } 922 923 /* Handle a packet received event 924 * 925 * The NIC gives a "discard" flag if it's a unicast packet with the 926 * wrong destination address 927 * Also "is multicast" and "matches multicast filter" flags can be used to 928 * discard non-matching multicast packets. 929 */ 930 static void 931 efx_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event) 932 { 933 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt; 934 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt; 935 unsigned expected_ptr; 936 bool rx_ev_pkt_ok; 937 u16 flags; 938 struct efx_rx_queue *rx_queue; 939 struct efx_nic *efx = channel->efx; 940 941 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 942 return; 943 944 /* Basic packet information */ 945 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT); 946 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK); 947 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); 948 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT)); 949 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1); 950 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) != 951 channel->channel); 952 953 rx_queue = efx_channel_get_rx_queue(channel); 954 955 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR); 956 expected_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 957 if (unlikely(rx_ev_desc_ptr != expected_ptr)) 958 efx_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr); 959 960 if (likely(rx_ev_pkt_ok)) { 961 /* If packet is marked as OK and packet type is TCP/IP or 962 * UDP/IP, then we can rely on the hardware checksum. 963 */ 964 flags = (rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP || 965 rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP) ? 966 EFX_RX_PKT_CSUMMED : 0; 967 } else { 968 flags = efx_handle_rx_not_ok(rx_queue, event); 969 } 970 971 /* Detect multicast packets that didn't match the filter */ 972 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); 973 if (rx_ev_mcast_pkt) { 974 unsigned int rx_ev_mcast_hash_match = 975 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH); 976 977 if (unlikely(!rx_ev_mcast_hash_match)) { 978 ++channel->n_rx_mcast_mismatch; 979 flags |= EFX_RX_PKT_DISCARD; 980 } 981 } 982 983 channel->irq_mod_score += 2; 984 985 /* Handle received packet */ 986 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt, flags); 987 } 988 989 /* If this flush done event corresponds to a &struct efx_tx_queue, then 990 * send an %EFX_CHANNEL_MAGIC_TX_DRAIN event to drain the event queue 991 * of all transmit completions. 992 */ 993 static void 994 efx_handle_tx_flush_done(struct efx_nic *efx, efx_qword_t *event) 995 { 996 struct efx_tx_queue *tx_queue; 997 int qid; 998 999 qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA); 1000 if (qid < EFX_TXQ_TYPES * efx->n_tx_channels) { 1001 tx_queue = efx_get_tx_queue(efx, qid / EFX_TXQ_TYPES, 1002 qid % EFX_TXQ_TYPES); 1003 1004 efx_magic_event(tx_queue->channel, 1005 EFX_CHANNEL_MAGIC_TX_DRAIN(tx_queue)); 1006 } 1007 } 1008 1009 /* If this flush done event corresponds to a &struct efx_rx_queue: If the flush 1010 * was succesful then send an %EFX_CHANNEL_MAGIC_RX_DRAIN, otherwise add 1011 * the RX queue back to the mask of RX queues in need of flushing. 1012 */ 1013 static void 1014 efx_handle_rx_flush_done(struct efx_nic *efx, efx_qword_t *event) 1015 { 1016 struct efx_channel *channel; 1017 struct efx_rx_queue *rx_queue; 1018 int qid; 1019 bool failed; 1020 1021 qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); 1022 failed = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); 1023 if (qid >= efx->n_channels) 1024 return; 1025 channel = efx_get_channel(efx, qid); 1026 if (!efx_channel_has_rx_queue(channel)) 1027 return; 1028 rx_queue = efx_channel_get_rx_queue(channel); 1029 1030 if (failed) { 1031 netif_info(efx, hw, efx->net_dev, 1032 "RXQ %d flush retry\n", qid); 1033 rx_queue->flush_pending = true; 1034 atomic_inc(&efx->rxq_flush_pending); 1035 } else { 1036 efx_magic_event(efx_rx_queue_channel(rx_queue), 1037 EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue)); 1038 } 1039 atomic_dec(&efx->rxq_flush_outstanding); 1040 if (efx_flush_wake(efx)) 1041 wake_up(&efx->flush_wq); 1042 } 1043 1044 static void 1045 efx_handle_drain_event(struct efx_channel *channel) 1046 { 1047 struct efx_nic *efx = channel->efx; 1048 1049 WARN_ON(atomic_read(&efx->drain_pending) == 0); 1050 atomic_dec(&efx->drain_pending); 1051 if (efx_flush_wake(efx)) 1052 wake_up(&efx->flush_wq); 1053 } 1054 1055 static void 1056 efx_handle_generated_event(struct efx_channel *channel, efx_qword_t *event) 1057 { 1058 struct efx_nic *efx = channel->efx; 1059 struct efx_rx_queue *rx_queue = 1060 efx_channel_has_rx_queue(channel) ? 1061 efx_channel_get_rx_queue(channel) : NULL; 1062 unsigned magic, code; 1063 1064 magic = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC); 1065 code = _EFX_CHANNEL_MAGIC_CODE(magic); 1066 1067 if (magic == EFX_CHANNEL_MAGIC_TEST(channel)) { 1068 /* ignore */ 1069 } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_FILL(rx_queue)) { 1070 /* The queue must be empty, so we won't receive any rx 1071 * events, so efx_process_channel() won't refill the 1072 * queue. Refill it here */ 1073 efx_fast_push_rx_descriptors(rx_queue); 1074 } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue)) { 1075 rx_queue->enabled = false; 1076 efx_handle_drain_event(channel); 1077 } else if (code == _EFX_CHANNEL_MAGIC_TX_DRAIN) { 1078 efx_handle_drain_event(channel); 1079 } else { 1080 netif_dbg(efx, hw, efx->net_dev, "channel %d received " 1081 "generated event "EFX_QWORD_FMT"\n", 1082 channel->channel, EFX_QWORD_VAL(*event)); 1083 } 1084 } 1085 1086 static void 1087 efx_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 1088 { 1089 struct efx_nic *efx = channel->efx; 1090 unsigned int ev_sub_code; 1091 unsigned int ev_sub_data; 1092 1093 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE); 1094 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA); 1095 1096 switch (ev_sub_code) { 1097 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: 1098 netif_vdbg(efx, hw, efx->net_dev, "channel %d TXQ %d flushed\n", 1099 channel->channel, ev_sub_data); 1100 efx_handle_tx_flush_done(efx, event); 1101 break; 1102 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: 1103 netif_vdbg(efx, hw, efx->net_dev, "channel %d RXQ %d flushed\n", 1104 channel->channel, ev_sub_data); 1105 efx_handle_rx_flush_done(efx, event); 1106 break; 1107 case FSE_AZ_EVQ_INIT_DONE_EV: 1108 netif_dbg(efx, hw, efx->net_dev, 1109 "channel %d EVQ %d initialised\n", 1110 channel->channel, ev_sub_data); 1111 break; 1112 case FSE_AZ_SRM_UPD_DONE_EV: 1113 netif_vdbg(efx, hw, efx->net_dev, 1114 "channel %d SRAM update done\n", channel->channel); 1115 break; 1116 case FSE_AZ_WAKE_UP_EV: 1117 netif_vdbg(efx, hw, efx->net_dev, 1118 "channel %d RXQ %d wakeup event\n", 1119 channel->channel, ev_sub_data); 1120 break; 1121 case FSE_AZ_TIMER_EV: 1122 netif_vdbg(efx, hw, efx->net_dev, 1123 "channel %d RX queue %d timer expired\n", 1124 channel->channel, ev_sub_data); 1125 break; 1126 case FSE_AA_RX_RECOVER_EV: 1127 netif_err(efx, rx_err, efx->net_dev, 1128 "channel %d seen DRIVER RX_RESET event. " 1129 "Resetting.\n", channel->channel); 1130 atomic_inc(&efx->rx_reset); 1131 efx_schedule_reset(efx, 1132 EFX_WORKAROUND_6555(efx) ? 1133 RESET_TYPE_RX_RECOVERY : 1134 RESET_TYPE_DISABLE); 1135 break; 1136 case FSE_BZ_RX_DSC_ERROR_EV: 1137 netif_err(efx, rx_err, efx->net_dev, 1138 "RX DMA Q %d reports descriptor fetch error." 1139 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data); 1140 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH); 1141 break; 1142 case FSE_BZ_TX_DSC_ERROR_EV: 1143 netif_err(efx, tx_err, efx->net_dev, 1144 "TX DMA Q %d reports descriptor fetch error." 1145 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data); 1146 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); 1147 break; 1148 default: 1149 netif_vdbg(efx, hw, efx->net_dev, 1150 "channel %d unknown driver event code %d " 1151 "data %04x\n", channel->channel, ev_sub_code, 1152 ev_sub_data); 1153 break; 1154 } 1155 } 1156 1157 int efx_nic_process_eventq(struct efx_channel *channel, int budget) 1158 { 1159 struct efx_nic *efx = channel->efx; 1160 unsigned int read_ptr; 1161 efx_qword_t event, *p_event; 1162 int ev_code; 1163 int tx_packets = 0; 1164 int spent = 0; 1165 1166 read_ptr = channel->eventq_read_ptr; 1167 1168 for (;;) { 1169 p_event = efx_event(channel, read_ptr); 1170 event = *p_event; 1171 1172 if (!efx_event_present(&event)) 1173 /* End of events */ 1174 break; 1175 1176 netif_vdbg(channel->efx, intr, channel->efx->net_dev, 1177 "channel %d event is "EFX_QWORD_FMT"\n", 1178 channel->channel, EFX_QWORD_VAL(event)); 1179 1180 /* Clear this event by marking it all ones */ 1181 EFX_SET_QWORD(*p_event); 1182 1183 ++read_ptr; 1184 1185 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE); 1186 1187 switch (ev_code) { 1188 case FSE_AZ_EV_CODE_RX_EV: 1189 efx_handle_rx_event(channel, &event); 1190 if (++spent == budget) 1191 goto out; 1192 break; 1193 case FSE_AZ_EV_CODE_TX_EV: 1194 tx_packets += efx_handle_tx_event(channel, &event); 1195 if (tx_packets > efx->txq_entries) { 1196 spent = budget; 1197 goto out; 1198 } 1199 break; 1200 case FSE_AZ_EV_CODE_DRV_GEN_EV: 1201 efx_handle_generated_event(channel, &event); 1202 break; 1203 case FSE_AZ_EV_CODE_DRIVER_EV: 1204 efx_handle_driver_event(channel, &event); 1205 break; 1206 case FSE_CZ_EV_CODE_MCDI_EV: 1207 efx_mcdi_process_event(channel, &event); 1208 break; 1209 case FSE_AZ_EV_CODE_GLOBAL_EV: 1210 if (efx->type->handle_global_event && 1211 efx->type->handle_global_event(channel, &event)) 1212 break; 1213 /* else fall through */ 1214 default: 1215 netif_err(channel->efx, hw, channel->efx->net_dev, 1216 "channel %d unknown event type %d (data " 1217 EFX_QWORD_FMT ")\n", channel->channel, 1218 ev_code, EFX_QWORD_VAL(event)); 1219 } 1220 } 1221 1222 out: 1223 channel->eventq_read_ptr = read_ptr; 1224 return spent; 1225 } 1226 1227 /* Check whether an event is present in the eventq at the current 1228 * read pointer. Only useful for self-test. 1229 */ 1230 bool efx_nic_event_present(struct efx_channel *channel) 1231 { 1232 return efx_event_present(efx_event(channel, channel->eventq_read_ptr)); 1233 } 1234 1235 /* Allocate buffer table entries for event queue */ 1236 int efx_nic_probe_eventq(struct efx_channel *channel) 1237 { 1238 struct efx_nic *efx = channel->efx; 1239 unsigned entries; 1240 1241 entries = channel->eventq_mask + 1; 1242 return efx_alloc_special_buffer(efx, &channel->eventq, 1243 entries * sizeof(efx_qword_t)); 1244 } 1245 1246 void efx_nic_init_eventq(struct efx_channel *channel) 1247 { 1248 efx_oword_t reg; 1249 struct efx_nic *efx = channel->efx; 1250 1251 netif_dbg(efx, hw, efx->net_dev, 1252 "channel %d event queue in special buffers %d-%d\n", 1253 channel->channel, channel->eventq.index, 1254 channel->eventq.index + channel->eventq.entries - 1); 1255 1256 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) { 1257 EFX_POPULATE_OWORD_3(reg, 1258 FRF_CZ_TIMER_Q_EN, 1, 1259 FRF_CZ_HOST_NOTIFY_MODE, 0, 1260 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS); 1261 efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, channel->channel); 1262 } 1263 1264 /* Pin event queue buffer */ 1265 efx_init_special_buffer(efx, &channel->eventq); 1266 1267 /* Fill event queue with all ones (i.e. empty events) */ 1268 memset(channel->eventq.addr, 0xff, channel->eventq.len); 1269 1270 /* Push event queue to card */ 1271 EFX_POPULATE_OWORD_3(reg, 1272 FRF_AZ_EVQ_EN, 1, 1273 FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries), 1274 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index); 1275 efx_writeo_table(efx, ®, efx->type->evq_ptr_tbl_base, 1276 channel->channel); 1277 1278 efx->type->push_irq_moderation(channel); 1279 } 1280 1281 void efx_nic_fini_eventq(struct efx_channel *channel) 1282 { 1283 efx_oword_t reg; 1284 struct efx_nic *efx = channel->efx; 1285 1286 /* Remove event queue from card */ 1287 EFX_ZERO_OWORD(reg); 1288 efx_writeo_table(efx, ®, efx->type->evq_ptr_tbl_base, 1289 channel->channel); 1290 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) 1291 efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, channel->channel); 1292 1293 /* Unpin event queue */ 1294 efx_fini_special_buffer(efx, &channel->eventq); 1295 } 1296 1297 /* Free buffers backing event queue */ 1298 void efx_nic_remove_eventq(struct efx_channel *channel) 1299 { 1300 efx_free_special_buffer(channel->efx, &channel->eventq); 1301 } 1302 1303 1304 void efx_nic_generate_test_event(struct efx_channel *channel) 1305 { 1306 efx_magic_event(channel, EFX_CHANNEL_MAGIC_TEST(channel)); 1307 } 1308 1309 void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue) 1310 { 1311 efx_magic_event(efx_rx_queue_channel(rx_queue), 1312 EFX_CHANNEL_MAGIC_FILL(rx_queue)); 1313 } 1314 1315 /************************************************************************** 1316 * 1317 * Hardware interrupts 1318 * The hardware interrupt handler does very little work; all the event 1319 * queue processing is carried out by per-channel tasklets. 1320 * 1321 **************************************************************************/ 1322 1323 /* Enable/disable/generate interrupts */ 1324 static inline void efx_nic_interrupts(struct efx_nic *efx, 1325 bool enabled, bool force) 1326 { 1327 efx_oword_t int_en_reg_ker; 1328 1329 EFX_POPULATE_OWORD_3(int_en_reg_ker, 1330 FRF_AZ_KER_INT_LEVE_SEL, efx->irq_level, 1331 FRF_AZ_KER_INT_KER, force, 1332 FRF_AZ_DRV_INT_EN_KER, enabled); 1333 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER); 1334 } 1335 1336 void efx_nic_enable_interrupts(struct efx_nic *efx) 1337 { 1338 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr)); 1339 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */ 1340 1341 efx_nic_interrupts(efx, true, false); 1342 } 1343 1344 void efx_nic_disable_interrupts(struct efx_nic *efx) 1345 { 1346 /* Disable interrupts */ 1347 efx_nic_interrupts(efx, false, false); 1348 } 1349 1350 /* Generate a test interrupt 1351 * Interrupt must already have been enabled, otherwise nasty things 1352 * may happen. 1353 */ 1354 void efx_nic_generate_interrupt(struct efx_nic *efx) 1355 { 1356 efx_nic_interrupts(efx, true, true); 1357 } 1358 1359 /* Process a fatal interrupt 1360 * Disable bus mastering ASAP and schedule a reset 1361 */ 1362 irqreturn_t efx_nic_fatal_interrupt(struct efx_nic *efx) 1363 { 1364 struct falcon_nic_data *nic_data = efx->nic_data; 1365 efx_oword_t *int_ker = efx->irq_status.addr; 1366 efx_oword_t fatal_intr; 1367 int error, mem_perr; 1368 1369 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER); 1370 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR); 1371 1372 netif_err(efx, hw, efx->net_dev, "SYSTEM ERROR "EFX_OWORD_FMT" status " 1373 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker), 1374 EFX_OWORD_VAL(fatal_intr), 1375 error ? "disabling bus mastering" : "no recognised error"); 1376 1377 /* If this is a memory parity error dump which blocks are offending */ 1378 mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) || 1379 EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER)); 1380 if (mem_perr) { 1381 efx_oword_t reg; 1382 efx_reado(efx, ®, FR_AZ_MEM_STAT); 1383 netif_err(efx, hw, efx->net_dev, 1384 "SYSTEM ERROR: memory parity error "EFX_OWORD_FMT"\n", 1385 EFX_OWORD_VAL(reg)); 1386 } 1387 1388 /* Disable both devices */ 1389 pci_clear_master(efx->pci_dev); 1390 if (efx_nic_is_dual_func(efx)) 1391 pci_clear_master(nic_data->pci_dev2); 1392 efx_nic_disable_interrupts(efx); 1393 1394 /* Count errors and reset or disable the NIC accordingly */ 1395 if (efx->int_error_count == 0 || 1396 time_after(jiffies, efx->int_error_expire)) { 1397 efx->int_error_count = 0; 1398 efx->int_error_expire = 1399 jiffies + EFX_INT_ERROR_EXPIRE * HZ; 1400 } 1401 if (++efx->int_error_count < EFX_MAX_INT_ERRORS) { 1402 netif_err(efx, hw, efx->net_dev, 1403 "SYSTEM ERROR - reset scheduled\n"); 1404 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR); 1405 } else { 1406 netif_err(efx, hw, efx->net_dev, 1407 "SYSTEM ERROR - max number of errors seen." 1408 "NIC will be disabled\n"); 1409 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 1410 } 1411 1412 return IRQ_HANDLED; 1413 } 1414 1415 /* Handle a legacy interrupt 1416 * Acknowledges the interrupt and schedule event queue processing. 1417 */ 1418 static irqreturn_t efx_legacy_interrupt(int irq, void *dev_id) 1419 { 1420 struct efx_nic *efx = dev_id; 1421 efx_oword_t *int_ker = efx->irq_status.addr; 1422 irqreturn_t result = IRQ_NONE; 1423 struct efx_channel *channel; 1424 efx_dword_t reg; 1425 u32 queues; 1426 int syserr; 1427 1428 /* Could this be ours? If interrupts are disabled then the 1429 * channel state may not be valid. 1430 */ 1431 if (!efx->legacy_irq_enabled) 1432 return result; 1433 1434 /* Read the ISR which also ACKs the interrupts */ 1435 efx_readd(efx, ®, FR_BZ_INT_ISR0); 1436 queues = EFX_EXTRACT_DWORD(reg, 0, 31); 1437 1438 /* Handle non-event-queue sources */ 1439 if (queues & (1U << efx->irq_level)) { 1440 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); 1441 if (unlikely(syserr)) 1442 return efx_nic_fatal_interrupt(efx); 1443 efx->last_irq_cpu = raw_smp_processor_id(); 1444 } 1445 1446 if (queues != 0) { 1447 if (EFX_WORKAROUND_15783(efx)) 1448 efx->irq_zero_count = 0; 1449 1450 /* Schedule processing of any interrupting queues */ 1451 efx_for_each_channel(channel, efx) { 1452 if (queues & 1) 1453 efx_schedule_channel_irq(channel); 1454 queues >>= 1; 1455 } 1456 result = IRQ_HANDLED; 1457 1458 } else if (EFX_WORKAROUND_15783(efx)) { 1459 efx_qword_t *event; 1460 1461 /* We can't return IRQ_HANDLED more than once on seeing ISR=0 1462 * because this might be a shared interrupt. */ 1463 if (efx->irq_zero_count++ == 0) 1464 result = IRQ_HANDLED; 1465 1466 /* Ensure we schedule or rearm all event queues */ 1467 efx_for_each_channel(channel, efx) { 1468 event = efx_event(channel, channel->eventq_read_ptr); 1469 if (efx_event_present(event)) 1470 efx_schedule_channel_irq(channel); 1471 else 1472 efx_nic_eventq_read_ack(channel); 1473 } 1474 } 1475 1476 if (result == IRQ_HANDLED) 1477 netif_vdbg(efx, intr, efx->net_dev, 1478 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 1479 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 1480 1481 return result; 1482 } 1483 1484 /* Handle an MSI interrupt 1485 * 1486 * Handle an MSI hardware interrupt. This routine schedules event 1487 * queue processing. No interrupt acknowledgement cycle is necessary. 1488 * Also, we never need to check that the interrupt is for us, since 1489 * MSI interrupts cannot be shared. 1490 */ 1491 static irqreturn_t efx_msi_interrupt(int irq, void *dev_id) 1492 { 1493 struct efx_channel *channel = *(struct efx_channel **)dev_id; 1494 struct efx_nic *efx = channel->efx; 1495 efx_oword_t *int_ker = efx->irq_status.addr; 1496 int syserr; 1497 1498 netif_vdbg(efx, intr, efx->net_dev, 1499 "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", 1500 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); 1501 1502 /* Handle non-event-queue sources */ 1503 if (channel->channel == efx->irq_level) { 1504 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); 1505 if (unlikely(syserr)) 1506 return efx_nic_fatal_interrupt(efx); 1507 efx->last_irq_cpu = raw_smp_processor_id(); 1508 } 1509 1510 /* Schedule processing of the channel */ 1511 efx_schedule_channel_irq(channel); 1512 1513 return IRQ_HANDLED; 1514 } 1515 1516 1517 /* Setup RSS indirection table. 1518 * This maps from the hash value of the packet to RXQ 1519 */ 1520 void efx_nic_push_rx_indir_table(struct efx_nic *efx) 1521 { 1522 size_t i = 0; 1523 efx_dword_t dword; 1524 1525 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) 1526 return; 1527 1528 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) != 1529 FR_BZ_RX_INDIRECTION_TBL_ROWS); 1530 1531 for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) { 1532 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE, 1533 efx->rx_indir_table[i]); 1534 efx_writed_table(efx, &dword, FR_BZ_RX_INDIRECTION_TBL, i); 1535 } 1536 } 1537 1538 /* Hook interrupt handler(s) 1539 * Try MSI and then legacy interrupts. 1540 */ 1541 int efx_nic_init_interrupt(struct efx_nic *efx) 1542 { 1543 struct efx_channel *channel; 1544 int rc; 1545 1546 if (!EFX_INT_MODE_USE_MSI(efx)) { 1547 irq_handler_t handler; 1548 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) 1549 handler = efx_legacy_interrupt; 1550 else 1551 handler = falcon_legacy_interrupt_a1; 1552 1553 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED, 1554 efx->name, efx); 1555 if (rc) { 1556 netif_err(efx, drv, efx->net_dev, 1557 "failed to hook legacy IRQ %d\n", 1558 efx->pci_dev->irq); 1559 goto fail1; 1560 } 1561 return 0; 1562 } 1563 1564 /* Hook MSI or MSI-X interrupt */ 1565 efx_for_each_channel(channel, efx) { 1566 rc = request_irq(channel->irq, efx_msi_interrupt, 1567 IRQF_PROBE_SHARED, /* Not shared */ 1568 efx->channel_name[channel->channel], 1569 &efx->channel[channel->channel]); 1570 if (rc) { 1571 netif_err(efx, drv, efx->net_dev, 1572 "failed to hook IRQ %d\n", channel->irq); 1573 goto fail2; 1574 } 1575 } 1576 1577 return 0; 1578 1579 fail2: 1580 efx_for_each_channel(channel, efx) 1581 free_irq(channel->irq, &efx->channel[channel->channel]); 1582 fail1: 1583 return rc; 1584 } 1585 1586 void efx_nic_fini_interrupt(struct efx_nic *efx) 1587 { 1588 struct efx_channel *channel; 1589 efx_oword_t reg; 1590 1591 /* Disable MSI/MSI-X interrupts */ 1592 efx_for_each_channel(channel, efx) { 1593 if (channel->irq) 1594 free_irq(channel->irq, &efx->channel[channel->channel]); 1595 } 1596 1597 /* ACK legacy interrupt */ 1598 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) 1599 efx_reado(efx, ®, FR_BZ_INT_ISR0); 1600 else 1601 falcon_irq_ack_a1(efx); 1602 1603 /* Disable legacy interrupt */ 1604 if (efx->legacy_irq) 1605 free_irq(efx->legacy_irq, efx); 1606 } 1607 1608 u32 efx_nic_fpga_ver(struct efx_nic *efx) 1609 { 1610 efx_oword_t altera_build; 1611 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD); 1612 return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER); 1613 } 1614 1615 void efx_nic_init_common(struct efx_nic *efx) 1616 { 1617 efx_oword_t temp; 1618 1619 /* Set positions of descriptor caches in SRAM. */ 1620 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, 1621 efx->type->tx_dc_base / 8); 1622 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG); 1623 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, 1624 efx->type->rx_dc_base / 8); 1625 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG); 1626 1627 /* Set TX descriptor cache size. */ 1628 BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER)); 1629 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER); 1630 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG); 1631 1632 /* Set RX descriptor cache size. Set low watermark to size-8, as 1633 * this allows most efficient prefetching. 1634 */ 1635 BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER)); 1636 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER); 1637 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG); 1638 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8); 1639 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM); 1640 1641 /* Program INT_KER address */ 1642 EFX_POPULATE_OWORD_2(temp, 1643 FRF_AZ_NORM_INT_VEC_DIS_KER, 1644 EFX_INT_MODE_USE_MSI(efx), 1645 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr); 1646 efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER); 1647 1648 if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx)) 1649 /* Use an interrupt level unused by event queues */ 1650 efx->irq_level = 0x1f; 1651 else 1652 /* Use a valid MSI-X vector */ 1653 efx->irq_level = 0; 1654 1655 /* Enable all the genuinely fatal interrupts. (They are still 1656 * masked by the overall interrupt mask, controlled by 1657 * falcon_interrupts()). 1658 * 1659 * Note: All other fatal interrupts are enabled 1660 */ 1661 EFX_POPULATE_OWORD_3(temp, 1662 FRF_AZ_ILL_ADR_INT_KER_EN, 1, 1663 FRF_AZ_RBUF_OWN_INT_KER_EN, 1, 1664 FRF_AZ_TBUF_OWN_INT_KER_EN, 1); 1665 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) 1666 EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1); 1667 EFX_INVERT_OWORD(temp); 1668 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER); 1669 1670 efx_nic_push_rx_indir_table(efx); 1671 1672 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be 1673 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q. 1674 */ 1675 efx_reado(efx, &temp, FR_AZ_TX_RESERVED); 1676 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe); 1677 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1); 1678 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1); 1679 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 1); 1680 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1); 1681 /* Enable SW_EV to inherit in char driver - assume harmless here */ 1682 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1); 1683 /* Prefetch threshold 2 => fetch when descriptor cache half empty */ 1684 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2); 1685 /* Disable hardware watchdog which can misfire */ 1686 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff); 1687 /* Squash TX of packets of 16 bytes or less */ 1688 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) 1689 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); 1690 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED); 1691 1692 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { 1693 EFX_POPULATE_OWORD_4(temp, 1694 /* Default values */ 1695 FRF_BZ_TX_PACE_SB_NOT_AF, 0x15, 1696 FRF_BZ_TX_PACE_SB_AF, 0xb, 1697 FRF_BZ_TX_PACE_FB_BASE, 0, 1698 /* Allow large pace values in the 1699 * fast bin. */ 1700 FRF_BZ_TX_PACE_BIN_TH, 1701 FFE_BZ_TX_PACE_RESERVED); 1702 efx_writeo(efx, &temp, FR_BZ_TX_PACE); 1703 } 1704 } 1705 1706 /* Register dump */ 1707 1708 #define REGISTER_REVISION_A 1 1709 #define REGISTER_REVISION_B 2 1710 #define REGISTER_REVISION_C 3 1711 #define REGISTER_REVISION_Z 3 /* latest revision */ 1712 1713 struct efx_nic_reg { 1714 u32 offset:24; 1715 u32 min_revision:2, max_revision:2; 1716 }; 1717 1718 #define REGISTER(name, min_rev, max_rev) { \ 1719 FR_ ## min_rev ## max_rev ## _ ## name, \ 1720 REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev \ 1721 } 1722 #define REGISTER_AA(name) REGISTER(name, A, A) 1723 #define REGISTER_AB(name) REGISTER(name, A, B) 1724 #define REGISTER_AZ(name) REGISTER(name, A, Z) 1725 #define REGISTER_BB(name) REGISTER(name, B, B) 1726 #define REGISTER_BZ(name) REGISTER(name, B, Z) 1727 #define REGISTER_CZ(name) REGISTER(name, C, Z) 1728 1729 static const struct efx_nic_reg efx_nic_regs[] = { 1730 REGISTER_AZ(ADR_REGION), 1731 REGISTER_AZ(INT_EN_KER), 1732 REGISTER_BZ(INT_EN_CHAR), 1733 REGISTER_AZ(INT_ADR_KER), 1734 REGISTER_BZ(INT_ADR_CHAR), 1735 /* INT_ACK_KER is WO */ 1736 /* INT_ISR0 is RC */ 1737 REGISTER_AZ(HW_INIT), 1738 REGISTER_CZ(USR_EV_CFG), 1739 REGISTER_AB(EE_SPI_HCMD), 1740 REGISTER_AB(EE_SPI_HADR), 1741 REGISTER_AB(EE_SPI_HDATA), 1742 REGISTER_AB(EE_BASE_PAGE), 1743 REGISTER_AB(EE_VPD_CFG0), 1744 /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */ 1745 /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */ 1746 /* PCIE_CORE_INDIRECT is indirect */ 1747 REGISTER_AB(NIC_STAT), 1748 REGISTER_AB(GPIO_CTL), 1749 REGISTER_AB(GLB_CTL), 1750 /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */ 1751 REGISTER_BZ(DP_CTRL), 1752 REGISTER_AZ(MEM_STAT), 1753 REGISTER_AZ(CS_DEBUG), 1754 REGISTER_AZ(ALTERA_BUILD), 1755 REGISTER_AZ(CSR_SPARE), 1756 REGISTER_AB(PCIE_SD_CTL0123), 1757 REGISTER_AB(PCIE_SD_CTL45), 1758 REGISTER_AB(PCIE_PCS_CTL_STAT), 1759 /* DEBUG_DATA_OUT is not used */ 1760 /* DRV_EV is WO */ 1761 REGISTER_AZ(EVQ_CTL), 1762 REGISTER_AZ(EVQ_CNT1), 1763 REGISTER_AZ(EVQ_CNT2), 1764 REGISTER_AZ(BUF_TBL_CFG), 1765 REGISTER_AZ(SRM_RX_DC_CFG), 1766 REGISTER_AZ(SRM_TX_DC_CFG), 1767 REGISTER_AZ(SRM_CFG), 1768 /* BUF_TBL_UPD is WO */ 1769 REGISTER_AZ(SRM_UPD_EVQ), 1770 REGISTER_AZ(SRAM_PARITY), 1771 REGISTER_AZ(RX_CFG), 1772 REGISTER_BZ(RX_FILTER_CTL), 1773 /* RX_FLUSH_DESCQ is WO */ 1774 REGISTER_AZ(RX_DC_CFG), 1775 REGISTER_AZ(RX_DC_PF_WM), 1776 REGISTER_BZ(RX_RSS_TKEY), 1777 /* RX_NODESC_DROP is RC */ 1778 REGISTER_AA(RX_SELF_RST), 1779 /* RX_DEBUG, RX_PUSH_DROP are not used */ 1780 REGISTER_CZ(RX_RSS_IPV6_REG1), 1781 REGISTER_CZ(RX_RSS_IPV6_REG2), 1782 REGISTER_CZ(RX_RSS_IPV6_REG3), 1783 /* TX_FLUSH_DESCQ is WO */ 1784 REGISTER_AZ(TX_DC_CFG), 1785 REGISTER_AA(TX_CHKSM_CFG), 1786 REGISTER_AZ(TX_CFG), 1787 /* TX_PUSH_DROP is not used */ 1788 REGISTER_AZ(TX_RESERVED), 1789 REGISTER_BZ(TX_PACE), 1790 /* TX_PACE_DROP_QID is RC */ 1791 REGISTER_BB(TX_VLAN), 1792 REGISTER_BZ(TX_IPFIL_PORTEN), 1793 REGISTER_AB(MD_TXD), 1794 REGISTER_AB(MD_RXD), 1795 REGISTER_AB(MD_CS), 1796 REGISTER_AB(MD_PHY_ADR), 1797 REGISTER_AB(MD_ID), 1798 /* MD_STAT is RC */ 1799 REGISTER_AB(MAC_STAT_DMA), 1800 REGISTER_AB(MAC_CTRL), 1801 REGISTER_BB(GEN_MODE), 1802 REGISTER_AB(MAC_MC_HASH_REG0), 1803 REGISTER_AB(MAC_MC_HASH_REG1), 1804 REGISTER_AB(GM_CFG1), 1805 REGISTER_AB(GM_CFG2), 1806 /* GM_IPG and GM_HD are not used */ 1807 REGISTER_AB(GM_MAX_FLEN), 1808 /* GM_TEST is not used */ 1809 REGISTER_AB(GM_ADR1), 1810 REGISTER_AB(GM_ADR2), 1811 REGISTER_AB(GMF_CFG0), 1812 REGISTER_AB(GMF_CFG1), 1813 REGISTER_AB(GMF_CFG2), 1814 REGISTER_AB(GMF_CFG3), 1815 REGISTER_AB(GMF_CFG4), 1816 REGISTER_AB(GMF_CFG5), 1817 REGISTER_BB(TX_SRC_MAC_CTL), 1818 REGISTER_AB(XM_ADR_LO), 1819 REGISTER_AB(XM_ADR_HI), 1820 REGISTER_AB(XM_GLB_CFG), 1821 REGISTER_AB(XM_TX_CFG), 1822 REGISTER_AB(XM_RX_CFG), 1823 REGISTER_AB(XM_MGT_INT_MASK), 1824 REGISTER_AB(XM_FC), 1825 REGISTER_AB(XM_PAUSE_TIME), 1826 REGISTER_AB(XM_TX_PARAM), 1827 REGISTER_AB(XM_RX_PARAM), 1828 /* XM_MGT_INT_MSK (note no 'A') is RC */ 1829 REGISTER_AB(XX_PWR_RST), 1830 REGISTER_AB(XX_SD_CTL), 1831 REGISTER_AB(XX_TXDRV_CTL), 1832 /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */ 1833 /* XX_CORE_STAT is partly RC */ 1834 }; 1835 1836 struct efx_nic_reg_table { 1837 u32 offset:24; 1838 u32 min_revision:2, max_revision:2; 1839 u32 step:6, rows:21; 1840 }; 1841 1842 #define REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) { \ 1843 offset, \ 1844 REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev, \ 1845 step, rows \ 1846 } 1847 #define REGISTER_TABLE(name, min_rev, max_rev) \ 1848 REGISTER_TABLE_DIMENSIONS( \ 1849 name, FR_ ## min_rev ## max_rev ## _ ## name, \ 1850 min_rev, max_rev, \ 1851 FR_ ## min_rev ## max_rev ## _ ## name ## _STEP, \ 1852 FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS) 1853 #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A) 1854 #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z) 1855 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B) 1856 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z) 1857 #define REGISTER_TABLE_BB_CZ(name) \ 1858 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B, \ 1859 FR_BZ_ ## name ## _STEP, \ 1860 FR_BB_ ## name ## _ROWS), \ 1861 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z, \ 1862 FR_BZ_ ## name ## _STEP, \ 1863 FR_CZ_ ## name ## _ROWS) 1864 #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z) 1865 1866 static const struct efx_nic_reg_table efx_nic_reg_tables[] = { 1867 /* DRIVER is not used */ 1868 /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */ 1869 REGISTER_TABLE_BB(TX_IPFIL_TBL), 1870 REGISTER_TABLE_BB(TX_SRC_MAC_TBL), 1871 REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER), 1872 REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL), 1873 REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER), 1874 REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL), 1875 REGISTER_TABLE_AA(EVQ_PTR_TBL_KER), 1876 REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL), 1877 /* We can't reasonably read all of the buffer table (up to 8MB!). 1878 * However this driver will only use a few entries. Reading 1879 * 1K entries allows for some expansion of queue count and 1880 * size before we need to change the version. */ 1881 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER, 1882 A, A, 8, 1024), 1883 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL, 1884 B, Z, 8, 1024), 1885 REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0), 1886 REGISTER_TABLE_BB_CZ(TIMER_TBL), 1887 REGISTER_TABLE_BB_CZ(TX_PACE_TBL), 1888 REGISTER_TABLE_BZ(RX_INDIRECTION_TBL), 1889 /* TX_FILTER_TBL0 is huge and not used by this driver */ 1890 REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0), 1891 REGISTER_TABLE_CZ(MC_TREG_SMEM), 1892 /* MSIX_PBA_TABLE is not mapped */ 1893 /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */ 1894 REGISTER_TABLE_BZ(RX_FILTER_TBL0), 1895 }; 1896 1897 size_t efx_nic_get_regs_len(struct efx_nic *efx) 1898 { 1899 const struct efx_nic_reg *reg; 1900 const struct efx_nic_reg_table *table; 1901 size_t len = 0; 1902 1903 for (reg = efx_nic_regs; 1904 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs); 1905 reg++) 1906 if (efx->type->revision >= reg->min_revision && 1907 efx->type->revision <= reg->max_revision) 1908 len += sizeof(efx_oword_t); 1909 1910 for (table = efx_nic_reg_tables; 1911 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables); 1912 table++) 1913 if (efx->type->revision >= table->min_revision && 1914 efx->type->revision <= table->max_revision) 1915 len += table->rows * min_t(size_t, table->step, 16); 1916 1917 return len; 1918 } 1919 1920 void efx_nic_get_regs(struct efx_nic *efx, void *buf) 1921 { 1922 const struct efx_nic_reg *reg; 1923 const struct efx_nic_reg_table *table; 1924 1925 for (reg = efx_nic_regs; 1926 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs); 1927 reg++) { 1928 if (efx->type->revision >= reg->min_revision && 1929 efx->type->revision <= reg->max_revision) { 1930 efx_reado(efx, (efx_oword_t *)buf, reg->offset); 1931 buf += sizeof(efx_oword_t); 1932 } 1933 } 1934 1935 for (table = efx_nic_reg_tables; 1936 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables); 1937 table++) { 1938 size_t size, i; 1939 1940 if (!(efx->type->revision >= table->min_revision && 1941 efx->type->revision <= table->max_revision)) 1942 continue; 1943 1944 size = min_t(size_t, table->step, 16); 1945 1946 for (i = 0; i < table->rows; i++) { 1947 switch (table->step) { 1948 case 4: /* 32-bit register or SRAM */ 1949 efx_readd_table(efx, buf, table->offset, i); 1950 break; 1951 case 8: /* 64-bit SRAM */ 1952 efx_sram_readq(efx, 1953 efx->membase + table->offset, 1954 buf, i); 1955 break; 1956 case 16: /* 128-bit register */ 1957 efx_reado_table(efx, buf, table->offset, i); 1958 break; 1959 case 32: /* 128-bit register, interleaved */ 1960 efx_reado_table(efx, buf, table->offset, 2 * i); 1961 break; 1962 default: 1963 WARN_ON(1); 1964 return; 1965 } 1966 buf += size; 1967 } 1968 } 1969 } 1970