1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2006-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/delay.h> 13 #include <linux/interrupt.h> 14 #include <linux/pci.h> 15 #include <linux/module.h> 16 #include <linux/seq_file.h> 17 #include <linux/cpu_rmap.h> 18 #include "net_driver.h" 19 #include "bitfield.h" 20 #include "efx.h" 21 #include "nic.h" 22 #include "farch_regs.h" 23 #include "io.h" 24 #include "workarounds.h" 25 26 /************************************************************************** 27 * 28 * Generic buffer handling 29 * These buffers are used for interrupt status, MAC stats, etc. 30 * 31 **************************************************************************/ 32 33 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, 34 unsigned int len, gfp_t gfp_flags) 35 { 36 buffer->addr = dma_zalloc_coherent(&efx->pci_dev->dev, len, 37 &buffer->dma_addr, gfp_flags); 38 if (!buffer->addr) 39 return -ENOMEM; 40 buffer->len = len; 41 return 0; 42 } 43 44 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer) 45 { 46 if (buffer->addr) { 47 dma_free_coherent(&efx->pci_dev->dev, buffer->len, 48 buffer->addr, buffer->dma_addr); 49 buffer->addr = NULL; 50 } 51 } 52 53 /* Check whether an event is present in the eventq at the current 54 * read pointer. Only useful for self-test. 55 */ 56 bool efx_nic_event_present(struct efx_channel *channel) 57 { 58 return efx_event_present(efx_event(channel, channel->eventq_read_ptr)); 59 } 60 61 void efx_nic_event_test_start(struct efx_channel *channel) 62 { 63 channel->event_test_cpu = -1; 64 smp_wmb(); 65 channel->efx->type->ev_test_generate(channel); 66 } 67 68 void efx_nic_irq_test_start(struct efx_nic *efx) 69 { 70 efx->last_irq_cpu = -1; 71 smp_wmb(); 72 efx->type->irq_test_generate(efx); 73 } 74 75 /* Hook interrupt handler(s) 76 * Try MSI and then legacy interrupts. 77 */ 78 int efx_nic_init_interrupt(struct efx_nic *efx) 79 { 80 struct efx_channel *channel; 81 unsigned int n_irqs; 82 int rc; 83 84 if (!EFX_INT_MODE_USE_MSI(efx)) { 85 rc = request_irq(efx->legacy_irq, 86 efx->type->irq_handle_legacy, IRQF_SHARED, 87 efx->name, efx); 88 if (rc) { 89 netif_err(efx, drv, efx->net_dev, 90 "failed to hook legacy IRQ %d\n", 91 efx->pci_dev->irq); 92 goto fail1; 93 } 94 return 0; 95 } 96 97 #ifdef CONFIG_RFS_ACCEL 98 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { 99 efx->net_dev->rx_cpu_rmap = 100 alloc_irq_cpu_rmap(efx->n_rx_channels); 101 if (!efx->net_dev->rx_cpu_rmap) { 102 rc = -ENOMEM; 103 goto fail1; 104 } 105 } 106 #endif 107 108 /* Hook MSI or MSI-X interrupt */ 109 n_irqs = 0; 110 efx_for_each_channel(channel, efx) { 111 rc = request_irq(channel->irq, efx->type->irq_handle_msi, 112 IRQF_PROBE_SHARED, /* Not shared */ 113 efx->msi_context[channel->channel].name, 114 &efx->msi_context[channel->channel]); 115 if (rc) { 116 netif_err(efx, drv, efx->net_dev, 117 "failed to hook IRQ %d\n", channel->irq); 118 goto fail2; 119 } 120 ++n_irqs; 121 122 #ifdef CONFIG_RFS_ACCEL 123 if (efx->interrupt_mode == EFX_INT_MODE_MSIX && 124 channel->channel < efx->n_rx_channels) { 125 rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap, 126 channel->irq); 127 if (rc) 128 goto fail2; 129 } 130 #endif 131 } 132 133 return 0; 134 135 fail2: 136 #ifdef CONFIG_RFS_ACCEL 137 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); 138 efx->net_dev->rx_cpu_rmap = NULL; 139 #endif 140 efx_for_each_channel(channel, efx) { 141 if (n_irqs-- == 0) 142 break; 143 free_irq(channel->irq, &efx->msi_context[channel->channel]); 144 } 145 fail1: 146 return rc; 147 } 148 149 void efx_nic_fini_interrupt(struct efx_nic *efx) 150 { 151 struct efx_channel *channel; 152 153 #ifdef CONFIG_RFS_ACCEL 154 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); 155 efx->net_dev->rx_cpu_rmap = NULL; 156 #endif 157 158 /* Disable MSI/MSI-X interrupts */ 159 efx_for_each_channel(channel, efx) 160 free_irq(channel->irq, &efx->msi_context[channel->channel]); 161 162 /* Disable legacy interrupt */ 163 if (efx->legacy_irq) 164 free_irq(efx->legacy_irq, efx); 165 } 166 167 /* Register dump */ 168 169 #define REGISTER_REVISION_A 1 170 #define REGISTER_REVISION_B 2 171 #define REGISTER_REVISION_C 3 172 #define REGISTER_REVISION_Z 3 /* latest revision */ 173 174 struct efx_nic_reg { 175 u32 offset:24; 176 u32 min_revision:2, max_revision:2; 177 }; 178 179 #define REGISTER(name, min_rev, max_rev) { \ 180 FR_ ## min_rev ## max_rev ## _ ## name, \ 181 REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev \ 182 } 183 #define REGISTER_AA(name) REGISTER(name, A, A) 184 #define REGISTER_AB(name) REGISTER(name, A, B) 185 #define REGISTER_AZ(name) REGISTER(name, A, Z) 186 #define REGISTER_BB(name) REGISTER(name, B, B) 187 #define REGISTER_BZ(name) REGISTER(name, B, Z) 188 #define REGISTER_CZ(name) REGISTER(name, C, Z) 189 190 static const struct efx_nic_reg efx_nic_regs[] = { 191 REGISTER_AZ(ADR_REGION), 192 REGISTER_AZ(INT_EN_KER), 193 REGISTER_BZ(INT_EN_CHAR), 194 REGISTER_AZ(INT_ADR_KER), 195 REGISTER_BZ(INT_ADR_CHAR), 196 /* INT_ACK_KER is WO */ 197 /* INT_ISR0 is RC */ 198 REGISTER_AZ(HW_INIT), 199 REGISTER_CZ(USR_EV_CFG), 200 REGISTER_AB(EE_SPI_HCMD), 201 REGISTER_AB(EE_SPI_HADR), 202 REGISTER_AB(EE_SPI_HDATA), 203 REGISTER_AB(EE_BASE_PAGE), 204 REGISTER_AB(EE_VPD_CFG0), 205 /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */ 206 /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */ 207 /* PCIE_CORE_INDIRECT is indirect */ 208 REGISTER_AB(NIC_STAT), 209 REGISTER_AB(GPIO_CTL), 210 REGISTER_AB(GLB_CTL), 211 /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */ 212 REGISTER_BZ(DP_CTRL), 213 REGISTER_AZ(MEM_STAT), 214 REGISTER_AZ(CS_DEBUG), 215 REGISTER_AZ(ALTERA_BUILD), 216 REGISTER_AZ(CSR_SPARE), 217 REGISTER_AB(PCIE_SD_CTL0123), 218 REGISTER_AB(PCIE_SD_CTL45), 219 REGISTER_AB(PCIE_PCS_CTL_STAT), 220 /* DEBUG_DATA_OUT is not used */ 221 /* DRV_EV is WO */ 222 REGISTER_AZ(EVQ_CTL), 223 REGISTER_AZ(EVQ_CNT1), 224 REGISTER_AZ(EVQ_CNT2), 225 REGISTER_AZ(BUF_TBL_CFG), 226 REGISTER_AZ(SRM_RX_DC_CFG), 227 REGISTER_AZ(SRM_TX_DC_CFG), 228 REGISTER_AZ(SRM_CFG), 229 /* BUF_TBL_UPD is WO */ 230 REGISTER_AZ(SRM_UPD_EVQ), 231 REGISTER_AZ(SRAM_PARITY), 232 REGISTER_AZ(RX_CFG), 233 REGISTER_BZ(RX_FILTER_CTL), 234 /* RX_FLUSH_DESCQ is WO */ 235 REGISTER_AZ(RX_DC_CFG), 236 REGISTER_AZ(RX_DC_PF_WM), 237 REGISTER_BZ(RX_RSS_TKEY), 238 /* RX_NODESC_DROP is RC */ 239 REGISTER_AA(RX_SELF_RST), 240 /* RX_DEBUG, RX_PUSH_DROP are not used */ 241 REGISTER_CZ(RX_RSS_IPV6_REG1), 242 REGISTER_CZ(RX_RSS_IPV6_REG2), 243 REGISTER_CZ(RX_RSS_IPV6_REG3), 244 /* TX_FLUSH_DESCQ is WO */ 245 REGISTER_AZ(TX_DC_CFG), 246 REGISTER_AA(TX_CHKSM_CFG), 247 REGISTER_AZ(TX_CFG), 248 /* TX_PUSH_DROP is not used */ 249 REGISTER_AZ(TX_RESERVED), 250 REGISTER_BZ(TX_PACE), 251 /* TX_PACE_DROP_QID is RC */ 252 REGISTER_BB(TX_VLAN), 253 REGISTER_BZ(TX_IPFIL_PORTEN), 254 REGISTER_AB(MD_TXD), 255 REGISTER_AB(MD_RXD), 256 REGISTER_AB(MD_CS), 257 REGISTER_AB(MD_PHY_ADR), 258 REGISTER_AB(MD_ID), 259 /* MD_STAT is RC */ 260 REGISTER_AB(MAC_STAT_DMA), 261 REGISTER_AB(MAC_CTRL), 262 REGISTER_BB(GEN_MODE), 263 REGISTER_AB(MAC_MC_HASH_REG0), 264 REGISTER_AB(MAC_MC_HASH_REG1), 265 REGISTER_AB(GM_CFG1), 266 REGISTER_AB(GM_CFG2), 267 /* GM_IPG and GM_HD are not used */ 268 REGISTER_AB(GM_MAX_FLEN), 269 /* GM_TEST is not used */ 270 REGISTER_AB(GM_ADR1), 271 REGISTER_AB(GM_ADR2), 272 REGISTER_AB(GMF_CFG0), 273 REGISTER_AB(GMF_CFG1), 274 REGISTER_AB(GMF_CFG2), 275 REGISTER_AB(GMF_CFG3), 276 REGISTER_AB(GMF_CFG4), 277 REGISTER_AB(GMF_CFG5), 278 REGISTER_BB(TX_SRC_MAC_CTL), 279 REGISTER_AB(XM_ADR_LO), 280 REGISTER_AB(XM_ADR_HI), 281 REGISTER_AB(XM_GLB_CFG), 282 REGISTER_AB(XM_TX_CFG), 283 REGISTER_AB(XM_RX_CFG), 284 REGISTER_AB(XM_MGT_INT_MASK), 285 REGISTER_AB(XM_FC), 286 REGISTER_AB(XM_PAUSE_TIME), 287 REGISTER_AB(XM_TX_PARAM), 288 REGISTER_AB(XM_RX_PARAM), 289 /* XM_MGT_INT_MSK (note no 'A') is RC */ 290 REGISTER_AB(XX_PWR_RST), 291 REGISTER_AB(XX_SD_CTL), 292 REGISTER_AB(XX_TXDRV_CTL), 293 /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */ 294 /* XX_CORE_STAT is partly RC */ 295 }; 296 297 struct efx_nic_reg_table { 298 u32 offset:24; 299 u32 min_revision:2, max_revision:2; 300 u32 step:6, rows:21; 301 }; 302 303 #define REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) { \ 304 offset, \ 305 REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev, \ 306 step, rows \ 307 } 308 #define REGISTER_TABLE(name, min_rev, max_rev) \ 309 REGISTER_TABLE_DIMENSIONS( \ 310 name, FR_ ## min_rev ## max_rev ## _ ## name, \ 311 min_rev, max_rev, \ 312 FR_ ## min_rev ## max_rev ## _ ## name ## _STEP, \ 313 FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS) 314 #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A) 315 #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z) 316 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B) 317 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z) 318 #define REGISTER_TABLE_BB_CZ(name) \ 319 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B, \ 320 FR_BZ_ ## name ## _STEP, \ 321 FR_BB_ ## name ## _ROWS), \ 322 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z, \ 323 FR_BZ_ ## name ## _STEP, \ 324 FR_CZ_ ## name ## _ROWS) 325 #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z) 326 327 static const struct efx_nic_reg_table efx_nic_reg_tables[] = { 328 /* DRIVER is not used */ 329 /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */ 330 REGISTER_TABLE_BB(TX_IPFIL_TBL), 331 REGISTER_TABLE_BB(TX_SRC_MAC_TBL), 332 REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER), 333 REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL), 334 REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER), 335 REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL), 336 REGISTER_TABLE_AA(EVQ_PTR_TBL_KER), 337 REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL), 338 /* We can't reasonably read all of the buffer table (up to 8MB!). 339 * However this driver will only use a few entries. Reading 340 * 1K entries allows for some expansion of queue count and 341 * size before we need to change the version. */ 342 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER, 343 A, A, 8, 1024), 344 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL, 345 B, Z, 8, 1024), 346 REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0), 347 REGISTER_TABLE_BB_CZ(TIMER_TBL), 348 REGISTER_TABLE_BB_CZ(TX_PACE_TBL), 349 REGISTER_TABLE_BZ(RX_INDIRECTION_TBL), 350 /* TX_FILTER_TBL0 is huge and not used by this driver */ 351 REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0), 352 REGISTER_TABLE_CZ(MC_TREG_SMEM), 353 /* MSIX_PBA_TABLE is not mapped */ 354 /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */ 355 REGISTER_TABLE_BZ(RX_FILTER_TBL0), 356 }; 357 358 size_t efx_nic_get_regs_len(struct efx_nic *efx) 359 { 360 const struct efx_nic_reg *reg; 361 const struct efx_nic_reg_table *table; 362 size_t len = 0; 363 364 for (reg = efx_nic_regs; 365 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs); 366 reg++) 367 if (efx->type->revision >= reg->min_revision && 368 efx->type->revision <= reg->max_revision) 369 len += sizeof(efx_oword_t); 370 371 for (table = efx_nic_reg_tables; 372 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables); 373 table++) 374 if (efx->type->revision >= table->min_revision && 375 efx->type->revision <= table->max_revision) 376 len += table->rows * min_t(size_t, table->step, 16); 377 378 return len; 379 } 380 381 void efx_nic_get_regs(struct efx_nic *efx, void *buf) 382 { 383 const struct efx_nic_reg *reg; 384 const struct efx_nic_reg_table *table; 385 386 for (reg = efx_nic_regs; 387 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs); 388 reg++) { 389 if (efx->type->revision >= reg->min_revision && 390 efx->type->revision <= reg->max_revision) { 391 efx_reado(efx, (efx_oword_t *)buf, reg->offset); 392 buf += sizeof(efx_oword_t); 393 } 394 } 395 396 for (table = efx_nic_reg_tables; 397 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables); 398 table++) { 399 size_t size, i; 400 401 if (!(efx->type->revision >= table->min_revision && 402 efx->type->revision <= table->max_revision)) 403 continue; 404 405 size = min_t(size_t, table->step, 16); 406 407 for (i = 0; i < table->rows; i++) { 408 switch (table->step) { 409 case 4: /* 32-bit SRAM */ 410 efx_readd(efx, buf, table->offset + 4 * i); 411 break; 412 case 8: /* 64-bit SRAM */ 413 efx_sram_readq(efx, 414 efx->membase + table->offset, 415 buf, i); 416 break; 417 case 16: /* 128-bit-readable register */ 418 efx_reado_table(efx, buf, table->offset, i); 419 break; 420 case 32: /* 128-bit register, interleaved */ 421 efx_reado_table(efx, buf, table->offset, 2 * i); 422 break; 423 default: 424 WARN_ON(1); 425 return; 426 } 427 buf += size; 428 } 429 } 430 } 431 432 /** 433 * efx_nic_describe_stats - Describe supported statistics for ethtool 434 * @desc: Array of &struct efx_hw_stat_desc describing the statistics 435 * @count: Length of the @desc array 436 * @mask: Bitmask of which elements of @desc are enabled 437 * @names: Buffer to copy names to, or %NULL. The names are copied 438 * starting at intervals of %ETH_GSTRING_LEN bytes. 439 * 440 * Returns the number of visible statistics, i.e. the number of set 441 * bits in the first @count bits of @mask for which a name is defined. 442 */ 443 size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count, 444 const unsigned long *mask, u8 *names) 445 { 446 size_t visible = 0; 447 size_t index; 448 449 for_each_set_bit(index, mask, count) { 450 if (desc[index].name) { 451 if (names) { 452 strlcpy(names, desc[index].name, 453 ETH_GSTRING_LEN); 454 names += ETH_GSTRING_LEN; 455 } 456 ++visible; 457 } 458 } 459 460 return visible; 461 } 462 463 /** 464 * efx_nic_update_stats - Convert statistics DMA buffer to array of u64 465 * @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer 466 * layout. DMA widths of 0, 16, 32 and 64 are supported; where 467 * the width is specified as 0 the corresponding element of 468 * @stats is not updated. 469 * @count: Length of the @desc array 470 * @mask: Bitmask of which elements of @desc are enabled 471 * @stats: Buffer to update with the converted statistics. The length 472 * of this array must be at least the number of set bits in the 473 * first @count bits of @mask. 474 * @dma_buf: DMA buffer containing hardware statistics 475 * @accumulate: If set, the converted values will be added rather than 476 * directly stored to the corresponding elements of @stats 477 */ 478 void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count, 479 const unsigned long *mask, 480 u64 *stats, const void *dma_buf, bool accumulate) 481 { 482 size_t index; 483 484 for_each_set_bit(index, mask, count) { 485 if (desc[index].dma_width) { 486 const void *addr = dma_buf + desc[index].offset; 487 u64 val; 488 489 switch (desc[index].dma_width) { 490 case 16: 491 val = le16_to_cpup((__le16 *)addr); 492 break; 493 case 32: 494 val = le32_to_cpup((__le32 *)addr); 495 break; 496 case 64: 497 val = le64_to_cpup((__le64 *)addr); 498 break; 499 default: 500 WARN_ON(1); 501 val = 0; 502 break; 503 } 504 505 if (accumulate) 506 *stats += val; 507 else 508 *stats = val; 509 } 510 511 ++stats; 512 } 513 } 514