1874aeea5SJeff Kirsher /**************************************************************************** 2874aeea5SJeff Kirsher * Driver for Solarflare Solarstorm network controllers and boards 3874aeea5SJeff Kirsher * Copyright 2005-2006 Fen Systems Ltd. 4874aeea5SJeff Kirsher * Copyright 2006-2011 Solarflare Communications Inc. 5874aeea5SJeff Kirsher * 6874aeea5SJeff Kirsher * This program is free software; you can redistribute it and/or modify it 7874aeea5SJeff Kirsher * under the terms of the GNU General Public License version 2 as published 8874aeea5SJeff Kirsher * by the Free Software Foundation, incorporated herein by reference. 9874aeea5SJeff Kirsher */ 10874aeea5SJeff Kirsher 11874aeea5SJeff Kirsher #include <linux/bitops.h> 12874aeea5SJeff Kirsher #include <linux/delay.h> 13874aeea5SJeff Kirsher #include <linux/interrupt.h> 14874aeea5SJeff Kirsher #include <linux/pci.h> 15874aeea5SJeff Kirsher #include <linux/module.h> 16874aeea5SJeff Kirsher #include <linux/seq_file.h> 17874aeea5SJeff Kirsher #include "net_driver.h" 18874aeea5SJeff Kirsher #include "bitfield.h" 19874aeea5SJeff Kirsher #include "efx.h" 20874aeea5SJeff Kirsher #include "nic.h" 21874aeea5SJeff Kirsher #include "regs.h" 22874aeea5SJeff Kirsher #include "io.h" 23874aeea5SJeff Kirsher #include "workarounds.h" 24874aeea5SJeff Kirsher 25874aeea5SJeff Kirsher /************************************************************************** 26874aeea5SJeff Kirsher * 27874aeea5SJeff Kirsher * Configurable values 28874aeea5SJeff Kirsher * 29874aeea5SJeff Kirsher ************************************************************************** 30874aeea5SJeff Kirsher */ 31874aeea5SJeff Kirsher 32874aeea5SJeff Kirsher /* This is set to 16 for a good reason. In summary, if larger than 33874aeea5SJeff Kirsher * 16, the descriptor cache holds more than a default socket 34874aeea5SJeff Kirsher * buffer's worth of packets (for UDP we can only have at most one 35874aeea5SJeff Kirsher * socket buffer's worth outstanding). This combined with the fact 36874aeea5SJeff Kirsher * that we only get 1 TX event per descriptor cache means the NIC 37874aeea5SJeff Kirsher * goes idle. 38874aeea5SJeff Kirsher */ 39874aeea5SJeff Kirsher #define TX_DC_ENTRIES 16 40874aeea5SJeff Kirsher #define TX_DC_ENTRIES_ORDER 1 41874aeea5SJeff Kirsher 42874aeea5SJeff Kirsher #define RX_DC_ENTRIES 64 43874aeea5SJeff Kirsher #define RX_DC_ENTRIES_ORDER 3 44874aeea5SJeff Kirsher 45874aeea5SJeff Kirsher /* If EFX_MAX_INT_ERRORS internal errors occur within 46874aeea5SJeff Kirsher * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and 47874aeea5SJeff Kirsher * disable it. 48874aeea5SJeff Kirsher */ 49874aeea5SJeff Kirsher #define EFX_INT_ERROR_EXPIRE 3600 50874aeea5SJeff Kirsher #define EFX_MAX_INT_ERRORS 5 51874aeea5SJeff Kirsher 52874aeea5SJeff Kirsher /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times 53874aeea5SJeff Kirsher */ 54874aeea5SJeff Kirsher #define EFX_FLUSH_INTERVAL 10 55874aeea5SJeff Kirsher #define EFX_FLUSH_POLL_COUNT 100 56874aeea5SJeff Kirsher 57874aeea5SJeff Kirsher /* Depth of RX flush request fifo */ 58874aeea5SJeff Kirsher #define EFX_RX_FLUSH_COUNT 4 59874aeea5SJeff Kirsher 60874aeea5SJeff Kirsher /* Generated event code for efx_generate_test_event() */ 61874aeea5SJeff Kirsher #define EFX_CHANNEL_MAGIC_TEST(_channel) \ 62874aeea5SJeff Kirsher (0x00010100 + (_channel)->channel) 63874aeea5SJeff Kirsher 64874aeea5SJeff Kirsher /* Generated event code for efx_generate_fill_event() */ 65874aeea5SJeff Kirsher #define EFX_CHANNEL_MAGIC_FILL(_channel) \ 66874aeea5SJeff Kirsher (0x00010200 + (_channel)->channel) 67874aeea5SJeff Kirsher 68874aeea5SJeff Kirsher /************************************************************************** 69874aeea5SJeff Kirsher * 70874aeea5SJeff Kirsher * Solarstorm hardware access 71874aeea5SJeff Kirsher * 72874aeea5SJeff Kirsher **************************************************************************/ 73874aeea5SJeff Kirsher 74874aeea5SJeff Kirsher static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value, 75874aeea5SJeff Kirsher unsigned int index) 76874aeea5SJeff Kirsher { 77874aeea5SJeff Kirsher efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base, 78874aeea5SJeff Kirsher value, index); 79874aeea5SJeff Kirsher } 80874aeea5SJeff Kirsher 81874aeea5SJeff Kirsher /* Read the current event from the event queue */ 82874aeea5SJeff Kirsher static inline efx_qword_t *efx_event(struct efx_channel *channel, 83874aeea5SJeff Kirsher unsigned int index) 84874aeea5SJeff Kirsher { 85874aeea5SJeff Kirsher return ((efx_qword_t *) (channel->eventq.addr)) + 86874aeea5SJeff Kirsher (index & channel->eventq_mask); 87874aeea5SJeff Kirsher } 88874aeea5SJeff Kirsher 89874aeea5SJeff Kirsher /* See if an event is present 90874aeea5SJeff Kirsher * 91874aeea5SJeff Kirsher * We check both the high and low dword of the event for all ones. We 92874aeea5SJeff Kirsher * wrote all ones when we cleared the event, and no valid event can 93874aeea5SJeff Kirsher * have all ones in either its high or low dwords. This approach is 94874aeea5SJeff Kirsher * robust against reordering. 95874aeea5SJeff Kirsher * 96874aeea5SJeff Kirsher * Note that using a single 64-bit comparison is incorrect; even 97874aeea5SJeff Kirsher * though the CPU read will be atomic, the DMA write may not be. 98874aeea5SJeff Kirsher */ 99874aeea5SJeff Kirsher static inline int efx_event_present(efx_qword_t *event) 100874aeea5SJeff Kirsher { 101874aeea5SJeff Kirsher return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | 102874aeea5SJeff Kirsher EFX_DWORD_IS_ALL_ONES(event->dword[1])); 103874aeea5SJeff Kirsher } 104874aeea5SJeff Kirsher 105874aeea5SJeff Kirsher static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b, 106874aeea5SJeff Kirsher const efx_oword_t *mask) 107874aeea5SJeff Kirsher { 108874aeea5SJeff Kirsher return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) || 109874aeea5SJeff Kirsher ((a->u64[1] ^ b->u64[1]) & mask->u64[1]); 110874aeea5SJeff Kirsher } 111874aeea5SJeff Kirsher 112874aeea5SJeff Kirsher int efx_nic_test_registers(struct efx_nic *efx, 113874aeea5SJeff Kirsher const struct efx_nic_register_test *regs, 114874aeea5SJeff Kirsher size_t n_regs) 115874aeea5SJeff Kirsher { 116874aeea5SJeff Kirsher unsigned address = 0, i, j; 117874aeea5SJeff Kirsher efx_oword_t mask, imask, original, reg, buf; 118874aeea5SJeff Kirsher 119874aeea5SJeff Kirsher /* Falcon should be in loopback to isolate the XMAC from the PHY */ 120874aeea5SJeff Kirsher WARN_ON(!LOOPBACK_INTERNAL(efx)); 121874aeea5SJeff Kirsher 122874aeea5SJeff Kirsher for (i = 0; i < n_regs; ++i) { 123874aeea5SJeff Kirsher address = regs[i].address; 124874aeea5SJeff Kirsher mask = imask = regs[i].mask; 125874aeea5SJeff Kirsher EFX_INVERT_OWORD(imask); 126874aeea5SJeff Kirsher 127874aeea5SJeff Kirsher efx_reado(efx, &original, address); 128874aeea5SJeff Kirsher 129874aeea5SJeff Kirsher /* bit sweep on and off */ 130874aeea5SJeff Kirsher for (j = 0; j < 128; j++) { 131874aeea5SJeff Kirsher if (!EFX_EXTRACT_OWORD32(mask, j, j)) 132874aeea5SJeff Kirsher continue; 133874aeea5SJeff Kirsher 134874aeea5SJeff Kirsher /* Test this testable bit can be set in isolation */ 135874aeea5SJeff Kirsher EFX_AND_OWORD(reg, original, mask); 136874aeea5SJeff Kirsher EFX_SET_OWORD32(reg, j, j, 1); 137874aeea5SJeff Kirsher 138874aeea5SJeff Kirsher efx_writeo(efx, ®, address); 139874aeea5SJeff Kirsher efx_reado(efx, &buf, address); 140874aeea5SJeff Kirsher 141874aeea5SJeff Kirsher if (efx_masked_compare_oword(®, &buf, &mask)) 142874aeea5SJeff Kirsher goto fail; 143874aeea5SJeff Kirsher 144874aeea5SJeff Kirsher /* Test this testable bit can be cleared in isolation */ 145874aeea5SJeff Kirsher EFX_OR_OWORD(reg, original, mask); 146874aeea5SJeff Kirsher EFX_SET_OWORD32(reg, j, j, 0); 147874aeea5SJeff Kirsher 148874aeea5SJeff Kirsher efx_writeo(efx, ®, address); 149874aeea5SJeff Kirsher efx_reado(efx, &buf, address); 150874aeea5SJeff Kirsher 151874aeea5SJeff Kirsher if (efx_masked_compare_oword(®, &buf, &mask)) 152874aeea5SJeff Kirsher goto fail; 153874aeea5SJeff Kirsher } 154874aeea5SJeff Kirsher 155874aeea5SJeff Kirsher efx_writeo(efx, &original, address); 156874aeea5SJeff Kirsher } 157874aeea5SJeff Kirsher 158874aeea5SJeff Kirsher return 0; 159874aeea5SJeff Kirsher 160874aeea5SJeff Kirsher fail: 161874aeea5SJeff Kirsher netif_err(efx, hw, efx->net_dev, 162874aeea5SJeff Kirsher "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT 163874aeea5SJeff Kirsher " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg), 164874aeea5SJeff Kirsher EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask)); 165874aeea5SJeff Kirsher return -EIO; 166874aeea5SJeff Kirsher } 167874aeea5SJeff Kirsher 168874aeea5SJeff Kirsher /************************************************************************** 169874aeea5SJeff Kirsher * 170874aeea5SJeff Kirsher * Special buffer handling 171874aeea5SJeff Kirsher * Special buffers are used for event queues and the TX and RX 172874aeea5SJeff Kirsher * descriptor rings. 173874aeea5SJeff Kirsher * 174874aeea5SJeff Kirsher *************************************************************************/ 175874aeea5SJeff Kirsher 176874aeea5SJeff Kirsher /* 177874aeea5SJeff Kirsher * Initialise a special buffer 178874aeea5SJeff Kirsher * 179874aeea5SJeff Kirsher * This will define a buffer (previously allocated via 180874aeea5SJeff Kirsher * efx_alloc_special_buffer()) in the buffer table, allowing 181874aeea5SJeff Kirsher * it to be used for event queues, descriptor rings etc. 182874aeea5SJeff Kirsher */ 183874aeea5SJeff Kirsher static void 184874aeea5SJeff Kirsher efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer) 185874aeea5SJeff Kirsher { 186874aeea5SJeff Kirsher efx_qword_t buf_desc; 187874aeea5SJeff Kirsher int index; 188874aeea5SJeff Kirsher dma_addr_t dma_addr; 189874aeea5SJeff Kirsher int i; 190874aeea5SJeff Kirsher 191874aeea5SJeff Kirsher EFX_BUG_ON_PARANOID(!buffer->addr); 192874aeea5SJeff Kirsher 193874aeea5SJeff Kirsher /* Write buffer descriptors to NIC */ 194874aeea5SJeff Kirsher for (i = 0; i < buffer->entries; i++) { 195874aeea5SJeff Kirsher index = buffer->index + i; 1965b6262d0SBen Hutchings dma_addr = buffer->dma_addr + (i * EFX_BUF_SIZE); 197874aeea5SJeff Kirsher netif_dbg(efx, probe, efx->net_dev, 198874aeea5SJeff Kirsher "mapping special buffer %d at %llx\n", 199874aeea5SJeff Kirsher index, (unsigned long long)dma_addr); 200874aeea5SJeff Kirsher EFX_POPULATE_QWORD_3(buf_desc, 201874aeea5SJeff Kirsher FRF_AZ_BUF_ADR_REGION, 0, 202874aeea5SJeff Kirsher FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12, 203874aeea5SJeff Kirsher FRF_AZ_BUF_OWNER_ID_FBUF, 0); 204874aeea5SJeff Kirsher efx_write_buf_tbl(efx, &buf_desc, index); 205874aeea5SJeff Kirsher } 206874aeea5SJeff Kirsher } 207874aeea5SJeff Kirsher 208874aeea5SJeff Kirsher /* Unmaps a buffer and clears the buffer table entries */ 209874aeea5SJeff Kirsher static void 210874aeea5SJeff Kirsher efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer) 211874aeea5SJeff Kirsher { 212874aeea5SJeff Kirsher efx_oword_t buf_tbl_upd; 213874aeea5SJeff Kirsher unsigned int start = buffer->index; 214874aeea5SJeff Kirsher unsigned int end = (buffer->index + buffer->entries - 1); 215874aeea5SJeff Kirsher 216874aeea5SJeff Kirsher if (!buffer->entries) 217874aeea5SJeff Kirsher return; 218874aeea5SJeff Kirsher 219874aeea5SJeff Kirsher netif_dbg(efx, hw, efx->net_dev, "unmapping special buffers %d-%d\n", 220874aeea5SJeff Kirsher buffer->index, buffer->index + buffer->entries - 1); 221874aeea5SJeff Kirsher 222874aeea5SJeff Kirsher EFX_POPULATE_OWORD_4(buf_tbl_upd, 223874aeea5SJeff Kirsher FRF_AZ_BUF_UPD_CMD, 0, 224874aeea5SJeff Kirsher FRF_AZ_BUF_CLR_CMD, 1, 225874aeea5SJeff Kirsher FRF_AZ_BUF_CLR_END_ID, end, 226874aeea5SJeff Kirsher FRF_AZ_BUF_CLR_START_ID, start); 227874aeea5SJeff Kirsher efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD); 228874aeea5SJeff Kirsher } 229874aeea5SJeff Kirsher 230874aeea5SJeff Kirsher /* 231874aeea5SJeff Kirsher * Allocate a new special buffer 232874aeea5SJeff Kirsher * 233874aeea5SJeff Kirsher * This allocates memory for a new buffer, clears it and allocates a 234874aeea5SJeff Kirsher * new buffer ID range. It does not write into the buffer table. 235874aeea5SJeff Kirsher * 236874aeea5SJeff Kirsher * This call will allocate 4KB buffers, since 8KB buffers can't be 237874aeea5SJeff Kirsher * used for event queues and descriptor rings. 238874aeea5SJeff Kirsher */ 239874aeea5SJeff Kirsher static int efx_alloc_special_buffer(struct efx_nic *efx, 240874aeea5SJeff Kirsher struct efx_special_buffer *buffer, 241874aeea5SJeff Kirsher unsigned int len) 242874aeea5SJeff Kirsher { 243874aeea5SJeff Kirsher len = ALIGN(len, EFX_BUF_SIZE); 244874aeea5SJeff Kirsher 245874aeea5SJeff Kirsher buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len, 246874aeea5SJeff Kirsher &buffer->dma_addr, GFP_KERNEL); 247874aeea5SJeff Kirsher if (!buffer->addr) 248874aeea5SJeff Kirsher return -ENOMEM; 249874aeea5SJeff Kirsher buffer->len = len; 250874aeea5SJeff Kirsher buffer->entries = len / EFX_BUF_SIZE; 251874aeea5SJeff Kirsher BUG_ON(buffer->dma_addr & (EFX_BUF_SIZE - 1)); 252874aeea5SJeff Kirsher 253874aeea5SJeff Kirsher /* All zeros is a potentially valid event so memset to 0xff */ 254874aeea5SJeff Kirsher memset(buffer->addr, 0xff, len); 255874aeea5SJeff Kirsher 256874aeea5SJeff Kirsher /* Select new buffer ID */ 257874aeea5SJeff Kirsher buffer->index = efx->next_buffer_table; 258874aeea5SJeff Kirsher efx->next_buffer_table += buffer->entries; 259874aeea5SJeff Kirsher 260874aeea5SJeff Kirsher netif_dbg(efx, probe, efx->net_dev, 261874aeea5SJeff Kirsher "allocating special buffers %d-%d at %llx+%x " 262874aeea5SJeff Kirsher "(virt %p phys %llx)\n", buffer->index, 263874aeea5SJeff Kirsher buffer->index + buffer->entries - 1, 264874aeea5SJeff Kirsher (u64)buffer->dma_addr, len, 265874aeea5SJeff Kirsher buffer->addr, (u64)virt_to_phys(buffer->addr)); 266874aeea5SJeff Kirsher 267874aeea5SJeff Kirsher return 0; 268874aeea5SJeff Kirsher } 269874aeea5SJeff Kirsher 270874aeea5SJeff Kirsher static void 271874aeea5SJeff Kirsher efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer) 272874aeea5SJeff Kirsher { 273874aeea5SJeff Kirsher if (!buffer->addr) 274874aeea5SJeff Kirsher return; 275874aeea5SJeff Kirsher 276874aeea5SJeff Kirsher netif_dbg(efx, hw, efx->net_dev, 277874aeea5SJeff Kirsher "deallocating special buffers %d-%d at %llx+%x " 278874aeea5SJeff Kirsher "(virt %p phys %llx)\n", buffer->index, 279874aeea5SJeff Kirsher buffer->index + buffer->entries - 1, 280874aeea5SJeff Kirsher (u64)buffer->dma_addr, buffer->len, 281874aeea5SJeff Kirsher buffer->addr, (u64)virt_to_phys(buffer->addr)); 282874aeea5SJeff Kirsher 283874aeea5SJeff Kirsher dma_free_coherent(&efx->pci_dev->dev, buffer->len, buffer->addr, 284874aeea5SJeff Kirsher buffer->dma_addr); 285874aeea5SJeff Kirsher buffer->addr = NULL; 286874aeea5SJeff Kirsher buffer->entries = 0; 287874aeea5SJeff Kirsher } 288874aeea5SJeff Kirsher 289874aeea5SJeff Kirsher /************************************************************************** 290874aeea5SJeff Kirsher * 291874aeea5SJeff Kirsher * Generic buffer handling 292874aeea5SJeff Kirsher * These buffers are used for interrupt status and MAC stats 293874aeea5SJeff Kirsher * 294874aeea5SJeff Kirsher **************************************************************************/ 295874aeea5SJeff Kirsher 296874aeea5SJeff Kirsher int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, 297874aeea5SJeff Kirsher unsigned int len) 298874aeea5SJeff Kirsher { 299874aeea5SJeff Kirsher buffer->addr = pci_alloc_consistent(efx->pci_dev, len, 300874aeea5SJeff Kirsher &buffer->dma_addr); 301874aeea5SJeff Kirsher if (!buffer->addr) 302874aeea5SJeff Kirsher return -ENOMEM; 303874aeea5SJeff Kirsher buffer->len = len; 304874aeea5SJeff Kirsher memset(buffer->addr, 0, len); 305874aeea5SJeff Kirsher return 0; 306874aeea5SJeff Kirsher } 307874aeea5SJeff Kirsher 308874aeea5SJeff Kirsher void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer) 309874aeea5SJeff Kirsher { 310874aeea5SJeff Kirsher if (buffer->addr) { 311874aeea5SJeff Kirsher pci_free_consistent(efx->pci_dev, buffer->len, 312874aeea5SJeff Kirsher buffer->addr, buffer->dma_addr); 313874aeea5SJeff Kirsher buffer->addr = NULL; 314874aeea5SJeff Kirsher } 315874aeea5SJeff Kirsher } 316874aeea5SJeff Kirsher 317874aeea5SJeff Kirsher /************************************************************************** 318874aeea5SJeff Kirsher * 319874aeea5SJeff Kirsher * TX path 320874aeea5SJeff Kirsher * 321874aeea5SJeff Kirsher **************************************************************************/ 322874aeea5SJeff Kirsher 323874aeea5SJeff Kirsher /* Returns a pointer to the specified transmit descriptor in the TX 324874aeea5SJeff Kirsher * descriptor queue belonging to the specified channel. 325874aeea5SJeff Kirsher */ 326874aeea5SJeff Kirsher static inline efx_qword_t * 327874aeea5SJeff Kirsher efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index) 328874aeea5SJeff Kirsher { 329874aeea5SJeff Kirsher return ((efx_qword_t *) (tx_queue->txd.addr)) + index; 330874aeea5SJeff Kirsher } 331874aeea5SJeff Kirsher 332874aeea5SJeff Kirsher /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 333874aeea5SJeff Kirsher static inline void efx_notify_tx_desc(struct efx_tx_queue *tx_queue) 334874aeea5SJeff Kirsher { 335874aeea5SJeff Kirsher unsigned write_ptr; 336874aeea5SJeff Kirsher efx_dword_t reg; 337874aeea5SJeff Kirsher 338874aeea5SJeff Kirsher write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 339874aeea5SJeff Kirsher EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr); 340874aeea5SJeff Kirsher efx_writed_page(tx_queue->efx, ®, 341874aeea5SJeff Kirsher FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue); 342874aeea5SJeff Kirsher } 343874aeea5SJeff Kirsher 344874aeea5SJeff Kirsher /* Write pointer and first descriptor for TX descriptor ring */ 345874aeea5SJeff Kirsher static inline void efx_push_tx_desc(struct efx_tx_queue *tx_queue, 346874aeea5SJeff Kirsher const efx_qword_t *txd) 347874aeea5SJeff Kirsher { 348874aeea5SJeff Kirsher unsigned write_ptr; 349874aeea5SJeff Kirsher efx_oword_t reg; 350874aeea5SJeff Kirsher 351874aeea5SJeff Kirsher BUILD_BUG_ON(FRF_AZ_TX_DESC_LBN != 0); 352874aeea5SJeff Kirsher BUILD_BUG_ON(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0); 353874aeea5SJeff Kirsher 354874aeea5SJeff Kirsher write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 355874aeea5SJeff Kirsher EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true, 356874aeea5SJeff Kirsher FRF_AZ_TX_DESC_WPTR, write_ptr); 357874aeea5SJeff Kirsher reg.qword[0] = *txd; 358874aeea5SJeff Kirsher efx_writeo_page(tx_queue->efx, ®, 359874aeea5SJeff Kirsher FR_BZ_TX_DESC_UPD_P0, tx_queue->queue); 360874aeea5SJeff Kirsher } 361874aeea5SJeff Kirsher 362874aeea5SJeff Kirsher static inline bool 363874aeea5SJeff Kirsher efx_may_push_tx_desc(struct efx_tx_queue *tx_queue, unsigned int write_count) 364874aeea5SJeff Kirsher { 365874aeea5SJeff Kirsher unsigned empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count); 366874aeea5SJeff Kirsher 367874aeea5SJeff Kirsher if (empty_read_count == 0) 368874aeea5SJeff Kirsher return false; 369874aeea5SJeff Kirsher 370874aeea5SJeff Kirsher tx_queue->empty_read_count = 0; 371874aeea5SJeff Kirsher return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0; 372874aeea5SJeff Kirsher } 373874aeea5SJeff Kirsher 374874aeea5SJeff Kirsher /* For each entry inserted into the software descriptor ring, create a 375874aeea5SJeff Kirsher * descriptor in the hardware TX descriptor ring (in host memory), and 376874aeea5SJeff Kirsher * write a doorbell. 377874aeea5SJeff Kirsher */ 378874aeea5SJeff Kirsher void efx_nic_push_buffers(struct efx_tx_queue *tx_queue) 379874aeea5SJeff Kirsher { 380874aeea5SJeff Kirsher 381874aeea5SJeff Kirsher struct efx_tx_buffer *buffer; 382874aeea5SJeff Kirsher efx_qword_t *txd; 383874aeea5SJeff Kirsher unsigned write_ptr; 384874aeea5SJeff Kirsher unsigned old_write_count = tx_queue->write_count; 385874aeea5SJeff Kirsher 386874aeea5SJeff Kirsher BUG_ON(tx_queue->write_count == tx_queue->insert_count); 387874aeea5SJeff Kirsher 388874aeea5SJeff Kirsher do { 389874aeea5SJeff Kirsher write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 390874aeea5SJeff Kirsher buffer = &tx_queue->buffer[write_ptr]; 391874aeea5SJeff Kirsher txd = efx_tx_desc(tx_queue, write_ptr); 392874aeea5SJeff Kirsher ++tx_queue->write_count; 393874aeea5SJeff Kirsher 394874aeea5SJeff Kirsher /* Create TX descriptor ring entry */ 395874aeea5SJeff Kirsher EFX_POPULATE_QWORD_4(*txd, 396874aeea5SJeff Kirsher FSF_AZ_TX_KER_CONT, buffer->continuation, 397874aeea5SJeff Kirsher FSF_AZ_TX_KER_BYTE_COUNT, buffer->len, 398874aeea5SJeff Kirsher FSF_AZ_TX_KER_BUF_REGION, 0, 399874aeea5SJeff Kirsher FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr); 400874aeea5SJeff Kirsher } while (tx_queue->write_count != tx_queue->insert_count); 401874aeea5SJeff Kirsher 402874aeea5SJeff Kirsher wmb(); /* Ensure descriptors are written before they are fetched */ 403874aeea5SJeff Kirsher 404874aeea5SJeff Kirsher if (efx_may_push_tx_desc(tx_queue, old_write_count)) { 405874aeea5SJeff Kirsher txd = efx_tx_desc(tx_queue, 406874aeea5SJeff Kirsher old_write_count & tx_queue->ptr_mask); 407874aeea5SJeff Kirsher efx_push_tx_desc(tx_queue, txd); 408874aeea5SJeff Kirsher ++tx_queue->pushes; 409874aeea5SJeff Kirsher } else { 410874aeea5SJeff Kirsher efx_notify_tx_desc(tx_queue); 411874aeea5SJeff Kirsher } 412874aeea5SJeff Kirsher } 413874aeea5SJeff Kirsher 414874aeea5SJeff Kirsher /* Allocate hardware resources for a TX queue */ 415874aeea5SJeff Kirsher int efx_nic_probe_tx(struct efx_tx_queue *tx_queue) 416874aeea5SJeff Kirsher { 417874aeea5SJeff Kirsher struct efx_nic *efx = tx_queue->efx; 418874aeea5SJeff Kirsher unsigned entries; 419874aeea5SJeff Kirsher 420874aeea5SJeff Kirsher entries = tx_queue->ptr_mask + 1; 421874aeea5SJeff Kirsher return efx_alloc_special_buffer(efx, &tx_queue->txd, 422874aeea5SJeff Kirsher entries * sizeof(efx_qword_t)); 423874aeea5SJeff Kirsher } 424874aeea5SJeff Kirsher 425874aeea5SJeff Kirsher void efx_nic_init_tx(struct efx_tx_queue *tx_queue) 426874aeea5SJeff Kirsher { 427874aeea5SJeff Kirsher struct efx_nic *efx = tx_queue->efx; 428874aeea5SJeff Kirsher efx_oword_t reg; 429874aeea5SJeff Kirsher 430874aeea5SJeff Kirsher tx_queue->flushed = FLUSH_NONE; 431874aeea5SJeff Kirsher 432874aeea5SJeff Kirsher /* Pin TX descriptor ring */ 433874aeea5SJeff Kirsher efx_init_special_buffer(efx, &tx_queue->txd); 434874aeea5SJeff Kirsher 435874aeea5SJeff Kirsher /* Push TX descriptor ring to card */ 436874aeea5SJeff Kirsher EFX_POPULATE_OWORD_10(reg, 437874aeea5SJeff Kirsher FRF_AZ_TX_DESCQ_EN, 1, 438874aeea5SJeff Kirsher FRF_AZ_TX_ISCSI_DDIG_EN, 0, 439874aeea5SJeff Kirsher FRF_AZ_TX_ISCSI_HDIG_EN, 0, 440874aeea5SJeff Kirsher FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index, 441874aeea5SJeff Kirsher FRF_AZ_TX_DESCQ_EVQ_ID, 442874aeea5SJeff Kirsher tx_queue->channel->channel, 443874aeea5SJeff Kirsher FRF_AZ_TX_DESCQ_OWNER_ID, 0, 444874aeea5SJeff Kirsher FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue, 445874aeea5SJeff Kirsher FRF_AZ_TX_DESCQ_SIZE, 446874aeea5SJeff Kirsher __ffs(tx_queue->txd.entries), 447874aeea5SJeff Kirsher FRF_AZ_TX_DESCQ_TYPE, 0, 448874aeea5SJeff Kirsher FRF_BZ_TX_NON_IP_DROP_DIS, 1); 449874aeea5SJeff Kirsher 450874aeea5SJeff Kirsher if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { 451874aeea5SJeff Kirsher int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; 452874aeea5SJeff Kirsher EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum); 453874aeea5SJeff Kirsher EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS, 454874aeea5SJeff Kirsher !csum); 455874aeea5SJeff Kirsher } 456874aeea5SJeff Kirsher 457874aeea5SJeff Kirsher efx_writeo_table(efx, ®, efx->type->txd_ptr_tbl_base, 458874aeea5SJeff Kirsher tx_queue->queue); 459874aeea5SJeff Kirsher 460874aeea5SJeff Kirsher if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) { 461874aeea5SJeff Kirsher /* Only 128 bits in this register */ 462874aeea5SJeff Kirsher BUILD_BUG_ON(EFX_MAX_TX_QUEUES > 128); 463874aeea5SJeff Kirsher 464874aeea5SJeff Kirsher efx_reado(efx, ®, FR_AA_TX_CHKSM_CFG); 465874aeea5SJeff Kirsher if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) 466874aeea5SJeff Kirsher clear_bit_le(tx_queue->queue, (void *)®); 467874aeea5SJeff Kirsher else 468874aeea5SJeff Kirsher set_bit_le(tx_queue->queue, (void *)®); 469874aeea5SJeff Kirsher efx_writeo(efx, ®, FR_AA_TX_CHKSM_CFG); 470874aeea5SJeff Kirsher } 471874aeea5SJeff Kirsher 472874aeea5SJeff Kirsher if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { 473874aeea5SJeff Kirsher EFX_POPULATE_OWORD_1(reg, 474874aeea5SJeff Kirsher FRF_BZ_TX_PACE, 475874aeea5SJeff Kirsher (tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ? 476874aeea5SJeff Kirsher FFE_BZ_TX_PACE_OFF : 477874aeea5SJeff Kirsher FFE_BZ_TX_PACE_RESERVED); 478874aeea5SJeff Kirsher efx_writeo_table(efx, ®, FR_BZ_TX_PACE_TBL, 479874aeea5SJeff Kirsher tx_queue->queue); 480874aeea5SJeff Kirsher } 481874aeea5SJeff Kirsher } 482874aeea5SJeff Kirsher 483874aeea5SJeff Kirsher static void efx_flush_tx_queue(struct efx_tx_queue *tx_queue) 484874aeea5SJeff Kirsher { 485874aeea5SJeff Kirsher struct efx_nic *efx = tx_queue->efx; 486874aeea5SJeff Kirsher efx_oword_t tx_flush_descq; 487874aeea5SJeff Kirsher 488874aeea5SJeff Kirsher tx_queue->flushed = FLUSH_PENDING; 489874aeea5SJeff Kirsher 490874aeea5SJeff Kirsher /* Post a flush command */ 491874aeea5SJeff Kirsher EFX_POPULATE_OWORD_2(tx_flush_descq, 492874aeea5SJeff Kirsher FRF_AZ_TX_FLUSH_DESCQ_CMD, 1, 493874aeea5SJeff Kirsher FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue); 494874aeea5SJeff Kirsher efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ); 495874aeea5SJeff Kirsher } 496874aeea5SJeff Kirsher 497874aeea5SJeff Kirsher void efx_nic_fini_tx(struct efx_tx_queue *tx_queue) 498874aeea5SJeff Kirsher { 499874aeea5SJeff Kirsher struct efx_nic *efx = tx_queue->efx; 500874aeea5SJeff Kirsher efx_oword_t tx_desc_ptr; 501874aeea5SJeff Kirsher 502874aeea5SJeff Kirsher /* The queue should have been flushed */ 503874aeea5SJeff Kirsher WARN_ON(tx_queue->flushed != FLUSH_DONE); 504874aeea5SJeff Kirsher 505874aeea5SJeff Kirsher /* Remove TX descriptor ring from card */ 506874aeea5SJeff Kirsher EFX_ZERO_OWORD(tx_desc_ptr); 507874aeea5SJeff Kirsher efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, 508874aeea5SJeff Kirsher tx_queue->queue); 509874aeea5SJeff Kirsher 510874aeea5SJeff Kirsher /* Unpin TX descriptor ring */ 511874aeea5SJeff Kirsher efx_fini_special_buffer(efx, &tx_queue->txd); 512874aeea5SJeff Kirsher } 513874aeea5SJeff Kirsher 514874aeea5SJeff Kirsher /* Free buffers backing TX queue */ 515874aeea5SJeff Kirsher void efx_nic_remove_tx(struct efx_tx_queue *tx_queue) 516874aeea5SJeff Kirsher { 517874aeea5SJeff Kirsher efx_free_special_buffer(tx_queue->efx, &tx_queue->txd); 518874aeea5SJeff Kirsher } 519874aeea5SJeff Kirsher 520874aeea5SJeff Kirsher /************************************************************************** 521874aeea5SJeff Kirsher * 522874aeea5SJeff Kirsher * RX path 523874aeea5SJeff Kirsher * 524874aeea5SJeff Kirsher **************************************************************************/ 525874aeea5SJeff Kirsher 526874aeea5SJeff Kirsher /* Returns a pointer to the specified descriptor in the RX descriptor queue */ 527874aeea5SJeff Kirsher static inline efx_qword_t * 528874aeea5SJeff Kirsher efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 529874aeea5SJeff Kirsher { 530874aeea5SJeff Kirsher return ((efx_qword_t *) (rx_queue->rxd.addr)) + index; 531874aeea5SJeff Kirsher } 532874aeea5SJeff Kirsher 533874aeea5SJeff Kirsher /* This creates an entry in the RX descriptor queue */ 534874aeea5SJeff Kirsher static inline void 535874aeea5SJeff Kirsher efx_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index) 536874aeea5SJeff Kirsher { 537874aeea5SJeff Kirsher struct efx_rx_buffer *rx_buf; 538874aeea5SJeff Kirsher efx_qword_t *rxd; 539874aeea5SJeff Kirsher 540874aeea5SJeff Kirsher rxd = efx_rx_desc(rx_queue, index); 541874aeea5SJeff Kirsher rx_buf = efx_rx_buffer(rx_queue, index); 542874aeea5SJeff Kirsher EFX_POPULATE_QWORD_3(*rxd, 543874aeea5SJeff Kirsher FSF_AZ_RX_KER_BUF_SIZE, 544874aeea5SJeff Kirsher rx_buf->len - 545874aeea5SJeff Kirsher rx_queue->efx->type->rx_buffer_padding, 546874aeea5SJeff Kirsher FSF_AZ_RX_KER_BUF_REGION, 0, 547874aeea5SJeff Kirsher FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 548874aeea5SJeff Kirsher } 549874aeea5SJeff Kirsher 550874aeea5SJeff Kirsher /* This writes to the RX_DESC_WPTR register for the specified receive 551874aeea5SJeff Kirsher * descriptor ring. 552874aeea5SJeff Kirsher */ 553874aeea5SJeff Kirsher void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue) 554874aeea5SJeff Kirsher { 555874aeea5SJeff Kirsher struct efx_nic *efx = rx_queue->efx; 556874aeea5SJeff Kirsher efx_dword_t reg; 557874aeea5SJeff Kirsher unsigned write_ptr; 558874aeea5SJeff Kirsher 559874aeea5SJeff Kirsher while (rx_queue->notified_count != rx_queue->added_count) { 560874aeea5SJeff Kirsher efx_build_rx_desc( 561874aeea5SJeff Kirsher rx_queue, 562874aeea5SJeff Kirsher rx_queue->notified_count & rx_queue->ptr_mask); 563874aeea5SJeff Kirsher ++rx_queue->notified_count; 564874aeea5SJeff Kirsher } 565874aeea5SJeff Kirsher 566874aeea5SJeff Kirsher wmb(); 567874aeea5SJeff Kirsher write_ptr = rx_queue->added_count & rx_queue->ptr_mask; 568874aeea5SJeff Kirsher EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr); 569874aeea5SJeff Kirsher efx_writed_page(efx, ®, FR_AZ_RX_DESC_UPD_DWORD_P0, 570874aeea5SJeff Kirsher efx_rx_queue_index(rx_queue)); 571874aeea5SJeff Kirsher } 572874aeea5SJeff Kirsher 573874aeea5SJeff Kirsher int efx_nic_probe_rx(struct efx_rx_queue *rx_queue) 574874aeea5SJeff Kirsher { 575874aeea5SJeff Kirsher struct efx_nic *efx = rx_queue->efx; 576874aeea5SJeff Kirsher unsigned entries; 577874aeea5SJeff Kirsher 578874aeea5SJeff Kirsher entries = rx_queue->ptr_mask + 1; 579874aeea5SJeff Kirsher return efx_alloc_special_buffer(efx, &rx_queue->rxd, 580874aeea5SJeff Kirsher entries * sizeof(efx_qword_t)); 581874aeea5SJeff Kirsher } 582874aeea5SJeff Kirsher 583874aeea5SJeff Kirsher void efx_nic_init_rx(struct efx_rx_queue *rx_queue) 584874aeea5SJeff Kirsher { 585874aeea5SJeff Kirsher efx_oword_t rx_desc_ptr; 586874aeea5SJeff Kirsher struct efx_nic *efx = rx_queue->efx; 587874aeea5SJeff Kirsher bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0; 588874aeea5SJeff Kirsher bool iscsi_digest_en = is_b0; 589874aeea5SJeff Kirsher 590874aeea5SJeff Kirsher netif_dbg(efx, hw, efx->net_dev, 591874aeea5SJeff Kirsher "RX queue %d ring in special buffers %d-%d\n", 592874aeea5SJeff Kirsher efx_rx_queue_index(rx_queue), rx_queue->rxd.index, 593874aeea5SJeff Kirsher rx_queue->rxd.index + rx_queue->rxd.entries - 1); 594874aeea5SJeff Kirsher 595874aeea5SJeff Kirsher rx_queue->flushed = FLUSH_NONE; 596874aeea5SJeff Kirsher 597874aeea5SJeff Kirsher /* Pin RX descriptor ring */ 598874aeea5SJeff Kirsher efx_init_special_buffer(efx, &rx_queue->rxd); 599874aeea5SJeff Kirsher 600874aeea5SJeff Kirsher /* Push RX descriptor ring to card */ 601874aeea5SJeff Kirsher EFX_POPULATE_OWORD_10(rx_desc_ptr, 602874aeea5SJeff Kirsher FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en, 603874aeea5SJeff Kirsher FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en, 604874aeea5SJeff Kirsher FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index, 605874aeea5SJeff Kirsher FRF_AZ_RX_DESCQ_EVQ_ID, 606874aeea5SJeff Kirsher efx_rx_queue_channel(rx_queue)->channel, 607874aeea5SJeff Kirsher FRF_AZ_RX_DESCQ_OWNER_ID, 0, 608874aeea5SJeff Kirsher FRF_AZ_RX_DESCQ_LABEL, 609874aeea5SJeff Kirsher efx_rx_queue_index(rx_queue), 610874aeea5SJeff Kirsher FRF_AZ_RX_DESCQ_SIZE, 611874aeea5SJeff Kirsher __ffs(rx_queue->rxd.entries), 612874aeea5SJeff Kirsher FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ , 613874aeea5SJeff Kirsher /* For >=B0 this is scatter so disable */ 614874aeea5SJeff Kirsher FRF_AZ_RX_DESCQ_JUMBO, !is_b0, 615874aeea5SJeff Kirsher FRF_AZ_RX_DESCQ_EN, 1); 616874aeea5SJeff Kirsher efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, 617874aeea5SJeff Kirsher efx_rx_queue_index(rx_queue)); 618874aeea5SJeff Kirsher } 619874aeea5SJeff Kirsher 620874aeea5SJeff Kirsher static void efx_flush_rx_queue(struct efx_rx_queue *rx_queue) 621874aeea5SJeff Kirsher { 622874aeea5SJeff Kirsher struct efx_nic *efx = rx_queue->efx; 623874aeea5SJeff Kirsher efx_oword_t rx_flush_descq; 624874aeea5SJeff Kirsher 625874aeea5SJeff Kirsher rx_queue->flushed = FLUSH_PENDING; 626874aeea5SJeff Kirsher 627874aeea5SJeff Kirsher /* Post a flush command */ 628874aeea5SJeff Kirsher EFX_POPULATE_OWORD_2(rx_flush_descq, 629874aeea5SJeff Kirsher FRF_AZ_RX_FLUSH_DESCQ_CMD, 1, 630874aeea5SJeff Kirsher FRF_AZ_RX_FLUSH_DESCQ, 631874aeea5SJeff Kirsher efx_rx_queue_index(rx_queue)); 632874aeea5SJeff Kirsher efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ); 633874aeea5SJeff Kirsher } 634874aeea5SJeff Kirsher 635874aeea5SJeff Kirsher void efx_nic_fini_rx(struct efx_rx_queue *rx_queue) 636874aeea5SJeff Kirsher { 637874aeea5SJeff Kirsher efx_oword_t rx_desc_ptr; 638874aeea5SJeff Kirsher struct efx_nic *efx = rx_queue->efx; 639874aeea5SJeff Kirsher 640874aeea5SJeff Kirsher /* The queue should already have been flushed */ 641874aeea5SJeff Kirsher WARN_ON(rx_queue->flushed != FLUSH_DONE); 642874aeea5SJeff Kirsher 643874aeea5SJeff Kirsher /* Remove RX descriptor ring from card */ 644874aeea5SJeff Kirsher EFX_ZERO_OWORD(rx_desc_ptr); 645874aeea5SJeff Kirsher efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, 646874aeea5SJeff Kirsher efx_rx_queue_index(rx_queue)); 647874aeea5SJeff Kirsher 648874aeea5SJeff Kirsher /* Unpin RX descriptor ring */ 649874aeea5SJeff Kirsher efx_fini_special_buffer(efx, &rx_queue->rxd); 650874aeea5SJeff Kirsher } 651874aeea5SJeff Kirsher 652874aeea5SJeff Kirsher /* Free buffers backing RX queue */ 653874aeea5SJeff Kirsher void efx_nic_remove_rx(struct efx_rx_queue *rx_queue) 654874aeea5SJeff Kirsher { 655874aeea5SJeff Kirsher efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd); 656874aeea5SJeff Kirsher } 657874aeea5SJeff Kirsher 658874aeea5SJeff Kirsher /************************************************************************** 659874aeea5SJeff Kirsher * 660874aeea5SJeff Kirsher * Event queue processing 661874aeea5SJeff Kirsher * Event queues are processed by per-channel tasklets. 662874aeea5SJeff Kirsher * 663874aeea5SJeff Kirsher **************************************************************************/ 664874aeea5SJeff Kirsher 665874aeea5SJeff Kirsher /* Update a channel's event queue's read pointer (RPTR) register 666874aeea5SJeff Kirsher * 667874aeea5SJeff Kirsher * This writes the EVQ_RPTR_REG register for the specified channel's 668874aeea5SJeff Kirsher * event queue. 669874aeea5SJeff Kirsher */ 670874aeea5SJeff Kirsher void efx_nic_eventq_read_ack(struct efx_channel *channel) 671874aeea5SJeff Kirsher { 672874aeea5SJeff Kirsher efx_dword_t reg; 673874aeea5SJeff Kirsher struct efx_nic *efx = channel->efx; 674874aeea5SJeff Kirsher 675874aeea5SJeff Kirsher EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, 676874aeea5SJeff Kirsher channel->eventq_read_ptr & channel->eventq_mask); 677874aeea5SJeff Kirsher efx_writed_table(efx, ®, efx->type->evq_rptr_tbl_base, 678874aeea5SJeff Kirsher channel->channel); 679874aeea5SJeff Kirsher } 680874aeea5SJeff Kirsher 681874aeea5SJeff Kirsher /* Use HW to insert a SW defined event */ 682874aeea5SJeff Kirsher static void efx_generate_event(struct efx_channel *channel, efx_qword_t *event) 683874aeea5SJeff Kirsher { 684874aeea5SJeff Kirsher efx_oword_t drv_ev_reg; 685874aeea5SJeff Kirsher 686874aeea5SJeff Kirsher BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 || 687874aeea5SJeff Kirsher FRF_AZ_DRV_EV_DATA_WIDTH != 64); 688874aeea5SJeff Kirsher drv_ev_reg.u32[0] = event->u32[0]; 689874aeea5SJeff Kirsher drv_ev_reg.u32[1] = event->u32[1]; 690874aeea5SJeff Kirsher drv_ev_reg.u32[2] = 0; 691874aeea5SJeff Kirsher drv_ev_reg.u32[3] = 0; 692874aeea5SJeff Kirsher EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel); 693874aeea5SJeff Kirsher efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV); 694874aeea5SJeff Kirsher } 695874aeea5SJeff Kirsher 696874aeea5SJeff Kirsher /* Handle a transmit completion event 697874aeea5SJeff Kirsher * 698874aeea5SJeff Kirsher * The NIC batches TX completion events; the message we receive is of 699874aeea5SJeff Kirsher * the form "complete all TX events up to this index". 700874aeea5SJeff Kirsher */ 701874aeea5SJeff Kirsher static int 702874aeea5SJeff Kirsher efx_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 703874aeea5SJeff Kirsher { 704874aeea5SJeff Kirsher unsigned int tx_ev_desc_ptr; 705874aeea5SJeff Kirsher unsigned int tx_ev_q_label; 706874aeea5SJeff Kirsher struct efx_tx_queue *tx_queue; 707874aeea5SJeff Kirsher struct efx_nic *efx = channel->efx; 708874aeea5SJeff Kirsher int tx_packets = 0; 709874aeea5SJeff Kirsher 710874aeea5SJeff Kirsher if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) { 711874aeea5SJeff Kirsher /* Transmit completion */ 712874aeea5SJeff Kirsher tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR); 713874aeea5SJeff Kirsher tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); 714874aeea5SJeff Kirsher tx_queue = efx_channel_get_tx_queue( 715874aeea5SJeff Kirsher channel, tx_ev_q_label % EFX_TXQ_TYPES); 716874aeea5SJeff Kirsher tx_packets = ((tx_ev_desc_ptr - tx_queue->read_count) & 717874aeea5SJeff Kirsher tx_queue->ptr_mask); 718874aeea5SJeff Kirsher channel->irq_mod_score += tx_packets; 719874aeea5SJeff Kirsher efx_xmit_done(tx_queue, tx_ev_desc_ptr); 720874aeea5SJeff Kirsher } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) { 721874aeea5SJeff Kirsher /* Rewrite the FIFO write pointer */ 722874aeea5SJeff Kirsher tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); 723874aeea5SJeff Kirsher tx_queue = efx_channel_get_tx_queue( 724874aeea5SJeff Kirsher channel, tx_ev_q_label % EFX_TXQ_TYPES); 725874aeea5SJeff Kirsher 726874aeea5SJeff Kirsher netif_tx_lock(efx->net_dev); 727874aeea5SJeff Kirsher efx_notify_tx_desc(tx_queue); 728874aeea5SJeff Kirsher netif_tx_unlock(efx->net_dev); 729874aeea5SJeff Kirsher } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) && 730874aeea5SJeff Kirsher EFX_WORKAROUND_10727(efx)) { 731874aeea5SJeff Kirsher efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); 732874aeea5SJeff Kirsher } else { 733874aeea5SJeff Kirsher netif_err(efx, tx_err, efx->net_dev, 734874aeea5SJeff Kirsher "channel %d unexpected TX event " 735874aeea5SJeff Kirsher EFX_QWORD_FMT"\n", channel->channel, 736874aeea5SJeff Kirsher EFX_QWORD_VAL(*event)); 737874aeea5SJeff Kirsher } 738874aeea5SJeff Kirsher 739874aeea5SJeff Kirsher return tx_packets; 740874aeea5SJeff Kirsher } 741874aeea5SJeff Kirsher 742874aeea5SJeff Kirsher /* Detect errors included in the rx_evt_pkt_ok bit. */ 743db339569SBen Hutchings static u16 efx_handle_rx_not_ok(struct efx_rx_queue *rx_queue, 744db339569SBen Hutchings const efx_qword_t *event) 745874aeea5SJeff Kirsher { 746874aeea5SJeff Kirsher struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 747874aeea5SJeff Kirsher struct efx_nic *efx = rx_queue->efx; 748874aeea5SJeff Kirsher bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err; 749874aeea5SJeff Kirsher bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err; 750874aeea5SJeff Kirsher bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc; 751874aeea5SJeff Kirsher bool rx_ev_other_err, rx_ev_pause_frm; 752874aeea5SJeff Kirsher bool rx_ev_hdr_type, rx_ev_mcast_pkt; 753874aeea5SJeff Kirsher unsigned rx_ev_pkt_type; 754874aeea5SJeff Kirsher 755874aeea5SJeff Kirsher rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); 756874aeea5SJeff Kirsher rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); 757874aeea5SJeff Kirsher rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC); 758874aeea5SJeff Kirsher rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE); 759874aeea5SJeff Kirsher rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event, 760874aeea5SJeff Kirsher FSF_AZ_RX_EV_BUF_OWNER_ID_ERR); 761874aeea5SJeff Kirsher rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event, 762874aeea5SJeff Kirsher FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR); 763874aeea5SJeff Kirsher rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event, 764874aeea5SJeff Kirsher FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR); 765874aeea5SJeff Kirsher rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR); 766874aeea5SJeff Kirsher rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC); 767874aeea5SJeff Kirsher rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ? 768874aeea5SJeff Kirsher 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB)); 769874aeea5SJeff Kirsher rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR); 770874aeea5SJeff Kirsher 771874aeea5SJeff Kirsher /* Every error apart from tobe_disc and pause_frm */ 772874aeea5SJeff Kirsher rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err | 773874aeea5SJeff Kirsher rx_ev_buf_owner_id_err | rx_ev_eth_crc_err | 774874aeea5SJeff Kirsher rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err); 775874aeea5SJeff Kirsher 776874aeea5SJeff Kirsher /* Count errors that are not in MAC stats. Ignore expected 777874aeea5SJeff Kirsher * checksum errors during self-test. */ 778874aeea5SJeff Kirsher if (rx_ev_frm_trunc) 779874aeea5SJeff Kirsher ++channel->n_rx_frm_trunc; 780874aeea5SJeff Kirsher else if (rx_ev_tobe_disc) 781874aeea5SJeff Kirsher ++channel->n_rx_tobe_disc; 782874aeea5SJeff Kirsher else if (!efx->loopback_selftest) { 783874aeea5SJeff Kirsher if (rx_ev_ip_hdr_chksum_err) 784874aeea5SJeff Kirsher ++channel->n_rx_ip_hdr_chksum_err; 785874aeea5SJeff Kirsher else if (rx_ev_tcp_udp_chksum_err) 786874aeea5SJeff Kirsher ++channel->n_rx_tcp_udp_chksum_err; 787874aeea5SJeff Kirsher } 788874aeea5SJeff Kirsher 789874aeea5SJeff Kirsher /* TOBE_DISC is expected on unicast mismatches; don't print out an 790874aeea5SJeff Kirsher * error message. FRM_TRUNC indicates RXDP dropped the packet due 791874aeea5SJeff Kirsher * to a FIFO overflow. 792874aeea5SJeff Kirsher */ 7935f3f9d6cSBen Hutchings #ifdef DEBUG 794874aeea5SJeff Kirsher if (rx_ev_other_err && net_ratelimit()) { 795874aeea5SJeff Kirsher netif_dbg(efx, rx_err, efx->net_dev, 796874aeea5SJeff Kirsher " RX queue %d unexpected RX event " 797874aeea5SJeff Kirsher EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n", 798874aeea5SJeff Kirsher efx_rx_queue_index(rx_queue), EFX_QWORD_VAL(*event), 799874aeea5SJeff Kirsher rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "", 800874aeea5SJeff Kirsher rx_ev_ip_hdr_chksum_err ? 801874aeea5SJeff Kirsher " [IP_HDR_CHKSUM_ERR]" : "", 802874aeea5SJeff Kirsher rx_ev_tcp_udp_chksum_err ? 803874aeea5SJeff Kirsher " [TCP_UDP_CHKSUM_ERR]" : "", 804874aeea5SJeff Kirsher rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "", 805874aeea5SJeff Kirsher rx_ev_frm_trunc ? " [FRM_TRUNC]" : "", 806874aeea5SJeff Kirsher rx_ev_drib_nib ? " [DRIB_NIB]" : "", 807874aeea5SJeff Kirsher rx_ev_tobe_disc ? " [TOBE_DISC]" : "", 808874aeea5SJeff Kirsher rx_ev_pause_frm ? " [PAUSE]" : ""); 809874aeea5SJeff Kirsher } 810874aeea5SJeff Kirsher #endif 811db339569SBen Hutchings 812db339569SBen Hutchings /* The frame must be discarded if any of these are true. */ 813db339569SBen Hutchings return (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib | 814db339569SBen Hutchings rx_ev_tobe_disc | rx_ev_pause_frm) ? 815db339569SBen Hutchings EFX_RX_PKT_DISCARD : 0; 816874aeea5SJeff Kirsher } 817874aeea5SJeff Kirsher 818874aeea5SJeff Kirsher /* Handle receive events that are not in-order. */ 819874aeea5SJeff Kirsher static void 820874aeea5SJeff Kirsher efx_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index) 821874aeea5SJeff Kirsher { 822874aeea5SJeff Kirsher struct efx_nic *efx = rx_queue->efx; 823874aeea5SJeff Kirsher unsigned expected, dropped; 824874aeea5SJeff Kirsher 825874aeea5SJeff Kirsher expected = rx_queue->removed_count & rx_queue->ptr_mask; 826874aeea5SJeff Kirsher dropped = (index - expected) & rx_queue->ptr_mask; 827874aeea5SJeff Kirsher netif_info(efx, rx_err, efx->net_dev, 828874aeea5SJeff Kirsher "dropped %d events (index=%d expected=%d)\n", 829874aeea5SJeff Kirsher dropped, index, expected); 830874aeea5SJeff Kirsher 831874aeea5SJeff Kirsher efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ? 832874aeea5SJeff Kirsher RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); 833874aeea5SJeff Kirsher } 834874aeea5SJeff Kirsher 835874aeea5SJeff Kirsher /* Handle a packet received event 836874aeea5SJeff Kirsher * 837874aeea5SJeff Kirsher * The NIC gives a "discard" flag if it's a unicast packet with the 838874aeea5SJeff Kirsher * wrong destination address 839874aeea5SJeff Kirsher * Also "is multicast" and "matches multicast filter" flags can be used to 840874aeea5SJeff Kirsher * discard non-matching multicast packets. 841874aeea5SJeff Kirsher */ 842874aeea5SJeff Kirsher static void 843874aeea5SJeff Kirsher efx_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event) 844874aeea5SJeff Kirsher { 845874aeea5SJeff Kirsher unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt; 846874aeea5SJeff Kirsher unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt; 847874aeea5SJeff Kirsher unsigned expected_ptr; 848db339569SBen Hutchings bool rx_ev_pkt_ok; 849db339569SBen Hutchings u16 flags; 850874aeea5SJeff Kirsher struct efx_rx_queue *rx_queue; 851874aeea5SJeff Kirsher 852874aeea5SJeff Kirsher /* Basic packet information */ 853874aeea5SJeff Kirsher rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT); 854874aeea5SJeff Kirsher rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK); 855874aeea5SJeff Kirsher rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); 856874aeea5SJeff Kirsher WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT)); 857874aeea5SJeff Kirsher WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1); 858874aeea5SJeff Kirsher WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) != 859874aeea5SJeff Kirsher channel->channel); 860874aeea5SJeff Kirsher 861874aeea5SJeff Kirsher rx_queue = efx_channel_get_rx_queue(channel); 862874aeea5SJeff Kirsher 863874aeea5SJeff Kirsher rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR); 864874aeea5SJeff Kirsher expected_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 865874aeea5SJeff Kirsher if (unlikely(rx_ev_desc_ptr != expected_ptr)) 866874aeea5SJeff Kirsher efx_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr); 867874aeea5SJeff Kirsher 868874aeea5SJeff Kirsher if (likely(rx_ev_pkt_ok)) { 869874aeea5SJeff Kirsher /* If packet is marked as OK and packet type is TCP/IP or 870874aeea5SJeff Kirsher * UDP/IP, then we can rely on the hardware checksum. 871874aeea5SJeff Kirsher */ 872db339569SBen Hutchings flags = (rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP || 873db339569SBen Hutchings rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP) ? 874db339569SBen Hutchings EFX_RX_PKT_CSUMMED : 0; 875874aeea5SJeff Kirsher } else { 876db339569SBen Hutchings flags = efx_handle_rx_not_ok(rx_queue, event); 877874aeea5SJeff Kirsher } 878874aeea5SJeff Kirsher 879874aeea5SJeff Kirsher /* Detect multicast packets that didn't match the filter */ 880874aeea5SJeff Kirsher rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); 881874aeea5SJeff Kirsher if (rx_ev_mcast_pkt) { 882874aeea5SJeff Kirsher unsigned int rx_ev_mcast_hash_match = 883874aeea5SJeff Kirsher EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH); 884874aeea5SJeff Kirsher 885874aeea5SJeff Kirsher if (unlikely(!rx_ev_mcast_hash_match)) { 886874aeea5SJeff Kirsher ++channel->n_rx_mcast_mismatch; 887db339569SBen Hutchings flags |= EFX_RX_PKT_DISCARD; 888874aeea5SJeff Kirsher } 889874aeea5SJeff Kirsher } 890874aeea5SJeff Kirsher 891874aeea5SJeff Kirsher channel->irq_mod_score += 2; 892874aeea5SJeff Kirsher 893874aeea5SJeff Kirsher /* Handle received packet */ 894db339569SBen Hutchings efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt, flags); 895874aeea5SJeff Kirsher } 896874aeea5SJeff Kirsher 897874aeea5SJeff Kirsher static void 898874aeea5SJeff Kirsher efx_handle_generated_event(struct efx_channel *channel, efx_qword_t *event) 899874aeea5SJeff Kirsher { 900874aeea5SJeff Kirsher struct efx_nic *efx = channel->efx; 901874aeea5SJeff Kirsher unsigned code; 902874aeea5SJeff Kirsher 903874aeea5SJeff Kirsher code = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC); 904874aeea5SJeff Kirsher if (code == EFX_CHANNEL_MAGIC_TEST(channel)) 905874aeea5SJeff Kirsher ; /* ignore */ 906874aeea5SJeff Kirsher else if (code == EFX_CHANNEL_MAGIC_FILL(channel)) 907874aeea5SJeff Kirsher /* The queue must be empty, so we won't receive any rx 908874aeea5SJeff Kirsher * events, so efx_process_channel() won't refill the 909874aeea5SJeff Kirsher * queue. Refill it here */ 910874aeea5SJeff Kirsher efx_fast_push_rx_descriptors(efx_channel_get_rx_queue(channel)); 911874aeea5SJeff Kirsher else 912874aeea5SJeff Kirsher netif_dbg(efx, hw, efx->net_dev, "channel %d received " 913874aeea5SJeff Kirsher "generated event "EFX_QWORD_FMT"\n", 914874aeea5SJeff Kirsher channel->channel, EFX_QWORD_VAL(*event)); 915874aeea5SJeff Kirsher } 916874aeea5SJeff Kirsher 917874aeea5SJeff Kirsher static void 918874aeea5SJeff Kirsher efx_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 919874aeea5SJeff Kirsher { 920874aeea5SJeff Kirsher struct efx_nic *efx = channel->efx; 921874aeea5SJeff Kirsher unsigned int ev_sub_code; 922874aeea5SJeff Kirsher unsigned int ev_sub_data; 923874aeea5SJeff Kirsher 924874aeea5SJeff Kirsher ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE); 925874aeea5SJeff Kirsher ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA); 926874aeea5SJeff Kirsher 927874aeea5SJeff Kirsher switch (ev_sub_code) { 928874aeea5SJeff Kirsher case FSE_AZ_TX_DESCQ_FLS_DONE_EV: 929874aeea5SJeff Kirsher netif_vdbg(efx, hw, efx->net_dev, "channel %d TXQ %d flushed\n", 930874aeea5SJeff Kirsher channel->channel, ev_sub_data); 931874aeea5SJeff Kirsher break; 932874aeea5SJeff Kirsher case FSE_AZ_RX_DESCQ_FLS_DONE_EV: 933874aeea5SJeff Kirsher netif_vdbg(efx, hw, efx->net_dev, "channel %d RXQ %d flushed\n", 934874aeea5SJeff Kirsher channel->channel, ev_sub_data); 935874aeea5SJeff Kirsher break; 936874aeea5SJeff Kirsher case FSE_AZ_EVQ_INIT_DONE_EV: 937874aeea5SJeff Kirsher netif_dbg(efx, hw, efx->net_dev, 938874aeea5SJeff Kirsher "channel %d EVQ %d initialised\n", 939874aeea5SJeff Kirsher channel->channel, ev_sub_data); 940874aeea5SJeff Kirsher break; 941874aeea5SJeff Kirsher case FSE_AZ_SRM_UPD_DONE_EV: 942874aeea5SJeff Kirsher netif_vdbg(efx, hw, efx->net_dev, 943874aeea5SJeff Kirsher "channel %d SRAM update done\n", channel->channel); 944874aeea5SJeff Kirsher break; 945874aeea5SJeff Kirsher case FSE_AZ_WAKE_UP_EV: 946874aeea5SJeff Kirsher netif_vdbg(efx, hw, efx->net_dev, 947874aeea5SJeff Kirsher "channel %d RXQ %d wakeup event\n", 948874aeea5SJeff Kirsher channel->channel, ev_sub_data); 949874aeea5SJeff Kirsher break; 950874aeea5SJeff Kirsher case FSE_AZ_TIMER_EV: 951874aeea5SJeff Kirsher netif_vdbg(efx, hw, efx->net_dev, 952874aeea5SJeff Kirsher "channel %d RX queue %d timer expired\n", 953874aeea5SJeff Kirsher channel->channel, ev_sub_data); 954874aeea5SJeff Kirsher break; 955874aeea5SJeff Kirsher case FSE_AA_RX_RECOVER_EV: 956874aeea5SJeff Kirsher netif_err(efx, rx_err, efx->net_dev, 957874aeea5SJeff Kirsher "channel %d seen DRIVER RX_RESET event. " 958874aeea5SJeff Kirsher "Resetting.\n", channel->channel); 959874aeea5SJeff Kirsher atomic_inc(&efx->rx_reset); 960874aeea5SJeff Kirsher efx_schedule_reset(efx, 961874aeea5SJeff Kirsher EFX_WORKAROUND_6555(efx) ? 962874aeea5SJeff Kirsher RESET_TYPE_RX_RECOVERY : 963874aeea5SJeff Kirsher RESET_TYPE_DISABLE); 964874aeea5SJeff Kirsher break; 965874aeea5SJeff Kirsher case FSE_BZ_RX_DSC_ERROR_EV: 966874aeea5SJeff Kirsher netif_err(efx, rx_err, efx->net_dev, 967874aeea5SJeff Kirsher "RX DMA Q %d reports descriptor fetch error." 968874aeea5SJeff Kirsher " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data); 969874aeea5SJeff Kirsher efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH); 970874aeea5SJeff Kirsher break; 971874aeea5SJeff Kirsher case FSE_BZ_TX_DSC_ERROR_EV: 972874aeea5SJeff Kirsher netif_err(efx, tx_err, efx->net_dev, 973874aeea5SJeff Kirsher "TX DMA Q %d reports descriptor fetch error." 974874aeea5SJeff Kirsher " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data); 975874aeea5SJeff Kirsher efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); 976874aeea5SJeff Kirsher break; 977874aeea5SJeff Kirsher default: 978874aeea5SJeff Kirsher netif_vdbg(efx, hw, efx->net_dev, 979874aeea5SJeff Kirsher "channel %d unknown driver event code %d " 980874aeea5SJeff Kirsher "data %04x\n", channel->channel, ev_sub_code, 981874aeea5SJeff Kirsher ev_sub_data); 982874aeea5SJeff Kirsher break; 983874aeea5SJeff Kirsher } 984874aeea5SJeff Kirsher } 985874aeea5SJeff Kirsher 986874aeea5SJeff Kirsher int efx_nic_process_eventq(struct efx_channel *channel, int budget) 987874aeea5SJeff Kirsher { 988874aeea5SJeff Kirsher struct efx_nic *efx = channel->efx; 989874aeea5SJeff Kirsher unsigned int read_ptr; 990874aeea5SJeff Kirsher efx_qword_t event, *p_event; 991874aeea5SJeff Kirsher int ev_code; 992874aeea5SJeff Kirsher int tx_packets = 0; 993874aeea5SJeff Kirsher int spent = 0; 994874aeea5SJeff Kirsher 995874aeea5SJeff Kirsher read_ptr = channel->eventq_read_ptr; 996874aeea5SJeff Kirsher 997874aeea5SJeff Kirsher for (;;) { 998874aeea5SJeff Kirsher p_event = efx_event(channel, read_ptr); 999874aeea5SJeff Kirsher event = *p_event; 1000874aeea5SJeff Kirsher 1001874aeea5SJeff Kirsher if (!efx_event_present(&event)) 1002874aeea5SJeff Kirsher /* End of events */ 1003874aeea5SJeff Kirsher break; 1004874aeea5SJeff Kirsher 1005874aeea5SJeff Kirsher netif_vdbg(channel->efx, intr, channel->efx->net_dev, 1006874aeea5SJeff Kirsher "channel %d event is "EFX_QWORD_FMT"\n", 1007874aeea5SJeff Kirsher channel->channel, EFX_QWORD_VAL(event)); 1008874aeea5SJeff Kirsher 1009874aeea5SJeff Kirsher /* Clear this event by marking it all ones */ 1010874aeea5SJeff Kirsher EFX_SET_QWORD(*p_event); 1011874aeea5SJeff Kirsher 1012874aeea5SJeff Kirsher ++read_ptr; 1013874aeea5SJeff Kirsher 1014874aeea5SJeff Kirsher ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE); 1015874aeea5SJeff Kirsher 1016874aeea5SJeff Kirsher switch (ev_code) { 1017874aeea5SJeff Kirsher case FSE_AZ_EV_CODE_RX_EV: 1018874aeea5SJeff Kirsher efx_handle_rx_event(channel, &event); 1019874aeea5SJeff Kirsher if (++spent == budget) 1020874aeea5SJeff Kirsher goto out; 1021874aeea5SJeff Kirsher break; 1022874aeea5SJeff Kirsher case FSE_AZ_EV_CODE_TX_EV: 1023874aeea5SJeff Kirsher tx_packets += efx_handle_tx_event(channel, &event); 1024874aeea5SJeff Kirsher if (tx_packets > efx->txq_entries) { 1025874aeea5SJeff Kirsher spent = budget; 1026874aeea5SJeff Kirsher goto out; 1027874aeea5SJeff Kirsher } 1028874aeea5SJeff Kirsher break; 1029874aeea5SJeff Kirsher case FSE_AZ_EV_CODE_DRV_GEN_EV: 1030874aeea5SJeff Kirsher efx_handle_generated_event(channel, &event); 1031874aeea5SJeff Kirsher break; 1032874aeea5SJeff Kirsher case FSE_AZ_EV_CODE_DRIVER_EV: 1033874aeea5SJeff Kirsher efx_handle_driver_event(channel, &event); 1034874aeea5SJeff Kirsher break; 1035874aeea5SJeff Kirsher case FSE_CZ_EV_CODE_MCDI_EV: 1036874aeea5SJeff Kirsher efx_mcdi_process_event(channel, &event); 1037874aeea5SJeff Kirsher break; 1038874aeea5SJeff Kirsher case FSE_AZ_EV_CODE_GLOBAL_EV: 1039874aeea5SJeff Kirsher if (efx->type->handle_global_event && 1040874aeea5SJeff Kirsher efx->type->handle_global_event(channel, &event)) 1041874aeea5SJeff Kirsher break; 1042874aeea5SJeff Kirsher /* else fall through */ 1043874aeea5SJeff Kirsher default: 1044874aeea5SJeff Kirsher netif_err(channel->efx, hw, channel->efx->net_dev, 1045874aeea5SJeff Kirsher "channel %d unknown event type %d (data " 1046874aeea5SJeff Kirsher EFX_QWORD_FMT ")\n", channel->channel, 1047874aeea5SJeff Kirsher ev_code, EFX_QWORD_VAL(event)); 1048874aeea5SJeff Kirsher } 1049874aeea5SJeff Kirsher } 1050874aeea5SJeff Kirsher 1051874aeea5SJeff Kirsher out: 1052874aeea5SJeff Kirsher channel->eventq_read_ptr = read_ptr; 1053874aeea5SJeff Kirsher return spent; 1054874aeea5SJeff Kirsher } 1055874aeea5SJeff Kirsher 1056874aeea5SJeff Kirsher /* Check whether an event is present in the eventq at the current 1057874aeea5SJeff Kirsher * read pointer. Only useful for self-test. 1058874aeea5SJeff Kirsher */ 1059874aeea5SJeff Kirsher bool efx_nic_event_present(struct efx_channel *channel) 1060874aeea5SJeff Kirsher { 1061874aeea5SJeff Kirsher return efx_event_present(efx_event(channel, channel->eventq_read_ptr)); 1062874aeea5SJeff Kirsher } 1063874aeea5SJeff Kirsher 1064874aeea5SJeff Kirsher /* Allocate buffer table entries for event queue */ 1065874aeea5SJeff Kirsher int efx_nic_probe_eventq(struct efx_channel *channel) 1066874aeea5SJeff Kirsher { 1067874aeea5SJeff Kirsher struct efx_nic *efx = channel->efx; 1068874aeea5SJeff Kirsher unsigned entries; 1069874aeea5SJeff Kirsher 1070874aeea5SJeff Kirsher entries = channel->eventq_mask + 1; 1071874aeea5SJeff Kirsher return efx_alloc_special_buffer(efx, &channel->eventq, 1072874aeea5SJeff Kirsher entries * sizeof(efx_qword_t)); 1073874aeea5SJeff Kirsher } 1074874aeea5SJeff Kirsher 1075874aeea5SJeff Kirsher void efx_nic_init_eventq(struct efx_channel *channel) 1076874aeea5SJeff Kirsher { 1077874aeea5SJeff Kirsher efx_oword_t reg; 1078874aeea5SJeff Kirsher struct efx_nic *efx = channel->efx; 1079874aeea5SJeff Kirsher 1080874aeea5SJeff Kirsher netif_dbg(efx, hw, efx->net_dev, 1081874aeea5SJeff Kirsher "channel %d event queue in special buffers %d-%d\n", 1082874aeea5SJeff Kirsher channel->channel, channel->eventq.index, 1083874aeea5SJeff Kirsher channel->eventq.index + channel->eventq.entries - 1); 1084874aeea5SJeff Kirsher 1085874aeea5SJeff Kirsher if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) { 1086874aeea5SJeff Kirsher EFX_POPULATE_OWORD_3(reg, 1087874aeea5SJeff Kirsher FRF_CZ_TIMER_Q_EN, 1, 1088874aeea5SJeff Kirsher FRF_CZ_HOST_NOTIFY_MODE, 0, 1089874aeea5SJeff Kirsher FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS); 1090874aeea5SJeff Kirsher efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, channel->channel); 1091874aeea5SJeff Kirsher } 1092874aeea5SJeff Kirsher 1093874aeea5SJeff Kirsher /* Pin event queue buffer */ 1094874aeea5SJeff Kirsher efx_init_special_buffer(efx, &channel->eventq); 1095874aeea5SJeff Kirsher 1096874aeea5SJeff Kirsher /* Fill event queue with all ones (i.e. empty events) */ 1097874aeea5SJeff Kirsher memset(channel->eventq.addr, 0xff, channel->eventq.len); 1098874aeea5SJeff Kirsher 1099874aeea5SJeff Kirsher /* Push event queue to card */ 1100874aeea5SJeff Kirsher EFX_POPULATE_OWORD_3(reg, 1101874aeea5SJeff Kirsher FRF_AZ_EVQ_EN, 1, 1102874aeea5SJeff Kirsher FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries), 1103874aeea5SJeff Kirsher FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index); 1104874aeea5SJeff Kirsher efx_writeo_table(efx, ®, efx->type->evq_ptr_tbl_base, 1105874aeea5SJeff Kirsher channel->channel); 1106874aeea5SJeff Kirsher 1107874aeea5SJeff Kirsher efx->type->push_irq_moderation(channel); 1108874aeea5SJeff Kirsher } 1109874aeea5SJeff Kirsher 1110874aeea5SJeff Kirsher void efx_nic_fini_eventq(struct efx_channel *channel) 1111874aeea5SJeff Kirsher { 1112874aeea5SJeff Kirsher efx_oword_t reg; 1113874aeea5SJeff Kirsher struct efx_nic *efx = channel->efx; 1114874aeea5SJeff Kirsher 1115874aeea5SJeff Kirsher /* Remove event queue from card */ 1116874aeea5SJeff Kirsher EFX_ZERO_OWORD(reg); 1117874aeea5SJeff Kirsher efx_writeo_table(efx, ®, efx->type->evq_ptr_tbl_base, 1118874aeea5SJeff Kirsher channel->channel); 1119874aeea5SJeff Kirsher if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) 1120874aeea5SJeff Kirsher efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, channel->channel); 1121874aeea5SJeff Kirsher 1122874aeea5SJeff Kirsher /* Unpin event queue */ 1123874aeea5SJeff Kirsher efx_fini_special_buffer(efx, &channel->eventq); 1124874aeea5SJeff Kirsher } 1125874aeea5SJeff Kirsher 1126874aeea5SJeff Kirsher /* Free buffers backing event queue */ 1127874aeea5SJeff Kirsher void efx_nic_remove_eventq(struct efx_channel *channel) 1128874aeea5SJeff Kirsher { 1129874aeea5SJeff Kirsher efx_free_special_buffer(channel->efx, &channel->eventq); 1130874aeea5SJeff Kirsher } 1131874aeea5SJeff Kirsher 1132874aeea5SJeff Kirsher 1133874aeea5SJeff Kirsher void efx_nic_generate_test_event(struct efx_channel *channel) 1134874aeea5SJeff Kirsher { 1135874aeea5SJeff Kirsher unsigned int magic = EFX_CHANNEL_MAGIC_TEST(channel); 1136874aeea5SJeff Kirsher efx_qword_t test_event; 1137874aeea5SJeff Kirsher 1138874aeea5SJeff Kirsher EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE, 1139874aeea5SJeff Kirsher FSE_AZ_EV_CODE_DRV_GEN_EV, 1140874aeea5SJeff Kirsher FSF_AZ_DRV_GEN_EV_MAGIC, magic); 1141874aeea5SJeff Kirsher efx_generate_event(channel, &test_event); 1142874aeea5SJeff Kirsher } 1143874aeea5SJeff Kirsher 1144874aeea5SJeff Kirsher void efx_nic_generate_fill_event(struct efx_channel *channel) 1145874aeea5SJeff Kirsher { 1146874aeea5SJeff Kirsher unsigned int magic = EFX_CHANNEL_MAGIC_FILL(channel); 1147874aeea5SJeff Kirsher efx_qword_t test_event; 1148874aeea5SJeff Kirsher 1149874aeea5SJeff Kirsher EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE, 1150874aeea5SJeff Kirsher FSE_AZ_EV_CODE_DRV_GEN_EV, 1151874aeea5SJeff Kirsher FSF_AZ_DRV_GEN_EV_MAGIC, magic); 1152874aeea5SJeff Kirsher efx_generate_event(channel, &test_event); 1153874aeea5SJeff Kirsher } 1154874aeea5SJeff Kirsher 1155874aeea5SJeff Kirsher /************************************************************************** 1156874aeea5SJeff Kirsher * 1157874aeea5SJeff Kirsher * Flush handling 1158874aeea5SJeff Kirsher * 1159874aeea5SJeff Kirsher **************************************************************************/ 1160874aeea5SJeff Kirsher 1161874aeea5SJeff Kirsher 1162874aeea5SJeff Kirsher static void efx_poll_flush_events(struct efx_nic *efx) 1163874aeea5SJeff Kirsher { 1164874aeea5SJeff Kirsher struct efx_channel *channel = efx_get_channel(efx, 0); 1165874aeea5SJeff Kirsher struct efx_tx_queue *tx_queue; 1166874aeea5SJeff Kirsher struct efx_rx_queue *rx_queue; 1167874aeea5SJeff Kirsher unsigned int read_ptr = channel->eventq_read_ptr; 1168874aeea5SJeff Kirsher unsigned int end_ptr = read_ptr + channel->eventq_mask - 1; 1169874aeea5SJeff Kirsher 1170874aeea5SJeff Kirsher do { 1171874aeea5SJeff Kirsher efx_qword_t *event = efx_event(channel, read_ptr); 1172874aeea5SJeff Kirsher int ev_code, ev_sub_code, ev_queue; 1173874aeea5SJeff Kirsher bool ev_failed; 1174874aeea5SJeff Kirsher 1175874aeea5SJeff Kirsher if (!efx_event_present(event)) 1176874aeea5SJeff Kirsher break; 1177874aeea5SJeff Kirsher 1178874aeea5SJeff Kirsher ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE); 1179874aeea5SJeff Kirsher ev_sub_code = EFX_QWORD_FIELD(*event, 1180874aeea5SJeff Kirsher FSF_AZ_DRIVER_EV_SUBCODE); 1181874aeea5SJeff Kirsher if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV && 1182874aeea5SJeff Kirsher ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) { 1183874aeea5SJeff Kirsher ev_queue = EFX_QWORD_FIELD(*event, 1184874aeea5SJeff Kirsher FSF_AZ_DRIVER_EV_SUBDATA); 1185874aeea5SJeff Kirsher if (ev_queue < EFX_TXQ_TYPES * efx->n_tx_channels) { 1186874aeea5SJeff Kirsher tx_queue = efx_get_tx_queue( 1187874aeea5SJeff Kirsher efx, ev_queue / EFX_TXQ_TYPES, 1188874aeea5SJeff Kirsher ev_queue % EFX_TXQ_TYPES); 1189874aeea5SJeff Kirsher tx_queue->flushed = FLUSH_DONE; 1190874aeea5SJeff Kirsher } 1191874aeea5SJeff Kirsher } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV && 1192874aeea5SJeff Kirsher ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) { 1193874aeea5SJeff Kirsher ev_queue = EFX_QWORD_FIELD( 1194874aeea5SJeff Kirsher *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); 1195874aeea5SJeff Kirsher ev_failed = EFX_QWORD_FIELD( 1196874aeea5SJeff Kirsher *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); 1197874aeea5SJeff Kirsher if (ev_queue < efx->n_rx_channels) { 1198874aeea5SJeff Kirsher rx_queue = efx_get_rx_queue(efx, ev_queue); 1199874aeea5SJeff Kirsher rx_queue->flushed = 1200874aeea5SJeff Kirsher ev_failed ? FLUSH_FAILED : FLUSH_DONE; 1201874aeea5SJeff Kirsher } 1202874aeea5SJeff Kirsher } 1203874aeea5SJeff Kirsher 1204874aeea5SJeff Kirsher /* We're about to destroy the queue anyway, so 1205874aeea5SJeff Kirsher * it's ok to throw away every non-flush event */ 1206874aeea5SJeff Kirsher EFX_SET_QWORD(*event); 1207874aeea5SJeff Kirsher 1208874aeea5SJeff Kirsher ++read_ptr; 1209874aeea5SJeff Kirsher } while (read_ptr != end_ptr); 1210874aeea5SJeff Kirsher 1211874aeea5SJeff Kirsher channel->eventq_read_ptr = read_ptr; 1212874aeea5SJeff Kirsher } 1213874aeea5SJeff Kirsher 1214874aeea5SJeff Kirsher /* Handle tx and rx flushes at the same time, since they run in 1215874aeea5SJeff Kirsher * parallel in the hardware and there's no reason for us to 1216874aeea5SJeff Kirsher * serialise them */ 1217874aeea5SJeff Kirsher int efx_nic_flush_queues(struct efx_nic *efx) 1218874aeea5SJeff Kirsher { 1219874aeea5SJeff Kirsher struct efx_channel *channel; 1220874aeea5SJeff Kirsher struct efx_rx_queue *rx_queue; 1221874aeea5SJeff Kirsher struct efx_tx_queue *tx_queue; 1222874aeea5SJeff Kirsher int i, tx_pending, rx_pending; 1223874aeea5SJeff Kirsher 1224874aeea5SJeff Kirsher /* If necessary prepare the hardware for flushing */ 1225874aeea5SJeff Kirsher efx->type->prepare_flush(efx); 1226874aeea5SJeff Kirsher 1227874aeea5SJeff Kirsher /* Flush all tx queues in parallel */ 1228874aeea5SJeff Kirsher efx_for_each_channel(channel, efx) { 1229874aeea5SJeff Kirsher efx_for_each_possible_channel_tx_queue(tx_queue, channel) { 1230874aeea5SJeff Kirsher if (tx_queue->initialised) 1231874aeea5SJeff Kirsher efx_flush_tx_queue(tx_queue); 1232874aeea5SJeff Kirsher } 1233874aeea5SJeff Kirsher } 1234874aeea5SJeff Kirsher 1235874aeea5SJeff Kirsher /* The hardware supports four concurrent rx flushes, each of which may 1236874aeea5SJeff Kirsher * need to be retried if there is an outstanding descriptor fetch */ 1237874aeea5SJeff Kirsher for (i = 0; i < EFX_FLUSH_POLL_COUNT; ++i) { 1238874aeea5SJeff Kirsher rx_pending = tx_pending = 0; 1239874aeea5SJeff Kirsher efx_for_each_channel(channel, efx) { 1240874aeea5SJeff Kirsher efx_for_each_channel_rx_queue(rx_queue, channel) { 1241874aeea5SJeff Kirsher if (rx_queue->flushed == FLUSH_PENDING) 1242874aeea5SJeff Kirsher ++rx_pending; 1243874aeea5SJeff Kirsher } 1244874aeea5SJeff Kirsher } 1245874aeea5SJeff Kirsher efx_for_each_channel(channel, efx) { 1246874aeea5SJeff Kirsher efx_for_each_channel_rx_queue(rx_queue, channel) { 1247874aeea5SJeff Kirsher if (rx_pending == EFX_RX_FLUSH_COUNT) 1248874aeea5SJeff Kirsher break; 1249874aeea5SJeff Kirsher if (rx_queue->flushed == FLUSH_FAILED || 1250874aeea5SJeff Kirsher rx_queue->flushed == FLUSH_NONE) { 1251874aeea5SJeff Kirsher efx_flush_rx_queue(rx_queue); 1252874aeea5SJeff Kirsher ++rx_pending; 1253874aeea5SJeff Kirsher } 1254874aeea5SJeff Kirsher } 1255874aeea5SJeff Kirsher efx_for_each_possible_channel_tx_queue(tx_queue, channel) { 1256874aeea5SJeff Kirsher if (tx_queue->initialised && 1257874aeea5SJeff Kirsher tx_queue->flushed != FLUSH_DONE) 1258874aeea5SJeff Kirsher ++tx_pending; 1259874aeea5SJeff Kirsher } 1260874aeea5SJeff Kirsher } 1261874aeea5SJeff Kirsher 1262874aeea5SJeff Kirsher if (rx_pending == 0 && tx_pending == 0) 1263874aeea5SJeff Kirsher return 0; 1264874aeea5SJeff Kirsher 1265874aeea5SJeff Kirsher msleep(EFX_FLUSH_INTERVAL); 1266874aeea5SJeff Kirsher efx_poll_flush_events(efx); 1267874aeea5SJeff Kirsher } 1268874aeea5SJeff Kirsher 1269874aeea5SJeff Kirsher /* Mark the queues as all flushed. We're going to return failure 1270874aeea5SJeff Kirsher * leading to a reset, or fake up success anyway */ 1271874aeea5SJeff Kirsher efx_for_each_channel(channel, efx) { 1272874aeea5SJeff Kirsher efx_for_each_possible_channel_tx_queue(tx_queue, channel) { 1273874aeea5SJeff Kirsher if (tx_queue->initialised && 1274874aeea5SJeff Kirsher tx_queue->flushed != FLUSH_DONE) 1275874aeea5SJeff Kirsher netif_err(efx, hw, efx->net_dev, 1276874aeea5SJeff Kirsher "tx queue %d flush command timed out\n", 1277874aeea5SJeff Kirsher tx_queue->queue); 1278874aeea5SJeff Kirsher tx_queue->flushed = FLUSH_DONE; 1279874aeea5SJeff Kirsher } 1280874aeea5SJeff Kirsher efx_for_each_channel_rx_queue(rx_queue, channel) { 1281874aeea5SJeff Kirsher if (rx_queue->flushed != FLUSH_DONE) 1282874aeea5SJeff Kirsher netif_err(efx, hw, efx->net_dev, 1283874aeea5SJeff Kirsher "rx queue %d flush command timed out\n", 1284874aeea5SJeff Kirsher efx_rx_queue_index(rx_queue)); 1285874aeea5SJeff Kirsher rx_queue->flushed = FLUSH_DONE; 1286874aeea5SJeff Kirsher } 1287874aeea5SJeff Kirsher } 1288874aeea5SJeff Kirsher 1289874aeea5SJeff Kirsher return -ETIMEDOUT; 1290874aeea5SJeff Kirsher } 1291874aeea5SJeff Kirsher 1292874aeea5SJeff Kirsher /************************************************************************** 1293874aeea5SJeff Kirsher * 1294874aeea5SJeff Kirsher * Hardware interrupts 1295874aeea5SJeff Kirsher * The hardware interrupt handler does very little work; all the event 1296874aeea5SJeff Kirsher * queue processing is carried out by per-channel tasklets. 1297874aeea5SJeff Kirsher * 1298874aeea5SJeff Kirsher **************************************************************************/ 1299874aeea5SJeff Kirsher 1300874aeea5SJeff Kirsher /* Enable/disable/generate interrupts */ 1301874aeea5SJeff Kirsher static inline void efx_nic_interrupts(struct efx_nic *efx, 1302874aeea5SJeff Kirsher bool enabled, bool force) 1303874aeea5SJeff Kirsher { 1304874aeea5SJeff Kirsher efx_oword_t int_en_reg_ker; 1305874aeea5SJeff Kirsher 1306874aeea5SJeff Kirsher EFX_POPULATE_OWORD_3(int_en_reg_ker, 13071646a6f3SBen Hutchings FRF_AZ_KER_INT_LEVE_SEL, efx->irq_level, 1308874aeea5SJeff Kirsher FRF_AZ_KER_INT_KER, force, 1309874aeea5SJeff Kirsher FRF_AZ_DRV_INT_EN_KER, enabled); 1310874aeea5SJeff Kirsher efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER); 1311874aeea5SJeff Kirsher } 1312874aeea5SJeff Kirsher 1313874aeea5SJeff Kirsher void efx_nic_enable_interrupts(struct efx_nic *efx) 1314874aeea5SJeff Kirsher { 1315874aeea5SJeff Kirsher struct efx_channel *channel; 1316874aeea5SJeff Kirsher 1317874aeea5SJeff Kirsher EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr)); 1318874aeea5SJeff Kirsher wmb(); /* Ensure interrupt vector is clear before interrupts enabled */ 1319874aeea5SJeff Kirsher 1320874aeea5SJeff Kirsher /* Enable interrupts */ 1321874aeea5SJeff Kirsher efx_nic_interrupts(efx, true, false); 1322874aeea5SJeff Kirsher 1323874aeea5SJeff Kirsher /* Force processing of all the channels to get the EVQ RPTRs up to 1324874aeea5SJeff Kirsher date */ 1325874aeea5SJeff Kirsher efx_for_each_channel(channel, efx) 1326874aeea5SJeff Kirsher efx_schedule_channel(channel); 1327874aeea5SJeff Kirsher } 1328874aeea5SJeff Kirsher 1329874aeea5SJeff Kirsher void efx_nic_disable_interrupts(struct efx_nic *efx) 1330874aeea5SJeff Kirsher { 1331874aeea5SJeff Kirsher /* Disable interrupts */ 1332874aeea5SJeff Kirsher efx_nic_interrupts(efx, false, false); 1333874aeea5SJeff Kirsher } 1334874aeea5SJeff Kirsher 1335874aeea5SJeff Kirsher /* Generate a test interrupt 1336874aeea5SJeff Kirsher * Interrupt must already have been enabled, otherwise nasty things 1337874aeea5SJeff Kirsher * may happen. 1338874aeea5SJeff Kirsher */ 1339874aeea5SJeff Kirsher void efx_nic_generate_interrupt(struct efx_nic *efx) 1340874aeea5SJeff Kirsher { 1341874aeea5SJeff Kirsher efx_nic_interrupts(efx, true, true); 1342874aeea5SJeff Kirsher } 1343874aeea5SJeff Kirsher 1344874aeea5SJeff Kirsher /* Process a fatal interrupt 1345874aeea5SJeff Kirsher * Disable bus mastering ASAP and schedule a reset 1346874aeea5SJeff Kirsher */ 1347874aeea5SJeff Kirsher irqreturn_t efx_nic_fatal_interrupt(struct efx_nic *efx) 1348874aeea5SJeff Kirsher { 1349874aeea5SJeff Kirsher struct falcon_nic_data *nic_data = efx->nic_data; 1350874aeea5SJeff Kirsher efx_oword_t *int_ker = efx->irq_status.addr; 1351874aeea5SJeff Kirsher efx_oword_t fatal_intr; 1352874aeea5SJeff Kirsher int error, mem_perr; 1353874aeea5SJeff Kirsher 1354874aeea5SJeff Kirsher efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER); 1355874aeea5SJeff Kirsher error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR); 1356874aeea5SJeff Kirsher 1357874aeea5SJeff Kirsher netif_err(efx, hw, efx->net_dev, "SYSTEM ERROR "EFX_OWORD_FMT" status " 1358874aeea5SJeff Kirsher EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker), 1359874aeea5SJeff Kirsher EFX_OWORD_VAL(fatal_intr), 1360874aeea5SJeff Kirsher error ? "disabling bus mastering" : "no recognised error"); 1361874aeea5SJeff Kirsher 1362874aeea5SJeff Kirsher /* If this is a memory parity error dump which blocks are offending */ 1363874aeea5SJeff Kirsher mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) || 1364874aeea5SJeff Kirsher EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER)); 1365874aeea5SJeff Kirsher if (mem_perr) { 1366874aeea5SJeff Kirsher efx_oword_t reg; 1367874aeea5SJeff Kirsher efx_reado(efx, ®, FR_AZ_MEM_STAT); 1368874aeea5SJeff Kirsher netif_err(efx, hw, efx->net_dev, 1369874aeea5SJeff Kirsher "SYSTEM ERROR: memory parity error "EFX_OWORD_FMT"\n", 1370874aeea5SJeff Kirsher EFX_OWORD_VAL(reg)); 1371874aeea5SJeff Kirsher } 1372874aeea5SJeff Kirsher 1373874aeea5SJeff Kirsher /* Disable both devices */ 1374874aeea5SJeff Kirsher pci_clear_master(efx->pci_dev); 1375874aeea5SJeff Kirsher if (efx_nic_is_dual_func(efx)) 1376874aeea5SJeff Kirsher pci_clear_master(nic_data->pci_dev2); 1377874aeea5SJeff Kirsher efx_nic_disable_interrupts(efx); 1378874aeea5SJeff Kirsher 1379874aeea5SJeff Kirsher /* Count errors and reset or disable the NIC accordingly */ 1380874aeea5SJeff Kirsher if (efx->int_error_count == 0 || 1381874aeea5SJeff Kirsher time_after(jiffies, efx->int_error_expire)) { 1382874aeea5SJeff Kirsher efx->int_error_count = 0; 1383874aeea5SJeff Kirsher efx->int_error_expire = 1384874aeea5SJeff Kirsher jiffies + EFX_INT_ERROR_EXPIRE * HZ; 1385874aeea5SJeff Kirsher } 1386874aeea5SJeff Kirsher if (++efx->int_error_count < EFX_MAX_INT_ERRORS) { 1387874aeea5SJeff Kirsher netif_err(efx, hw, efx->net_dev, 1388874aeea5SJeff Kirsher "SYSTEM ERROR - reset scheduled\n"); 1389874aeea5SJeff Kirsher efx_schedule_reset(efx, RESET_TYPE_INT_ERROR); 1390874aeea5SJeff Kirsher } else { 1391874aeea5SJeff Kirsher netif_err(efx, hw, efx->net_dev, 1392874aeea5SJeff Kirsher "SYSTEM ERROR - max number of errors seen." 1393874aeea5SJeff Kirsher "NIC will be disabled\n"); 1394874aeea5SJeff Kirsher efx_schedule_reset(efx, RESET_TYPE_DISABLE); 1395874aeea5SJeff Kirsher } 1396874aeea5SJeff Kirsher 1397874aeea5SJeff Kirsher return IRQ_HANDLED; 1398874aeea5SJeff Kirsher } 1399874aeea5SJeff Kirsher 1400874aeea5SJeff Kirsher /* Handle a legacy interrupt 1401874aeea5SJeff Kirsher * Acknowledges the interrupt and schedule event queue processing. 1402874aeea5SJeff Kirsher */ 1403874aeea5SJeff Kirsher static irqreturn_t efx_legacy_interrupt(int irq, void *dev_id) 1404874aeea5SJeff Kirsher { 1405874aeea5SJeff Kirsher struct efx_nic *efx = dev_id; 1406874aeea5SJeff Kirsher efx_oword_t *int_ker = efx->irq_status.addr; 1407874aeea5SJeff Kirsher irqreturn_t result = IRQ_NONE; 1408874aeea5SJeff Kirsher struct efx_channel *channel; 1409874aeea5SJeff Kirsher efx_dword_t reg; 1410874aeea5SJeff Kirsher u32 queues; 1411874aeea5SJeff Kirsher int syserr; 1412874aeea5SJeff Kirsher 1413874aeea5SJeff Kirsher /* Could this be ours? If interrupts are disabled then the 1414874aeea5SJeff Kirsher * channel state may not be valid. 1415874aeea5SJeff Kirsher */ 1416874aeea5SJeff Kirsher if (!efx->legacy_irq_enabled) 1417874aeea5SJeff Kirsher return result; 1418874aeea5SJeff Kirsher 1419874aeea5SJeff Kirsher /* Read the ISR which also ACKs the interrupts */ 1420874aeea5SJeff Kirsher efx_readd(efx, ®, FR_BZ_INT_ISR0); 1421874aeea5SJeff Kirsher queues = EFX_EXTRACT_DWORD(reg, 0, 31); 1422874aeea5SJeff Kirsher 14231646a6f3SBen Hutchings /* Handle non-event-queue sources */ 14241646a6f3SBen Hutchings if (queues & (1U << efx->irq_level)) { 1425874aeea5SJeff Kirsher syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); 1426874aeea5SJeff Kirsher if (unlikely(syserr)) 1427874aeea5SJeff Kirsher return efx_nic_fatal_interrupt(efx); 14281646a6f3SBen Hutchings efx->last_irq_cpu = raw_smp_processor_id(); 1429874aeea5SJeff Kirsher } 1430874aeea5SJeff Kirsher 1431874aeea5SJeff Kirsher if (queues != 0) { 1432874aeea5SJeff Kirsher if (EFX_WORKAROUND_15783(efx)) 1433874aeea5SJeff Kirsher efx->irq_zero_count = 0; 1434874aeea5SJeff Kirsher 1435874aeea5SJeff Kirsher /* Schedule processing of any interrupting queues */ 1436874aeea5SJeff Kirsher efx_for_each_channel(channel, efx) { 1437874aeea5SJeff Kirsher if (queues & 1) 14381646a6f3SBen Hutchings efx_schedule_channel_irq(channel); 1439874aeea5SJeff Kirsher queues >>= 1; 1440874aeea5SJeff Kirsher } 1441874aeea5SJeff Kirsher result = IRQ_HANDLED; 1442874aeea5SJeff Kirsher 1443874aeea5SJeff Kirsher } else if (EFX_WORKAROUND_15783(efx)) { 1444874aeea5SJeff Kirsher efx_qword_t *event; 1445874aeea5SJeff Kirsher 1446874aeea5SJeff Kirsher /* We can't return IRQ_HANDLED more than once on seeing ISR=0 1447874aeea5SJeff Kirsher * because this might be a shared interrupt. */ 1448874aeea5SJeff Kirsher if (efx->irq_zero_count++ == 0) 1449874aeea5SJeff Kirsher result = IRQ_HANDLED; 1450874aeea5SJeff Kirsher 1451874aeea5SJeff Kirsher /* Ensure we schedule or rearm all event queues */ 1452874aeea5SJeff Kirsher efx_for_each_channel(channel, efx) { 1453874aeea5SJeff Kirsher event = efx_event(channel, channel->eventq_read_ptr); 1454874aeea5SJeff Kirsher if (efx_event_present(event)) 14551646a6f3SBen Hutchings efx_schedule_channel_irq(channel); 1456874aeea5SJeff Kirsher else 1457874aeea5SJeff Kirsher efx_nic_eventq_read_ack(channel); 1458874aeea5SJeff Kirsher } 1459874aeea5SJeff Kirsher } 1460874aeea5SJeff Kirsher 14611646a6f3SBen Hutchings if (result == IRQ_HANDLED) 1462874aeea5SJeff Kirsher netif_vdbg(efx, intr, efx->net_dev, 1463874aeea5SJeff Kirsher "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 1464874aeea5SJeff Kirsher irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 1465874aeea5SJeff Kirsher 1466874aeea5SJeff Kirsher return result; 1467874aeea5SJeff Kirsher } 1468874aeea5SJeff Kirsher 1469874aeea5SJeff Kirsher /* Handle an MSI interrupt 1470874aeea5SJeff Kirsher * 1471874aeea5SJeff Kirsher * Handle an MSI hardware interrupt. This routine schedules event 1472874aeea5SJeff Kirsher * queue processing. No interrupt acknowledgement cycle is necessary. 1473874aeea5SJeff Kirsher * Also, we never need to check that the interrupt is for us, since 1474874aeea5SJeff Kirsher * MSI interrupts cannot be shared. 1475874aeea5SJeff Kirsher */ 1476874aeea5SJeff Kirsher static irqreturn_t efx_msi_interrupt(int irq, void *dev_id) 1477874aeea5SJeff Kirsher { 1478874aeea5SJeff Kirsher struct efx_channel *channel = *(struct efx_channel **)dev_id; 1479874aeea5SJeff Kirsher struct efx_nic *efx = channel->efx; 1480874aeea5SJeff Kirsher efx_oword_t *int_ker = efx->irq_status.addr; 1481874aeea5SJeff Kirsher int syserr; 1482874aeea5SJeff Kirsher 1483874aeea5SJeff Kirsher netif_vdbg(efx, intr, efx->net_dev, 1484874aeea5SJeff Kirsher "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", 1485874aeea5SJeff Kirsher irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); 1486874aeea5SJeff Kirsher 14871646a6f3SBen Hutchings /* Handle non-event-queue sources */ 14881646a6f3SBen Hutchings if (channel->channel == efx->irq_level) { 1489874aeea5SJeff Kirsher syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); 1490874aeea5SJeff Kirsher if (unlikely(syserr)) 1491874aeea5SJeff Kirsher return efx_nic_fatal_interrupt(efx); 14921646a6f3SBen Hutchings efx->last_irq_cpu = raw_smp_processor_id(); 1493874aeea5SJeff Kirsher } 1494874aeea5SJeff Kirsher 1495874aeea5SJeff Kirsher /* Schedule processing of the channel */ 14961646a6f3SBen Hutchings efx_schedule_channel_irq(channel); 1497874aeea5SJeff Kirsher 1498874aeea5SJeff Kirsher return IRQ_HANDLED; 1499874aeea5SJeff Kirsher } 1500874aeea5SJeff Kirsher 1501874aeea5SJeff Kirsher 1502874aeea5SJeff Kirsher /* Setup RSS indirection table. 1503874aeea5SJeff Kirsher * This maps from the hash value of the packet to RXQ 1504874aeea5SJeff Kirsher */ 1505874aeea5SJeff Kirsher void efx_nic_push_rx_indir_table(struct efx_nic *efx) 1506874aeea5SJeff Kirsher { 1507874aeea5SJeff Kirsher size_t i = 0; 1508874aeea5SJeff Kirsher efx_dword_t dword; 1509874aeea5SJeff Kirsher 1510874aeea5SJeff Kirsher if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) 1511874aeea5SJeff Kirsher return; 1512874aeea5SJeff Kirsher 1513874aeea5SJeff Kirsher BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) != 1514874aeea5SJeff Kirsher FR_BZ_RX_INDIRECTION_TBL_ROWS); 1515874aeea5SJeff Kirsher 1516874aeea5SJeff Kirsher for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) { 1517874aeea5SJeff Kirsher EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE, 1518874aeea5SJeff Kirsher efx->rx_indir_table[i]); 1519874aeea5SJeff Kirsher efx_writed_table(efx, &dword, FR_BZ_RX_INDIRECTION_TBL, i); 1520874aeea5SJeff Kirsher } 1521874aeea5SJeff Kirsher } 1522874aeea5SJeff Kirsher 1523874aeea5SJeff Kirsher /* Hook interrupt handler(s) 1524874aeea5SJeff Kirsher * Try MSI and then legacy interrupts. 1525874aeea5SJeff Kirsher */ 1526874aeea5SJeff Kirsher int efx_nic_init_interrupt(struct efx_nic *efx) 1527874aeea5SJeff Kirsher { 1528874aeea5SJeff Kirsher struct efx_channel *channel; 1529874aeea5SJeff Kirsher int rc; 1530874aeea5SJeff Kirsher 1531874aeea5SJeff Kirsher if (!EFX_INT_MODE_USE_MSI(efx)) { 1532874aeea5SJeff Kirsher irq_handler_t handler; 1533874aeea5SJeff Kirsher if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) 1534874aeea5SJeff Kirsher handler = efx_legacy_interrupt; 1535874aeea5SJeff Kirsher else 1536874aeea5SJeff Kirsher handler = falcon_legacy_interrupt_a1; 1537874aeea5SJeff Kirsher 1538874aeea5SJeff Kirsher rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED, 1539874aeea5SJeff Kirsher efx->name, efx); 1540874aeea5SJeff Kirsher if (rc) { 1541874aeea5SJeff Kirsher netif_err(efx, drv, efx->net_dev, 1542874aeea5SJeff Kirsher "failed to hook legacy IRQ %d\n", 1543874aeea5SJeff Kirsher efx->pci_dev->irq); 1544874aeea5SJeff Kirsher goto fail1; 1545874aeea5SJeff Kirsher } 1546874aeea5SJeff Kirsher return 0; 1547874aeea5SJeff Kirsher } 1548874aeea5SJeff Kirsher 1549874aeea5SJeff Kirsher /* Hook MSI or MSI-X interrupt */ 1550874aeea5SJeff Kirsher efx_for_each_channel(channel, efx) { 1551874aeea5SJeff Kirsher rc = request_irq(channel->irq, efx_msi_interrupt, 1552874aeea5SJeff Kirsher IRQF_PROBE_SHARED, /* Not shared */ 1553874aeea5SJeff Kirsher efx->channel_name[channel->channel], 1554874aeea5SJeff Kirsher &efx->channel[channel->channel]); 1555874aeea5SJeff Kirsher if (rc) { 1556874aeea5SJeff Kirsher netif_err(efx, drv, efx->net_dev, 1557874aeea5SJeff Kirsher "failed to hook IRQ %d\n", channel->irq); 1558874aeea5SJeff Kirsher goto fail2; 1559874aeea5SJeff Kirsher } 1560874aeea5SJeff Kirsher } 1561874aeea5SJeff Kirsher 1562874aeea5SJeff Kirsher return 0; 1563874aeea5SJeff Kirsher 1564874aeea5SJeff Kirsher fail2: 1565874aeea5SJeff Kirsher efx_for_each_channel(channel, efx) 1566874aeea5SJeff Kirsher free_irq(channel->irq, &efx->channel[channel->channel]); 1567874aeea5SJeff Kirsher fail1: 1568874aeea5SJeff Kirsher return rc; 1569874aeea5SJeff Kirsher } 1570874aeea5SJeff Kirsher 1571874aeea5SJeff Kirsher void efx_nic_fini_interrupt(struct efx_nic *efx) 1572874aeea5SJeff Kirsher { 1573874aeea5SJeff Kirsher struct efx_channel *channel; 1574874aeea5SJeff Kirsher efx_oword_t reg; 1575874aeea5SJeff Kirsher 1576874aeea5SJeff Kirsher /* Disable MSI/MSI-X interrupts */ 1577874aeea5SJeff Kirsher efx_for_each_channel(channel, efx) { 1578874aeea5SJeff Kirsher if (channel->irq) 1579874aeea5SJeff Kirsher free_irq(channel->irq, &efx->channel[channel->channel]); 1580874aeea5SJeff Kirsher } 1581874aeea5SJeff Kirsher 1582874aeea5SJeff Kirsher /* ACK legacy interrupt */ 1583874aeea5SJeff Kirsher if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) 1584874aeea5SJeff Kirsher efx_reado(efx, ®, FR_BZ_INT_ISR0); 1585874aeea5SJeff Kirsher else 1586874aeea5SJeff Kirsher falcon_irq_ack_a1(efx); 1587874aeea5SJeff Kirsher 1588874aeea5SJeff Kirsher /* Disable legacy interrupt */ 1589874aeea5SJeff Kirsher if (efx->legacy_irq) 1590874aeea5SJeff Kirsher free_irq(efx->legacy_irq, efx); 1591874aeea5SJeff Kirsher } 1592874aeea5SJeff Kirsher 1593874aeea5SJeff Kirsher u32 efx_nic_fpga_ver(struct efx_nic *efx) 1594874aeea5SJeff Kirsher { 1595874aeea5SJeff Kirsher efx_oword_t altera_build; 1596874aeea5SJeff Kirsher efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD); 1597874aeea5SJeff Kirsher return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER); 1598874aeea5SJeff Kirsher } 1599874aeea5SJeff Kirsher 1600874aeea5SJeff Kirsher void efx_nic_init_common(struct efx_nic *efx) 1601874aeea5SJeff Kirsher { 1602874aeea5SJeff Kirsher efx_oword_t temp; 1603874aeea5SJeff Kirsher 1604874aeea5SJeff Kirsher /* Set positions of descriptor caches in SRAM. */ 1605874aeea5SJeff Kirsher EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, 1606874aeea5SJeff Kirsher efx->type->tx_dc_base / 8); 1607874aeea5SJeff Kirsher efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG); 1608874aeea5SJeff Kirsher EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, 1609874aeea5SJeff Kirsher efx->type->rx_dc_base / 8); 1610874aeea5SJeff Kirsher efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG); 1611874aeea5SJeff Kirsher 1612874aeea5SJeff Kirsher /* Set TX descriptor cache size. */ 1613874aeea5SJeff Kirsher BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER)); 1614874aeea5SJeff Kirsher EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER); 1615874aeea5SJeff Kirsher efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG); 1616874aeea5SJeff Kirsher 1617874aeea5SJeff Kirsher /* Set RX descriptor cache size. Set low watermark to size-8, as 1618874aeea5SJeff Kirsher * this allows most efficient prefetching. 1619874aeea5SJeff Kirsher */ 1620874aeea5SJeff Kirsher BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER)); 1621874aeea5SJeff Kirsher EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER); 1622874aeea5SJeff Kirsher efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG); 1623874aeea5SJeff Kirsher EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8); 1624874aeea5SJeff Kirsher efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM); 1625874aeea5SJeff Kirsher 1626874aeea5SJeff Kirsher /* Program INT_KER address */ 1627874aeea5SJeff Kirsher EFX_POPULATE_OWORD_2(temp, 1628874aeea5SJeff Kirsher FRF_AZ_NORM_INT_VEC_DIS_KER, 1629874aeea5SJeff Kirsher EFX_INT_MODE_USE_MSI(efx), 1630874aeea5SJeff Kirsher FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr); 1631874aeea5SJeff Kirsher efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER); 1632874aeea5SJeff Kirsher 1633874aeea5SJeff Kirsher if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx)) 1634874aeea5SJeff Kirsher /* Use an interrupt level unused by event queues */ 16351646a6f3SBen Hutchings efx->irq_level = 0x1f; 1636874aeea5SJeff Kirsher else 1637874aeea5SJeff Kirsher /* Use a valid MSI-X vector */ 16381646a6f3SBen Hutchings efx->irq_level = 0; 1639874aeea5SJeff Kirsher 1640874aeea5SJeff Kirsher /* Enable all the genuinely fatal interrupts. (They are still 1641874aeea5SJeff Kirsher * masked by the overall interrupt mask, controlled by 1642874aeea5SJeff Kirsher * falcon_interrupts()). 1643874aeea5SJeff Kirsher * 1644874aeea5SJeff Kirsher * Note: All other fatal interrupts are enabled 1645874aeea5SJeff Kirsher */ 1646874aeea5SJeff Kirsher EFX_POPULATE_OWORD_3(temp, 1647874aeea5SJeff Kirsher FRF_AZ_ILL_ADR_INT_KER_EN, 1, 1648874aeea5SJeff Kirsher FRF_AZ_RBUF_OWN_INT_KER_EN, 1, 1649874aeea5SJeff Kirsher FRF_AZ_TBUF_OWN_INT_KER_EN, 1); 1650874aeea5SJeff Kirsher if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) 1651874aeea5SJeff Kirsher EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1); 1652874aeea5SJeff Kirsher EFX_INVERT_OWORD(temp); 1653874aeea5SJeff Kirsher efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER); 1654874aeea5SJeff Kirsher 1655874aeea5SJeff Kirsher efx_nic_push_rx_indir_table(efx); 1656874aeea5SJeff Kirsher 1657874aeea5SJeff Kirsher /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be 1658874aeea5SJeff Kirsher * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q. 1659874aeea5SJeff Kirsher */ 1660874aeea5SJeff Kirsher efx_reado(efx, &temp, FR_AZ_TX_RESERVED); 1661874aeea5SJeff Kirsher EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe); 1662874aeea5SJeff Kirsher EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1); 1663874aeea5SJeff Kirsher EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1); 1664874aeea5SJeff Kirsher EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 1); 1665874aeea5SJeff Kirsher EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1); 1666874aeea5SJeff Kirsher /* Enable SW_EV to inherit in char driver - assume harmless here */ 1667874aeea5SJeff Kirsher EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1); 1668874aeea5SJeff Kirsher /* Prefetch threshold 2 => fetch when descriptor cache half empty */ 1669874aeea5SJeff Kirsher EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2); 1670874aeea5SJeff Kirsher /* Disable hardware watchdog which can misfire */ 1671874aeea5SJeff Kirsher EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff); 1672874aeea5SJeff Kirsher /* Squash TX of packets of 16 bytes or less */ 1673874aeea5SJeff Kirsher if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) 1674874aeea5SJeff Kirsher EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); 1675874aeea5SJeff Kirsher efx_writeo(efx, &temp, FR_AZ_TX_RESERVED); 1676874aeea5SJeff Kirsher 1677874aeea5SJeff Kirsher if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { 1678874aeea5SJeff Kirsher EFX_POPULATE_OWORD_4(temp, 1679874aeea5SJeff Kirsher /* Default values */ 1680874aeea5SJeff Kirsher FRF_BZ_TX_PACE_SB_NOT_AF, 0x15, 1681874aeea5SJeff Kirsher FRF_BZ_TX_PACE_SB_AF, 0xb, 1682874aeea5SJeff Kirsher FRF_BZ_TX_PACE_FB_BASE, 0, 1683874aeea5SJeff Kirsher /* Allow large pace values in the 1684874aeea5SJeff Kirsher * fast bin. */ 1685874aeea5SJeff Kirsher FRF_BZ_TX_PACE_BIN_TH, 1686874aeea5SJeff Kirsher FFE_BZ_TX_PACE_RESERVED); 1687874aeea5SJeff Kirsher efx_writeo(efx, &temp, FR_BZ_TX_PACE); 1688874aeea5SJeff Kirsher } 1689874aeea5SJeff Kirsher } 1690874aeea5SJeff Kirsher 1691874aeea5SJeff Kirsher /* Register dump */ 1692874aeea5SJeff Kirsher 1693874aeea5SJeff Kirsher #define REGISTER_REVISION_A 1 1694874aeea5SJeff Kirsher #define REGISTER_REVISION_B 2 1695874aeea5SJeff Kirsher #define REGISTER_REVISION_C 3 1696874aeea5SJeff Kirsher #define REGISTER_REVISION_Z 3 /* latest revision */ 1697874aeea5SJeff Kirsher 1698874aeea5SJeff Kirsher struct efx_nic_reg { 1699874aeea5SJeff Kirsher u32 offset:24; 1700874aeea5SJeff Kirsher u32 min_revision:2, max_revision:2; 1701874aeea5SJeff Kirsher }; 1702874aeea5SJeff Kirsher 1703874aeea5SJeff Kirsher #define REGISTER(name, min_rev, max_rev) { \ 1704874aeea5SJeff Kirsher FR_ ## min_rev ## max_rev ## _ ## name, \ 1705874aeea5SJeff Kirsher REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev \ 1706874aeea5SJeff Kirsher } 1707874aeea5SJeff Kirsher #define REGISTER_AA(name) REGISTER(name, A, A) 1708874aeea5SJeff Kirsher #define REGISTER_AB(name) REGISTER(name, A, B) 1709874aeea5SJeff Kirsher #define REGISTER_AZ(name) REGISTER(name, A, Z) 1710874aeea5SJeff Kirsher #define REGISTER_BB(name) REGISTER(name, B, B) 1711874aeea5SJeff Kirsher #define REGISTER_BZ(name) REGISTER(name, B, Z) 1712874aeea5SJeff Kirsher #define REGISTER_CZ(name) REGISTER(name, C, Z) 1713874aeea5SJeff Kirsher 1714874aeea5SJeff Kirsher static const struct efx_nic_reg efx_nic_regs[] = { 1715874aeea5SJeff Kirsher REGISTER_AZ(ADR_REGION), 1716874aeea5SJeff Kirsher REGISTER_AZ(INT_EN_KER), 1717874aeea5SJeff Kirsher REGISTER_BZ(INT_EN_CHAR), 1718874aeea5SJeff Kirsher REGISTER_AZ(INT_ADR_KER), 1719874aeea5SJeff Kirsher REGISTER_BZ(INT_ADR_CHAR), 1720874aeea5SJeff Kirsher /* INT_ACK_KER is WO */ 1721874aeea5SJeff Kirsher /* INT_ISR0 is RC */ 1722874aeea5SJeff Kirsher REGISTER_AZ(HW_INIT), 1723874aeea5SJeff Kirsher REGISTER_CZ(USR_EV_CFG), 1724874aeea5SJeff Kirsher REGISTER_AB(EE_SPI_HCMD), 1725874aeea5SJeff Kirsher REGISTER_AB(EE_SPI_HADR), 1726874aeea5SJeff Kirsher REGISTER_AB(EE_SPI_HDATA), 1727874aeea5SJeff Kirsher REGISTER_AB(EE_BASE_PAGE), 1728874aeea5SJeff Kirsher REGISTER_AB(EE_VPD_CFG0), 1729874aeea5SJeff Kirsher /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */ 1730874aeea5SJeff Kirsher /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */ 1731874aeea5SJeff Kirsher /* PCIE_CORE_INDIRECT is indirect */ 1732874aeea5SJeff Kirsher REGISTER_AB(NIC_STAT), 1733874aeea5SJeff Kirsher REGISTER_AB(GPIO_CTL), 1734874aeea5SJeff Kirsher REGISTER_AB(GLB_CTL), 1735874aeea5SJeff Kirsher /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */ 1736874aeea5SJeff Kirsher REGISTER_BZ(DP_CTRL), 1737874aeea5SJeff Kirsher REGISTER_AZ(MEM_STAT), 1738874aeea5SJeff Kirsher REGISTER_AZ(CS_DEBUG), 1739874aeea5SJeff Kirsher REGISTER_AZ(ALTERA_BUILD), 1740874aeea5SJeff Kirsher REGISTER_AZ(CSR_SPARE), 1741874aeea5SJeff Kirsher REGISTER_AB(PCIE_SD_CTL0123), 1742874aeea5SJeff Kirsher REGISTER_AB(PCIE_SD_CTL45), 1743874aeea5SJeff Kirsher REGISTER_AB(PCIE_PCS_CTL_STAT), 1744874aeea5SJeff Kirsher /* DEBUG_DATA_OUT is not used */ 1745874aeea5SJeff Kirsher /* DRV_EV is WO */ 1746874aeea5SJeff Kirsher REGISTER_AZ(EVQ_CTL), 1747874aeea5SJeff Kirsher REGISTER_AZ(EVQ_CNT1), 1748874aeea5SJeff Kirsher REGISTER_AZ(EVQ_CNT2), 1749874aeea5SJeff Kirsher REGISTER_AZ(BUF_TBL_CFG), 1750874aeea5SJeff Kirsher REGISTER_AZ(SRM_RX_DC_CFG), 1751874aeea5SJeff Kirsher REGISTER_AZ(SRM_TX_DC_CFG), 1752874aeea5SJeff Kirsher REGISTER_AZ(SRM_CFG), 1753874aeea5SJeff Kirsher /* BUF_TBL_UPD is WO */ 1754874aeea5SJeff Kirsher REGISTER_AZ(SRM_UPD_EVQ), 1755874aeea5SJeff Kirsher REGISTER_AZ(SRAM_PARITY), 1756874aeea5SJeff Kirsher REGISTER_AZ(RX_CFG), 1757874aeea5SJeff Kirsher REGISTER_BZ(RX_FILTER_CTL), 1758874aeea5SJeff Kirsher /* RX_FLUSH_DESCQ is WO */ 1759874aeea5SJeff Kirsher REGISTER_AZ(RX_DC_CFG), 1760874aeea5SJeff Kirsher REGISTER_AZ(RX_DC_PF_WM), 1761874aeea5SJeff Kirsher REGISTER_BZ(RX_RSS_TKEY), 1762874aeea5SJeff Kirsher /* RX_NODESC_DROP is RC */ 1763874aeea5SJeff Kirsher REGISTER_AA(RX_SELF_RST), 1764874aeea5SJeff Kirsher /* RX_DEBUG, RX_PUSH_DROP are not used */ 1765874aeea5SJeff Kirsher REGISTER_CZ(RX_RSS_IPV6_REG1), 1766874aeea5SJeff Kirsher REGISTER_CZ(RX_RSS_IPV6_REG2), 1767874aeea5SJeff Kirsher REGISTER_CZ(RX_RSS_IPV6_REG3), 1768874aeea5SJeff Kirsher /* TX_FLUSH_DESCQ is WO */ 1769874aeea5SJeff Kirsher REGISTER_AZ(TX_DC_CFG), 1770874aeea5SJeff Kirsher REGISTER_AA(TX_CHKSM_CFG), 1771874aeea5SJeff Kirsher REGISTER_AZ(TX_CFG), 1772874aeea5SJeff Kirsher /* TX_PUSH_DROP is not used */ 1773874aeea5SJeff Kirsher REGISTER_AZ(TX_RESERVED), 1774874aeea5SJeff Kirsher REGISTER_BZ(TX_PACE), 1775874aeea5SJeff Kirsher /* TX_PACE_DROP_QID is RC */ 1776874aeea5SJeff Kirsher REGISTER_BB(TX_VLAN), 1777874aeea5SJeff Kirsher REGISTER_BZ(TX_IPFIL_PORTEN), 1778874aeea5SJeff Kirsher REGISTER_AB(MD_TXD), 1779874aeea5SJeff Kirsher REGISTER_AB(MD_RXD), 1780874aeea5SJeff Kirsher REGISTER_AB(MD_CS), 1781874aeea5SJeff Kirsher REGISTER_AB(MD_PHY_ADR), 1782874aeea5SJeff Kirsher REGISTER_AB(MD_ID), 1783874aeea5SJeff Kirsher /* MD_STAT is RC */ 1784874aeea5SJeff Kirsher REGISTER_AB(MAC_STAT_DMA), 1785874aeea5SJeff Kirsher REGISTER_AB(MAC_CTRL), 1786874aeea5SJeff Kirsher REGISTER_BB(GEN_MODE), 1787874aeea5SJeff Kirsher REGISTER_AB(MAC_MC_HASH_REG0), 1788874aeea5SJeff Kirsher REGISTER_AB(MAC_MC_HASH_REG1), 1789874aeea5SJeff Kirsher REGISTER_AB(GM_CFG1), 1790874aeea5SJeff Kirsher REGISTER_AB(GM_CFG2), 1791874aeea5SJeff Kirsher /* GM_IPG and GM_HD are not used */ 1792874aeea5SJeff Kirsher REGISTER_AB(GM_MAX_FLEN), 1793874aeea5SJeff Kirsher /* GM_TEST is not used */ 1794874aeea5SJeff Kirsher REGISTER_AB(GM_ADR1), 1795874aeea5SJeff Kirsher REGISTER_AB(GM_ADR2), 1796874aeea5SJeff Kirsher REGISTER_AB(GMF_CFG0), 1797874aeea5SJeff Kirsher REGISTER_AB(GMF_CFG1), 1798874aeea5SJeff Kirsher REGISTER_AB(GMF_CFG2), 1799874aeea5SJeff Kirsher REGISTER_AB(GMF_CFG3), 1800874aeea5SJeff Kirsher REGISTER_AB(GMF_CFG4), 1801874aeea5SJeff Kirsher REGISTER_AB(GMF_CFG5), 1802874aeea5SJeff Kirsher REGISTER_BB(TX_SRC_MAC_CTL), 1803874aeea5SJeff Kirsher REGISTER_AB(XM_ADR_LO), 1804874aeea5SJeff Kirsher REGISTER_AB(XM_ADR_HI), 1805874aeea5SJeff Kirsher REGISTER_AB(XM_GLB_CFG), 1806874aeea5SJeff Kirsher REGISTER_AB(XM_TX_CFG), 1807874aeea5SJeff Kirsher REGISTER_AB(XM_RX_CFG), 1808874aeea5SJeff Kirsher REGISTER_AB(XM_MGT_INT_MASK), 1809874aeea5SJeff Kirsher REGISTER_AB(XM_FC), 1810874aeea5SJeff Kirsher REGISTER_AB(XM_PAUSE_TIME), 1811874aeea5SJeff Kirsher REGISTER_AB(XM_TX_PARAM), 1812874aeea5SJeff Kirsher REGISTER_AB(XM_RX_PARAM), 1813874aeea5SJeff Kirsher /* XM_MGT_INT_MSK (note no 'A') is RC */ 1814874aeea5SJeff Kirsher REGISTER_AB(XX_PWR_RST), 1815874aeea5SJeff Kirsher REGISTER_AB(XX_SD_CTL), 1816874aeea5SJeff Kirsher REGISTER_AB(XX_TXDRV_CTL), 1817874aeea5SJeff Kirsher /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */ 1818874aeea5SJeff Kirsher /* XX_CORE_STAT is partly RC */ 1819874aeea5SJeff Kirsher }; 1820874aeea5SJeff Kirsher 1821874aeea5SJeff Kirsher struct efx_nic_reg_table { 1822874aeea5SJeff Kirsher u32 offset:24; 1823874aeea5SJeff Kirsher u32 min_revision:2, max_revision:2; 1824874aeea5SJeff Kirsher u32 step:6, rows:21; 1825874aeea5SJeff Kirsher }; 1826874aeea5SJeff Kirsher 1827874aeea5SJeff Kirsher #define REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) { \ 1828874aeea5SJeff Kirsher offset, \ 1829874aeea5SJeff Kirsher REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev, \ 1830874aeea5SJeff Kirsher step, rows \ 1831874aeea5SJeff Kirsher } 1832874aeea5SJeff Kirsher #define REGISTER_TABLE(name, min_rev, max_rev) \ 1833874aeea5SJeff Kirsher REGISTER_TABLE_DIMENSIONS( \ 1834874aeea5SJeff Kirsher name, FR_ ## min_rev ## max_rev ## _ ## name, \ 1835874aeea5SJeff Kirsher min_rev, max_rev, \ 1836874aeea5SJeff Kirsher FR_ ## min_rev ## max_rev ## _ ## name ## _STEP, \ 1837874aeea5SJeff Kirsher FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS) 1838874aeea5SJeff Kirsher #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A) 1839874aeea5SJeff Kirsher #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z) 1840874aeea5SJeff Kirsher #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B) 1841874aeea5SJeff Kirsher #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z) 1842874aeea5SJeff Kirsher #define REGISTER_TABLE_BB_CZ(name) \ 1843874aeea5SJeff Kirsher REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B, \ 1844874aeea5SJeff Kirsher FR_BZ_ ## name ## _STEP, \ 1845874aeea5SJeff Kirsher FR_BB_ ## name ## _ROWS), \ 1846874aeea5SJeff Kirsher REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z, \ 1847874aeea5SJeff Kirsher FR_BZ_ ## name ## _STEP, \ 1848874aeea5SJeff Kirsher FR_CZ_ ## name ## _ROWS) 1849874aeea5SJeff Kirsher #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z) 1850874aeea5SJeff Kirsher 1851874aeea5SJeff Kirsher static const struct efx_nic_reg_table efx_nic_reg_tables[] = { 1852874aeea5SJeff Kirsher /* DRIVER is not used */ 1853874aeea5SJeff Kirsher /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */ 1854874aeea5SJeff Kirsher REGISTER_TABLE_BB(TX_IPFIL_TBL), 1855874aeea5SJeff Kirsher REGISTER_TABLE_BB(TX_SRC_MAC_TBL), 1856874aeea5SJeff Kirsher REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER), 1857874aeea5SJeff Kirsher REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL), 1858874aeea5SJeff Kirsher REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER), 1859874aeea5SJeff Kirsher REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL), 1860874aeea5SJeff Kirsher REGISTER_TABLE_AA(EVQ_PTR_TBL_KER), 1861874aeea5SJeff Kirsher REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL), 1862874aeea5SJeff Kirsher /* We can't reasonably read all of the buffer table (up to 8MB!). 1863874aeea5SJeff Kirsher * However this driver will only use a few entries. Reading 1864874aeea5SJeff Kirsher * 1K entries allows for some expansion of queue count and 1865874aeea5SJeff Kirsher * size before we need to change the version. */ 1866874aeea5SJeff Kirsher REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER, 1867874aeea5SJeff Kirsher A, A, 8, 1024), 1868874aeea5SJeff Kirsher REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL, 1869874aeea5SJeff Kirsher B, Z, 8, 1024), 1870874aeea5SJeff Kirsher REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0), 1871874aeea5SJeff Kirsher REGISTER_TABLE_BB_CZ(TIMER_TBL), 1872874aeea5SJeff Kirsher REGISTER_TABLE_BB_CZ(TX_PACE_TBL), 1873874aeea5SJeff Kirsher REGISTER_TABLE_BZ(RX_INDIRECTION_TBL), 1874874aeea5SJeff Kirsher /* TX_FILTER_TBL0 is huge and not used by this driver */ 1875874aeea5SJeff Kirsher REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0), 1876874aeea5SJeff Kirsher REGISTER_TABLE_CZ(MC_TREG_SMEM), 1877874aeea5SJeff Kirsher /* MSIX_PBA_TABLE is not mapped */ 1878874aeea5SJeff Kirsher /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */ 1879874aeea5SJeff Kirsher REGISTER_TABLE_BZ(RX_FILTER_TBL0), 1880874aeea5SJeff Kirsher }; 1881874aeea5SJeff Kirsher 1882874aeea5SJeff Kirsher size_t efx_nic_get_regs_len(struct efx_nic *efx) 1883874aeea5SJeff Kirsher { 1884874aeea5SJeff Kirsher const struct efx_nic_reg *reg; 1885874aeea5SJeff Kirsher const struct efx_nic_reg_table *table; 1886874aeea5SJeff Kirsher size_t len = 0; 1887874aeea5SJeff Kirsher 1888874aeea5SJeff Kirsher for (reg = efx_nic_regs; 1889874aeea5SJeff Kirsher reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs); 1890874aeea5SJeff Kirsher reg++) 1891874aeea5SJeff Kirsher if (efx->type->revision >= reg->min_revision && 1892874aeea5SJeff Kirsher efx->type->revision <= reg->max_revision) 1893874aeea5SJeff Kirsher len += sizeof(efx_oword_t); 1894874aeea5SJeff Kirsher 1895874aeea5SJeff Kirsher for (table = efx_nic_reg_tables; 1896874aeea5SJeff Kirsher table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables); 1897874aeea5SJeff Kirsher table++) 1898874aeea5SJeff Kirsher if (efx->type->revision >= table->min_revision && 1899874aeea5SJeff Kirsher efx->type->revision <= table->max_revision) 1900874aeea5SJeff Kirsher len += table->rows * min_t(size_t, table->step, 16); 1901874aeea5SJeff Kirsher 1902874aeea5SJeff Kirsher return len; 1903874aeea5SJeff Kirsher } 1904874aeea5SJeff Kirsher 1905874aeea5SJeff Kirsher void efx_nic_get_regs(struct efx_nic *efx, void *buf) 1906874aeea5SJeff Kirsher { 1907874aeea5SJeff Kirsher const struct efx_nic_reg *reg; 1908874aeea5SJeff Kirsher const struct efx_nic_reg_table *table; 1909874aeea5SJeff Kirsher 1910874aeea5SJeff Kirsher for (reg = efx_nic_regs; 1911874aeea5SJeff Kirsher reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs); 1912874aeea5SJeff Kirsher reg++) { 1913874aeea5SJeff Kirsher if (efx->type->revision >= reg->min_revision && 1914874aeea5SJeff Kirsher efx->type->revision <= reg->max_revision) { 1915874aeea5SJeff Kirsher efx_reado(efx, (efx_oword_t *)buf, reg->offset); 1916874aeea5SJeff Kirsher buf += sizeof(efx_oword_t); 1917874aeea5SJeff Kirsher } 1918874aeea5SJeff Kirsher } 1919874aeea5SJeff Kirsher 1920874aeea5SJeff Kirsher for (table = efx_nic_reg_tables; 1921874aeea5SJeff Kirsher table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables); 1922874aeea5SJeff Kirsher table++) { 1923874aeea5SJeff Kirsher size_t size, i; 1924874aeea5SJeff Kirsher 1925874aeea5SJeff Kirsher if (!(efx->type->revision >= table->min_revision && 1926874aeea5SJeff Kirsher efx->type->revision <= table->max_revision)) 1927874aeea5SJeff Kirsher continue; 1928874aeea5SJeff Kirsher 1929874aeea5SJeff Kirsher size = min_t(size_t, table->step, 16); 1930874aeea5SJeff Kirsher 1931874aeea5SJeff Kirsher for (i = 0; i < table->rows; i++) { 1932874aeea5SJeff Kirsher switch (table->step) { 1933874aeea5SJeff Kirsher case 4: /* 32-bit register or SRAM */ 1934874aeea5SJeff Kirsher efx_readd_table(efx, buf, table->offset, i); 1935874aeea5SJeff Kirsher break; 1936874aeea5SJeff Kirsher case 8: /* 64-bit SRAM */ 1937874aeea5SJeff Kirsher efx_sram_readq(efx, 1938874aeea5SJeff Kirsher efx->membase + table->offset, 1939874aeea5SJeff Kirsher buf, i); 1940874aeea5SJeff Kirsher break; 1941874aeea5SJeff Kirsher case 16: /* 128-bit register */ 1942874aeea5SJeff Kirsher efx_reado_table(efx, buf, table->offset, i); 1943874aeea5SJeff Kirsher break; 1944874aeea5SJeff Kirsher case 32: /* 128-bit register, interleaved */ 1945874aeea5SJeff Kirsher efx_reado_table(efx, buf, table->offset, 2 * i); 1946874aeea5SJeff Kirsher break; 1947874aeea5SJeff Kirsher default: 1948874aeea5SJeff Kirsher WARN_ON(1); 1949874aeea5SJeff Kirsher return; 1950874aeea5SJeff Kirsher } 1951874aeea5SJeff Kirsher buf += size; 1952874aeea5SJeff Kirsher } 1953874aeea5SJeff Kirsher } 1954874aeea5SJeff Kirsher } 1955