1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /****************************************************************************
3  * Driver for Solarflare network controllers and boards
4  * Copyright 2005-2006 Fen Systems Ltd.
5  * Copyright 2005-2013 Solarflare Communications Inc.
6  */
7 
8 /* Common definitions for all Efx net driver code */
9 
10 #ifndef EFX_NET_DRIVER_H
11 #define EFX_NET_DRIVER_H
12 
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/ethtool.h>
16 #include <linux/if_vlan.h>
17 #include <linux/timer.h>
18 #include <linux/mdio.h>
19 #include <linux/list.h>
20 #include <linux/pci.h>
21 #include <linux/device.h>
22 #include <linux/highmem.h>
23 #include <linux/workqueue.h>
24 #include <linux/mutex.h>
25 #include <linux/rwsem.h>
26 #include <linux/vmalloc.h>
27 #include <linux/mtd/mtd.h>
28 #include <net/busy_poll.h>
29 #include <net/xdp.h>
30 
31 #include "enum.h"
32 #include "bitfield.h"
33 #include "filter.h"
34 
35 /**************************************************************************
36  *
37  * Build definitions
38  *
39  **************************************************************************/
40 
41 #ifdef DEBUG
42 #define EFX_WARN_ON_ONCE_PARANOID(x) WARN_ON_ONCE(x)
43 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
44 #else
45 #define EFX_WARN_ON_ONCE_PARANOID(x) do {} while (0)
46 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
47 #endif
48 
49 /**************************************************************************
50  *
51  * Efx data structures
52  *
53  **************************************************************************/
54 
55 #define EFX_MAX_CHANNELS 32U
56 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
57 #define EFX_EXTRA_CHANNEL_IOV	0
58 #define EFX_EXTRA_CHANNEL_PTP	1
59 #define EFX_EXTRA_CHANNEL_TC	2
60 #define EFX_MAX_EXTRA_CHANNELS	3U
61 
62 /* Checksum generation is a per-queue option in hardware, so each
63  * queue visible to the networking core is backed by two hardware TX
64  * queues. */
65 #define EFX_MAX_TX_TC		2
66 #define EFX_MAX_CORE_TX_QUEUES	(EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
67 #define EFX_TXQ_TYPE_OUTER_CSUM	1	/* Outer checksum offload */
68 #define EFX_TXQ_TYPE_INNER_CSUM	2	/* Inner checksum offload */
69 #define EFX_TXQ_TYPE_HIGHPRI	4	/* High-priority (for TC) */
70 #define EFX_TXQ_TYPES		8
71 /* HIGHPRI is Siena-only, and INNER_CSUM is EF10, so no need for both */
72 #define EFX_MAX_TXQ_PER_CHANNEL	4
73 #define EFX_MAX_TX_QUEUES	(EFX_MAX_TXQ_PER_CHANNEL * EFX_MAX_CHANNELS)
74 
75 /* Maximum possible MTU the driver supports */
76 #define EFX_MAX_MTU (9 * 1024)
77 
78 /* Minimum MTU, from RFC791 (IP) */
79 #define EFX_MIN_MTU 68
80 
81 /* Maximum total header length for TSOv2 */
82 #define EFX_TSO2_MAX_HDRLEN	208
83 
84 /* Size of an RX scatter buffer.  Small enough to pack 2 into a 4K page,
85  * and should be a multiple of the cache line size.
86  */
87 #define EFX_RX_USR_BUF_SIZE	(2048 - 256)
88 
89 /* If possible, we should ensure cache line alignment at start and end
90  * of every buffer.  Otherwise, we just need to ensure 4-byte
91  * alignment of the network header.
92  */
93 #if NET_IP_ALIGN == 0
94 #define EFX_RX_BUF_ALIGNMENT	L1_CACHE_BYTES
95 #else
96 #define EFX_RX_BUF_ALIGNMENT	4
97 #endif
98 
99 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
100  * still fit two standard MTU size packets into a single 4K page.
101  */
102 #define EFX_XDP_HEADROOM	128
103 #define EFX_XDP_TAILROOM	SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
104 
105 /* Forward declare Precision Time Protocol (PTP) support structure. */
106 struct efx_ptp_data;
107 struct hwtstamp_config;
108 
109 struct efx_self_tests;
110 
111 /**
112  * struct efx_buffer - A general-purpose DMA buffer
113  * @addr: host base address of the buffer
114  * @dma_addr: DMA base address of the buffer
115  * @len: Buffer length, in bytes
116  *
117  * The NIC uses these buffers for its interrupt status registers and
118  * MAC stats dumps.
119  */
120 struct efx_buffer {
121 	void *addr;
122 	dma_addr_t dma_addr;
123 	unsigned int len;
124 };
125 
126 /**
127  * struct efx_special_buffer - DMA buffer entered into buffer table
128  * @buf: Standard &struct efx_buffer
129  * @index: Buffer index within controller;s buffer table
130  * @entries: Number of buffer table entries
131  *
132  * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE.
133  * Event and descriptor rings are addressed via one or more buffer
134  * table entries (and so can be physically non-contiguous, although we
135  * currently do not take advantage of that).  On Falcon and Siena we
136  * have to take care of allocating and initialising the entries
137  * ourselves.  On later hardware this is managed by the firmware and
138  * @index and @entries are left as 0.
139  */
140 struct efx_special_buffer {
141 	struct efx_buffer buf;
142 	unsigned int index;
143 	unsigned int entries;
144 };
145 
146 /**
147  * struct efx_tx_buffer - buffer state for a TX descriptor
148  * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be
149  *	freed when descriptor completes
150  * @xdpf: When @flags & %EFX_TX_BUF_XDP, the XDP frame information; its @data
151  *	member is the associated buffer to drop a page reference on.
152  * @option: When @flags & %EFX_TX_BUF_OPTION, an EF10-specific option
153  *	descriptor.
154  * @dma_addr: DMA address of the fragment.
155  * @flags: Flags for allocation and DMA mapping type
156  * @len: Length of this fragment.
157  *	This field is zero when the queue slot is empty.
158  * @unmap_len: Length of this fragment to unmap
159  * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.
160  * Only valid if @unmap_len != 0.
161  */
162 struct efx_tx_buffer {
163 	union {
164 		const struct sk_buff *skb;
165 		struct xdp_frame *xdpf;
166 	};
167 	union {
168 		efx_qword_t option;    /* EF10 */
169 		dma_addr_t dma_addr;
170 	};
171 	unsigned short flags;
172 	unsigned short len;
173 	unsigned short unmap_len;
174 	unsigned short dma_offset;
175 };
176 #define EFX_TX_BUF_CONT		1	/* not last descriptor of packet */
177 #define EFX_TX_BUF_SKB		2	/* buffer is last part of skb */
178 #define EFX_TX_BUF_MAP_SINGLE	8	/* buffer was mapped with dma_map_single() */
179 #define EFX_TX_BUF_OPTION	0x10	/* empty buffer for option descriptor */
180 #define EFX_TX_BUF_XDP		0x20	/* buffer was sent with XDP */
181 #define EFX_TX_BUF_TSO_V3	0x40	/* empty buffer for a TSO_V3 descriptor */
182 #define EFX_TX_BUF_EFV		0x100	/* buffer was sent from representor */
183 
184 /**
185  * struct efx_tx_queue - An Efx TX queue
186  *
187  * This is a ring buffer of TX fragments.
188  * Since the TX completion path always executes on the same
189  * CPU and the xmit path can operate on different CPUs,
190  * performance is increased by ensuring that the completion
191  * path and the xmit path operate on different cache lines.
192  * This is particularly important if the xmit path is always
193  * executing on one CPU which is different from the completion
194  * path.  There is also a cache line for members which are
195  * read but not written on the fast path.
196  *
197  * @efx: The associated Efx NIC
198  * @queue: DMA queue number
199  * @label: Label for TX completion events.
200  *	Is our index within @channel->tx_queue array.
201  * @type: configuration type of this TX queue.  A bitmask of %EFX_TXQ_TYPE_* flags.
202  * @tso_version: Version of TSO in use for this queue.
203  * @tso_encap: Is encapsulated TSO supported? Supported in TSOv2 on 8000 series.
204  * @channel: The associated channel
205  * @core_txq: The networking core TX queue structure
206  * @buffer: The software buffer ring
207  * @cb_page: Array of pages of copy buffers.  Carved up according to
208  *	%EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks.
209  * @txd: The hardware descriptor ring
210  * @ptr_mask: The size of the ring minus 1.
211  * @piobuf: PIO buffer region for this TX queue (shared with its partner).
212  *	Size of the region is efx_piobuf_size.
213  * @piobuf_offset: Buffer offset to be specified in PIO descriptors
214  * @initialised: Has hardware queue been initialised?
215  * @timestamping: Is timestamping enabled for this channel?
216  * @xdp_tx: Is this an XDP tx queue?
217  * @read_count: Current read pointer.
218  *	This is the number of buffers that have been removed from both rings.
219  * @old_write_count: The value of @write_count when last checked.
220  *	This is here for performance reasons.  The xmit path will
221  *	only get the up-to-date value of @write_count if this
222  *	variable indicates that the queue is empty.  This is to
223  *	avoid cache-line ping-pong between the xmit path and the
224  *	completion path.
225  * @merge_events: Number of TX merged completion events
226  * @completed_timestamp_major: Top part of the most recent tx timestamp.
227  * @completed_timestamp_minor: Low part of the most recent tx timestamp.
228  * @insert_count: Current insert pointer
229  *	This is the number of buffers that have been added to the
230  *	software ring.
231  * @write_count: Current write pointer
232  *	This is the number of buffers that have been added to the
233  *	hardware ring.
234  * @packet_write_count: Completable write pointer
235  *	This is the write pointer of the last packet written.
236  *	Normally this will equal @write_count, but as option descriptors
237  *	don't produce completion events, they won't update this.
238  *	Filled in iff @efx->type->option_descriptors; only used for PIO.
239  *	Thus, this is written and used on EF10, and neither on farch.
240  * @old_read_count: The value of read_count when last checked.
241  *	This is here for performance reasons.  The xmit path will
242  *	only get the up-to-date value of read_count if this
243  *	variable indicates that the queue is full.  This is to
244  *	avoid cache-line ping-pong between the xmit path and the
245  *	completion path.
246  * @tso_bursts: Number of times TSO xmit invoked by kernel
247  * @tso_long_headers: Number of packets with headers too long for standard
248  *	blocks
249  * @tso_packets: Number of packets via the TSO xmit path
250  * @tso_fallbacks: Number of times TSO fallback used
251  * @pushes: Number of times the TX push feature has been used
252  * @pio_packets: Number of times the TX PIO feature has been used
253  * @xmit_pending: Are any packets waiting to be pushed to the NIC
254  * @cb_packets: Number of times the TX copybreak feature has been used
255  * @notify_count: Count of notified descriptors to the NIC
256  * @empty_read_count: If the completion path has seen the queue as empty
257  *	and the transmission path has not yet checked this, the value of
258  *	@read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
259  */
260 struct efx_tx_queue {
261 	/* Members which don't change on the fast path */
262 	struct efx_nic *efx ____cacheline_aligned_in_smp;
263 	unsigned int queue;
264 	unsigned int label;
265 	unsigned int type;
266 	unsigned int tso_version;
267 	bool tso_encap;
268 	struct efx_channel *channel;
269 	struct netdev_queue *core_txq;
270 	struct efx_tx_buffer *buffer;
271 	struct efx_buffer *cb_page;
272 	struct efx_special_buffer txd;
273 	unsigned int ptr_mask;
274 	void __iomem *piobuf;
275 	unsigned int piobuf_offset;
276 	bool initialised;
277 	bool timestamping;
278 	bool xdp_tx;
279 
280 	/* Members used mainly on the completion path */
281 	unsigned int read_count ____cacheline_aligned_in_smp;
282 	unsigned int old_write_count;
283 	unsigned int merge_events;
284 	unsigned int bytes_compl;
285 	unsigned int pkts_compl;
286 	u32 completed_timestamp_major;
287 	u32 completed_timestamp_minor;
288 
289 	/* Members used only on the xmit path */
290 	unsigned int insert_count ____cacheline_aligned_in_smp;
291 	unsigned int write_count;
292 	unsigned int packet_write_count;
293 	unsigned int old_read_count;
294 	unsigned int tso_bursts;
295 	unsigned int tso_long_headers;
296 	unsigned int tso_packets;
297 	unsigned int tso_fallbacks;
298 	unsigned int pushes;
299 	unsigned int pio_packets;
300 	bool xmit_pending;
301 	unsigned int cb_packets;
302 	unsigned int notify_count;
303 	/* Statistics to supplement MAC stats */
304 	unsigned long tx_packets;
305 
306 	/* Members shared between paths and sometimes updated */
307 	unsigned int empty_read_count ____cacheline_aligned_in_smp;
308 #define EFX_EMPTY_COUNT_VALID 0x80000000
309 	atomic_t flush_outstanding;
310 };
311 
312 #define EFX_TX_CB_ORDER	7
313 #define EFX_TX_CB_SIZE	(1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN
314 
315 /**
316  * struct efx_rx_buffer - An Efx RX data buffer
317  * @dma_addr: DMA base address of the buffer
318  * @page: The associated page buffer.
319  *	Will be %NULL if the buffer slot is currently free.
320  * @page_offset: If pending: offset in @page of DMA base address.
321  *	If completed: offset in @page of Ethernet header.
322  * @len: If pending: length for DMA descriptor.
323  *	If completed: received length, excluding hash prefix.
324  * @flags: Flags for buffer and packet state.  These are only set on the
325  *	first buffer of a scattered packet.
326  */
327 struct efx_rx_buffer {
328 	dma_addr_t dma_addr;
329 	struct page *page;
330 	u16 page_offset;
331 	u16 len;
332 	u16 flags;
333 };
334 #define EFX_RX_BUF_LAST_IN_PAGE	0x0001
335 #define EFX_RX_PKT_CSUMMED	0x0002
336 #define EFX_RX_PKT_DISCARD	0x0004
337 #define EFX_RX_PKT_TCP		0x0040
338 #define EFX_RX_PKT_PREFIX_LEN	0x0080	/* length is in prefix only */
339 #define EFX_RX_PKT_CSUM_LEVEL	0x0200
340 
341 /**
342  * struct efx_rx_page_state - Page-based rx buffer state
343  *
344  * Inserted at the start of every page allocated for receive buffers.
345  * Used to facilitate sharing dma mappings between recycled rx buffers
346  * and those passed up to the kernel.
347  *
348  * @dma_addr: The dma address of this page.
349  */
350 struct efx_rx_page_state {
351 	dma_addr_t dma_addr;
352 
353 	unsigned int __pad[] ____cacheline_aligned;
354 };
355 
356 /**
357  * struct efx_rx_queue - An Efx RX queue
358  * @efx: The associated Efx NIC
359  * @core_index:  Index of network core RX queue.  Will be >= 0 iff this
360  *	is associated with a real RX queue.
361  * @buffer: The software buffer ring
362  * @rxd: The hardware descriptor ring
363  * @ptr_mask: The size of the ring minus 1.
364  * @refill_enabled: Enable refill whenever fill level is low
365  * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
366  *	@rxq_flush_pending.
367  * @grant_credits: Posted RX descriptors need to be granted to the MAE with
368  *	%MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS.  For %EFX_EXTRA_CHANNEL_TC,
369  *	and only supported on EF100.
370  * @added_count: Number of buffers added to the receive queue.
371  * @notified_count: Number of buffers given to NIC (<= @added_count).
372  * @granted_count: Number of buffers granted to the MAE (<= @notified_count).
373  * @removed_count: Number of buffers removed from the receive queue.
374  * @scatter_n: Used by NIC specific receive code.
375  * @scatter_len: Used by NIC specific receive code.
376  * @page_ring: The ring to store DMA mapped pages for reuse.
377  * @page_add: Counter to calculate the write pointer for the recycle ring.
378  * @page_remove: Counter to calculate the read pointer for the recycle ring.
379  * @page_recycle_count: The number of pages that have been recycled.
380  * @page_recycle_failed: The number of pages that couldn't be recycled because
381  *      the kernel still held a reference to them.
382  * @page_recycle_full: The number of pages that were released because the
383  *      recycle ring was full.
384  * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
385  * @max_fill: RX descriptor maximum fill level (<= ring size)
386  * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
387  *	(<= @max_fill)
388  * @min_fill: RX descriptor minimum non-zero fill level.
389  *	This records the minimum fill level observed when a ring
390  *	refill was triggered.
391  * @recycle_count: RX buffer recycle counter.
392  * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
393  * @grant_work: workitem used to grant credits to the MAE if @grant_credits
394  * @xdp_rxq_info: XDP specific RX queue information.
395  * @xdp_rxq_info_valid: Is xdp_rxq_info valid data?.
396  */
397 struct efx_rx_queue {
398 	struct efx_nic *efx;
399 	int core_index;
400 	struct efx_rx_buffer *buffer;
401 	struct efx_special_buffer rxd;
402 	unsigned int ptr_mask;
403 	bool refill_enabled;
404 	bool flush_pending;
405 	bool grant_credits;
406 
407 	unsigned int added_count;
408 	unsigned int notified_count;
409 	unsigned int granted_count;
410 	unsigned int removed_count;
411 	unsigned int scatter_n;
412 	unsigned int scatter_len;
413 	struct page **page_ring;
414 	unsigned int page_add;
415 	unsigned int page_remove;
416 	unsigned int page_recycle_count;
417 	unsigned int page_recycle_failed;
418 	unsigned int page_recycle_full;
419 	unsigned int page_ptr_mask;
420 	unsigned int max_fill;
421 	unsigned int fast_fill_trigger;
422 	unsigned int min_fill;
423 	unsigned int min_overfill;
424 	unsigned int recycle_count;
425 	struct timer_list slow_fill;
426 	unsigned int slow_fill_count;
427 	struct work_struct grant_work;
428 	/* Statistics to supplement MAC stats */
429 	unsigned long rx_packets;
430 	struct xdp_rxq_info xdp_rxq_info;
431 	bool xdp_rxq_info_valid;
432 };
433 
434 enum efx_sync_events_state {
435 	SYNC_EVENTS_DISABLED = 0,
436 	SYNC_EVENTS_QUIESCENT,
437 	SYNC_EVENTS_REQUESTED,
438 	SYNC_EVENTS_VALID,
439 };
440 
441 /**
442  * struct efx_channel - An Efx channel
443  *
444  * A channel comprises an event queue, at least one TX queue, at least
445  * one RX queue, and an associated tasklet for processing the event
446  * queue.
447  *
448  * @efx: Associated Efx NIC
449  * @channel: Channel instance number
450  * @type: Channel type definition
451  * @eventq_init: Event queue initialised flag
452  * @enabled: Channel enabled indicator
453  * @irq: IRQ number (MSI and MSI-X only)
454  * @irq_moderation_us: IRQ moderation value (in microseconds)
455  * @napi_dev: Net device used with NAPI
456  * @napi_str: NAPI control structure
457  * @state: state for NAPI vs busy polling
458  * @state_lock: lock protecting @state
459  * @eventq: Event queue buffer
460  * @eventq_mask: Event queue pointer mask
461  * @eventq_read_ptr: Event queue read pointer
462  * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
463  * @irq_count: Number of IRQs since last adaptive moderation decision
464  * @irq_mod_score: IRQ moderation score
465  * @rfs_filter_count: number of accelerated RFS filters currently in place;
466  *	equals the count of @rps_flow_id slots filled
467  * @rfs_last_expiry: value of jiffies last time some accelerated RFS filters
468  *	were checked for expiry
469  * @rfs_expire_index: next accelerated RFS filter ID to check for expiry
470  * @n_rfs_succeeded: number of successful accelerated RFS filter insertions
471  * @n_rfs_failed: number of failed accelerated RFS filter insertions
472  * @filter_work: Work item for efx_filter_rfs_expire()
473  * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS,
474  *      indexed by filter ID
475  * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
476  * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
477  * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
478  * @n_rx_mcast_mismatch: Count of unmatched multicast frames
479  * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
480  * @n_rx_overlength: Count of RX_OVERLENGTH errors
481  * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
482  * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
483  *	lack of descriptors
484  * @n_rx_merge_events: Number of RX merged completion events
485  * @n_rx_merge_packets: Number of RX packets completed by merged events
486  * @n_rx_xdp_drops: Count of RX packets intentionally dropped due to XDP
487  * @n_rx_xdp_bad_drops: Count of RX packets dropped due to XDP errors
488  * @n_rx_xdp_tx: Count of RX packets retransmitted due to XDP
489  * @n_rx_xdp_redirect: Count of RX packets redirected to a different NIC by XDP
490  * @n_rx_mport_bad: Count of RX packets dropped because their ingress mport was
491  *	not recognised
492  * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by
493  *	__efx_rx_packet(), or zero if there is none
494  * @rx_pkt_index: Ring index of first buffer for next packet to be delivered
495  *	by __efx_rx_packet(), if @rx_pkt_n_frags != 0
496  * @rx_list: list of SKBs from current RX, awaiting processing
497  * @rx_queue: RX queue for this channel
498  * @tx_queue: TX queues for this channel
499  * @tx_queue_by_type: pointers into @tx_queue, or %NULL, indexed by txq type
500  * @sync_events_state: Current state of sync events on this channel
501  * @sync_timestamp_major: Major part of the last ptp sync event
502  * @sync_timestamp_minor: Minor part of the last ptp sync event
503  */
504 struct efx_channel {
505 	struct efx_nic *efx;
506 	int channel;
507 	const struct efx_channel_type *type;
508 	bool eventq_init;
509 	bool enabled;
510 	int irq;
511 	unsigned int irq_moderation_us;
512 	struct net_device *napi_dev;
513 	struct napi_struct napi_str;
514 #ifdef CONFIG_NET_RX_BUSY_POLL
515 	unsigned long busy_poll_state;
516 #endif
517 	struct efx_special_buffer eventq;
518 	unsigned int eventq_mask;
519 	unsigned int eventq_read_ptr;
520 	int event_test_cpu;
521 
522 	unsigned int irq_count;
523 	unsigned int irq_mod_score;
524 #ifdef CONFIG_RFS_ACCEL
525 	unsigned int rfs_filter_count;
526 	unsigned int rfs_last_expiry;
527 	unsigned int rfs_expire_index;
528 	unsigned int n_rfs_succeeded;
529 	unsigned int n_rfs_failed;
530 	struct delayed_work filter_work;
531 #define RPS_FLOW_ID_INVALID 0xFFFFFFFF
532 	u32 *rps_flow_id;
533 #endif
534 
535 	unsigned int n_rx_tobe_disc;
536 	unsigned int n_rx_ip_hdr_chksum_err;
537 	unsigned int n_rx_tcp_udp_chksum_err;
538 	unsigned int n_rx_outer_ip_hdr_chksum_err;
539 	unsigned int n_rx_outer_tcp_udp_chksum_err;
540 	unsigned int n_rx_inner_ip_hdr_chksum_err;
541 	unsigned int n_rx_inner_tcp_udp_chksum_err;
542 	unsigned int n_rx_eth_crc_err;
543 	unsigned int n_rx_mcast_mismatch;
544 	unsigned int n_rx_frm_trunc;
545 	unsigned int n_rx_overlength;
546 	unsigned int n_skbuff_leaks;
547 	unsigned int n_rx_nodesc_trunc;
548 	unsigned int n_rx_merge_events;
549 	unsigned int n_rx_merge_packets;
550 	unsigned int n_rx_xdp_drops;
551 	unsigned int n_rx_xdp_bad_drops;
552 	unsigned int n_rx_xdp_tx;
553 	unsigned int n_rx_xdp_redirect;
554 	unsigned int n_rx_mport_bad;
555 
556 	unsigned int rx_pkt_n_frags;
557 	unsigned int rx_pkt_index;
558 
559 	struct list_head *rx_list;
560 
561 	struct efx_rx_queue rx_queue;
562 	struct efx_tx_queue tx_queue[EFX_MAX_TXQ_PER_CHANNEL];
563 	struct efx_tx_queue *tx_queue_by_type[EFX_TXQ_TYPES];
564 
565 	enum efx_sync_events_state sync_events_state;
566 	u32 sync_timestamp_major;
567 	u32 sync_timestamp_minor;
568 };
569 
570 /**
571  * struct efx_msi_context - Context for each MSI
572  * @efx: The associated NIC
573  * @index: Index of the channel/IRQ
574  * @name: Name of the channel/IRQ
575  *
576  * Unlike &struct efx_channel, this is never reallocated and is always
577  * safe for the IRQ handler to access.
578  */
579 struct efx_msi_context {
580 	struct efx_nic *efx;
581 	unsigned int index;
582 	char name[IFNAMSIZ + 6];
583 };
584 
585 /**
586  * struct efx_channel_type - distinguishes traffic and extra channels
587  * @handle_no_channel: Handle failure to allocate an extra channel
588  * @pre_probe: Set up extra state prior to initialisation
589  * @start: called early in efx_start_channels()
590  * @stop: called early in efx_stop_channels()
591  * @post_remove: Tear down extra state after finalisation, if allocated.
592  *	May be called on channels that have not been probed.
593  * @get_name: Generate the channel's name (used for its IRQ handler)
594  * @copy: Copy the channel state prior to reallocation.  May be %NULL if
595  *	reallocation is not supported.
596  * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()
597  * @receive_raw: Handle an RX buffer ready to be passed to __efx_rx_packet()
598  * @want_txqs: Determine whether this channel should have TX queues
599  *	created.  If %NULL, TX queues are not created.
600  * @keep_eventq: Flag for whether event queue should be kept initialised
601  *	while the device is stopped
602  * @want_pio: Flag for whether PIO buffers should be linked to this
603  *	channel's TX queues.
604  */
605 struct efx_channel_type {
606 	void (*handle_no_channel)(struct efx_nic *);
607 	int (*pre_probe)(struct efx_channel *);
608 	int (*start)(struct efx_channel *);
609 	void (*stop)(struct efx_channel *);
610 	void (*post_remove)(struct efx_channel *);
611 	void (*get_name)(struct efx_channel *, char *buf, size_t len);
612 	struct efx_channel *(*copy)(const struct efx_channel *);
613 	bool (*receive_skb)(struct efx_channel *, struct sk_buff *);
614 	bool (*receive_raw)(struct efx_rx_queue *, u32);
615 	bool (*want_txqs)(struct efx_channel *);
616 	bool keep_eventq;
617 	bool want_pio;
618 };
619 
620 enum efx_led_mode {
621 	EFX_LED_OFF	= 0,
622 	EFX_LED_ON	= 1,
623 	EFX_LED_DEFAULT	= 2
624 };
625 
626 #define STRING_TABLE_LOOKUP(val, member) \
627 	((val) < member ## _max) ? member ## _names[val] : "(invalid)"
628 
629 extern const char *const efx_loopback_mode_names[];
630 extern const unsigned int efx_loopback_mode_max;
631 #define LOOPBACK_MODE(efx) \
632 	STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
633 
634 enum efx_int_mode {
635 	/* Be careful if altering to correct macro below */
636 	EFX_INT_MODE_MSIX = 0,
637 	EFX_INT_MODE_MSI = 1,
638 	EFX_INT_MODE_LEGACY = 2,
639 	EFX_INT_MODE_MAX	/* Insert any new items before this */
640 };
641 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
642 
643 enum nic_state {
644 	STATE_UNINIT = 0,	/* device being probed/removed */
645 	STATE_PROBED,		/* hardware probed */
646 	STATE_NET_DOWN,		/* netdev registered */
647 	STATE_NET_UP,		/* ready for traffic */
648 	STATE_DISABLED,		/* device disabled due to hardware errors */
649 
650 	STATE_RECOVERY = 0x100,/* recovering from PCI error */
651 	STATE_FROZEN = 0x200,	/* frozen by power management */
652 };
653 
654 static inline bool efx_net_active(enum nic_state state)
655 {
656 	return state == STATE_NET_DOWN || state == STATE_NET_UP;
657 }
658 
659 static inline bool efx_frozen(enum nic_state state)
660 {
661 	return state & STATE_FROZEN;
662 }
663 
664 static inline bool efx_recovering(enum nic_state state)
665 {
666 	return state & STATE_RECOVERY;
667 }
668 
669 static inline enum nic_state efx_freeze(enum nic_state state)
670 {
671 	WARN_ON(!efx_net_active(state));
672 	return state | STATE_FROZEN;
673 }
674 
675 static inline enum nic_state efx_thaw(enum nic_state state)
676 {
677 	WARN_ON(!efx_frozen(state));
678 	return state & ~STATE_FROZEN;
679 }
680 
681 static inline enum nic_state efx_recover(enum nic_state state)
682 {
683 	WARN_ON(!efx_net_active(state));
684 	return state | STATE_RECOVERY;
685 }
686 
687 static inline enum nic_state efx_recovered(enum nic_state state)
688 {
689 	WARN_ON(!efx_recovering(state));
690 	return state & ~STATE_RECOVERY;
691 }
692 
693 /* Forward declaration */
694 struct efx_nic;
695 
696 /* Pseudo bit-mask flow control field */
697 #define EFX_FC_RX	FLOW_CTRL_RX
698 #define EFX_FC_TX	FLOW_CTRL_TX
699 #define EFX_FC_AUTO	4
700 
701 /**
702  * struct efx_link_state - Current state of the link
703  * @up: Link is up
704  * @fd: Link is full-duplex
705  * @fc: Actual flow control flags
706  * @speed: Link speed (Mbps)
707  */
708 struct efx_link_state {
709 	bool up;
710 	bool fd;
711 	u8 fc;
712 	unsigned int speed;
713 };
714 
715 static inline bool efx_link_state_equal(const struct efx_link_state *left,
716 					const struct efx_link_state *right)
717 {
718 	return left->up == right->up && left->fd == right->fd &&
719 		left->fc == right->fc && left->speed == right->speed;
720 }
721 
722 /**
723  * enum efx_phy_mode - PHY operating mode flags
724  * @PHY_MODE_NORMAL: on and should pass traffic
725  * @PHY_MODE_TX_DISABLED: on with TX disabled
726  * @PHY_MODE_LOW_POWER: set to low power through MDIO
727  * @PHY_MODE_OFF: switched off through external control
728  * @PHY_MODE_SPECIAL: on but will not pass traffic
729  */
730 enum efx_phy_mode {
731 	PHY_MODE_NORMAL		= 0,
732 	PHY_MODE_TX_DISABLED	= 1,
733 	PHY_MODE_LOW_POWER	= 2,
734 	PHY_MODE_OFF		= 4,
735 	PHY_MODE_SPECIAL	= 8,
736 };
737 
738 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
739 {
740 	return !!(mode & ~PHY_MODE_TX_DISABLED);
741 }
742 
743 /**
744  * struct efx_hw_stat_desc - Description of a hardware statistic
745  * @name: Name of the statistic as visible through ethtool, or %NULL if
746  *	it should not be exposed
747  * @dma_width: Width in bits (0 for non-DMA statistics)
748  * @offset: Offset within stats (ignored for non-DMA statistics)
749  */
750 struct efx_hw_stat_desc {
751 	const char *name;
752 	u16 dma_width;
753 	u16 offset;
754 };
755 
756 /* Number of bits used in a multicast filter hash address */
757 #define EFX_MCAST_HASH_BITS 8
758 
759 /* Number of (single-bit) entries in a multicast filter hash */
760 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
761 
762 /* An Efx multicast filter hash */
763 union efx_multicast_hash {
764 	u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
765 	efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
766 };
767 
768 struct vfdi_status;
769 
770 /* The reserved RSS context value */
771 #define EFX_MCDI_RSS_CONTEXT_INVALID	0xffffffff
772 /**
773  * struct efx_rss_context - A user-defined RSS context for filtering
774  * @list: node of linked list on which this struct is stored
775  * @context_id: the RSS_CONTEXT_ID returned by MC firmware, or
776  *	%EFX_MCDI_RSS_CONTEXT_INVALID if this context is not present on the NIC.
777  *	For Siena, 0 if RSS is active, else %EFX_MCDI_RSS_CONTEXT_INVALID.
778  * @user_id: the rss_context ID exposed to userspace over ethtool.
779  * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled
780  * @rx_hash_key: Toeplitz hash key for this RSS context
781  * @indir_table: Indirection table for this RSS context
782  */
783 struct efx_rss_context {
784 	struct list_head list;
785 	u32 context_id;
786 	u32 user_id;
787 	bool rx_hash_udp_4tuple;
788 	u8 rx_hash_key[40];
789 	u32 rx_indir_table[128];
790 };
791 
792 #ifdef CONFIG_RFS_ACCEL
793 /* Order of these is important, since filter_id >= %EFX_ARFS_FILTER_ID_PENDING
794  * is used to test if filter does or will exist.
795  */
796 #define EFX_ARFS_FILTER_ID_PENDING	-1
797 #define EFX_ARFS_FILTER_ID_ERROR	-2
798 #define EFX_ARFS_FILTER_ID_REMOVING	-3
799 /**
800  * struct efx_arfs_rule - record of an ARFS filter and its IDs
801  * @node: linkage into hash table
802  * @spec: details of the filter (used as key for hash table).  Use efx->type to
803  *	determine which member to use.
804  * @rxq_index: channel to which the filter will steer traffic.
805  * @arfs_id: filter ID which was returned to ARFS
806  * @filter_id: index in software filter table.  May be
807  *	%EFX_ARFS_FILTER_ID_PENDING if filter was not inserted yet,
808  *	%EFX_ARFS_FILTER_ID_ERROR if filter insertion failed, or
809  *	%EFX_ARFS_FILTER_ID_REMOVING if expiry is currently removing the filter.
810  */
811 struct efx_arfs_rule {
812 	struct hlist_node node;
813 	struct efx_filter_spec spec;
814 	u16 rxq_index;
815 	u16 arfs_id;
816 	s32 filter_id;
817 };
818 
819 /* Size chosen so that the table is one page (4kB) */
820 #define EFX_ARFS_HASH_TABLE_SIZE	512
821 
822 /**
823  * struct efx_async_filter_insertion - Request to asynchronously insert a filter
824  * @net_dev: Reference to the netdevice
825  * @spec: The filter to insert
826  * @work: Workitem for this request
827  * @rxq_index: Identifies the channel for which this request was made
828  * @flow_id: Identifies the kernel-side flow for which this request was made
829  */
830 struct efx_async_filter_insertion {
831 	struct net_device *net_dev;
832 	struct efx_filter_spec spec;
833 	struct work_struct work;
834 	u16 rxq_index;
835 	u32 flow_id;
836 };
837 
838 /* Maximum number of ARFS workitems that may be in flight on an efx_nic */
839 #define EFX_RPS_MAX_IN_FLIGHT	8
840 #endif /* CONFIG_RFS_ACCEL */
841 
842 enum efx_xdp_tx_queues_mode {
843 	EFX_XDP_TX_QUEUES_DEDICATED,	/* one queue per core, locking not needed */
844 	EFX_XDP_TX_QUEUES_SHARED,	/* each queue used by more than 1 core */
845 	EFX_XDP_TX_QUEUES_BORROWED	/* queues borrowed from net stack */
846 };
847 
848 struct efx_mae;
849 
850 /**
851  * struct efx_nic - an Efx NIC
852  * @name: Device name (net device name or bus id before net device registered)
853  * @pci_dev: The PCI device
854  * @node: List node for maintaning primary/secondary function lists
855  * @primary: &struct efx_nic instance for the primary function of this
856  *	controller.  May be the same structure, and may be %NULL if no
857  *	primary function is bound.  Serialised by rtnl_lock.
858  * @secondary_list: List of &struct efx_nic instances for the secondary PCI
859  *	functions of the controller, if this is for the primary function.
860  *	Serialised by rtnl_lock.
861  * @type: Controller type attributes
862  * @legacy_irq: IRQ number
863  * @workqueue: Workqueue for port reconfigures and the HW monitor.
864  *	Work items do not hold and must not acquire RTNL.
865  * @workqueue_name: Name of workqueue
866  * @reset_work: Scheduled reset workitem
867  * @membase_phys: Memory BAR value as physical address
868  * @membase: Memory BAR value
869  * @vi_stride: step between per-VI registers / memory regions
870  * @interrupt_mode: Interrupt mode
871  * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
872  * @timer_max_ns: Interrupt timer maximum value, in nanoseconds
873  * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
874  * @irqs_hooked: Channel interrupts are hooked
875  * @irq_rx_mod_step_us: Step size for IRQ moderation for RX event queues
876  * @irq_rx_moderation_us: IRQ moderation time for RX event queues
877  * @msg_enable: Log message enable flags
878  * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.
879  * @reset_pending: Bitmask for pending resets
880  * @tx_queue: TX DMA queues
881  * @rx_queue: RX DMA queues
882  * @channel: Channels
883  * @msi_context: Context for each MSI
884  * @extra_channel_types: Types of extra (non-traffic) channels that
885  *	should be allocated for this NIC
886  * @mae: Details of the Match Action Engine
887  * @xdp_tx_queue_count: Number of entries in %xdp_tx_queues.
888  * @xdp_tx_queues: Array of pointers to tx queues used for XDP transmit.
889  * @xdp_txq_queues_mode: XDP TX queues sharing strategy.
890  * @rxq_entries: Size of receive queues requested by user.
891  * @txq_entries: Size of transmit queues requested by user.
892  * @txq_stop_thresh: TX queue fill level at or above which we stop it.
893  * @txq_wake_thresh: TX queue fill level at or below which we wake it.
894  * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
895  * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
896  * @sram_lim_qw: Qword address limit of SRAM
897  * @next_buffer_table: First available buffer table id
898  * @n_channels: Number of channels in use
899  * @n_rx_channels: Number of channels used for RX (= number of RX queues)
900  * @n_tx_channels: Number of channels used for TX
901  * @n_extra_tx_channels: Number of extra channels with TX queues
902  * @tx_queues_per_channel: number of TX queues probed on each channel
903  * @n_xdp_channels: Number of channels used for XDP TX
904  * @xdp_channel_offset: Offset of zeroth channel used for XPD TX.
905  * @xdp_tx_per_channel: Max number of TX queues on an XDP TX channel.
906  * @rx_ip_align: RX DMA address offset to have IP header aligned in
907  *	in accordance with NET_IP_ALIGN
908  * @rx_dma_len: Current maximum RX DMA length
909  * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
910  * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
911  *	for use in sk_buff::truesize
912  * @rx_prefix_size: Size of RX prefix before packet data
913  * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data
914  *	(valid only if @rx_prefix_size != 0; always negative)
915  * @rx_packet_len_offset: Offset of RX packet length from start of packet data
916  *	(valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative)
917  * @rx_packet_ts_offset: Offset of timestamp from start of packet data
918  *	(valid only if channel->sync_timestamps_enabled; always negative)
919  * @rx_scatter: Scatter mode enabled for receives
920  * @rss_context: Main RSS context.  Its @list member is the head of the list of
921  *	RSS contexts created by user requests
922  * @rss_lock: Protects custom RSS context software state in @rss_context.list
923  * @vport_id: The function's vport ID, only relevant for PFs
924  * @int_error_count: Number of internal errors seen recently
925  * @int_error_expire: Time at which error count will be expired
926  * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot
927  * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
928  *	acknowledge but do nothing else.
929  * @irq_status: Interrupt status buffer
930  * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
931  * @irq_level: IRQ level/index for IRQs not triggered by an event queue
932  * @selftest_work: Work item for asynchronous self-test
933  * @mtd_list: List of MTDs attached to the NIC
934  * @nic_data: Hardware dependent state
935  * @mcdi: Management-Controller-to-Driver Interface state
936  * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
937  *	efx_monitor() and efx_reconfigure_port()
938  * @port_enabled: Port enabled indicator.
939  *	Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
940  *	efx_mac_work() with kernel interfaces. Safe to read under any
941  *	one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
942  *	be held to modify it.
943  * @port_initialized: Port initialized?
944  * @net_dev: Operating system network device. Consider holding the rtnl lock
945  * @fixed_features: Features which cannot be turned off
946  * @num_mac_stats: Number of MAC stats reported by firmware (MAC_STATS_NUM_STATS
947  *	field of %MC_CMD_GET_CAPABILITIES_V4 response, or %MC_CMD_MAC_NSTATS)
948  * @stats_buffer: DMA buffer for statistics
949  * @phy_type: PHY type
950  * @phy_data: PHY private data (including PHY-specific stats)
951  * @mdio: PHY MDIO interface
952  * @mdio_bus: PHY MDIO bus ID (only used by Siena)
953  * @phy_mode: PHY operating mode. Serialised by @mac_lock.
954  * @link_advertising: Autonegotiation advertising flags
955  * @fec_config: Forward Error Correction configuration flags.  For bit positions
956  *	see &enum ethtool_fec_config_bits.
957  * @link_state: Current state of the link
958  * @n_link_state_changes: Number of times the link has changed state
959  * @unicast_filter: Flag for Falcon-arch simple unicast filter.
960  *	Protected by @mac_lock.
961  * @multicast_hash: Multicast hash table for Falcon-arch.
962  *	Protected by @mac_lock.
963  * @wanted_fc: Wanted flow control flags
964  * @fc_disable: When non-zero flow control is disabled. Typically used to
965  *	ensure that network back pressure doesn't delay dma queue flushes.
966  *	Serialised by the rtnl lock.
967  * @mac_work: Work item for changing MAC promiscuity and multicast hash
968  * @loopback_mode: Loopback status
969  * @loopback_modes: Supported loopback mode bitmask
970  * @loopback_selftest: Offline self-test private state
971  * @xdp_prog: Current XDP programme for this interface
972  * @filter_sem: Filter table rw_semaphore, protects existence of @filter_state
973  * @filter_state: Architecture-dependent filter table state
974  * @rps_mutex: Protects RPS state of all channels
975  * @rps_slot_map: bitmap of in-flight entries in @rps_slot
976  * @rps_slot: array of ARFS insertion requests for efx_filter_rfs_work()
977  * @rps_hash_lock: Protects ARFS filter mapping state (@rps_hash_table and
978  *	@rps_next_id).
979  * @rps_hash_table: Mapping between ARFS filters and their various IDs
980  * @rps_next_id: next arfs_id for an ARFS filter
981  * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
982  * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
983  *	Decremented when the efx_flush_rx_queue() is called.
984  * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
985  *	completed (either success or failure). Not used when MCDI is used to
986  *	flush receive queues.
987  * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
988  * @vf_count: Number of VFs intended to be enabled.
989  * @vf_init_count: Number of VFs that have been fully initialised.
990  * @vi_scale: log2 number of vnics per VF.
991  * @vf_reps_lock: Protects vf_reps list
992  * @vf_reps: local VF reps
993  * @ptp_data: PTP state data
994  * @ptp_warned: has this NIC seen and warned about unexpected PTP events?
995  * @vpd_sn: Serial number read from VPD
996  * @xdp_rxq_info_failed: Have any of the rx queues failed to initialise their
997  *      xdp_rxq_info structures?
998  * @netdev_notifier: Netdevice notifier.
999  * @tc: state for TC offload (EF100).
1000  * @devlink: reference to devlink structure owned by this device
1001  * @dl_port: devlink port associated with the PF
1002  * @mem_bar: The BAR that is mapped into membase.
1003  * @reg_base: Offset from the start of the bar to the function control window.
1004  * @monitor_work: Hardware monitor workitem
1005  * @biu_lock: BIU (bus interface unit) lock
1006  * @last_irq_cpu: Last CPU to handle a possible test interrupt.  This
1007  *	field is used by efx_test_interrupts() to verify that an
1008  *	interrupt has occurred.
1009  * @stats_lock: Statistics update lock. Must be held when calling
1010  *	efx_nic_type::{update,start,stop}_stats.
1011  * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb
1012  *
1013  * This is stored in the private area of the &struct net_device.
1014  */
1015 struct efx_nic {
1016 	/* The following fields should be written very rarely */
1017 
1018 	char name[IFNAMSIZ];
1019 	struct list_head node;
1020 	struct efx_nic *primary;
1021 	struct list_head secondary_list;
1022 	struct pci_dev *pci_dev;
1023 	unsigned int port_num;
1024 	const struct efx_nic_type *type;
1025 	int legacy_irq;
1026 	bool eeh_disabled_legacy_irq;
1027 	struct workqueue_struct *workqueue;
1028 	char workqueue_name[16];
1029 	struct work_struct reset_work;
1030 	resource_size_t membase_phys;
1031 	void __iomem *membase;
1032 
1033 	unsigned int vi_stride;
1034 
1035 	enum efx_int_mode interrupt_mode;
1036 	unsigned int timer_quantum_ns;
1037 	unsigned int timer_max_ns;
1038 	bool irq_rx_adaptive;
1039 	bool irqs_hooked;
1040 	unsigned int irq_mod_step_us;
1041 	unsigned int irq_rx_moderation_us;
1042 	u32 msg_enable;
1043 
1044 	enum nic_state state;
1045 	unsigned long reset_pending;
1046 
1047 	struct efx_channel *channel[EFX_MAX_CHANNELS];
1048 	struct efx_msi_context msi_context[EFX_MAX_CHANNELS];
1049 	const struct efx_channel_type *
1050 	extra_channel_type[EFX_MAX_EXTRA_CHANNELS];
1051 	struct efx_mae *mae;
1052 
1053 	unsigned int xdp_tx_queue_count;
1054 	struct efx_tx_queue **xdp_tx_queues;
1055 	enum efx_xdp_tx_queues_mode xdp_txq_queues_mode;
1056 
1057 	unsigned rxq_entries;
1058 	unsigned txq_entries;
1059 	unsigned int txq_stop_thresh;
1060 	unsigned int txq_wake_thresh;
1061 
1062 	unsigned tx_dc_base;
1063 	unsigned rx_dc_base;
1064 	unsigned sram_lim_qw;
1065 	unsigned next_buffer_table;
1066 
1067 	unsigned int max_channels;
1068 	unsigned int max_vis;
1069 	unsigned int max_tx_channels;
1070 	unsigned n_channels;
1071 	unsigned n_rx_channels;
1072 	unsigned rss_spread;
1073 	unsigned tx_channel_offset;
1074 	unsigned n_tx_channels;
1075 	unsigned n_extra_tx_channels;
1076 	unsigned int tx_queues_per_channel;
1077 	unsigned int n_xdp_channels;
1078 	unsigned int xdp_channel_offset;
1079 	unsigned int xdp_tx_per_channel;
1080 	unsigned int rx_ip_align;
1081 	unsigned int rx_dma_len;
1082 	unsigned int rx_buffer_order;
1083 	unsigned int rx_buffer_truesize;
1084 	unsigned int rx_page_buf_step;
1085 	unsigned int rx_bufs_per_page;
1086 	unsigned int rx_pages_per_batch;
1087 	unsigned int rx_prefix_size;
1088 	int rx_packet_hash_offset;
1089 	int rx_packet_len_offset;
1090 	int rx_packet_ts_offset;
1091 	bool rx_scatter;
1092 	struct efx_rss_context rss_context;
1093 	struct mutex rss_lock;
1094 	u32 vport_id;
1095 
1096 	unsigned int_error_count;
1097 	unsigned long int_error_expire;
1098 
1099 	bool must_realloc_vis;
1100 	bool irq_soft_enabled;
1101 	struct efx_buffer irq_status;
1102 	unsigned irq_zero_count;
1103 	unsigned irq_level;
1104 	struct delayed_work selftest_work;
1105 
1106 #ifdef CONFIG_SFC_MTD
1107 	struct list_head mtd_list;
1108 #endif
1109 
1110 	void *nic_data;
1111 	struct efx_mcdi_data *mcdi;
1112 
1113 	struct mutex mac_lock;
1114 	struct work_struct mac_work;
1115 	bool port_enabled;
1116 
1117 	bool mc_bist_for_other_fn;
1118 	bool port_initialized;
1119 	struct net_device *net_dev;
1120 
1121 	netdev_features_t fixed_features;
1122 
1123 	u16 num_mac_stats;
1124 	struct efx_buffer stats_buffer;
1125 	u64 rx_nodesc_drops_total;
1126 	u64 rx_nodesc_drops_while_down;
1127 	bool rx_nodesc_drops_prev_state;
1128 
1129 	unsigned int phy_type;
1130 	void *phy_data;
1131 	struct mdio_if_info mdio;
1132 	unsigned int mdio_bus;
1133 	enum efx_phy_mode phy_mode;
1134 
1135 	__ETHTOOL_DECLARE_LINK_MODE_MASK(link_advertising);
1136 	u32 fec_config;
1137 	struct efx_link_state link_state;
1138 	unsigned int n_link_state_changes;
1139 
1140 	bool unicast_filter;
1141 	union efx_multicast_hash multicast_hash;
1142 	u8 wanted_fc;
1143 	unsigned fc_disable;
1144 
1145 	atomic_t rx_reset;
1146 	enum efx_loopback_mode loopback_mode;
1147 	u64 loopback_modes;
1148 
1149 	void *loopback_selftest;
1150 	/* We access loopback_selftest immediately before running XDP,
1151 	 * so we want them next to each other.
1152 	 */
1153 	struct bpf_prog __rcu *xdp_prog;
1154 
1155 	struct rw_semaphore filter_sem;
1156 	void *filter_state;
1157 #ifdef CONFIG_RFS_ACCEL
1158 	struct mutex rps_mutex;
1159 	unsigned long rps_slot_map;
1160 	struct efx_async_filter_insertion rps_slot[EFX_RPS_MAX_IN_FLIGHT];
1161 	spinlock_t rps_hash_lock;
1162 	struct hlist_head *rps_hash_table;
1163 	u32 rps_next_id;
1164 #endif
1165 
1166 	atomic_t active_queues;
1167 	atomic_t rxq_flush_pending;
1168 	atomic_t rxq_flush_outstanding;
1169 	wait_queue_head_t flush_wq;
1170 
1171 #ifdef CONFIG_SFC_SRIOV
1172 	unsigned vf_count;
1173 	unsigned vf_init_count;
1174 	unsigned vi_scale;
1175 #endif
1176 	spinlock_t vf_reps_lock;
1177 	struct list_head vf_reps;
1178 
1179 	struct efx_ptp_data *ptp_data;
1180 	bool ptp_warned;
1181 
1182 	char *vpd_sn;
1183 	bool xdp_rxq_info_failed;
1184 
1185 	struct notifier_block netdev_notifier;
1186 	struct efx_tc_state *tc;
1187 
1188 	struct devlink *devlink;
1189 	struct devlink_port *dl_port;
1190 	unsigned int mem_bar;
1191 	u32 reg_base;
1192 
1193 	/* The following fields may be written more often */
1194 
1195 	struct delayed_work monitor_work ____cacheline_aligned_in_smp;
1196 	spinlock_t biu_lock;
1197 	int last_irq_cpu;
1198 	spinlock_t stats_lock;
1199 	atomic_t n_rx_noskb_drops;
1200 };
1201 
1202 /**
1203  * struct efx_probe_data - State after hardware probe
1204  * @pci_dev: The PCI device
1205  * @efx: Efx NIC details
1206  */
1207 struct efx_probe_data {
1208 	struct pci_dev *pci_dev;
1209 	struct efx_nic efx;
1210 };
1211 
1212 static inline struct efx_nic *efx_netdev_priv(struct net_device *dev)
1213 {
1214 	struct efx_probe_data **probe_ptr = netdev_priv(dev);
1215 	struct efx_probe_data *probe_data = *probe_ptr;
1216 
1217 	return &probe_data->efx;
1218 }
1219 
1220 static inline int efx_dev_registered(struct efx_nic *efx)
1221 {
1222 	return efx->net_dev->reg_state == NETREG_REGISTERED;
1223 }
1224 
1225 static inline unsigned int efx_port_num(struct efx_nic *efx)
1226 {
1227 	return efx->port_num;
1228 }
1229 
1230 struct efx_mtd_partition {
1231 	struct list_head node;
1232 	struct mtd_info mtd;
1233 	const char *dev_type_name;
1234 	const char *type_name;
1235 	char name[IFNAMSIZ + 20];
1236 };
1237 
1238 struct efx_udp_tunnel {
1239 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID	0xffff
1240 	u16 type; /* TUNNEL_ENCAP_UDP_PORT_ENTRY_foo, see mcdi_pcol.h */
1241 	__be16 port;
1242 };
1243 
1244 /**
1245  * struct efx_nic_type - Efx device type definition
1246  * @mem_bar: Get the memory BAR
1247  * @mem_map_size: Get memory BAR mapped size
1248  * @probe: Probe the controller
1249  * @remove: Free resources allocated by probe()
1250  * @init: Initialise the controller
1251  * @dimension_resources: Dimension controller resources (buffer table,
1252  *	and VIs once the available interrupt resources are clear)
1253  * @fini: Shut down the controller
1254  * @monitor: Periodic function for polling link state and hardware monitor
1255  * @map_reset_reason: Map ethtool reset reason to a reset method
1256  * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
1257  * @reset: Reset the controller hardware and possibly the PHY.  This will
1258  *	be called while the controller is uninitialised.
1259  * @probe_port: Probe the MAC and PHY
1260  * @remove_port: Free resources allocated by probe_port()
1261  * @handle_global_event: Handle a "global" event (may be %NULL)
1262  * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1263  * @prepare_flush: Prepare the hardware for flushing the DMA queues
1264  *	(for Falcon architecture)
1265  * @finish_flush: Clean up after flushing the DMA queues (for Falcon
1266  *	architecture)
1267  * @prepare_flr: Prepare for an FLR
1268  * @finish_flr: Clean up after an FLR
1269  * @describe_stats: Describe statistics for ethtool
1270  * @update_stats: Update statistics not provided by event handling.
1271  *	Either argument may be %NULL.
1272  * @update_stats_atomic: Update statistics while in atomic context, if that
1273  *	is more limiting than @update_stats.  Otherwise, leave %NULL and
1274  *	driver core will call @update_stats.
1275  * @start_stats: Start the regular fetching of statistics
1276  * @pull_stats: Pull stats from the NIC and wait until they arrive.
1277  * @stop_stats: Stop the regular fetching of statistics
1278  * @push_irq_moderation: Apply interrupt moderation value
1279  * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
1280  * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
1281  * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
1282  *	to the hardware.  Serialised by the mac_lock.
1283  * @check_mac_fault: Check MAC fault state. True if fault present.
1284  * @get_wol: Get WoL configuration from driver state
1285  * @set_wol: Push WoL configuration to the NIC
1286  * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
1287  * @get_fec_stats: Get standard FEC statistics.
1288  * @test_chip: Test registers.  May use efx_farch_test_registers(), and is
1289  *	expected to reset the NIC.
1290  * @test_nvram: Test validity of NVRAM contents
1291  * @mcdi_request: Send an MCDI request with the given header and SDU.
1292  *	The SDU length may be any value from 0 up to the protocol-
1293  *	defined maximum, but its buffer will be padded to a multiple
1294  *	of 4 bytes.
1295  * @mcdi_poll_response: Test whether an MCDI response is available.
1296  * @mcdi_read_response: Read the MCDI response PDU.  The offset will
1297  *	be a multiple of 4.  The length may not be, but the buffer
1298  *	will be padded so it is safe to round up.
1299  * @mcdi_poll_reboot: Test whether the MCDI has rebooted.  If so,
1300  *	return an appropriate error code for aborting any current
1301  *	request; otherwise return 0.
1302  * @irq_enable_master: Enable IRQs on the NIC.  Each event queue must
1303  *	be separately enabled after this.
1304  * @irq_test_generate: Generate a test IRQ
1305  * @irq_disable_non_ev: Disable non-event IRQs on the NIC.  Each event
1306  *	queue must be separately disabled before this.
1307  * @irq_handle_msi: Handle MSI for a channel.  The @dev_id argument is
1308  *	a pointer to the &struct efx_msi_context for the channel.
1309  * @irq_handle_legacy: Handle legacy interrupt.  The @dev_id argument
1310  *	is a pointer to the &struct efx_nic.
1311  * @tx_probe: Allocate resources for TX queue (and select TXQ type)
1312  * @tx_init: Initialise TX queue on the NIC
1313  * @tx_remove: Free resources for TX queue
1314  * @tx_write: Write TX descriptors and doorbell
1315  * @tx_enqueue: Add an SKB to TX queue
1316  * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC
1317  * @rx_pull_rss_config: Read RSS hash key and indirection table back from the NIC
1318  * @rx_push_rss_context_config: Write RSS hash key and indirection table for
1319  *	user RSS context to the NIC
1320  * @rx_pull_rss_context_config: Read RSS hash key and indirection table for user
1321  *	RSS context back from the NIC
1322  * @rx_probe: Allocate resources for RX queue
1323  * @rx_init: Initialise RX queue on the NIC
1324  * @rx_remove: Free resources for RX queue
1325  * @rx_write: Write RX descriptors and doorbell
1326  * @rx_defer_refill: Generate a refill reminder event
1327  * @rx_packet: Receive the queued RX buffer on a channel
1328  * @rx_buf_hash_valid: Determine whether the RX prefix contains a valid hash
1329  * @ev_probe: Allocate resources for event queue
1330  * @ev_init: Initialise event queue on the NIC
1331  * @ev_fini: Deinitialise event queue on the NIC
1332  * @ev_remove: Free resources for event queue
1333  * @ev_process: Process events for a queue, up to the given NAPI quota
1334  * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
1335  * @ev_test_generate: Generate a test event
1336  * @filter_table_probe: Probe filter capabilities and set up filter software state
1337  * @filter_table_restore: Restore filters removed from hardware
1338  * @filter_table_remove: Remove filters from hardware and tear down software state
1339  * @filter_update_rx_scatter: Update filters after change to rx scatter setting
1340  * @filter_insert: add or replace a filter
1341  * @filter_remove_safe: remove a filter by ID, carefully
1342  * @filter_get_safe: retrieve a filter by ID, carefully
1343  * @filter_clear_rx: Remove all RX filters whose priority is less than or
1344  *	equal to the given priority and is not %EFX_FILTER_PRI_AUTO
1345  * @filter_count_rx_used: Get the number of filters in use at a given priority
1346  * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1
1347  * @filter_get_rx_ids: Get list of RX filters at a given priority
1348  * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS.
1349  *	This must check whether the specified table entry is used by RFS
1350  *	and that rps_may_expire_flow() returns true for it.
1351  * @mtd_probe: Probe and add MTD partitions associated with this net device,
1352  *	 using efx_mtd_add()
1353  * @mtd_rename: Set an MTD partition name using the net device name
1354  * @mtd_read: Read from an MTD partition
1355  * @mtd_erase: Erase part of an MTD partition
1356  * @mtd_write: Write to an MTD partition
1357  * @mtd_sync: Wait for write-back to complete on MTD partition.  This
1358  *	also notifies the driver that a writer has finished using this
1359  *	partition.
1360  * @ptp_write_host_time: Send host time to MC as part of sync protocol
1361  * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX
1362  *	timestamping, possibly only temporarily for the purposes of a reset.
1363  * @ptp_set_ts_config: Set hardware timestamp configuration.  The flags
1364  *	and tx_type will already have been validated but this operation
1365  *	must validate and update rx_filter.
1366  * @get_phys_port_id: Get the underlying physical port id.
1367  * @set_mac_address: Set the MAC address of the device
1368  * @tso_versions: Returns mask of firmware-assisted TSO versions supported.
1369  *	If %NULL, then device does not support any TSO version.
1370  * @udp_tnl_push_ports: Push the list of UDP tunnel ports to the NIC if required.
1371  * @udp_tnl_has_port: Check if a port has been added as UDP tunnel
1372  * @print_additional_fwver: Dump NIC-specific additional FW version info
1373  * @sensor_event: Handle a sensor event from MCDI
1374  * @rx_recycle_ring_size: Size of the RX recycle ring
1375  * @revision: Hardware architecture revision
1376  * @txd_ptr_tbl_base: TX descriptor ring base address
1377  * @rxd_ptr_tbl_base: RX descriptor ring base address
1378  * @buf_tbl_base: Buffer table base address
1379  * @evq_ptr_tbl_base: Event queue pointer table base address
1380  * @evq_rptr_tbl_base: Event queue read-pointer table base address
1381  * @max_dma_mask: Maximum possible DMA mask
1382  * @rx_prefix_size: Size of RX prefix before packet data
1383  * @rx_hash_offset: Offset of RX flow hash within prefix
1384  * @rx_ts_offset: Offset of timestamp within prefix
1385  * @rx_buffer_padding: Size of padding at end of RX packet
1386  * @can_rx_scatter: NIC is able to scatter packets to multiple buffers
1387  * @always_rx_scatter: NIC will always scatter packets to multiple buffers
1388  * @option_descriptors: NIC supports TX option descriptors
1389  * @min_interrupt_mode: Lowest capability interrupt mode supported
1390  *	from &enum efx_int_mode.
1391  * @timer_period_max: Maximum period of interrupt timer (in ticks)
1392  * @offload_features: net_device feature flags for protocol offload
1393  *	features implemented in hardware
1394  * @mcdi_max_ver: Maximum MCDI version supported
1395  * @hwtstamp_filters: Mask of hardware timestamp filter types supported
1396  */
1397 struct efx_nic_type {
1398 	bool is_vf;
1399 	unsigned int (*mem_bar)(struct efx_nic *efx);
1400 	unsigned int (*mem_map_size)(struct efx_nic *efx);
1401 	int (*probe)(struct efx_nic *efx);
1402 	void (*remove)(struct efx_nic *efx);
1403 	int (*init)(struct efx_nic *efx);
1404 	int (*dimension_resources)(struct efx_nic *efx);
1405 	void (*fini)(struct efx_nic *efx);
1406 	void (*monitor)(struct efx_nic *efx);
1407 	enum reset_type (*map_reset_reason)(enum reset_type reason);
1408 	int (*map_reset_flags)(u32 *flags);
1409 	int (*reset)(struct efx_nic *efx, enum reset_type method);
1410 	int (*probe_port)(struct efx_nic *efx);
1411 	void (*remove_port)(struct efx_nic *efx);
1412 	bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
1413 	int (*fini_dmaq)(struct efx_nic *efx);
1414 	void (*prepare_flush)(struct efx_nic *efx);
1415 	void (*finish_flush)(struct efx_nic *efx);
1416 	void (*prepare_flr)(struct efx_nic *efx);
1417 	void (*finish_flr)(struct efx_nic *efx);
1418 	size_t (*describe_stats)(struct efx_nic *efx, u8 *names);
1419 	size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats,
1420 			       struct rtnl_link_stats64 *core_stats);
1421 	size_t (*update_stats_atomic)(struct efx_nic *efx, u64 *full_stats,
1422 				      struct rtnl_link_stats64 *core_stats);
1423 	void (*start_stats)(struct efx_nic *efx);
1424 	void (*pull_stats)(struct efx_nic *efx);
1425 	void (*stop_stats)(struct efx_nic *efx);
1426 	void (*push_irq_moderation)(struct efx_channel *channel);
1427 	int (*reconfigure_port)(struct efx_nic *efx);
1428 	void (*prepare_enable_fc_tx)(struct efx_nic *efx);
1429 	int (*reconfigure_mac)(struct efx_nic *efx, bool mtu_only);
1430 	bool (*check_mac_fault)(struct efx_nic *efx);
1431 	void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
1432 	int (*set_wol)(struct efx_nic *efx, u32 type);
1433 	void (*resume_wol)(struct efx_nic *efx);
1434 	void (*get_fec_stats)(struct efx_nic *efx,
1435 			      struct ethtool_fec_stats *fec_stats);
1436 	unsigned int (*check_caps)(const struct efx_nic *efx,
1437 				   u8 flag,
1438 				   u32 offset);
1439 	int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests);
1440 	int (*test_nvram)(struct efx_nic *efx);
1441 	void (*mcdi_request)(struct efx_nic *efx,
1442 			     const efx_dword_t *hdr, size_t hdr_len,
1443 			     const efx_dword_t *sdu, size_t sdu_len);
1444 	bool (*mcdi_poll_response)(struct efx_nic *efx);
1445 	void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu,
1446 				   size_t pdu_offset, size_t pdu_len);
1447 	int (*mcdi_poll_reboot)(struct efx_nic *efx);
1448 	void (*mcdi_reboot_detected)(struct efx_nic *efx);
1449 	void (*irq_enable_master)(struct efx_nic *efx);
1450 	int (*irq_test_generate)(struct efx_nic *efx);
1451 	void (*irq_disable_non_ev)(struct efx_nic *efx);
1452 	irqreturn_t (*irq_handle_msi)(int irq, void *dev_id);
1453 	irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id);
1454 	int (*tx_probe)(struct efx_tx_queue *tx_queue);
1455 	void (*tx_init)(struct efx_tx_queue *tx_queue);
1456 	void (*tx_remove)(struct efx_tx_queue *tx_queue);
1457 	void (*tx_write)(struct efx_tx_queue *tx_queue);
1458 	netdev_tx_t (*tx_enqueue)(struct efx_tx_queue *tx_queue, struct sk_buff *skb);
1459 	unsigned int (*tx_limit_len)(struct efx_tx_queue *tx_queue,
1460 				     dma_addr_t dma_addr, unsigned int len);
1461 	int (*rx_push_rss_config)(struct efx_nic *efx, bool user,
1462 				  const u32 *rx_indir_table, const u8 *key);
1463 	int (*rx_pull_rss_config)(struct efx_nic *efx);
1464 	int (*rx_push_rss_context_config)(struct efx_nic *efx,
1465 					  struct efx_rss_context *ctx,
1466 					  const u32 *rx_indir_table,
1467 					  const u8 *key);
1468 	int (*rx_pull_rss_context_config)(struct efx_nic *efx,
1469 					  struct efx_rss_context *ctx);
1470 	void (*rx_restore_rss_contexts)(struct efx_nic *efx);
1471 	int (*rx_probe)(struct efx_rx_queue *rx_queue);
1472 	void (*rx_init)(struct efx_rx_queue *rx_queue);
1473 	void (*rx_remove)(struct efx_rx_queue *rx_queue);
1474 	void (*rx_write)(struct efx_rx_queue *rx_queue);
1475 	void (*rx_defer_refill)(struct efx_rx_queue *rx_queue);
1476 	void (*rx_packet)(struct efx_channel *channel);
1477 	bool (*rx_buf_hash_valid)(const u8 *prefix);
1478 	int (*ev_probe)(struct efx_channel *channel);
1479 	int (*ev_init)(struct efx_channel *channel);
1480 	void (*ev_fini)(struct efx_channel *channel);
1481 	void (*ev_remove)(struct efx_channel *channel);
1482 	int (*ev_process)(struct efx_channel *channel, int quota);
1483 	void (*ev_read_ack)(struct efx_channel *channel);
1484 	void (*ev_test_generate)(struct efx_channel *channel);
1485 	int (*filter_table_probe)(struct efx_nic *efx);
1486 	void (*filter_table_restore)(struct efx_nic *efx);
1487 	void (*filter_table_remove)(struct efx_nic *efx);
1488 	void (*filter_update_rx_scatter)(struct efx_nic *efx);
1489 	s32 (*filter_insert)(struct efx_nic *efx,
1490 			     struct efx_filter_spec *spec, bool replace);
1491 	int (*filter_remove_safe)(struct efx_nic *efx,
1492 				  enum efx_filter_priority priority,
1493 				  u32 filter_id);
1494 	int (*filter_get_safe)(struct efx_nic *efx,
1495 			       enum efx_filter_priority priority,
1496 			       u32 filter_id, struct efx_filter_spec *);
1497 	int (*filter_clear_rx)(struct efx_nic *efx,
1498 			       enum efx_filter_priority priority);
1499 	u32 (*filter_count_rx_used)(struct efx_nic *efx,
1500 				    enum efx_filter_priority priority);
1501 	u32 (*filter_get_rx_id_limit)(struct efx_nic *efx);
1502 	s32 (*filter_get_rx_ids)(struct efx_nic *efx,
1503 				 enum efx_filter_priority priority,
1504 				 u32 *buf, u32 size);
1505 #ifdef CONFIG_RFS_ACCEL
1506 	bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id,
1507 				      unsigned int index);
1508 #endif
1509 #ifdef CONFIG_SFC_MTD
1510 	int (*mtd_probe)(struct efx_nic *efx);
1511 	void (*mtd_rename)(struct efx_mtd_partition *part);
1512 	int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len,
1513 			size_t *retlen, u8 *buffer);
1514 	int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len);
1515 	int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len,
1516 			 size_t *retlen, const u8 *buffer);
1517 	int (*mtd_sync)(struct mtd_info *mtd);
1518 #endif
1519 	void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time);
1520 	int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp);
1521 	int (*ptp_set_ts_config)(struct efx_nic *efx,
1522 				 struct hwtstamp_config *init);
1523 	int (*sriov_configure)(struct efx_nic *efx, int num_vfs);
1524 	int (*vlan_rx_add_vid)(struct efx_nic *efx, __be16 proto, u16 vid);
1525 	int (*vlan_rx_kill_vid)(struct efx_nic *efx, __be16 proto, u16 vid);
1526 	int (*get_phys_port_id)(struct efx_nic *efx,
1527 				struct netdev_phys_item_id *ppid);
1528 	int (*sriov_init)(struct efx_nic *efx);
1529 	void (*sriov_fini)(struct efx_nic *efx);
1530 	bool (*sriov_wanted)(struct efx_nic *efx);
1531 	void (*sriov_reset)(struct efx_nic *efx);
1532 	void (*sriov_flr)(struct efx_nic *efx, unsigned vf_i);
1533 	int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, const u8 *mac);
1534 	int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan,
1535 				 u8 qos);
1536 	int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i,
1537 				     bool spoofchk);
1538 	int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i,
1539 				   struct ifla_vf_info *ivi);
1540 	int (*sriov_set_vf_link_state)(struct efx_nic *efx, int vf_i,
1541 				       int link_state);
1542 	int (*vswitching_probe)(struct efx_nic *efx);
1543 	int (*vswitching_restore)(struct efx_nic *efx);
1544 	void (*vswitching_remove)(struct efx_nic *efx);
1545 	int (*get_mac_address)(struct efx_nic *efx, unsigned char *perm_addr);
1546 	int (*set_mac_address)(struct efx_nic *efx);
1547 	u32 (*tso_versions)(struct efx_nic *efx);
1548 	int (*udp_tnl_push_ports)(struct efx_nic *efx);
1549 	bool (*udp_tnl_has_port)(struct efx_nic *efx, __be16 port);
1550 	size_t (*print_additional_fwver)(struct efx_nic *efx, char *buf,
1551 					 size_t len);
1552 	void (*sensor_event)(struct efx_nic *efx, efx_qword_t *ev);
1553 	unsigned int (*rx_recycle_ring_size)(const struct efx_nic *efx);
1554 
1555 	int revision;
1556 	unsigned int txd_ptr_tbl_base;
1557 	unsigned int rxd_ptr_tbl_base;
1558 	unsigned int buf_tbl_base;
1559 	unsigned int evq_ptr_tbl_base;
1560 	unsigned int evq_rptr_tbl_base;
1561 	u64 max_dma_mask;
1562 	unsigned int rx_prefix_size;
1563 	unsigned int rx_hash_offset;
1564 	unsigned int rx_ts_offset;
1565 	unsigned int rx_buffer_padding;
1566 	bool can_rx_scatter;
1567 	bool always_rx_scatter;
1568 	bool option_descriptors;
1569 	unsigned int min_interrupt_mode;
1570 	unsigned int timer_period_max;
1571 	netdev_features_t offload_features;
1572 	int mcdi_max_ver;
1573 	unsigned int max_rx_ip_filters;
1574 	u32 hwtstamp_filters;
1575 	unsigned int rx_hash_key_size;
1576 };
1577 
1578 /**************************************************************************
1579  *
1580  * Prototypes and inline functions
1581  *
1582  *************************************************************************/
1583 
1584 static inline struct efx_channel *
1585 efx_get_channel(struct efx_nic *efx, unsigned index)
1586 {
1587 	EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_channels);
1588 	return efx->channel[index];
1589 }
1590 
1591 /* Iterate over all used channels */
1592 #define efx_for_each_channel(_channel, _efx)				\
1593 	for (_channel = (_efx)->channel[0];				\
1594 	     _channel;							\
1595 	     _channel = (_channel->channel + 1 < (_efx)->n_channels) ?	\
1596 		     (_efx)->channel[_channel->channel + 1] : NULL)
1597 
1598 /* Iterate over all used channels in reverse */
1599 #define efx_for_each_channel_rev(_channel, _efx)			\
1600 	for (_channel = (_efx)->channel[(_efx)->n_channels - 1];	\
1601 	     _channel;							\
1602 	     _channel = _channel->channel ?				\
1603 		     (_efx)->channel[_channel->channel - 1] : NULL)
1604 
1605 static inline struct efx_channel *
1606 efx_get_tx_channel(struct efx_nic *efx, unsigned int index)
1607 {
1608 	EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_tx_channels);
1609 	return efx->channel[efx->tx_channel_offset + index];
1610 }
1611 
1612 static inline struct efx_channel *
1613 efx_get_xdp_channel(struct efx_nic *efx, unsigned int index)
1614 {
1615 	EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_xdp_channels);
1616 	return efx->channel[efx->xdp_channel_offset + index];
1617 }
1618 
1619 static inline bool efx_channel_is_xdp_tx(struct efx_channel *channel)
1620 {
1621 	return channel->channel - channel->efx->xdp_channel_offset <
1622 	       channel->efx->n_xdp_channels;
1623 }
1624 
1625 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel)
1626 {
1627 	return channel && channel->channel >= channel->efx->tx_channel_offset;
1628 }
1629 
1630 static inline unsigned int efx_channel_num_tx_queues(struct efx_channel *channel)
1631 {
1632 	if (efx_channel_is_xdp_tx(channel))
1633 		return channel->efx->xdp_tx_per_channel;
1634 	return channel->efx->tx_queues_per_channel;
1635 }
1636 
1637 static inline struct efx_tx_queue *
1638 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned int type)
1639 {
1640 	EFX_WARN_ON_ONCE_PARANOID(type >= EFX_TXQ_TYPES);
1641 	return channel->tx_queue_by_type[type];
1642 }
1643 
1644 static inline struct efx_tx_queue *
1645 efx_get_tx_queue(struct efx_nic *efx, unsigned int index, unsigned int type)
1646 {
1647 	struct efx_channel *channel = efx_get_tx_channel(efx, index);
1648 
1649 	return efx_channel_get_tx_queue(channel, type);
1650 }
1651 
1652 /* Iterate over all TX queues belonging to a channel */
1653 #define efx_for_each_channel_tx_queue(_tx_queue, _channel)		\
1654 	if (!efx_channel_has_tx_queues(_channel))			\
1655 		;							\
1656 	else								\
1657 		for (_tx_queue = (_channel)->tx_queue;			\
1658 		     _tx_queue < (_channel)->tx_queue +			\
1659 				 efx_channel_num_tx_queues(_channel);		\
1660 		     _tx_queue++)
1661 
1662 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel)
1663 {
1664 	return channel->rx_queue.core_index >= 0;
1665 }
1666 
1667 static inline struct efx_rx_queue *
1668 efx_channel_get_rx_queue(struct efx_channel *channel)
1669 {
1670 	EFX_WARN_ON_ONCE_PARANOID(!efx_channel_has_rx_queue(channel));
1671 	return &channel->rx_queue;
1672 }
1673 
1674 /* Iterate over all RX queues belonging to a channel */
1675 #define efx_for_each_channel_rx_queue(_rx_queue, _channel)		\
1676 	if (!efx_channel_has_rx_queue(_channel))			\
1677 		;							\
1678 	else								\
1679 		for (_rx_queue = &(_channel)->rx_queue;			\
1680 		     _rx_queue;						\
1681 		     _rx_queue = NULL)
1682 
1683 static inline struct efx_channel *
1684 efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
1685 {
1686 	return container_of(rx_queue, struct efx_channel, rx_queue);
1687 }
1688 
1689 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
1690 {
1691 	return efx_rx_queue_channel(rx_queue)->channel;
1692 }
1693 
1694 /* Returns a pointer to the specified receive buffer in the RX
1695  * descriptor queue.
1696  */
1697 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
1698 						  unsigned int index)
1699 {
1700 	return &rx_queue->buffer[index];
1701 }
1702 
1703 static inline struct efx_rx_buffer *
1704 efx_rx_buf_next(struct efx_rx_queue *rx_queue, struct efx_rx_buffer *rx_buf)
1705 {
1706 	if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask)))
1707 		return efx_rx_buffer(rx_queue, 0);
1708 	else
1709 		return rx_buf + 1;
1710 }
1711 
1712 /**
1713  * EFX_MAX_FRAME_LEN - calculate maximum frame length
1714  *
1715  * This calculates the maximum frame length that will be used for a
1716  * given MTU.  The frame length will be equal to the MTU plus a
1717  * constant amount of header space and padding.  This is the quantity
1718  * that the net driver will program into the MAC as the maximum frame
1719  * length.
1720  *
1721  * The 10G MAC requires 8-byte alignment on the frame
1722  * length, so we round up to the nearest 8.
1723  *
1724  * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1725  * XGMII cycle).  If the frame length reaches the maximum value in the
1726  * same cycle, the XMAC can miss the IPG altogether.  We work around
1727  * this by adding a further 16 bytes.
1728  */
1729 #define EFX_FRAME_PAD	16
1730 #define EFX_MAX_FRAME_LEN(mtu) \
1731 	(ALIGN(((mtu) + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN + EFX_FRAME_PAD), 8))
1732 
1733 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb)
1734 {
1735 	return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
1736 }
1737 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb)
1738 {
1739 	skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1740 }
1741 
1742 /* Get the max fill level of the TX queues on this channel */
1743 static inline unsigned int
1744 efx_channel_tx_fill_level(struct efx_channel *channel)
1745 {
1746 	struct efx_tx_queue *tx_queue;
1747 	unsigned int fill_level = 0;
1748 
1749 	efx_for_each_channel_tx_queue(tx_queue, channel)
1750 		fill_level = max(fill_level,
1751 				 tx_queue->insert_count - tx_queue->read_count);
1752 
1753 	return fill_level;
1754 }
1755 
1756 /* Conservative approximation of efx_channel_tx_fill_level using cached value */
1757 static inline unsigned int
1758 efx_channel_tx_old_fill_level(struct efx_channel *channel)
1759 {
1760 	struct efx_tx_queue *tx_queue;
1761 	unsigned int fill_level = 0;
1762 
1763 	efx_for_each_channel_tx_queue(tx_queue, channel)
1764 		fill_level = max(fill_level,
1765 				 tx_queue->insert_count - tx_queue->old_read_count);
1766 
1767 	return fill_level;
1768 }
1769 
1770 /* Get all supported features.
1771  * If a feature is not fixed, it is present in hw_features.
1772  * If a feature is fixed, it does not present in hw_features, but
1773  * always in features.
1774  */
1775 static inline netdev_features_t efx_supported_features(const struct efx_nic *efx)
1776 {
1777 	const struct net_device *net_dev = efx->net_dev;
1778 
1779 	return net_dev->features | net_dev->hw_features;
1780 }
1781 
1782 /* Get the current TX queue insert index. */
1783 static inline unsigned int
1784 efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue)
1785 {
1786 	return tx_queue->insert_count & tx_queue->ptr_mask;
1787 }
1788 
1789 /* Get a TX buffer. */
1790 static inline struct efx_tx_buffer *
1791 __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
1792 {
1793 	return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];
1794 }
1795 
1796 /* Get a TX buffer, checking it's not currently in use. */
1797 static inline struct efx_tx_buffer *
1798 efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
1799 {
1800 	struct efx_tx_buffer *buffer =
1801 		__efx_tx_queue_get_insert_buffer(tx_queue);
1802 
1803 	EFX_WARN_ON_ONCE_PARANOID(buffer->len);
1804 	EFX_WARN_ON_ONCE_PARANOID(buffer->flags);
1805 	EFX_WARN_ON_ONCE_PARANOID(buffer->unmap_len);
1806 
1807 	return buffer;
1808 }
1809 
1810 #endif /* EFX_NET_DRIVER_H */
1811