1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 /* Common definitions for all Efx net driver code */ 12 13 #ifndef EFX_NET_DRIVER_H 14 #define EFX_NET_DRIVER_H 15 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/ethtool.h> 19 #include <linux/if_vlan.h> 20 #include <linux/timer.h> 21 #include <linux/mdio.h> 22 #include <linux/list.h> 23 #include <linux/pci.h> 24 #include <linux/device.h> 25 #include <linux/highmem.h> 26 #include <linux/workqueue.h> 27 #include <linux/mutex.h> 28 #include <linux/rwsem.h> 29 #include <linux/vmalloc.h> 30 #include <linux/i2c.h> 31 #include <linux/mtd/mtd.h> 32 #include <net/busy_poll.h> 33 34 #include "enum.h" 35 #include "bitfield.h" 36 #include "filter.h" 37 38 /************************************************************************** 39 * 40 * Build definitions 41 * 42 **************************************************************************/ 43 44 #define EFX_DRIVER_VERSION "4.1" 45 46 #ifdef DEBUG 47 #define EFX_WARN_ON_ONCE_PARANOID(x) WARN_ON_ONCE(x) 48 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) 49 #else 50 #define EFX_WARN_ON_ONCE_PARANOID(x) do {} while (0) 51 #define EFX_WARN_ON_PARANOID(x) do {} while (0) 52 #endif 53 54 /************************************************************************** 55 * 56 * Efx data structures 57 * 58 **************************************************************************/ 59 60 #define EFX_MAX_CHANNELS 32U 61 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS 62 #define EFX_EXTRA_CHANNEL_IOV 0 63 #define EFX_EXTRA_CHANNEL_PTP 1 64 #define EFX_MAX_EXTRA_CHANNELS 2U 65 66 /* Checksum generation is a per-queue option in hardware, so each 67 * queue visible to the networking core is backed by two hardware TX 68 * queues. */ 69 #define EFX_MAX_TX_TC 2 70 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS) 71 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */ 72 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */ 73 #define EFX_TXQ_TYPES 4 74 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS) 75 76 /* Maximum possible MTU the driver supports */ 77 #define EFX_MAX_MTU (9 * 1024) 78 79 /* Minimum MTU, from RFC791 (IP) */ 80 #define EFX_MIN_MTU 68 81 82 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page, 83 * and should be a multiple of the cache line size. 84 */ 85 #define EFX_RX_USR_BUF_SIZE (2048 - 256) 86 87 /* If possible, we should ensure cache line alignment at start and end 88 * of every buffer. Otherwise, we just need to ensure 4-byte 89 * alignment of the network header. 90 */ 91 #if NET_IP_ALIGN == 0 92 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES 93 #else 94 #define EFX_RX_BUF_ALIGNMENT 4 95 #endif 96 97 /* Forward declare Precision Time Protocol (PTP) support structure. */ 98 struct efx_ptp_data; 99 struct hwtstamp_config; 100 101 struct efx_self_tests; 102 103 /** 104 * struct efx_buffer - A general-purpose DMA buffer 105 * @addr: host base address of the buffer 106 * @dma_addr: DMA base address of the buffer 107 * @len: Buffer length, in bytes 108 * 109 * The NIC uses these buffers for its interrupt status registers and 110 * MAC stats dumps. 111 */ 112 struct efx_buffer { 113 void *addr; 114 dma_addr_t dma_addr; 115 unsigned int len; 116 }; 117 118 /** 119 * struct efx_special_buffer - DMA buffer entered into buffer table 120 * @buf: Standard &struct efx_buffer 121 * @index: Buffer index within controller;s buffer table 122 * @entries: Number of buffer table entries 123 * 124 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE. 125 * Event and descriptor rings are addressed via one or more buffer 126 * table entries (and so can be physically non-contiguous, although we 127 * currently do not take advantage of that). On Falcon and Siena we 128 * have to take care of allocating and initialising the entries 129 * ourselves. On later hardware this is managed by the firmware and 130 * @index and @entries are left as 0. 131 */ 132 struct efx_special_buffer { 133 struct efx_buffer buf; 134 unsigned int index; 135 unsigned int entries; 136 }; 137 138 /** 139 * struct efx_tx_buffer - buffer state for a TX descriptor 140 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be 141 * freed when descriptor completes 142 * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor. 143 * @dma_addr: DMA address of the fragment. 144 * @flags: Flags for allocation and DMA mapping type 145 * @len: Length of this fragment. 146 * This field is zero when the queue slot is empty. 147 * @unmap_len: Length of this fragment to unmap 148 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping. 149 * Only valid if @unmap_len != 0. 150 */ 151 struct efx_tx_buffer { 152 const struct sk_buff *skb; 153 union { 154 efx_qword_t option; 155 dma_addr_t dma_addr; 156 }; 157 unsigned short flags; 158 unsigned short len; 159 unsigned short unmap_len; 160 unsigned short dma_offset; 161 }; 162 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */ 163 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */ 164 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */ 165 #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */ 166 167 /** 168 * struct efx_tx_queue - An Efx TX queue 169 * 170 * This is a ring buffer of TX fragments. 171 * Since the TX completion path always executes on the same 172 * CPU and the xmit path can operate on different CPUs, 173 * performance is increased by ensuring that the completion 174 * path and the xmit path operate on different cache lines. 175 * This is particularly important if the xmit path is always 176 * executing on one CPU which is different from the completion 177 * path. There is also a cache line for members which are 178 * read but not written on the fast path. 179 * 180 * @efx: The associated Efx NIC 181 * @queue: DMA queue number 182 * @tso_version: Version of TSO in use for this queue. 183 * @channel: The associated channel 184 * @core_txq: The networking core TX queue structure 185 * @buffer: The software buffer ring 186 * @cb_page: Array of pages of copy buffers. Carved up according to 187 * %EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks. 188 * @txd: The hardware descriptor ring 189 * @ptr_mask: The size of the ring minus 1. 190 * @piobuf: PIO buffer region for this TX queue (shared with its partner). 191 * Size of the region is efx_piobuf_size. 192 * @piobuf_offset: Buffer offset to be specified in PIO descriptors 193 * @initialised: Has hardware queue been initialised? 194 * @timestamping: Is timestamping enabled for this channel? 195 * @handle_tso: TSO xmit preparation handler. Sets up the TSO metadata and 196 * may also map tx data, depending on the nature of the TSO implementation. 197 * @read_count: Current read pointer. 198 * This is the number of buffers that have been removed from both rings. 199 * @old_write_count: The value of @write_count when last checked. 200 * This is here for performance reasons. The xmit path will 201 * only get the up-to-date value of @write_count if this 202 * variable indicates that the queue is empty. This is to 203 * avoid cache-line ping-pong between the xmit path and the 204 * completion path. 205 * @merge_events: Number of TX merged completion events 206 * @completed_desc_ptr: Most recent completed pointer - only used with 207 * timestamping. 208 * @completed_timestamp_major: Top part of the most recent tx timestamp. 209 * @completed_timestamp_minor: Low part of the most recent tx timestamp. 210 * @insert_count: Current insert pointer 211 * This is the number of buffers that have been added to the 212 * software ring. 213 * @write_count: Current write pointer 214 * This is the number of buffers that have been added to the 215 * hardware ring. 216 * @packet_write_count: Completable write pointer 217 * This is the write pointer of the last packet written. 218 * Normally this will equal @write_count, but as option descriptors 219 * don't produce completion events, they won't update this. 220 * Filled in iff @efx->type->option_descriptors; only used for PIO. 221 * Thus, this is written and used on EF10, and neither on farch. 222 * @old_read_count: The value of read_count when last checked. 223 * This is here for performance reasons. The xmit path will 224 * only get the up-to-date value of read_count if this 225 * variable indicates that the queue is full. This is to 226 * avoid cache-line ping-pong between the xmit path and the 227 * completion path. 228 * @tso_bursts: Number of times TSO xmit invoked by kernel 229 * @tso_long_headers: Number of packets with headers too long for standard 230 * blocks 231 * @tso_packets: Number of packets via the TSO xmit path 232 * @tso_fallbacks: Number of times TSO fallback used 233 * @pushes: Number of times the TX push feature has been used 234 * @pio_packets: Number of times the TX PIO feature has been used 235 * @xmit_more_available: Are any packets waiting to be pushed to the NIC 236 * @cb_packets: Number of times the TX copybreak feature has been used 237 * @empty_read_count: If the completion path has seen the queue as empty 238 * and the transmission path has not yet checked this, the value of 239 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0. 240 */ 241 struct efx_tx_queue { 242 /* Members which don't change on the fast path */ 243 struct efx_nic *efx ____cacheline_aligned_in_smp; 244 unsigned queue; 245 unsigned int tso_version; 246 struct efx_channel *channel; 247 struct netdev_queue *core_txq; 248 struct efx_tx_buffer *buffer; 249 struct efx_buffer *cb_page; 250 struct efx_special_buffer txd; 251 unsigned int ptr_mask; 252 void __iomem *piobuf; 253 unsigned int piobuf_offset; 254 bool initialised; 255 bool timestamping; 256 257 /* Function pointers used in the fast path. */ 258 int (*handle_tso)(struct efx_tx_queue*, struct sk_buff*, bool *); 259 260 /* Members used mainly on the completion path */ 261 unsigned int read_count ____cacheline_aligned_in_smp; 262 unsigned int old_write_count; 263 unsigned int merge_events; 264 unsigned int bytes_compl; 265 unsigned int pkts_compl; 266 unsigned int completed_desc_ptr; 267 u32 completed_timestamp_major; 268 u32 completed_timestamp_minor; 269 270 /* Members used only on the xmit path */ 271 unsigned int insert_count ____cacheline_aligned_in_smp; 272 unsigned int write_count; 273 unsigned int packet_write_count; 274 unsigned int old_read_count; 275 unsigned int tso_bursts; 276 unsigned int tso_long_headers; 277 unsigned int tso_packets; 278 unsigned int tso_fallbacks; 279 unsigned int pushes; 280 unsigned int pio_packets; 281 bool xmit_more_available; 282 unsigned int cb_packets; 283 /* Statistics to supplement MAC stats */ 284 unsigned long tx_packets; 285 286 /* Members shared between paths and sometimes updated */ 287 unsigned int empty_read_count ____cacheline_aligned_in_smp; 288 #define EFX_EMPTY_COUNT_VALID 0x80000000 289 atomic_t flush_outstanding; 290 }; 291 292 #define EFX_TX_CB_ORDER 7 293 #define EFX_TX_CB_SIZE (1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN 294 295 /** 296 * struct efx_rx_buffer - An Efx RX data buffer 297 * @dma_addr: DMA base address of the buffer 298 * @page: The associated page buffer. 299 * Will be %NULL if the buffer slot is currently free. 300 * @page_offset: If pending: offset in @page of DMA base address. 301 * If completed: offset in @page of Ethernet header. 302 * @len: If pending: length for DMA descriptor. 303 * If completed: received length, excluding hash prefix. 304 * @flags: Flags for buffer and packet state. These are only set on the 305 * first buffer of a scattered packet. 306 */ 307 struct efx_rx_buffer { 308 dma_addr_t dma_addr; 309 struct page *page; 310 u16 page_offset; 311 u16 len; 312 u16 flags; 313 }; 314 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001 315 #define EFX_RX_PKT_CSUMMED 0x0002 316 #define EFX_RX_PKT_DISCARD 0x0004 317 #define EFX_RX_PKT_TCP 0x0040 318 #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */ 319 #define EFX_RX_PKT_CSUM_LEVEL 0x0200 320 321 /** 322 * struct efx_rx_page_state - Page-based rx buffer state 323 * 324 * Inserted at the start of every page allocated for receive buffers. 325 * Used to facilitate sharing dma mappings between recycled rx buffers 326 * and those passed up to the kernel. 327 * 328 * @dma_addr: The dma address of this page. 329 */ 330 struct efx_rx_page_state { 331 dma_addr_t dma_addr; 332 333 unsigned int __pad[0] ____cacheline_aligned; 334 }; 335 336 /** 337 * struct efx_rx_queue - An Efx RX queue 338 * @efx: The associated Efx NIC 339 * @core_index: Index of network core RX queue. Will be >= 0 iff this 340 * is associated with a real RX queue. 341 * @buffer: The software buffer ring 342 * @rxd: The hardware descriptor ring 343 * @ptr_mask: The size of the ring minus 1. 344 * @refill_enabled: Enable refill whenever fill level is low 345 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as 346 * @rxq_flush_pending. 347 * @added_count: Number of buffers added to the receive queue. 348 * @notified_count: Number of buffers given to NIC (<= @added_count). 349 * @removed_count: Number of buffers removed from the receive queue. 350 * @scatter_n: Used by NIC specific receive code. 351 * @scatter_len: Used by NIC specific receive code. 352 * @page_ring: The ring to store DMA mapped pages for reuse. 353 * @page_add: Counter to calculate the write pointer for the recycle ring. 354 * @page_remove: Counter to calculate the read pointer for the recycle ring. 355 * @page_recycle_count: The number of pages that have been recycled. 356 * @page_recycle_failed: The number of pages that couldn't be recycled because 357 * the kernel still held a reference to them. 358 * @page_recycle_full: The number of pages that were released because the 359 * recycle ring was full. 360 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1. 361 * @max_fill: RX descriptor maximum fill level (<= ring size) 362 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill 363 * (<= @max_fill) 364 * @min_fill: RX descriptor minimum non-zero fill level. 365 * This records the minimum fill level observed when a ring 366 * refill was triggered. 367 * @recycle_count: RX buffer recycle counter. 368 * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). 369 */ 370 struct efx_rx_queue { 371 struct efx_nic *efx; 372 int core_index; 373 struct efx_rx_buffer *buffer; 374 struct efx_special_buffer rxd; 375 unsigned int ptr_mask; 376 bool refill_enabled; 377 bool flush_pending; 378 379 unsigned int added_count; 380 unsigned int notified_count; 381 unsigned int removed_count; 382 unsigned int scatter_n; 383 unsigned int scatter_len; 384 struct page **page_ring; 385 unsigned int page_add; 386 unsigned int page_remove; 387 unsigned int page_recycle_count; 388 unsigned int page_recycle_failed; 389 unsigned int page_recycle_full; 390 unsigned int page_ptr_mask; 391 unsigned int max_fill; 392 unsigned int fast_fill_trigger; 393 unsigned int min_fill; 394 unsigned int min_overfill; 395 unsigned int recycle_count; 396 struct timer_list slow_fill; 397 unsigned int slow_fill_count; 398 /* Statistics to supplement MAC stats */ 399 unsigned long rx_packets; 400 }; 401 402 enum efx_sync_events_state { 403 SYNC_EVENTS_DISABLED = 0, 404 SYNC_EVENTS_QUIESCENT, 405 SYNC_EVENTS_REQUESTED, 406 SYNC_EVENTS_VALID, 407 }; 408 409 /** 410 * struct efx_channel - An Efx channel 411 * 412 * A channel comprises an event queue, at least one TX queue, at least 413 * one RX queue, and an associated tasklet for processing the event 414 * queue. 415 * 416 * @efx: Associated Efx NIC 417 * @channel: Channel instance number 418 * @type: Channel type definition 419 * @eventq_init: Event queue initialised flag 420 * @enabled: Channel enabled indicator 421 * @irq: IRQ number (MSI and MSI-X only) 422 * @irq_moderation_us: IRQ moderation value (in microseconds) 423 * @napi_dev: Net device used with NAPI 424 * @napi_str: NAPI control structure 425 * @state: state for NAPI vs busy polling 426 * @state_lock: lock protecting @state 427 * @eventq: Event queue buffer 428 * @eventq_mask: Event queue pointer mask 429 * @eventq_read_ptr: Event queue read pointer 430 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel 431 * @irq_count: Number of IRQs since last adaptive moderation decision 432 * @irq_mod_score: IRQ moderation score 433 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS, 434 * indexed by filter ID 435 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors 436 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors 437 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors 438 * @n_rx_mcast_mismatch: Count of unmatched multicast frames 439 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors 440 * @n_rx_overlength: Count of RX_OVERLENGTH errors 441 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun 442 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to 443 * lack of descriptors 444 * @n_rx_merge_events: Number of RX merged completion events 445 * @n_rx_merge_packets: Number of RX packets completed by merged events 446 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by 447 * __efx_rx_packet(), or zero if there is none 448 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered 449 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0 450 * @rx_queue: RX queue for this channel 451 * @tx_queue: TX queues for this channel 452 * @sync_events_state: Current state of sync events on this channel 453 * @sync_timestamp_major: Major part of the last ptp sync event 454 * @sync_timestamp_minor: Minor part of the last ptp sync event 455 */ 456 struct efx_channel { 457 struct efx_nic *efx; 458 int channel; 459 const struct efx_channel_type *type; 460 bool eventq_init; 461 bool enabled; 462 int irq; 463 unsigned int irq_moderation_us; 464 struct net_device *napi_dev; 465 struct napi_struct napi_str; 466 #ifdef CONFIG_NET_RX_BUSY_POLL 467 unsigned long busy_poll_state; 468 #endif 469 struct efx_special_buffer eventq; 470 unsigned int eventq_mask; 471 unsigned int eventq_read_ptr; 472 int event_test_cpu; 473 474 unsigned int irq_count; 475 unsigned int irq_mod_score; 476 #ifdef CONFIG_RFS_ACCEL 477 unsigned int rfs_filters_added; 478 #define RPS_FLOW_ID_INVALID 0xFFFFFFFF 479 u32 *rps_flow_id; 480 #endif 481 482 unsigned int n_rx_tobe_disc; 483 unsigned int n_rx_ip_hdr_chksum_err; 484 unsigned int n_rx_tcp_udp_chksum_err; 485 unsigned int n_rx_outer_ip_hdr_chksum_err; 486 unsigned int n_rx_outer_tcp_udp_chksum_err; 487 unsigned int n_rx_inner_ip_hdr_chksum_err; 488 unsigned int n_rx_inner_tcp_udp_chksum_err; 489 unsigned int n_rx_eth_crc_err; 490 unsigned int n_rx_mcast_mismatch; 491 unsigned int n_rx_frm_trunc; 492 unsigned int n_rx_overlength; 493 unsigned int n_skbuff_leaks; 494 unsigned int n_rx_nodesc_trunc; 495 unsigned int n_rx_merge_events; 496 unsigned int n_rx_merge_packets; 497 498 unsigned int rx_pkt_n_frags; 499 unsigned int rx_pkt_index; 500 501 struct efx_rx_queue rx_queue; 502 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES]; 503 504 enum efx_sync_events_state sync_events_state; 505 u32 sync_timestamp_major; 506 u32 sync_timestamp_minor; 507 }; 508 509 /** 510 * struct efx_msi_context - Context for each MSI 511 * @efx: The associated NIC 512 * @index: Index of the channel/IRQ 513 * @name: Name of the channel/IRQ 514 * 515 * Unlike &struct efx_channel, this is never reallocated and is always 516 * safe for the IRQ handler to access. 517 */ 518 struct efx_msi_context { 519 struct efx_nic *efx; 520 unsigned int index; 521 char name[IFNAMSIZ + 6]; 522 }; 523 524 /** 525 * struct efx_channel_type - distinguishes traffic and extra channels 526 * @handle_no_channel: Handle failure to allocate an extra channel 527 * @pre_probe: Set up extra state prior to initialisation 528 * @post_remove: Tear down extra state after finalisation, if allocated. 529 * May be called on channels that have not been probed. 530 * @get_name: Generate the channel's name (used for its IRQ handler) 531 * @copy: Copy the channel state prior to reallocation. May be %NULL if 532 * reallocation is not supported. 533 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb() 534 * @want_txqs: Determine whether this channel should have TX queues 535 * created. If %NULL, TX queues are not created. 536 * @keep_eventq: Flag for whether event queue should be kept initialised 537 * while the device is stopped 538 * @want_pio: Flag for whether PIO buffers should be linked to this 539 * channel's TX queues. 540 */ 541 struct efx_channel_type { 542 void (*handle_no_channel)(struct efx_nic *); 543 int (*pre_probe)(struct efx_channel *); 544 void (*post_remove)(struct efx_channel *); 545 void (*get_name)(struct efx_channel *, char *buf, size_t len); 546 struct efx_channel *(*copy)(const struct efx_channel *); 547 bool (*receive_skb)(struct efx_channel *, struct sk_buff *); 548 bool (*want_txqs)(struct efx_channel *); 549 bool keep_eventq; 550 bool want_pio; 551 }; 552 553 enum efx_led_mode { 554 EFX_LED_OFF = 0, 555 EFX_LED_ON = 1, 556 EFX_LED_DEFAULT = 2 557 }; 558 559 #define STRING_TABLE_LOOKUP(val, member) \ 560 ((val) < member ## _max) ? member ## _names[val] : "(invalid)" 561 562 extern const char *const efx_loopback_mode_names[]; 563 extern const unsigned int efx_loopback_mode_max; 564 #define LOOPBACK_MODE(efx) \ 565 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) 566 567 extern const char *const efx_reset_type_names[]; 568 extern const unsigned int efx_reset_type_max; 569 #define RESET_TYPE(type) \ 570 STRING_TABLE_LOOKUP(type, efx_reset_type) 571 572 void efx_get_udp_tunnel_type_name(u16 type, char *buf, size_t buflen); 573 574 enum efx_int_mode { 575 /* Be careful if altering to correct macro below */ 576 EFX_INT_MODE_MSIX = 0, 577 EFX_INT_MODE_MSI = 1, 578 EFX_INT_MODE_LEGACY = 2, 579 EFX_INT_MODE_MAX /* Insert any new items before this */ 580 }; 581 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) 582 583 enum nic_state { 584 STATE_UNINIT = 0, /* device being probed/removed or is frozen */ 585 STATE_READY = 1, /* hardware ready and netdev registered */ 586 STATE_DISABLED = 2, /* device disabled due to hardware errors */ 587 STATE_RECOVERY = 3, /* device recovering from PCI error */ 588 }; 589 590 /* Forward declaration */ 591 struct efx_nic; 592 593 /* Pseudo bit-mask flow control field */ 594 #define EFX_FC_RX FLOW_CTRL_RX 595 #define EFX_FC_TX FLOW_CTRL_TX 596 #define EFX_FC_AUTO 4 597 598 /** 599 * struct efx_link_state - Current state of the link 600 * @up: Link is up 601 * @fd: Link is full-duplex 602 * @fc: Actual flow control flags 603 * @speed: Link speed (Mbps) 604 */ 605 struct efx_link_state { 606 bool up; 607 bool fd; 608 u8 fc; 609 unsigned int speed; 610 }; 611 612 static inline bool efx_link_state_equal(const struct efx_link_state *left, 613 const struct efx_link_state *right) 614 { 615 return left->up == right->up && left->fd == right->fd && 616 left->fc == right->fc && left->speed == right->speed; 617 } 618 619 /** 620 * struct efx_phy_operations - Efx PHY operations table 621 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, 622 * efx->loopback_modes. 623 * @init: Initialise PHY 624 * @fini: Shut down PHY 625 * @reconfigure: Reconfigure PHY (e.g. for new link parameters) 626 * @poll: Update @link_state and report whether it changed. 627 * Serialised by the mac_lock. 628 * @get_link_ksettings: Get ethtool settings. Serialised by the mac_lock. 629 * @set_link_ksettings: Set ethtool settings. Serialised by the mac_lock. 630 * @set_npage_adv: Set abilities advertised in (Extended) Next Page 631 * (only needed where AN bit is set in mmds) 632 * @test_alive: Test that PHY is 'alive' (online) 633 * @test_name: Get the name of a PHY-specific test/result 634 * @run_tests: Run tests and record results as appropriate (offline). 635 * Flags are the ethtool tests flags. 636 */ 637 struct efx_phy_operations { 638 int (*probe) (struct efx_nic *efx); 639 int (*init) (struct efx_nic *efx); 640 void (*fini) (struct efx_nic *efx); 641 void (*remove) (struct efx_nic *efx); 642 int (*reconfigure) (struct efx_nic *efx); 643 bool (*poll) (struct efx_nic *efx); 644 void (*get_link_ksettings)(struct efx_nic *efx, 645 struct ethtool_link_ksettings *cmd); 646 int (*set_link_ksettings)(struct efx_nic *efx, 647 const struct ethtool_link_ksettings *cmd); 648 void (*set_npage_adv) (struct efx_nic *efx, u32); 649 int (*test_alive) (struct efx_nic *efx); 650 const char *(*test_name) (struct efx_nic *efx, unsigned int index); 651 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); 652 int (*get_module_eeprom) (struct efx_nic *efx, 653 struct ethtool_eeprom *ee, 654 u8 *data); 655 int (*get_module_info) (struct efx_nic *efx, 656 struct ethtool_modinfo *modinfo); 657 }; 658 659 /** 660 * enum efx_phy_mode - PHY operating mode flags 661 * @PHY_MODE_NORMAL: on and should pass traffic 662 * @PHY_MODE_TX_DISABLED: on with TX disabled 663 * @PHY_MODE_LOW_POWER: set to low power through MDIO 664 * @PHY_MODE_OFF: switched off through external control 665 * @PHY_MODE_SPECIAL: on but will not pass traffic 666 */ 667 enum efx_phy_mode { 668 PHY_MODE_NORMAL = 0, 669 PHY_MODE_TX_DISABLED = 1, 670 PHY_MODE_LOW_POWER = 2, 671 PHY_MODE_OFF = 4, 672 PHY_MODE_SPECIAL = 8, 673 }; 674 675 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) 676 { 677 return !!(mode & ~PHY_MODE_TX_DISABLED); 678 } 679 680 /** 681 * struct efx_hw_stat_desc - Description of a hardware statistic 682 * @name: Name of the statistic as visible through ethtool, or %NULL if 683 * it should not be exposed 684 * @dma_width: Width in bits (0 for non-DMA statistics) 685 * @offset: Offset within stats (ignored for non-DMA statistics) 686 */ 687 struct efx_hw_stat_desc { 688 const char *name; 689 u16 dma_width; 690 u16 offset; 691 }; 692 693 /* Number of bits used in a multicast filter hash address */ 694 #define EFX_MCAST_HASH_BITS 8 695 696 /* Number of (single-bit) entries in a multicast filter hash */ 697 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) 698 699 /* An Efx multicast filter hash */ 700 union efx_multicast_hash { 701 u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; 702 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; 703 }; 704 705 struct vfdi_status; 706 707 /** 708 * struct efx_nic - an Efx NIC 709 * @name: Device name (net device name or bus id before net device registered) 710 * @pci_dev: The PCI device 711 * @node: List node for maintaning primary/secondary function lists 712 * @primary: &struct efx_nic instance for the primary function of this 713 * controller. May be the same structure, and may be %NULL if no 714 * primary function is bound. Serialised by rtnl_lock. 715 * @secondary_list: List of &struct efx_nic instances for the secondary PCI 716 * functions of the controller, if this is for the primary function. 717 * Serialised by rtnl_lock. 718 * @type: Controller type attributes 719 * @legacy_irq: IRQ number 720 * @workqueue: Workqueue for port reconfigures and the HW monitor. 721 * Work items do not hold and must not acquire RTNL. 722 * @workqueue_name: Name of workqueue 723 * @reset_work: Scheduled reset workitem 724 * @membase_phys: Memory BAR value as physical address 725 * @membase: Memory BAR value 726 * @vi_stride: step between per-VI registers / memory regions 727 * @interrupt_mode: Interrupt mode 728 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds 729 * @timer_max_ns: Interrupt timer maximum value, in nanoseconds 730 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues 731 * @irq_rx_mod_step_us: Step size for IRQ moderation for RX event queues 732 * @irq_rx_moderation_us: IRQ moderation time for RX event queues 733 * @msg_enable: Log message enable flags 734 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock. 735 * @reset_pending: Bitmask for pending resets 736 * @tx_queue: TX DMA queues 737 * @rx_queue: RX DMA queues 738 * @channel: Channels 739 * @msi_context: Context for each MSI 740 * @extra_channel_types: Types of extra (non-traffic) channels that 741 * should be allocated for this NIC 742 * @rxq_entries: Size of receive queues requested by user. 743 * @txq_entries: Size of transmit queues requested by user. 744 * @txq_stop_thresh: TX queue fill level at or above which we stop it. 745 * @txq_wake_thresh: TX queue fill level at or below which we wake it. 746 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches 747 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches 748 * @sram_lim_qw: Qword address limit of SRAM 749 * @next_buffer_table: First available buffer table id 750 * @n_channels: Number of channels in use 751 * @n_rx_channels: Number of channels used for RX (= number of RX queues) 752 * @n_tx_channels: Number of channels used for TX 753 * @n_extra_tx_channels: Number of extra channels with TX queues 754 * @rx_ip_align: RX DMA address offset to have IP header aligned in 755 * in accordance with NET_IP_ALIGN 756 * @rx_dma_len: Current maximum RX DMA length 757 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer 758 * @rx_buffer_truesize: Amortised allocation size of an RX buffer, 759 * for use in sk_buff::truesize 760 * @rx_prefix_size: Size of RX prefix before packet data 761 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data 762 * (valid only if @rx_prefix_size != 0; always negative) 763 * @rx_packet_len_offset: Offset of RX packet length from start of packet data 764 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative) 765 * @rx_packet_ts_offset: Offset of timestamp from start of packet data 766 * (valid only if channel->sync_timestamps_enabled; always negative) 767 * @rx_hash_key: Toeplitz hash key for RSS 768 * @rx_indir_table: Indirection table for RSS 769 * @rx_scatter: Scatter mode enabled for receives 770 * @rss_active: RSS enabled on hardware 771 * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled 772 * @int_error_count: Number of internal errors seen recently 773 * @int_error_expire: Time at which error count will be expired 774 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will 775 * acknowledge but do nothing else. 776 * @irq_status: Interrupt status buffer 777 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 778 * @irq_level: IRQ level/index for IRQs not triggered by an event queue 779 * @selftest_work: Work item for asynchronous self-test 780 * @mtd_list: List of MTDs attached to the NIC 781 * @nic_data: Hardware dependent state 782 * @mcdi: Management-Controller-to-Driver Interface state 783 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, 784 * efx_monitor() and efx_reconfigure_port() 785 * @port_enabled: Port enabled indicator. 786 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and 787 * efx_mac_work() with kernel interfaces. Safe to read under any 788 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must 789 * be held to modify it. 790 * @port_initialized: Port initialized? 791 * @net_dev: Operating system network device. Consider holding the rtnl lock 792 * @fixed_features: Features which cannot be turned off 793 * @num_mac_stats: Number of MAC stats reported by firmware (MAC_STATS_NUM_STATS 794 * field of %MC_CMD_GET_CAPABILITIES_V4 response, or %MC_CMD_MAC_NSTATS) 795 * @stats_buffer: DMA buffer for statistics 796 * @phy_type: PHY type 797 * @phy_op: PHY interface 798 * @phy_data: PHY private data (including PHY-specific stats) 799 * @mdio: PHY MDIO interface 800 * @mdio_bus: PHY MDIO bus ID (only used by Siena) 801 * @phy_mode: PHY operating mode. Serialised by @mac_lock. 802 * @link_advertising: Autonegotiation advertising flags 803 * @link_state: Current state of the link 804 * @n_link_state_changes: Number of times the link has changed state 805 * @unicast_filter: Flag for Falcon-arch simple unicast filter. 806 * Protected by @mac_lock. 807 * @multicast_hash: Multicast hash table for Falcon-arch. 808 * Protected by @mac_lock. 809 * @wanted_fc: Wanted flow control flags 810 * @fc_disable: When non-zero flow control is disabled. Typically used to 811 * ensure that network back pressure doesn't delay dma queue flushes. 812 * Serialised by the rtnl lock. 813 * @mac_work: Work item for changing MAC promiscuity and multicast hash 814 * @loopback_mode: Loopback status 815 * @loopback_modes: Supported loopback mode bitmask 816 * @loopback_selftest: Offline self-test private state 817 * @filter_sem: Filter table rw_semaphore, for freeing the table 818 * @filter_lock: Filter table lock, for mere content changes 819 * @filter_state: Architecture-dependent filter table state 820 * @rps_expire_channel: Next channel to check for expiry 821 * @rps_expire_index: Next index to check for expiry in 822 * @rps_expire_channel's @rps_flow_id 823 * @active_queues: Count of RX and TX queues that haven't been flushed and drained. 824 * @rxq_flush_pending: Count of number of receive queues that need to be flushed. 825 * Decremented when the efx_flush_rx_queue() is called. 826 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet 827 * completed (either success or failure). Not used when MCDI is used to 828 * flush receive queues. 829 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions. 830 * @vf_count: Number of VFs intended to be enabled. 831 * @vf_init_count: Number of VFs that have been fully initialised. 832 * @vi_scale: log2 number of vnics per VF. 833 * @ptp_data: PTP state data 834 * @ptp_warned: has this NIC seen and warned about unexpected PTP events? 835 * @vpd_sn: Serial number read from VPD 836 * @monitor_work: Hardware monitor workitem 837 * @biu_lock: BIU (bus interface unit) lock 838 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This 839 * field is used by efx_test_interrupts() to verify that an 840 * interrupt has occurred. 841 * @stats_lock: Statistics update lock. Must be held when calling 842 * efx_nic_type::{update,start,stop}_stats. 843 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb 844 * 845 * This is stored in the private area of the &struct net_device. 846 */ 847 struct efx_nic { 848 /* The following fields should be written very rarely */ 849 850 char name[IFNAMSIZ]; 851 struct list_head node; 852 struct efx_nic *primary; 853 struct list_head secondary_list; 854 struct pci_dev *pci_dev; 855 unsigned int port_num; 856 const struct efx_nic_type *type; 857 int legacy_irq; 858 bool eeh_disabled_legacy_irq; 859 struct workqueue_struct *workqueue; 860 char workqueue_name[16]; 861 struct work_struct reset_work; 862 resource_size_t membase_phys; 863 void __iomem *membase; 864 865 unsigned int vi_stride; 866 867 enum efx_int_mode interrupt_mode; 868 unsigned int timer_quantum_ns; 869 unsigned int timer_max_ns; 870 bool irq_rx_adaptive; 871 unsigned int irq_mod_step_us; 872 unsigned int irq_rx_moderation_us; 873 u32 msg_enable; 874 875 enum nic_state state; 876 unsigned long reset_pending; 877 878 struct efx_channel *channel[EFX_MAX_CHANNELS]; 879 struct efx_msi_context msi_context[EFX_MAX_CHANNELS]; 880 const struct efx_channel_type * 881 extra_channel_type[EFX_MAX_EXTRA_CHANNELS]; 882 883 unsigned rxq_entries; 884 unsigned txq_entries; 885 unsigned int txq_stop_thresh; 886 unsigned int txq_wake_thresh; 887 888 unsigned tx_dc_base; 889 unsigned rx_dc_base; 890 unsigned sram_lim_qw; 891 unsigned next_buffer_table; 892 893 unsigned int max_channels; 894 unsigned int max_tx_channels; 895 unsigned n_channels; 896 unsigned n_rx_channels; 897 unsigned rss_spread; 898 unsigned tx_channel_offset; 899 unsigned n_tx_channels; 900 unsigned n_extra_tx_channels; 901 unsigned int rx_ip_align; 902 unsigned int rx_dma_len; 903 unsigned int rx_buffer_order; 904 unsigned int rx_buffer_truesize; 905 unsigned int rx_page_buf_step; 906 unsigned int rx_bufs_per_page; 907 unsigned int rx_pages_per_batch; 908 unsigned int rx_prefix_size; 909 int rx_packet_hash_offset; 910 int rx_packet_len_offset; 911 int rx_packet_ts_offset; 912 u8 rx_hash_key[40]; 913 u32 rx_indir_table[128]; 914 bool rx_scatter; 915 bool rss_active; 916 bool rx_hash_udp_4tuple; 917 918 unsigned int_error_count; 919 unsigned long int_error_expire; 920 921 bool irq_soft_enabled; 922 struct efx_buffer irq_status; 923 unsigned irq_zero_count; 924 unsigned irq_level; 925 struct delayed_work selftest_work; 926 927 #ifdef CONFIG_SFC_MTD 928 struct list_head mtd_list; 929 #endif 930 931 void *nic_data; 932 struct efx_mcdi_data *mcdi; 933 934 struct mutex mac_lock; 935 struct work_struct mac_work; 936 bool port_enabled; 937 938 bool mc_bist_for_other_fn; 939 bool port_initialized; 940 struct net_device *net_dev; 941 942 netdev_features_t fixed_features; 943 944 u16 num_mac_stats; 945 struct efx_buffer stats_buffer; 946 u64 rx_nodesc_drops_total; 947 u64 rx_nodesc_drops_while_down; 948 bool rx_nodesc_drops_prev_state; 949 950 unsigned int phy_type; 951 const struct efx_phy_operations *phy_op; 952 void *phy_data; 953 struct mdio_if_info mdio; 954 unsigned int mdio_bus; 955 enum efx_phy_mode phy_mode; 956 957 __ETHTOOL_DECLARE_LINK_MODE_MASK(link_advertising); 958 struct efx_link_state link_state; 959 unsigned int n_link_state_changes; 960 961 bool unicast_filter; 962 union efx_multicast_hash multicast_hash; 963 u8 wanted_fc; 964 unsigned fc_disable; 965 966 atomic_t rx_reset; 967 enum efx_loopback_mode loopback_mode; 968 u64 loopback_modes; 969 970 void *loopback_selftest; 971 972 struct rw_semaphore filter_sem; 973 spinlock_t filter_lock; 974 void *filter_state; 975 #ifdef CONFIG_RFS_ACCEL 976 unsigned int rps_expire_channel; 977 unsigned int rps_expire_index; 978 #endif 979 980 atomic_t active_queues; 981 atomic_t rxq_flush_pending; 982 atomic_t rxq_flush_outstanding; 983 wait_queue_head_t flush_wq; 984 985 #ifdef CONFIG_SFC_SRIOV 986 unsigned vf_count; 987 unsigned vf_init_count; 988 unsigned vi_scale; 989 #endif 990 991 struct efx_ptp_data *ptp_data; 992 bool ptp_warned; 993 994 char *vpd_sn; 995 996 /* The following fields may be written more often */ 997 998 struct delayed_work monitor_work ____cacheline_aligned_in_smp; 999 spinlock_t biu_lock; 1000 int last_irq_cpu; 1001 spinlock_t stats_lock; 1002 atomic_t n_rx_noskb_drops; 1003 }; 1004 1005 static inline int efx_dev_registered(struct efx_nic *efx) 1006 { 1007 return efx->net_dev->reg_state == NETREG_REGISTERED; 1008 } 1009 1010 static inline unsigned int efx_port_num(struct efx_nic *efx) 1011 { 1012 return efx->port_num; 1013 } 1014 1015 struct efx_mtd_partition { 1016 struct list_head node; 1017 struct mtd_info mtd; 1018 const char *dev_type_name; 1019 const char *type_name; 1020 char name[IFNAMSIZ + 20]; 1021 }; 1022 1023 struct efx_udp_tunnel { 1024 u16 type; /* TUNNEL_ENCAP_UDP_PORT_ENTRY_foo, see mcdi_pcol.h */ 1025 __be16 port; 1026 /* Count of repeated adds of the same port. Used only inside the list, 1027 * not in request arguments. 1028 */ 1029 u16 count; 1030 }; 1031 1032 /** 1033 * struct efx_nic_type - Efx device type definition 1034 * @mem_bar: Get the memory BAR 1035 * @mem_map_size: Get memory BAR mapped size 1036 * @probe: Probe the controller 1037 * @remove: Free resources allocated by probe() 1038 * @init: Initialise the controller 1039 * @dimension_resources: Dimension controller resources (buffer table, 1040 * and VIs once the available interrupt resources are clear) 1041 * @fini: Shut down the controller 1042 * @monitor: Periodic function for polling link state and hardware monitor 1043 * @map_reset_reason: Map ethtool reset reason to a reset method 1044 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible 1045 * @reset: Reset the controller hardware and possibly the PHY. This will 1046 * be called while the controller is uninitialised. 1047 * @probe_port: Probe the MAC and PHY 1048 * @remove_port: Free resources allocated by probe_port() 1049 * @handle_global_event: Handle a "global" event (may be %NULL) 1050 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues) 1051 * @prepare_flush: Prepare the hardware for flushing the DMA queues 1052 * (for Falcon architecture) 1053 * @finish_flush: Clean up after flushing the DMA queues (for Falcon 1054 * architecture) 1055 * @prepare_flr: Prepare for an FLR 1056 * @finish_flr: Clean up after an FLR 1057 * @describe_stats: Describe statistics for ethtool 1058 * @update_stats: Update statistics not provided by event handling. 1059 * Either argument may be %NULL. 1060 * @start_stats: Start the regular fetching of statistics 1061 * @pull_stats: Pull stats from the NIC and wait until they arrive. 1062 * @stop_stats: Stop the regular fetching of statistics 1063 * @set_id_led: Set state of identifying LED or revert to automatic function 1064 * @push_irq_moderation: Apply interrupt moderation value 1065 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY 1066 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL) 1067 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings 1068 * to the hardware. Serialised by the mac_lock. 1069 * @check_mac_fault: Check MAC fault state. True if fault present. 1070 * @get_wol: Get WoL configuration from driver state 1071 * @set_wol: Push WoL configuration to the NIC 1072 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) 1073 * @test_chip: Test registers. May use efx_farch_test_registers(), and is 1074 * expected to reset the NIC. 1075 * @test_nvram: Test validity of NVRAM contents 1076 * @mcdi_request: Send an MCDI request with the given header and SDU. 1077 * The SDU length may be any value from 0 up to the protocol- 1078 * defined maximum, but its buffer will be padded to a multiple 1079 * of 4 bytes. 1080 * @mcdi_poll_response: Test whether an MCDI response is available. 1081 * @mcdi_read_response: Read the MCDI response PDU. The offset will 1082 * be a multiple of 4. The length may not be, but the buffer 1083 * will be padded so it is safe to round up. 1084 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so, 1085 * return an appropriate error code for aborting any current 1086 * request; otherwise return 0. 1087 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must 1088 * be separately enabled after this. 1089 * @irq_test_generate: Generate a test IRQ 1090 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event 1091 * queue must be separately disabled before this. 1092 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is 1093 * a pointer to the &struct efx_msi_context for the channel. 1094 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument 1095 * is a pointer to the &struct efx_nic. 1096 * @tx_probe: Allocate resources for TX queue 1097 * @tx_init: Initialise TX queue on the NIC 1098 * @tx_remove: Free resources for TX queue 1099 * @tx_write: Write TX descriptors and doorbell 1100 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC 1101 * @rx_pull_rss_config: Read RSS hash key and indirection table back from the NIC 1102 * @rx_probe: Allocate resources for RX queue 1103 * @rx_init: Initialise RX queue on the NIC 1104 * @rx_remove: Free resources for RX queue 1105 * @rx_write: Write RX descriptors and doorbell 1106 * @rx_defer_refill: Generate a refill reminder event 1107 * @ev_probe: Allocate resources for event queue 1108 * @ev_init: Initialise event queue on the NIC 1109 * @ev_fini: Deinitialise event queue on the NIC 1110 * @ev_remove: Free resources for event queue 1111 * @ev_process: Process events for a queue, up to the given NAPI quota 1112 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ 1113 * @ev_test_generate: Generate a test event 1114 * @filter_table_probe: Probe filter capabilities and set up filter software state 1115 * @filter_table_restore: Restore filters removed from hardware 1116 * @filter_table_remove: Remove filters from hardware and tear down software state 1117 * @filter_update_rx_scatter: Update filters after change to rx scatter setting 1118 * @filter_insert: add or replace a filter 1119 * @filter_remove_safe: remove a filter by ID, carefully 1120 * @filter_get_safe: retrieve a filter by ID, carefully 1121 * @filter_clear_rx: Remove all RX filters whose priority is less than or 1122 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO 1123 * @filter_count_rx_used: Get the number of filters in use at a given priority 1124 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1 1125 * @filter_get_rx_ids: Get list of RX filters at a given priority 1126 * @filter_rfs_insert: Add or replace a filter for RFS. This must be 1127 * atomic. The hardware change may be asynchronous but should 1128 * not be delayed for long. It may fail if this can't be done 1129 * atomically. 1130 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS. 1131 * This must check whether the specified table entry is used by RFS 1132 * and that rps_may_expire_flow() returns true for it. 1133 * @mtd_probe: Probe and add MTD partitions associated with this net device, 1134 * using efx_mtd_add() 1135 * @mtd_rename: Set an MTD partition name using the net device name 1136 * @mtd_read: Read from an MTD partition 1137 * @mtd_erase: Erase part of an MTD partition 1138 * @mtd_write: Write to an MTD partition 1139 * @mtd_sync: Wait for write-back to complete on MTD partition. This 1140 * also notifies the driver that a writer has finished using this 1141 * partition. 1142 * @ptp_write_host_time: Send host time to MC as part of sync protocol 1143 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX 1144 * timestamping, possibly only temporarily for the purposes of a reset. 1145 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags 1146 * and tx_type will already have been validated but this operation 1147 * must validate and update rx_filter. 1148 * @get_phys_port_id: Get the underlying physical port id. 1149 * @set_mac_address: Set the MAC address of the device 1150 * @tso_versions: Returns mask of firmware-assisted TSO versions supported. 1151 * If %NULL, then device does not support any TSO version. 1152 * @udp_tnl_push_ports: Push the list of UDP tunnel ports to the NIC if required. 1153 * @udp_tnl_add_port: Add a UDP tunnel port 1154 * @udp_tnl_has_port: Check if a port has been added as UDP tunnel 1155 * @udp_tnl_del_port: Remove a UDP tunnel port 1156 * @revision: Hardware architecture revision 1157 * @txd_ptr_tbl_base: TX descriptor ring base address 1158 * @rxd_ptr_tbl_base: RX descriptor ring base address 1159 * @buf_tbl_base: Buffer table base address 1160 * @evq_ptr_tbl_base: Event queue pointer table base address 1161 * @evq_rptr_tbl_base: Event queue read-pointer table base address 1162 * @max_dma_mask: Maximum possible DMA mask 1163 * @rx_prefix_size: Size of RX prefix before packet data 1164 * @rx_hash_offset: Offset of RX flow hash within prefix 1165 * @rx_ts_offset: Offset of timestamp within prefix 1166 * @rx_buffer_padding: Size of padding at end of RX packet 1167 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers 1168 * @always_rx_scatter: NIC will always scatter packets to multiple buffers 1169 * @option_descriptors: NIC supports TX option descriptors 1170 * @min_interrupt_mode: Lowest capability interrupt mode supported 1171 * from &enum efx_int_mode. 1172 * @max_interrupt_mode: Highest capability interrupt mode supported 1173 * from &enum efx_int_mode. 1174 * @timer_period_max: Maximum period of interrupt timer (in ticks) 1175 * @offload_features: net_device feature flags for protocol offload 1176 * features implemented in hardware 1177 * @mcdi_max_ver: Maximum MCDI version supported 1178 * @hwtstamp_filters: Mask of hardware timestamp filter types supported 1179 */ 1180 struct efx_nic_type { 1181 bool is_vf; 1182 unsigned int (*mem_bar)(struct efx_nic *efx); 1183 unsigned int (*mem_map_size)(struct efx_nic *efx); 1184 int (*probe)(struct efx_nic *efx); 1185 void (*remove)(struct efx_nic *efx); 1186 int (*init)(struct efx_nic *efx); 1187 int (*dimension_resources)(struct efx_nic *efx); 1188 void (*fini)(struct efx_nic *efx); 1189 void (*monitor)(struct efx_nic *efx); 1190 enum reset_type (*map_reset_reason)(enum reset_type reason); 1191 int (*map_reset_flags)(u32 *flags); 1192 int (*reset)(struct efx_nic *efx, enum reset_type method); 1193 int (*probe_port)(struct efx_nic *efx); 1194 void (*remove_port)(struct efx_nic *efx); 1195 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *); 1196 int (*fini_dmaq)(struct efx_nic *efx); 1197 void (*prepare_flush)(struct efx_nic *efx); 1198 void (*finish_flush)(struct efx_nic *efx); 1199 void (*prepare_flr)(struct efx_nic *efx); 1200 void (*finish_flr)(struct efx_nic *efx); 1201 size_t (*describe_stats)(struct efx_nic *efx, u8 *names); 1202 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats, 1203 struct rtnl_link_stats64 *core_stats); 1204 void (*start_stats)(struct efx_nic *efx); 1205 void (*pull_stats)(struct efx_nic *efx); 1206 void (*stop_stats)(struct efx_nic *efx); 1207 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); 1208 void (*push_irq_moderation)(struct efx_channel *channel); 1209 int (*reconfigure_port)(struct efx_nic *efx); 1210 void (*prepare_enable_fc_tx)(struct efx_nic *efx); 1211 int (*reconfigure_mac)(struct efx_nic *efx); 1212 bool (*check_mac_fault)(struct efx_nic *efx); 1213 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); 1214 int (*set_wol)(struct efx_nic *efx, u32 type); 1215 void (*resume_wol)(struct efx_nic *efx); 1216 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests); 1217 int (*test_nvram)(struct efx_nic *efx); 1218 void (*mcdi_request)(struct efx_nic *efx, 1219 const efx_dword_t *hdr, size_t hdr_len, 1220 const efx_dword_t *sdu, size_t sdu_len); 1221 bool (*mcdi_poll_response)(struct efx_nic *efx); 1222 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu, 1223 size_t pdu_offset, size_t pdu_len); 1224 int (*mcdi_poll_reboot)(struct efx_nic *efx); 1225 void (*mcdi_reboot_detected)(struct efx_nic *efx); 1226 void (*irq_enable_master)(struct efx_nic *efx); 1227 int (*irq_test_generate)(struct efx_nic *efx); 1228 void (*irq_disable_non_ev)(struct efx_nic *efx); 1229 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id); 1230 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id); 1231 int (*tx_probe)(struct efx_tx_queue *tx_queue); 1232 void (*tx_init)(struct efx_tx_queue *tx_queue); 1233 void (*tx_remove)(struct efx_tx_queue *tx_queue); 1234 void (*tx_write)(struct efx_tx_queue *tx_queue); 1235 unsigned int (*tx_limit_len)(struct efx_tx_queue *tx_queue, 1236 dma_addr_t dma_addr, unsigned int len); 1237 int (*rx_push_rss_config)(struct efx_nic *efx, bool user, 1238 const u32 *rx_indir_table, const u8 *key); 1239 int (*rx_pull_rss_config)(struct efx_nic *efx); 1240 int (*rx_probe)(struct efx_rx_queue *rx_queue); 1241 void (*rx_init)(struct efx_rx_queue *rx_queue); 1242 void (*rx_remove)(struct efx_rx_queue *rx_queue); 1243 void (*rx_write)(struct efx_rx_queue *rx_queue); 1244 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue); 1245 int (*ev_probe)(struct efx_channel *channel); 1246 int (*ev_init)(struct efx_channel *channel); 1247 void (*ev_fini)(struct efx_channel *channel); 1248 void (*ev_remove)(struct efx_channel *channel); 1249 int (*ev_process)(struct efx_channel *channel, int quota); 1250 void (*ev_read_ack)(struct efx_channel *channel); 1251 void (*ev_test_generate)(struct efx_channel *channel); 1252 int (*filter_table_probe)(struct efx_nic *efx); 1253 void (*filter_table_restore)(struct efx_nic *efx); 1254 void (*filter_table_remove)(struct efx_nic *efx); 1255 void (*filter_update_rx_scatter)(struct efx_nic *efx); 1256 s32 (*filter_insert)(struct efx_nic *efx, 1257 struct efx_filter_spec *spec, bool replace); 1258 int (*filter_remove_safe)(struct efx_nic *efx, 1259 enum efx_filter_priority priority, 1260 u32 filter_id); 1261 int (*filter_get_safe)(struct efx_nic *efx, 1262 enum efx_filter_priority priority, 1263 u32 filter_id, struct efx_filter_spec *); 1264 int (*filter_clear_rx)(struct efx_nic *efx, 1265 enum efx_filter_priority priority); 1266 u32 (*filter_count_rx_used)(struct efx_nic *efx, 1267 enum efx_filter_priority priority); 1268 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx); 1269 s32 (*filter_get_rx_ids)(struct efx_nic *efx, 1270 enum efx_filter_priority priority, 1271 u32 *buf, u32 size); 1272 #ifdef CONFIG_RFS_ACCEL 1273 s32 (*filter_rfs_insert)(struct efx_nic *efx, 1274 struct efx_filter_spec *spec); 1275 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id, 1276 unsigned int index); 1277 #endif 1278 #ifdef CONFIG_SFC_MTD 1279 int (*mtd_probe)(struct efx_nic *efx); 1280 void (*mtd_rename)(struct efx_mtd_partition *part); 1281 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len, 1282 size_t *retlen, u8 *buffer); 1283 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len); 1284 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len, 1285 size_t *retlen, const u8 *buffer); 1286 int (*mtd_sync)(struct mtd_info *mtd); 1287 #endif 1288 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time); 1289 int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp); 1290 int (*ptp_set_ts_config)(struct efx_nic *efx, 1291 struct hwtstamp_config *init); 1292 int (*sriov_configure)(struct efx_nic *efx, int num_vfs); 1293 int (*vlan_rx_add_vid)(struct efx_nic *efx, __be16 proto, u16 vid); 1294 int (*vlan_rx_kill_vid)(struct efx_nic *efx, __be16 proto, u16 vid); 1295 int (*get_phys_port_id)(struct efx_nic *efx, 1296 struct netdev_phys_item_id *ppid); 1297 int (*sriov_init)(struct efx_nic *efx); 1298 void (*sriov_fini)(struct efx_nic *efx); 1299 bool (*sriov_wanted)(struct efx_nic *efx); 1300 void (*sriov_reset)(struct efx_nic *efx); 1301 void (*sriov_flr)(struct efx_nic *efx, unsigned vf_i); 1302 int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, u8 *mac); 1303 int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan, 1304 u8 qos); 1305 int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i, 1306 bool spoofchk); 1307 int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i, 1308 struct ifla_vf_info *ivi); 1309 int (*sriov_set_vf_link_state)(struct efx_nic *efx, int vf_i, 1310 int link_state); 1311 int (*vswitching_probe)(struct efx_nic *efx); 1312 int (*vswitching_restore)(struct efx_nic *efx); 1313 void (*vswitching_remove)(struct efx_nic *efx); 1314 int (*get_mac_address)(struct efx_nic *efx, unsigned char *perm_addr); 1315 int (*set_mac_address)(struct efx_nic *efx); 1316 u32 (*tso_versions)(struct efx_nic *efx); 1317 int (*udp_tnl_push_ports)(struct efx_nic *efx); 1318 int (*udp_tnl_add_port)(struct efx_nic *efx, struct efx_udp_tunnel tnl); 1319 bool (*udp_tnl_has_port)(struct efx_nic *efx, __be16 port); 1320 int (*udp_tnl_del_port)(struct efx_nic *efx, struct efx_udp_tunnel tnl); 1321 1322 int revision; 1323 unsigned int txd_ptr_tbl_base; 1324 unsigned int rxd_ptr_tbl_base; 1325 unsigned int buf_tbl_base; 1326 unsigned int evq_ptr_tbl_base; 1327 unsigned int evq_rptr_tbl_base; 1328 u64 max_dma_mask; 1329 unsigned int rx_prefix_size; 1330 unsigned int rx_hash_offset; 1331 unsigned int rx_ts_offset; 1332 unsigned int rx_buffer_padding; 1333 bool can_rx_scatter; 1334 bool always_rx_scatter; 1335 bool option_descriptors; 1336 unsigned int min_interrupt_mode; 1337 unsigned int max_interrupt_mode; 1338 unsigned int timer_period_max; 1339 netdev_features_t offload_features; 1340 int mcdi_max_ver; 1341 unsigned int max_rx_ip_filters; 1342 u32 hwtstamp_filters; 1343 unsigned int rx_hash_key_size; 1344 }; 1345 1346 /************************************************************************** 1347 * 1348 * Prototypes and inline functions 1349 * 1350 *************************************************************************/ 1351 1352 static inline struct efx_channel * 1353 efx_get_channel(struct efx_nic *efx, unsigned index) 1354 { 1355 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_channels); 1356 return efx->channel[index]; 1357 } 1358 1359 /* Iterate over all used channels */ 1360 #define efx_for_each_channel(_channel, _efx) \ 1361 for (_channel = (_efx)->channel[0]; \ 1362 _channel; \ 1363 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ 1364 (_efx)->channel[_channel->channel + 1] : NULL) 1365 1366 /* Iterate over all used channels in reverse */ 1367 #define efx_for_each_channel_rev(_channel, _efx) \ 1368 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \ 1369 _channel; \ 1370 _channel = _channel->channel ? \ 1371 (_efx)->channel[_channel->channel - 1] : NULL) 1372 1373 static inline struct efx_tx_queue * 1374 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) 1375 { 1376 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_tx_channels || 1377 type >= EFX_TXQ_TYPES); 1378 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type]; 1379 } 1380 1381 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel) 1382 { 1383 return channel->type && channel->type->want_txqs && 1384 channel->type->want_txqs(channel); 1385 } 1386 1387 static inline struct efx_tx_queue * 1388 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type) 1389 { 1390 EFX_WARN_ON_ONCE_PARANOID(!efx_channel_has_tx_queues(channel) || 1391 type >= EFX_TXQ_TYPES); 1392 return &channel->tx_queue[type]; 1393 } 1394 1395 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue) 1396 { 1397 return !(tx_queue->efx->net_dev->num_tc < 2 && 1398 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI); 1399 } 1400 1401 /* Iterate over all TX queues belonging to a channel */ 1402 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ 1403 if (!efx_channel_has_tx_queues(_channel)) \ 1404 ; \ 1405 else \ 1406 for (_tx_queue = (_channel)->tx_queue; \ 1407 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \ 1408 efx_tx_queue_used(_tx_queue); \ 1409 _tx_queue++) 1410 1411 /* Iterate over all possible TX queues belonging to a channel */ 1412 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \ 1413 if (!efx_channel_has_tx_queues(_channel)) \ 1414 ; \ 1415 else \ 1416 for (_tx_queue = (_channel)->tx_queue; \ 1417 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ 1418 _tx_queue++) 1419 1420 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel) 1421 { 1422 return channel->rx_queue.core_index >= 0; 1423 } 1424 1425 static inline struct efx_rx_queue * 1426 efx_channel_get_rx_queue(struct efx_channel *channel) 1427 { 1428 EFX_WARN_ON_ONCE_PARANOID(!efx_channel_has_rx_queue(channel)); 1429 return &channel->rx_queue; 1430 } 1431 1432 /* Iterate over all RX queues belonging to a channel */ 1433 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ 1434 if (!efx_channel_has_rx_queue(_channel)) \ 1435 ; \ 1436 else \ 1437 for (_rx_queue = &(_channel)->rx_queue; \ 1438 _rx_queue; \ 1439 _rx_queue = NULL) 1440 1441 static inline struct efx_channel * 1442 efx_rx_queue_channel(struct efx_rx_queue *rx_queue) 1443 { 1444 return container_of(rx_queue, struct efx_channel, rx_queue); 1445 } 1446 1447 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) 1448 { 1449 return efx_rx_queue_channel(rx_queue)->channel; 1450 } 1451 1452 /* Returns a pointer to the specified receive buffer in the RX 1453 * descriptor queue. 1454 */ 1455 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, 1456 unsigned int index) 1457 { 1458 return &rx_queue->buffer[index]; 1459 } 1460 1461 /** 1462 * EFX_MAX_FRAME_LEN - calculate maximum frame length 1463 * 1464 * This calculates the maximum frame length that will be used for a 1465 * given MTU. The frame length will be equal to the MTU plus a 1466 * constant amount of header space and padding. This is the quantity 1467 * that the net driver will program into the MAC as the maximum frame 1468 * length. 1469 * 1470 * The 10G MAC requires 8-byte alignment on the frame 1471 * length, so we round up to the nearest 8. 1472 * 1473 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an 1474 * XGMII cycle). If the frame length reaches the maximum value in the 1475 * same cycle, the XMAC can miss the IPG altogether. We work around 1476 * this by adding a further 16 bytes. 1477 */ 1478 #define EFX_FRAME_PAD 16 1479 #define EFX_MAX_FRAME_LEN(mtu) \ 1480 (ALIGN(((mtu) + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN + EFX_FRAME_PAD), 8)) 1481 1482 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb) 1483 { 1484 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP; 1485 } 1486 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb) 1487 { 1488 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1489 } 1490 1491 /* Get all supported features. 1492 * If a feature is not fixed, it is present in hw_features. 1493 * If a feature is fixed, it does not present in hw_features, but 1494 * always in features. 1495 */ 1496 static inline netdev_features_t efx_supported_features(const struct efx_nic *efx) 1497 { 1498 const struct net_device *net_dev = efx->net_dev; 1499 1500 return net_dev->features | net_dev->hw_features; 1501 } 1502 1503 /* Get the current TX queue insert index. */ 1504 static inline unsigned int 1505 efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue) 1506 { 1507 return tx_queue->insert_count & tx_queue->ptr_mask; 1508 } 1509 1510 /* Get a TX buffer. */ 1511 static inline struct efx_tx_buffer * 1512 __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue) 1513 { 1514 return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)]; 1515 } 1516 1517 /* Get a TX buffer, checking it's not currently in use. */ 1518 static inline struct efx_tx_buffer * 1519 efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue) 1520 { 1521 struct efx_tx_buffer *buffer = 1522 __efx_tx_queue_get_insert_buffer(tx_queue); 1523 1524 EFX_WARN_ON_ONCE_PARANOID(buffer->len); 1525 EFX_WARN_ON_ONCE_PARANOID(buffer->flags); 1526 EFX_WARN_ON_ONCE_PARANOID(buffer->unmap_len); 1527 1528 return buffer; 1529 } 1530 1531 #endif /* EFX_NET_DRIVER_H */ 1532