1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 /* Common definitions for all Efx net driver code */ 12 13 #ifndef EFX_NET_DRIVER_H 14 #define EFX_NET_DRIVER_H 15 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/ethtool.h> 19 #include <linux/if_vlan.h> 20 #include <linux/timer.h> 21 #include <linux/mdio.h> 22 #include <linux/list.h> 23 #include <linux/pci.h> 24 #include <linux/device.h> 25 #include <linux/highmem.h> 26 #include <linux/workqueue.h> 27 #include <linux/mutex.h> 28 #include <linux/vmalloc.h> 29 #include <linux/i2c.h> 30 #include <linux/mtd/mtd.h> 31 32 #include "enum.h" 33 #include "bitfield.h" 34 #include "filter.h" 35 36 /************************************************************************** 37 * 38 * Build definitions 39 * 40 **************************************************************************/ 41 42 #define EFX_DRIVER_VERSION "4.0" 43 44 #ifdef DEBUG 45 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) 46 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) 47 #else 48 #define EFX_BUG_ON_PARANOID(x) do {} while (0) 49 #define EFX_WARN_ON_PARANOID(x) do {} while (0) 50 #endif 51 52 /************************************************************************** 53 * 54 * Efx data structures 55 * 56 **************************************************************************/ 57 58 #define EFX_MAX_CHANNELS 32U 59 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS 60 #define EFX_EXTRA_CHANNEL_IOV 0 61 #define EFX_EXTRA_CHANNEL_PTP 1 62 #define EFX_MAX_EXTRA_CHANNELS 2U 63 64 /* Checksum generation is a per-queue option in hardware, so each 65 * queue visible to the networking core is backed by two hardware TX 66 * queues. */ 67 #define EFX_MAX_TX_TC 2 68 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS) 69 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */ 70 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */ 71 #define EFX_TXQ_TYPES 4 72 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS) 73 74 /* Maximum possible MTU the driver supports */ 75 #define EFX_MAX_MTU (9 * 1024) 76 77 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page, 78 * and should be a multiple of the cache line size. 79 */ 80 #define EFX_RX_USR_BUF_SIZE (2048 - 256) 81 82 /* If possible, we should ensure cache line alignment at start and end 83 * of every buffer. Otherwise, we just need to ensure 4-byte 84 * alignment of the network header. 85 */ 86 #if NET_IP_ALIGN == 0 87 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES 88 #else 89 #define EFX_RX_BUF_ALIGNMENT 4 90 #endif 91 92 /* Forward declare Precision Time Protocol (PTP) support structure. */ 93 struct efx_ptp_data; 94 95 struct efx_self_tests; 96 97 /** 98 * struct efx_buffer - A general-purpose DMA buffer 99 * @addr: host base address of the buffer 100 * @dma_addr: DMA base address of the buffer 101 * @len: Buffer length, in bytes 102 * 103 * The NIC uses these buffers for its interrupt status registers and 104 * MAC stats dumps. 105 */ 106 struct efx_buffer { 107 void *addr; 108 dma_addr_t dma_addr; 109 unsigned int len; 110 }; 111 112 /** 113 * struct efx_special_buffer - DMA buffer entered into buffer table 114 * @buf: Standard &struct efx_buffer 115 * @index: Buffer index within controller;s buffer table 116 * @entries: Number of buffer table entries 117 * 118 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE. 119 * Event and descriptor rings are addressed via one or more buffer 120 * table entries (and so can be physically non-contiguous, although we 121 * currently do not take advantage of that). On Falcon and Siena we 122 * have to take care of allocating and initialising the entries 123 * ourselves. On later hardware this is managed by the firmware and 124 * @index and @entries are left as 0. 125 */ 126 struct efx_special_buffer { 127 struct efx_buffer buf; 128 unsigned int index; 129 unsigned int entries; 130 }; 131 132 /** 133 * struct efx_tx_buffer - buffer state for a TX descriptor 134 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be 135 * freed when descriptor completes 136 * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be 137 * freed when descriptor completes. 138 * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor. 139 * @dma_addr: DMA address of the fragment. 140 * @flags: Flags for allocation and DMA mapping type 141 * @len: Length of this fragment. 142 * This field is zero when the queue slot is empty. 143 * @unmap_len: Length of this fragment to unmap 144 */ 145 struct efx_tx_buffer { 146 union { 147 const struct sk_buff *skb; 148 void *heap_buf; 149 }; 150 union { 151 efx_qword_t option; 152 dma_addr_t dma_addr; 153 }; 154 unsigned short flags; 155 unsigned short len; 156 unsigned short unmap_len; 157 }; 158 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */ 159 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */ 160 #define EFX_TX_BUF_HEAP 4 /* buffer was allocated with kmalloc() */ 161 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */ 162 #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */ 163 164 /** 165 * struct efx_tx_queue - An Efx TX queue 166 * 167 * This is a ring buffer of TX fragments. 168 * Since the TX completion path always executes on the same 169 * CPU and the xmit path can operate on different CPUs, 170 * performance is increased by ensuring that the completion 171 * path and the xmit path operate on different cache lines. 172 * This is particularly important if the xmit path is always 173 * executing on one CPU which is different from the completion 174 * path. There is also a cache line for members which are 175 * read but not written on the fast path. 176 * 177 * @efx: The associated Efx NIC 178 * @queue: DMA queue number 179 * @channel: The associated channel 180 * @core_txq: The networking core TX queue structure 181 * @buffer: The software buffer ring 182 * @tsoh_page: Array of pages of TSO header buffers 183 * @txd: The hardware descriptor ring 184 * @ptr_mask: The size of the ring minus 1. 185 * @initialised: Has hardware queue been initialised? 186 * @read_count: Current read pointer. 187 * This is the number of buffers that have been removed from both rings. 188 * @old_write_count: The value of @write_count when last checked. 189 * This is here for performance reasons. The xmit path will 190 * only get the up-to-date value of @write_count if this 191 * variable indicates that the queue is empty. This is to 192 * avoid cache-line ping-pong between the xmit path and the 193 * completion path. 194 * @merge_events: Number of TX merged completion events 195 * @insert_count: Current insert pointer 196 * This is the number of buffers that have been added to the 197 * software ring. 198 * @write_count: Current write pointer 199 * This is the number of buffers that have been added to the 200 * hardware ring. 201 * @old_read_count: The value of read_count when last checked. 202 * This is here for performance reasons. The xmit path will 203 * only get the up-to-date value of read_count if this 204 * variable indicates that the queue is full. This is to 205 * avoid cache-line ping-pong between the xmit path and the 206 * completion path. 207 * @tso_bursts: Number of times TSO xmit invoked by kernel 208 * @tso_long_headers: Number of packets with headers too long for standard 209 * blocks 210 * @tso_packets: Number of packets via the TSO xmit path 211 * @pushes: Number of times the TX push feature has been used 212 * @empty_read_count: If the completion path has seen the queue as empty 213 * and the transmission path has not yet checked this, the value of 214 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0. 215 */ 216 struct efx_tx_queue { 217 /* Members which don't change on the fast path */ 218 struct efx_nic *efx ____cacheline_aligned_in_smp; 219 unsigned queue; 220 struct efx_channel *channel; 221 struct netdev_queue *core_txq; 222 struct efx_tx_buffer *buffer; 223 struct efx_buffer *tsoh_page; 224 struct efx_special_buffer txd; 225 unsigned int ptr_mask; 226 bool initialised; 227 228 /* Members used mainly on the completion path */ 229 unsigned int read_count ____cacheline_aligned_in_smp; 230 unsigned int old_write_count; 231 unsigned int merge_events; 232 233 /* Members used only on the xmit path */ 234 unsigned int insert_count ____cacheline_aligned_in_smp; 235 unsigned int write_count; 236 unsigned int old_read_count; 237 unsigned int tso_bursts; 238 unsigned int tso_long_headers; 239 unsigned int tso_packets; 240 unsigned int pushes; 241 242 /* Members shared between paths and sometimes updated */ 243 unsigned int empty_read_count ____cacheline_aligned_in_smp; 244 #define EFX_EMPTY_COUNT_VALID 0x80000000 245 atomic_t flush_outstanding; 246 }; 247 248 /** 249 * struct efx_rx_buffer - An Efx RX data buffer 250 * @dma_addr: DMA base address of the buffer 251 * @page: The associated page buffer. 252 * Will be %NULL if the buffer slot is currently free. 253 * @page_offset: If pending: offset in @page of DMA base address. 254 * If completed: offset in @page of Ethernet header. 255 * @len: If pending: length for DMA descriptor. 256 * If completed: received length, excluding hash prefix. 257 * @flags: Flags for buffer and packet state. These are only set on the 258 * first buffer of a scattered packet. 259 */ 260 struct efx_rx_buffer { 261 dma_addr_t dma_addr; 262 struct page *page; 263 u16 page_offset; 264 u16 len; 265 u16 flags; 266 }; 267 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001 268 #define EFX_RX_PKT_CSUMMED 0x0002 269 #define EFX_RX_PKT_DISCARD 0x0004 270 #define EFX_RX_PKT_TCP 0x0040 271 #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */ 272 273 /** 274 * struct efx_rx_page_state - Page-based rx buffer state 275 * 276 * Inserted at the start of every page allocated for receive buffers. 277 * Used to facilitate sharing dma mappings between recycled rx buffers 278 * and those passed up to the kernel. 279 * 280 * @refcnt: Number of struct efx_rx_buffer's referencing this page. 281 * When refcnt falls to zero, the page is unmapped for dma 282 * @dma_addr: The dma address of this page. 283 */ 284 struct efx_rx_page_state { 285 unsigned refcnt; 286 dma_addr_t dma_addr; 287 288 unsigned int __pad[0] ____cacheline_aligned; 289 }; 290 291 /** 292 * struct efx_rx_queue - An Efx RX queue 293 * @efx: The associated Efx NIC 294 * @core_index: Index of network core RX queue. Will be >= 0 iff this 295 * is associated with a real RX queue. 296 * @buffer: The software buffer ring 297 * @rxd: The hardware descriptor ring 298 * @ptr_mask: The size of the ring minus 1. 299 * @refill_enabled: Enable refill whenever fill level is low 300 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as 301 * @rxq_flush_pending. 302 * @added_count: Number of buffers added to the receive queue. 303 * @notified_count: Number of buffers given to NIC (<= @added_count). 304 * @removed_count: Number of buffers removed from the receive queue. 305 * @scatter_n: Used by NIC specific receive code. 306 * @scatter_len: Used by NIC specific receive code. 307 * @page_ring: The ring to store DMA mapped pages for reuse. 308 * @page_add: Counter to calculate the write pointer for the recycle ring. 309 * @page_remove: Counter to calculate the read pointer for the recycle ring. 310 * @page_recycle_count: The number of pages that have been recycled. 311 * @page_recycle_failed: The number of pages that couldn't be recycled because 312 * the kernel still held a reference to them. 313 * @page_recycle_full: The number of pages that were released because the 314 * recycle ring was full. 315 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1. 316 * @max_fill: RX descriptor maximum fill level (<= ring size) 317 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill 318 * (<= @max_fill) 319 * @min_fill: RX descriptor minimum non-zero fill level. 320 * This records the minimum fill level observed when a ring 321 * refill was triggered. 322 * @recycle_count: RX buffer recycle counter. 323 * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). 324 */ 325 struct efx_rx_queue { 326 struct efx_nic *efx; 327 int core_index; 328 struct efx_rx_buffer *buffer; 329 struct efx_special_buffer rxd; 330 unsigned int ptr_mask; 331 bool refill_enabled; 332 bool flush_pending; 333 334 unsigned int added_count; 335 unsigned int notified_count; 336 unsigned int removed_count; 337 unsigned int scatter_n; 338 unsigned int scatter_len; 339 struct page **page_ring; 340 unsigned int page_add; 341 unsigned int page_remove; 342 unsigned int page_recycle_count; 343 unsigned int page_recycle_failed; 344 unsigned int page_recycle_full; 345 unsigned int page_ptr_mask; 346 unsigned int max_fill; 347 unsigned int fast_fill_trigger; 348 unsigned int min_fill; 349 unsigned int min_overfill; 350 unsigned int recycle_count; 351 struct timer_list slow_fill; 352 unsigned int slow_fill_count; 353 }; 354 355 enum efx_rx_alloc_method { 356 RX_ALLOC_METHOD_AUTO = 0, 357 RX_ALLOC_METHOD_SKB = 1, 358 RX_ALLOC_METHOD_PAGE = 2, 359 }; 360 361 /** 362 * struct efx_channel - An Efx channel 363 * 364 * A channel comprises an event queue, at least one TX queue, at least 365 * one RX queue, and an associated tasklet for processing the event 366 * queue. 367 * 368 * @efx: Associated Efx NIC 369 * @channel: Channel instance number 370 * @type: Channel type definition 371 * @eventq_init: Event queue initialised flag 372 * @enabled: Channel enabled indicator 373 * @irq: IRQ number (MSI and MSI-X only) 374 * @irq_moderation: IRQ moderation value (in hardware ticks) 375 * @napi_dev: Net device used with NAPI 376 * @napi_str: NAPI control structure 377 * @eventq: Event queue buffer 378 * @eventq_mask: Event queue pointer mask 379 * @eventq_read_ptr: Event queue read pointer 380 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel 381 * @irq_count: Number of IRQs since last adaptive moderation decision 382 * @irq_mod_score: IRQ moderation score 383 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors 384 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors 385 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors 386 * @n_rx_mcast_mismatch: Count of unmatched multicast frames 387 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors 388 * @n_rx_overlength: Count of RX_OVERLENGTH errors 389 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun 390 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to 391 * lack of descriptors 392 * @n_rx_merge_events: Number of RX merged completion events 393 * @n_rx_merge_packets: Number of RX packets completed by merged events 394 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by 395 * __efx_rx_packet(), or zero if there is none 396 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered 397 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0 398 * @rx_queue: RX queue for this channel 399 * @tx_queue: TX queues for this channel 400 */ 401 struct efx_channel { 402 struct efx_nic *efx; 403 int channel; 404 const struct efx_channel_type *type; 405 bool eventq_init; 406 bool enabled; 407 int irq; 408 unsigned int irq_moderation; 409 struct net_device *napi_dev; 410 struct napi_struct napi_str; 411 struct efx_special_buffer eventq; 412 unsigned int eventq_mask; 413 unsigned int eventq_read_ptr; 414 int event_test_cpu; 415 416 unsigned int irq_count; 417 unsigned int irq_mod_score; 418 #ifdef CONFIG_RFS_ACCEL 419 unsigned int rfs_filters_added; 420 #endif 421 422 unsigned n_rx_tobe_disc; 423 unsigned n_rx_ip_hdr_chksum_err; 424 unsigned n_rx_tcp_udp_chksum_err; 425 unsigned n_rx_mcast_mismatch; 426 unsigned n_rx_frm_trunc; 427 unsigned n_rx_overlength; 428 unsigned n_skbuff_leaks; 429 unsigned int n_rx_nodesc_trunc; 430 unsigned int n_rx_merge_events; 431 unsigned int n_rx_merge_packets; 432 433 unsigned int rx_pkt_n_frags; 434 unsigned int rx_pkt_index; 435 436 struct efx_rx_queue rx_queue; 437 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES]; 438 }; 439 440 /** 441 * struct efx_msi_context - Context for each MSI 442 * @efx: The associated NIC 443 * @index: Index of the channel/IRQ 444 * @name: Name of the channel/IRQ 445 * 446 * Unlike &struct efx_channel, this is never reallocated and is always 447 * safe for the IRQ handler to access. 448 */ 449 struct efx_msi_context { 450 struct efx_nic *efx; 451 unsigned int index; 452 char name[IFNAMSIZ + 6]; 453 }; 454 455 /** 456 * struct efx_channel_type - distinguishes traffic and extra channels 457 * @handle_no_channel: Handle failure to allocate an extra channel 458 * @pre_probe: Set up extra state prior to initialisation 459 * @post_remove: Tear down extra state after finalisation, if allocated. 460 * May be called on channels that have not been probed. 461 * @get_name: Generate the channel's name (used for its IRQ handler) 462 * @copy: Copy the channel state prior to reallocation. May be %NULL if 463 * reallocation is not supported. 464 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb() 465 * @keep_eventq: Flag for whether event queue should be kept initialised 466 * while the device is stopped 467 */ 468 struct efx_channel_type { 469 void (*handle_no_channel)(struct efx_nic *); 470 int (*pre_probe)(struct efx_channel *); 471 void (*post_remove)(struct efx_channel *); 472 void (*get_name)(struct efx_channel *, char *buf, size_t len); 473 struct efx_channel *(*copy)(const struct efx_channel *); 474 bool (*receive_skb)(struct efx_channel *, struct sk_buff *); 475 bool keep_eventq; 476 }; 477 478 enum efx_led_mode { 479 EFX_LED_OFF = 0, 480 EFX_LED_ON = 1, 481 EFX_LED_DEFAULT = 2 482 }; 483 484 #define STRING_TABLE_LOOKUP(val, member) \ 485 ((val) < member ## _max) ? member ## _names[val] : "(invalid)" 486 487 extern const char *const efx_loopback_mode_names[]; 488 extern const unsigned int efx_loopback_mode_max; 489 #define LOOPBACK_MODE(efx) \ 490 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) 491 492 extern const char *const efx_reset_type_names[]; 493 extern const unsigned int efx_reset_type_max; 494 #define RESET_TYPE(type) \ 495 STRING_TABLE_LOOKUP(type, efx_reset_type) 496 497 enum efx_int_mode { 498 /* Be careful if altering to correct macro below */ 499 EFX_INT_MODE_MSIX = 0, 500 EFX_INT_MODE_MSI = 1, 501 EFX_INT_MODE_LEGACY = 2, 502 EFX_INT_MODE_MAX /* Insert any new items before this */ 503 }; 504 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) 505 506 enum nic_state { 507 STATE_UNINIT = 0, /* device being probed/removed or is frozen */ 508 STATE_READY = 1, /* hardware ready and netdev registered */ 509 STATE_DISABLED = 2, /* device disabled due to hardware errors */ 510 STATE_RECOVERY = 3, /* device recovering from PCI error */ 511 }; 512 513 /* 514 * Alignment of the skb->head which wraps a page-allocated RX buffer 515 * 516 * The skb allocated to wrap an rx_buffer can have this alignment. Since 517 * the data is memcpy'd from the rx_buf, it does not need to be equal to 518 * NET_IP_ALIGN. 519 */ 520 #define EFX_PAGE_SKB_ALIGN 2 521 522 /* Forward declaration */ 523 struct efx_nic; 524 525 /* Pseudo bit-mask flow control field */ 526 #define EFX_FC_RX FLOW_CTRL_RX 527 #define EFX_FC_TX FLOW_CTRL_TX 528 #define EFX_FC_AUTO 4 529 530 /** 531 * struct efx_link_state - Current state of the link 532 * @up: Link is up 533 * @fd: Link is full-duplex 534 * @fc: Actual flow control flags 535 * @speed: Link speed (Mbps) 536 */ 537 struct efx_link_state { 538 bool up; 539 bool fd; 540 u8 fc; 541 unsigned int speed; 542 }; 543 544 static inline bool efx_link_state_equal(const struct efx_link_state *left, 545 const struct efx_link_state *right) 546 { 547 return left->up == right->up && left->fd == right->fd && 548 left->fc == right->fc && left->speed == right->speed; 549 } 550 551 /** 552 * struct efx_phy_operations - Efx PHY operations table 553 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, 554 * efx->loopback_modes. 555 * @init: Initialise PHY 556 * @fini: Shut down PHY 557 * @reconfigure: Reconfigure PHY (e.g. for new link parameters) 558 * @poll: Update @link_state and report whether it changed. 559 * Serialised by the mac_lock. 560 * @get_settings: Get ethtool settings. Serialised by the mac_lock. 561 * @set_settings: Set ethtool settings. Serialised by the mac_lock. 562 * @set_npage_adv: Set abilities advertised in (Extended) Next Page 563 * (only needed where AN bit is set in mmds) 564 * @test_alive: Test that PHY is 'alive' (online) 565 * @test_name: Get the name of a PHY-specific test/result 566 * @run_tests: Run tests and record results as appropriate (offline). 567 * Flags are the ethtool tests flags. 568 */ 569 struct efx_phy_operations { 570 int (*probe) (struct efx_nic *efx); 571 int (*init) (struct efx_nic *efx); 572 void (*fini) (struct efx_nic *efx); 573 void (*remove) (struct efx_nic *efx); 574 int (*reconfigure) (struct efx_nic *efx); 575 bool (*poll) (struct efx_nic *efx); 576 void (*get_settings) (struct efx_nic *efx, 577 struct ethtool_cmd *ecmd); 578 int (*set_settings) (struct efx_nic *efx, 579 struct ethtool_cmd *ecmd); 580 void (*set_npage_adv) (struct efx_nic *efx, u32); 581 int (*test_alive) (struct efx_nic *efx); 582 const char *(*test_name) (struct efx_nic *efx, unsigned int index); 583 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); 584 int (*get_module_eeprom) (struct efx_nic *efx, 585 struct ethtool_eeprom *ee, 586 u8 *data); 587 int (*get_module_info) (struct efx_nic *efx, 588 struct ethtool_modinfo *modinfo); 589 }; 590 591 /** 592 * enum efx_phy_mode - PHY operating mode flags 593 * @PHY_MODE_NORMAL: on and should pass traffic 594 * @PHY_MODE_TX_DISABLED: on with TX disabled 595 * @PHY_MODE_LOW_POWER: set to low power through MDIO 596 * @PHY_MODE_OFF: switched off through external control 597 * @PHY_MODE_SPECIAL: on but will not pass traffic 598 */ 599 enum efx_phy_mode { 600 PHY_MODE_NORMAL = 0, 601 PHY_MODE_TX_DISABLED = 1, 602 PHY_MODE_LOW_POWER = 2, 603 PHY_MODE_OFF = 4, 604 PHY_MODE_SPECIAL = 8, 605 }; 606 607 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) 608 { 609 return !!(mode & ~PHY_MODE_TX_DISABLED); 610 } 611 612 /** 613 * struct efx_hw_stat_desc - Description of a hardware statistic 614 * @name: Name of the statistic as visible through ethtool, or %NULL if 615 * it should not be exposed 616 * @dma_width: Width in bits (0 for non-DMA statistics) 617 * @offset: Offset within stats (ignored for non-DMA statistics) 618 */ 619 struct efx_hw_stat_desc { 620 const char *name; 621 u16 dma_width; 622 u16 offset; 623 }; 624 625 /* Number of bits used in a multicast filter hash address */ 626 #define EFX_MCAST_HASH_BITS 8 627 628 /* Number of (single-bit) entries in a multicast filter hash */ 629 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) 630 631 /* An Efx multicast filter hash */ 632 union efx_multicast_hash { 633 u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; 634 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; 635 }; 636 637 struct efx_vf; 638 struct vfdi_status; 639 640 /** 641 * struct efx_nic - an Efx NIC 642 * @name: Device name (net device name or bus id before net device registered) 643 * @pci_dev: The PCI device 644 * @type: Controller type attributes 645 * @legacy_irq: IRQ number 646 * @workqueue: Workqueue for port reconfigures and the HW monitor. 647 * Work items do not hold and must not acquire RTNL. 648 * @workqueue_name: Name of workqueue 649 * @reset_work: Scheduled reset workitem 650 * @membase_phys: Memory BAR value as physical address 651 * @membase: Memory BAR value 652 * @interrupt_mode: Interrupt mode 653 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds 654 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues 655 * @irq_rx_moderation: IRQ moderation time for RX event queues 656 * @msg_enable: Log message enable flags 657 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock. 658 * @reset_pending: Bitmask for pending resets 659 * @tx_queue: TX DMA queues 660 * @rx_queue: RX DMA queues 661 * @channel: Channels 662 * @msi_context: Context for each MSI 663 * @extra_channel_types: Types of extra (non-traffic) channels that 664 * should be allocated for this NIC 665 * @rxq_entries: Size of receive queues requested by user. 666 * @txq_entries: Size of transmit queues requested by user. 667 * @txq_stop_thresh: TX queue fill level at or above which we stop it. 668 * @txq_wake_thresh: TX queue fill level at or below which we wake it. 669 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches 670 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches 671 * @sram_lim_qw: Qword address limit of SRAM 672 * @next_buffer_table: First available buffer table id 673 * @n_channels: Number of channels in use 674 * @n_rx_channels: Number of channels used for RX (= number of RX queues) 675 * @n_tx_channels: Number of channels used for TX 676 * @rx_dma_len: Current maximum RX DMA length 677 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer 678 * @rx_buffer_truesize: Amortised allocation size of an RX buffer, 679 * for use in sk_buff::truesize 680 * @rx_prefix_size: Size of RX prefix before packet data 681 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data 682 * (valid only if @rx_prefix_size != 0; always negative) 683 * @rx_packet_len_offset: Offset of RX packet length from start of packet data 684 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative) 685 * @rx_hash_key: Toeplitz hash key for RSS 686 * @rx_indir_table: Indirection table for RSS 687 * @rx_scatter: Scatter mode enabled for receives 688 * @int_error_count: Number of internal errors seen recently 689 * @int_error_expire: Time at which error count will be expired 690 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will 691 * acknowledge but do nothing else. 692 * @irq_status: Interrupt status buffer 693 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 694 * @irq_level: IRQ level/index for IRQs not triggered by an event queue 695 * @selftest_work: Work item for asynchronous self-test 696 * @mtd_list: List of MTDs attached to the NIC 697 * @nic_data: Hardware dependent state 698 * @mcdi: Management-Controller-to-Driver Interface state 699 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, 700 * efx_monitor() and efx_reconfigure_port() 701 * @port_enabled: Port enabled indicator. 702 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and 703 * efx_mac_work() with kernel interfaces. Safe to read under any 704 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must 705 * be held to modify it. 706 * @port_initialized: Port initialized? 707 * @net_dev: Operating system network device. Consider holding the rtnl lock 708 * @stats_buffer: DMA buffer for statistics 709 * @phy_type: PHY type 710 * @phy_op: PHY interface 711 * @phy_data: PHY private data (including PHY-specific stats) 712 * @mdio: PHY MDIO interface 713 * @mdio_bus: PHY MDIO bus ID (only used by Siena) 714 * @phy_mode: PHY operating mode. Serialised by @mac_lock. 715 * @link_advertising: Autonegotiation advertising flags 716 * @link_state: Current state of the link 717 * @n_link_state_changes: Number of times the link has changed state 718 * @unicast_filter: Flag for Falcon-arch simple unicast filter. 719 * Protected by @mac_lock. 720 * @multicast_hash: Multicast hash table for Falcon-arch. 721 * Protected by @mac_lock. 722 * @wanted_fc: Wanted flow control flags 723 * @fc_disable: When non-zero flow control is disabled. Typically used to 724 * ensure that network back pressure doesn't delay dma queue flushes. 725 * Serialised by the rtnl lock. 726 * @mac_work: Work item for changing MAC promiscuity and multicast hash 727 * @loopback_mode: Loopback status 728 * @loopback_modes: Supported loopback mode bitmask 729 * @loopback_selftest: Offline self-test private state 730 * @filter_lock: Filter table lock 731 * @filter_state: Architecture-dependent filter table state 732 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS, 733 * indexed by filter ID 734 * @rps_expire_index: Next index to check for expiry in @rps_flow_id 735 * @active_queues: Count of RX and TX queues that haven't been flushed and drained. 736 * @rxq_flush_pending: Count of number of receive queues that need to be flushed. 737 * Decremented when the efx_flush_rx_queue() is called. 738 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet 739 * completed (either success or failure). Not used when MCDI is used to 740 * flush receive queues. 741 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions. 742 * @vf: Array of &struct efx_vf objects. 743 * @vf_count: Number of VFs intended to be enabled. 744 * @vf_init_count: Number of VFs that have been fully initialised. 745 * @vi_scale: log2 number of vnics per VF. 746 * @vf_buftbl_base: The zeroth buffer table index used to back VF queues. 747 * @vfdi_status: Common VFDI status page to be dmad to VF address space. 748 * @local_addr_list: List of local addresses. Protected by %local_lock. 749 * @local_page_list: List of DMA addressable pages used to broadcast 750 * %local_addr_list. Protected by %local_lock. 751 * @local_lock: Mutex protecting %local_addr_list and %local_page_list. 752 * @peer_work: Work item to broadcast peer addresses to VMs. 753 * @ptp_data: PTP state data 754 * @monitor_work: Hardware monitor workitem 755 * @biu_lock: BIU (bus interface unit) lock 756 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This 757 * field is used by efx_test_interrupts() to verify that an 758 * interrupt has occurred. 759 * @stats_lock: Statistics update lock. Must be held when calling 760 * efx_nic_type::{update,start,stop}_stats. 761 * 762 * This is stored in the private area of the &struct net_device. 763 */ 764 struct efx_nic { 765 /* The following fields should be written very rarely */ 766 767 char name[IFNAMSIZ]; 768 struct pci_dev *pci_dev; 769 unsigned int port_num; 770 const struct efx_nic_type *type; 771 int legacy_irq; 772 bool eeh_disabled_legacy_irq; 773 struct workqueue_struct *workqueue; 774 char workqueue_name[16]; 775 struct work_struct reset_work; 776 resource_size_t membase_phys; 777 void __iomem *membase; 778 779 enum efx_int_mode interrupt_mode; 780 unsigned int timer_quantum_ns; 781 bool irq_rx_adaptive; 782 unsigned int irq_rx_moderation; 783 u32 msg_enable; 784 785 enum nic_state state; 786 unsigned long reset_pending; 787 788 struct efx_channel *channel[EFX_MAX_CHANNELS]; 789 struct efx_msi_context msi_context[EFX_MAX_CHANNELS]; 790 const struct efx_channel_type * 791 extra_channel_type[EFX_MAX_EXTRA_CHANNELS]; 792 793 unsigned rxq_entries; 794 unsigned txq_entries; 795 unsigned int txq_stop_thresh; 796 unsigned int txq_wake_thresh; 797 798 unsigned tx_dc_base; 799 unsigned rx_dc_base; 800 unsigned sram_lim_qw; 801 unsigned next_buffer_table; 802 803 unsigned int max_channels; 804 unsigned n_channels; 805 unsigned n_rx_channels; 806 unsigned rss_spread; 807 unsigned tx_channel_offset; 808 unsigned n_tx_channels; 809 unsigned int rx_dma_len; 810 unsigned int rx_buffer_order; 811 unsigned int rx_buffer_truesize; 812 unsigned int rx_page_buf_step; 813 unsigned int rx_bufs_per_page; 814 unsigned int rx_pages_per_batch; 815 unsigned int rx_prefix_size; 816 int rx_packet_hash_offset; 817 int rx_packet_len_offset; 818 u8 rx_hash_key[40]; 819 u32 rx_indir_table[128]; 820 bool rx_scatter; 821 822 unsigned int_error_count; 823 unsigned long int_error_expire; 824 825 bool irq_soft_enabled; 826 struct efx_buffer irq_status; 827 unsigned irq_zero_count; 828 unsigned irq_level; 829 struct delayed_work selftest_work; 830 831 #ifdef CONFIG_SFC_MTD 832 struct list_head mtd_list; 833 #endif 834 835 void *nic_data; 836 struct efx_mcdi_data *mcdi; 837 838 struct mutex mac_lock; 839 struct work_struct mac_work; 840 bool port_enabled; 841 842 bool port_initialized; 843 struct net_device *net_dev; 844 845 struct efx_buffer stats_buffer; 846 847 unsigned int phy_type; 848 const struct efx_phy_operations *phy_op; 849 void *phy_data; 850 struct mdio_if_info mdio; 851 unsigned int mdio_bus; 852 enum efx_phy_mode phy_mode; 853 854 u32 link_advertising; 855 struct efx_link_state link_state; 856 unsigned int n_link_state_changes; 857 858 bool unicast_filter; 859 union efx_multicast_hash multicast_hash; 860 u8 wanted_fc; 861 unsigned fc_disable; 862 863 atomic_t rx_reset; 864 enum efx_loopback_mode loopback_mode; 865 u64 loopback_modes; 866 867 void *loopback_selftest; 868 869 spinlock_t filter_lock; 870 void *filter_state; 871 #ifdef CONFIG_RFS_ACCEL 872 u32 *rps_flow_id; 873 unsigned int rps_expire_index; 874 #endif 875 876 atomic_t active_queues; 877 atomic_t rxq_flush_pending; 878 atomic_t rxq_flush_outstanding; 879 wait_queue_head_t flush_wq; 880 881 #ifdef CONFIG_SFC_SRIOV 882 struct efx_channel *vfdi_channel; 883 struct efx_vf *vf; 884 unsigned vf_count; 885 unsigned vf_init_count; 886 unsigned vi_scale; 887 unsigned vf_buftbl_base; 888 struct efx_buffer vfdi_status; 889 struct list_head local_addr_list; 890 struct list_head local_page_list; 891 struct mutex local_lock; 892 struct work_struct peer_work; 893 #endif 894 895 struct efx_ptp_data *ptp_data; 896 897 /* The following fields may be written more often */ 898 899 struct delayed_work monitor_work ____cacheline_aligned_in_smp; 900 spinlock_t biu_lock; 901 int last_irq_cpu; 902 spinlock_t stats_lock; 903 }; 904 905 static inline int efx_dev_registered(struct efx_nic *efx) 906 { 907 return efx->net_dev->reg_state == NETREG_REGISTERED; 908 } 909 910 static inline unsigned int efx_port_num(struct efx_nic *efx) 911 { 912 return efx->port_num; 913 } 914 915 struct efx_mtd_partition { 916 struct list_head node; 917 struct mtd_info mtd; 918 const char *dev_type_name; 919 const char *type_name; 920 char name[IFNAMSIZ + 20]; 921 }; 922 923 /** 924 * struct efx_nic_type - Efx device type definition 925 * @mem_map_size: Get memory BAR mapped size 926 * @probe: Probe the controller 927 * @remove: Free resources allocated by probe() 928 * @init: Initialise the controller 929 * @dimension_resources: Dimension controller resources (buffer table, 930 * and VIs once the available interrupt resources are clear) 931 * @fini: Shut down the controller 932 * @monitor: Periodic function for polling link state and hardware monitor 933 * @map_reset_reason: Map ethtool reset reason to a reset method 934 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible 935 * @reset: Reset the controller hardware and possibly the PHY. This will 936 * be called while the controller is uninitialised. 937 * @probe_port: Probe the MAC and PHY 938 * @remove_port: Free resources allocated by probe_port() 939 * @handle_global_event: Handle a "global" event (may be %NULL) 940 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues) 941 * @prepare_flush: Prepare the hardware for flushing the DMA queues 942 * (for Falcon architecture) 943 * @finish_flush: Clean up after flushing the DMA queues (for Falcon 944 * architecture) 945 * @describe_stats: Describe statistics for ethtool 946 * @update_stats: Update statistics not provided by event handling. 947 * Either argument may be %NULL. 948 * @start_stats: Start the regular fetching of statistics 949 * @stop_stats: Stop the regular fetching of statistics 950 * @set_id_led: Set state of identifying LED or revert to automatic function 951 * @push_irq_moderation: Apply interrupt moderation value 952 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY 953 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL) 954 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings 955 * to the hardware. Serialised by the mac_lock. 956 * @check_mac_fault: Check MAC fault state. True if fault present. 957 * @get_wol: Get WoL configuration from driver state 958 * @set_wol: Push WoL configuration to the NIC 959 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) 960 * @test_chip: Test registers. May use efx_farch_test_registers(), and is 961 * expected to reset the NIC. 962 * @test_nvram: Test validity of NVRAM contents 963 * @mcdi_request: Send an MCDI request with the given header and SDU. 964 * The SDU length may be any value from 0 up to the protocol- 965 * defined maximum, but its buffer will be padded to a multiple 966 * of 4 bytes. 967 * @mcdi_poll_response: Test whether an MCDI response is available. 968 * @mcdi_read_response: Read the MCDI response PDU. The offset will 969 * be a multiple of 4. The length may not be, but the buffer 970 * will be padded so it is safe to round up. 971 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so, 972 * return an appropriate error code for aborting any current 973 * request; otherwise return 0. 974 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must 975 * be separately enabled after this. 976 * @irq_test_generate: Generate a test IRQ 977 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event 978 * queue must be separately disabled before this. 979 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is 980 * a pointer to the &struct efx_msi_context for the channel. 981 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument 982 * is a pointer to the &struct efx_nic. 983 * @tx_probe: Allocate resources for TX queue 984 * @tx_init: Initialise TX queue on the NIC 985 * @tx_remove: Free resources for TX queue 986 * @tx_write: Write TX descriptors and doorbell 987 * @rx_push_indir_table: Write RSS indirection table to the NIC 988 * @rx_probe: Allocate resources for RX queue 989 * @rx_init: Initialise RX queue on the NIC 990 * @rx_remove: Free resources for RX queue 991 * @rx_write: Write RX descriptors and doorbell 992 * @rx_defer_refill: Generate a refill reminder event 993 * @ev_probe: Allocate resources for event queue 994 * @ev_init: Initialise event queue on the NIC 995 * @ev_fini: Deinitialise event queue on the NIC 996 * @ev_remove: Free resources for event queue 997 * @ev_process: Process events for a queue, up to the given NAPI quota 998 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ 999 * @ev_test_generate: Generate a test event 1000 * @filter_table_probe: Probe filter capabilities and set up filter software state 1001 * @filter_table_restore: Restore filters removed from hardware 1002 * @filter_table_remove: Remove filters from hardware and tear down software state 1003 * @filter_update_rx_scatter: Update filters after change to rx scatter setting 1004 * @filter_insert: add or replace a filter 1005 * @filter_remove_safe: remove a filter by ID, carefully 1006 * @filter_get_safe: retrieve a filter by ID, carefully 1007 * @filter_clear_rx: remove RX filters by priority 1008 * @filter_count_rx_used: Get the number of filters in use at a given priority 1009 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1 1010 * @filter_get_rx_ids: Get list of RX filters at a given priority 1011 * @filter_rfs_insert: Add or replace a filter for RFS. This must be 1012 * atomic. The hardware change may be asynchronous but should 1013 * not be delayed for long. It may fail if this can't be done 1014 * atomically. 1015 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS. 1016 * This must check whether the specified table entry is used by RFS 1017 * and that rps_may_expire_flow() returns true for it. 1018 * @mtd_probe: Probe and add MTD partitions associated with this net device, 1019 * using efx_mtd_add() 1020 * @mtd_rename: Set an MTD partition name using the net device name 1021 * @mtd_read: Read from an MTD partition 1022 * @mtd_erase: Erase part of an MTD partition 1023 * @mtd_write: Write to an MTD partition 1024 * @mtd_sync: Wait for write-back to complete on MTD partition. This 1025 * also notifies the driver that a writer has finished using this 1026 * partition. 1027 * @revision: Hardware architecture revision 1028 * @txd_ptr_tbl_base: TX descriptor ring base address 1029 * @rxd_ptr_tbl_base: RX descriptor ring base address 1030 * @buf_tbl_base: Buffer table base address 1031 * @evq_ptr_tbl_base: Event queue pointer table base address 1032 * @evq_rptr_tbl_base: Event queue read-pointer table base address 1033 * @max_dma_mask: Maximum possible DMA mask 1034 * @rx_prefix_size: Size of RX prefix before packet data 1035 * @rx_hash_offset: Offset of RX flow hash within prefix 1036 * @rx_buffer_padding: Size of padding at end of RX packet 1037 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers 1038 * @always_rx_scatter: NIC will always scatter packets to multiple buffers 1039 * @max_interrupt_mode: Highest capability interrupt mode supported 1040 * from &enum efx_init_mode. 1041 * @timer_period_max: Maximum period of interrupt timer (in ticks) 1042 * @offload_features: net_device feature flags for protocol offload 1043 * features implemented in hardware 1044 * @mcdi_max_ver: Maximum MCDI version supported 1045 */ 1046 struct efx_nic_type { 1047 unsigned int (*mem_map_size)(struct efx_nic *efx); 1048 int (*probe)(struct efx_nic *efx); 1049 void (*remove)(struct efx_nic *efx); 1050 int (*init)(struct efx_nic *efx); 1051 int (*dimension_resources)(struct efx_nic *efx); 1052 void (*fini)(struct efx_nic *efx); 1053 void (*monitor)(struct efx_nic *efx); 1054 enum reset_type (*map_reset_reason)(enum reset_type reason); 1055 int (*map_reset_flags)(u32 *flags); 1056 int (*reset)(struct efx_nic *efx, enum reset_type method); 1057 int (*probe_port)(struct efx_nic *efx); 1058 void (*remove_port)(struct efx_nic *efx); 1059 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *); 1060 int (*fini_dmaq)(struct efx_nic *efx); 1061 void (*prepare_flush)(struct efx_nic *efx); 1062 void (*finish_flush)(struct efx_nic *efx); 1063 size_t (*describe_stats)(struct efx_nic *efx, u8 *names); 1064 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats, 1065 struct rtnl_link_stats64 *core_stats); 1066 void (*start_stats)(struct efx_nic *efx); 1067 void (*stop_stats)(struct efx_nic *efx); 1068 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); 1069 void (*push_irq_moderation)(struct efx_channel *channel); 1070 int (*reconfigure_port)(struct efx_nic *efx); 1071 void (*prepare_enable_fc_tx)(struct efx_nic *efx); 1072 int (*reconfigure_mac)(struct efx_nic *efx); 1073 bool (*check_mac_fault)(struct efx_nic *efx); 1074 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); 1075 int (*set_wol)(struct efx_nic *efx, u32 type); 1076 void (*resume_wol)(struct efx_nic *efx); 1077 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests); 1078 int (*test_nvram)(struct efx_nic *efx); 1079 void (*mcdi_request)(struct efx_nic *efx, 1080 const efx_dword_t *hdr, size_t hdr_len, 1081 const efx_dword_t *sdu, size_t sdu_len); 1082 bool (*mcdi_poll_response)(struct efx_nic *efx); 1083 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu, 1084 size_t pdu_offset, size_t pdu_len); 1085 int (*mcdi_poll_reboot)(struct efx_nic *efx); 1086 void (*irq_enable_master)(struct efx_nic *efx); 1087 void (*irq_test_generate)(struct efx_nic *efx); 1088 void (*irq_disable_non_ev)(struct efx_nic *efx); 1089 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id); 1090 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id); 1091 int (*tx_probe)(struct efx_tx_queue *tx_queue); 1092 void (*tx_init)(struct efx_tx_queue *tx_queue); 1093 void (*tx_remove)(struct efx_tx_queue *tx_queue); 1094 void (*tx_write)(struct efx_tx_queue *tx_queue); 1095 void (*rx_push_indir_table)(struct efx_nic *efx); 1096 int (*rx_probe)(struct efx_rx_queue *rx_queue); 1097 void (*rx_init)(struct efx_rx_queue *rx_queue); 1098 void (*rx_remove)(struct efx_rx_queue *rx_queue); 1099 void (*rx_write)(struct efx_rx_queue *rx_queue); 1100 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue); 1101 int (*ev_probe)(struct efx_channel *channel); 1102 int (*ev_init)(struct efx_channel *channel); 1103 void (*ev_fini)(struct efx_channel *channel); 1104 void (*ev_remove)(struct efx_channel *channel); 1105 int (*ev_process)(struct efx_channel *channel, int quota); 1106 void (*ev_read_ack)(struct efx_channel *channel); 1107 void (*ev_test_generate)(struct efx_channel *channel); 1108 int (*filter_table_probe)(struct efx_nic *efx); 1109 void (*filter_table_restore)(struct efx_nic *efx); 1110 void (*filter_table_remove)(struct efx_nic *efx); 1111 void (*filter_update_rx_scatter)(struct efx_nic *efx); 1112 s32 (*filter_insert)(struct efx_nic *efx, 1113 struct efx_filter_spec *spec, bool replace); 1114 int (*filter_remove_safe)(struct efx_nic *efx, 1115 enum efx_filter_priority priority, 1116 u32 filter_id); 1117 int (*filter_get_safe)(struct efx_nic *efx, 1118 enum efx_filter_priority priority, 1119 u32 filter_id, struct efx_filter_spec *); 1120 void (*filter_clear_rx)(struct efx_nic *efx, 1121 enum efx_filter_priority priority); 1122 u32 (*filter_count_rx_used)(struct efx_nic *efx, 1123 enum efx_filter_priority priority); 1124 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx); 1125 s32 (*filter_get_rx_ids)(struct efx_nic *efx, 1126 enum efx_filter_priority priority, 1127 u32 *buf, u32 size); 1128 #ifdef CONFIG_RFS_ACCEL 1129 s32 (*filter_rfs_insert)(struct efx_nic *efx, 1130 struct efx_filter_spec *spec); 1131 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id, 1132 unsigned int index); 1133 #endif 1134 #ifdef CONFIG_SFC_MTD 1135 int (*mtd_probe)(struct efx_nic *efx); 1136 void (*mtd_rename)(struct efx_mtd_partition *part); 1137 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len, 1138 size_t *retlen, u8 *buffer); 1139 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len); 1140 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len, 1141 size_t *retlen, const u8 *buffer); 1142 int (*mtd_sync)(struct mtd_info *mtd); 1143 #endif 1144 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time); 1145 1146 int revision; 1147 unsigned int txd_ptr_tbl_base; 1148 unsigned int rxd_ptr_tbl_base; 1149 unsigned int buf_tbl_base; 1150 unsigned int evq_ptr_tbl_base; 1151 unsigned int evq_rptr_tbl_base; 1152 u64 max_dma_mask; 1153 unsigned int rx_prefix_size; 1154 unsigned int rx_hash_offset; 1155 unsigned int rx_buffer_padding; 1156 bool can_rx_scatter; 1157 bool always_rx_scatter; 1158 unsigned int max_interrupt_mode; 1159 unsigned int timer_period_max; 1160 netdev_features_t offload_features; 1161 int mcdi_max_ver; 1162 unsigned int max_rx_ip_filters; 1163 }; 1164 1165 /************************************************************************** 1166 * 1167 * Prototypes and inline functions 1168 * 1169 *************************************************************************/ 1170 1171 static inline struct efx_channel * 1172 efx_get_channel(struct efx_nic *efx, unsigned index) 1173 { 1174 EFX_BUG_ON_PARANOID(index >= efx->n_channels); 1175 return efx->channel[index]; 1176 } 1177 1178 /* Iterate over all used channels */ 1179 #define efx_for_each_channel(_channel, _efx) \ 1180 for (_channel = (_efx)->channel[0]; \ 1181 _channel; \ 1182 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ 1183 (_efx)->channel[_channel->channel + 1] : NULL) 1184 1185 /* Iterate over all used channels in reverse */ 1186 #define efx_for_each_channel_rev(_channel, _efx) \ 1187 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \ 1188 _channel; \ 1189 _channel = _channel->channel ? \ 1190 (_efx)->channel[_channel->channel - 1] : NULL) 1191 1192 static inline struct efx_tx_queue * 1193 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) 1194 { 1195 EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels || 1196 type >= EFX_TXQ_TYPES); 1197 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type]; 1198 } 1199 1200 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel) 1201 { 1202 return channel->channel - channel->efx->tx_channel_offset < 1203 channel->efx->n_tx_channels; 1204 } 1205 1206 static inline struct efx_tx_queue * 1207 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type) 1208 { 1209 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) || 1210 type >= EFX_TXQ_TYPES); 1211 return &channel->tx_queue[type]; 1212 } 1213 1214 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue) 1215 { 1216 return !(tx_queue->efx->net_dev->num_tc < 2 && 1217 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI); 1218 } 1219 1220 /* Iterate over all TX queues belonging to a channel */ 1221 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ 1222 if (!efx_channel_has_tx_queues(_channel)) \ 1223 ; \ 1224 else \ 1225 for (_tx_queue = (_channel)->tx_queue; \ 1226 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \ 1227 efx_tx_queue_used(_tx_queue); \ 1228 _tx_queue++) 1229 1230 /* Iterate over all possible TX queues belonging to a channel */ 1231 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \ 1232 if (!efx_channel_has_tx_queues(_channel)) \ 1233 ; \ 1234 else \ 1235 for (_tx_queue = (_channel)->tx_queue; \ 1236 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ 1237 _tx_queue++) 1238 1239 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel) 1240 { 1241 return channel->rx_queue.core_index >= 0; 1242 } 1243 1244 static inline struct efx_rx_queue * 1245 efx_channel_get_rx_queue(struct efx_channel *channel) 1246 { 1247 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel)); 1248 return &channel->rx_queue; 1249 } 1250 1251 /* Iterate over all RX queues belonging to a channel */ 1252 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ 1253 if (!efx_channel_has_rx_queue(_channel)) \ 1254 ; \ 1255 else \ 1256 for (_rx_queue = &(_channel)->rx_queue; \ 1257 _rx_queue; \ 1258 _rx_queue = NULL) 1259 1260 static inline struct efx_channel * 1261 efx_rx_queue_channel(struct efx_rx_queue *rx_queue) 1262 { 1263 return container_of(rx_queue, struct efx_channel, rx_queue); 1264 } 1265 1266 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) 1267 { 1268 return efx_rx_queue_channel(rx_queue)->channel; 1269 } 1270 1271 /* Returns a pointer to the specified receive buffer in the RX 1272 * descriptor queue. 1273 */ 1274 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, 1275 unsigned int index) 1276 { 1277 return &rx_queue->buffer[index]; 1278 } 1279 1280 1281 /** 1282 * EFX_MAX_FRAME_LEN - calculate maximum frame length 1283 * 1284 * This calculates the maximum frame length that will be used for a 1285 * given MTU. The frame length will be equal to the MTU plus a 1286 * constant amount of header space and padding. This is the quantity 1287 * that the net driver will program into the MAC as the maximum frame 1288 * length. 1289 * 1290 * The 10G MAC requires 8-byte alignment on the frame 1291 * length, so we round up to the nearest 8. 1292 * 1293 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an 1294 * XGMII cycle). If the frame length reaches the maximum value in the 1295 * same cycle, the XMAC can miss the IPG altogether. We work around 1296 * this by adding a further 16 bytes. 1297 */ 1298 #define EFX_MAX_FRAME_LEN(mtu) \ 1299 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16) 1300 1301 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb) 1302 { 1303 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP; 1304 } 1305 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb) 1306 { 1307 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1308 } 1309 1310 #endif /* EFX_NET_DRIVER_H */ 1311