1 /**************************************************************************** 2 * Driver for Solarflare Solarstorm network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2011 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 /* Common definitions for all Efx net driver code */ 12 13 #ifndef EFX_NET_DRIVER_H 14 #define EFX_NET_DRIVER_H 15 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/ethtool.h> 19 #include <linux/if_vlan.h> 20 #include <linux/timer.h> 21 #include <linux/mdio.h> 22 #include <linux/list.h> 23 #include <linux/pci.h> 24 #include <linux/device.h> 25 #include <linux/highmem.h> 26 #include <linux/workqueue.h> 27 #include <linux/mutex.h> 28 #include <linux/vmalloc.h> 29 #include <linux/i2c.h> 30 31 #include "enum.h" 32 #include "bitfield.h" 33 34 /************************************************************************** 35 * 36 * Build definitions 37 * 38 **************************************************************************/ 39 40 #define EFX_DRIVER_VERSION "3.2" 41 42 #ifdef DEBUG 43 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) 44 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) 45 #else 46 #define EFX_BUG_ON_PARANOID(x) do {} while (0) 47 #define EFX_WARN_ON_PARANOID(x) do {} while (0) 48 #endif 49 50 /************************************************************************** 51 * 52 * Efx data structures 53 * 54 **************************************************************************/ 55 56 #define EFX_MAX_CHANNELS 32U 57 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS 58 #define EFX_EXTRA_CHANNEL_IOV 0 59 #define EFX_EXTRA_CHANNEL_PTP 1 60 #define EFX_MAX_EXTRA_CHANNELS 2U 61 62 /* Checksum generation is a per-queue option in hardware, so each 63 * queue visible to the networking core is backed by two hardware TX 64 * queues. */ 65 #define EFX_MAX_TX_TC 2 66 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS) 67 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */ 68 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */ 69 #define EFX_TXQ_TYPES 4 70 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS) 71 72 /* Maximum possible MTU the driver supports */ 73 #define EFX_MAX_MTU (9 * 1024) 74 75 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page, 76 * and should be a multiple of the cache line size. 77 */ 78 #define EFX_RX_USR_BUF_SIZE (2048 - 256) 79 80 /* If possible, we should ensure cache line alignment at start and end 81 * of every buffer. Otherwise, we just need to ensure 4-byte 82 * alignment of the network header. 83 */ 84 #if NET_IP_ALIGN == 0 85 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES 86 #else 87 #define EFX_RX_BUF_ALIGNMENT 4 88 #endif 89 90 /* Forward declare Precision Time Protocol (PTP) support structure. */ 91 struct efx_ptp_data; 92 93 struct efx_self_tests; 94 95 /** 96 * struct efx_special_buffer - An Efx special buffer 97 * @addr: CPU base address of the buffer 98 * @dma_addr: DMA base address of the buffer 99 * @len: Buffer length, in bytes 100 * @index: Buffer index within controller;s buffer table 101 * @entries: Number of buffer table entries 102 * 103 * Special buffers are used for the event queues and the TX and RX 104 * descriptor queues for each channel. They are *not* used for the 105 * actual transmit and receive buffers. 106 */ 107 struct efx_special_buffer { 108 void *addr; 109 dma_addr_t dma_addr; 110 unsigned int len; 111 unsigned int index; 112 unsigned int entries; 113 }; 114 115 /** 116 * struct efx_tx_buffer - buffer state for a TX descriptor 117 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be 118 * freed when descriptor completes 119 * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be 120 * freed when descriptor completes. 121 * @dma_addr: DMA address of the fragment. 122 * @flags: Flags for allocation and DMA mapping type 123 * @len: Length of this fragment. 124 * This field is zero when the queue slot is empty. 125 * @unmap_len: Length of this fragment to unmap 126 */ 127 struct efx_tx_buffer { 128 union { 129 const struct sk_buff *skb; 130 void *heap_buf; 131 }; 132 dma_addr_t dma_addr; 133 unsigned short flags; 134 unsigned short len; 135 unsigned short unmap_len; 136 }; 137 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */ 138 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */ 139 #define EFX_TX_BUF_HEAP 4 /* buffer was allocated with kmalloc() */ 140 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */ 141 142 /** 143 * struct efx_tx_queue - An Efx TX queue 144 * 145 * This is a ring buffer of TX fragments. 146 * Since the TX completion path always executes on the same 147 * CPU and the xmit path can operate on different CPUs, 148 * performance is increased by ensuring that the completion 149 * path and the xmit path operate on different cache lines. 150 * This is particularly important if the xmit path is always 151 * executing on one CPU which is different from the completion 152 * path. There is also a cache line for members which are 153 * read but not written on the fast path. 154 * 155 * @efx: The associated Efx NIC 156 * @queue: DMA queue number 157 * @channel: The associated channel 158 * @core_txq: The networking core TX queue structure 159 * @buffer: The software buffer ring 160 * @tsoh_page: Array of pages of TSO header buffers 161 * @txd: The hardware descriptor ring 162 * @ptr_mask: The size of the ring minus 1. 163 * @initialised: Has hardware queue been initialised? 164 * @read_count: Current read pointer. 165 * This is the number of buffers that have been removed from both rings. 166 * @old_write_count: The value of @write_count when last checked. 167 * This is here for performance reasons. The xmit path will 168 * only get the up-to-date value of @write_count if this 169 * variable indicates that the queue is empty. This is to 170 * avoid cache-line ping-pong between the xmit path and the 171 * completion path. 172 * @insert_count: Current insert pointer 173 * This is the number of buffers that have been added to the 174 * software ring. 175 * @write_count: Current write pointer 176 * This is the number of buffers that have been added to the 177 * hardware ring. 178 * @old_read_count: The value of read_count when last checked. 179 * This is here for performance reasons. The xmit path will 180 * only get the up-to-date value of read_count if this 181 * variable indicates that the queue is full. This is to 182 * avoid cache-line ping-pong between the xmit path and the 183 * completion path. 184 * @tso_bursts: Number of times TSO xmit invoked by kernel 185 * @tso_long_headers: Number of packets with headers too long for standard 186 * blocks 187 * @tso_packets: Number of packets via the TSO xmit path 188 * @pushes: Number of times the TX push feature has been used 189 * @empty_read_count: If the completion path has seen the queue as empty 190 * and the transmission path has not yet checked this, the value of 191 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0. 192 */ 193 struct efx_tx_queue { 194 /* Members which don't change on the fast path */ 195 struct efx_nic *efx ____cacheline_aligned_in_smp; 196 unsigned queue; 197 struct efx_channel *channel; 198 struct netdev_queue *core_txq; 199 struct efx_tx_buffer *buffer; 200 struct efx_buffer *tsoh_page; 201 struct efx_special_buffer txd; 202 unsigned int ptr_mask; 203 bool initialised; 204 205 /* Members used mainly on the completion path */ 206 unsigned int read_count ____cacheline_aligned_in_smp; 207 unsigned int old_write_count; 208 209 /* Members used only on the xmit path */ 210 unsigned int insert_count ____cacheline_aligned_in_smp; 211 unsigned int write_count; 212 unsigned int old_read_count; 213 unsigned int tso_bursts; 214 unsigned int tso_long_headers; 215 unsigned int tso_packets; 216 unsigned int pushes; 217 218 /* Members shared between paths and sometimes updated */ 219 unsigned int empty_read_count ____cacheline_aligned_in_smp; 220 #define EFX_EMPTY_COUNT_VALID 0x80000000 221 atomic_t flush_outstanding; 222 }; 223 224 /** 225 * struct efx_rx_buffer - An Efx RX data buffer 226 * @dma_addr: DMA base address of the buffer 227 * @page: The associated page buffer. 228 * Will be %NULL if the buffer slot is currently free. 229 * @page_offset: If pending: offset in @page of DMA base address. 230 * If completed: offset in @page of Ethernet header. 231 * @len: If pending: length for DMA descriptor. 232 * If completed: received length, excluding hash prefix. 233 * @flags: Flags for buffer and packet state. These are only set on the 234 * first buffer of a scattered packet. 235 */ 236 struct efx_rx_buffer { 237 dma_addr_t dma_addr; 238 struct page *page; 239 u16 page_offset; 240 u16 len; 241 u16 flags; 242 }; 243 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001 244 #define EFX_RX_PKT_CSUMMED 0x0002 245 #define EFX_RX_PKT_DISCARD 0x0004 246 #define EFX_RX_PKT_TCP 0x0040 247 248 /** 249 * struct efx_rx_page_state - Page-based rx buffer state 250 * 251 * Inserted at the start of every page allocated for receive buffers. 252 * Used to facilitate sharing dma mappings between recycled rx buffers 253 * and those passed up to the kernel. 254 * 255 * @refcnt: Number of struct efx_rx_buffer's referencing this page. 256 * When refcnt falls to zero, the page is unmapped for dma 257 * @dma_addr: The dma address of this page. 258 */ 259 struct efx_rx_page_state { 260 unsigned refcnt; 261 dma_addr_t dma_addr; 262 263 unsigned int __pad[0] ____cacheline_aligned; 264 }; 265 266 /** 267 * struct efx_rx_queue - An Efx RX queue 268 * @efx: The associated Efx NIC 269 * @core_index: Index of network core RX queue. Will be >= 0 iff this 270 * is associated with a real RX queue. 271 * @buffer: The software buffer ring 272 * @rxd: The hardware descriptor ring 273 * @ptr_mask: The size of the ring minus 1. 274 * @enabled: Receive queue enabled indicator. 275 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as 276 * @rxq_flush_pending. 277 * @added_count: Number of buffers added to the receive queue. 278 * @notified_count: Number of buffers given to NIC (<= @added_count). 279 * @removed_count: Number of buffers removed from the receive queue. 280 * @scatter_n: Number of buffers used by current packet 281 * @page_ring: The ring to store DMA mapped pages for reuse. 282 * @page_add: Counter to calculate the write pointer for the recycle ring. 283 * @page_remove: Counter to calculate the read pointer for the recycle ring. 284 * @page_recycle_count: The number of pages that have been recycled. 285 * @page_recycle_failed: The number of pages that couldn't be recycled because 286 * the kernel still held a reference to them. 287 * @page_recycle_full: The number of pages that were released because the 288 * recycle ring was full. 289 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1. 290 * @max_fill: RX descriptor maximum fill level (<= ring size) 291 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill 292 * (<= @max_fill) 293 * @min_fill: RX descriptor minimum non-zero fill level. 294 * This records the minimum fill level observed when a ring 295 * refill was triggered. 296 * @recycle_count: RX buffer recycle counter. 297 * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). 298 */ 299 struct efx_rx_queue { 300 struct efx_nic *efx; 301 int core_index; 302 struct efx_rx_buffer *buffer; 303 struct efx_special_buffer rxd; 304 unsigned int ptr_mask; 305 bool enabled; 306 bool flush_pending; 307 308 unsigned int added_count; 309 unsigned int notified_count; 310 unsigned int removed_count; 311 unsigned int scatter_n; 312 struct page **page_ring; 313 unsigned int page_add; 314 unsigned int page_remove; 315 unsigned int page_recycle_count; 316 unsigned int page_recycle_failed; 317 unsigned int page_recycle_full; 318 unsigned int page_ptr_mask; 319 unsigned int max_fill; 320 unsigned int fast_fill_trigger; 321 unsigned int min_fill; 322 unsigned int min_overfill; 323 unsigned int recycle_count; 324 struct timer_list slow_fill; 325 unsigned int slow_fill_count; 326 }; 327 328 /** 329 * struct efx_buffer - An Efx general-purpose buffer 330 * @addr: host base address of the buffer 331 * @dma_addr: DMA base address of the buffer 332 * @len: Buffer length, in bytes 333 * 334 * The NIC uses these buffers for its interrupt status registers and 335 * MAC stats dumps. 336 */ 337 struct efx_buffer { 338 void *addr; 339 dma_addr_t dma_addr; 340 unsigned int len; 341 }; 342 343 344 enum efx_rx_alloc_method { 345 RX_ALLOC_METHOD_AUTO = 0, 346 RX_ALLOC_METHOD_SKB = 1, 347 RX_ALLOC_METHOD_PAGE = 2, 348 }; 349 350 /** 351 * struct efx_channel - An Efx channel 352 * 353 * A channel comprises an event queue, at least one TX queue, at least 354 * one RX queue, and an associated tasklet for processing the event 355 * queue. 356 * 357 * @efx: Associated Efx NIC 358 * @channel: Channel instance number 359 * @type: Channel type definition 360 * @enabled: Channel enabled indicator 361 * @irq: IRQ number (MSI and MSI-X only) 362 * @irq_moderation: IRQ moderation value (in hardware ticks) 363 * @napi_dev: Net device used with NAPI 364 * @napi_str: NAPI control structure 365 * @work_pending: Is work pending via NAPI? 366 * @eventq: Event queue buffer 367 * @eventq_mask: Event queue pointer mask 368 * @eventq_read_ptr: Event queue read pointer 369 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel 370 * @irq_count: Number of IRQs since last adaptive moderation decision 371 * @irq_mod_score: IRQ moderation score 372 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors 373 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors 374 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors 375 * @n_rx_mcast_mismatch: Count of unmatched multicast frames 376 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors 377 * @n_rx_overlength: Count of RX_OVERLENGTH errors 378 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun 379 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to 380 * lack of descriptors 381 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by 382 * __efx_rx_packet(), or zero if there is none 383 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered 384 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0 385 * @rx_queue: RX queue for this channel 386 * @tx_queue: TX queues for this channel 387 */ 388 struct efx_channel { 389 struct efx_nic *efx; 390 int channel; 391 const struct efx_channel_type *type; 392 bool enabled; 393 int irq; 394 unsigned int irq_moderation; 395 struct net_device *napi_dev; 396 struct napi_struct napi_str; 397 bool work_pending; 398 struct efx_special_buffer eventq; 399 unsigned int eventq_mask; 400 unsigned int eventq_read_ptr; 401 int event_test_cpu; 402 403 unsigned int irq_count; 404 unsigned int irq_mod_score; 405 #ifdef CONFIG_RFS_ACCEL 406 unsigned int rfs_filters_added; 407 #endif 408 409 unsigned n_rx_tobe_disc; 410 unsigned n_rx_ip_hdr_chksum_err; 411 unsigned n_rx_tcp_udp_chksum_err; 412 unsigned n_rx_mcast_mismatch; 413 unsigned n_rx_frm_trunc; 414 unsigned n_rx_overlength; 415 unsigned n_skbuff_leaks; 416 unsigned int n_rx_nodesc_trunc; 417 418 unsigned int rx_pkt_n_frags; 419 unsigned int rx_pkt_index; 420 421 struct efx_rx_queue rx_queue; 422 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES]; 423 }; 424 425 /** 426 * struct efx_channel_type - distinguishes traffic and extra channels 427 * @handle_no_channel: Handle failure to allocate an extra channel 428 * @pre_probe: Set up extra state prior to initialisation 429 * @post_remove: Tear down extra state after finalisation, if allocated. 430 * May be called on channels that have not been probed. 431 * @get_name: Generate the channel's name (used for its IRQ handler) 432 * @copy: Copy the channel state prior to reallocation. May be %NULL if 433 * reallocation is not supported. 434 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb() 435 * @keep_eventq: Flag for whether event queue should be kept initialised 436 * while the device is stopped 437 */ 438 struct efx_channel_type { 439 void (*handle_no_channel)(struct efx_nic *); 440 int (*pre_probe)(struct efx_channel *); 441 void (*post_remove)(struct efx_channel *); 442 void (*get_name)(struct efx_channel *, char *buf, size_t len); 443 struct efx_channel *(*copy)(const struct efx_channel *); 444 bool (*receive_skb)(struct efx_channel *, struct sk_buff *); 445 bool keep_eventq; 446 }; 447 448 enum efx_led_mode { 449 EFX_LED_OFF = 0, 450 EFX_LED_ON = 1, 451 EFX_LED_DEFAULT = 2 452 }; 453 454 #define STRING_TABLE_LOOKUP(val, member) \ 455 ((val) < member ## _max) ? member ## _names[val] : "(invalid)" 456 457 extern const char *const efx_loopback_mode_names[]; 458 extern const unsigned int efx_loopback_mode_max; 459 #define LOOPBACK_MODE(efx) \ 460 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) 461 462 extern const char *const efx_reset_type_names[]; 463 extern const unsigned int efx_reset_type_max; 464 #define RESET_TYPE(type) \ 465 STRING_TABLE_LOOKUP(type, efx_reset_type) 466 467 enum efx_int_mode { 468 /* Be careful if altering to correct macro below */ 469 EFX_INT_MODE_MSIX = 0, 470 EFX_INT_MODE_MSI = 1, 471 EFX_INT_MODE_LEGACY = 2, 472 EFX_INT_MODE_MAX /* Insert any new items before this */ 473 }; 474 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) 475 476 enum nic_state { 477 STATE_UNINIT = 0, /* device being probed/removed or is frozen */ 478 STATE_READY = 1, /* hardware ready and netdev registered */ 479 STATE_DISABLED = 2, /* device disabled due to hardware errors */ 480 STATE_RECOVERY = 3, /* device recovering from PCI error */ 481 }; 482 483 /* 484 * Alignment of the skb->head which wraps a page-allocated RX buffer 485 * 486 * The skb allocated to wrap an rx_buffer can have this alignment. Since 487 * the data is memcpy'd from the rx_buf, it does not need to be equal to 488 * NET_IP_ALIGN. 489 */ 490 #define EFX_PAGE_SKB_ALIGN 2 491 492 /* Forward declaration */ 493 struct efx_nic; 494 495 /* Pseudo bit-mask flow control field */ 496 #define EFX_FC_RX FLOW_CTRL_RX 497 #define EFX_FC_TX FLOW_CTRL_TX 498 #define EFX_FC_AUTO 4 499 500 /** 501 * struct efx_link_state - Current state of the link 502 * @up: Link is up 503 * @fd: Link is full-duplex 504 * @fc: Actual flow control flags 505 * @speed: Link speed (Mbps) 506 */ 507 struct efx_link_state { 508 bool up; 509 bool fd; 510 u8 fc; 511 unsigned int speed; 512 }; 513 514 static inline bool efx_link_state_equal(const struct efx_link_state *left, 515 const struct efx_link_state *right) 516 { 517 return left->up == right->up && left->fd == right->fd && 518 left->fc == right->fc && left->speed == right->speed; 519 } 520 521 /** 522 * struct efx_phy_operations - Efx PHY operations table 523 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, 524 * efx->loopback_modes. 525 * @init: Initialise PHY 526 * @fini: Shut down PHY 527 * @reconfigure: Reconfigure PHY (e.g. for new link parameters) 528 * @poll: Update @link_state and report whether it changed. 529 * Serialised by the mac_lock. 530 * @get_settings: Get ethtool settings. Serialised by the mac_lock. 531 * @set_settings: Set ethtool settings. Serialised by the mac_lock. 532 * @set_npage_adv: Set abilities advertised in (Extended) Next Page 533 * (only needed where AN bit is set in mmds) 534 * @test_alive: Test that PHY is 'alive' (online) 535 * @test_name: Get the name of a PHY-specific test/result 536 * @run_tests: Run tests and record results as appropriate (offline). 537 * Flags are the ethtool tests flags. 538 */ 539 struct efx_phy_operations { 540 int (*probe) (struct efx_nic *efx); 541 int (*init) (struct efx_nic *efx); 542 void (*fini) (struct efx_nic *efx); 543 void (*remove) (struct efx_nic *efx); 544 int (*reconfigure) (struct efx_nic *efx); 545 bool (*poll) (struct efx_nic *efx); 546 void (*get_settings) (struct efx_nic *efx, 547 struct ethtool_cmd *ecmd); 548 int (*set_settings) (struct efx_nic *efx, 549 struct ethtool_cmd *ecmd); 550 void (*set_npage_adv) (struct efx_nic *efx, u32); 551 int (*test_alive) (struct efx_nic *efx); 552 const char *(*test_name) (struct efx_nic *efx, unsigned int index); 553 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); 554 int (*get_module_eeprom) (struct efx_nic *efx, 555 struct ethtool_eeprom *ee, 556 u8 *data); 557 int (*get_module_info) (struct efx_nic *efx, 558 struct ethtool_modinfo *modinfo); 559 }; 560 561 /** 562 * enum efx_phy_mode - PHY operating mode flags 563 * @PHY_MODE_NORMAL: on and should pass traffic 564 * @PHY_MODE_TX_DISABLED: on with TX disabled 565 * @PHY_MODE_LOW_POWER: set to low power through MDIO 566 * @PHY_MODE_OFF: switched off through external control 567 * @PHY_MODE_SPECIAL: on but will not pass traffic 568 */ 569 enum efx_phy_mode { 570 PHY_MODE_NORMAL = 0, 571 PHY_MODE_TX_DISABLED = 1, 572 PHY_MODE_LOW_POWER = 2, 573 PHY_MODE_OFF = 4, 574 PHY_MODE_SPECIAL = 8, 575 }; 576 577 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) 578 { 579 return !!(mode & ~PHY_MODE_TX_DISABLED); 580 } 581 582 /* 583 * Efx extended statistics 584 * 585 * Not all statistics are provided by all supported MACs. The purpose 586 * is this structure is to contain the raw statistics provided by each 587 * MAC. 588 */ 589 struct efx_mac_stats { 590 u64 tx_bytes; 591 u64 tx_good_bytes; 592 u64 tx_bad_bytes; 593 u64 tx_packets; 594 u64 tx_bad; 595 u64 tx_pause; 596 u64 tx_control; 597 u64 tx_unicast; 598 u64 tx_multicast; 599 u64 tx_broadcast; 600 u64 tx_lt64; 601 u64 tx_64; 602 u64 tx_65_to_127; 603 u64 tx_128_to_255; 604 u64 tx_256_to_511; 605 u64 tx_512_to_1023; 606 u64 tx_1024_to_15xx; 607 u64 tx_15xx_to_jumbo; 608 u64 tx_gtjumbo; 609 u64 tx_collision; 610 u64 tx_single_collision; 611 u64 tx_multiple_collision; 612 u64 tx_excessive_collision; 613 u64 tx_deferred; 614 u64 tx_late_collision; 615 u64 tx_excessive_deferred; 616 u64 tx_non_tcpudp; 617 u64 tx_mac_src_error; 618 u64 tx_ip_src_error; 619 u64 rx_bytes; 620 u64 rx_good_bytes; 621 u64 rx_bad_bytes; 622 u64 rx_packets; 623 u64 rx_good; 624 u64 rx_bad; 625 u64 rx_pause; 626 u64 rx_control; 627 u64 rx_unicast; 628 u64 rx_multicast; 629 u64 rx_broadcast; 630 u64 rx_lt64; 631 u64 rx_64; 632 u64 rx_65_to_127; 633 u64 rx_128_to_255; 634 u64 rx_256_to_511; 635 u64 rx_512_to_1023; 636 u64 rx_1024_to_15xx; 637 u64 rx_15xx_to_jumbo; 638 u64 rx_gtjumbo; 639 u64 rx_bad_lt64; 640 u64 rx_bad_64_to_15xx; 641 u64 rx_bad_15xx_to_jumbo; 642 u64 rx_bad_gtjumbo; 643 u64 rx_overflow; 644 u64 rx_missed; 645 u64 rx_false_carrier; 646 u64 rx_symbol_error; 647 u64 rx_align_error; 648 u64 rx_length_error; 649 u64 rx_internal_error; 650 u64 rx_good_lt64; 651 }; 652 653 /* Number of bits used in a multicast filter hash address */ 654 #define EFX_MCAST_HASH_BITS 8 655 656 /* Number of (single-bit) entries in a multicast filter hash */ 657 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) 658 659 /* An Efx multicast filter hash */ 660 union efx_multicast_hash { 661 u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; 662 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; 663 }; 664 665 struct efx_filter_state; 666 struct efx_vf; 667 struct vfdi_status; 668 669 /** 670 * struct efx_nic - an Efx NIC 671 * @name: Device name (net device name or bus id before net device registered) 672 * @pci_dev: The PCI device 673 * @type: Controller type attributes 674 * @legacy_irq: IRQ number 675 * @legacy_irq_enabled: Are IRQs enabled on NIC (INT_EN_KER register)? 676 * @workqueue: Workqueue for port reconfigures and the HW monitor. 677 * Work items do not hold and must not acquire RTNL. 678 * @workqueue_name: Name of workqueue 679 * @reset_work: Scheduled reset workitem 680 * @membase_phys: Memory BAR value as physical address 681 * @membase: Memory BAR value 682 * @interrupt_mode: Interrupt mode 683 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds 684 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues 685 * @irq_rx_moderation: IRQ moderation time for RX event queues 686 * @msg_enable: Log message enable flags 687 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock. 688 * @reset_pending: Bitmask for pending resets 689 * @tx_queue: TX DMA queues 690 * @rx_queue: RX DMA queues 691 * @channel: Channels 692 * @channel_name: Names for channels and their IRQs 693 * @extra_channel_types: Types of extra (non-traffic) channels that 694 * should be allocated for this NIC 695 * @rxq_entries: Size of receive queues requested by user. 696 * @txq_entries: Size of transmit queues requested by user. 697 * @txq_stop_thresh: TX queue fill level at or above which we stop it. 698 * @txq_wake_thresh: TX queue fill level at or below which we wake it. 699 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches 700 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches 701 * @sram_lim_qw: Qword address limit of SRAM 702 * @next_buffer_table: First available buffer table id 703 * @n_channels: Number of channels in use 704 * @n_rx_channels: Number of channels used for RX (= number of RX queues) 705 * @n_tx_channels: Number of channels used for TX 706 * @rx_dma_len: Current maximum RX DMA length 707 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer 708 * @rx_buffer_truesize: Amortised allocation size of an RX buffer, 709 * for use in sk_buff::truesize 710 * @rx_hash_key: Toeplitz hash key for RSS 711 * @rx_indir_table: Indirection table for RSS 712 * @rx_scatter: Scatter mode enabled for receives 713 * @int_error_count: Number of internal errors seen recently 714 * @int_error_expire: Time at which error count will be expired 715 * @irq_status: Interrupt status buffer 716 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 717 * @irq_level: IRQ level/index for IRQs not triggered by an event queue 718 * @selftest_work: Work item for asynchronous self-test 719 * @mtd_list: List of MTDs attached to the NIC 720 * @nic_data: Hardware dependent state 721 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, 722 * efx_monitor() and efx_reconfigure_port() 723 * @port_enabled: Port enabled indicator. 724 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and 725 * efx_mac_work() with kernel interfaces. Safe to read under any 726 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must 727 * be held to modify it. 728 * @port_initialized: Port initialized? 729 * @net_dev: Operating system network device. Consider holding the rtnl lock 730 * @stats_buffer: DMA buffer for statistics 731 * @phy_type: PHY type 732 * @phy_op: PHY interface 733 * @phy_data: PHY private data (including PHY-specific stats) 734 * @mdio: PHY MDIO interface 735 * @mdio_bus: PHY MDIO bus ID (only used by Siena) 736 * @phy_mode: PHY operating mode. Serialised by @mac_lock. 737 * @link_advertising: Autonegotiation advertising flags 738 * @link_state: Current state of the link 739 * @n_link_state_changes: Number of times the link has changed state 740 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock. 741 * @multicast_hash: Multicast hash table 742 * @wanted_fc: Wanted flow control flags 743 * @fc_disable: When non-zero flow control is disabled. Typically used to 744 * ensure that network back pressure doesn't delay dma queue flushes. 745 * Serialised by the rtnl lock. 746 * @mac_work: Work item for changing MAC promiscuity and multicast hash 747 * @loopback_mode: Loopback status 748 * @loopback_modes: Supported loopback mode bitmask 749 * @loopback_selftest: Offline self-test private state 750 * @drain_pending: Count of RX and TX queues that haven't been flushed and drained. 751 * @rxq_flush_pending: Count of number of receive queues that need to be flushed. 752 * Decremented when the efx_flush_rx_queue() is called. 753 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet 754 * completed (either success or failure). Not used when MCDI is used to 755 * flush receive queues. 756 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions. 757 * @vf: Array of &struct efx_vf objects. 758 * @vf_count: Number of VFs intended to be enabled. 759 * @vf_init_count: Number of VFs that have been fully initialised. 760 * @vi_scale: log2 number of vnics per VF. 761 * @vf_buftbl_base: The zeroth buffer table index used to back VF queues. 762 * @vfdi_status: Common VFDI status page to be dmad to VF address space. 763 * @local_addr_list: List of local addresses. Protected by %local_lock. 764 * @local_page_list: List of DMA addressable pages used to broadcast 765 * %local_addr_list. Protected by %local_lock. 766 * @local_lock: Mutex protecting %local_addr_list and %local_page_list. 767 * @peer_work: Work item to broadcast peer addresses to VMs. 768 * @ptp_data: PTP state data 769 * @monitor_work: Hardware monitor workitem 770 * @biu_lock: BIU (bus interface unit) lock 771 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This 772 * field is used by efx_test_interrupts() to verify that an 773 * interrupt has occurred. 774 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count 775 * @mac_stats: MAC statistics. These include all statistics the MACs 776 * can provide. Generic code converts these into a standard 777 * &struct net_device_stats. 778 * @stats_lock: Statistics update lock. Serialises statistics fetches 779 * and access to @mac_stats. 780 * 781 * This is stored in the private area of the &struct net_device. 782 */ 783 struct efx_nic { 784 /* The following fields should be written very rarely */ 785 786 char name[IFNAMSIZ]; 787 struct pci_dev *pci_dev; 788 unsigned int port_num; 789 const struct efx_nic_type *type; 790 int legacy_irq; 791 bool legacy_irq_enabled; 792 bool eeh_disabled_legacy_irq; 793 struct workqueue_struct *workqueue; 794 char workqueue_name[16]; 795 struct work_struct reset_work; 796 resource_size_t membase_phys; 797 void __iomem *membase; 798 799 enum efx_int_mode interrupt_mode; 800 unsigned int timer_quantum_ns; 801 bool irq_rx_adaptive; 802 unsigned int irq_rx_moderation; 803 u32 msg_enable; 804 805 enum nic_state state; 806 unsigned long reset_pending; 807 808 struct efx_channel *channel[EFX_MAX_CHANNELS]; 809 char channel_name[EFX_MAX_CHANNELS][IFNAMSIZ + 6]; 810 const struct efx_channel_type * 811 extra_channel_type[EFX_MAX_EXTRA_CHANNELS]; 812 813 unsigned rxq_entries; 814 unsigned txq_entries; 815 unsigned int txq_stop_thresh; 816 unsigned int txq_wake_thresh; 817 818 unsigned tx_dc_base; 819 unsigned rx_dc_base; 820 unsigned sram_lim_qw; 821 unsigned next_buffer_table; 822 unsigned n_channels; 823 unsigned n_rx_channels; 824 unsigned rss_spread; 825 unsigned tx_channel_offset; 826 unsigned n_tx_channels; 827 unsigned int rx_dma_len; 828 unsigned int rx_buffer_order; 829 unsigned int rx_buffer_truesize; 830 unsigned int rx_page_buf_step; 831 unsigned int rx_bufs_per_page; 832 unsigned int rx_pages_per_batch; 833 u8 rx_hash_key[40]; 834 u32 rx_indir_table[128]; 835 bool rx_scatter; 836 837 unsigned int_error_count; 838 unsigned long int_error_expire; 839 840 struct efx_buffer irq_status; 841 unsigned irq_zero_count; 842 unsigned irq_level; 843 struct delayed_work selftest_work; 844 845 #ifdef CONFIG_SFC_MTD 846 struct list_head mtd_list; 847 #endif 848 849 void *nic_data; 850 851 struct mutex mac_lock; 852 struct work_struct mac_work; 853 bool port_enabled; 854 855 bool port_initialized; 856 struct net_device *net_dev; 857 858 struct efx_buffer stats_buffer; 859 860 unsigned int phy_type; 861 const struct efx_phy_operations *phy_op; 862 void *phy_data; 863 struct mdio_if_info mdio; 864 unsigned int mdio_bus; 865 enum efx_phy_mode phy_mode; 866 867 u32 link_advertising; 868 struct efx_link_state link_state; 869 unsigned int n_link_state_changes; 870 871 bool promiscuous; 872 union efx_multicast_hash multicast_hash; 873 u8 wanted_fc; 874 unsigned fc_disable; 875 876 atomic_t rx_reset; 877 enum efx_loopback_mode loopback_mode; 878 u64 loopback_modes; 879 880 void *loopback_selftest; 881 882 struct efx_filter_state *filter_state; 883 884 atomic_t drain_pending; 885 atomic_t rxq_flush_pending; 886 atomic_t rxq_flush_outstanding; 887 wait_queue_head_t flush_wq; 888 889 #ifdef CONFIG_SFC_SRIOV 890 struct efx_channel *vfdi_channel; 891 struct efx_vf *vf; 892 unsigned vf_count; 893 unsigned vf_init_count; 894 unsigned vi_scale; 895 unsigned vf_buftbl_base; 896 struct efx_buffer vfdi_status; 897 struct list_head local_addr_list; 898 struct list_head local_page_list; 899 struct mutex local_lock; 900 struct work_struct peer_work; 901 #endif 902 903 struct efx_ptp_data *ptp_data; 904 905 /* The following fields may be written more often */ 906 907 struct delayed_work monitor_work ____cacheline_aligned_in_smp; 908 spinlock_t biu_lock; 909 int last_irq_cpu; 910 unsigned n_rx_nodesc_drop_cnt; 911 struct efx_mac_stats mac_stats; 912 spinlock_t stats_lock; 913 }; 914 915 static inline int efx_dev_registered(struct efx_nic *efx) 916 { 917 return efx->net_dev->reg_state == NETREG_REGISTERED; 918 } 919 920 static inline unsigned int efx_port_num(struct efx_nic *efx) 921 { 922 return efx->port_num; 923 } 924 925 /** 926 * struct efx_nic_type - Efx device type definition 927 * @probe: Probe the controller 928 * @remove: Free resources allocated by probe() 929 * @init: Initialise the controller 930 * @dimension_resources: Dimension controller resources (buffer table, 931 * and VIs once the available interrupt resources are clear) 932 * @fini: Shut down the controller 933 * @monitor: Periodic function for polling link state and hardware monitor 934 * @map_reset_reason: Map ethtool reset reason to a reset method 935 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible 936 * @reset: Reset the controller hardware and possibly the PHY. This will 937 * be called while the controller is uninitialised. 938 * @probe_port: Probe the MAC and PHY 939 * @remove_port: Free resources allocated by probe_port() 940 * @handle_global_event: Handle a "global" event (may be %NULL) 941 * @prepare_flush: Prepare the hardware for flushing the DMA queues 942 * @finish_flush: Clean up after flushing the DMA queues 943 * @update_stats: Update statistics not provided by event handling 944 * @start_stats: Start the regular fetching of statistics 945 * @stop_stats: Stop the regular fetching of statistics 946 * @set_id_led: Set state of identifying LED or revert to automatic function 947 * @push_irq_moderation: Apply interrupt moderation value 948 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY 949 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings 950 * to the hardware. Serialised by the mac_lock. 951 * @check_mac_fault: Check MAC fault state. True if fault present. 952 * @get_wol: Get WoL configuration from driver state 953 * @set_wol: Push WoL configuration to the NIC 954 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) 955 * @test_chip: Test registers. Should use efx_nic_test_registers(), and is 956 * expected to reset the NIC. 957 * @test_nvram: Test validity of NVRAM contents 958 * @revision: Hardware architecture revision 959 * @mem_map_size: Memory BAR mapped size 960 * @txd_ptr_tbl_base: TX descriptor ring base address 961 * @rxd_ptr_tbl_base: RX descriptor ring base address 962 * @buf_tbl_base: Buffer table base address 963 * @evq_ptr_tbl_base: Event queue pointer table base address 964 * @evq_rptr_tbl_base: Event queue read-pointer table base address 965 * @max_dma_mask: Maximum possible DMA mask 966 * @rx_buffer_hash_size: Size of hash at start of RX packet 967 * @rx_buffer_padding: Size of padding at end of RX packet 968 * @can_rx_scatter: NIC is able to scatter packet to multiple buffers 969 * @max_interrupt_mode: Highest capability interrupt mode supported 970 * from &enum efx_init_mode. 971 * @phys_addr_channels: Number of channels with physically addressed 972 * descriptors 973 * @timer_period_max: Maximum period of interrupt timer (in ticks) 974 * @offload_features: net_device feature flags for protocol offload 975 * features implemented in hardware 976 */ 977 struct efx_nic_type { 978 int (*probe)(struct efx_nic *efx); 979 void (*remove)(struct efx_nic *efx); 980 int (*init)(struct efx_nic *efx); 981 void (*dimension_resources)(struct efx_nic *efx); 982 void (*fini)(struct efx_nic *efx); 983 void (*monitor)(struct efx_nic *efx); 984 enum reset_type (*map_reset_reason)(enum reset_type reason); 985 int (*map_reset_flags)(u32 *flags); 986 int (*reset)(struct efx_nic *efx, enum reset_type method); 987 int (*probe_port)(struct efx_nic *efx); 988 void (*remove_port)(struct efx_nic *efx); 989 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *); 990 void (*prepare_flush)(struct efx_nic *efx); 991 void (*finish_flush)(struct efx_nic *efx); 992 void (*update_stats)(struct efx_nic *efx); 993 void (*start_stats)(struct efx_nic *efx); 994 void (*stop_stats)(struct efx_nic *efx); 995 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); 996 void (*push_irq_moderation)(struct efx_channel *channel); 997 int (*reconfigure_port)(struct efx_nic *efx); 998 int (*reconfigure_mac)(struct efx_nic *efx); 999 bool (*check_mac_fault)(struct efx_nic *efx); 1000 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); 1001 int (*set_wol)(struct efx_nic *efx, u32 type); 1002 void (*resume_wol)(struct efx_nic *efx); 1003 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests); 1004 int (*test_nvram)(struct efx_nic *efx); 1005 1006 int revision; 1007 unsigned int mem_map_size; 1008 unsigned int txd_ptr_tbl_base; 1009 unsigned int rxd_ptr_tbl_base; 1010 unsigned int buf_tbl_base; 1011 unsigned int evq_ptr_tbl_base; 1012 unsigned int evq_rptr_tbl_base; 1013 u64 max_dma_mask; 1014 unsigned int rx_buffer_hash_size; 1015 unsigned int rx_buffer_padding; 1016 bool can_rx_scatter; 1017 unsigned int max_interrupt_mode; 1018 unsigned int phys_addr_channels; 1019 unsigned int timer_period_max; 1020 netdev_features_t offload_features; 1021 }; 1022 1023 /************************************************************************** 1024 * 1025 * Prototypes and inline functions 1026 * 1027 *************************************************************************/ 1028 1029 static inline struct efx_channel * 1030 efx_get_channel(struct efx_nic *efx, unsigned index) 1031 { 1032 EFX_BUG_ON_PARANOID(index >= efx->n_channels); 1033 return efx->channel[index]; 1034 } 1035 1036 /* Iterate over all used channels */ 1037 #define efx_for_each_channel(_channel, _efx) \ 1038 for (_channel = (_efx)->channel[0]; \ 1039 _channel; \ 1040 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ 1041 (_efx)->channel[_channel->channel + 1] : NULL) 1042 1043 /* Iterate over all used channels in reverse */ 1044 #define efx_for_each_channel_rev(_channel, _efx) \ 1045 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \ 1046 _channel; \ 1047 _channel = _channel->channel ? \ 1048 (_efx)->channel[_channel->channel - 1] : NULL) 1049 1050 static inline struct efx_tx_queue * 1051 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) 1052 { 1053 EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels || 1054 type >= EFX_TXQ_TYPES); 1055 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type]; 1056 } 1057 1058 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel) 1059 { 1060 return channel->channel - channel->efx->tx_channel_offset < 1061 channel->efx->n_tx_channels; 1062 } 1063 1064 static inline struct efx_tx_queue * 1065 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type) 1066 { 1067 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) || 1068 type >= EFX_TXQ_TYPES); 1069 return &channel->tx_queue[type]; 1070 } 1071 1072 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue) 1073 { 1074 return !(tx_queue->efx->net_dev->num_tc < 2 && 1075 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI); 1076 } 1077 1078 /* Iterate over all TX queues belonging to a channel */ 1079 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ 1080 if (!efx_channel_has_tx_queues(_channel)) \ 1081 ; \ 1082 else \ 1083 for (_tx_queue = (_channel)->tx_queue; \ 1084 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \ 1085 efx_tx_queue_used(_tx_queue); \ 1086 _tx_queue++) 1087 1088 /* Iterate over all possible TX queues belonging to a channel */ 1089 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \ 1090 if (!efx_channel_has_tx_queues(_channel)) \ 1091 ; \ 1092 else \ 1093 for (_tx_queue = (_channel)->tx_queue; \ 1094 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ 1095 _tx_queue++) 1096 1097 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel) 1098 { 1099 return channel->rx_queue.core_index >= 0; 1100 } 1101 1102 static inline struct efx_rx_queue * 1103 efx_channel_get_rx_queue(struct efx_channel *channel) 1104 { 1105 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel)); 1106 return &channel->rx_queue; 1107 } 1108 1109 /* Iterate over all RX queues belonging to a channel */ 1110 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ 1111 if (!efx_channel_has_rx_queue(_channel)) \ 1112 ; \ 1113 else \ 1114 for (_rx_queue = &(_channel)->rx_queue; \ 1115 _rx_queue; \ 1116 _rx_queue = NULL) 1117 1118 static inline struct efx_channel * 1119 efx_rx_queue_channel(struct efx_rx_queue *rx_queue) 1120 { 1121 return container_of(rx_queue, struct efx_channel, rx_queue); 1122 } 1123 1124 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) 1125 { 1126 return efx_rx_queue_channel(rx_queue)->channel; 1127 } 1128 1129 /* Returns a pointer to the specified receive buffer in the RX 1130 * descriptor queue. 1131 */ 1132 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, 1133 unsigned int index) 1134 { 1135 return &rx_queue->buffer[index]; 1136 } 1137 1138 1139 /** 1140 * EFX_MAX_FRAME_LEN - calculate maximum frame length 1141 * 1142 * This calculates the maximum frame length that will be used for a 1143 * given MTU. The frame length will be equal to the MTU plus a 1144 * constant amount of header space and padding. This is the quantity 1145 * that the net driver will program into the MAC as the maximum frame 1146 * length. 1147 * 1148 * The 10G MAC requires 8-byte alignment on the frame 1149 * length, so we round up to the nearest 8. 1150 * 1151 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an 1152 * XGMII cycle). If the frame length reaches the maximum value in the 1153 * same cycle, the XMAC can miss the IPG altogether. We work around 1154 * this by adding a further 16 bytes. 1155 */ 1156 #define EFX_MAX_FRAME_LEN(mtu) \ 1157 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16) 1158 1159 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb) 1160 { 1161 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP; 1162 } 1163 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb) 1164 { 1165 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1166 } 1167 1168 #endif /* EFX_NET_DRIVER_H */ 1169