1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 /* Common definitions for all Efx net driver code */ 12 13 #ifndef EFX_NET_DRIVER_H 14 #define EFX_NET_DRIVER_H 15 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/ethtool.h> 19 #include <linux/if_vlan.h> 20 #include <linux/timer.h> 21 #include <linux/mdio.h> 22 #include <linux/list.h> 23 #include <linux/pci.h> 24 #include <linux/device.h> 25 #include <linux/highmem.h> 26 #include <linux/workqueue.h> 27 #include <linux/mutex.h> 28 #include <linux/vmalloc.h> 29 #include <linux/i2c.h> 30 #include <linux/mtd/mtd.h> 31 32 #include "enum.h" 33 #include "bitfield.h" 34 #include "filter.h" 35 36 /************************************************************************** 37 * 38 * Build definitions 39 * 40 **************************************************************************/ 41 42 #define EFX_DRIVER_VERSION "4.0" 43 44 #ifdef DEBUG 45 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) 46 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) 47 #else 48 #define EFX_BUG_ON_PARANOID(x) do {} while (0) 49 #define EFX_WARN_ON_PARANOID(x) do {} while (0) 50 #endif 51 52 /************************************************************************** 53 * 54 * Efx data structures 55 * 56 **************************************************************************/ 57 58 #define EFX_MAX_CHANNELS 32U 59 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS 60 #define EFX_EXTRA_CHANNEL_IOV 0 61 #define EFX_EXTRA_CHANNEL_PTP 1 62 #define EFX_MAX_EXTRA_CHANNELS 2U 63 64 /* Checksum generation is a per-queue option in hardware, so each 65 * queue visible to the networking core is backed by two hardware TX 66 * queues. */ 67 #define EFX_MAX_TX_TC 2 68 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS) 69 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */ 70 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */ 71 #define EFX_TXQ_TYPES 4 72 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS) 73 74 /* Maximum possible MTU the driver supports */ 75 #define EFX_MAX_MTU (9 * 1024) 76 77 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page, 78 * and should be a multiple of the cache line size. 79 */ 80 #define EFX_RX_USR_BUF_SIZE (2048 - 256) 81 82 /* If possible, we should ensure cache line alignment at start and end 83 * of every buffer. Otherwise, we just need to ensure 4-byte 84 * alignment of the network header. 85 */ 86 #if NET_IP_ALIGN == 0 87 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES 88 #else 89 #define EFX_RX_BUF_ALIGNMENT 4 90 #endif 91 92 /* Forward declare Precision Time Protocol (PTP) support structure. */ 93 struct efx_ptp_data; 94 struct hwtstamp_config; 95 96 struct efx_self_tests; 97 98 /** 99 * struct efx_buffer - A general-purpose DMA buffer 100 * @addr: host base address of the buffer 101 * @dma_addr: DMA base address of the buffer 102 * @len: Buffer length, in bytes 103 * 104 * The NIC uses these buffers for its interrupt status registers and 105 * MAC stats dumps. 106 */ 107 struct efx_buffer { 108 void *addr; 109 dma_addr_t dma_addr; 110 unsigned int len; 111 }; 112 113 /** 114 * struct efx_special_buffer - DMA buffer entered into buffer table 115 * @buf: Standard &struct efx_buffer 116 * @index: Buffer index within controller;s buffer table 117 * @entries: Number of buffer table entries 118 * 119 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE. 120 * Event and descriptor rings are addressed via one or more buffer 121 * table entries (and so can be physically non-contiguous, although we 122 * currently do not take advantage of that). On Falcon and Siena we 123 * have to take care of allocating and initialising the entries 124 * ourselves. On later hardware this is managed by the firmware and 125 * @index and @entries are left as 0. 126 */ 127 struct efx_special_buffer { 128 struct efx_buffer buf; 129 unsigned int index; 130 unsigned int entries; 131 }; 132 133 /** 134 * struct efx_tx_buffer - buffer state for a TX descriptor 135 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be 136 * freed when descriptor completes 137 * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be 138 * freed when descriptor completes. 139 * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor. 140 * @dma_addr: DMA address of the fragment. 141 * @flags: Flags for allocation and DMA mapping type 142 * @len: Length of this fragment. 143 * This field is zero when the queue slot is empty. 144 * @unmap_len: Length of this fragment to unmap 145 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping. 146 * Only valid if @unmap_len != 0. 147 */ 148 struct efx_tx_buffer { 149 union { 150 const struct sk_buff *skb; 151 void *heap_buf; 152 }; 153 union { 154 efx_qword_t option; 155 dma_addr_t dma_addr; 156 }; 157 unsigned short flags; 158 unsigned short len; 159 unsigned short unmap_len; 160 unsigned short dma_offset; 161 }; 162 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */ 163 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */ 164 #define EFX_TX_BUF_HEAP 4 /* buffer was allocated with kmalloc() */ 165 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */ 166 #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */ 167 168 /** 169 * struct efx_tx_queue - An Efx TX queue 170 * 171 * This is a ring buffer of TX fragments. 172 * Since the TX completion path always executes on the same 173 * CPU and the xmit path can operate on different CPUs, 174 * performance is increased by ensuring that the completion 175 * path and the xmit path operate on different cache lines. 176 * This is particularly important if the xmit path is always 177 * executing on one CPU which is different from the completion 178 * path. There is also a cache line for members which are 179 * read but not written on the fast path. 180 * 181 * @efx: The associated Efx NIC 182 * @queue: DMA queue number 183 * @channel: The associated channel 184 * @core_txq: The networking core TX queue structure 185 * @buffer: The software buffer ring 186 * @tsoh_page: Array of pages of TSO header buffers 187 * @txd: The hardware descriptor ring 188 * @ptr_mask: The size of the ring minus 1. 189 * @piobuf: PIO buffer region for this TX queue (shared with its partner). 190 * Size of the region is efx_piobuf_size. 191 * @piobuf_offset: Buffer offset to be specified in PIO descriptors 192 * @initialised: Has hardware queue been initialised? 193 * @read_count: Current read pointer. 194 * This is the number of buffers that have been removed from both rings. 195 * @old_write_count: The value of @write_count when last checked. 196 * This is here for performance reasons. The xmit path will 197 * only get the up-to-date value of @write_count if this 198 * variable indicates that the queue is empty. This is to 199 * avoid cache-line ping-pong between the xmit path and the 200 * completion path. 201 * @merge_events: Number of TX merged completion events 202 * @insert_count: Current insert pointer 203 * This is the number of buffers that have been added to the 204 * software ring. 205 * @write_count: Current write pointer 206 * This is the number of buffers that have been added to the 207 * hardware ring. 208 * @old_read_count: The value of read_count when last checked. 209 * This is here for performance reasons. The xmit path will 210 * only get the up-to-date value of read_count if this 211 * variable indicates that the queue is full. This is to 212 * avoid cache-line ping-pong between the xmit path and the 213 * completion path. 214 * @tso_bursts: Number of times TSO xmit invoked by kernel 215 * @tso_long_headers: Number of packets with headers too long for standard 216 * blocks 217 * @tso_packets: Number of packets via the TSO xmit path 218 * @pushes: Number of times the TX push feature has been used 219 * @pio_packets: Number of times the TX PIO feature has been used 220 * @empty_read_count: If the completion path has seen the queue as empty 221 * and the transmission path has not yet checked this, the value of 222 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0. 223 */ 224 struct efx_tx_queue { 225 /* Members which don't change on the fast path */ 226 struct efx_nic *efx ____cacheline_aligned_in_smp; 227 unsigned queue; 228 struct efx_channel *channel; 229 struct netdev_queue *core_txq; 230 struct efx_tx_buffer *buffer; 231 struct efx_buffer *tsoh_page; 232 struct efx_special_buffer txd; 233 unsigned int ptr_mask; 234 void __iomem *piobuf; 235 unsigned int piobuf_offset; 236 bool initialised; 237 238 /* Members used mainly on the completion path */ 239 unsigned int read_count ____cacheline_aligned_in_smp; 240 unsigned int old_write_count; 241 unsigned int merge_events; 242 243 /* Members used only on the xmit path */ 244 unsigned int insert_count ____cacheline_aligned_in_smp; 245 unsigned int write_count; 246 unsigned int old_read_count; 247 unsigned int tso_bursts; 248 unsigned int tso_long_headers; 249 unsigned int tso_packets; 250 unsigned int pushes; 251 unsigned int pio_packets; 252 253 /* Members shared between paths and sometimes updated */ 254 unsigned int empty_read_count ____cacheline_aligned_in_smp; 255 #define EFX_EMPTY_COUNT_VALID 0x80000000 256 atomic_t flush_outstanding; 257 }; 258 259 /** 260 * struct efx_rx_buffer - An Efx RX data buffer 261 * @dma_addr: DMA base address of the buffer 262 * @page: The associated page buffer. 263 * Will be %NULL if the buffer slot is currently free. 264 * @page_offset: If pending: offset in @page of DMA base address. 265 * If completed: offset in @page of Ethernet header. 266 * @len: If pending: length for DMA descriptor. 267 * If completed: received length, excluding hash prefix. 268 * @flags: Flags for buffer and packet state. These are only set on the 269 * first buffer of a scattered packet. 270 */ 271 struct efx_rx_buffer { 272 dma_addr_t dma_addr; 273 struct page *page; 274 u16 page_offset; 275 u16 len; 276 u16 flags; 277 }; 278 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001 279 #define EFX_RX_PKT_CSUMMED 0x0002 280 #define EFX_RX_PKT_DISCARD 0x0004 281 #define EFX_RX_PKT_TCP 0x0040 282 #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */ 283 284 /** 285 * struct efx_rx_page_state - Page-based rx buffer state 286 * 287 * Inserted at the start of every page allocated for receive buffers. 288 * Used to facilitate sharing dma mappings between recycled rx buffers 289 * and those passed up to the kernel. 290 * 291 * @dma_addr: The dma address of this page. 292 */ 293 struct efx_rx_page_state { 294 dma_addr_t dma_addr; 295 296 unsigned int __pad[0] ____cacheline_aligned; 297 }; 298 299 /** 300 * struct efx_rx_queue - An Efx RX queue 301 * @efx: The associated Efx NIC 302 * @core_index: Index of network core RX queue. Will be >= 0 iff this 303 * is associated with a real RX queue. 304 * @buffer: The software buffer ring 305 * @rxd: The hardware descriptor ring 306 * @ptr_mask: The size of the ring minus 1. 307 * @refill_enabled: Enable refill whenever fill level is low 308 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as 309 * @rxq_flush_pending. 310 * @added_count: Number of buffers added to the receive queue. 311 * @notified_count: Number of buffers given to NIC (<= @added_count). 312 * @removed_count: Number of buffers removed from the receive queue. 313 * @scatter_n: Used by NIC specific receive code. 314 * @scatter_len: Used by NIC specific receive code. 315 * @page_ring: The ring to store DMA mapped pages for reuse. 316 * @page_add: Counter to calculate the write pointer for the recycle ring. 317 * @page_remove: Counter to calculate the read pointer for the recycle ring. 318 * @page_recycle_count: The number of pages that have been recycled. 319 * @page_recycle_failed: The number of pages that couldn't be recycled because 320 * the kernel still held a reference to them. 321 * @page_recycle_full: The number of pages that were released because the 322 * recycle ring was full. 323 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1. 324 * @max_fill: RX descriptor maximum fill level (<= ring size) 325 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill 326 * (<= @max_fill) 327 * @min_fill: RX descriptor minimum non-zero fill level. 328 * This records the minimum fill level observed when a ring 329 * refill was triggered. 330 * @recycle_count: RX buffer recycle counter. 331 * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). 332 */ 333 struct efx_rx_queue { 334 struct efx_nic *efx; 335 int core_index; 336 struct efx_rx_buffer *buffer; 337 struct efx_special_buffer rxd; 338 unsigned int ptr_mask; 339 bool refill_enabled; 340 bool flush_pending; 341 342 unsigned int added_count; 343 unsigned int notified_count; 344 unsigned int removed_count; 345 unsigned int scatter_n; 346 unsigned int scatter_len; 347 struct page **page_ring; 348 unsigned int page_add; 349 unsigned int page_remove; 350 unsigned int page_recycle_count; 351 unsigned int page_recycle_failed; 352 unsigned int page_recycle_full; 353 unsigned int page_ptr_mask; 354 unsigned int max_fill; 355 unsigned int fast_fill_trigger; 356 unsigned int min_fill; 357 unsigned int min_overfill; 358 unsigned int recycle_count; 359 struct timer_list slow_fill; 360 unsigned int slow_fill_count; 361 }; 362 363 enum efx_sync_events_state { 364 SYNC_EVENTS_DISABLED = 0, 365 SYNC_EVENTS_QUIESCENT, 366 SYNC_EVENTS_REQUESTED, 367 SYNC_EVENTS_VALID, 368 }; 369 370 /** 371 * struct efx_channel - An Efx channel 372 * 373 * A channel comprises an event queue, at least one TX queue, at least 374 * one RX queue, and an associated tasklet for processing the event 375 * queue. 376 * 377 * @efx: Associated Efx NIC 378 * @channel: Channel instance number 379 * @type: Channel type definition 380 * @eventq_init: Event queue initialised flag 381 * @enabled: Channel enabled indicator 382 * @irq: IRQ number (MSI and MSI-X only) 383 * @irq_moderation: IRQ moderation value (in hardware ticks) 384 * @napi_dev: Net device used with NAPI 385 * @napi_str: NAPI control structure 386 * @eventq: Event queue buffer 387 * @eventq_mask: Event queue pointer mask 388 * @eventq_read_ptr: Event queue read pointer 389 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel 390 * @irq_count: Number of IRQs since last adaptive moderation decision 391 * @irq_mod_score: IRQ moderation score 392 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors 393 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors 394 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors 395 * @n_rx_mcast_mismatch: Count of unmatched multicast frames 396 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors 397 * @n_rx_overlength: Count of RX_OVERLENGTH errors 398 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun 399 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to 400 * lack of descriptors 401 * @n_rx_merge_events: Number of RX merged completion events 402 * @n_rx_merge_packets: Number of RX packets completed by merged events 403 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by 404 * __efx_rx_packet(), or zero if there is none 405 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered 406 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0 407 * @rx_queue: RX queue for this channel 408 * @tx_queue: TX queues for this channel 409 * @sync_events_state: Current state of sync events on this channel 410 * @sync_timestamp_major: Major part of the last ptp sync event 411 * @sync_timestamp_minor: Minor part of the last ptp sync event 412 */ 413 struct efx_channel { 414 struct efx_nic *efx; 415 int channel; 416 const struct efx_channel_type *type; 417 bool eventq_init; 418 bool enabled; 419 int irq; 420 unsigned int irq_moderation; 421 struct net_device *napi_dev; 422 struct napi_struct napi_str; 423 struct efx_special_buffer eventq; 424 unsigned int eventq_mask; 425 unsigned int eventq_read_ptr; 426 int event_test_cpu; 427 428 unsigned int irq_count; 429 unsigned int irq_mod_score; 430 #ifdef CONFIG_RFS_ACCEL 431 unsigned int rfs_filters_added; 432 #endif 433 434 unsigned n_rx_tobe_disc; 435 unsigned n_rx_ip_hdr_chksum_err; 436 unsigned n_rx_tcp_udp_chksum_err; 437 unsigned n_rx_mcast_mismatch; 438 unsigned n_rx_frm_trunc; 439 unsigned n_rx_overlength; 440 unsigned n_skbuff_leaks; 441 unsigned int n_rx_nodesc_trunc; 442 unsigned int n_rx_merge_events; 443 unsigned int n_rx_merge_packets; 444 445 unsigned int rx_pkt_n_frags; 446 unsigned int rx_pkt_index; 447 448 struct efx_rx_queue rx_queue; 449 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES]; 450 451 enum efx_sync_events_state sync_events_state; 452 u32 sync_timestamp_major; 453 u32 sync_timestamp_minor; 454 }; 455 456 /** 457 * struct efx_msi_context - Context for each MSI 458 * @efx: The associated NIC 459 * @index: Index of the channel/IRQ 460 * @name: Name of the channel/IRQ 461 * 462 * Unlike &struct efx_channel, this is never reallocated and is always 463 * safe for the IRQ handler to access. 464 */ 465 struct efx_msi_context { 466 struct efx_nic *efx; 467 unsigned int index; 468 char name[IFNAMSIZ + 6]; 469 }; 470 471 /** 472 * struct efx_channel_type - distinguishes traffic and extra channels 473 * @handle_no_channel: Handle failure to allocate an extra channel 474 * @pre_probe: Set up extra state prior to initialisation 475 * @post_remove: Tear down extra state after finalisation, if allocated. 476 * May be called on channels that have not been probed. 477 * @get_name: Generate the channel's name (used for its IRQ handler) 478 * @copy: Copy the channel state prior to reallocation. May be %NULL if 479 * reallocation is not supported. 480 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb() 481 * @keep_eventq: Flag for whether event queue should be kept initialised 482 * while the device is stopped 483 */ 484 struct efx_channel_type { 485 void (*handle_no_channel)(struct efx_nic *); 486 int (*pre_probe)(struct efx_channel *); 487 void (*post_remove)(struct efx_channel *); 488 void (*get_name)(struct efx_channel *, char *buf, size_t len); 489 struct efx_channel *(*copy)(const struct efx_channel *); 490 bool (*receive_skb)(struct efx_channel *, struct sk_buff *); 491 bool keep_eventq; 492 }; 493 494 enum efx_led_mode { 495 EFX_LED_OFF = 0, 496 EFX_LED_ON = 1, 497 EFX_LED_DEFAULT = 2 498 }; 499 500 #define STRING_TABLE_LOOKUP(val, member) \ 501 ((val) < member ## _max) ? member ## _names[val] : "(invalid)" 502 503 extern const char *const efx_loopback_mode_names[]; 504 extern const unsigned int efx_loopback_mode_max; 505 #define LOOPBACK_MODE(efx) \ 506 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) 507 508 extern const char *const efx_reset_type_names[]; 509 extern const unsigned int efx_reset_type_max; 510 #define RESET_TYPE(type) \ 511 STRING_TABLE_LOOKUP(type, efx_reset_type) 512 513 enum efx_int_mode { 514 /* Be careful if altering to correct macro below */ 515 EFX_INT_MODE_MSIX = 0, 516 EFX_INT_MODE_MSI = 1, 517 EFX_INT_MODE_LEGACY = 2, 518 EFX_INT_MODE_MAX /* Insert any new items before this */ 519 }; 520 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) 521 522 enum nic_state { 523 STATE_UNINIT = 0, /* device being probed/removed or is frozen */ 524 STATE_READY = 1, /* hardware ready and netdev registered */ 525 STATE_DISABLED = 2, /* device disabled due to hardware errors */ 526 STATE_RECOVERY = 3, /* device recovering from PCI error */ 527 }; 528 529 /* Forward declaration */ 530 struct efx_nic; 531 532 /* Pseudo bit-mask flow control field */ 533 #define EFX_FC_RX FLOW_CTRL_RX 534 #define EFX_FC_TX FLOW_CTRL_TX 535 #define EFX_FC_AUTO 4 536 537 /** 538 * struct efx_link_state - Current state of the link 539 * @up: Link is up 540 * @fd: Link is full-duplex 541 * @fc: Actual flow control flags 542 * @speed: Link speed (Mbps) 543 */ 544 struct efx_link_state { 545 bool up; 546 bool fd; 547 u8 fc; 548 unsigned int speed; 549 }; 550 551 static inline bool efx_link_state_equal(const struct efx_link_state *left, 552 const struct efx_link_state *right) 553 { 554 return left->up == right->up && left->fd == right->fd && 555 left->fc == right->fc && left->speed == right->speed; 556 } 557 558 /** 559 * struct efx_phy_operations - Efx PHY operations table 560 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, 561 * efx->loopback_modes. 562 * @init: Initialise PHY 563 * @fini: Shut down PHY 564 * @reconfigure: Reconfigure PHY (e.g. for new link parameters) 565 * @poll: Update @link_state and report whether it changed. 566 * Serialised by the mac_lock. 567 * @get_settings: Get ethtool settings. Serialised by the mac_lock. 568 * @set_settings: Set ethtool settings. Serialised by the mac_lock. 569 * @set_npage_adv: Set abilities advertised in (Extended) Next Page 570 * (only needed where AN bit is set in mmds) 571 * @test_alive: Test that PHY is 'alive' (online) 572 * @test_name: Get the name of a PHY-specific test/result 573 * @run_tests: Run tests and record results as appropriate (offline). 574 * Flags are the ethtool tests flags. 575 */ 576 struct efx_phy_operations { 577 int (*probe) (struct efx_nic *efx); 578 int (*init) (struct efx_nic *efx); 579 void (*fini) (struct efx_nic *efx); 580 void (*remove) (struct efx_nic *efx); 581 int (*reconfigure) (struct efx_nic *efx); 582 bool (*poll) (struct efx_nic *efx); 583 void (*get_settings) (struct efx_nic *efx, 584 struct ethtool_cmd *ecmd); 585 int (*set_settings) (struct efx_nic *efx, 586 struct ethtool_cmd *ecmd); 587 void (*set_npage_adv) (struct efx_nic *efx, u32); 588 int (*test_alive) (struct efx_nic *efx); 589 const char *(*test_name) (struct efx_nic *efx, unsigned int index); 590 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); 591 int (*get_module_eeprom) (struct efx_nic *efx, 592 struct ethtool_eeprom *ee, 593 u8 *data); 594 int (*get_module_info) (struct efx_nic *efx, 595 struct ethtool_modinfo *modinfo); 596 }; 597 598 /** 599 * enum efx_phy_mode - PHY operating mode flags 600 * @PHY_MODE_NORMAL: on and should pass traffic 601 * @PHY_MODE_TX_DISABLED: on with TX disabled 602 * @PHY_MODE_LOW_POWER: set to low power through MDIO 603 * @PHY_MODE_OFF: switched off through external control 604 * @PHY_MODE_SPECIAL: on but will not pass traffic 605 */ 606 enum efx_phy_mode { 607 PHY_MODE_NORMAL = 0, 608 PHY_MODE_TX_DISABLED = 1, 609 PHY_MODE_LOW_POWER = 2, 610 PHY_MODE_OFF = 4, 611 PHY_MODE_SPECIAL = 8, 612 }; 613 614 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) 615 { 616 return !!(mode & ~PHY_MODE_TX_DISABLED); 617 } 618 619 /** 620 * struct efx_hw_stat_desc - Description of a hardware statistic 621 * @name: Name of the statistic as visible through ethtool, or %NULL if 622 * it should not be exposed 623 * @dma_width: Width in bits (0 for non-DMA statistics) 624 * @offset: Offset within stats (ignored for non-DMA statistics) 625 */ 626 struct efx_hw_stat_desc { 627 const char *name; 628 u16 dma_width; 629 u16 offset; 630 }; 631 632 /* Number of bits used in a multicast filter hash address */ 633 #define EFX_MCAST_HASH_BITS 8 634 635 /* Number of (single-bit) entries in a multicast filter hash */ 636 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) 637 638 /* An Efx multicast filter hash */ 639 union efx_multicast_hash { 640 u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; 641 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; 642 }; 643 644 struct efx_vf; 645 struct vfdi_status; 646 647 /** 648 * struct efx_nic - an Efx NIC 649 * @name: Device name (net device name or bus id before net device registered) 650 * @pci_dev: The PCI device 651 * @node: List node for maintaning primary/secondary function lists 652 * @primary: &struct efx_nic instance for the primary function of this 653 * controller. May be the same structure, and may be %NULL if no 654 * primary function is bound. Serialised by rtnl_lock. 655 * @secondary_list: List of &struct efx_nic instances for the secondary PCI 656 * functions of the controller, if this is for the primary function. 657 * Serialised by rtnl_lock. 658 * @type: Controller type attributes 659 * @legacy_irq: IRQ number 660 * @workqueue: Workqueue for port reconfigures and the HW monitor. 661 * Work items do not hold and must not acquire RTNL. 662 * @workqueue_name: Name of workqueue 663 * @reset_work: Scheduled reset workitem 664 * @membase_phys: Memory BAR value as physical address 665 * @membase: Memory BAR value 666 * @interrupt_mode: Interrupt mode 667 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds 668 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues 669 * @irq_rx_moderation: IRQ moderation time for RX event queues 670 * @msg_enable: Log message enable flags 671 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock. 672 * @reset_pending: Bitmask for pending resets 673 * @tx_queue: TX DMA queues 674 * @rx_queue: RX DMA queues 675 * @channel: Channels 676 * @msi_context: Context for each MSI 677 * @extra_channel_types: Types of extra (non-traffic) channels that 678 * should be allocated for this NIC 679 * @rxq_entries: Size of receive queues requested by user. 680 * @txq_entries: Size of transmit queues requested by user. 681 * @txq_stop_thresh: TX queue fill level at or above which we stop it. 682 * @txq_wake_thresh: TX queue fill level at or below which we wake it. 683 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches 684 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches 685 * @sram_lim_qw: Qword address limit of SRAM 686 * @next_buffer_table: First available buffer table id 687 * @n_channels: Number of channels in use 688 * @n_rx_channels: Number of channels used for RX (= number of RX queues) 689 * @n_tx_channels: Number of channels used for TX 690 * @rx_ip_align: RX DMA address offset to have IP header aligned in 691 * in accordance with NET_IP_ALIGN 692 * @rx_dma_len: Current maximum RX DMA length 693 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer 694 * @rx_buffer_truesize: Amortised allocation size of an RX buffer, 695 * for use in sk_buff::truesize 696 * @rx_prefix_size: Size of RX prefix before packet data 697 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data 698 * (valid only if @rx_prefix_size != 0; always negative) 699 * @rx_packet_len_offset: Offset of RX packet length from start of packet data 700 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative) 701 * @rx_packet_ts_offset: Offset of timestamp from start of packet data 702 * (valid only if channel->sync_timestamps_enabled; always negative) 703 * @rx_hash_key: Toeplitz hash key for RSS 704 * @rx_indir_table: Indirection table for RSS 705 * @rx_scatter: Scatter mode enabled for receives 706 * @int_error_count: Number of internal errors seen recently 707 * @int_error_expire: Time at which error count will be expired 708 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will 709 * acknowledge but do nothing else. 710 * @irq_status: Interrupt status buffer 711 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 712 * @irq_level: IRQ level/index for IRQs not triggered by an event queue 713 * @selftest_work: Work item for asynchronous self-test 714 * @mtd_list: List of MTDs attached to the NIC 715 * @nic_data: Hardware dependent state 716 * @mcdi: Management-Controller-to-Driver Interface state 717 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, 718 * efx_monitor() and efx_reconfigure_port() 719 * @port_enabled: Port enabled indicator. 720 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and 721 * efx_mac_work() with kernel interfaces. Safe to read under any 722 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must 723 * be held to modify it. 724 * @port_initialized: Port initialized? 725 * @net_dev: Operating system network device. Consider holding the rtnl lock 726 * @stats_buffer: DMA buffer for statistics 727 * @phy_type: PHY type 728 * @phy_op: PHY interface 729 * @phy_data: PHY private data (including PHY-specific stats) 730 * @mdio: PHY MDIO interface 731 * @mdio_bus: PHY MDIO bus ID (only used by Siena) 732 * @phy_mode: PHY operating mode. Serialised by @mac_lock. 733 * @link_advertising: Autonegotiation advertising flags 734 * @link_state: Current state of the link 735 * @n_link_state_changes: Number of times the link has changed state 736 * @unicast_filter: Flag for Falcon-arch simple unicast filter. 737 * Protected by @mac_lock. 738 * @multicast_hash: Multicast hash table for Falcon-arch. 739 * Protected by @mac_lock. 740 * @wanted_fc: Wanted flow control flags 741 * @fc_disable: When non-zero flow control is disabled. Typically used to 742 * ensure that network back pressure doesn't delay dma queue flushes. 743 * Serialised by the rtnl lock. 744 * @mac_work: Work item for changing MAC promiscuity and multicast hash 745 * @loopback_mode: Loopback status 746 * @loopback_modes: Supported loopback mode bitmask 747 * @loopback_selftest: Offline self-test private state 748 * @filter_lock: Filter table lock 749 * @filter_state: Architecture-dependent filter table state 750 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS, 751 * indexed by filter ID 752 * @rps_expire_index: Next index to check for expiry in @rps_flow_id 753 * @active_queues: Count of RX and TX queues that haven't been flushed and drained. 754 * @rxq_flush_pending: Count of number of receive queues that need to be flushed. 755 * Decremented when the efx_flush_rx_queue() is called. 756 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet 757 * completed (either success or failure). Not used when MCDI is used to 758 * flush receive queues. 759 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions. 760 * @vf: Array of &struct efx_vf objects. 761 * @vf_count: Number of VFs intended to be enabled. 762 * @vf_init_count: Number of VFs that have been fully initialised. 763 * @vi_scale: log2 number of vnics per VF. 764 * @vf_buftbl_base: The zeroth buffer table index used to back VF queues. 765 * @vfdi_status: Common VFDI status page to be dmad to VF address space. 766 * @local_addr_list: List of local addresses. Protected by %local_lock. 767 * @local_page_list: List of DMA addressable pages used to broadcast 768 * %local_addr_list. Protected by %local_lock. 769 * @local_lock: Mutex protecting %local_addr_list and %local_page_list. 770 * @peer_work: Work item to broadcast peer addresses to VMs. 771 * @ptp_data: PTP state data 772 * @vpd_sn: Serial number read from VPD 773 * @monitor_work: Hardware monitor workitem 774 * @biu_lock: BIU (bus interface unit) lock 775 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This 776 * field is used by efx_test_interrupts() to verify that an 777 * interrupt has occurred. 778 * @stats_lock: Statistics update lock. Must be held when calling 779 * efx_nic_type::{update,start,stop}_stats. 780 * 781 * This is stored in the private area of the &struct net_device. 782 */ 783 struct efx_nic { 784 /* The following fields should be written very rarely */ 785 786 char name[IFNAMSIZ]; 787 struct list_head node; 788 struct efx_nic *primary; 789 struct list_head secondary_list; 790 struct pci_dev *pci_dev; 791 unsigned int port_num; 792 const struct efx_nic_type *type; 793 int legacy_irq; 794 bool eeh_disabled_legacy_irq; 795 struct workqueue_struct *workqueue; 796 char workqueue_name[16]; 797 struct work_struct reset_work; 798 resource_size_t membase_phys; 799 void __iomem *membase; 800 801 enum efx_int_mode interrupt_mode; 802 unsigned int timer_quantum_ns; 803 bool irq_rx_adaptive; 804 unsigned int irq_rx_moderation; 805 u32 msg_enable; 806 807 enum nic_state state; 808 unsigned long reset_pending; 809 810 struct efx_channel *channel[EFX_MAX_CHANNELS]; 811 struct efx_msi_context msi_context[EFX_MAX_CHANNELS]; 812 const struct efx_channel_type * 813 extra_channel_type[EFX_MAX_EXTRA_CHANNELS]; 814 815 unsigned rxq_entries; 816 unsigned txq_entries; 817 unsigned int txq_stop_thresh; 818 unsigned int txq_wake_thresh; 819 820 unsigned tx_dc_base; 821 unsigned rx_dc_base; 822 unsigned sram_lim_qw; 823 unsigned next_buffer_table; 824 825 unsigned int max_channels; 826 unsigned n_channels; 827 unsigned n_rx_channels; 828 unsigned rss_spread; 829 unsigned tx_channel_offset; 830 unsigned n_tx_channels; 831 unsigned int rx_ip_align; 832 unsigned int rx_dma_len; 833 unsigned int rx_buffer_order; 834 unsigned int rx_buffer_truesize; 835 unsigned int rx_page_buf_step; 836 unsigned int rx_bufs_per_page; 837 unsigned int rx_pages_per_batch; 838 unsigned int rx_prefix_size; 839 int rx_packet_hash_offset; 840 int rx_packet_len_offset; 841 int rx_packet_ts_offset; 842 u8 rx_hash_key[40]; 843 u32 rx_indir_table[128]; 844 bool rx_scatter; 845 846 unsigned int_error_count; 847 unsigned long int_error_expire; 848 849 bool irq_soft_enabled; 850 struct efx_buffer irq_status; 851 unsigned irq_zero_count; 852 unsigned irq_level; 853 struct delayed_work selftest_work; 854 855 #ifdef CONFIG_SFC_MTD 856 struct list_head mtd_list; 857 #endif 858 859 void *nic_data; 860 struct efx_mcdi_data *mcdi; 861 862 struct mutex mac_lock; 863 struct work_struct mac_work; 864 bool port_enabled; 865 866 bool mc_bist_for_other_fn; 867 bool port_initialized; 868 struct net_device *net_dev; 869 870 struct efx_buffer stats_buffer; 871 u64 rx_nodesc_drops_total; 872 u64 rx_nodesc_drops_while_down; 873 bool rx_nodesc_drops_prev_state; 874 875 unsigned int phy_type; 876 const struct efx_phy_operations *phy_op; 877 void *phy_data; 878 struct mdio_if_info mdio; 879 unsigned int mdio_bus; 880 enum efx_phy_mode phy_mode; 881 882 u32 link_advertising; 883 struct efx_link_state link_state; 884 unsigned int n_link_state_changes; 885 886 bool unicast_filter; 887 union efx_multicast_hash multicast_hash; 888 u8 wanted_fc; 889 unsigned fc_disable; 890 891 atomic_t rx_reset; 892 enum efx_loopback_mode loopback_mode; 893 u64 loopback_modes; 894 895 void *loopback_selftest; 896 897 spinlock_t filter_lock; 898 void *filter_state; 899 #ifdef CONFIG_RFS_ACCEL 900 u32 *rps_flow_id; 901 unsigned int rps_expire_index; 902 #endif 903 904 atomic_t active_queues; 905 atomic_t rxq_flush_pending; 906 atomic_t rxq_flush_outstanding; 907 wait_queue_head_t flush_wq; 908 909 #ifdef CONFIG_SFC_SRIOV 910 struct efx_channel *vfdi_channel; 911 struct efx_vf *vf; 912 unsigned vf_count; 913 unsigned vf_init_count; 914 unsigned vi_scale; 915 unsigned vf_buftbl_base; 916 struct efx_buffer vfdi_status; 917 struct list_head local_addr_list; 918 struct list_head local_page_list; 919 struct mutex local_lock; 920 struct work_struct peer_work; 921 #endif 922 923 struct efx_ptp_data *ptp_data; 924 925 char *vpd_sn; 926 927 /* The following fields may be written more often */ 928 929 struct delayed_work monitor_work ____cacheline_aligned_in_smp; 930 spinlock_t biu_lock; 931 int last_irq_cpu; 932 spinlock_t stats_lock; 933 }; 934 935 static inline int efx_dev_registered(struct efx_nic *efx) 936 { 937 return efx->net_dev->reg_state == NETREG_REGISTERED; 938 } 939 940 static inline unsigned int efx_port_num(struct efx_nic *efx) 941 { 942 return efx->port_num; 943 } 944 945 struct efx_mtd_partition { 946 struct list_head node; 947 struct mtd_info mtd; 948 const char *dev_type_name; 949 const char *type_name; 950 char name[IFNAMSIZ + 20]; 951 }; 952 953 /** 954 * struct efx_nic_type - Efx device type definition 955 * @mem_map_size: Get memory BAR mapped size 956 * @probe: Probe the controller 957 * @remove: Free resources allocated by probe() 958 * @init: Initialise the controller 959 * @dimension_resources: Dimension controller resources (buffer table, 960 * and VIs once the available interrupt resources are clear) 961 * @fini: Shut down the controller 962 * @monitor: Periodic function for polling link state and hardware monitor 963 * @map_reset_reason: Map ethtool reset reason to a reset method 964 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible 965 * @reset: Reset the controller hardware and possibly the PHY. This will 966 * be called while the controller is uninitialised. 967 * @probe_port: Probe the MAC and PHY 968 * @remove_port: Free resources allocated by probe_port() 969 * @handle_global_event: Handle a "global" event (may be %NULL) 970 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues) 971 * @prepare_flush: Prepare the hardware for flushing the DMA queues 972 * (for Falcon architecture) 973 * @finish_flush: Clean up after flushing the DMA queues (for Falcon 974 * architecture) 975 * @describe_stats: Describe statistics for ethtool 976 * @update_stats: Update statistics not provided by event handling. 977 * Either argument may be %NULL. 978 * @start_stats: Start the regular fetching of statistics 979 * @pull_stats: Pull stats from the NIC and wait until they arrive. 980 * @stop_stats: Stop the regular fetching of statistics 981 * @set_id_led: Set state of identifying LED or revert to automatic function 982 * @push_irq_moderation: Apply interrupt moderation value 983 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY 984 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL) 985 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings 986 * to the hardware. Serialised by the mac_lock. 987 * @check_mac_fault: Check MAC fault state. True if fault present. 988 * @get_wol: Get WoL configuration from driver state 989 * @set_wol: Push WoL configuration to the NIC 990 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) 991 * @test_chip: Test registers. May use efx_farch_test_registers(), and is 992 * expected to reset the NIC. 993 * @test_nvram: Test validity of NVRAM contents 994 * @mcdi_request: Send an MCDI request with the given header and SDU. 995 * The SDU length may be any value from 0 up to the protocol- 996 * defined maximum, but its buffer will be padded to a multiple 997 * of 4 bytes. 998 * @mcdi_poll_response: Test whether an MCDI response is available. 999 * @mcdi_read_response: Read the MCDI response PDU. The offset will 1000 * be a multiple of 4. The length may not be, but the buffer 1001 * will be padded so it is safe to round up. 1002 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so, 1003 * return an appropriate error code for aborting any current 1004 * request; otherwise return 0. 1005 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must 1006 * be separately enabled after this. 1007 * @irq_test_generate: Generate a test IRQ 1008 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event 1009 * queue must be separately disabled before this. 1010 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is 1011 * a pointer to the &struct efx_msi_context for the channel. 1012 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument 1013 * is a pointer to the &struct efx_nic. 1014 * @tx_probe: Allocate resources for TX queue 1015 * @tx_init: Initialise TX queue on the NIC 1016 * @tx_remove: Free resources for TX queue 1017 * @tx_write: Write TX descriptors and doorbell 1018 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC 1019 * @rx_probe: Allocate resources for RX queue 1020 * @rx_init: Initialise RX queue on the NIC 1021 * @rx_remove: Free resources for RX queue 1022 * @rx_write: Write RX descriptors and doorbell 1023 * @rx_defer_refill: Generate a refill reminder event 1024 * @ev_probe: Allocate resources for event queue 1025 * @ev_init: Initialise event queue on the NIC 1026 * @ev_fini: Deinitialise event queue on the NIC 1027 * @ev_remove: Free resources for event queue 1028 * @ev_process: Process events for a queue, up to the given NAPI quota 1029 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ 1030 * @ev_test_generate: Generate a test event 1031 * @filter_table_probe: Probe filter capabilities and set up filter software state 1032 * @filter_table_restore: Restore filters removed from hardware 1033 * @filter_table_remove: Remove filters from hardware and tear down software state 1034 * @filter_update_rx_scatter: Update filters after change to rx scatter setting 1035 * @filter_insert: add or replace a filter 1036 * @filter_remove_safe: remove a filter by ID, carefully 1037 * @filter_get_safe: retrieve a filter by ID, carefully 1038 * @filter_clear_rx: Remove all RX filters whose priority is less than or 1039 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO 1040 * @filter_count_rx_used: Get the number of filters in use at a given priority 1041 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1 1042 * @filter_get_rx_ids: Get list of RX filters at a given priority 1043 * @filter_rfs_insert: Add or replace a filter for RFS. This must be 1044 * atomic. The hardware change may be asynchronous but should 1045 * not be delayed for long. It may fail if this can't be done 1046 * atomically. 1047 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS. 1048 * This must check whether the specified table entry is used by RFS 1049 * and that rps_may_expire_flow() returns true for it. 1050 * @mtd_probe: Probe and add MTD partitions associated with this net device, 1051 * using efx_mtd_add() 1052 * @mtd_rename: Set an MTD partition name using the net device name 1053 * @mtd_read: Read from an MTD partition 1054 * @mtd_erase: Erase part of an MTD partition 1055 * @mtd_write: Write to an MTD partition 1056 * @mtd_sync: Wait for write-back to complete on MTD partition. This 1057 * also notifies the driver that a writer has finished using this 1058 * partition. 1059 * @ptp_write_host_time: Send host time to MC as part of sync protocol 1060 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX 1061 * timestamping, possibly only temporarily for the purposes of a reset. 1062 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags 1063 * and tx_type will already have been validated but this operation 1064 * must validate and update rx_filter. 1065 * @revision: Hardware architecture revision 1066 * @txd_ptr_tbl_base: TX descriptor ring base address 1067 * @rxd_ptr_tbl_base: RX descriptor ring base address 1068 * @buf_tbl_base: Buffer table base address 1069 * @evq_ptr_tbl_base: Event queue pointer table base address 1070 * @evq_rptr_tbl_base: Event queue read-pointer table base address 1071 * @max_dma_mask: Maximum possible DMA mask 1072 * @rx_prefix_size: Size of RX prefix before packet data 1073 * @rx_hash_offset: Offset of RX flow hash within prefix 1074 * @rx_ts_offset: Offset of timestamp within prefix 1075 * @rx_buffer_padding: Size of padding at end of RX packet 1076 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers 1077 * @always_rx_scatter: NIC will always scatter packets to multiple buffers 1078 * @max_interrupt_mode: Highest capability interrupt mode supported 1079 * from &enum efx_init_mode. 1080 * @timer_period_max: Maximum period of interrupt timer (in ticks) 1081 * @offload_features: net_device feature flags for protocol offload 1082 * features implemented in hardware 1083 * @mcdi_max_ver: Maximum MCDI version supported 1084 * @hwtstamp_filters: Mask of hardware timestamp filter types supported 1085 */ 1086 struct efx_nic_type { 1087 unsigned int (*mem_map_size)(struct efx_nic *efx); 1088 int (*probe)(struct efx_nic *efx); 1089 void (*remove)(struct efx_nic *efx); 1090 int (*init)(struct efx_nic *efx); 1091 int (*dimension_resources)(struct efx_nic *efx); 1092 void (*fini)(struct efx_nic *efx); 1093 void (*monitor)(struct efx_nic *efx); 1094 enum reset_type (*map_reset_reason)(enum reset_type reason); 1095 int (*map_reset_flags)(u32 *flags); 1096 int (*reset)(struct efx_nic *efx, enum reset_type method); 1097 int (*probe_port)(struct efx_nic *efx); 1098 void (*remove_port)(struct efx_nic *efx); 1099 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *); 1100 int (*fini_dmaq)(struct efx_nic *efx); 1101 void (*prepare_flush)(struct efx_nic *efx); 1102 void (*finish_flush)(struct efx_nic *efx); 1103 size_t (*describe_stats)(struct efx_nic *efx, u8 *names); 1104 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats, 1105 struct rtnl_link_stats64 *core_stats); 1106 void (*start_stats)(struct efx_nic *efx); 1107 void (*pull_stats)(struct efx_nic *efx); 1108 void (*stop_stats)(struct efx_nic *efx); 1109 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); 1110 void (*push_irq_moderation)(struct efx_channel *channel); 1111 int (*reconfigure_port)(struct efx_nic *efx); 1112 void (*prepare_enable_fc_tx)(struct efx_nic *efx); 1113 int (*reconfigure_mac)(struct efx_nic *efx); 1114 bool (*check_mac_fault)(struct efx_nic *efx); 1115 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); 1116 int (*set_wol)(struct efx_nic *efx, u32 type); 1117 void (*resume_wol)(struct efx_nic *efx); 1118 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests); 1119 int (*test_nvram)(struct efx_nic *efx); 1120 void (*mcdi_request)(struct efx_nic *efx, 1121 const efx_dword_t *hdr, size_t hdr_len, 1122 const efx_dword_t *sdu, size_t sdu_len); 1123 bool (*mcdi_poll_response)(struct efx_nic *efx); 1124 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu, 1125 size_t pdu_offset, size_t pdu_len); 1126 int (*mcdi_poll_reboot)(struct efx_nic *efx); 1127 void (*irq_enable_master)(struct efx_nic *efx); 1128 void (*irq_test_generate)(struct efx_nic *efx); 1129 void (*irq_disable_non_ev)(struct efx_nic *efx); 1130 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id); 1131 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id); 1132 int (*tx_probe)(struct efx_tx_queue *tx_queue); 1133 void (*tx_init)(struct efx_tx_queue *tx_queue); 1134 void (*tx_remove)(struct efx_tx_queue *tx_queue); 1135 void (*tx_write)(struct efx_tx_queue *tx_queue); 1136 void (*rx_push_rss_config)(struct efx_nic *efx); 1137 int (*rx_probe)(struct efx_rx_queue *rx_queue); 1138 void (*rx_init)(struct efx_rx_queue *rx_queue); 1139 void (*rx_remove)(struct efx_rx_queue *rx_queue); 1140 void (*rx_write)(struct efx_rx_queue *rx_queue); 1141 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue); 1142 int (*ev_probe)(struct efx_channel *channel); 1143 int (*ev_init)(struct efx_channel *channel); 1144 void (*ev_fini)(struct efx_channel *channel); 1145 void (*ev_remove)(struct efx_channel *channel); 1146 int (*ev_process)(struct efx_channel *channel, int quota); 1147 void (*ev_read_ack)(struct efx_channel *channel); 1148 void (*ev_test_generate)(struct efx_channel *channel); 1149 int (*filter_table_probe)(struct efx_nic *efx); 1150 void (*filter_table_restore)(struct efx_nic *efx); 1151 void (*filter_table_remove)(struct efx_nic *efx); 1152 void (*filter_update_rx_scatter)(struct efx_nic *efx); 1153 s32 (*filter_insert)(struct efx_nic *efx, 1154 struct efx_filter_spec *spec, bool replace); 1155 int (*filter_remove_safe)(struct efx_nic *efx, 1156 enum efx_filter_priority priority, 1157 u32 filter_id); 1158 int (*filter_get_safe)(struct efx_nic *efx, 1159 enum efx_filter_priority priority, 1160 u32 filter_id, struct efx_filter_spec *); 1161 int (*filter_clear_rx)(struct efx_nic *efx, 1162 enum efx_filter_priority priority); 1163 u32 (*filter_count_rx_used)(struct efx_nic *efx, 1164 enum efx_filter_priority priority); 1165 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx); 1166 s32 (*filter_get_rx_ids)(struct efx_nic *efx, 1167 enum efx_filter_priority priority, 1168 u32 *buf, u32 size); 1169 #ifdef CONFIG_RFS_ACCEL 1170 s32 (*filter_rfs_insert)(struct efx_nic *efx, 1171 struct efx_filter_spec *spec); 1172 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id, 1173 unsigned int index); 1174 #endif 1175 #ifdef CONFIG_SFC_MTD 1176 int (*mtd_probe)(struct efx_nic *efx); 1177 void (*mtd_rename)(struct efx_mtd_partition *part); 1178 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len, 1179 size_t *retlen, u8 *buffer); 1180 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len); 1181 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len, 1182 size_t *retlen, const u8 *buffer); 1183 int (*mtd_sync)(struct mtd_info *mtd); 1184 #endif 1185 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time); 1186 int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp); 1187 int (*ptp_set_ts_config)(struct efx_nic *efx, 1188 struct hwtstamp_config *init); 1189 1190 int revision; 1191 unsigned int txd_ptr_tbl_base; 1192 unsigned int rxd_ptr_tbl_base; 1193 unsigned int buf_tbl_base; 1194 unsigned int evq_ptr_tbl_base; 1195 unsigned int evq_rptr_tbl_base; 1196 u64 max_dma_mask; 1197 unsigned int rx_prefix_size; 1198 unsigned int rx_hash_offset; 1199 unsigned int rx_ts_offset; 1200 unsigned int rx_buffer_padding; 1201 bool can_rx_scatter; 1202 bool always_rx_scatter; 1203 unsigned int max_interrupt_mode; 1204 unsigned int timer_period_max; 1205 netdev_features_t offload_features; 1206 int mcdi_max_ver; 1207 unsigned int max_rx_ip_filters; 1208 u32 hwtstamp_filters; 1209 }; 1210 1211 /************************************************************************** 1212 * 1213 * Prototypes and inline functions 1214 * 1215 *************************************************************************/ 1216 1217 static inline struct efx_channel * 1218 efx_get_channel(struct efx_nic *efx, unsigned index) 1219 { 1220 EFX_BUG_ON_PARANOID(index >= efx->n_channels); 1221 return efx->channel[index]; 1222 } 1223 1224 /* Iterate over all used channels */ 1225 #define efx_for_each_channel(_channel, _efx) \ 1226 for (_channel = (_efx)->channel[0]; \ 1227 _channel; \ 1228 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ 1229 (_efx)->channel[_channel->channel + 1] : NULL) 1230 1231 /* Iterate over all used channels in reverse */ 1232 #define efx_for_each_channel_rev(_channel, _efx) \ 1233 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \ 1234 _channel; \ 1235 _channel = _channel->channel ? \ 1236 (_efx)->channel[_channel->channel - 1] : NULL) 1237 1238 static inline struct efx_tx_queue * 1239 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) 1240 { 1241 EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels || 1242 type >= EFX_TXQ_TYPES); 1243 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type]; 1244 } 1245 1246 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel) 1247 { 1248 return channel->channel - channel->efx->tx_channel_offset < 1249 channel->efx->n_tx_channels; 1250 } 1251 1252 static inline struct efx_tx_queue * 1253 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type) 1254 { 1255 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) || 1256 type >= EFX_TXQ_TYPES); 1257 return &channel->tx_queue[type]; 1258 } 1259 1260 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue) 1261 { 1262 return !(tx_queue->efx->net_dev->num_tc < 2 && 1263 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI); 1264 } 1265 1266 /* Iterate over all TX queues belonging to a channel */ 1267 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ 1268 if (!efx_channel_has_tx_queues(_channel)) \ 1269 ; \ 1270 else \ 1271 for (_tx_queue = (_channel)->tx_queue; \ 1272 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \ 1273 efx_tx_queue_used(_tx_queue); \ 1274 _tx_queue++) 1275 1276 /* Iterate over all possible TX queues belonging to a channel */ 1277 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \ 1278 if (!efx_channel_has_tx_queues(_channel)) \ 1279 ; \ 1280 else \ 1281 for (_tx_queue = (_channel)->tx_queue; \ 1282 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ 1283 _tx_queue++) 1284 1285 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel) 1286 { 1287 return channel->rx_queue.core_index >= 0; 1288 } 1289 1290 static inline struct efx_rx_queue * 1291 efx_channel_get_rx_queue(struct efx_channel *channel) 1292 { 1293 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel)); 1294 return &channel->rx_queue; 1295 } 1296 1297 /* Iterate over all RX queues belonging to a channel */ 1298 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ 1299 if (!efx_channel_has_rx_queue(_channel)) \ 1300 ; \ 1301 else \ 1302 for (_rx_queue = &(_channel)->rx_queue; \ 1303 _rx_queue; \ 1304 _rx_queue = NULL) 1305 1306 static inline struct efx_channel * 1307 efx_rx_queue_channel(struct efx_rx_queue *rx_queue) 1308 { 1309 return container_of(rx_queue, struct efx_channel, rx_queue); 1310 } 1311 1312 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) 1313 { 1314 return efx_rx_queue_channel(rx_queue)->channel; 1315 } 1316 1317 /* Returns a pointer to the specified receive buffer in the RX 1318 * descriptor queue. 1319 */ 1320 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, 1321 unsigned int index) 1322 { 1323 return &rx_queue->buffer[index]; 1324 } 1325 1326 /** 1327 * EFX_MAX_FRAME_LEN - calculate maximum frame length 1328 * 1329 * This calculates the maximum frame length that will be used for a 1330 * given MTU. The frame length will be equal to the MTU plus a 1331 * constant amount of header space and padding. This is the quantity 1332 * that the net driver will program into the MAC as the maximum frame 1333 * length. 1334 * 1335 * The 10G MAC requires 8-byte alignment on the frame 1336 * length, so we round up to the nearest 8. 1337 * 1338 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an 1339 * XGMII cycle). If the frame length reaches the maximum value in the 1340 * same cycle, the XMAC can miss the IPG altogether. We work around 1341 * this by adding a further 16 bytes. 1342 */ 1343 #define EFX_MAX_FRAME_LEN(mtu) \ 1344 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16) 1345 1346 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb) 1347 { 1348 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP; 1349 } 1350 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb) 1351 { 1352 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1353 } 1354 1355 #endif /* EFX_NET_DRIVER_H */ 1356