1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 /* Common definitions for all Efx net driver code */ 12 13 #ifndef EFX_NET_DRIVER_H 14 #define EFX_NET_DRIVER_H 15 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/ethtool.h> 19 #include <linux/if_vlan.h> 20 #include <linux/timer.h> 21 #include <linux/mdio.h> 22 #include <linux/list.h> 23 #include <linux/pci.h> 24 #include <linux/device.h> 25 #include <linux/highmem.h> 26 #include <linux/workqueue.h> 27 #include <linux/mutex.h> 28 #include <linux/rwsem.h> 29 #include <linux/vmalloc.h> 30 #include <linux/i2c.h> 31 #include <linux/mtd/mtd.h> 32 #include <net/busy_poll.h> 33 34 #include "enum.h" 35 #include "bitfield.h" 36 #include "filter.h" 37 38 /************************************************************************** 39 * 40 * Build definitions 41 * 42 **************************************************************************/ 43 44 #define EFX_DRIVER_VERSION "4.0" 45 46 #ifdef DEBUG 47 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) 48 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) 49 #else 50 #define EFX_BUG_ON_PARANOID(x) do {} while (0) 51 #define EFX_WARN_ON_PARANOID(x) do {} while (0) 52 #endif 53 54 /************************************************************************** 55 * 56 * Efx data structures 57 * 58 **************************************************************************/ 59 60 #define EFX_MAX_CHANNELS 32U 61 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS 62 #define EFX_EXTRA_CHANNEL_IOV 0 63 #define EFX_EXTRA_CHANNEL_PTP 1 64 #define EFX_MAX_EXTRA_CHANNELS 2U 65 66 /* Checksum generation is a per-queue option in hardware, so each 67 * queue visible to the networking core is backed by two hardware TX 68 * queues. */ 69 #define EFX_MAX_TX_TC 2 70 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS) 71 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */ 72 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */ 73 #define EFX_TXQ_TYPES 4 74 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS) 75 76 /* Maximum possible MTU the driver supports */ 77 #define EFX_MAX_MTU (9 * 1024) 78 79 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page, 80 * and should be a multiple of the cache line size. 81 */ 82 #define EFX_RX_USR_BUF_SIZE (2048 - 256) 83 84 /* If possible, we should ensure cache line alignment at start and end 85 * of every buffer. Otherwise, we just need to ensure 4-byte 86 * alignment of the network header. 87 */ 88 #if NET_IP_ALIGN == 0 89 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES 90 #else 91 #define EFX_RX_BUF_ALIGNMENT 4 92 #endif 93 94 /* Forward declare Precision Time Protocol (PTP) support structure. */ 95 struct efx_ptp_data; 96 struct hwtstamp_config; 97 98 struct efx_self_tests; 99 100 /** 101 * struct efx_buffer - A general-purpose DMA buffer 102 * @addr: host base address of the buffer 103 * @dma_addr: DMA base address of the buffer 104 * @len: Buffer length, in bytes 105 * 106 * The NIC uses these buffers for its interrupt status registers and 107 * MAC stats dumps. 108 */ 109 struct efx_buffer { 110 void *addr; 111 dma_addr_t dma_addr; 112 unsigned int len; 113 }; 114 115 /** 116 * struct efx_special_buffer - DMA buffer entered into buffer table 117 * @buf: Standard &struct efx_buffer 118 * @index: Buffer index within controller;s buffer table 119 * @entries: Number of buffer table entries 120 * 121 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE. 122 * Event and descriptor rings are addressed via one or more buffer 123 * table entries (and so can be physically non-contiguous, although we 124 * currently do not take advantage of that). On Falcon and Siena we 125 * have to take care of allocating and initialising the entries 126 * ourselves. On later hardware this is managed by the firmware and 127 * @index and @entries are left as 0. 128 */ 129 struct efx_special_buffer { 130 struct efx_buffer buf; 131 unsigned int index; 132 unsigned int entries; 133 }; 134 135 /** 136 * struct efx_tx_buffer - buffer state for a TX descriptor 137 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be 138 * freed when descriptor completes 139 * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be 140 * freed when descriptor completes. 141 * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor. 142 * @dma_addr: DMA address of the fragment. 143 * @flags: Flags for allocation and DMA mapping type 144 * @len: Length of this fragment. 145 * This field is zero when the queue slot is empty. 146 * @unmap_len: Length of this fragment to unmap 147 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping. 148 * Only valid if @unmap_len != 0. 149 */ 150 struct efx_tx_buffer { 151 union { 152 const struct sk_buff *skb; 153 void *heap_buf; 154 }; 155 union { 156 efx_qword_t option; 157 dma_addr_t dma_addr; 158 }; 159 unsigned short flags; 160 unsigned short len; 161 unsigned short unmap_len; 162 unsigned short dma_offset; 163 }; 164 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */ 165 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */ 166 #define EFX_TX_BUF_HEAP 4 /* buffer was allocated with kmalloc() */ 167 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */ 168 #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */ 169 170 /** 171 * struct efx_tx_queue - An Efx TX queue 172 * 173 * This is a ring buffer of TX fragments. 174 * Since the TX completion path always executes on the same 175 * CPU and the xmit path can operate on different CPUs, 176 * performance is increased by ensuring that the completion 177 * path and the xmit path operate on different cache lines. 178 * This is particularly important if the xmit path is always 179 * executing on one CPU which is different from the completion 180 * path. There is also a cache line for members which are 181 * read but not written on the fast path. 182 * 183 * @efx: The associated Efx NIC 184 * @queue: DMA queue number 185 * @channel: The associated channel 186 * @core_txq: The networking core TX queue structure 187 * @buffer: The software buffer ring 188 * @tsoh_page: Array of pages of TSO header buffers 189 * @txd: The hardware descriptor ring 190 * @ptr_mask: The size of the ring minus 1. 191 * @piobuf: PIO buffer region for this TX queue (shared with its partner). 192 * Size of the region is efx_piobuf_size. 193 * @piobuf_offset: Buffer offset to be specified in PIO descriptors 194 * @initialised: Has hardware queue been initialised? 195 * @read_count: Current read pointer. 196 * This is the number of buffers that have been removed from both rings. 197 * @old_write_count: The value of @write_count when last checked. 198 * This is here for performance reasons. The xmit path will 199 * only get the up-to-date value of @write_count if this 200 * variable indicates that the queue is empty. This is to 201 * avoid cache-line ping-pong between the xmit path and the 202 * completion path. 203 * @merge_events: Number of TX merged completion events 204 * @insert_count: Current insert pointer 205 * This is the number of buffers that have been added to the 206 * software ring. 207 * @write_count: Current write pointer 208 * This is the number of buffers that have been added to the 209 * hardware ring. 210 * @old_read_count: The value of read_count when last checked. 211 * This is here for performance reasons. The xmit path will 212 * only get the up-to-date value of read_count if this 213 * variable indicates that the queue is full. This is to 214 * avoid cache-line ping-pong between the xmit path and the 215 * completion path. 216 * @tso_bursts: Number of times TSO xmit invoked by kernel 217 * @tso_long_headers: Number of packets with headers too long for standard 218 * blocks 219 * @tso_packets: Number of packets via the TSO xmit path 220 * @pushes: Number of times the TX push feature has been used 221 * @pio_packets: Number of times the TX PIO feature has been used 222 * @xmit_more_available: Are any packets waiting to be pushed to the NIC 223 * @empty_read_count: If the completion path has seen the queue as empty 224 * and the transmission path has not yet checked this, the value of 225 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0. 226 */ 227 struct efx_tx_queue { 228 /* Members which don't change on the fast path */ 229 struct efx_nic *efx ____cacheline_aligned_in_smp; 230 unsigned queue; 231 struct efx_channel *channel; 232 struct netdev_queue *core_txq; 233 struct efx_tx_buffer *buffer; 234 struct efx_buffer *tsoh_page; 235 struct efx_special_buffer txd; 236 unsigned int ptr_mask; 237 void __iomem *piobuf; 238 unsigned int piobuf_offset; 239 bool initialised; 240 241 /* Members used mainly on the completion path */ 242 unsigned int read_count ____cacheline_aligned_in_smp; 243 unsigned int old_write_count; 244 unsigned int merge_events; 245 unsigned int bytes_compl; 246 unsigned int pkts_compl; 247 248 /* Members used only on the xmit path */ 249 unsigned int insert_count ____cacheline_aligned_in_smp; 250 unsigned int write_count; 251 unsigned int old_read_count; 252 unsigned int tso_bursts; 253 unsigned int tso_long_headers; 254 unsigned int tso_packets; 255 unsigned int pushes; 256 unsigned int pio_packets; 257 bool xmit_more_available; 258 /* Statistics to supplement MAC stats */ 259 unsigned long tx_packets; 260 261 /* Members shared between paths and sometimes updated */ 262 unsigned int empty_read_count ____cacheline_aligned_in_smp; 263 #define EFX_EMPTY_COUNT_VALID 0x80000000 264 atomic_t flush_outstanding; 265 }; 266 267 /** 268 * struct efx_rx_buffer - An Efx RX data buffer 269 * @dma_addr: DMA base address of the buffer 270 * @page: The associated page buffer. 271 * Will be %NULL if the buffer slot is currently free. 272 * @page_offset: If pending: offset in @page of DMA base address. 273 * If completed: offset in @page of Ethernet header. 274 * @len: If pending: length for DMA descriptor. 275 * If completed: received length, excluding hash prefix. 276 * @flags: Flags for buffer and packet state. These are only set on the 277 * first buffer of a scattered packet. 278 */ 279 struct efx_rx_buffer { 280 dma_addr_t dma_addr; 281 struct page *page; 282 u16 page_offset; 283 u16 len; 284 u16 flags; 285 }; 286 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001 287 #define EFX_RX_PKT_CSUMMED 0x0002 288 #define EFX_RX_PKT_DISCARD 0x0004 289 #define EFX_RX_PKT_TCP 0x0040 290 #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */ 291 292 /** 293 * struct efx_rx_page_state - Page-based rx buffer state 294 * 295 * Inserted at the start of every page allocated for receive buffers. 296 * Used to facilitate sharing dma mappings between recycled rx buffers 297 * and those passed up to the kernel. 298 * 299 * @dma_addr: The dma address of this page. 300 */ 301 struct efx_rx_page_state { 302 dma_addr_t dma_addr; 303 304 unsigned int __pad[0] ____cacheline_aligned; 305 }; 306 307 /** 308 * struct efx_rx_queue - An Efx RX queue 309 * @efx: The associated Efx NIC 310 * @core_index: Index of network core RX queue. Will be >= 0 iff this 311 * is associated with a real RX queue. 312 * @buffer: The software buffer ring 313 * @rxd: The hardware descriptor ring 314 * @ptr_mask: The size of the ring minus 1. 315 * @refill_enabled: Enable refill whenever fill level is low 316 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as 317 * @rxq_flush_pending. 318 * @added_count: Number of buffers added to the receive queue. 319 * @notified_count: Number of buffers given to NIC (<= @added_count). 320 * @removed_count: Number of buffers removed from the receive queue. 321 * @scatter_n: Used by NIC specific receive code. 322 * @scatter_len: Used by NIC specific receive code. 323 * @page_ring: The ring to store DMA mapped pages for reuse. 324 * @page_add: Counter to calculate the write pointer for the recycle ring. 325 * @page_remove: Counter to calculate the read pointer for the recycle ring. 326 * @page_recycle_count: The number of pages that have been recycled. 327 * @page_recycle_failed: The number of pages that couldn't be recycled because 328 * the kernel still held a reference to them. 329 * @page_recycle_full: The number of pages that were released because the 330 * recycle ring was full. 331 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1. 332 * @max_fill: RX descriptor maximum fill level (<= ring size) 333 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill 334 * (<= @max_fill) 335 * @min_fill: RX descriptor minimum non-zero fill level. 336 * This records the minimum fill level observed when a ring 337 * refill was triggered. 338 * @recycle_count: RX buffer recycle counter. 339 * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). 340 */ 341 struct efx_rx_queue { 342 struct efx_nic *efx; 343 int core_index; 344 struct efx_rx_buffer *buffer; 345 struct efx_special_buffer rxd; 346 unsigned int ptr_mask; 347 bool refill_enabled; 348 bool flush_pending; 349 350 unsigned int added_count; 351 unsigned int notified_count; 352 unsigned int removed_count; 353 unsigned int scatter_n; 354 unsigned int scatter_len; 355 struct page **page_ring; 356 unsigned int page_add; 357 unsigned int page_remove; 358 unsigned int page_recycle_count; 359 unsigned int page_recycle_failed; 360 unsigned int page_recycle_full; 361 unsigned int page_ptr_mask; 362 unsigned int max_fill; 363 unsigned int fast_fill_trigger; 364 unsigned int min_fill; 365 unsigned int min_overfill; 366 unsigned int recycle_count; 367 struct timer_list slow_fill; 368 unsigned int slow_fill_count; 369 /* Statistics to supplement MAC stats */ 370 unsigned long rx_packets; 371 }; 372 373 enum efx_sync_events_state { 374 SYNC_EVENTS_DISABLED = 0, 375 SYNC_EVENTS_QUIESCENT, 376 SYNC_EVENTS_REQUESTED, 377 SYNC_EVENTS_VALID, 378 }; 379 380 /** 381 * struct efx_channel - An Efx channel 382 * 383 * A channel comprises an event queue, at least one TX queue, at least 384 * one RX queue, and an associated tasklet for processing the event 385 * queue. 386 * 387 * @efx: Associated Efx NIC 388 * @channel: Channel instance number 389 * @type: Channel type definition 390 * @eventq_init: Event queue initialised flag 391 * @enabled: Channel enabled indicator 392 * @irq: IRQ number (MSI and MSI-X only) 393 * @irq_moderation: IRQ moderation value (in hardware ticks) 394 * @napi_dev: Net device used with NAPI 395 * @napi_str: NAPI control structure 396 * @state: state for NAPI vs busy polling 397 * @state_lock: lock protecting @state 398 * @eventq: Event queue buffer 399 * @eventq_mask: Event queue pointer mask 400 * @eventq_read_ptr: Event queue read pointer 401 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel 402 * @irq_count: Number of IRQs since last adaptive moderation decision 403 * @irq_mod_score: IRQ moderation score 404 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors 405 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors 406 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors 407 * @n_rx_mcast_mismatch: Count of unmatched multicast frames 408 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors 409 * @n_rx_overlength: Count of RX_OVERLENGTH errors 410 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun 411 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to 412 * lack of descriptors 413 * @n_rx_merge_events: Number of RX merged completion events 414 * @n_rx_merge_packets: Number of RX packets completed by merged events 415 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by 416 * __efx_rx_packet(), or zero if there is none 417 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered 418 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0 419 * @rx_queue: RX queue for this channel 420 * @tx_queue: TX queues for this channel 421 * @sync_events_state: Current state of sync events on this channel 422 * @sync_timestamp_major: Major part of the last ptp sync event 423 * @sync_timestamp_minor: Minor part of the last ptp sync event 424 */ 425 struct efx_channel { 426 struct efx_nic *efx; 427 int channel; 428 const struct efx_channel_type *type; 429 bool eventq_init; 430 bool enabled; 431 int irq; 432 unsigned int irq_moderation; 433 struct net_device *napi_dev; 434 struct napi_struct napi_str; 435 #ifdef CONFIG_NET_RX_BUSY_POLL 436 unsigned long busy_poll_state; 437 #endif 438 struct efx_special_buffer eventq; 439 unsigned int eventq_mask; 440 unsigned int eventq_read_ptr; 441 int event_test_cpu; 442 443 unsigned int irq_count; 444 unsigned int irq_mod_score; 445 #ifdef CONFIG_RFS_ACCEL 446 unsigned int rfs_filters_added; 447 #endif 448 449 unsigned n_rx_tobe_disc; 450 unsigned n_rx_ip_hdr_chksum_err; 451 unsigned n_rx_tcp_udp_chksum_err; 452 unsigned n_rx_mcast_mismatch; 453 unsigned n_rx_frm_trunc; 454 unsigned n_rx_overlength; 455 unsigned n_skbuff_leaks; 456 unsigned int n_rx_nodesc_trunc; 457 unsigned int n_rx_merge_events; 458 unsigned int n_rx_merge_packets; 459 460 unsigned int rx_pkt_n_frags; 461 unsigned int rx_pkt_index; 462 463 struct efx_rx_queue rx_queue; 464 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES]; 465 466 enum efx_sync_events_state sync_events_state; 467 u32 sync_timestamp_major; 468 u32 sync_timestamp_minor; 469 }; 470 471 #ifdef CONFIG_NET_RX_BUSY_POLL 472 enum efx_channel_busy_poll_state { 473 EFX_CHANNEL_STATE_IDLE = 0, 474 EFX_CHANNEL_STATE_NAPI = BIT(0), 475 EFX_CHANNEL_STATE_NAPI_REQ_BIT = 1, 476 EFX_CHANNEL_STATE_NAPI_REQ = BIT(1), 477 EFX_CHANNEL_STATE_POLL_BIT = 2, 478 EFX_CHANNEL_STATE_POLL = BIT(2), 479 EFX_CHANNEL_STATE_DISABLE_BIT = 3, 480 }; 481 482 static inline void efx_channel_busy_poll_init(struct efx_channel *channel) 483 { 484 WRITE_ONCE(channel->busy_poll_state, EFX_CHANNEL_STATE_IDLE); 485 } 486 487 /* Called from the device poll routine to get ownership of a channel. */ 488 static inline bool efx_channel_lock_napi(struct efx_channel *channel) 489 { 490 unsigned long prev, old = READ_ONCE(channel->busy_poll_state); 491 492 while (1) { 493 switch (old) { 494 case EFX_CHANNEL_STATE_POLL: 495 /* Ensure efx_channel_try_lock_poll() wont starve us */ 496 set_bit(EFX_CHANNEL_STATE_NAPI_REQ_BIT, 497 &channel->busy_poll_state); 498 /* fallthrough */ 499 case EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_NAPI_REQ: 500 return false; 501 default: 502 break; 503 } 504 prev = cmpxchg(&channel->busy_poll_state, old, 505 EFX_CHANNEL_STATE_NAPI); 506 if (unlikely(prev != old)) { 507 /* This is likely to mean we've just entered polling 508 * state. Go back round to set the REQ bit. 509 */ 510 old = prev; 511 continue; 512 } 513 return true; 514 } 515 } 516 517 static inline void efx_channel_unlock_napi(struct efx_channel *channel) 518 { 519 /* Make sure write has completed from efx_channel_lock_napi() */ 520 smp_wmb(); 521 WRITE_ONCE(channel->busy_poll_state, EFX_CHANNEL_STATE_IDLE); 522 } 523 524 /* Called from efx_busy_poll(). */ 525 static inline bool efx_channel_try_lock_poll(struct efx_channel *channel) 526 { 527 return cmpxchg(&channel->busy_poll_state, EFX_CHANNEL_STATE_IDLE, 528 EFX_CHANNEL_STATE_POLL) == EFX_CHANNEL_STATE_IDLE; 529 } 530 531 static inline void efx_channel_unlock_poll(struct efx_channel *channel) 532 { 533 clear_bit_unlock(EFX_CHANNEL_STATE_POLL_BIT, &channel->busy_poll_state); 534 } 535 536 static inline bool efx_channel_busy_polling(struct efx_channel *channel) 537 { 538 return test_bit(EFX_CHANNEL_STATE_POLL_BIT, &channel->busy_poll_state); 539 } 540 541 static inline void efx_channel_enable(struct efx_channel *channel) 542 { 543 clear_bit_unlock(EFX_CHANNEL_STATE_DISABLE_BIT, 544 &channel->busy_poll_state); 545 } 546 547 /* Stop further polling or napi access. 548 * Returns false if the channel is currently busy polling. 549 */ 550 static inline bool efx_channel_disable(struct efx_channel *channel) 551 { 552 set_bit(EFX_CHANNEL_STATE_DISABLE_BIT, &channel->busy_poll_state); 553 /* Implicit barrier in efx_channel_busy_polling() */ 554 return !efx_channel_busy_polling(channel); 555 } 556 557 #else /* CONFIG_NET_RX_BUSY_POLL */ 558 559 static inline void efx_channel_busy_poll_init(struct efx_channel *channel) 560 { 561 } 562 563 static inline bool efx_channel_lock_napi(struct efx_channel *channel) 564 { 565 return true; 566 } 567 568 static inline void efx_channel_unlock_napi(struct efx_channel *channel) 569 { 570 } 571 572 static inline bool efx_channel_try_lock_poll(struct efx_channel *channel) 573 { 574 return false; 575 } 576 577 static inline void efx_channel_unlock_poll(struct efx_channel *channel) 578 { 579 } 580 581 static inline bool efx_channel_busy_polling(struct efx_channel *channel) 582 { 583 return false; 584 } 585 586 static inline void efx_channel_enable(struct efx_channel *channel) 587 { 588 } 589 590 static inline bool efx_channel_disable(struct efx_channel *channel) 591 { 592 return true; 593 } 594 #endif /* CONFIG_NET_RX_BUSY_POLL */ 595 596 /** 597 * struct efx_msi_context - Context for each MSI 598 * @efx: The associated NIC 599 * @index: Index of the channel/IRQ 600 * @name: Name of the channel/IRQ 601 * 602 * Unlike &struct efx_channel, this is never reallocated and is always 603 * safe for the IRQ handler to access. 604 */ 605 struct efx_msi_context { 606 struct efx_nic *efx; 607 unsigned int index; 608 char name[IFNAMSIZ + 6]; 609 }; 610 611 /** 612 * struct efx_channel_type - distinguishes traffic and extra channels 613 * @handle_no_channel: Handle failure to allocate an extra channel 614 * @pre_probe: Set up extra state prior to initialisation 615 * @post_remove: Tear down extra state after finalisation, if allocated. 616 * May be called on channels that have not been probed. 617 * @get_name: Generate the channel's name (used for its IRQ handler) 618 * @copy: Copy the channel state prior to reallocation. May be %NULL if 619 * reallocation is not supported. 620 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb() 621 * @keep_eventq: Flag for whether event queue should be kept initialised 622 * while the device is stopped 623 */ 624 struct efx_channel_type { 625 void (*handle_no_channel)(struct efx_nic *); 626 int (*pre_probe)(struct efx_channel *); 627 void (*post_remove)(struct efx_channel *); 628 void (*get_name)(struct efx_channel *, char *buf, size_t len); 629 struct efx_channel *(*copy)(const struct efx_channel *); 630 bool (*receive_skb)(struct efx_channel *, struct sk_buff *); 631 bool keep_eventq; 632 }; 633 634 enum efx_led_mode { 635 EFX_LED_OFF = 0, 636 EFX_LED_ON = 1, 637 EFX_LED_DEFAULT = 2 638 }; 639 640 #define STRING_TABLE_LOOKUP(val, member) \ 641 ((val) < member ## _max) ? member ## _names[val] : "(invalid)" 642 643 extern const char *const efx_loopback_mode_names[]; 644 extern const unsigned int efx_loopback_mode_max; 645 #define LOOPBACK_MODE(efx) \ 646 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) 647 648 extern const char *const efx_reset_type_names[]; 649 extern const unsigned int efx_reset_type_max; 650 #define RESET_TYPE(type) \ 651 STRING_TABLE_LOOKUP(type, efx_reset_type) 652 653 enum efx_int_mode { 654 /* Be careful if altering to correct macro below */ 655 EFX_INT_MODE_MSIX = 0, 656 EFX_INT_MODE_MSI = 1, 657 EFX_INT_MODE_LEGACY = 2, 658 EFX_INT_MODE_MAX /* Insert any new items before this */ 659 }; 660 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) 661 662 enum nic_state { 663 STATE_UNINIT = 0, /* device being probed/removed or is frozen */ 664 STATE_READY = 1, /* hardware ready and netdev registered */ 665 STATE_DISABLED = 2, /* device disabled due to hardware errors */ 666 STATE_RECOVERY = 3, /* device recovering from PCI error */ 667 }; 668 669 /* Forward declaration */ 670 struct efx_nic; 671 672 /* Pseudo bit-mask flow control field */ 673 #define EFX_FC_RX FLOW_CTRL_RX 674 #define EFX_FC_TX FLOW_CTRL_TX 675 #define EFX_FC_AUTO 4 676 677 /** 678 * struct efx_link_state - Current state of the link 679 * @up: Link is up 680 * @fd: Link is full-duplex 681 * @fc: Actual flow control flags 682 * @speed: Link speed (Mbps) 683 */ 684 struct efx_link_state { 685 bool up; 686 bool fd; 687 u8 fc; 688 unsigned int speed; 689 }; 690 691 static inline bool efx_link_state_equal(const struct efx_link_state *left, 692 const struct efx_link_state *right) 693 { 694 return left->up == right->up && left->fd == right->fd && 695 left->fc == right->fc && left->speed == right->speed; 696 } 697 698 /** 699 * struct efx_phy_operations - Efx PHY operations table 700 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, 701 * efx->loopback_modes. 702 * @init: Initialise PHY 703 * @fini: Shut down PHY 704 * @reconfigure: Reconfigure PHY (e.g. for new link parameters) 705 * @poll: Update @link_state and report whether it changed. 706 * Serialised by the mac_lock. 707 * @get_settings: Get ethtool settings. Serialised by the mac_lock. 708 * @set_settings: Set ethtool settings. Serialised by the mac_lock. 709 * @set_npage_adv: Set abilities advertised in (Extended) Next Page 710 * (only needed where AN bit is set in mmds) 711 * @test_alive: Test that PHY is 'alive' (online) 712 * @test_name: Get the name of a PHY-specific test/result 713 * @run_tests: Run tests and record results as appropriate (offline). 714 * Flags are the ethtool tests flags. 715 */ 716 struct efx_phy_operations { 717 int (*probe) (struct efx_nic *efx); 718 int (*init) (struct efx_nic *efx); 719 void (*fini) (struct efx_nic *efx); 720 void (*remove) (struct efx_nic *efx); 721 int (*reconfigure) (struct efx_nic *efx); 722 bool (*poll) (struct efx_nic *efx); 723 void (*get_settings) (struct efx_nic *efx, 724 struct ethtool_cmd *ecmd); 725 int (*set_settings) (struct efx_nic *efx, 726 struct ethtool_cmd *ecmd); 727 void (*set_npage_adv) (struct efx_nic *efx, u32); 728 int (*test_alive) (struct efx_nic *efx); 729 const char *(*test_name) (struct efx_nic *efx, unsigned int index); 730 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); 731 int (*get_module_eeprom) (struct efx_nic *efx, 732 struct ethtool_eeprom *ee, 733 u8 *data); 734 int (*get_module_info) (struct efx_nic *efx, 735 struct ethtool_modinfo *modinfo); 736 }; 737 738 /** 739 * enum efx_phy_mode - PHY operating mode flags 740 * @PHY_MODE_NORMAL: on and should pass traffic 741 * @PHY_MODE_TX_DISABLED: on with TX disabled 742 * @PHY_MODE_LOW_POWER: set to low power through MDIO 743 * @PHY_MODE_OFF: switched off through external control 744 * @PHY_MODE_SPECIAL: on but will not pass traffic 745 */ 746 enum efx_phy_mode { 747 PHY_MODE_NORMAL = 0, 748 PHY_MODE_TX_DISABLED = 1, 749 PHY_MODE_LOW_POWER = 2, 750 PHY_MODE_OFF = 4, 751 PHY_MODE_SPECIAL = 8, 752 }; 753 754 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) 755 { 756 return !!(mode & ~PHY_MODE_TX_DISABLED); 757 } 758 759 /** 760 * struct efx_hw_stat_desc - Description of a hardware statistic 761 * @name: Name of the statistic as visible through ethtool, or %NULL if 762 * it should not be exposed 763 * @dma_width: Width in bits (0 for non-DMA statistics) 764 * @offset: Offset within stats (ignored for non-DMA statistics) 765 */ 766 struct efx_hw_stat_desc { 767 const char *name; 768 u16 dma_width; 769 u16 offset; 770 }; 771 772 /* Number of bits used in a multicast filter hash address */ 773 #define EFX_MCAST_HASH_BITS 8 774 775 /* Number of (single-bit) entries in a multicast filter hash */ 776 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) 777 778 /* An Efx multicast filter hash */ 779 union efx_multicast_hash { 780 u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; 781 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; 782 }; 783 784 struct vfdi_status; 785 786 /** 787 * struct efx_nic - an Efx NIC 788 * @name: Device name (net device name or bus id before net device registered) 789 * @pci_dev: The PCI device 790 * @node: List node for maintaning primary/secondary function lists 791 * @primary: &struct efx_nic instance for the primary function of this 792 * controller. May be the same structure, and may be %NULL if no 793 * primary function is bound. Serialised by rtnl_lock. 794 * @secondary_list: List of &struct efx_nic instances for the secondary PCI 795 * functions of the controller, if this is for the primary function. 796 * Serialised by rtnl_lock. 797 * @type: Controller type attributes 798 * @legacy_irq: IRQ number 799 * @workqueue: Workqueue for port reconfigures and the HW monitor. 800 * Work items do not hold and must not acquire RTNL. 801 * @workqueue_name: Name of workqueue 802 * @reset_work: Scheduled reset workitem 803 * @membase_phys: Memory BAR value as physical address 804 * @membase: Memory BAR value 805 * @interrupt_mode: Interrupt mode 806 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds 807 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues 808 * @irq_rx_moderation: IRQ moderation time for RX event queues 809 * @msg_enable: Log message enable flags 810 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock. 811 * @reset_pending: Bitmask for pending resets 812 * @tx_queue: TX DMA queues 813 * @rx_queue: RX DMA queues 814 * @channel: Channels 815 * @msi_context: Context for each MSI 816 * @extra_channel_types: Types of extra (non-traffic) channels that 817 * should be allocated for this NIC 818 * @rxq_entries: Size of receive queues requested by user. 819 * @txq_entries: Size of transmit queues requested by user. 820 * @txq_stop_thresh: TX queue fill level at or above which we stop it. 821 * @txq_wake_thresh: TX queue fill level at or below which we wake it. 822 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches 823 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches 824 * @sram_lim_qw: Qword address limit of SRAM 825 * @next_buffer_table: First available buffer table id 826 * @n_channels: Number of channels in use 827 * @n_rx_channels: Number of channels used for RX (= number of RX queues) 828 * @n_tx_channels: Number of channels used for TX 829 * @rx_ip_align: RX DMA address offset to have IP header aligned in 830 * in accordance with NET_IP_ALIGN 831 * @rx_dma_len: Current maximum RX DMA length 832 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer 833 * @rx_buffer_truesize: Amortised allocation size of an RX buffer, 834 * for use in sk_buff::truesize 835 * @rx_prefix_size: Size of RX prefix before packet data 836 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data 837 * (valid only if @rx_prefix_size != 0; always negative) 838 * @rx_packet_len_offset: Offset of RX packet length from start of packet data 839 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative) 840 * @rx_packet_ts_offset: Offset of timestamp from start of packet data 841 * (valid only if channel->sync_timestamps_enabled; always negative) 842 * @rx_hash_key: Toeplitz hash key for RSS 843 * @rx_indir_table: Indirection table for RSS 844 * @rx_scatter: Scatter mode enabled for receives 845 * @int_error_count: Number of internal errors seen recently 846 * @int_error_expire: Time at which error count will be expired 847 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will 848 * acknowledge but do nothing else. 849 * @irq_status: Interrupt status buffer 850 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 851 * @irq_level: IRQ level/index for IRQs not triggered by an event queue 852 * @selftest_work: Work item for asynchronous self-test 853 * @mtd_list: List of MTDs attached to the NIC 854 * @nic_data: Hardware dependent state 855 * @mcdi: Management-Controller-to-Driver Interface state 856 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, 857 * efx_monitor() and efx_reconfigure_port() 858 * @port_enabled: Port enabled indicator. 859 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and 860 * efx_mac_work() with kernel interfaces. Safe to read under any 861 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must 862 * be held to modify it. 863 * @port_initialized: Port initialized? 864 * @net_dev: Operating system network device. Consider holding the rtnl lock 865 * @stats_buffer: DMA buffer for statistics 866 * @phy_type: PHY type 867 * @phy_op: PHY interface 868 * @phy_data: PHY private data (including PHY-specific stats) 869 * @mdio: PHY MDIO interface 870 * @mdio_bus: PHY MDIO bus ID (only used by Siena) 871 * @phy_mode: PHY operating mode. Serialised by @mac_lock. 872 * @link_advertising: Autonegotiation advertising flags 873 * @link_state: Current state of the link 874 * @n_link_state_changes: Number of times the link has changed state 875 * @unicast_filter: Flag for Falcon-arch simple unicast filter. 876 * Protected by @mac_lock. 877 * @multicast_hash: Multicast hash table for Falcon-arch. 878 * Protected by @mac_lock. 879 * @wanted_fc: Wanted flow control flags 880 * @fc_disable: When non-zero flow control is disabled. Typically used to 881 * ensure that network back pressure doesn't delay dma queue flushes. 882 * Serialised by the rtnl lock. 883 * @mac_work: Work item for changing MAC promiscuity and multicast hash 884 * @loopback_mode: Loopback status 885 * @loopback_modes: Supported loopback mode bitmask 886 * @loopback_selftest: Offline self-test private state 887 * @filter_sem: Filter table rw_semaphore, for freeing the table 888 * @filter_lock: Filter table lock, for mere content changes 889 * @filter_state: Architecture-dependent filter table state 890 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS, 891 * indexed by filter ID 892 * @rps_expire_index: Next index to check for expiry in @rps_flow_id 893 * @active_queues: Count of RX and TX queues that haven't been flushed and drained. 894 * @rxq_flush_pending: Count of number of receive queues that need to be flushed. 895 * Decremented when the efx_flush_rx_queue() is called. 896 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet 897 * completed (either success or failure). Not used when MCDI is used to 898 * flush receive queues. 899 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions. 900 * @vf_count: Number of VFs intended to be enabled. 901 * @vf_init_count: Number of VFs that have been fully initialised. 902 * @vi_scale: log2 number of vnics per VF. 903 * @ptp_data: PTP state data 904 * @vpd_sn: Serial number read from VPD 905 * @monitor_work: Hardware monitor workitem 906 * @biu_lock: BIU (bus interface unit) lock 907 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This 908 * field is used by efx_test_interrupts() to verify that an 909 * interrupt has occurred. 910 * @stats_lock: Statistics update lock. Must be held when calling 911 * efx_nic_type::{update,start,stop}_stats. 912 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb 913 * @mc_promisc: Whether in multicast promiscuous mode when last changed 914 * 915 * This is stored in the private area of the &struct net_device. 916 */ 917 struct efx_nic { 918 /* The following fields should be written very rarely */ 919 920 char name[IFNAMSIZ]; 921 struct list_head node; 922 struct efx_nic *primary; 923 struct list_head secondary_list; 924 struct pci_dev *pci_dev; 925 unsigned int port_num; 926 const struct efx_nic_type *type; 927 int legacy_irq; 928 bool eeh_disabled_legacy_irq; 929 struct workqueue_struct *workqueue; 930 char workqueue_name[16]; 931 struct work_struct reset_work; 932 resource_size_t membase_phys; 933 void __iomem *membase; 934 935 enum efx_int_mode interrupt_mode; 936 unsigned int timer_quantum_ns; 937 bool irq_rx_adaptive; 938 unsigned int irq_rx_moderation; 939 u32 msg_enable; 940 941 enum nic_state state; 942 unsigned long reset_pending; 943 944 struct efx_channel *channel[EFX_MAX_CHANNELS]; 945 struct efx_msi_context msi_context[EFX_MAX_CHANNELS]; 946 const struct efx_channel_type * 947 extra_channel_type[EFX_MAX_EXTRA_CHANNELS]; 948 949 unsigned rxq_entries; 950 unsigned txq_entries; 951 unsigned int txq_stop_thresh; 952 unsigned int txq_wake_thresh; 953 954 unsigned tx_dc_base; 955 unsigned rx_dc_base; 956 unsigned sram_lim_qw; 957 unsigned next_buffer_table; 958 959 unsigned int max_channels; 960 unsigned int max_tx_channels; 961 unsigned n_channels; 962 unsigned n_rx_channels; 963 unsigned rss_spread; 964 unsigned tx_channel_offset; 965 unsigned n_tx_channels; 966 unsigned int rx_ip_align; 967 unsigned int rx_dma_len; 968 unsigned int rx_buffer_order; 969 unsigned int rx_buffer_truesize; 970 unsigned int rx_page_buf_step; 971 unsigned int rx_bufs_per_page; 972 unsigned int rx_pages_per_batch; 973 unsigned int rx_prefix_size; 974 int rx_packet_hash_offset; 975 int rx_packet_len_offset; 976 int rx_packet_ts_offset; 977 u8 rx_hash_key[40]; 978 u32 rx_indir_table[128]; 979 bool rx_scatter; 980 981 unsigned int_error_count; 982 unsigned long int_error_expire; 983 984 bool irq_soft_enabled; 985 struct efx_buffer irq_status; 986 unsigned irq_zero_count; 987 unsigned irq_level; 988 struct delayed_work selftest_work; 989 990 #ifdef CONFIG_SFC_MTD 991 struct list_head mtd_list; 992 #endif 993 994 void *nic_data; 995 struct efx_mcdi_data *mcdi; 996 997 struct mutex mac_lock; 998 struct work_struct mac_work; 999 bool port_enabled; 1000 1001 bool mc_bist_for_other_fn; 1002 bool port_initialized; 1003 struct net_device *net_dev; 1004 1005 struct efx_buffer stats_buffer; 1006 u64 rx_nodesc_drops_total; 1007 u64 rx_nodesc_drops_while_down; 1008 bool rx_nodesc_drops_prev_state; 1009 1010 unsigned int phy_type; 1011 const struct efx_phy_operations *phy_op; 1012 void *phy_data; 1013 struct mdio_if_info mdio; 1014 unsigned int mdio_bus; 1015 enum efx_phy_mode phy_mode; 1016 1017 u32 link_advertising; 1018 struct efx_link_state link_state; 1019 unsigned int n_link_state_changes; 1020 1021 bool unicast_filter; 1022 union efx_multicast_hash multicast_hash; 1023 u8 wanted_fc; 1024 unsigned fc_disable; 1025 1026 atomic_t rx_reset; 1027 enum efx_loopback_mode loopback_mode; 1028 u64 loopback_modes; 1029 1030 void *loopback_selftest; 1031 1032 struct rw_semaphore filter_sem; 1033 spinlock_t filter_lock; 1034 void *filter_state; 1035 #ifdef CONFIG_RFS_ACCEL 1036 u32 *rps_flow_id; 1037 unsigned int rps_expire_index; 1038 #endif 1039 1040 atomic_t active_queues; 1041 atomic_t rxq_flush_pending; 1042 atomic_t rxq_flush_outstanding; 1043 wait_queue_head_t flush_wq; 1044 1045 #ifdef CONFIG_SFC_SRIOV 1046 unsigned vf_count; 1047 unsigned vf_init_count; 1048 unsigned vi_scale; 1049 #endif 1050 1051 struct efx_ptp_data *ptp_data; 1052 1053 char *vpd_sn; 1054 1055 /* The following fields may be written more often */ 1056 1057 struct delayed_work monitor_work ____cacheline_aligned_in_smp; 1058 spinlock_t biu_lock; 1059 int last_irq_cpu; 1060 spinlock_t stats_lock; 1061 atomic_t n_rx_noskb_drops; 1062 bool mc_promisc; 1063 }; 1064 1065 static inline int efx_dev_registered(struct efx_nic *efx) 1066 { 1067 return efx->net_dev->reg_state == NETREG_REGISTERED; 1068 } 1069 1070 static inline unsigned int efx_port_num(struct efx_nic *efx) 1071 { 1072 return efx->port_num; 1073 } 1074 1075 struct efx_mtd_partition { 1076 struct list_head node; 1077 struct mtd_info mtd; 1078 const char *dev_type_name; 1079 const char *type_name; 1080 char name[IFNAMSIZ + 20]; 1081 }; 1082 1083 /** 1084 * struct efx_nic_type - Efx device type definition 1085 * @mem_bar: Get the memory BAR 1086 * @mem_map_size: Get memory BAR mapped size 1087 * @probe: Probe the controller 1088 * @remove: Free resources allocated by probe() 1089 * @init: Initialise the controller 1090 * @dimension_resources: Dimension controller resources (buffer table, 1091 * and VIs once the available interrupt resources are clear) 1092 * @fini: Shut down the controller 1093 * @monitor: Periodic function for polling link state and hardware monitor 1094 * @map_reset_reason: Map ethtool reset reason to a reset method 1095 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible 1096 * @reset: Reset the controller hardware and possibly the PHY. This will 1097 * be called while the controller is uninitialised. 1098 * @probe_port: Probe the MAC and PHY 1099 * @remove_port: Free resources allocated by probe_port() 1100 * @handle_global_event: Handle a "global" event (may be %NULL) 1101 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues) 1102 * @prepare_flush: Prepare the hardware for flushing the DMA queues 1103 * (for Falcon architecture) 1104 * @finish_flush: Clean up after flushing the DMA queues (for Falcon 1105 * architecture) 1106 * @prepare_flr: Prepare for an FLR 1107 * @finish_flr: Clean up after an FLR 1108 * @describe_stats: Describe statistics for ethtool 1109 * @update_stats: Update statistics not provided by event handling. 1110 * Either argument may be %NULL. 1111 * @start_stats: Start the regular fetching of statistics 1112 * @pull_stats: Pull stats from the NIC and wait until they arrive. 1113 * @stop_stats: Stop the regular fetching of statistics 1114 * @set_id_led: Set state of identifying LED or revert to automatic function 1115 * @push_irq_moderation: Apply interrupt moderation value 1116 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY 1117 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL) 1118 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings 1119 * to the hardware. Serialised by the mac_lock. 1120 * @check_mac_fault: Check MAC fault state. True if fault present. 1121 * @get_wol: Get WoL configuration from driver state 1122 * @set_wol: Push WoL configuration to the NIC 1123 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) 1124 * @test_chip: Test registers. May use efx_farch_test_registers(), and is 1125 * expected to reset the NIC. 1126 * @test_nvram: Test validity of NVRAM contents 1127 * @mcdi_request: Send an MCDI request with the given header and SDU. 1128 * The SDU length may be any value from 0 up to the protocol- 1129 * defined maximum, but its buffer will be padded to a multiple 1130 * of 4 bytes. 1131 * @mcdi_poll_response: Test whether an MCDI response is available. 1132 * @mcdi_read_response: Read the MCDI response PDU. The offset will 1133 * be a multiple of 4. The length may not be, but the buffer 1134 * will be padded so it is safe to round up. 1135 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so, 1136 * return an appropriate error code for aborting any current 1137 * request; otherwise return 0. 1138 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must 1139 * be separately enabled after this. 1140 * @irq_test_generate: Generate a test IRQ 1141 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event 1142 * queue must be separately disabled before this. 1143 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is 1144 * a pointer to the &struct efx_msi_context for the channel. 1145 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument 1146 * is a pointer to the &struct efx_nic. 1147 * @tx_probe: Allocate resources for TX queue 1148 * @tx_init: Initialise TX queue on the NIC 1149 * @tx_remove: Free resources for TX queue 1150 * @tx_write: Write TX descriptors and doorbell 1151 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC 1152 * @rx_probe: Allocate resources for RX queue 1153 * @rx_init: Initialise RX queue on the NIC 1154 * @rx_remove: Free resources for RX queue 1155 * @rx_write: Write RX descriptors and doorbell 1156 * @rx_defer_refill: Generate a refill reminder event 1157 * @ev_probe: Allocate resources for event queue 1158 * @ev_init: Initialise event queue on the NIC 1159 * @ev_fini: Deinitialise event queue on the NIC 1160 * @ev_remove: Free resources for event queue 1161 * @ev_process: Process events for a queue, up to the given NAPI quota 1162 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ 1163 * @ev_test_generate: Generate a test event 1164 * @filter_table_probe: Probe filter capabilities and set up filter software state 1165 * @filter_table_restore: Restore filters removed from hardware 1166 * @filter_table_remove: Remove filters from hardware and tear down software state 1167 * @filter_update_rx_scatter: Update filters after change to rx scatter setting 1168 * @filter_insert: add or replace a filter 1169 * @filter_remove_safe: remove a filter by ID, carefully 1170 * @filter_get_safe: retrieve a filter by ID, carefully 1171 * @filter_clear_rx: Remove all RX filters whose priority is less than or 1172 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO 1173 * @filter_count_rx_used: Get the number of filters in use at a given priority 1174 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1 1175 * @filter_get_rx_ids: Get list of RX filters at a given priority 1176 * @filter_rfs_insert: Add or replace a filter for RFS. This must be 1177 * atomic. The hardware change may be asynchronous but should 1178 * not be delayed for long. It may fail if this can't be done 1179 * atomically. 1180 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS. 1181 * This must check whether the specified table entry is used by RFS 1182 * and that rps_may_expire_flow() returns true for it. 1183 * @mtd_probe: Probe and add MTD partitions associated with this net device, 1184 * using efx_mtd_add() 1185 * @mtd_rename: Set an MTD partition name using the net device name 1186 * @mtd_read: Read from an MTD partition 1187 * @mtd_erase: Erase part of an MTD partition 1188 * @mtd_write: Write to an MTD partition 1189 * @mtd_sync: Wait for write-back to complete on MTD partition. This 1190 * also notifies the driver that a writer has finished using this 1191 * partition. 1192 * @ptp_write_host_time: Send host time to MC as part of sync protocol 1193 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX 1194 * timestamping, possibly only temporarily for the purposes of a reset. 1195 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags 1196 * and tx_type will already have been validated but this operation 1197 * must validate and update rx_filter. 1198 * @set_mac_address: Set the MAC address of the device 1199 * @revision: Hardware architecture revision 1200 * @txd_ptr_tbl_base: TX descriptor ring base address 1201 * @rxd_ptr_tbl_base: RX descriptor ring base address 1202 * @buf_tbl_base: Buffer table base address 1203 * @evq_ptr_tbl_base: Event queue pointer table base address 1204 * @evq_rptr_tbl_base: Event queue read-pointer table base address 1205 * @max_dma_mask: Maximum possible DMA mask 1206 * @rx_prefix_size: Size of RX prefix before packet data 1207 * @rx_hash_offset: Offset of RX flow hash within prefix 1208 * @rx_ts_offset: Offset of timestamp within prefix 1209 * @rx_buffer_padding: Size of padding at end of RX packet 1210 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers 1211 * @always_rx_scatter: NIC will always scatter packets to multiple buffers 1212 * @max_interrupt_mode: Highest capability interrupt mode supported 1213 * from &enum efx_init_mode. 1214 * @timer_period_max: Maximum period of interrupt timer (in ticks) 1215 * @offload_features: net_device feature flags for protocol offload 1216 * features implemented in hardware 1217 * @mcdi_max_ver: Maximum MCDI version supported 1218 * @hwtstamp_filters: Mask of hardware timestamp filter types supported 1219 */ 1220 struct efx_nic_type { 1221 bool is_vf; 1222 unsigned int mem_bar; 1223 unsigned int (*mem_map_size)(struct efx_nic *efx); 1224 int (*probe)(struct efx_nic *efx); 1225 void (*remove)(struct efx_nic *efx); 1226 int (*init)(struct efx_nic *efx); 1227 int (*dimension_resources)(struct efx_nic *efx); 1228 void (*fini)(struct efx_nic *efx); 1229 void (*monitor)(struct efx_nic *efx); 1230 enum reset_type (*map_reset_reason)(enum reset_type reason); 1231 int (*map_reset_flags)(u32 *flags); 1232 int (*reset)(struct efx_nic *efx, enum reset_type method); 1233 int (*probe_port)(struct efx_nic *efx); 1234 void (*remove_port)(struct efx_nic *efx); 1235 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *); 1236 int (*fini_dmaq)(struct efx_nic *efx); 1237 void (*prepare_flush)(struct efx_nic *efx); 1238 void (*finish_flush)(struct efx_nic *efx); 1239 void (*prepare_flr)(struct efx_nic *efx); 1240 void (*finish_flr)(struct efx_nic *efx); 1241 size_t (*describe_stats)(struct efx_nic *efx, u8 *names); 1242 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats, 1243 struct rtnl_link_stats64 *core_stats); 1244 void (*start_stats)(struct efx_nic *efx); 1245 void (*pull_stats)(struct efx_nic *efx); 1246 void (*stop_stats)(struct efx_nic *efx); 1247 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); 1248 void (*push_irq_moderation)(struct efx_channel *channel); 1249 int (*reconfigure_port)(struct efx_nic *efx); 1250 void (*prepare_enable_fc_tx)(struct efx_nic *efx); 1251 int (*reconfigure_mac)(struct efx_nic *efx); 1252 bool (*check_mac_fault)(struct efx_nic *efx); 1253 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); 1254 int (*set_wol)(struct efx_nic *efx, u32 type); 1255 void (*resume_wol)(struct efx_nic *efx); 1256 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests); 1257 int (*test_nvram)(struct efx_nic *efx); 1258 void (*mcdi_request)(struct efx_nic *efx, 1259 const efx_dword_t *hdr, size_t hdr_len, 1260 const efx_dword_t *sdu, size_t sdu_len); 1261 bool (*mcdi_poll_response)(struct efx_nic *efx); 1262 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu, 1263 size_t pdu_offset, size_t pdu_len); 1264 int (*mcdi_poll_reboot)(struct efx_nic *efx); 1265 void (*mcdi_reboot_detected)(struct efx_nic *efx); 1266 void (*irq_enable_master)(struct efx_nic *efx); 1267 void (*irq_test_generate)(struct efx_nic *efx); 1268 void (*irq_disable_non_ev)(struct efx_nic *efx); 1269 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id); 1270 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id); 1271 int (*tx_probe)(struct efx_tx_queue *tx_queue); 1272 void (*tx_init)(struct efx_tx_queue *tx_queue); 1273 void (*tx_remove)(struct efx_tx_queue *tx_queue); 1274 void (*tx_write)(struct efx_tx_queue *tx_queue); 1275 int (*rx_push_rss_config)(struct efx_nic *efx, bool user, 1276 const u32 *rx_indir_table); 1277 int (*rx_probe)(struct efx_rx_queue *rx_queue); 1278 void (*rx_init)(struct efx_rx_queue *rx_queue); 1279 void (*rx_remove)(struct efx_rx_queue *rx_queue); 1280 void (*rx_write)(struct efx_rx_queue *rx_queue); 1281 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue); 1282 int (*ev_probe)(struct efx_channel *channel); 1283 int (*ev_init)(struct efx_channel *channel); 1284 void (*ev_fini)(struct efx_channel *channel); 1285 void (*ev_remove)(struct efx_channel *channel); 1286 int (*ev_process)(struct efx_channel *channel, int quota); 1287 void (*ev_read_ack)(struct efx_channel *channel); 1288 void (*ev_test_generate)(struct efx_channel *channel); 1289 int (*filter_table_probe)(struct efx_nic *efx); 1290 void (*filter_table_restore)(struct efx_nic *efx); 1291 void (*filter_table_remove)(struct efx_nic *efx); 1292 void (*filter_update_rx_scatter)(struct efx_nic *efx); 1293 s32 (*filter_insert)(struct efx_nic *efx, 1294 struct efx_filter_spec *spec, bool replace); 1295 int (*filter_remove_safe)(struct efx_nic *efx, 1296 enum efx_filter_priority priority, 1297 u32 filter_id); 1298 int (*filter_get_safe)(struct efx_nic *efx, 1299 enum efx_filter_priority priority, 1300 u32 filter_id, struct efx_filter_spec *); 1301 int (*filter_clear_rx)(struct efx_nic *efx, 1302 enum efx_filter_priority priority); 1303 u32 (*filter_count_rx_used)(struct efx_nic *efx, 1304 enum efx_filter_priority priority); 1305 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx); 1306 s32 (*filter_get_rx_ids)(struct efx_nic *efx, 1307 enum efx_filter_priority priority, 1308 u32 *buf, u32 size); 1309 #ifdef CONFIG_RFS_ACCEL 1310 s32 (*filter_rfs_insert)(struct efx_nic *efx, 1311 struct efx_filter_spec *spec); 1312 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id, 1313 unsigned int index); 1314 #endif 1315 #ifdef CONFIG_SFC_MTD 1316 int (*mtd_probe)(struct efx_nic *efx); 1317 void (*mtd_rename)(struct efx_mtd_partition *part); 1318 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len, 1319 size_t *retlen, u8 *buffer); 1320 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len); 1321 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len, 1322 size_t *retlen, const u8 *buffer); 1323 int (*mtd_sync)(struct mtd_info *mtd); 1324 #endif 1325 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time); 1326 int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp); 1327 int (*ptp_set_ts_config)(struct efx_nic *efx, 1328 struct hwtstamp_config *init); 1329 int (*sriov_configure)(struct efx_nic *efx, int num_vfs); 1330 int (*sriov_init)(struct efx_nic *efx); 1331 void (*sriov_fini)(struct efx_nic *efx); 1332 bool (*sriov_wanted)(struct efx_nic *efx); 1333 void (*sriov_reset)(struct efx_nic *efx); 1334 void (*sriov_flr)(struct efx_nic *efx, unsigned vf_i); 1335 int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, u8 *mac); 1336 int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan, 1337 u8 qos); 1338 int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i, 1339 bool spoofchk); 1340 int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i, 1341 struct ifla_vf_info *ivi); 1342 int (*sriov_set_vf_link_state)(struct efx_nic *efx, int vf_i, 1343 int link_state); 1344 int (*sriov_get_phys_port_id)(struct efx_nic *efx, 1345 struct netdev_phys_item_id *ppid); 1346 int (*vswitching_probe)(struct efx_nic *efx); 1347 int (*vswitching_restore)(struct efx_nic *efx); 1348 void (*vswitching_remove)(struct efx_nic *efx); 1349 int (*get_mac_address)(struct efx_nic *efx, unsigned char *perm_addr); 1350 int (*set_mac_address)(struct efx_nic *efx); 1351 1352 int revision; 1353 unsigned int txd_ptr_tbl_base; 1354 unsigned int rxd_ptr_tbl_base; 1355 unsigned int buf_tbl_base; 1356 unsigned int evq_ptr_tbl_base; 1357 unsigned int evq_rptr_tbl_base; 1358 u64 max_dma_mask; 1359 unsigned int rx_prefix_size; 1360 unsigned int rx_hash_offset; 1361 unsigned int rx_ts_offset; 1362 unsigned int rx_buffer_padding; 1363 bool can_rx_scatter; 1364 bool always_rx_scatter; 1365 unsigned int max_interrupt_mode; 1366 unsigned int timer_period_max; 1367 netdev_features_t offload_features; 1368 int mcdi_max_ver; 1369 unsigned int max_rx_ip_filters; 1370 u32 hwtstamp_filters; 1371 }; 1372 1373 /************************************************************************** 1374 * 1375 * Prototypes and inline functions 1376 * 1377 *************************************************************************/ 1378 1379 static inline struct efx_channel * 1380 efx_get_channel(struct efx_nic *efx, unsigned index) 1381 { 1382 EFX_BUG_ON_PARANOID(index >= efx->n_channels); 1383 return efx->channel[index]; 1384 } 1385 1386 /* Iterate over all used channels */ 1387 #define efx_for_each_channel(_channel, _efx) \ 1388 for (_channel = (_efx)->channel[0]; \ 1389 _channel; \ 1390 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ 1391 (_efx)->channel[_channel->channel + 1] : NULL) 1392 1393 /* Iterate over all used channels in reverse */ 1394 #define efx_for_each_channel_rev(_channel, _efx) \ 1395 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \ 1396 _channel; \ 1397 _channel = _channel->channel ? \ 1398 (_efx)->channel[_channel->channel - 1] : NULL) 1399 1400 static inline struct efx_tx_queue * 1401 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) 1402 { 1403 EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels || 1404 type >= EFX_TXQ_TYPES); 1405 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type]; 1406 } 1407 1408 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel) 1409 { 1410 return channel->channel - channel->efx->tx_channel_offset < 1411 channel->efx->n_tx_channels; 1412 } 1413 1414 static inline struct efx_tx_queue * 1415 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type) 1416 { 1417 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) || 1418 type >= EFX_TXQ_TYPES); 1419 return &channel->tx_queue[type]; 1420 } 1421 1422 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue) 1423 { 1424 return !(tx_queue->efx->net_dev->num_tc < 2 && 1425 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI); 1426 } 1427 1428 /* Iterate over all TX queues belonging to a channel */ 1429 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ 1430 if (!efx_channel_has_tx_queues(_channel)) \ 1431 ; \ 1432 else \ 1433 for (_tx_queue = (_channel)->tx_queue; \ 1434 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \ 1435 efx_tx_queue_used(_tx_queue); \ 1436 _tx_queue++) 1437 1438 /* Iterate over all possible TX queues belonging to a channel */ 1439 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \ 1440 if (!efx_channel_has_tx_queues(_channel)) \ 1441 ; \ 1442 else \ 1443 for (_tx_queue = (_channel)->tx_queue; \ 1444 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ 1445 _tx_queue++) 1446 1447 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel) 1448 { 1449 return channel->rx_queue.core_index >= 0; 1450 } 1451 1452 static inline struct efx_rx_queue * 1453 efx_channel_get_rx_queue(struct efx_channel *channel) 1454 { 1455 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel)); 1456 return &channel->rx_queue; 1457 } 1458 1459 /* Iterate over all RX queues belonging to a channel */ 1460 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ 1461 if (!efx_channel_has_rx_queue(_channel)) \ 1462 ; \ 1463 else \ 1464 for (_rx_queue = &(_channel)->rx_queue; \ 1465 _rx_queue; \ 1466 _rx_queue = NULL) 1467 1468 static inline struct efx_channel * 1469 efx_rx_queue_channel(struct efx_rx_queue *rx_queue) 1470 { 1471 return container_of(rx_queue, struct efx_channel, rx_queue); 1472 } 1473 1474 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) 1475 { 1476 return efx_rx_queue_channel(rx_queue)->channel; 1477 } 1478 1479 /* Returns a pointer to the specified receive buffer in the RX 1480 * descriptor queue. 1481 */ 1482 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, 1483 unsigned int index) 1484 { 1485 return &rx_queue->buffer[index]; 1486 } 1487 1488 /** 1489 * EFX_MAX_FRAME_LEN - calculate maximum frame length 1490 * 1491 * This calculates the maximum frame length that will be used for a 1492 * given MTU. The frame length will be equal to the MTU plus a 1493 * constant amount of header space and padding. This is the quantity 1494 * that the net driver will program into the MAC as the maximum frame 1495 * length. 1496 * 1497 * The 10G MAC requires 8-byte alignment on the frame 1498 * length, so we round up to the nearest 8. 1499 * 1500 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an 1501 * XGMII cycle). If the frame length reaches the maximum value in the 1502 * same cycle, the XMAC can miss the IPG altogether. We work around 1503 * this by adding a further 16 bytes. 1504 */ 1505 #define EFX_MAX_FRAME_LEN(mtu) \ 1506 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16) 1507 1508 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb) 1509 { 1510 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP; 1511 } 1512 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb) 1513 { 1514 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1515 } 1516 1517 #endif /* EFX_NET_DRIVER_H */ 1518