1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 /* Common definitions for all Efx net driver code */ 12 13 #ifndef EFX_NET_DRIVER_H 14 #define EFX_NET_DRIVER_H 15 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/ethtool.h> 19 #include <linux/if_vlan.h> 20 #include <linux/timer.h> 21 #include <linux/mdio.h> 22 #include <linux/list.h> 23 #include <linux/pci.h> 24 #include <linux/device.h> 25 #include <linux/highmem.h> 26 #include <linux/workqueue.h> 27 #include <linux/mutex.h> 28 #include <linux/rwsem.h> 29 #include <linux/vmalloc.h> 30 #include <linux/i2c.h> 31 #include <linux/mtd/mtd.h> 32 #include <net/busy_poll.h> 33 34 #include "enum.h" 35 #include "bitfield.h" 36 #include "filter.h" 37 38 /************************************************************************** 39 * 40 * Build definitions 41 * 42 **************************************************************************/ 43 44 #define EFX_DRIVER_VERSION "4.0" 45 46 #ifdef DEBUG 47 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) 48 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) 49 #else 50 #define EFX_BUG_ON_PARANOID(x) do {} while (0) 51 #define EFX_WARN_ON_PARANOID(x) do {} while (0) 52 #endif 53 54 /************************************************************************** 55 * 56 * Efx data structures 57 * 58 **************************************************************************/ 59 60 #define EFX_MAX_CHANNELS 32U 61 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS 62 #define EFX_EXTRA_CHANNEL_IOV 0 63 #define EFX_EXTRA_CHANNEL_PTP 1 64 #define EFX_MAX_EXTRA_CHANNELS 2U 65 66 /* Checksum generation is a per-queue option in hardware, so each 67 * queue visible to the networking core is backed by two hardware TX 68 * queues. */ 69 #define EFX_MAX_TX_TC 2 70 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS) 71 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */ 72 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */ 73 #define EFX_TXQ_TYPES 4 74 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS) 75 76 /* Maximum possible MTU the driver supports */ 77 #define EFX_MAX_MTU (9 * 1024) 78 79 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page, 80 * and should be a multiple of the cache line size. 81 */ 82 #define EFX_RX_USR_BUF_SIZE (2048 - 256) 83 84 /* If possible, we should ensure cache line alignment at start and end 85 * of every buffer. Otherwise, we just need to ensure 4-byte 86 * alignment of the network header. 87 */ 88 #if NET_IP_ALIGN == 0 89 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES 90 #else 91 #define EFX_RX_BUF_ALIGNMENT 4 92 #endif 93 94 /* Forward declare Precision Time Protocol (PTP) support structure. */ 95 struct efx_ptp_data; 96 struct hwtstamp_config; 97 98 struct efx_self_tests; 99 100 /** 101 * struct efx_buffer - A general-purpose DMA buffer 102 * @addr: host base address of the buffer 103 * @dma_addr: DMA base address of the buffer 104 * @len: Buffer length, in bytes 105 * 106 * The NIC uses these buffers for its interrupt status registers and 107 * MAC stats dumps. 108 */ 109 struct efx_buffer { 110 void *addr; 111 dma_addr_t dma_addr; 112 unsigned int len; 113 }; 114 115 /** 116 * struct efx_special_buffer - DMA buffer entered into buffer table 117 * @buf: Standard &struct efx_buffer 118 * @index: Buffer index within controller;s buffer table 119 * @entries: Number of buffer table entries 120 * 121 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE. 122 * Event and descriptor rings are addressed via one or more buffer 123 * table entries (and so can be physically non-contiguous, although we 124 * currently do not take advantage of that). On Falcon and Siena we 125 * have to take care of allocating and initialising the entries 126 * ourselves. On later hardware this is managed by the firmware and 127 * @index and @entries are left as 0. 128 */ 129 struct efx_special_buffer { 130 struct efx_buffer buf; 131 unsigned int index; 132 unsigned int entries; 133 }; 134 135 /** 136 * struct efx_tx_buffer - buffer state for a TX descriptor 137 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be 138 * freed when descriptor completes 139 * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be 140 * freed when descriptor completes. 141 * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor. 142 * @dma_addr: DMA address of the fragment. 143 * @flags: Flags for allocation and DMA mapping type 144 * @len: Length of this fragment. 145 * This field is zero when the queue slot is empty. 146 * @unmap_len: Length of this fragment to unmap 147 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping. 148 * Only valid if @unmap_len != 0. 149 */ 150 struct efx_tx_buffer { 151 union { 152 const struct sk_buff *skb; 153 void *heap_buf; 154 }; 155 union { 156 efx_qword_t option; 157 dma_addr_t dma_addr; 158 }; 159 unsigned short flags; 160 unsigned short len; 161 unsigned short unmap_len; 162 unsigned short dma_offset; 163 }; 164 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */ 165 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */ 166 #define EFX_TX_BUF_HEAP 4 /* buffer was allocated with kmalloc() */ 167 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */ 168 #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */ 169 170 /** 171 * struct efx_tx_queue - An Efx TX queue 172 * 173 * This is a ring buffer of TX fragments. 174 * Since the TX completion path always executes on the same 175 * CPU and the xmit path can operate on different CPUs, 176 * performance is increased by ensuring that the completion 177 * path and the xmit path operate on different cache lines. 178 * This is particularly important if the xmit path is always 179 * executing on one CPU which is different from the completion 180 * path. There is also a cache line for members which are 181 * read but not written on the fast path. 182 * 183 * @efx: The associated Efx NIC 184 * @queue: DMA queue number 185 * @tso_version: Version of TSO in use for this queue. 186 * @channel: The associated channel 187 * @core_txq: The networking core TX queue structure 188 * @buffer: The software buffer ring 189 * @tsoh_page: Array of pages of TSO header buffers 190 * @txd: The hardware descriptor ring 191 * @ptr_mask: The size of the ring minus 1. 192 * @piobuf: PIO buffer region for this TX queue (shared with its partner). 193 * Size of the region is efx_piobuf_size. 194 * @piobuf_offset: Buffer offset to be specified in PIO descriptors 195 * @initialised: Has hardware queue been initialised? 196 * @read_count: Current read pointer. 197 * This is the number of buffers that have been removed from both rings. 198 * @old_write_count: The value of @write_count when last checked. 199 * This is here for performance reasons. The xmit path will 200 * only get the up-to-date value of @write_count if this 201 * variable indicates that the queue is empty. This is to 202 * avoid cache-line ping-pong between the xmit path and the 203 * completion path. 204 * @merge_events: Number of TX merged completion events 205 * @insert_count: Current insert pointer 206 * This is the number of buffers that have been added to the 207 * software ring. 208 * @write_count: Current write pointer 209 * This is the number of buffers that have been added to the 210 * hardware ring. 211 * @old_read_count: The value of read_count when last checked. 212 * This is here for performance reasons. The xmit path will 213 * only get the up-to-date value of read_count if this 214 * variable indicates that the queue is full. This is to 215 * avoid cache-line ping-pong between the xmit path and the 216 * completion path. 217 * @tso_bursts: Number of times TSO xmit invoked by kernel 218 * @tso_long_headers: Number of packets with headers too long for standard 219 * blocks 220 * @tso_packets: Number of packets via the TSO xmit path 221 * @pushes: Number of times the TX push feature has been used 222 * @pio_packets: Number of times the TX PIO feature has been used 223 * @xmit_more_available: Are any packets waiting to be pushed to the NIC 224 * @empty_read_count: If the completion path has seen the queue as empty 225 * and the transmission path has not yet checked this, the value of 226 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0. 227 */ 228 struct efx_tx_queue { 229 /* Members which don't change on the fast path */ 230 struct efx_nic *efx ____cacheline_aligned_in_smp; 231 unsigned queue; 232 unsigned int tso_version; 233 struct efx_channel *channel; 234 struct netdev_queue *core_txq; 235 struct efx_tx_buffer *buffer; 236 struct efx_buffer *tsoh_page; 237 struct efx_special_buffer txd; 238 unsigned int ptr_mask; 239 void __iomem *piobuf; 240 unsigned int piobuf_offset; 241 bool initialised; 242 243 /* Members used mainly on the completion path */ 244 unsigned int read_count ____cacheline_aligned_in_smp; 245 unsigned int old_write_count; 246 unsigned int merge_events; 247 unsigned int bytes_compl; 248 unsigned int pkts_compl; 249 250 /* Members used only on the xmit path */ 251 unsigned int insert_count ____cacheline_aligned_in_smp; 252 unsigned int write_count; 253 unsigned int old_read_count; 254 unsigned int tso_bursts; 255 unsigned int tso_long_headers; 256 unsigned int tso_packets; 257 unsigned int pushes; 258 unsigned int pio_packets; 259 bool xmit_more_available; 260 /* Statistics to supplement MAC stats */ 261 unsigned long tx_packets; 262 263 /* Members shared between paths and sometimes updated */ 264 unsigned int empty_read_count ____cacheline_aligned_in_smp; 265 #define EFX_EMPTY_COUNT_VALID 0x80000000 266 atomic_t flush_outstanding; 267 }; 268 269 /** 270 * struct efx_rx_buffer - An Efx RX data buffer 271 * @dma_addr: DMA base address of the buffer 272 * @page: The associated page buffer. 273 * Will be %NULL if the buffer slot is currently free. 274 * @page_offset: If pending: offset in @page of DMA base address. 275 * If completed: offset in @page of Ethernet header. 276 * @len: If pending: length for DMA descriptor. 277 * If completed: received length, excluding hash prefix. 278 * @flags: Flags for buffer and packet state. These are only set on the 279 * first buffer of a scattered packet. 280 */ 281 struct efx_rx_buffer { 282 dma_addr_t dma_addr; 283 struct page *page; 284 u16 page_offset; 285 u16 len; 286 u16 flags; 287 }; 288 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001 289 #define EFX_RX_PKT_CSUMMED 0x0002 290 #define EFX_RX_PKT_DISCARD 0x0004 291 #define EFX_RX_PKT_TCP 0x0040 292 #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */ 293 294 /** 295 * struct efx_rx_page_state - Page-based rx buffer state 296 * 297 * Inserted at the start of every page allocated for receive buffers. 298 * Used to facilitate sharing dma mappings between recycled rx buffers 299 * and those passed up to the kernel. 300 * 301 * @dma_addr: The dma address of this page. 302 */ 303 struct efx_rx_page_state { 304 dma_addr_t dma_addr; 305 306 unsigned int __pad[0] ____cacheline_aligned; 307 }; 308 309 /** 310 * struct efx_rx_queue - An Efx RX queue 311 * @efx: The associated Efx NIC 312 * @core_index: Index of network core RX queue. Will be >= 0 iff this 313 * is associated with a real RX queue. 314 * @buffer: The software buffer ring 315 * @rxd: The hardware descriptor ring 316 * @ptr_mask: The size of the ring minus 1. 317 * @refill_enabled: Enable refill whenever fill level is low 318 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as 319 * @rxq_flush_pending. 320 * @added_count: Number of buffers added to the receive queue. 321 * @notified_count: Number of buffers given to NIC (<= @added_count). 322 * @removed_count: Number of buffers removed from the receive queue. 323 * @scatter_n: Used by NIC specific receive code. 324 * @scatter_len: Used by NIC specific receive code. 325 * @page_ring: The ring to store DMA mapped pages for reuse. 326 * @page_add: Counter to calculate the write pointer for the recycle ring. 327 * @page_remove: Counter to calculate the read pointer for the recycle ring. 328 * @page_recycle_count: The number of pages that have been recycled. 329 * @page_recycle_failed: The number of pages that couldn't be recycled because 330 * the kernel still held a reference to them. 331 * @page_recycle_full: The number of pages that were released because the 332 * recycle ring was full. 333 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1. 334 * @max_fill: RX descriptor maximum fill level (<= ring size) 335 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill 336 * (<= @max_fill) 337 * @min_fill: RX descriptor minimum non-zero fill level. 338 * This records the minimum fill level observed when a ring 339 * refill was triggered. 340 * @recycle_count: RX buffer recycle counter. 341 * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). 342 */ 343 struct efx_rx_queue { 344 struct efx_nic *efx; 345 int core_index; 346 struct efx_rx_buffer *buffer; 347 struct efx_special_buffer rxd; 348 unsigned int ptr_mask; 349 bool refill_enabled; 350 bool flush_pending; 351 352 unsigned int added_count; 353 unsigned int notified_count; 354 unsigned int removed_count; 355 unsigned int scatter_n; 356 unsigned int scatter_len; 357 struct page **page_ring; 358 unsigned int page_add; 359 unsigned int page_remove; 360 unsigned int page_recycle_count; 361 unsigned int page_recycle_failed; 362 unsigned int page_recycle_full; 363 unsigned int page_ptr_mask; 364 unsigned int max_fill; 365 unsigned int fast_fill_trigger; 366 unsigned int min_fill; 367 unsigned int min_overfill; 368 unsigned int recycle_count; 369 struct timer_list slow_fill; 370 unsigned int slow_fill_count; 371 /* Statistics to supplement MAC stats */ 372 unsigned long rx_packets; 373 }; 374 375 enum efx_sync_events_state { 376 SYNC_EVENTS_DISABLED = 0, 377 SYNC_EVENTS_QUIESCENT, 378 SYNC_EVENTS_REQUESTED, 379 SYNC_EVENTS_VALID, 380 }; 381 382 /** 383 * struct efx_channel - An Efx channel 384 * 385 * A channel comprises an event queue, at least one TX queue, at least 386 * one RX queue, and an associated tasklet for processing the event 387 * queue. 388 * 389 * @efx: Associated Efx NIC 390 * @channel: Channel instance number 391 * @type: Channel type definition 392 * @eventq_init: Event queue initialised flag 393 * @enabled: Channel enabled indicator 394 * @irq: IRQ number (MSI and MSI-X only) 395 * @irq_moderation: IRQ moderation value (in hardware ticks) 396 * @napi_dev: Net device used with NAPI 397 * @napi_str: NAPI control structure 398 * @state: state for NAPI vs busy polling 399 * @state_lock: lock protecting @state 400 * @eventq: Event queue buffer 401 * @eventq_mask: Event queue pointer mask 402 * @eventq_read_ptr: Event queue read pointer 403 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel 404 * @irq_count: Number of IRQs since last adaptive moderation decision 405 * @irq_mod_score: IRQ moderation score 406 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors 407 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors 408 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors 409 * @n_rx_mcast_mismatch: Count of unmatched multicast frames 410 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors 411 * @n_rx_overlength: Count of RX_OVERLENGTH errors 412 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun 413 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to 414 * lack of descriptors 415 * @n_rx_merge_events: Number of RX merged completion events 416 * @n_rx_merge_packets: Number of RX packets completed by merged events 417 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by 418 * __efx_rx_packet(), or zero if there is none 419 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered 420 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0 421 * @rx_queue: RX queue for this channel 422 * @tx_queue: TX queues for this channel 423 * @sync_events_state: Current state of sync events on this channel 424 * @sync_timestamp_major: Major part of the last ptp sync event 425 * @sync_timestamp_minor: Minor part of the last ptp sync event 426 */ 427 struct efx_channel { 428 struct efx_nic *efx; 429 int channel; 430 const struct efx_channel_type *type; 431 bool eventq_init; 432 bool enabled; 433 int irq; 434 unsigned int irq_moderation; 435 struct net_device *napi_dev; 436 struct napi_struct napi_str; 437 #ifdef CONFIG_NET_RX_BUSY_POLL 438 unsigned long busy_poll_state; 439 #endif 440 struct efx_special_buffer eventq; 441 unsigned int eventq_mask; 442 unsigned int eventq_read_ptr; 443 int event_test_cpu; 444 445 unsigned int irq_count; 446 unsigned int irq_mod_score; 447 #ifdef CONFIG_RFS_ACCEL 448 unsigned int rfs_filters_added; 449 #endif 450 451 unsigned n_rx_tobe_disc; 452 unsigned n_rx_ip_hdr_chksum_err; 453 unsigned n_rx_tcp_udp_chksum_err; 454 unsigned n_rx_mcast_mismatch; 455 unsigned n_rx_frm_trunc; 456 unsigned n_rx_overlength; 457 unsigned n_skbuff_leaks; 458 unsigned int n_rx_nodesc_trunc; 459 unsigned int n_rx_merge_events; 460 unsigned int n_rx_merge_packets; 461 462 unsigned int rx_pkt_n_frags; 463 unsigned int rx_pkt_index; 464 465 struct efx_rx_queue rx_queue; 466 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES]; 467 468 enum efx_sync_events_state sync_events_state; 469 u32 sync_timestamp_major; 470 u32 sync_timestamp_minor; 471 }; 472 473 #ifdef CONFIG_NET_RX_BUSY_POLL 474 enum efx_channel_busy_poll_state { 475 EFX_CHANNEL_STATE_IDLE = 0, 476 EFX_CHANNEL_STATE_NAPI = BIT(0), 477 EFX_CHANNEL_STATE_NAPI_REQ_BIT = 1, 478 EFX_CHANNEL_STATE_NAPI_REQ = BIT(1), 479 EFX_CHANNEL_STATE_POLL_BIT = 2, 480 EFX_CHANNEL_STATE_POLL = BIT(2), 481 EFX_CHANNEL_STATE_DISABLE_BIT = 3, 482 }; 483 484 static inline void efx_channel_busy_poll_init(struct efx_channel *channel) 485 { 486 WRITE_ONCE(channel->busy_poll_state, EFX_CHANNEL_STATE_IDLE); 487 } 488 489 /* Called from the device poll routine to get ownership of a channel. */ 490 static inline bool efx_channel_lock_napi(struct efx_channel *channel) 491 { 492 unsigned long prev, old = READ_ONCE(channel->busy_poll_state); 493 494 while (1) { 495 switch (old) { 496 case EFX_CHANNEL_STATE_POLL: 497 /* Ensure efx_channel_try_lock_poll() wont starve us */ 498 set_bit(EFX_CHANNEL_STATE_NAPI_REQ_BIT, 499 &channel->busy_poll_state); 500 /* fallthrough */ 501 case EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_NAPI_REQ: 502 return false; 503 default: 504 break; 505 } 506 prev = cmpxchg(&channel->busy_poll_state, old, 507 EFX_CHANNEL_STATE_NAPI); 508 if (unlikely(prev != old)) { 509 /* This is likely to mean we've just entered polling 510 * state. Go back round to set the REQ bit. 511 */ 512 old = prev; 513 continue; 514 } 515 return true; 516 } 517 } 518 519 static inline void efx_channel_unlock_napi(struct efx_channel *channel) 520 { 521 /* Make sure write has completed from efx_channel_lock_napi() */ 522 smp_wmb(); 523 WRITE_ONCE(channel->busy_poll_state, EFX_CHANNEL_STATE_IDLE); 524 } 525 526 /* Called from efx_busy_poll(). */ 527 static inline bool efx_channel_try_lock_poll(struct efx_channel *channel) 528 { 529 return cmpxchg(&channel->busy_poll_state, EFX_CHANNEL_STATE_IDLE, 530 EFX_CHANNEL_STATE_POLL) == EFX_CHANNEL_STATE_IDLE; 531 } 532 533 static inline void efx_channel_unlock_poll(struct efx_channel *channel) 534 { 535 clear_bit_unlock(EFX_CHANNEL_STATE_POLL_BIT, &channel->busy_poll_state); 536 } 537 538 static inline bool efx_channel_busy_polling(struct efx_channel *channel) 539 { 540 return test_bit(EFX_CHANNEL_STATE_POLL_BIT, &channel->busy_poll_state); 541 } 542 543 static inline void efx_channel_enable(struct efx_channel *channel) 544 { 545 clear_bit_unlock(EFX_CHANNEL_STATE_DISABLE_BIT, 546 &channel->busy_poll_state); 547 } 548 549 /* Stop further polling or napi access. 550 * Returns false if the channel is currently busy polling. 551 */ 552 static inline bool efx_channel_disable(struct efx_channel *channel) 553 { 554 set_bit(EFX_CHANNEL_STATE_DISABLE_BIT, &channel->busy_poll_state); 555 /* Implicit barrier in efx_channel_busy_polling() */ 556 return !efx_channel_busy_polling(channel); 557 } 558 559 #else /* CONFIG_NET_RX_BUSY_POLL */ 560 561 static inline void efx_channel_busy_poll_init(struct efx_channel *channel) 562 { 563 } 564 565 static inline bool efx_channel_lock_napi(struct efx_channel *channel) 566 { 567 return true; 568 } 569 570 static inline void efx_channel_unlock_napi(struct efx_channel *channel) 571 { 572 } 573 574 static inline bool efx_channel_try_lock_poll(struct efx_channel *channel) 575 { 576 return false; 577 } 578 579 static inline void efx_channel_unlock_poll(struct efx_channel *channel) 580 { 581 } 582 583 static inline bool efx_channel_busy_polling(struct efx_channel *channel) 584 { 585 return false; 586 } 587 588 static inline void efx_channel_enable(struct efx_channel *channel) 589 { 590 } 591 592 static inline bool efx_channel_disable(struct efx_channel *channel) 593 { 594 return true; 595 } 596 #endif /* CONFIG_NET_RX_BUSY_POLL */ 597 598 /** 599 * struct efx_msi_context - Context for each MSI 600 * @efx: The associated NIC 601 * @index: Index of the channel/IRQ 602 * @name: Name of the channel/IRQ 603 * 604 * Unlike &struct efx_channel, this is never reallocated and is always 605 * safe for the IRQ handler to access. 606 */ 607 struct efx_msi_context { 608 struct efx_nic *efx; 609 unsigned int index; 610 char name[IFNAMSIZ + 6]; 611 }; 612 613 /** 614 * struct efx_channel_type - distinguishes traffic and extra channels 615 * @handle_no_channel: Handle failure to allocate an extra channel 616 * @pre_probe: Set up extra state prior to initialisation 617 * @post_remove: Tear down extra state after finalisation, if allocated. 618 * May be called on channels that have not been probed. 619 * @get_name: Generate the channel's name (used for its IRQ handler) 620 * @copy: Copy the channel state prior to reallocation. May be %NULL if 621 * reallocation is not supported. 622 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb() 623 * @keep_eventq: Flag for whether event queue should be kept initialised 624 * while the device is stopped 625 */ 626 struct efx_channel_type { 627 void (*handle_no_channel)(struct efx_nic *); 628 int (*pre_probe)(struct efx_channel *); 629 void (*post_remove)(struct efx_channel *); 630 void (*get_name)(struct efx_channel *, char *buf, size_t len); 631 struct efx_channel *(*copy)(const struct efx_channel *); 632 bool (*receive_skb)(struct efx_channel *, struct sk_buff *); 633 bool keep_eventq; 634 }; 635 636 enum efx_led_mode { 637 EFX_LED_OFF = 0, 638 EFX_LED_ON = 1, 639 EFX_LED_DEFAULT = 2 640 }; 641 642 #define STRING_TABLE_LOOKUP(val, member) \ 643 ((val) < member ## _max) ? member ## _names[val] : "(invalid)" 644 645 extern const char *const efx_loopback_mode_names[]; 646 extern const unsigned int efx_loopback_mode_max; 647 #define LOOPBACK_MODE(efx) \ 648 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) 649 650 extern const char *const efx_reset_type_names[]; 651 extern const unsigned int efx_reset_type_max; 652 #define RESET_TYPE(type) \ 653 STRING_TABLE_LOOKUP(type, efx_reset_type) 654 655 enum efx_int_mode { 656 /* Be careful if altering to correct macro below */ 657 EFX_INT_MODE_MSIX = 0, 658 EFX_INT_MODE_MSI = 1, 659 EFX_INT_MODE_LEGACY = 2, 660 EFX_INT_MODE_MAX /* Insert any new items before this */ 661 }; 662 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) 663 664 enum nic_state { 665 STATE_UNINIT = 0, /* device being probed/removed or is frozen */ 666 STATE_READY = 1, /* hardware ready and netdev registered */ 667 STATE_DISABLED = 2, /* device disabled due to hardware errors */ 668 STATE_RECOVERY = 3, /* device recovering from PCI error */ 669 }; 670 671 /* Forward declaration */ 672 struct efx_nic; 673 674 /* Pseudo bit-mask flow control field */ 675 #define EFX_FC_RX FLOW_CTRL_RX 676 #define EFX_FC_TX FLOW_CTRL_TX 677 #define EFX_FC_AUTO 4 678 679 /** 680 * struct efx_link_state - Current state of the link 681 * @up: Link is up 682 * @fd: Link is full-duplex 683 * @fc: Actual flow control flags 684 * @speed: Link speed (Mbps) 685 */ 686 struct efx_link_state { 687 bool up; 688 bool fd; 689 u8 fc; 690 unsigned int speed; 691 }; 692 693 static inline bool efx_link_state_equal(const struct efx_link_state *left, 694 const struct efx_link_state *right) 695 { 696 return left->up == right->up && left->fd == right->fd && 697 left->fc == right->fc && left->speed == right->speed; 698 } 699 700 /** 701 * struct efx_phy_operations - Efx PHY operations table 702 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, 703 * efx->loopback_modes. 704 * @init: Initialise PHY 705 * @fini: Shut down PHY 706 * @reconfigure: Reconfigure PHY (e.g. for new link parameters) 707 * @poll: Update @link_state and report whether it changed. 708 * Serialised by the mac_lock. 709 * @get_settings: Get ethtool settings. Serialised by the mac_lock. 710 * @set_settings: Set ethtool settings. Serialised by the mac_lock. 711 * @set_npage_adv: Set abilities advertised in (Extended) Next Page 712 * (only needed where AN bit is set in mmds) 713 * @test_alive: Test that PHY is 'alive' (online) 714 * @test_name: Get the name of a PHY-specific test/result 715 * @run_tests: Run tests and record results as appropriate (offline). 716 * Flags are the ethtool tests flags. 717 */ 718 struct efx_phy_operations { 719 int (*probe) (struct efx_nic *efx); 720 int (*init) (struct efx_nic *efx); 721 void (*fini) (struct efx_nic *efx); 722 void (*remove) (struct efx_nic *efx); 723 int (*reconfigure) (struct efx_nic *efx); 724 bool (*poll) (struct efx_nic *efx); 725 void (*get_settings) (struct efx_nic *efx, 726 struct ethtool_cmd *ecmd); 727 int (*set_settings) (struct efx_nic *efx, 728 struct ethtool_cmd *ecmd); 729 void (*set_npage_adv) (struct efx_nic *efx, u32); 730 int (*test_alive) (struct efx_nic *efx); 731 const char *(*test_name) (struct efx_nic *efx, unsigned int index); 732 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); 733 int (*get_module_eeprom) (struct efx_nic *efx, 734 struct ethtool_eeprom *ee, 735 u8 *data); 736 int (*get_module_info) (struct efx_nic *efx, 737 struct ethtool_modinfo *modinfo); 738 }; 739 740 /** 741 * enum efx_phy_mode - PHY operating mode flags 742 * @PHY_MODE_NORMAL: on and should pass traffic 743 * @PHY_MODE_TX_DISABLED: on with TX disabled 744 * @PHY_MODE_LOW_POWER: set to low power through MDIO 745 * @PHY_MODE_OFF: switched off through external control 746 * @PHY_MODE_SPECIAL: on but will not pass traffic 747 */ 748 enum efx_phy_mode { 749 PHY_MODE_NORMAL = 0, 750 PHY_MODE_TX_DISABLED = 1, 751 PHY_MODE_LOW_POWER = 2, 752 PHY_MODE_OFF = 4, 753 PHY_MODE_SPECIAL = 8, 754 }; 755 756 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) 757 { 758 return !!(mode & ~PHY_MODE_TX_DISABLED); 759 } 760 761 /** 762 * struct efx_hw_stat_desc - Description of a hardware statistic 763 * @name: Name of the statistic as visible through ethtool, or %NULL if 764 * it should not be exposed 765 * @dma_width: Width in bits (0 for non-DMA statistics) 766 * @offset: Offset within stats (ignored for non-DMA statistics) 767 */ 768 struct efx_hw_stat_desc { 769 const char *name; 770 u16 dma_width; 771 u16 offset; 772 }; 773 774 /* Number of bits used in a multicast filter hash address */ 775 #define EFX_MCAST_HASH_BITS 8 776 777 /* Number of (single-bit) entries in a multicast filter hash */ 778 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) 779 780 /* An Efx multicast filter hash */ 781 union efx_multicast_hash { 782 u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; 783 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; 784 }; 785 786 struct vfdi_status; 787 788 /** 789 * struct efx_nic - an Efx NIC 790 * @name: Device name (net device name or bus id before net device registered) 791 * @pci_dev: The PCI device 792 * @node: List node for maintaning primary/secondary function lists 793 * @primary: &struct efx_nic instance for the primary function of this 794 * controller. May be the same structure, and may be %NULL if no 795 * primary function is bound. Serialised by rtnl_lock. 796 * @secondary_list: List of &struct efx_nic instances for the secondary PCI 797 * functions of the controller, if this is for the primary function. 798 * Serialised by rtnl_lock. 799 * @type: Controller type attributes 800 * @legacy_irq: IRQ number 801 * @workqueue: Workqueue for port reconfigures and the HW monitor. 802 * Work items do not hold and must not acquire RTNL. 803 * @workqueue_name: Name of workqueue 804 * @reset_work: Scheduled reset workitem 805 * @membase_phys: Memory BAR value as physical address 806 * @membase: Memory BAR value 807 * @interrupt_mode: Interrupt mode 808 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds 809 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues 810 * @irq_rx_moderation: IRQ moderation time for RX event queues 811 * @msg_enable: Log message enable flags 812 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock. 813 * @reset_pending: Bitmask for pending resets 814 * @tx_queue: TX DMA queues 815 * @rx_queue: RX DMA queues 816 * @channel: Channels 817 * @msi_context: Context for each MSI 818 * @extra_channel_types: Types of extra (non-traffic) channels that 819 * should be allocated for this NIC 820 * @rxq_entries: Size of receive queues requested by user. 821 * @txq_entries: Size of transmit queues requested by user. 822 * @txq_stop_thresh: TX queue fill level at or above which we stop it. 823 * @txq_wake_thresh: TX queue fill level at or below which we wake it. 824 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches 825 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches 826 * @sram_lim_qw: Qword address limit of SRAM 827 * @next_buffer_table: First available buffer table id 828 * @n_channels: Number of channels in use 829 * @n_rx_channels: Number of channels used for RX (= number of RX queues) 830 * @n_tx_channels: Number of channels used for TX 831 * @rx_ip_align: RX DMA address offset to have IP header aligned in 832 * in accordance with NET_IP_ALIGN 833 * @rx_dma_len: Current maximum RX DMA length 834 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer 835 * @rx_buffer_truesize: Amortised allocation size of an RX buffer, 836 * for use in sk_buff::truesize 837 * @rx_prefix_size: Size of RX prefix before packet data 838 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data 839 * (valid only if @rx_prefix_size != 0; always negative) 840 * @rx_packet_len_offset: Offset of RX packet length from start of packet data 841 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative) 842 * @rx_packet_ts_offset: Offset of timestamp from start of packet data 843 * (valid only if channel->sync_timestamps_enabled; always negative) 844 * @rx_hash_key: Toeplitz hash key for RSS 845 * @rx_indir_table: Indirection table for RSS 846 * @rx_scatter: Scatter mode enabled for receives 847 * @int_error_count: Number of internal errors seen recently 848 * @int_error_expire: Time at which error count will be expired 849 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will 850 * acknowledge but do nothing else. 851 * @irq_status: Interrupt status buffer 852 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 853 * @irq_level: IRQ level/index for IRQs not triggered by an event queue 854 * @selftest_work: Work item for asynchronous self-test 855 * @mtd_list: List of MTDs attached to the NIC 856 * @nic_data: Hardware dependent state 857 * @mcdi: Management-Controller-to-Driver Interface state 858 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, 859 * efx_monitor() and efx_reconfigure_port() 860 * @port_enabled: Port enabled indicator. 861 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and 862 * efx_mac_work() with kernel interfaces. Safe to read under any 863 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must 864 * be held to modify it. 865 * @port_initialized: Port initialized? 866 * @net_dev: Operating system network device. Consider holding the rtnl lock 867 * @stats_buffer: DMA buffer for statistics 868 * @phy_type: PHY type 869 * @phy_op: PHY interface 870 * @phy_data: PHY private data (including PHY-specific stats) 871 * @mdio: PHY MDIO interface 872 * @mdio_bus: PHY MDIO bus ID (only used by Siena) 873 * @phy_mode: PHY operating mode. Serialised by @mac_lock. 874 * @link_advertising: Autonegotiation advertising flags 875 * @link_state: Current state of the link 876 * @n_link_state_changes: Number of times the link has changed state 877 * @unicast_filter: Flag for Falcon-arch simple unicast filter. 878 * Protected by @mac_lock. 879 * @multicast_hash: Multicast hash table for Falcon-arch. 880 * Protected by @mac_lock. 881 * @wanted_fc: Wanted flow control flags 882 * @fc_disable: When non-zero flow control is disabled. Typically used to 883 * ensure that network back pressure doesn't delay dma queue flushes. 884 * Serialised by the rtnl lock. 885 * @mac_work: Work item for changing MAC promiscuity and multicast hash 886 * @loopback_mode: Loopback status 887 * @loopback_modes: Supported loopback mode bitmask 888 * @loopback_selftest: Offline self-test private state 889 * @filter_sem: Filter table rw_semaphore, for freeing the table 890 * @filter_lock: Filter table lock, for mere content changes 891 * @filter_state: Architecture-dependent filter table state 892 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS, 893 * indexed by filter ID 894 * @rps_expire_index: Next index to check for expiry in @rps_flow_id 895 * @active_queues: Count of RX and TX queues that haven't been flushed and drained. 896 * @rxq_flush_pending: Count of number of receive queues that need to be flushed. 897 * Decremented when the efx_flush_rx_queue() is called. 898 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet 899 * completed (either success or failure). Not used when MCDI is used to 900 * flush receive queues. 901 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions. 902 * @vf_count: Number of VFs intended to be enabled. 903 * @vf_init_count: Number of VFs that have been fully initialised. 904 * @vi_scale: log2 number of vnics per VF. 905 * @ptp_data: PTP state data 906 * @vpd_sn: Serial number read from VPD 907 * @monitor_work: Hardware monitor workitem 908 * @biu_lock: BIU (bus interface unit) lock 909 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This 910 * field is used by efx_test_interrupts() to verify that an 911 * interrupt has occurred. 912 * @stats_lock: Statistics update lock. Must be held when calling 913 * efx_nic_type::{update,start,stop}_stats. 914 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb 915 * @mc_promisc: Whether in multicast promiscuous mode when last changed 916 * 917 * This is stored in the private area of the &struct net_device. 918 */ 919 struct efx_nic { 920 /* The following fields should be written very rarely */ 921 922 char name[IFNAMSIZ]; 923 struct list_head node; 924 struct efx_nic *primary; 925 struct list_head secondary_list; 926 struct pci_dev *pci_dev; 927 unsigned int port_num; 928 const struct efx_nic_type *type; 929 int legacy_irq; 930 bool eeh_disabled_legacy_irq; 931 struct workqueue_struct *workqueue; 932 char workqueue_name[16]; 933 struct work_struct reset_work; 934 resource_size_t membase_phys; 935 void __iomem *membase; 936 937 enum efx_int_mode interrupt_mode; 938 unsigned int timer_quantum_ns; 939 bool irq_rx_adaptive; 940 unsigned int irq_rx_moderation; 941 u32 msg_enable; 942 943 enum nic_state state; 944 unsigned long reset_pending; 945 946 struct efx_channel *channel[EFX_MAX_CHANNELS]; 947 struct efx_msi_context msi_context[EFX_MAX_CHANNELS]; 948 const struct efx_channel_type * 949 extra_channel_type[EFX_MAX_EXTRA_CHANNELS]; 950 951 unsigned rxq_entries; 952 unsigned txq_entries; 953 unsigned int txq_stop_thresh; 954 unsigned int txq_wake_thresh; 955 956 unsigned tx_dc_base; 957 unsigned rx_dc_base; 958 unsigned sram_lim_qw; 959 unsigned next_buffer_table; 960 961 unsigned int max_channels; 962 unsigned int max_tx_channels; 963 unsigned n_channels; 964 unsigned n_rx_channels; 965 unsigned rss_spread; 966 unsigned tx_channel_offset; 967 unsigned n_tx_channels; 968 unsigned int rx_ip_align; 969 unsigned int rx_dma_len; 970 unsigned int rx_buffer_order; 971 unsigned int rx_buffer_truesize; 972 unsigned int rx_page_buf_step; 973 unsigned int rx_bufs_per_page; 974 unsigned int rx_pages_per_batch; 975 unsigned int rx_prefix_size; 976 int rx_packet_hash_offset; 977 int rx_packet_len_offset; 978 int rx_packet_ts_offset; 979 u8 rx_hash_key[40]; 980 u32 rx_indir_table[128]; 981 bool rx_scatter; 982 983 unsigned int_error_count; 984 unsigned long int_error_expire; 985 986 bool irq_soft_enabled; 987 struct efx_buffer irq_status; 988 unsigned irq_zero_count; 989 unsigned irq_level; 990 struct delayed_work selftest_work; 991 992 #ifdef CONFIG_SFC_MTD 993 struct list_head mtd_list; 994 #endif 995 996 void *nic_data; 997 struct efx_mcdi_data *mcdi; 998 999 struct mutex mac_lock; 1000 struct work_struct mac_work; 1001 bool port_enabled; 1002 1003 bool mc_bist_for_other_fn; 1004 bool port_initialized; 1005 struct net_device *net_dev; 1006 1007 struct efx_buffer stats_buffer; 1008 u64 rx_nodesc_drops_total; 1009 u64 rx_nodesc_drops_while_down; 1010 bool rx_nodesc_drops_prev_state; 1011 1012 unsigned int phy_type; 1013 const struct efx_phy_operations *phy_op; 1014 void *phy_data; 1015 struct mdio_if_info mdio; 1016 unsigned int mdio_bus; 1017 enum efx_phy_mode phy_mode; 1018 1019 u32 link_advertising; 1020 struct efx_link_state link_state; 1021 unsigned int n_link_state_changes; 1022 1023 bool unicast_filter; 1024 union efx_multicast_hash multicast_hash; 1025 u8 wanted_fc; 1026 unsigned fc_disable; 1027 1028 atomic_t rx_reset; 1029 enum efx_loopback_mode loopback_mode; 1030 u64 loopback_modes; 1031 1032 void *loopback_selftest; 1033 1034 struct rw_semaphore filter_sem; 1035 spinlock_t filter_lock; 1036 void *filter_state; 1037 #ifdef CONFIG_RFS_ACCEL 1038 u32 *rps_flow_id; 1039 unsigned int rps_expire_index; 1040 #endif 1041 1042 atomic_t active_queues; 1043 atomic_t rxq_flush_pending; 1044 atomic_t rxq_flush_outstanding; 1045 wait_queue_head_t flush_wq; 1046 1047 #ifdef CONFIG_SFC_SRIOV 1048 unsigned vf_count; 1049 unsigned vf_init_count; 1050 unsigned vi_scale; 1051 #endif 1052 1053 struct efx_ptp_data *ptp_data; 1054 1055 char *vpd_sn; 1056 1057 /* The following fields may be written more often */ 1058 1059 struct delayed_work monitor_work ____cacheline_aligned_in_smp; 1060 spinlock_t biu_lock; 1061 int last_irq_cpu; 1062 spinlock_t stats_lock; 1063 atomic_t n_rx_noskb_drops; 1064 bool mc_promisc; 1065 }; 1066 1067 static inline int efx_dev_registered(struct efx_nic *efx) 1068 { 1069 return efx->net_dev->reg_state == NETREG_REGISTERED; 1070 } 1071 1072 static inline unsigned int efx_port_num(struct efx_nic *efx) 1073 { 1074 return efx->port_num; 1075 } 1076 1077 struct efx_mtd_partition { 1078 struct list_head node; 1079 struct mtd_info mtd; 1080 const char *dev_type_name; 1081 const char *type_name; 1082 char name[IFNAMSIZ + 20]; 1083 }; 1084 1085 /** 1086 * struct efx_nic_type - Efx device type definition 1087 * @mem_bar: Get the memory BAR 1088 * @mem_map_size: Get memory BAR mapped size 1089 * @probe: Probe the controller 1090 * @remove: Free resources allocated by probe() 1091 * @init: Initialise the controller 1092 * @dimension_resources: Dimension controller resources (buffer table, 1093 * and VIs once the available interrupt resources are clear) 1094 * @fini: Shut down the controller 1095 * @monitor: Periodic function for polling link state and hardware monitor 1096 * @map_reset_reason: Map ethtool reset reason to a reset method 1097 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible 1098 * @reset: Reset the controller hardware and possibly the PHY. This will 1099 * be called while the controller is uninitialised. 1100 * @probe_port: Probe the MAC and PHY 1101 * @remove_port: Free resources allocated by probe_port() 1102 * @handle_global_event: Handle a "global" event (may be %NULL) 1103 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues) 1104 * @prepare_flush: Prepare the hardware for flushing the DMA queues 1105 * (for Falcon architecture) 1106 * @finish_flush: Clean up after flushing the DMA queues (for Falcon 1107 * architecture) 1108 * @prepare_flr: Prepare for an FLR 1109 * @finish_flr: Clean up after an FLR 1110 * @describe_stats: Describe statistics for ethtool 1111 * @update_stats: Update statistics not provided by event handling. 1112 * Either argument may be %NULL. 1113 * @start_stats: Start the regular fetching of statistics 1114 * @pull_stats: Pull stats from the NIC and wait until they arrive. 1115 * @stop_stats: Stop the regular fetching of statistics 1116 * @set_id_led: Set state of identifying LED or revert to automatic function 1117 * @push_irq_moderation: Apply interrupt moderation value 1118 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY 1119 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL) 1120 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings 1121 * to the hardware. Serialised by the mac_lock. 1122 * @check_mac_fault: Check MAC fault state. True if fault present. 1123 * @get_wol: Get WoL configuration from driver state 1124 * @set_wol: Push WoL configuration to the NIC 1125 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) 1126 * @test_chip: Test registers. May use efx_farch_test_registers(), and is 1127 * expected to reset the NIC. 1128 * @test_nvram: Test validity of NVRAM contents 1129 * @mcdi_request: Send an MCDI request with the given header and SDU. 1130 * The SDU length may be any value from 0 up to the protocol- 1131 * defined maximum, but its buffer will be padded to a multiple 1132 * of 4 bytes. 1133 * @mcdi_poll_response: Test whether an MCDI response is available. 1134 * @mcdi_read_response: Read the MCDI response PDU. The offset will 1135 * be a multiple of 4. The length may not be, but the buffer 1136 * will be padded so it is safe to round up. 1137 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so, 1138 * return an appropriate error code for aborting any current 1139 * request; otherwise return 0. 1140 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must 1141 * be separately enabled after this. 1142 * @irq_test_generate: Generate a test IRQ 1143 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event 1144 * queue must be separately disabled before this. 1145 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is 1146 * a pointer to the &struct efx_msi_context for the channel. 1147 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument 1148 * is a pointer to the &struct efx_nic. 1149 * @tx_probe: Allocate resources for TX queue 1150 * @tx_init: Initialise TX queue on the NIC 1151 * @tx_remove: Free resources for TX queue 1152 * @tx_write: Write TX descriptors and doorbell 1153 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC 1154 * @rx_probe: Allocate resources for RX queue 1155 * @rx_init: Initialise RX queue on the NIC 1156 * @rx_remove: Free resources for RX queue 1157 * @rx_write: Write RX descriptors and doorbell 1158 * @rx_defer_refill: Generate a refill reminder event 1159 * @ev_probe: Allocate resources for event queue 1160 * @ev_init: Initialise event queue on the NIC 1161 * @ev_fini: Deinitialise event queue on the NIC 1162 * @ev_remove: Free resources for event queue 1163 * @ev_process: Process events for a queue, up to the given NAPI quota 1164 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ 1165 * @ev_test_generate: Generate a test event 1166 * @filter_table_probe: Probe filter capabilities and set up filter software state 1167 * @filter_table_restore: Restore filters removed from hardware 1168 * @filter_table_remove: Remove filters from hardware and tear down software state 1169 * @filter_update_rx_scatter: Update filters after change to rx scatter setting 1170 * @filter_insert: add or replace a filter 1171 * @filter_remove_safe: remove a filter by ID, carefully 1172 * @filter_get_safe: retrieve a filter by ID, carefully 1173 * @filter_clear_rx: Remove all RX filters whose priority is less than or 1174 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO 1175 * @filter_count_rx_used: Get the number of filters in use at a given priority 1176 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1 1177 * @filter_get_rx_ids: Get list of RX filters at a given priority 1178 * @filter_rfs_insert: Add or replace a filter for RFS. This must be 1179 * atomic. The hardware change may be asynchronous but should 1180 * not be delayed for long. It may fail if this can't be done 1181 * atomically. 1182 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS. 1183 * This must check whether the specified table entry is used by RFS 1184 * and that rps_may_expire_flow() returns true for it. 1185 * @mtd_probe: Probe and add MTD partitions associated with this net device, 1186 * using efx_mtd_add() 1187 * @mtd_rename: Set an MTD partition name using the net device name 1188 * @mtd_read: Read from an MTD partition 1189 * @mtd_erase: Erase part of an MTD partition 1190 * @mtd_write: Write to an MTD partition 1191 * @mtd_sync: Wait for write-back to complete on MTD partition. This 1192 * also notifies the driver that a writer has finished using this 1193 * partition. 1194 * @ptp_write_host_time: Send host time to MC as part of sync protocol 1195 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX 1196 * timestamping, possibly only temporarily for the purposes of a reset. 1197 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags 1198 * and tx_type will already have been validated but this operation 1199 * must validate and update rx_filter. 1200 * @set_mac_address: Set the MAC address of the device 1201 * @revision: Hardware architecture revision 1202 * @txd_ptr_tbl_base: TX descriptor ring base address 1203 * @rxd_ptr_tbl_base: RX descriptor ring base address 1204 * @buf_tbl_base: Buffer table base address 1205 * @evq_ptr_tbl_base: Event queue pointer table base address 1206 * @evq_rptr_tbl_base: Event queue read-pointer table base address 1207 * @max_dma_mask: Maximum possible DMA mask 1208 * @rx_prefix_size: Size of RX prefix before packet data 1209 * @rx_hash_offset: Offset of RX flow hash within prefix 1210 * @rx_ts_offset: Offset of timestamp within prefix 1211 * @rx_buffer_padding: Size of padding at end of RX packet 1212 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers 1213 * @always_rx_scatter: NIC will always scatter packets to multiple buffers 1214 * @max_interrupt_mode: Highest capability interrupt mode supported 1215 * from &enum efx_init_mode. 1216 * @timer_period_max: Maximum period of interrupt timer (in ticks) 1217 * @offload_features: net_device feature flags for protocol offload 1218 * features implemented in hardware 1219 * @mcdi_max_ver: Maximum MCDI version supported 1220 * @hwtstamp_filters: Mask of hardware timestamp filter types supported 1221 */ 1222 struct efx_nic_type { 1223 bool is_vf; 1224 unsigned int mem_bar; 1225 unsigned int (*mem_map_size)(struct efx_nic *efx); 1226 int (*probe)(struct efx_nic *efx); 1227 void (*remove)(struct efx_nic *efx); 1228 int (*init)(struct efx_nic *efx); 1229 int (*dimension_resources)(struct efx_nic *efx); 1230 void (*fini)(struct efx_nic *efx); 1231 void (*monitor)(struct efx_nic *efx); 1232 enum reset_type (*map_reset_reason)(enum reset_type reason); 1233 int (*map_reset_flags)(u32 *flags); 1234 int (*reset)(struct efx_nic *efx, enum reset_type method); 1235 int (*probe_port)(struct efx_nic *efx); 1236 void (*remove_port)(struct efx_nic *efx); 1237 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *); 1238 int (*fini_dmaq)(struct efx_nic *efx); 1239 void (*prepare_flush)(struct efx_nic *efx); 1240 void (*finish_flush)(struct efx_nic *efx); 1241 void (*prepare_flr)(struct efx_nic *efx); 1242 void (*finish_flr)(struct efx_nic *efx); 1243 size_t (*describe_stats)(struct efx_nic *efx, u8 *names); 1244 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats, 1245 struct rtnl_link_stats64 *core_stats); 1246 void (*start_stats)(struct efx_nic *efx); 1247 void (*pull_stats)(struct efx_nic *efx); 1248 void (*stop_stats)(struct efx_nic *efx); 1249 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); 1250 void (*push_irq_moderation)(struct efx_channel *channel); 1251 int (*reconfigure_port)(struct efx_nic *efx); 1252 void (*prepare_enable_fc_tx)(struct efx_nic *efx); 1253 int (*reconfigure_mac)(struct efx_nic *efx); 1254 bool (*check_mac_fault)(struct efx_nic *efx); 1255 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); 1256 int (*set_wol)(struct efx_nic *efx, u32 type); 1257 void (*resume_wol)(struct efx_nic *efx); 1258 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests); 1259 int (*test_nvram)(struct efx_nic *efx); 1260 void (*mcdi_request)(struct efx_nic *efx, 1261 const efx_dword_t *hdr, size_t hdr_len, 1262 const efx_dword_t *sdu, size_t sdu_len); 1263 bool (*mcdi_poll_response)(struct efx_nic *efx); 1264 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu, 1265 size_t pdu_offset, size_t pdu_len); 1266 int (*mcdi_poll_reboot)(struct efx_nic *efx); 1267 void (*mcdi_reboot_detected)(struct efx_nic *efx); 1268 void (*irq_enable_master)(struct efx_nic *efx); 1269 void (*irq_test_generate)(struct efx_nic *efx); 1270 void (*irq_disable_non_ev)(struct efx_nic *efx); 1271 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id); 1272 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id); 1273 int (*tx_probe)(struct efx_tx_queue *tx_queue); 1274 void (*tx_init)(struct efx_tx_queue *tx_queue); 1275 void (*tx_remove)(struct efx_tx_queue *tx_queue); 1276 void (*tx_write)(struct efx_tx_queue *tx_queue); 1277 int (*rx_push_rss_config)(struct efx_nic *efx, bool user, 1278 const u32 *rx_indir_table); 1279 int (*rx_probe)(struct efx_rx_queue *rx_queue); 1280 void (*rx_init)(struct efx_rx_queue *rx_queue); 1281 void (*rx_remove)(struct efx_rx_queue *rx_queue); 1282 void (*rx_write)(struct efx_rx_queue *rx_queue); 1283 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue); 1284 int (*ev_probe)(struct efx_channel *channel); 1285 int (*ev_init)(struct efx_channel *channel); 1286 void (*ev_fini)(struct efx_channel *channel); 1287 void (*ev_remove)(struct efx_channel *channel); 1288 int (*ev_process)(struct efx_channel *channel, int quota); 1289 void (*ev_read_ack)(struct efx_channel *channel); 1290 void (*ev_test_generate)(struct efx_channel *channel); 1291 int (*filter_table_probe)(struct efx_nic *efx); 1292 void (*filter_table_restore)(struct efx_nic *efx); 1293 void (*filter_table_remove)(struct efx_nic *efx); 1294 void (*filter_update_rx_scatter)(struct efx_nic *efx); 1295 s32 (*filter_insert)(struct efx_nic *efx, 1296 struct efx_filter_spec *spec, bool replace); 1297 int (*filter_remove_safe)(struct efx_nic *efx, 1298 enum efx_filter_priority priority, 1299 u32 filter_id); 1300 int (*filter_get_safe)(struct efx_nic *efx, 1301 enum efx_filter_priority priority, 1302 u32 filter_id, struct efx_filter_spec *); 1303 int (*filter_clear_rx)(struct efx_nic *efx, 1304 enum efx_filter_priority priority); 1305 u32 (*filter_count_rx_used)(struct efx_nic *efx, 1306 enum efx_filter_priority priority); 1307 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx); 1308 s32 (*filter_get_rx_ids)(struct efx_nic *efx, 1309 enum efx_filter_priority priority, 1310 u32 *buf, u32 size); 1311 #ifdef CONFIG_RFS_ACCEL 1312 s32 (*filter_rfs_insert)(struct efx_nic *efx, 1313 struct efx_filter_spec *spec); 1314 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id, 1315 unsigned int index); 1316 #endif 1317 #ifdef CONFIG_SFC_MTD 1318 int (*mtd_probe)(struct efx_nic *efx); 1319 void (*mtd_rename)(struct efx_mtd_partition *part); 1320 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len, 1321 size_t *retlen, u8 *buffer); 1322 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len); 1323 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len, 1324 size_t *retlen, const u8 *buffer); 1325 int (*mtd_sync)(struct mtd_info *mtd); 1326 #endif 1327 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time); 1328 int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp); 1329 int (*ptp_set_ts_config)(struct efx_nic *efx, 1330 struct hwtstamp_config *init); 1331 int (*sriov_configure)(struct efx_nic *efx, int num_vfs); 1332 int (*sriov_init)(struct efx_nic *efx); 1333 void (*sriov_fini)(struct efx_nic *efx); 1334 bool (*sriov_wanted)(struct efx_nic *efx); 1335 void (*sriov_reset)(struct efx_nic *efx); 1336 void (*sriov_flr)(struct efx_nic *efx, unsigned vf_i); 1337 int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, u8 *mac); 1338 int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan, 1339 u8 qos); 1340 int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i, 1341 bool spoofchk); 1342 int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i, 1343 struct ifla_vf_info *ivi); 1344 int (*sriov_set_vf_link_state)(struct efx_nic *efx, int vf_i, 1345 int link_state); 1346 int (*sriov_get_phys_port_id)(struct efx_nic *efx, 1347 struct netdev_phys_item_id *ppid); 1348 int (*vswitching_probe)(struct efx_nic *efx); 1349 int (*vswitching_restore)(struct efx_nic *efx); 1350 void (*vswitching_remove)(struct efx_nic *efx); 1351 int (*get_mac_address)(struct efx_nic *efx, unsigned char *perm_addr); 1352 int (*set_mac_address)(struct efx_nic *efx); 1353 1354 int revision; 1355 unsigned int txd_ptr_tbl_base; 1356 unsigned int rxd_ptr_tbl_base; 1357 unsigned int buf_tbl_base; 1358 unsigned int evq_ptr_tbl_base; 1359 unsigned int evq_rptr_tbl_base; 1360 u64 max_dma_mask; 1361 unsigned int rx_prefix_size; 1362 unsigned int rx_hash_offset; 1363 unsigned int rx_ts_offset; 1364 unsigned int rx_buffer_padding; 1365 bool can_rx_scatter; 1366 bool always_rx_scatter; 1367 unsigned int max_interrupt_mode; 1368 unsigned int timer_period_max; 1369 netdev_features_t offload_features; 1370 int mcdi_max_ver; 1371 unsigned int max_rx_ip_filters; 1372 u32 hwtstamp_filters; 1373 }; 1374 1375 /************************************************************************** 1376 * 1377 * Prototypes and inline functions 1378 * 1379 *************************************************************************/ 1380 1381 static inline struct efx_channel * 1382 efx_get_channel(struct efx_nic *efx, unsigned index) 1383 { 1384 EFX_BUG_ON_PARANOID(index >= efx->n_channels); 1385 return efx->channel[index]; 1386 } 1387 1388 /* Iterate over all used channels */ 1389 #define efx_for_each_channel(_channel, _efx) \ 1390 for (_channel = (_efx)->channel[0]; \ 1391 _channel; \ 1392 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ 1393 (_efx)->channel[_channel->channel + 1] : NULL) 1394 1395 /* Iterate over all used channels in reverse */ 1396 #define efx_for_each_channel_rev(_channel, _efx) \ 1397 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \ 1398 _channel; \ 1399 _channel = _channel->channel ? \ 1400 (_efx)->channel[_channel->channel - 1] : NULL) 1401 1402 static inline struct efx_tx_queue * 1403 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) 1404 { 1405 EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels || 1406 type >= EFX_TXQ_TYPES); 1407 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type]; 1408 } 1409 1410 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel) 1411 { 1412 return channel->channel - channel->efx->tx_channel_offset < 1413 channel->efx->n_tx_channels; 1414 } 1415 1416 static inline struct efx_tx_queue * 1417 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type) 1418 { 1419 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) || 1420 type >= EFX_TXQ_TYPES); 1421 return &channel->tx_queue[type]; 1422 } 1423 1424 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue) 1425 { 1426 return !(tx_queue->efx->net_dev->num_tc < 2 && 1427 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI); 1428 } 1429 1430 /* Iterate over all TX queues belonging to a channel */ 1431 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ 1432 if (!efx_channel_has_tx_queues(_channel)) \ 1433 ; \ 1434 else \ 1435 for (_tx_queue = (_channel)->tx_queue; \ 1436 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \ 1437 efx_tx_queue_used(_tx_queue); \ 1438 _tx_queue++) 1439 1440 /* Iterate over all possible TX queues belonging to a channel */ 1441 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \ 1442 if (!efx_channel_has_tx_queues(_channel)) \ 1443 ; \ 1444 else \ 1445 for (_tx_queue = (_channel)->tx_queue; \ 1446 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ 1447 _tx_queue++) 1448 1449 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel) 1450 { 1451 return channel->rx_queue.core_index >= 0; 1452 } 1453 1454 static inline struct efx_rx_queue * 1455 efx_channel_get_rx_queue(struct efx_channel *channel) 1456 { 1457 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel)); 1458 return &channel->rx_queue; 1459 } 1460 1461 /* Iterate over all RX queues belonging to a channel */ 1462 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ 1463 if (!efx_channel_has_rx_queue(_channel)) \ 1464 ; \ 1465 else \ 1466 for (_rx_queue = &(_channel)->rx_queue; \ 1467 _rx_queue; \ 1468 _rx_queue = NULL) 1469 1470 static inline struct efx_channel * 1471 efx_rx_queue_channel(struct efx_rx_queue *rx_queue) 1472 { 1473 return container_of(rx_queue, struct efx_channel, rx_queue); 1474 } 1475 1476 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) 1477 { 1478 return efx_rx_queue_channel(rx_queue)->channel; 1479 } 1480 1481 /* Returns a pointer to the specified receive buffer in the RX 1482 * descriptor queue. 1483 */ 1484 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, 1485 unsigned int index) 1486 { 1487 return &rx_queue->buffer[index]; 1488 } 1489 1490 /** 1491 * EFX_MAX_FRAME_LEN - calculate maximum frame length 1492 * 1493 * This calculates the maximum frame length that will be used for a 1494 * given MTU. The frame length will be equal to the MTU plus a 1495 * constant amount of header space and padding. This is the quantity 1496 * that the net driver will program into the MAC as the maximum frame 1497 * length. 1498 * 1499 * The 10G MAC requires 8-byte alignment on the frame 1500 * length, so we round up to the nearest 8. 1501 * 1502 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an 1503 * XGMII cycle). If the frame length reaches the maximum value in the 1504 * same cycle, the XMAC can miss the IPG altogether. We work around 1505 * this by adding a further 16 bytes. 1506 */ 1507 #define EFX_FRAME_PAD 16 1508 #define EFX_MAX_FRAME_LEN(mtu) \ 1509 (ALIGN(((mtu) + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN + EFX_FRAME_PAD), 8)) 1510 1511 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb) 1512 { 1513 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP; 1514 } 1515 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb) 1516 { 1517 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1518 } 1519 1520 #endif /* EFX_NET_DRIVER_H */ 1521