1 /**************************************************************************** 2 * Driver for Solarflare Solarstorm network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2011 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 /* Common definitions for all Efx net driver code */ 12 13 #ifndef EFX_NET_DRIVER_H 14 #define EFX_NET_DRIVER_H 15 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/ethtool.h> 19 #include <linux/if_vlan.h> 20 #include <linux/timer.h> 21 #include <linux/mdio.h> 22 #include <linux/list.h> 23 #include <linux/pci.h> 24 #include <linux/device.h> 25 #include <linux/highmem.h> 26 #include <linux/workqueue.h> 27 #include <linux/mutex.h> 28 #include <linux/vmalloc.h> 29 #include <linux/i2c.h> 30 31 #include "enum.h" 32 #include "bitfield.h" 33 34 /************************************************************************** 35 * 36 * Build definitions 37 * 38 **************************************************************************/ 39 40 #define EFX_DRIVER_VERSION "3.1" 41 42 #ifdef DEBUG 43 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) 44 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) 45 #else 46 #define EFX_BUG_ON_PARANOID(x) do {} while (0) 47 #define EFX_WARN_ON_PARANOID(x) do {} while (0) 48 #endif 49 50 /************************************************************************** 51 * 52 * Efx data structures 53 * 54 **************************************************************************/ 55 56 #define EFX_MAX_CHANNELS 32U 57 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS 58 #define EFX_EXTRA_CHANNEL_IOV 0 59 #define EFX_MAX_EXTRA_CHANNELS 1U 60 61 /* Checksum generation is a per-queue option in hardware, so each 62 * queue visible to the networking core is backed by two hardware TX 63 * queues. */ 64 #define EFX_MAX_TX_TC 2 65 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS) 66 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */ 67 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */ 68 #define EFX_TXQ_TYPES 4 69 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS) 70 71 /** 72 * struct efx_special_buffer - An Efx special buffer 73 * @addr: CPU base address of the buffer 74 * @dma_addr: DMA base address of the buffer 75 * @len: Buffer length, in bytes 76 * @index: Buffer index within controller;s buffer table 77 * @entries: Number of buffer table entries 78 * 79 * Special buffers are used for the event queues and the TX and RX 80 * descriptor queues for each channel. They are *not* used for the 81 * actual transmit and receive buffers. 82 */ 83 struct efx_special_buffer { 84 void *addr; 85 dma_addr_t dma_addr; 86 unsigned int len; 87 unsigned int index; 88 unsigned int entries; 89 }; 90 91 /** 92 * struct efx_tx_buffer - An Efx TX buffer 93 * @skb: The associated socket buffer. 94 * Set only on the final fragment of a packet; %NULL for all other 95 * fragments. When this fragment completes, then we can free this 96 * skb. 97 * @tsoh: The associated TSO header structure, or %NULL if this 98 * buffer is not a TSO header. 99 * @dma_addr: DMA address of the fragment. 100 * @len: Length of this fragment. 101 * This field is zero when the queue slot is empty. 102 * @continuation: True if this fragment is not the end of a packet. 103 * @unmap_single: True if pci_unmap_single should be used. 104 * @unmap_len: Length of this fragment to unmap 105 */ 106 struct efx_tx_buffer { 107 const struct sk_buff *skb; 108 struct efx_tso_header *tsoh; 109 dma_addr_t dma_addr; 110 unsigned short len; 111 bool continuation; 112 bool unmap_single; 113 unsigned short unmap_len; 114 }; 115 116 /** 117 * struct efx_tx_queue - An Efx TX queue 118 * 119 * This is a ring buffer of TX fragments. 120 * Since the TX completion path always executes on the same 121 * CPU and the xmit path can operate on different CPUs, 122 * performance is increased by ensuring that the completion 123 * path and the xmit path operate on different cache lines. 124 * This is particularly important if the xmit path is always 125 * executing on one CPU which is different from the completion 126 * path. There is also a cache line for members which are 127 * read but not written on the fast path. 128 * 129 * @efx: The associated Efx NIC 130 * @queue: DMA queue number 131 * @channel: The associated channel 132 * @core_txq: The networking core TX queue structure 133 * @buffer: The software buffer ring 134 * @txd: The hardware descriptor ring 135 * @ptr_mask: The size of the ring minus 1. 136 * @initialised: Has hardware queue been initialised? 137 * @read_count: Current read pointer. 138 * This is the number of buffers that have been removed from both rings. 139 * @old_write_count: The value of @write_count when last checked. 140 * This is here for performance reasons. The xmit path will 141 * only get the up-to-date value of @write_count if this 142 * variable indicates that the queue is empty. This is to 143 * avoid cache-line ping-pong between the xmit path and the 144 * completion path. 145 * @insert_count: Current insert pointer 146 * This is the number of buffers that have been added to the 147 * software ring. 148 * @write_count: Current write pointer 149 * This is the number of buffers that have been added to the 150 * hardware ring. 151 * @old_read_count: The value of read_count when last checked. 152 * This is here for performance reasons. The xmit path will 153 * only get the up-to-date value of read_count if this 154 * variable indicates that the queue is full. This is to 155 * avoid cache-line ping-pong between the xmit path and the 156 * completion path. 157 * @tso_headers_free: A list of TSO headers allocated for this TX queue 158 * that are not in use, and so available for new TSO sends. The list 159 * is protected by the TX queue lock. 160 * @tso_bursts: Number of times TSO xmit invoked by kernel 161 * @tso_long_headers: Number of packets with headers too long for standard 162 * blocks 163 * @tso_packets: Number of packets via the TSO xmit path 164 * @pushes: Number of times the TX push feature has been used 165 * @empty_read_count: If the completion path has seen the queue as empty 166 * and the transmission path has not yet checked this, the value of 167 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0. 168 */ 169 struct efx_tx_queue { 170 /* Members which don't change on the fast path */ 171 struct efx_nic *efx ____cacheline_aligned_in_smp; 172 unsigned queue; 173 struct efx_channel *channel; 174 struct netdev_queue *core_txq; 175 struct efx_tx_buffer *buffer; 176 struct efx_special_buffer txd; 177 unsigned int ptr_mask; 178 bool initialised; 179 180 /* Members used mainly on the completion path */ 181 unsigned int read_count ____cacheline_aligned_in_smp; 182 unsigned int old_write_count; 183 184 /* Members used only on the xmit path */ 185 unsigned int insert_count ____cacheline_aligned_in_smp; 186 unsigned int write_count; 187 unsigned int old_read_count; 188 struct efx_tso_header *tso_headers_free; 189 unsigned int tso_bursts; 190 unsigned int tso_long_headers; 191 unsigned int tso_packets; 192 unsigned int pushes; 193 194 /* Members shared between paths and sometimes updated */ 195 unsigned int empty_read_count ____cacheline_aligned_in_smp; 196 #define EFX_EMPTY_COUNT_VALID 0x80000000 197 }; 198 199 /** 200 * struct efx_rx_buffer - An Efx RX data buffer 201 * @dma_addr: DMA base address of the buffer 202 * @skb: The associated socket buffer. Valid iff !(@flags & %EFX_RX_BUF_PAGE). 203 * Will be %NULL if the buffer slot is currently free. 204 * @page: The associated page buffer. Valif iff @flags & %EFX_RX_BUF_PAGE. 205 * Will be %NULL if the buffer slot is currently free. 206 * @len: Buffer length, in bytes. 207 * @flags: Flags for buffer and packet state. 208 */ 209 struct efx_rx_buffer { 210 dma_addr_t dma_addr; 211 union { 212 struct sk_buff *skb; 213 struct page *page; 214 } u; 215 unsigned int len; 216 u16 flags; 217 }; 218 #define EFX_RX_BUF_PAGE 0x0001 219 #define EFX_RX_PKT_CSUMMED 0x0002 220 #define EFX_RX_PKT_DISCARD 0x0004 221 222 /** 223 * struct efx_rx_page_state - Page-based rx buffer state 224 * 225 * Inserted at the start of every page allocated for receive buffers. 226 * Used to facilitate sharing dma mappings between recycled rx buffers 227 * and those passed up to the kernel. 228 * 229 * @refcnt: Number of struct efx_rx_buffer's referencing this page. 230 * When refcnt falls to zero, the page is unmapped for dma 231 * @dma_addr: The dma address of this page. 232 */ 233 struct efx_rx_page_state { 234 unsigned refcnt; 235 dma_addr_t dma_addr; 236 237 unsigned int __pad[0] ____cacheline_aligned; 238 }; 239 240 /** 241 * struct efx_rx_queue - An Efx RX queue 242 * @efx: The associated Efx NIC 243 * @buffer: The software buffer ring 244 * @rxd: The hardware descriptor ring 245 * @ptr_mask: The size of the ring minus 1. 246 * @enabled: Receive queue enabled indicator. 247 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as 248 * @rxq_flush_pending. 249 * @added_count: Number of buffers added to the receive queue. 250 * @notified_count: Number of buffers given to NIC (<= @added_count). 251 * @removed_count: Number of buffers removed from the receive queue. 252 * @max_fill: RX descriptor maximum fill level (<= ring size) 253 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill 254 * (<= @max_fill) 255 * @min_fill: RX descriptor minimum non-zero fill level. 256 * This records the minimum fill level observed when a ring 257 * refill was triggered. 258 * @alloc_page_count: RX allocation strategy counter. 259 * @alloc_skb_count: RX allocation strategy counter. 260 * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). 261 */ 262 struct efx_rx_queue { 263 struct efx_nic *efx; 264 struct efx_rx_buffer *buffer; 265 struct efx_special_buffer rxd; 266 unsigned int ptr_mask; 267 bool enabled; 268 bool flush_pending; 269 270 int added_count; 271 int notified_count; 272 int removed_count; 273 unsigned int max_fill; 274 unsigned int fast_fill_trigger; 275 unsigned int min_fill; 276 unsigned int min_overfill; 277 unsigned int alloc_page_count; 278 unsigned int alloc_skb_count; 279 struct timer_list slow_fill; 280 unsigned int slow_fill_count; 281 }; 282 283 /** 284 * struct efx_buffer - An Efx general-purpose buffer 285 * @addr: host base address of the buffer 286 * @dma_addr: DMA base address of the buffer 287 * @len: Buffer length, in bytes 288 * 289 * The NIC uses these buffers for its interrupt status registers and 290 * MAC stats dumps. 291 */ 292 struct efx_buffer { 293 void *addr; 294 dma_addr_t dma_addr; 295 unsigned int len; 296 }; 297 298 299 enum efx_rx_alloc_method { 300 RX_ALLOC_METHOD_AUTO = 0, 301 RX_ALLOC_METHOD_SKB = 1, 302 RX_ALLOC_METHOD_PAGE = 2, 303 }; 304 305 /** 306 * struct efx_channel - An Efx channel 307 * 308 * A channel comprises an event queue, at least one TX queue, at least 309 * one RX queue, and an associated tasklet for processing the event 310 * queue. 311 * 312 * @efx: Associated Efx NIC 313 * @channel: Channel instance number 314 * @type: Channel type definition 315 * @enabled: Channel enabled indicator 316 * @irq: IRQ number (MSI and MSI-X only) 317 * @irq_moderation: IRQ moderation value (in hardware ticks) 318 * @napi_dev: Net device used with NAPI 319 * @napi_str: NAPI control structure 320 * @work_pending: Is work pending via NAPI? 321 * @eventq: Event queue buffer 322 * @eventq_mask: Event queue pointer mask 323 * @eventq_read_ptr: Event queue read pointer 324 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel 325 * @irq_count: Number of IRQs since last adaptive moderation decision 326 * @irq_mod_score: IRQ moderation score 327 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors 328 * and diagnostic counters 329 * @rx_alloc_push_pages: RX allocation method currently in use for pushing 330 * descriptors 331 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors 332 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors 333 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors 334 * @n_rx_mcast_mismatch: Count of unmatched multicast frames 335 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors 336 * @n_rx_overlength: Count of RX_OVERLENGTH errors 337 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun 338 * @rx_queue: RX queue for this channel 339 * @tx_queue: TX queues for this channel 340 */ 341 struct efx_channel { 342 struct efx_nic *efx; 343 int channel; 344 const struct efx_channel_type *type; 345 bool enabled; 346 int irq; 347 unsigned int irq_moderation; 348 struct net_device *napi_dev; 349 struct napi_struct napi_str; 350 bool work_pending; 351 struct efx_special_buffer eventq; 352 unsigned int eventq_mask; 353 unsigned int eventq_read_ptr; 354 int event_test_cpu; 355 356 unsigned int irq_count; 357 unsigned int irq_mod_score; 358 #ifdef CONFIG_RFS_ACCEL 359 unsigned int rfs_filters_added; 360 #endif 361 362 int rx_alloc_level; 363 int rx_alloc_push_pages; 364 365 unsigned n_rx_tobe_disc; 366 unsigned n_rx_ip_hdr_chksum_err; 367 unsigned n_rx_tcp_udp_chksum_err; 368 unsigned n_rx_mcast_mismatch; 369 unsigned n_rx_frm_trunc; 370 unsigned n_rx_overlength; 371 unsigned n_skbuff_leaks; 372 373 /* Used to pipeline received packets in order to optimise memory 374 * access with prefetches. 375 */ 376 struct efx_rx_buffer *rx_pkt; 377 378 struct efx_rx_queue rx_queue; 379 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES]; 380 }; 381 382 /** 383 * struct efx_channel_type - distinguishes traffic and extra channels 384 * @handle_no_channel: Handle failure to allocate an extra channel 385 * @pre_probe: Set up extra state prior to initialisation 386 * @post_remove: Tear down extra state after finalisation, if allocated. 387 * May be called on channels that have not been probed. 388 * @get_name: Generate the channel's name (used for its IRQ handler) 389 * @copy: Copy the channel state prior to reallocation. May be %NULL if 390 * reallocation is not supported. 391 * @keep_eventq: Flag for whether event queue should be kept initialised 392 * while the device is stopped 393 */ 394 struct efx_channel_type { 395 void (*handle_no_channel)(struct efx_nic *); 396 int (*pre_probe)(struct efx_channel *); 397 void (*get_name)(struct efx_channel *, char *buf, size_t len); 398 struct efx_channel *(*copy)(const struct efx_channel *); 399 bool keep_eventq; 400 }; 401 402 enum efx_led_mode { 403 EFX_LED_OFF = 0, 404 EFX_LED_ON = 1, 405 EFX_LED_DEFAULT = 2 406 }; 407 408 #define STRING_TABLE_LOOKUP(val, member) \ 409 ((val) < member ## _max) ? member ## _names[val] : "(invalid)" 410 411 extern const char *const efx_loopback_mode_names[]; 412 extern const unsigned int efx_loopback_mode_max; 413 #define LOOPBACK_MODE(efx) \ 414 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) 415 416 extern const char *const efx_reset_type_names[]; 417 extern const unsigned int efx_reset_type_max; 418 #define RESET_TYPE(type) \ 419 STRING_TABLE_LOOKUP(type, efx_reset_type) 420 421 enum efx_int_mode { 422 /* Be careful if altering to correct macro below */ 423 EFX_INT_MODE_MSIX = 0, 424 EFX_INT_MODE_MSI = 1, 425 EFX_INT_MODE_LEGACY = 2, 426 EFX_INT_MODE_MAX /* Insert any new items before this */ 427 }; 428 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) 429 430 enum nic_state { 431 STATE_INIT = 0, 432 STATE_RUNNING = 1, 433 STATE_FINI = 2, 434 STATE_DISABLED = 3, 435 STATE_MAX, 436 }; 437 438 /* 439 * Alignment of page-allocated RX buffers 440 * 441 * Controls the number of bytes inserted at the start of an RX buffer. 442 * This is the equivalent of NET_IP_ALIGN [which controls the alignment 443 * of the skb->head for hardware DMA]. 444 */ 445 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 446 #define EFX_PAGE_IP_ALIGN 0 447 #else 448 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN 449 #endif 450 451 /* 452 * Alignment of the skb->head which wraps a page-allocated RX buffer 453 * 454 * The skb allocated to wrap an rx_buffer can have this alignment. Since 455 * the data is memcpy'd from the rx_buf, it does not need to be equal to 456 * EFX_PAGE_IP_ALIGN. 457 */ 458 #define EFX_PAGE_SKB_ALIGN 2 459 460 /* Forward declaration */ 461 struct efx_nic; 462 463 /* Pseudo bit-mask flow control field */ 464 #define EFX_FC_RX FLOW_CTRL_RX 465 #define EFX_FC_TX FLOW_CTRL_TX 466 #define EFX_FC_AUTO 4 467 468 /** 469 * struct efx_link_state - Current state of the link 470 * @up: Link is up 471 * @fd: Link is full-duplex 472 * @fc: Actual flow control flags 473 * @speed: Link speed (Mbps) 474 */ 475 struct efx_link_state { 476 bool up; 477 bool fd; 478 u8 fc; 479 unsigned int speed; 480 }; 481 482 static inline bool efx_link_state_equal(const struct efx_link_state *left, 483 const struct efx_link_state *right) 484 { 485 return left->up == right->up && left->fd == right->fd && 486 left->fc == right->fc && left->speed == right->speed; 487 } 488 489 /** 490 * struct efx_phy_operations - Efx PHY operations table 491 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, 492 * efx->loopback_modes. 493 * @init: Initialise PHY 494 * @fini: Shut down PHY 495 * @reconfigure: Reconfigure PHY (e.g. for new link parameters) 496 * @poll: Update @link_state and report whether it changed. 497 * Serialised by the mac_lock. 498 * @get_settings: Get ethtool settings. Serialised by the mac_lock. 499 * @set_settings: Set ethtool settings. Serialised by the mac_lock. 500 * @set_npage_adv: Set abilities advertised in (Extended) Next Page 501 * (only needed where AN bit is set in mmds) 502 * @test_alive: Test that PHY is 'alive' (online) 503 * @test_name: Get the name of a PHY-specific test/result 504 * @run_tests: Run tests and record results as appropriate (offline). 505 * Flags are the ethtool tests flags. 506 */ 507 struct efx_phy_operations { 508 int (*probe) (struct efx_nic *efx); 509 int (*init) (struct efx_nic *efx); 510 void (*fini) (struct efx_nic *efx); 511 void (*remove) (struct efx_nic *efx); 512 int (*reconfigure) (struct efx_nic *efx); 513 bool (*poll) (struct efx_nic *efx); 514 void (*get_settings) (struct efx_nic *efx, 515 struct ethtool_cmd *ecmd); 516 int (*set_settings) (struct efx_nic *efx, 517 struct ethtool_cmd *ecmd); 518 void (*set_npage_adv) (struct efx_nic *efx, u32); 519 int (*test_alive) (struct efx_nic *efx); 520 const char *(*test_name) (struct efx_nic *efx, unsigned int index); 521 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); 522 int (*get_module_eeprom) (struct efx_nic *efx, 523 struct ethtool_eeprom *ee, 524 u8 *data); 525 int (*get_module_info) (struct efx_nic *efx, 526 struct ethtool_modinfo *modinfo); 527 }; 528 529 /** 530 * @enum efx_phy_mode - PHY operating mode flags 531 * @PHY_MODE_NORMAL: on and should pass traffic 532 * @PHY_MODE_TX_DISABLED: on with TX disabled 533 * @PHY_MODE_LOW_POWER: set to low power through MDIO 534 * @PHY_MODE_OFF: switched off through external control 535 * @PHY_MODE_SPECIAL: on but will not pass traffic 536 */ 537 enum efx_phy_mode { 538 PHY_MODE_NORMAL = 0, 539 PHY_MODE_TX_DISABLED = 1, 540 PHY_MODE_LOW_POWER = 2, 541 PHY_MODE_OFF = 4, 542 PHY_MODE_SPECIAL = 8, 543 }; 544 545 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) 546 { 547 return !!(mode & ~PHY_MODE_TX_DISABLED); 548 } 549 550 /* 551 * Efx extended statistics 552 * 553 * Not all statistics are provided by all supported MACs. The purpose 554 * is this structure is to contain the raw statistics provided by each 555 * MAC. 556 */ 557 struct efx_mac_stats { 558 u64 tx_bytes; 559 u64 tx_good_bytes; 560 u64 tx_bad_bytes; 561 u64 tx_packets; 562 u64 tx_bad; 563 u64 tx_pause; 564 u64 tx_control; 565 u64 tx_unicast; 566 u64 tx_multicast; 567 u64 tx_broadcast; 568 u64 tx_lt64; 569 u64 tx_64; 570 u64 tx_65_to_127; 571 u64 tx_128_to_255; 572 u64 tx_256_to_511; 573 u64 tx_512_to_1023; 574 u64 tx_1024_to_15xx; 575 u64 tx_15xx_to_jumbo; 576 u64 tx_gtjumbo; 577 u64 tx_collision; 578 u64 tx_single_collision; 579 u64 tx_multiple_collision; 580 u64 tx_excessive_collision; 581 u64 tx_deferred; 582 u64 tx_late_collision; 583 u64 tx_excessive_deferred; 584 u64 tx_non_tcpudp; 585 u64 tx_mac_src_error; 586 u64 tx_ip_src_error; 587 u64 rx_bytes; 588 u64 rx_good_bytes; 589 u64 rx_bad_bytes; 590 u64 rx_packets; 591 u64 rx_good; 592 u64 rx_bad; 593 u64 rx_pause; 594 u64 rx_control; 595 u64 rx_unicast; 596 u64 rx_multicast; 597 u64 rx_broadcast; 598 u64 rx_lt64; 599 u64 rx_64; 600 u64 rx_65_to_127; 601 u64 rx_128_to_255; 602 u64 rx_256_to_511; 603 u64 rx_512_to_1023; 604 u64 rx_1024_to_15xx; 605 u64 rx_15xx_to_jumbo; 606 u64 rx_gtjumbo; 607 u64 rx_bad_lt64; 608 u64 rx_bad_64_to_15xx; 609 u64 rx_bad_15xx_to_jumbo; 610 u64 rx_bad_gtjumbo; 611 u64 rx_overflow; 612 u64 rx_missed; 613 u64 rx_false_carrier; 614 u64 rx_symbol_error; 615 u64 rx_align_error; 616 u64 rx_length_error; 617 u64 rx_internal_error; 618 u64 rx_good_lt64; 619 }; 620 621 /* Number of bits used in a multicast filter hash address */ 622 #define EFX_MCAST_HASH_BITS 8 623 624 /* Number of (single-bit) entries in a multicast filter hash */ 625 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) 626 627 /* An Efx multicast filter hash */ 628 union efx_multicast_hash { 629 u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; 630 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; 631 }; 632 633 struct efx_filter_state; 634 struct efx_vf; 635 struct vfdi_status; 636 637 /** 638 * struct efx_nic - an Efx NIC 639 * @name: Device name (net device name or bus id before net device registered) 640 * @pci_dev: The PCI device 641 * @type: Controller type attributes 642 * @legacy_irq: IRQ number 643 * @legacy_irq_enabled: Are IRQs enabled on NIC (INT_EN_KER register)? 644 * @workqueue: Workqueue for port reconfigures and the HW monitor. 645 * Work items do not hold and must not acquire RTNL. 646 * @workqueue_name: Name of workqueue 647 * @reset_work: Scheduled reset workitem 648 * @membase_phys: Memory BAR value as physical address 649 * @membase: Memory BAR value 650 * @interrupt_mode: Interrupt mode 651 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds 652 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues 653 * @irq_rx_moderation: IRQ moderation time for RX event queues 654 * @msg_enable: Log message enable flags 655 * @state: Device state flag. Serialised by the rtnl_lock. 656 * @reset_pending: Bitmask for pending resets 657 * @tx_queue: TX DMA queues 658 * @rx_queue: RX DMA queues 659 * @channel: Channels 660 * @channel_name: Names for channels and their IRQs 661 * @extra_channel_types: Types of extra (non-traffic) channels that 662 * should be allocated for this NIC 663 * @rxq_entries: Size of receive queues requested by user. 664 * @txq_entries: Size of transmit queues requested by user. 665 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches 666 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches 667 * @sram_lim_qw: Qword address limit of SRAM 668 * @next_buffer_table: First available buffer table id 669 * @n_channels: Number of channels in use 670 * @n_rx_channels: Number of channels used for RX (= number of RX queues) 671 * @n_tx_channels: Number of channels used for TX 672 * @rx_buffer_len: RX buffer length 673 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer 674 * @rx_hash_key: Toeplitz hash key for RSS 675 * @rx_indir_table: Indirection table for RSS 676 * @int_error_count: Number of internal errors seen recently 677 * @int_error_expire: Time at which error count will be expired 678 * @irq_status: Interrupt status buffer 679 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 680 * @irq_level: IRQ level/index for IRQs not triggered by an event queue 681 * @selftest_work: Work item for asynchronous self-test 682 * @mtd_list: List of MTDs attached to the NIC 683 * @nic_data: Hardware dependent state 684 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, 685 * efx_monitor() and efx_reconfigure_port() 686 * @port_enabled: Port enabled indicator. 687 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and 688 * efx_mac_work() with kernel interfaces. Safe to read under any 689 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must 690 * be held to modify it. 691 * @port_initialized: Port initialized? 692 * @net_dev: Operating system network device. Consider holding the rtnl lock 693 * @stats_buffer: DMA buffer for statistics 694 * @phy_type: PHY type 695 * @phy_op: PHY interface 696 * @phy_data: PHY private data (including PHY-specific stats) 697 * @mdio: PHY MDIO interface 698 * @mdio_bus: PHY MDIO bus ID (only used by Siena) 699 * @phy_mode: PHY operating mode. Serialised by @mac_lock. 700 * @link_advertising: Autonegotiation advertising flags 701 * @link_state: Current state of the link 702 * @n_link_state_changes: Number of times the link has changed state 703 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock. 704 * @multicast_hash: Multicast hash table 705 * @wanted_fc: Wanted flow control flags 706 * @fc_disable: When non-zero flow control is disabled. Typically used to 707 * ensure that network back pressure doesn't delay dma queue flushes. 708 * Serialised by the rtnl lock. 709 * @mac_work: Work item for changing MAC promiscuity and multicast hash 710 * @loopback_mode: Loopback status 711 * @loopback_modes: Supported loopback mode bitmask 712 * @loopback_selftest: Offline self-test private state 713 * @drain_pending: Count of RX and TX queues that haven't been flushed and drained. 714 * @rxq_flush_pending: Count of number of receive queues that need to be flushed. 715 * Decremented when the efx_flush_rx_queue() is called. 716 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet 717 * completed (either success or failure). Not used when MCDI is used to 718 * flush receive queues. 719 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions. 720 * @vf: Array of &struct efx_vf objects. 721 * @vf_count: Number of VFs intended to be enabled. 722 * @vf_init_count: Number of VFs that have been fully initialised. 723 * @vi_scale: log2 number of vnics per VF. 724 * @vf_buftbl_base: The zeroth buffer table index used to back VF queues. 725 * @vfdi_status: Common VFDI status page to be dmad to VF address space. 726 * @local_addr_list: List of local addresses. Protected by %local_lock. 727 * @local_page_list: List of DMA addressable pages used to broadcast 728 * %local_addr_list. Protected by %local_lock. 729 * @local_lock: Mutex protecting %local_addr_list and %local_page_list. 730 * @peer_work: Work item to broadcast peer addresses to VMs. 731 * @monitor_work: Hardware monitor workitem 732 * @biu_lock: BIU (bus interface unit) lock 733 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This 734 * field is used by efx_test_interrupts() to verify that an 735 * interrupt has occurred. 736 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count 737 * @mac_stats: MAC statistics. These include all statistics the MACs 738 * can provide. Generic code converts these into a standard 739 * &struct net_device_stats. 740 * @stats_lock: Statistics update lock. Serialises statistics fetches 741 * and access to @mac_stats. 742 * 743 * This is stored in the private area of the &struct net_device. 744 */ 745 struct efx_nic { 746 /* The following fields should be written very rarely */ 747 748 char name[IFNAMSIZ]; 749 struct pci_dev *pci_dev; 750 const struct efx_nic_type *type; 751 int legacy_irq; 752 bool legacy_irq_enabled; 753 struct workqueue_struct *workqueue; 754 char workqueue_name[16]; 755 struct work_struct reset_work; 756 resource_size_t membase_phys; 757 void __iomem *membase; 758 759 enum efx_int_mode interrupt_mode; 760 unsigned int timer_quantum_ns; 761 bool irq_rx_adaptive; 762 unsigned int irq_rx_moderation; 763 u32 msg_enable; 764 765 enum nic_state state; 766 unsigned long reset_pending; 767 768 struct efx_channel *channel[EFX_MAX_CHANNELS]; 769 char channel_name[EFX_MAX_CHANNELS][IFNAMSIZ + 6]; 770 const struct efx_channel_type * 771 extra_channel_type[EFX_MAX_EXTRA_CHANNELS]; 772 773 unsigned rxq_entries; 774 unsigned txq_entries; 775 unsigned tx_dc_base; 776 unsigned rx_dc_base; 777 unsigned sram_lim_qw; 778 unsigned next_buffer_table; 779 unsigned n_channels; 780 unsigned n_rx_channels; 781 unsigned rss_spread; 782 unsigned tx_channel_offset; 783 unsigned n_tx_channels; 784 unsigned int rx_buffer_len; 785 unsigned int rx_buffer_order; 786 u8 rx_hash_key[40]; 787 u32 rx_indir_table[128]; 788 789 unsigned int_error_count; 790 unsigned long int_error_expire; 791 792 struct efx_buffer irq_status; 793 unsigned irq_zero_count; 794 unsigned irq_level; 795 struct delayed_work selftest_work; 796 797 #ifdef CONFIG_SFC_MTD 798 struct list_head mtd_list; 799 #endif 800 801 void *nic_data; 802 803 struct mutex mac_lock; 804 struct work_struct mac_work; 805 bool port_enabled; 806 807 bool port_initialized; 808 struct net_device *net_dev; 809 810 struct efx_buffer stats_buffer; 811 812 unsigned int phy_type; 813 const struct efx_phy_operations *phy_op; 814 void *phy_data; 815 struct mdio_if_info mdio; 816 unsigned int mdio_bus; 817 enum efx_phy_mode phy_mode; 818 819 u32 link_advertising; 820 struct efx_link_state link_state; 821 unsigned int n_link_state_changes; 822 823 bool promiscuous; 824 union efx_multicast_hash multicast_hash; 825 u8 wanted_fc; 826 unsigned fc_disable; 827 828 atomic_t rx_reset; 829 enum efx_loopback_mode loopback_mode; 830 u64 loopback_modes; 831 832 void *loopback_selftest; 833 834 struct efx_filter_state *filter_state; 835 836 atomic_t drain_pending; 837 atomic_t rxq_flush_pending; 838 atomic_t rxq_flush_outstanding; 839 wait_queue_head_t flush_wq; 840 841 #ifdef CONFIG_SFC_SRIOV 842 struct efx_channel *vfdi_channel; 843 struct efx_vf *vf; 844 unsigned vf_count; 845 unsigned vf_init_count; 846 unsigned vi_scale; 847 unsigned vf_buftbl_base; 848 struct efx_buffer vfdi_status; 849 struct list_head local_addr_list; 850 struct list_head local_page_list; 851 struct mutex local_lock; 852 struct work_struct peer_work; 853 #endif 854 855 /* The following fields may be written more often */ 856 857 struct delayed_work monitor_work ____cacheline_aligned_in_smp; 858 spinlock_t biu_lock; 859 int last_irq_cpu; 860 unsigned n_rx_nodesc_drop_cnt; 861 struct efx_mac_stats mac_stats; 862 spinlock_t stats_lock; 863 }; 864 865 static inline int efx_dev_registered(struct efx_nic *efx) 866 { 867 return efx->net_dev->reg_state == NETREG_REGISTERED; 868 } 869 870 static inline unsigned int efx_port_num(struct efx_nic *efx) 871 { 872 return efx->net_dev->dev_id; 873 } 874 875 /** 876 * struct efx_nic_type - Efx device type definition 877 * @probe: Probe the controller 878 * @remove: Free resources allocated by probe() 879 * @init: Initialise the controller 880 * @dimension_resources: Dimension controller resources (buffer table, 881 * and VIs once the available interrupt resources are clear) 882 * @fini: Shut down the controller 883 * @monitor: Periodic function for polling link state and hardware monitor 884 * @map_reset_reason: Map ethtool reset reason to a reset method 885 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible 886 * @reset: Reset the controller hardware and possibly the PHY. This will 887 * be called while the controller is uninitialised. 888 * @probe_port: Probe the MAC and PHY 889 * @remove_port: Free resources allocated by probe_port() 890 * @handle_global_event: Handle a "global" event (may be %NULL) 891 * @prepare_flush: Prepare the hardware for flushing the DMA queues 892 * @update_stats: Update statistics not provided by event handling 893 * @start_stats: Start the regular fetching of statistics 894 * @stop_stats: Stop the regular fetching of statistics 895 * @set_id_led: Set state of identifying LED or revert to automatic function 896 * @push_irq_moderation: Apply interrupt moderation value 897 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY 898 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings 899 * to the hardware. Serialised by the mac_lock. 900 * @check_mac_fault: Check MAC fault state. True if fault present. 901 * @get_wol: Get WoL configuration from driver state 902 * @set_wol: Push WoL configuration to the NIC 903 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) 904 * @test_registers: Test read/write functionality of control registers 905 * @test_nvram: Test validity of NVRAM contents 906 * @revision: Hardware architecture revision 907 * @mem_map_size: Memory BAR mapped size 908 * @txd_ptr_tbl_base: TX descriptor ring base address 909 * @rxd_ptr_tbl_base: RX descriptor ring base address 910 * @buf_tbl_base: Buffer table base address 911 * @evq_ptr_tbl_base: Event queue pointer table base address 912 * @evq_rptr_tbl_base: Event queue read-pointer table base address 913 * @max_dma_mask: Maximum possible DMA mask 914 * @rx_buffer_hash_size: Size of hash at start of RX buffer 915 * @rx_buffer_padding: Size of padding at end of RX buffer 916 * @max_interrupt_mode: Highest capability interrupt mode supported 917 * from &enum efx_init_mode. 918 * @phys_addr_channels: Number of channels with physically addressed 919 * descriptors 920 * @timer_period_max: Maximum period of interrupt timer (in ticks) 921 * @offload_features: net_device feature flags for protocol offload 922 * features implemented in hardware 923 */ 924 struct efx_nic_type { 925 int (*probe)(struct efx_nic *efx); 926 void (*remove)(struct efx_nic *efx); 927 int (*init)(struct efx_nic *efx); 928 void (*dimension_resources)(struct efx_nic *efx); 929 void (*fini)(struct efx_nic *efx); 930 void (*monitor)(struct efx_nic *efx); 931 enum reset_type (*map_reset_reason)(enum reset_type reason); 932 int (*map_reset_flags)(u32 *flags); 933 int (*reset)(struct efx_nic *efx, enum reset_type method); 934 int (*probe_port)(struct efx_nic *efx); 935 void (*remove_port)(struct efx_nic *efx); 936 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *); 937 void (*prepare_flush)(struct efx_nic *efx); 938 void (*update_stats)(struct efx_nic *efx); 939 void (*start_stats)(struct efx_nic *efx); 940 void (*stop_stats)(struct efx_nic *efx); 941 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); 942 void (*push_irq_moderation)(struct efx_channel *channel); 943 int (*reconfigure_port)(struct efx_nic *efx); 944 int (*reconfigure_mac)(struct efx_nic *efx); 945 bool (*check_mac_fault)(struct efx_nic *efx); 946 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); 947 int (*set_wol)(struct efx_nic *efx, u32 type); 948 void (*resume_wol)(struct efx_nic *efx); 949 int (*test_registers)(struct efx_nic *efx); 950 int (*test_nvram)(struct efx_nic *efx); 951 952 int revision; 953 unsigned int mem_map_size; 954 unsigned int txd_ptr_tbl_base; 955 unsigned int rxd_ptr_tbl_base; 956 unsigned int buf_tbl_base; 957 unsigned int evq_ptr_tbl_base; 958 unsigned int evq_rptr_tbl_base; 959 u64 max_dma_mask; 960 unsigned int rx_buffer_hash_size; 961 unsigned int rx_buffer_padding; 962 unsigned int max_interrupt_mode; 963 unsigned int phys_addr_channels; 964 unsigned int timer_period_max; 965 netdev_features_t offload_features; 966 }; 967 968 /************************************************************************** 969 * 970 * Prototypes and inline functions 971 * 972 *************************************************************************/ 973 974 static inline struct efx_channel * 975 efx_get_channel(struct efx_nic *efx, unsigned index) 976 { 977 EFX_BUG_ON_PARANOID(index >= efx->n_channels); 978 return efx->channel[index]; 979 } 980 981 /* Iterate over all used channels */ 982 #define efx_for_each_channel(_channel, _efx) \ 983 for (_channel = (_efx)->channel[0]; \ 984 _channel; \ 985 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ 986 (_efx)->channel[_channel->channel + 1] : NULL) 987 988 /* Iterate over all used channels in reverse */ 989 #define efx_for_each_channel_rev(_channel, _efx) \ 990 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \ 991 _channel; \ 992 _channel = _channel->channel ? \ 993 (_efx)->channel[_channel->channel - 1] : NULL) 994 995 static inline struct efx_tx_queue * 996 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) 997 { 998 EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels || 999 type >= EFX_TXQ_TYPES); 1000 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type]; 1001 } 1002 1003 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel) 1004 { 1005 return channel->channel - channel->efx->tx_channel_offset < 1006 channel->efx->n_tx_channels; 1007 } 1008 1009 static inline struct efx_tx_queue * 1010 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type) 1011 { 1012 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) || 1013 type >= EFX_TXQ_TYPES); 1014 return &channel->tx_queue[type]; 1015 } 1016 1017 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue) 1018 { 1019 return !(tx_queue->efx->net_dev->num_tc < 2 && 1020 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI); 1021 } 1022 1023 /* Iterate over all TX queues belonging to a channel */ 1024 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ 1025 if (!efx_channel_has_tx_queues(_channel)) \ 1026 ; \ 1027 else \ 1028 for (_tx_queue = (_channel)->tx_queue; \ 1029 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \ 1030 efx_tx_queue_used(_tx_queue); \ 1031 _tx_queue++) 1032 1033 /* Iterate over all possible TX queues belonging to a channel */ 1034 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \ 1035 if (!efx_channel_has_tx_queues(_channel)) \ 1036 ; \ 1037 else \ 1038 for (_tx_queue = (_channel)->tx_queue; \ 1039 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ 1040 _tx_queue++) 1041 1042 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel) 1043 { 1044 return channel->channel < channel->efx->n_rx_channels; 1045 } 1046 1047 static inline struct efx_rx_queue * 1048 efx_channel_get_rx_queue(struct efx_channel *channel) 1049 { 1050 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel)); 1051 return &channel->rx_queue; 1052 } 1053 1054 /* Iterate over all RX queues belonging to a channel */ 1055 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ 1056 if (!efx_channel_has_rx_queue(_channel)) \ 1057 ; \ 1058 else \ 1059 for (_rx_queue = &(_channel)->rx_queue; \ 1060 _rx_queue; \ 1061 _rx_queue = NULL) 1062 1063 static inline struct efx_channel * 1064 efx_rx_queue_channel(struct efx_rx_queue *rx_queue) 1065 { 1066 return container_of(rx_queue, struct efx_channel, rx_queue); 1067 } 1068 1069 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) 1070 { 1071 return efx_rx_queue_channel(rx_queue)->channel; 1072 } 1073 1074 /* Returns a pointer to the specified receive buffer in the RX 1075 * descriptor queue. 1076 */ 1077 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, 1078 unsigned int index) 1079 { 1080 return &rx_queue->buffer[index]; 1081 } 1082 1083 /* Set bit in a little-endian bitfield */ 1084 static inline void set_bit_le(unsigned nr, unsigned char *addr) 1085 { 1086 addr[nr / 8] |= (1 << (nr % 8)); 1087 } 1088 1089 /* Clear bit in a little-endian bitfield */ 1090 static inline void clear_bit_le(unsigned nr, unsigned char *addr) 1091 { 1092 addr[nr / 8] &= ~(1 << (nr % 8)); 1093 } 1094 1095 1096 /** 1097 * EFX_MAX_FRAME_LEN - calculate maximum frame length 1098 * 1099 * This calculates the maximum frame length that will be used for a 1100 * given MTU. The frame length will be equal to the MTU plus a 1101 * constant amount of header space and padding. This is the quantity 1102 * that the net driver will program into the MAC as the maximum frame 1103 * length. 1104 * 1105 * The 10G MAC requires 8-byte alignment on the frame 1106 * length, so we round up to the nearest 8. 1107 * 1108 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an 1109 * XGMII cycle). If the frame length reaches the maximum value in the 1110 * same cycle, the XMAC can miss the IPG altogether. We work around 1111 * this by adding a further 16 bytes. 1112 */ 1113 #define EFX_MAX_FRAME_LEN(mtu) \ 1114 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16) 1115 1116 1117 #endif /* EFX_NET_DRIVER_H */ 1118