1 /****************************************************************************
2  * Driver for Solarflare network controllers and boards
3  * Copyright 2005-2006 Fen Systems Ltd.
4  * Copyright 2005-2013 Solarflare Communications Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published
8  * by the Free Software Foundation, incorporated herein by reference.
9  */
10 
11 /* Common definitions for all Efx net driver code */
12 
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
15 
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/if_vlan.h>
20 #include <linux/timer.h>
21 #include <linux/mdio.h>
22 #include <linux/list.h>
23 #include <linux/pci.h>
24 #include <linux/device.h>
25 #include <linux/highmem.h>
26 #include <linux/workqueue.h>
27 #include <linux/mutex.h>
28 #include <linux/rwsem.h>
29 #include <linux/vmalloc.h>
30 #include <linux/i2c.h>
31 #include <linux/mtd/mtd.h>
32 #include <net/busy_poll.h>
33 
34 #include "enum.h"
35 #include "bitfield.h"
36 #include "filter.h"
37 
38 /**************************************************************************
39  *
40  * Build definitions
41  *
42  **************************************************************************/
43 
44 #define EFX_DRIVER_VERSION	"4.0"
45 
46 #ifdef DEBUG
47 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
48 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
49 #else
50 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
51 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
52 #endif
53 
54 /**************************************************************************
55  *
56  * Efx data structures
57  *
58  **************************************************************************/
59 
60 #define EFX_MAX_CHANNELS 32U
61 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
62 #define EFX_EXTRA_CHANNEL_IOV	0
63 #define EFX_EXTRA_CHANNEL_PTP	1
64 #define EFX_MAX_EXTRA_CHANNELS	2U
65 
66 /* Checksum generation is a per-queue option in hardware, so each
67  * queue visible to the networking core is backed by two hardware TX
68  * queues. */
69 #define EFX_MAX_TX_TC		2
70 #define EFX_MAX_CORE_TX_QUEUES	(EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
71 #define EFX_TXQ_TYPE_OFFLOAD	1	/* flag */
72 #define EFX_TXQ_TYPE_HIGHPRI	2	/* flag */
73 #define EFX_TXQ_TYPES		4
74 #define EFX_MAX_TX_QUEUES	(EFX_TXQ_TYPES * EFX_MAX_CHANNELS)
75 
76 /* Maximum possible MTU the driver supports */
77 #define EFX_MAX_MTU (9 * 1024)
78 
79 /* Size of an RX scatter buffer.  Small enough to pack 2 into a 4K page,
80  * and should be a multiple of the cache line size.
81  */
82 #define EFX_RX_USR_BUF_SIZE	(2048 - 256)
83 
84 /* If possible, we should ensure cache line alignment at start and end
85  * of every buffer.  Otherwise, we just need to ensure 4-byte
86  * alignment of the network header.
87  */
88 #if NET_IP_ALIGN == 0
89 #define EFX_RX_BUF_ALIGNMENT	L1_CACHE_BYTES
90 #else
91 #define EFX_RX_BUF_ALIGNMENT	4
92 #endif
93 
94 /* Forward declare Precision Time Protocol (PTP) support structure. */
95 struct efx_ptp_data;
96 struct hwtstamp_config;
97 
98 struct efx_self_tests;
99 
100 /**
101  * struct efx_buffer - A general-purpose DMA buffer
102  * @addr: host base address of the buffer
103  * @dma_addr: DMA base address of the buffer
104  * @len: Buffer length, in bytes
105  *
106  * The NIC uses these buffers for its interrupt status registers and
107  * MAC stats dumps.
108  */
109 struct efx_buffer {
110 	void *addr;
111 	dma_addr_t dma_addr;
112 	unsigned int len;
113 };
114 
115 /**
116  * struct efx_special_buffer - DMA buffer entered into buffer table
117  * @buf: Standard &struct efx_buffer
118  * @index: Buffer index within controller;s buffer table
119  * @entries: Number of buffer table entries
120  *
121  * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE.
122  * Event and descriptor rings are addressed via one or more buffer
123  * table entries (and so can be physically non-contiguous, although we
124  * currently do not take advantage of that).  On Falcon and Siena we
125  * have to take care of allocating and initialising the entries
126  * ourselves.  On later hardware this is managed by the firmware and
127  * @index and @entries are left as 0.
128  */
129 struct efx_special_buffer {
130 	struct efx_buffer buf;
131 	unsigned int index;
132 	unsigned int entries;
133 };
134 
135 /**
136  * struct efx_tx_buffer - buffer state for a TX descriptor
137  * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be
138  *	freed when descriptor completes
139  * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be
140  *	freed when descriptor completes.
141  * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor.
142  * @dma_addr: DMA address of the fragment.
143  * @flags: Flags for allocation and DMA mapping type
144  * @len: Length of this fragment.
145  *	This field is zero when the queue slot is empty.
146  * @unmap_len: Length of this fragment to unmap
147  * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.
148  * Only valid if @unmap_len != 0.
149  */
150 struct efx_tx_buffer {
151 	union {
152 		const struct sk_buff *skb;
153 		void *heap_buf;
154 	};
155 	union {
156 		efx_qword_t option;
157 		dma_addr_t dma_addr;
158 	};
159 	unsigned short flags;
160 	unsigned short len;
161 	unsigned short unmap_len;
162 	unsigned short dma_offset;
163 };
164 #define EFX_TX_BUF_CONT		1	/* not last descriptor of packet */
165 #define EFX_TX_BUF_SKB		2	/* buffer is last part of skb */
166 #define EFX_TX_BUF_HEAP		4	/* buffer was allocated with kmalloc() */
167 #define EFX_TX_BUF_MAP_SINGLE	8	/* buffer was mapped with dma_map_single() */
168 #define EFX_TX_BUF_OPTION	0x10	/* empty buffer for option descriptor */
169 
170 /**
171  * struct efx_tx_queue - An Efx TX queue
172  *
173  * This is a ring buffer of TX fragments.
174  * Since the TX completion path always executes on the same
175  * CPU and the xmit path can operate on different CPUs,
176  * performance is increased by ensuring that the completion
177  * path and the xmit path operate on different cache lines.
178  * This is particularly important if the xmit path is always
179  * executing on one CPU which is different from the completion
180  * path.  There is also a cache line for members which are
181  * read but not written on the fast path.
182  *
183  * @efx: The associated Efx NIC
184  * @queue: DMA queue number
185  * @tso_version: Version of TSO in use for this queue.
186  * @channel: The associated channel
187  * @core_txq: The networking core TX queue structure
188  * @buffer: The software buffer ring
189  * @tsoh_page: Array of pages of TSO header buffers
190  * @txd: The hardware descriptor ring
191  * @ptr_mask: The size of the ring minus 1.
192  * @piobuf: PIO buffer region for this TX queue (shared with its partner).
193  *	Size of the region is efx_piobuf_size.
194  * @piobuf_offset: Buffer offset to be specified in PIO descriptors
195  * @initialised: Has hardware queue been initialised?
196  * @read_count: Current read pointer.
197  *	This is the number of buffers that have been removed from both rings.
198  * @old_write_count: The value of @write_count when last checked.
199  *	This is here for performance reasons.  The xmit path will
200  *	only get the up-to-date value of @write_count if this
201  *	variable indicates that the queue is empty.  This is to
202  *	avoid cache-line ping-pong between the xmit path and the
203  *	completion path.
204  * @merge_events: Number of TX merged completion events
205  * @insert_count: Current insert pointer
206  *	This is the number of buffers that have been added to the
207  *	software ring.
208  * @write_count: Current write pointer
209  *	This is the number of buffers that have been added to the
210  *	hardware ring.
211  * @old_read_count: The value of read_count when last checked.
212  *	This is here for performance reasons.  The xmit path will
213  *	only get the up-to-date value of read_count if this
214  *	variable indicates that the queue is full.  This is to
215  *	avoid cache-line ping-pong between the xmit path and the
216  *	completion path.
217  * @tso_bursts: Number of times TSO xmit invoked by kernel
218  * @tso_long_headers: Number of packets with headers too long for standard
219  *	blocks
220  * @tso_packets: Number of packets via the TSO xmit path
221  * @pushes: Number of times the TX push feature has been used
222  * @pio_packets: Number of times the TX PIO feature has been used
223  * @xmit_more_available: Are any packets waiting to be pushed to the NIC
224  * @empty_read_count: If the completion path has seen the queue as empty
225  *	and the transmission path has not yet checked this, the value of
226  *	@read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
227  */
228 struct efx_tx_queue {
229 	/* Members which don't change on the fast path */
230 	struct efx_nic *efx ____cacheline_aligned_in_smp;
231 	unsigned queue;
232 	unsigned int tso_version;
233 	struct efx_channel *channel;
234 	struct netdev_queue *core_txq;
235 	struct efx_tx_buffer *buffer;
236 	struct efx_buffer *tsoh_page;
237 	struct efx_special_buffer txd;
238 	unsigned int ptr_mask;
239 	void __iomem *piobuf;
240 	unsigned int piobuf_offset;
241 	bool initialised;
242 
243 	/* Members used mainly on the completion path */
244 	unsigned int read_count ____cacheline_aligned_in_smp;
245 	unsigned int old_write_count;
246 	unsigned int merge_events;
247 	unsigned int bytes_compl;
248 	unsigned int pkts_compl;
249 
250 	/* Members used only on the xmit path */
251 	unsigned int insert_count ____cacheline_aligned_in_smp;
252 	unsigned int write_count;
253 	unsigned int old_read_count;
254 	unsigned int tso_bursts;
255 	unsigned int tso_long_headers;
256 	unsigned int tso_packets;
257 	unsigned int pushes;
258 	unsigned int pio_packets;
259 	bool xmit_more_available;
260 	/* Statistics to supplement MAC stats */
261 	unsigned long tx_packets;
262 
263 	/* Members shared between paths and sometimes updated */
264 	unsigned int empty_read_count ____cacheline_aligned_in_smp;
265 #define EFX_EMPTY_COUNT_VALID 0x80000000
266 	atomic_t flush_outstanding;
267 };
268 
269 /**
270  * struct efx_rx_buffer - An Efx RX data buffer
271  * @dma_addr: DMA base address of the buffer
272  * @page: The associated page buffer.
273  *	Will be %NULL if the buffer slot is currently free.
274  * @page_offset: If pending: offset in @page of DMA base address.
275  *	If completed: offset in @page of Ethernet header.
276  * @len: If pending: length for DMA descriptor.
277  *	If completed: received length, excluding hash prefix.
278  * @flags: Flags for buffer and packet state.  These are only set on the
279  *	first buffer of a scattered packet.
280  */
281 struct efx_rx_buffer {
282 	dma_addr_t dma_addr;
283 	struct page *page;
284 	u16 page_offset;
285 	u16 len;
286 	u16 flags;
287 };
288 #define EFX_RX_BUF_LAST_IN_PAGE	0x0001
289 #define EFX_RX_PKT_CSUMMED	0x0002
290 #define EFX_RX_PKT_DISCARD	0x0004
291 #define EFX_RX_PKT_TCP		0x0040
292 #define EFX_RX_PKT_PREFIX_LEN	0x0080	/* length is in prefix only */
293 
294 /**
295  * struct efx_rx_page_state - Page-based rx buffer state
296  *
297  * Inserted at the start of every page allocated for receive buffers.
298  * Used to facilitate sharing dma mappings between recycled rx buffers
299  * and those passed up to the kernel.
300  *
301  * @dma_addr: The dma address of this page.
302  */
303 struct efx_rx_page_state {
304 	dma_addr_t dma_addr;
305 
306 	unsigned int __pad[0] ____cacheline_aligned;
307 };
308 
309 /**
310  * struct efx_rx_queue - An Efx RX queue
311  * @efx: The associated Efx NIC
312  * @core_index:  Index of network core RX queue.  Will be >= 0 iff this
313  *	is associated with a real RX queue.
314  * @buffer: The software buffer ring
315  * @rxd: The hardware descriptor ring
316  * @ptr_mask: The size of the ring minus 1.
317  * @refill_enabled: Enable refill whenever fill level is low
318  * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
319  *	@rxq_flush_pending.
320  * @added_count: Number of buffers added to the receive queue.
321  * @notified_count: Number of buffers given to NIC (<= @added_count).
322  * @removed_count: Number of buffers removed from the receive queue.
323  * @scatter_n: Used by NIC specific receive code.
324  * @scatter_len: Used by NIC specific receive code.
325  * @page_ring: The ring to store DMA mapped pages for reuse.
326  * @page_add: Counter to calculate the write pointer for the recycle ring.
327  * @page_remove: Counter to calculate the read pointer for the recycle ring.
328  * @page_recycle_count: The number of pages that have been recycled.
329  * @page_recycle_failed: The number of pages that couldn't be recycled because
330  *      the kernel still held a reference to them.
331  * @page_recycle_full: The number of pages that were released because the
332  *      recycle ring was full.
333  * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
334  * @max_fill: RX descriptor maximum fill level (<= ring size)
335  * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
336  *	(<= @max_fill)
337  * @min_fill: RX descriptor minimum non-zero fill level.
338  *	This records the minimum fill level observed when a ring
339  *	refill was triggered.
340  * @recycle_count: RX buffer recycle counter.
341  * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
342  */
343 struct efx_rx_queue {
344 	struct efx_nic *efx;
345 	int core_index;
346 	struct efx_rx_buffer *buffer;
347 	struct efx_special_buffer rxd;
348 	unsigned int ptr_mask;
349 	bool refill_enabled;
350 	bool flush_pending;
351 
352 	unsigned int added_count;
353 	unsigned int notified_count;
354 	unsigned int removed_count;
355 	unsigned int scatter_n;
356 	unsigned int scatter_len;
357 	struct page **page_ring;
358 	unsigned int page_add;
359 	unsigned int page_remove;
360 	unsigned int page_recycle_count;
361 	unsigned int page_recycle_failed;
362 	unsigned int page_recycle_full;
363 	unsigned int page_ptr_mask;
364 	unsigned int max_fill;
365 	unsigned int fast_fill_trigger;
366 	unsigned int min_fill;
367 	unsigned int min_overfill;
368 	unsigned int recycle_count;
369 	struct timer_list slow_fill;
370 	unsigned int slow_fill_count;
371 	/* Statistics to supplement MAC stats */
372 	unsigned long rx_packets;
373 };
374 
375 enum efx_sync_events_state {
376 	SYNC_EVENTS_DISABLED = 0,
377 	SYNC_EVENTS_QUIESCENT,
378 	SYNC_EVENTS_REQUESTED,
379 	SYNC_EVENTS_VALID,
380 };
381 
382 /**
383  * struct efx_channel - An Efx channel
384  *
385  * A channel comprises an event queue, at least one TX queue, at least
386  * one RX queue, and an associated tasklet for processing the event
387  * queue.
388  *
389  * @efx: Associated Efx NIC
390  * @channel: Channel instance number
391  * @type: Channel type definition
392  * @eventq_init: Event queue initialised flag
393  * @enabled: Channel enabled indicator
394  * @irq: IRQ number (MSI and MSI-X only)
395  * @irq_moderation: IRQ moderation value (in hardware ticks)
396  * @napi_dev: Net device used with NAPI
397  * @napi_str: NAPI control structure
398  * @state: state for NAPI vs busy polling
399  * @state_lock: lock protecting @state
400  * @eventq: Event queue buffer
401  * @eventq_mask: Event queue pointer mask
402  * @eventq_read_ptr: Event queue read pointer
403  * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
404  * @irq_count: Number of IRQs since last adaptive moderation decision
405  * @irq_mod_score: IRQ moderation score
406  * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS,
407  *      indexed by filter ID
408  * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
409  * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
410  * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
411  * @n_rx_mcast_mismatch: Count of unmatched multicast frames
412  * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
413  * @n_rx_overlength: Count of RX_OVERLENGTH errors
414  * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
415  * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
416  *	lack of descriptors
417  * @n_rx_merge_events: Number of RX merged completion events
418  * @n_rx_merge_packets: Number of RX packets completed by merged events
419  * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by
420  *	__efx_rx_packet(), or zero if there is none
421  * @rx_pkt_index: Ring index of first buffer for next packet to be delivered
422  *	by __efx_rx_packet(), if @rx_pkt_n_frags != 0
423  * @rx_queue: RX queue for this channel
424  * @tx_queue: TX queues for this channel
425  * @sync_events_state: Current state of sync events on this channel
426  * @sync_timestamp_major: Major part of the last ptp sync event
427  * @sync_timestamp_minor: Minor part of the last ptp sync event
428  */
429 struct efx_channel {
430 	struct efx_nic *efx;
431 	int channel;
432 	const struct efx_channel_type *type;
433 	bool eventq_init;
434 	bool enabled;
435 	int irq;
436 	unsigned int irq_moderation;
437 	struct net_device *napi_dev;
438 	struct napi_struct napi_str;
439 #ifdef CONFIG_NET_RX_BUSY_POLL
440 	unsigned long busy_poll_state;
441 #endif
442 	struct efx_special_buffer eventq;
443 	unsigned int eventq_mask;
444 	unsigned int eventq_read_ptr;
445 	int event_test_cpu;
446 
447 	unsigned int irq_count;
448 	unsigned int irq_mod_score;
449 #ifdef CONFIG_RFS_ACCEL
450 	unsigned int rfs_filters_added;
451 #define RPS_FLOW_ID_INVALID 0xFFFFFFFF
452 	u32 *rps_flow_id;
453 #endif
454 
455 	unsigned n_rx_tobe_disc;
456 	unsigned n_rx_ip_hdr_chksum_err;
457 	unsigned n_rx_tcp_udp_chksum_err;
458 	unsigned n_rx_mcast_mismatch;
459 	unsigned n_rx_frm_trunc;
460 	unsigned n_rx_overlength;
461 	unsigned n_skbuff_leaks;
462 	unsigned int n_rx_nodesc_trunc;
463 	unsigned int n_rx_merge_events;
464 	unsigned int n_rx_merge_packets;
465 
466 	unsigned int rx_pkt_n_frags;
467 	unsigned int rx_pkt_index;
468 
469 	struct efx_rx_queue rx_queue;
470 	struct efx_tx_queue tx_queue[EFX_TXQ_TYPES];
471 
472 	enum efx_sync_events_state sync_events_state;
473 	u32 sync_timestamp_major;
474 	u32 sync_timestamp_minor;
475 };
476 
477 #ifdef CONFIG_NET_RX_BUSY_POLL
478 enum efx_channel_busy_poll_state {
479 	EFX_CHANNEL_STATE_IDLE = 0,
480 	EFX_CHANNEL_STATE_NAPI = BIT(0),
481 	EFX_CHANNEL_STATE_NAPI_REQ_BIT = 1,
482 	EFX_CHANNEL_STATE_NAPI_REQ = BIT(1),
483 	EFX_CHANNEL_STATE_POLL_BIT = 2,
484 	EFX_CHANNEL_STATE_POLL = BIT(2),
485 	EFX_CHANNEL_STATE_DISABLE_BIT = 3,
486 };
487 
488 static inline void efx_channel_busy_poll_init(struct efx_channel *channel)
489 {
490 	WRITE_ONCE(channel->busy_poll_state, EFX_CHANNEL_STATE_IDLE);
491 }
492 
493 /* Called from the device poll routine to get ownership of a channel. */
494 static inline bool efx_channel_lock_napi(struct efx_channel *channel)
495 {
496 	unsigned long prev, old = READ_ONCE(channel->busy_poll_state);
497 
498 	while (1) {
499 		switch (old) {
500 		case EFX_CHANNEL_STATE_POLL:
501 			/* Ensure efx_channel_try_lock_poll() wont starve us */
502 			set_bit(EFX_CHANNEL_STATE_NAPI_REQ_BIT,
503 				&channel->busy_poll_state);
504 			/* fallthrough */
505 		case EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_NAPI_REQ:
506 			return false;
507 		default:
508 			break;
509 		}
510 		prev = cmpxchg(&channel->busy_poll_state, old,
511 			       EFX_CHANNEL_STATE_NAPI);
512 		if (unlikely(prev != old)) {
513 			/* This is likely to mean we've just entered polling
514 			 * state. Go back round to set the REQ bit.
515 			 */
516 			old = prev;
517 			continue;
518 		}
519 		return true;
520 	}
521 }
522 
523 static inline void efx_channel_unlock_napi(struct efx_channel *channel)
524 {
525 	/* Make sure write has completed from efx_channel_lock_napi() */
526 	smp_wmb();
527 	WRITE_ONCE(channel->busy_poll_state, EFX_CHANNEL_STATE_IDLE);
528 }
529 
530 /* Called from efx_busy_poll(). */
531 static inline bool efx_channel_try_lock_poll(struct efx_channel *channel)
532 {
533 	return cmpxchg(&channel->busy_poll_state, EFX_CHANNEL_STATE_IDLE,
534 			EFX_CHANNEL_STATE_POLL) == EFX_CHANNEL_STATE_IDLE;
535 }
536 
537 static inline void efx_channel_unlock_poll(struct efx_channel *channel)
538 {
539 	clear_bit_unlock(EFX_CHANNEL_STATE_POLL_BIT, &channel->busy_poll_state);
540 }
541 
542 static inline bool efx_channel_busy_polling(struct efx_channel *channel)
543 {
544 	return test_bit(EFX_CHANNEL_STATE_POLL_BIT, &channel->busy_poll_state);
545 }
546 
547 static inline void efx_channel_enable(struct efx_channel *channel)
548 {
549 	clear_bit_unlock(EFX_CHANNEL_STATE_DISABLE_BIT,
550 			 &channel->busy_poll_state);
551 }
552 
553 /* Stop further polling or napi access.
554  * Returns false if the channel is currently busy polling.
555  */
556 static inline bool efx_channel_disable(struct efx_channel *channel)
557 {
558 	set_bit(EFX_CHANNEL_STATE_DISABLE_BIT, &channel->busy_poll_state);
559 	/* Implicit barrier in efx_channel_busy_polling() */
560 	return !efx_channel_busy_polling(channel);
561 }
562 
563 #else /* CONFIG_NET_RX_BUSY_POLL */
564 
565 static inline void efx_channel_busy_poll_init(struct efx_channel *channel)
566 {
567 }
568 
569 static inline bool efx_channel_lock_napi(struct efx_channel *channel)
570 {
571 	return true;
572 }
573 
574 static inline void efx_channel_unlock_napi(struct efx_channel *channel)
575 {
576 }
577 
578 static inline bool efx_channel_try_lock_poll(struct efx_channel *channel)
579 {
580 	return false;
581 }
582 
583 static inline void efx_channel_unlock_poll(struct efx_channel *channel)
584 {
585 }
586 
587 static inline bool efx_channel_busy_polling(struct efx_channel *channel)
588 {
589 	return false;
590 }
591 
592 static inline void efx_channel_enable(struct efx_channel *channel)
593 {
594 }
595 
596 static inline bool efx_channel_disable(struct efx_channel *channel)
597 {
598 	return true;
599 }
600 #endif /* CONFIG_NET_RX_BUSY_POLL */
601 
602 /**
603  * struct efx_msi_context - Context for each MSI
604  * @efx: The associated NIC
605  * @index: Index of the channel/IRQ
606  * @name: Name of the channel/IRQ
607  *
608  * Unlike &struct efx_channel, this is never reallocated and is always
609  * safe for the IRQ handler to access.
610  */
611 struct efx_msi_context {
612 	struct efx_nic *efx;
613 	unsigned int index;
614 	char name[IFNAMSIZ + 6];
615 };
616 
617 /**
618  * struct efx_channel_type - distinguishes traffic and extra channels
619  * @handle_no_channel: Handle failure to allocate an extra channel
620  * @pre_probe: Set up extra state prior to initialisation
621  * @post_remove: Tear down extra state after finalisation, if allocated.
622  *	May be called on channels that have not been probed.
623  * @get_name: Generate the channel's name (used for its IRQ handler)
624  * @copy: Copy the channel state prior to reallocation.  May be %NULL if
625  *	reallocation is not supported.
626  * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()
627  * @keep_eventq: Flag for whether event queue should be kept initialised
628  *	while the device is stopped
629  */
630 struct efx_channel_type {
631 	void (*handle_no_channel)(struct efx_nic *);
632 	int (*pre_probe)(struct efx_channel *);
633 	void (*post_remove)(struct efx_channel *);
634 	void (*get_name)(struct efx_channel *, char *buf, size_t len);
635 	struct efx_channel *(*copy)(const struct efx_channel *);
636 	bool (*receive_skb)(struct efx_channel *, struct sk_buff *);
637 	bool keep_eventq;
638 };
639 
640 enum efx_led_mode {
641 	EFX_LED_OFF	= 0,
642 	EFX_LED_ON	= 1,
643 	EFX_LED_DEFAULT	= 2
644 };
645 
646 #define STRING_TABLE_LOOKUP(val, member) \
647 	((val) < member ## _max) ? member ## _names[val] : "(invalid)"
648 
649 extern const char *const efx_loopback_mode_names[];
650 extern const unsigned int efx_loopback_mode_max;
651 #define LOOPBACK_MODE(efx) \
652 	STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
653 
654 extern const char *const efx_reset_type_names[];
655 extern const unsigned int efx_reset_type_max;
656 #define RESET_TYPE(type) \
657 	STRING_TABLE_LOOKUP(type, efx_reset_type)
658 
659 enum efx_int_mode {
660 	/* Be careful if altering to correct macro below */
661 	EFX_INT_MODE_MSIX = 0,
662 	EFX_INT_MODE_MSI = 1,
663 	EFX_INT_MODE_LEGACY = 2,
664 	EFX_INT_MODE_MAX	/* Insert any new items before this */
665 };
666 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
667 
668 enum nic_state {
669 	STATE_UNINIT = 0,	/* device being probed/removed or is frozen */
670 	STATE_READY = 1,	/* hardware ready and netdev registered */
671 	STATE_DISABLED = 2,	/* device disabled due to hardware errors */
672 	STATE_RECOVERY = 3,	/* device recovering from PCI error */
673 };
674 
675 /* Forward declaration */
676 struct efx_nic;
677 
678 /* Pseudo bit-mask flow control field */
679 #define EFX_FC_RX	FLOW_CTRL_RX
680 #define EFX_FC_TX	FLOW_CTRL_TX
681 #define EFX_FC_AUTO	4
682 
683 /**
684  * struct efx_link_state - Current state of the link
685  * @up: Link is up
686  * @fd: Link is full-duplex
687  * @fc: Actual flow control flags
688  * @speed: Link speed (Mbps)
689  */
690 struct efx_link_state {
691 	bool up;
692 	bool fd;
693 	u8 fc;
694 	unsigned int speed;
695 };
696 
697 static inline bool efx_link_state_equal(const struct efx_link_state *left,
698 					const struct efx_link_state *right)
699 {
700 	return left->up == right->up && left->fd == right->fd &&
701 		left->fc == right->fc && left->speed == right->speed;
702 }
703 
704 /**
705  * struct efx_phy_operations - Efx PHY operations table
706  * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
707  *	efx->loopback_modes.
708  * @init: Initialise PHY
709  * @fini: Shut down PHY
710  * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
711  * @poll: Update @link_state and report whether it changed.
712  *	Serialised by the mac_lock.
713  * @get_settings: Get ethtool settings. Serialised by the mac_lock.
714  * @set_settings: Set ethtool settings. Serialised by the mac_lock.
715  * @set_npage_adv: Set abilities advertised in (Extended) Next Page
716  *	(only needed where AN bit is set in mmds)
717  * @test_alive: Test that PHY is 'alive' (online)
718  * @test_name: Get the name of a PHY-specific test/result
719  * @run_tests: Run tests and record results as appropriate (offline).
720  *	Flags are the ethtool tests flags.
721  */
722 struct efx_phy_operations {
723 	int (*probe) (struct efx_nic *efx);
724 	int (*init) (struct efx_nic *efx);
725 	void (*fini) (struct efx_nic *efx);
726 	void (*remove) (struct efx_nic *efx);
727 	int (*reconfigure) (struct efx_nic *efx);
728 	bool (*poll) (struct efx_nic *efx);
729 	void (*get_settings) (struct efx_nic *efx,
730 			      struct ethtool_cmd *ecmd);
731 	int (*set_settings) (struct efx_nic *efx,
732 			     struct ethtool_cmd *ecmd);
733 	void (*set_npage_adv) (struct efx_nic *efx, u32);
734 	int (*test_alive) (struct efx_nic *efx);
735 	const char *(*test_name) (struct efx_nic *efx, unsigned int index);
736 	int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
737 	int (*get_module_eeprom) (struct efx_nic *efx,
738 			       struct ethtool_eeprom *ee,
739 			       u8 *data);
740 	int (*get_module_info) (struct efx_nic *efx,
741 				struct ethtool_modinfo *modinfo);
742 };
743 
744 /**
745  * enum efx_phy_mode - PHY operating mode flags
746  * @PHY_MODE_NORMAL: on and should pass traffic
747  * @PHY_MODE_TX_DISABLED: on with TX disabled
748  * @PHY_MODE_LOW_POWER: set to low power through MDIO
749  * @PHY_MODE_OFF: switched off through external control
750  * @PHY_MODE_SPECIAL: on but will not pass traffic
751  */
752 enum efx_phy_mode {
753 	PHY_MODE_NORMAL		= 0,
754 	PHY_MODE_TX_DISABLED	= 1,
755 	PHY_MODE_LOW_POWER	= 2,
756 	PHY_MODE_OFF		= 4,
757 	PHY_MODE_SPECIAL	= 8,
758 };
759 
760 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
761 {
762 	return !!(mode & ~PHY_MODE_TX_DISABLED);
763 }
764 
765 /**
766  * struct efx_hw_stat_desc - Description of a hardware statistic
767  * @name: Name of the statistic as visible through ethtool, or %NULL if
768  *	it should not be exposed
769  * @dma_width: Width in bits (0 for non-DMA statistics)
770  * @offset: Offset within stats (ignored for non-DMA statistics)
771  */
772 struct efx_hw_stat_desc {
773 	const char *name;
774 	u16 dma_width;
775 	u16 offset;
776 };
777 
778 /* Number of bits used in a multicast filter hash address */
779 #define EFX_MCAST_HASH_BITS 8
780 
781 /* Number of (single-bit) entries in a multicast filter hash */
782 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
783 
784 /* An Efx multicast filter hash */
785 union efx_multicast_hash {
786 	u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
787 	efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
788 };
789 
790 struct vfdi_status;
791 
792 /**
793  * struct efx_nic - an Efx NIC
794  * @name: Device name (net device name or bus id before net device registered)
795  * @pci_dev: The PCI device
796  * @node: List node for maintaning primary/secondary function lists
797  * @primary: &struct efx_nic instance for the primary function of this
798  *	controller.  May be the same structure, and may be %NULL if no
799  *	primary function is bound.  Serialised by rtnl_lock.
800  * @secondary_list: List of &struct efx_nic instances for the secondary PCI
801  *	functions of the controller, if this is for the primary function.
802  *	Serialised by rtnl_lock.
803  * @type: Controller type attributes
804  * @legacy_irq: IRQ number
805  * @workqueue: Workqueue for port reconfigures and the HW monitor.
806  *	Work items do not hold and must not acquire RTNL.
807  * @workqueue_name: Name of workqueue
808  * @reset_work: Scheduled reset workitem
809  * @membase_phys: Memory BAR value as physical address
810  * @membase: Memory BAR value
811  * @interrupt_mode: Interrupt mode
812  * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
813  * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
814  * @irq_rx_moderation: IRQ moderation time for RX event queues
815  * @msg_enable: Log message enable flags
816  * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.
817  * @reset_pending: Bitmask for pending resets
818  * @tx_queue: TX DMA queues
819  * @rx_queue: RX DMA queues
820  * @channel: Channels
821  * @msi_context: Context for each MSI
822  * @extra_channel_types: Types of extra (non-traffic) channels that
823  *	should be allocated for this NIC
824  * @rxq_entries: Size of receive queues requested by user.
825  * @txq_entries: Size of transmit queues requested by user.
826  * @txq_stop_thresh: TX queue fill level at or above which we stop it.
827  * @txq_wake_thresh: TX queue fill level at or below which we wake it.
828  * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
829  * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
830  * @sram_lim_qw: Qword address limit of SRAM
831  * @next_buffer_table: First available buffer table id
832  * @n_channels: Number of channels in use
833  * @n_rx_channels: Number of channels used for RX (= number of RX queues)
834  * @n_tx_channels: Number of channels used for TX
835  * @rx_ip_align: RX DMA address offset to have IP header aligned in
836  *	in accordance with NET_IP_ALIGN
837  * @rx_dma_len: Current maximum RX DMA length
838  * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
839  * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
840  *	for use in sk_buff::truesize
841  * @rx_prefix_size: Size of RX prefix before packet data
842  * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data
843  *	(valid only if @rx_prefix_size != 0; always negative)
844  * @rx_packet_len_offset: Offset of RX packet length from start of packet data
845  *	(valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative)
846  * @rx_packet_ts_offset: Offset of timestamp from start of packet data
847  *	(valid only if channel->sync_timestamps_enabled; always negative)
848  * @rx_hash_key: Toeplitz hash key for RSS
849  * @rx_indir_table: Indirection table for RSS
850  * @rx_scatter: Scatter mode enabled for receives
851  * @int_error_count: Number of internal errors seen recently
852  * @int_error_expire: Time at which error count will be expired
853  * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
854  *	acknowledge but do nothing else.
855  * @irq_status: Interrupt status buffer
856  * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
857  * @irq_level: IRQ level/index for IRQs not triggered by an event queue
858  * @selftest_work: Work item for asynchronous self-test
859  * @mtd_list: List of MTDs attached to the NIC
860  * @nic_data: Hardware dependent state
861  * @mcdi: Management-Controller-to-Driver Interface state
862  * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
863  *	efx_monitor() and efx_reconfigure_port()
864  * @port_enabled: Port enabled indicator.
865  *	Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
866  *	efx_mac_work() with kernel interfaces. Safe to read under any
867  *	one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
868  *	be held to modify it.
869  * @port_initialized: Port initialized?
870  * @net_dev: Operating system network device. Consider holding the rtnl lock
871  * @stats_buffer: DMA buffer for statistics
872  * @phy_type: PHY type
873  * @phy_op: PHY interface
874  * @phy_data: PHY private data (including PHY-specific stats)
875  * @mdio: PHY MDIO interface
876  * @mdio_bus: PHY MDIO bus ID (only used by Siena)
877  * @phy_mode: PHY operating mode. Serialised by @mac_lock.
878  * @link_advertising: Autonegotiation advertising flags
879  * @link_state: Current state of the link
880  * @n_link_state_changes: Number of times the link has changed state
881  * @unicast_filter: Flag for Falcon-arch simple unicast filter.
882  *	Protected by @mac_lock.
883  * @multicast_hash: Multicast hash table for Falcon-arch.
884  *	Protected by @mac_lock.
885  * @wanted_fc: Wanted flow control flags
886  * @fc_disable: When non-zero flow control is disabled. Typically used to
887  *	ensure that network back pressure doesn't delay dma queue flushes.
888  *	Serialised by the rtnl lock.
889  * @mac_work: Work item for changing MAC promiscuity and multicast hash
890  * @loopback_mode: Loopback status
891  * @loopback_modes: Supported loopback mode bitmask
892  * @loopback_selftest: Offline self-test private state
893  * @filter_sem: Filter table rw_semaphore, for freeing the table
894  * @filter_lock: Filter table lock, for mere content changes
895  * @filter_state: Architecture-dependent filter table state
896  * @rps_expire_channel: Next channel to check for expiry
897  * @rps_expire_index: Next index to check for expiry in
898  *	@rps_expire_channel's @rps_flow_id
899  * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
900  * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
901  *	Decremented when the efx_flush_rx_queue() is called.
902  * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
903  *	completed (either success or failure). Not used when MCDI is used to
904  *	flush receive queues.
905  * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
906  * @vf_count: Number of VFs intended to be enabled.
907  * @vf_init_count: Number of VFs that have been fully initialised.
908  * @vi_scale: log2 number of vnics per VF.
909  * @ptp_data: PTP state data
910  * @vpd_sn: Serial number read from VPD
911  * @monitor_work: Hardware monitor workitem
912  * @biu_lock: BIU (bus interface unit) lock
913  * @last_irq_cpu: Last CPU to handle a possible test interrupt.  This
914  *	field is used by efx_test_interrupts() to verify that an
915  *	interrupt has occurred.
916  * @stats_lock: Statistics update lock. Must be held when calling
917  *	efx_nic_type::{update,start,stop}_stats.
918  * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb
919  * @mc_promisc: Whether in multicast promiscuous mode when last changed
920  *
921  * This is stored in the private area of the &struct net_device.
922  */
923 struct efx_nic {
924 	/* The following fields should be written very rarely */
925 
926 	char name[IFNAMSIZ];
927 	struct list_head node;
928 	struct efx_nic *primary;
929 	struct list_head secondary_list;
930 	struct pci_dev *pci_dev;
931 	unsigned int port_num;
932 	const struct efx_nic_type *type;
933 	int legacy_irq;
934 	bool eeh_disabled_legacy_irq;
935 	struct workqueue_struct *workqueue;
936 	char workqueue_name[16];
937 	struct work_struct reset_work;
938 	resource_size_t membase_phys;
939 	void __iomem *membase;
940 
941 	enum efx_int_mode interrupt_mode;
942 	unsigned int timer_quantum_ns;
943 	bool irq_rx_adaptive;
944 	unsigned int irq_rx_moderation;
945 	u32 msg_enable;
946 
947 	enum nic_state state;
948 	unsigned long reset_pending;
949 
950 	struct efx_channel *channel[EFX_MAX_CHANNELS];
951 	struct efx_msi_context msi_context[EFX_MAX_CHANNELS];
952 	const struct efx_channel_type *
953 	extra_channel_type[EFX_MAX_EXTRA_CHANNELS];
954 
955 	unsigned rxq_entries;
956 	unsigned txq_entries;
957 	unsigned int txq_stop_thresh;
958 	unsigned int txq_wake_thresh;
959 
960 	unsigned tx_dc_base;
961 	unsigned rx_dc_base;
962 	unsigned sram_lim_qw;
963 	unsigned next_buffer_table;
964 
965 	unsigned int max_channels;
966 	unsigned int max_tx_channels;
967 	unsigned n_channels;
968 	unsigned n_rx_channels;
969 	unsigned rss_spread;
970 	unsigned tx_channel_offset;
971 	unsigned n_tx_channels;
972 	unsigned int rx_ip_align;
973 	unsigned int rx_dma_len;
974 	unsigned int rx_buffer_order;
975 	unsigned int rx_buffer_truesize;
976 	unsigned int rx_page_buf_step;
977 	unsigned int rx_bufs_per_page;
978 	unsigned int rx_pages_per_batch;
979 	unsigned int rx_prefix_size;
980 	int rx_packet_hash_offset;
981 	int rx_packet_len_offset;
982 	int rx_packet_ts_offset;
983 	u8 rx_hash_key[40];
984 	u32 rx_indir_table[128];
985 	bool rx_scatter;
986 
987 	unsigned int_error_count;
988 	unsigned long int_error_expire;
989 
990 	bool irq_soft_enabled;
991 	struct efx_buffer irq_status;
992 	unsigned irq_zero_count;
993 	unsigned irq_level;
994 	struct delayed_work selftest_work;
995 
996 #ifdef CONFIG_SFC_MTD
997 	struct list_head mtd_list;
998 #endif
999 
1000 	void *nic_data;
1001 	struct efx_mcdi_data *mcdi;
1002 
1003 	struct mutex mac_lock;
1004 	struct work_struct mac_work;
1005 	bool port_enabled;
1006 
1007 	bool mc_bist_for_other_fn;
1008 	bool port_initialized;
1009 	struct net_device *net_dev;
1010 
1011 	struct efx_buffer stats_buffer;
1012 	u64 rx_nodesc_drops_total;
1013 	u64 rx_nodesc_drops_while_down;
1014 	bool rx_nodesc_drops_prev_state;
1015 
1016 	unsigned int phy_type;
1017 	const struct efx_phy_operations *phy_op;
1018 	void *phy_data;
1019 	struct mdio_if_info mdio;
1020 	unsigned int mdio_bus;
1021 	enum efx_phy_mode phy_mode;
1022 
1023 	u32 link_advertising;
1024 	struct efx_link_state link_state;
1025 	unsigned int n_link_state_changes;
1026 
1027 	bool unicast_filter;
1028 	union efx_multicast_hash multicast_hash;
1029 	u8 wanted_fc;
1030 	unsigned fc_disable;
1031 
1032 	atomic_t rx_reset;
1033 	enum efx_loopback_mode loopback_mode;
1034 	u64 loopback_modes;
1035 
1036 	void *loopback_selftest;
1037 
1038 	struct rw_semaphore filter_sem;
1039 	spinlock_t filter_lock;
1040 	void *filter_state;
1041 #ifdef CONFIG_RFS_ACCEL
1042 	unsigned int rps_expire_channel;
1043 	unsigned int rps_expire_index;
1044 #endif
1045 
1046 	atomic_t active_queues;
1047 	atomic_t rxq_flush_pending;
1048 	atomic_t rxq_flush_outstanding;
1049 	wait_queue_head_t flush_wq;
1050 
1051 #ifdef CONFIG_SFC_SRIOV
1052 	unsigned vf_count;
1053 	unsigned vf_init_count;
1054 	unsigned vi_scale;
1055 #endif
1056 
1057 	struct efx_ptp_data *ptp_data;
1058 
1059 	char *vpd_sn;
1060 
1061 	/* The following fields may be written more often */
1062 
1063 	struct delayed_work monitor_work ____cacheline_aligned_in_smp;
1064 	spinlock_t biu_lock;
1065 	int last_irq_cpu;
1066 	spinlock_t stats_lock;
1067 	atomic_t n_rx_noskb_drops;
1068 	bool mc_promisc;
1069 };
1070 
1071 static inline int efx_dev_registered(struct efx_nic *efx)
1072 {
1073 	return efx->net_dev->reg_state == NETREG_REGISTERED;
1074 }
1075 
1076 static inline unsigned int efx_port_num(struct efx_nic *efx)
1077 {
1078 	return efx->port_num;
1079 }
1080 
1081 struct efx_mtd_partition {
1082 	struct list_head node;
1083 	struct mtd_info mtd;
1084 	const char *dev_type_name;
1085 	const char *type_name;
1086 	char name[IFNAMSIZ + 20];
1087 };
1088 
1089 /**
1090  * struct efx_nic_type - Efx device type definition
1091  * @mem_bar: Get the memory BAR
1092  * @mem_map_size: Get memory BAR mapped size
1093  * @probe: Probe the controller
1094  * @remove: Free resources allocated by probe()
1095  * @init: Initialise the controller
1096  * @dimension_resources: Dimension controller resources (buffer table,
1097  *	and VIs once the available interrupt resources are clear)
1098  * @fini: Shut down the controller
1099  * @monitor: Periodic function for polling link state and hardware monitor
1100  * @map_reset_reason: Map ethtool reset reason to a reset method
1101  * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
1102  * @reset: Reset the controller hardware and possibly the PHY.  This will
1103  *	be called while the controller is uninitialised.
1104  * @probe_port: Probe the MAC and PHY
1105  * @remove_port: Free resources allocated by probe_port()
1106  * @handle_global_event: Handle a "global" event (may be %NULL)
1107  * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1108  * @prepare_flush: Prepare the hardware for flushing the DMA queues
1109  *	(for Falcon architecture)
1110  * @finish_flush: Clean up after flushing the DMA queues (for Falcon
1111  *	architecture)
1112  * @prepare_flr: Prepare for an FLR
1113  * @finish_flr: Clean up after an FLR
1114  * @describe_stats: Describe statistics for ethtool
1115  * @update_stats: Update statistics not provided by event handling.
1116  *	Either argument may be %NULL.
1117  * @start_stats: Start the regular fetching of statistics
1118  * @pull_stats: Pull stats from the NIC and wait until they arrive.
1119  * @stop_stats: Stop the regular fetching of statistics
1120  * @set_id_led: Set state of identifying LED or revert to automatic function
1121  * @push_irq_moderation: Apply interrupt moderation value
1122  * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
1123  * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
1124  * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
1125  *	to the hardware.  Serialised by the mac_lock.
1126  * @check_mac_fault: Check MAC fault state. True if fault present.
1127  * @get_wol: Get WoL configuration from driver state
1128  * @set_wol: Push WoL configuration to the NIC
1129  * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
1130  * @test_chip: Test registers.  May use efx_farch_test_registers(), and is
1131  *	expected to reset the NIC.
1132  * @test_nvram: Test validity of NVRAM contents
1133  * @mcdi_request: Send an MCDI request with the given header and SDU.
1134  *	The SDU length may be any value from 0 up to the protocol-
1135  *	defined maximum, but its buffer will be padded to a multiple
1136  *	of 4 bytes.
1137  * @mcdi_poll_response: Test whether an MCDI response is available.
1138  * @mcdi_read_response: Read the MCDI response PDU.  The offset will
1139  *	be a multiple of 4.  The length may not be, but the buffer
1140  *	will be padded so it is safe to round up.
1141  * @mcdi_poll_reboot: Test whether the MCDI has rebooted.  If so,
1142  *	return an appropriate error code for aborting any current
1143  *	request; otherwise return 0.
1144  * @irq_enable_master: Enable IRQs on the NIC.  Each event queue must
1145  *	be separately enabled after this.
1146  * @irq_test_generate: Generate a test IRQ
1147  * @irq_disable_non_ev: Disable non-event IRQs on the NIC.  Each event
1148  *	queue must be separately disabled before this.
1149  * @irq_handle_msi: Handle MSI for a channel.  The @dev_id argument is
1150  *	a pointer to the &struct efx_msi_context for the channel.
1151  * @irq_handle_legacy: Handle legacy interrupt.  The @dev_id argument
1152  *	is a pointer to the &struct efx_nic.
1153  * @tx_probe: Allocate resources for TX queue
1154  * @tx_init: Initialise TX queue on the NIC
1155  * @tx_remove: Free resources for TX queue
1156  * @tx_write: Write TX descriptors and doorbell
1157  * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC
1158  * @rx_probe: Allocate resources for RX queue
1159  * @rx_init: Initialise RX queue on the NIC
1160  * @rx_remove: Free resources for RX queue
1161  * @rx_write: Write RX descriptors and doorbell
1162  * @rx_defer_refill: Generate a refill reminder event
1163  * @ev_probe: Allocate resources for event queue
1164  * @ev_init: Initialise event queue on the NIC
1165  * @ev_fini: Deinitialise event queue on the NIC
1166  * @ev_remove: Free resources for event queue
1167  * @ev_process: Process events for a queue, up to the given NAPI quota
1168  * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
1169  * @ev_test_generate: Generate a test event
1170  * @filter_table_probe: Probe filter capabilities and set up filter software state
1171  * @filter_table_restore: Restore filters removed from hardware
1172  * @filter_table_remove: Remove filters from hardware and tear down software state
1173  * @filter_update_rx_scatter: Update filters after change to rx scatter setting
1174  * @filter_insert: add or replace a filter
1175  * @filter_remove_safe: remove a filter by ID, carefully
1176  * @filter_get_safe: retrieve a filter by ID, carefully
1177  * @filter_clear_rx: Remove all RX filters whose priority is less than or
1178  *	equal to the given priority and is not %EFX_FILTER_PRI_AUTO
1179  * @filter_count_rx_used: Get the number of filters in use at a given priority
1180  * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1
1181  * @filter_get_rx_ids: Get list of RX filters at a given priority
1182  * @filter_rfs_insert: Add or replace a filter for RFS.  This must be
1183  *	atomic.  The hardware change may be asynchronous but should
1184  *	not be delayed for long.  It may fail if this can't be done
1185  *	atomically.
1186  * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS.
1187  *	This must check whether the specified table entry is used by RFS
1188  *	and that rps_may_expire_flow() returns true for it.
1189  * @mtd_probe: Probe and add MTD partitions associated with this net device,
1190  *	 using efx_mtd_add()
1191  * @mtd_rename: Set an MTD partition name using the net device name
1192  * @mtd_read: Read from an MTD partition
1193  * @mtd_erase: Erase part of an MTD partition
1194  * @mtd_write: Write to an MTD partition
1195  * @mtd_sync: Wait for write-back to complete on MTD partition.  This
1196  *	also notifies the driver that a writer has finished using this
1197  *	partition.
1198  * @ptp_write_host_time: Send host time to MC as part of sync protocol
1199  * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX
1200  *	timestamping, possibly only temporarily for the purposes of a reset.
1201  * @ptp_set_ts_config: Set hardware timestamp configuration.  The flags
1202  *	and tx_type will already have been validated but this operation
1203  *	must validate and update rx_filter.
1204  * @set_mac_address: Set the MAC address of the device
1205  * @revision: Hardware architecture revision
1206  * @txd_ptr_tbl_base: TX descriptor ring base address
1207  * @rxd_ptr_tbl_base: RX descriptor ring base address
1208  * @buf_tbl_base: Buffer table base address
1209  * @evq_ptr_tbl_base: Event queue pointer table base address
1210  * @evq_rptr_tbl_base: Event queue read-pointer table base address
1211  * @max_dma_mask: Maximum possible DMA mask
1212  * @rx_prefix_size: Size of RX prefix before packet data
1213  * @rx_hash_offset: Offset of RX flow hash within prefix
1214  * @rx_ts_offset: Offset of timestamp within prefix
1215  * @rx_buffer_padding: Size of padding at end of RX packet
1216  * @can_rx_scatter: NIC is able to scatter packets to multiple buffers
1217  * @always_rx_scatter: NIC will always scatter packets to multiple buffers
1218  * @max_interrupt_mode: Highest capability interrupt mode supported
1219  *	from &enum efx_init_mode.
1220  * @timer_period_max: Maximum period of interrupt timer (in ticks)
1221  * @offload_features: net_device feature flags for protocol offload
1222  *	features implemented in hardware
1223  * @mcdi_max_ver: Maximum MCDI version supported
1224  * @hwtstamp_filters: Mask of hardware timestamp filter types supported
1225  */
1226 struct efx_nic_type {
1227 	bool is_vf;
1228 	unsigned int mem_bar;
1229 	unsigned int (*mem_map_size)(struct efx_nic *efx);
1230 	int (*probe)(struct efx_nic *efx);
1231 	void (*remove)(struct efx_nic *efx);
1232 	int (*init)(struct efx_nic *efx);
1233 	int (*dimension_resources)(struct efx_nic *efx);
1234 	void (*fini)(struct efx_nic *efx);
1235 	void (*monitor)(struct efx_nic *efx);
1236 	enum reset_type (*map_reset_reason)(enum reset_type reason);
1237 	int (*map_reset_flags)(u32 *flags);
1238 	int (*reset)(struct efx_nic *efx, enum reset_type method);
1239 	int (*probe_port)(struct efx_nic *efx);
1240 	void (*remove_port)(struct efx_nic *efx);
1241 	bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
1242 	int (*fini_dmaq)(struct efx_nic *efx);
1243 	void (*prepare_flush)(struct efx_nic *efx);
1244 	void (*finish_flush)(struct efx_nic *efx);
1245 	void (*prepare_flr)(struct efx_nic *efx);
1246 	void (*finish_flr)(struct efx_nic *efx);
1247 	size_t (*describe_stats)(struct efx_nic *efx, u8 *names);
1248 	size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats,
1249 			       struct rtnl_link_stats64 *core_stats);
1250 	void (*start_stats)(struct efx_nic *efx);
1251 	void (*pull_stats)(struct efx_nic *efx);
1252 	void (*stop_stats)(struct efx_nic *efx);
1253 	void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
1254 	void (*push_irq_moderation)(struct efx_channel *channel);
1255 	int (*reconfigure_port)(struct efx_nic *efx);
1256 	void (*prepare_enable_fc_tx)(struct efx_nic *efx);
1257 	int (*reconfigure_mac)(struct efx_nic *efx);
1258 	bool (*check_mac_fault)(struct efx_nic *efx);
1259 	void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
1260 	int (*set_wol)(struct efx_nic *efx, u32 type);
1261 	void (*resume_wol)(struct efx_nic *efx);
1262 	int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests);
1263 	int (*test_nvram)(struct efx_nic *efx);
1264 	void (*mcdi_request)(struct efx_nic *efx,
1265 			     const efx_dword_t *hdr, size_t hdr_len,
1266 			     const efx_dword_t *sdu, size_t sdu_len);
1267 	bool (*mcdi_poll_response)(struct efx_nic *efx);
1268 	void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu,
1269 				   size_t pdu_offset, size_t pdu_len);
1270 	int (*mcdi_poll_reboot)(struct efx_nic *efx);
1271 	void (*mcdi_reboot_detected)(struct efx_nic *efx);
1272 	void (*irq_enable_master)(struct efx_nic *efx);
1273 	void (*irq_test_generate)(struct efx_nic *efx);
1274 	void (*irq_disable_non_ev)(struct efx_nic *efx);
1275 	irqreturn_t (*irq_handle_msi)(int irq, void *dev_id);
1276 	irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id);
1277 	int (*tx_probe)(struct efx_tx_queue *tx_queue);
1278 	void (*tx_init)(struct efx_tx_queue *tx_queue);
1279 	void (*tx_remove)(struct efx_tx_queue *tx_queue);
1280 	void (*tx_write)(struct efx_tx_queue *tx_queue);
1281 	int (*rx_push_rss_config)(struct efx_nic *efx, bool user,
1282 				  const u32 *rx_indir_table);
1283 	int (*rx_probe)(struct efx_rx_queue *rx_queue);
1284 	void (*rx_init)(struct efx_rx_queue *rx_queue);
1285 	void (*rx_remove)(struct efx_rx_queue *rx_queue);
1286 	void (*rx_write)(struct efx_rx_queue *rx_queue);
1287 	void (*rx_defer_refill)(struct efx_rx_queue *rx_queue);
1288 	int (*ev_probe)(struct efx_channel *channel);
1289 	int (*ev_init)(struct efx_channel *channel);
1290 	void (*ev_fini)(struct efx_channel *channel);
1291 	void (*ev_remove)(struct efx_channel *channel);
1292 	int (*ev_process)(struct efx_channel *channel, int quota);
1293 	void (*ev_read_ack)(struct efx_channel *channel);
1294 	void (*ev_test_generate)(struct efx_channel *channel);
1295 	int (*filter_table_probe)(struct efx_nic *efx);
1296 	void (*filter_table_restore)(struct efx_nic *efx);
1297 	void (*filter_table_remove)(struct efx_nic *efx);
1298 	void (*filter_update_rx_scatter)(struct efx_nic *efx);
1299 	s32 (*filter_insert)(struct efx_nic *efx,
1300 			     struct efx_filter_spec *spec, bool replace);
1301 	int (*filter_remove_safe)(struct efx_nic *efx,
1302 				  enum efx_filter_priority priority,
1303 				  u32 filter_id);
1304 	int (*filter_get_safe)(struct efx_nic *efx,
1305 			       enum efx_filter_priority priority,
1306 			       u32 filter_id, struct efx_filter_spec *);
1307 	int (*filter_clear_rx)(struct efx_nic *efx,
1308 			       enum efx_filter_priority priority);
1309 	u32 (*filter_count_rx_used)(struct efx_nic *efx,
1310 				    enum efx_filter_priority priority);
1311 	u32 (*filter_get_rx_id_limit)(struct efx_nic *efx);
1312 	s32 (*filter_get_rx_ids)(struct efx_nic *efx,
1313 				 enum efx_filter_priority priority,
1314 				 u32 *buf, u32 size);
1315 #ifdef CONFIG_RFS_ACCEL
1316 	s32 (*filter_rfs_insert)(struct efx_nic *efx,
1317 				 struct efx_filter_spec *spec);
1318 	bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id,
1319 				      unsigned int index);
1320 #endif
1321 #ifdef CONFIG_SFC_MTD
1322 	int (*mtd_probe)(struct efx_nic *efx);
1323 	void (*mtd_rename)(struct efx_mtd_partition *part);
1324 	int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len,
1325 			size_t *retlen, u8 *buffer);
1326 	int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len);
1327 	int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len,
1328 			 size_t *retlen, const u8 *buffer);
1329 	int (*mtd_sync)(struct mtd_info *mtd);
1330 #endif
1331 	void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time);
1332 	int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp);
1333 	int (*ptp_set_ts_config)(struct efx_nic *efx,
1334 				 struct hwtstamp_config *init);
1335 	int (*sriov_configure)(struct efx_nic *efx, int num_vfs);
1336 	int (*sriov_init)(struct efx_nic *efx);
1337 	void (*sriov_fini)(struct efx_nic *efx);
1338 	bool (*sriov_wanted)(struct efx_nic *efx);
1339 	void (*sriov_reset)(struct efx_nic *efx);
1340 	void (*sriov_flr)(struct efx_nic *efx, unsigned vf_i);
1341 	int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, u8 *mac);
1342 	int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan,
1343 				 u8 qos);
1344 	int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i,
1345 				     bool spoofchk);
1346 	int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i,
1347 				   struct ifla_vf_info *ivi);
1348 	int (*sriov_set_vf_link_state)(struct efx_nic *efx, int vf_i,
1349 				       int link_state);
1350 	int (*sriov_get_phys_port_id)(struct efx_nic *efx,
1351 				      struct netdev_phys_item_id *ppid);
1352 	int (*vswitching_probe)(struct efx_nic *efx);
1353 	int (*vswitching_restore)(struct efx_nic *efx);
1354 	void (*vswitching_remove)(struct efx_nic *efx);
1355 	int (*get_mac_address)(struct efx_nic *efx, unsigned char *perm_addr);
1356 	int (*set_mac_address)(struct efx_nic *efx);
1357 
1358 	int revision;
1359 	unsigned int txd_ptr_tbl_base;
1360 	unsigned int rxd_ptr_tbl_base;
1361 	unsigned int buf_tbl_base;
1362 	unsigned int evq_ptr_tbl_base;
1363 	unsigned int evq_rptr_tbl_base;
1364 	u64 max_dma_mask;
1365 	unsigned int rx_prefix_size;
1366 	unsigned int rx_hash_offset;
1367 	unsigned int rx_ts_offset;
1368 	unsigned int rx_buffer_padding;
1369 	bool can_rx_scatter;
1370 	bool always_rx_scatter;
1371 	unsigned int max_interrupt_mode;
1372 	unsigned int timer_period_max;
1373 	netdev_features_t offload_features;
1374 	int mcdi_max_ver;
1375 	unsigned int max_rx_ip_filters;
1376 	u32 hwtstamp_filters;
1377 };
1378 
1379 /**************************************************************************
1380  *
1381  * Prototypes and inline functions
1382  *
1383  *************************************************************************/
1384 
1385 static inline struct efx_channel *
1386 efx_get_channel(struct efx_nic *efx, unsigned index)
1387 {
1388 	EFX_BUG_ON_PARANOID(index >= efx->n_channels);
1389 	return efx->channel[index];
1390 }
1391 
1392 /* Iterate over all used channels */
1393 #define efx_for_each_channel(_channel, _efx)				\
1394 	for (_channel = (_efx)->channel[0];				\
1395 	     _channel;							\
1396 	     _channel = (_channel->channel + 1 < (_efx)->n_channels) ?	\
1397 		     (_efx)->channel[_channel->channel + 1] : NULL)
1398 
1399 /* Iterate over all used channels in reverse */
1400 #define efx_for_each_channel_rev(_channel, _efx)			\
1401 	for (_channel = (_efx)->channel[(_efx)->n_channels - 1];	\
1402 	     _channel;							\
1403 	     _channel = _channel->channel ?				\
1404 		     (_efx)->channel[_channel->channel - 1] : NULL)
1405 
1406 static inline struct efx_tx_queue *
1407 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type)
1408 {
1409 	EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels ||
1410 			    type >= EFX_TXQ_TYPES);
1411 	return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type];
1412 }
1413 
1414 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel)
1415 {
1416 	return channel->channel - channel->efx->tx_channel_offset <
1417 		channel->efx->n_tx_channels;
1418 }
1419 
1420 static inline struct efx_tx_queue *
1421 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type)
1422 {
1423 	EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) ||
1424 			    type >= EFX_TXQ_TYPES);
1425 	return &channel->tx_queue[type];
1426 }
1427 
1428 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue)
1429 {
1430 	return !(tx_queue->efx->net_dev->num_tc < 2 &&
1431 		 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI);
1432 }
1433 
1434 /* Iterate over all TX queues belonging to a channel */
1435 #define efx_for_each_channel_tx_queue(_tx_queue, _channel)		\
1436 	if (!efx_channel_has_tx_queues(_channel))			\
1437 		;							\
1438 	else								\
1439 		for (_tx_queue = (_channel)->tx_queue;			\
1440 		     _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \
1441 			     efx_tx_queue_used(_tx_queue);		\
1442 		     _tx_queue++)
1443 
1444 /* Iterate over all possible TX queues belonging to a channel */
1445 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel)	\
1446 	if (!efx_channel_has_tx_queues(_channel))			\
1447 		;							\
1448 	else								\
1449 		for (_tx_queue = (_channel)->tx_queue;			\
1450 		     _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES;	\
1451 		     _tx_queue++)
1452 
1453 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel)
1454 {
1455 	return channel->rx_queue.core_index >= 0;
1456 }
1457 
1458 static inline struct efx_rx_queue *
1459 efx_channel_get_rx_queue(struct efx_channel *channel)
1460 {
1461 	EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel));
1462 	return &channel->rx_queue;
1463 }
1464 
1465 /* Iterate over all RX queues belonging to a channel */
1466 #define efx_for_each_channel_rx_queue(_rx_queue, _channel)		\
1467 	if (!efx_channel_has_rx_queue(_channel))			\
1468 		;							\
1469 	else								\
1470 		for (_rx_queue = &(_channel)->rx_queue;			\
1471 		     _rx_queue;						\
1472 		     _rx_queue = NULL)
1473 
1474 static inline struct efx_channel *
1475 efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
1476 {
1477 	return container_of(rx_queue, struct efx_channel, rx_queue);
1478 }
1479 
1480 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
1481 {
1482 	return efx_rx_queue_channel(rx_queue)->channel;
1483 }
1484 
1485 /* Returns a pointer to the specified receive buffer in the RX
1486  * descriptor queue.
1487  */
1488 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
1489 						  unsigned int index)
1490 {
1491 	return &rx_queue->buffer[index];
1492 }
1493 
1494 /**
1495  * EFX_MAX_FRAME_LEN - calculate maximum frame length
1496  *
1497  * This calculates the maximum frame length that will be used for a
1498  * given MTU.  The frame length will be equal to the MTU plus a
1499  * constant amount of header space and padding.  This is the quantity
1500  * that the net driver will program into the MAC as the maximum frame
1501  * length.
1502  *
1503  * The 10G MAC requires 8-byte alignment on the frame
1504  * length, so we round up to the nearest 8.
1505  *
1506  * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1507  * XGMII cycle).  If the frame length reaches the maximum value in the
1508  * same cycle, the XMAC can miss the IPG altogether.  We work around
1509  * this by adding a further 16 bytes.
1510  */
1511 #define EFX_FRAME_PAD	16
1512 #define EFX_MAX_FRAME_LEN(mtu) \
1513 	(ALIGN(((mtu) + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN + EFX_FRAME_PAD), 8))
1514 
1515 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb)
1516 {
1517 	return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
1518 }
1519 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb)
1520 {
1521 	skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1522 }
1523 
1524 #endif /* EFX_NET_DRIVER_H */
1525