1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2005-2006 Fen Systems Ltd. 5 * Copyright 2005-2013 Solarflare Communications Inc. 6 */ 7 8 /* Common definitions for all Efx net driver code */ 9 10 #ifndef EFX_NET_DRIVER_H 11 #define EFX_NET_DRIVER_H 12 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool.h> 16 #include <linux/if_vlan.h> 17 #include <linux/timer.h> 18 #include <linux/mdio.h> 19 #include <linux/list.h> 20 #include <linux/pci.h> 21 #include <linux/device.h> 22 #include <linux/highmem.h> 23 #include <linux/workqueue.h> 24 #include <linux/mutex.h> 25 #include <linux/rwsem.h> 26 #include <linux/vmalloc.h> 27 #include <linux/mtd/mtd.h> 28 #include <net/busy_poll.h> 29 #include <net/xdp.h> 30 31 #include "enum.h" 32 #include "bitfield.h" 33 #include "filter.h" 34 35 /************************************************************************** 36 * 37 * Build definitions 38 * 39 **************************************************************************/ 40 41 #ifdef DEBUG 42 #define EFX_WARN_ON_ONCE_PARANOID(x) WARN_ON_ONCE(x) 43 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) 44 #else 45 #define EFX_WARN_ON_ONCE_PARANOID(x) do {} while (0) 46 #define EFX_WARN_ON_PARANOID(x) do {} while (0) 47 #endif 48 49 /************************************************************************** 50 * 51 * Efx data structures 52 * 53 **************************************************************************/ 54 55 #define EFX_MAX_CHANNELS 32U 56 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS 57 #define EFX_EXTRA_CHANNEL_IOV 0 58 #define EFX_EXTRA_CHANNEL_PTP 1 59 #define EFX_MAX_EXTRA_CHANNELS 2U 60 61 /* Checksum generation is a per-queue option in hardware, so each 62 * queue visible to the networking core is backed by two hardware TX 63 * queues. */ 64 #define EFX_MAX_TX_TC 2 65 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS) 66 #define EFX_TXQ_TYPE_OUTER_CSUM 1 /* Outer checksum offload */ 67 #define EFX_TXQ_TYPE_INNER_CSUM 2 /* Inner checksum offload */ 68 #define EFX_TXQ_TYPE_HIGHPRI 4 /* High-priority (for TC) */ 69 #define EFX_TXQ_TYPES 8 70 /* HIGHPRI is Siena-only, and INNER_CSUM is EF10, so no need for both */ 71 #define EFX_MAX_TXQ_PER_CHANNEL 4 72 #define EFX_MAX_TX_QUEUES (EFX_MAX_TXQ_PER_CHANNEL * EFX_MAX_CHANNELS) 73 74 /* Maximum possible MTU the driver supports */ 75 #define EFX_MAX_MTU (9 * 1024) 76 77 /* Minimum MTU, from RFC791 (IP) */ 78 #define EFX_MIN_MTU 68 79 80 /* Maximum total header length for TSOv2 */ 81 #define EFX_TSO2_MAX_HDRLEN 208 82 83 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page, 84 * and should be a multiple of the cache line size. 85 */ 86 #define EFX_RX_USR_BUF_SIZE (2048 - 256) 87 88 /* If possible, we should ensure cache line alignment at start and end 89 * of every buffer. Otherwise, we just need to ensure 4-byte 90 * alignment of the network header. 91 */ 92 #if NET_IP_ALIGN == 0 93 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES 94 #else 95 #define EFX_RX_BUF_ALIGNMENT 4 96 #endif 97 98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and 99 * still fit two standard MTU size packets into a single 4K page. 100 */ 101 #define EFX_XDP_HEADROOM 128 102 #define EFX_XDP_TAILROOM SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) 103 104 /* Forward declare Precision Time Protocol (PTP) support structure. */ 105 struct efx_ptp_data; 106 struct hwtstamp_config; 107 108 struct efx_self_tests; 109 110 /** 111 * struct efx_buffer - A general-purpose DMA buffer 112 * @addr: host base address of the buffer 113 * @dma_addr: DMA base address of the buffer 114 * @len: Buffer length, in bytes 115 * 116 * The NIC uses these buffers for its interrupt status registers and 117 * MAC stats dumps. 118 */ 119 struct efx_buffer { 120 void *addr; 121 dma_addr_t dma_addr; 122 unsigned int len; 123 }; 124 125 /** 126 * struct efx_special_buffer - DMA buffer entered into buffer table 127 * @buf: Standard &struct efx_buffer 128 * @index: Buffer index within controller;s buffer table 129 * @entries: Number of buffer table entries 130 * 131 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE. 132 * Event and descriptor rings are addressed via one or more buffer 133 * table entries (and so can be physically non-contiguous, although we 134 * currently do not take advantage of that). On Falcon and Siena we 135 * have to take care of allocating and initialising the entries 136 * ourselves. On later hardware this is managed by the firmware and 137 * @index and @entries are left as 0. 138 */ 139 struct efx_special_buffer { 140 struct efx_buffer buf; 141 unsigned int index; 142 unsigned int entries; 143 }; 144 145 /** 146 * struct efx_tx_buffer - buffer state for a TX descriptor 147 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be 148 * freed when descriptor completes 149 * @xdpf: When @flags & %EFX_TX_BUF_XDP, the XDP frame information; its @data 150 * member is the associated buffer to drop a page reference on. 151 * @option: When @flags & %EFX_TX_BUF_OPTION, an EF10-specific option 152 * descriptor. 153 * @dma_addr: DMA address of the fragment. 154 * @flags: Flags for allocation and DMA mapping type 155 * @len: Length of this fragment. 156 * This field is zero when the queue slot is empty. 157 * @unmap_len: Length of this fragment to unmap 158 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping. 159 * Only valid if @unmap_len != 0. 160 */ 161 struct efx_tx_buffer { 162 union { 163 const struct sk_buff *skb; 164 struct xdp_frame *xdpf; 165 }; 166 union { 167 efx_qword_t option; /* EF10 */ 168 dma_addr_t dma_addr; 169 }; 170 unsigned short flags; 171 unsigned short len; 172 unsigned short unmap_len; 173 unsigned short dma_offset; 174 }; 175 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */ 176 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */ 177 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */ 178 #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */ 179 #define EFX_TX_BUF_XDP 0x20 /* buffer was sent with XDP */ 180 #define EFX_TX_BUF_TSO_V3 0x40 /* empty buffer for a TSO_V3 descriptor */ 181 182 /** 183 * struct efx_tx_queue - An Efx TX queue 184 * 185 * This is a ring buffer of TX fragments. 186 * Since the TX completion path always executes on the same 187 * CPU and the xmit path can operate on different CPUs, 188 * performance is increased by ensuring that the completion 189 * path and the xmit path operate on different cache lines. 190 * This is particularly important if the xmit path is always 191 * executing on one CPU which is different from the completion 192 * path. There is also a cache line for members which are 193 * read but not written on the fast path. 194 * 195 * @efx: The associated Efx NIC 196 * @queue: DMA queue number 197 * @label: Label for TX completion events. 198 * Is our index within @channel->tx_queue array. 199 * @type: configuration type of this TX queue. A bitmask of %EFX_TXQ_TYPE_* flags. 200 * @tso_version: Version of TSO in use for this queue. 201 * @tso_encap: Is encapsulated TSO supported? Supported in TSOv2 on 8000 series. 202 * @channel: The associated channel 203 * @core_txq: The networking core TX queue structure 204 * @buffer: The software buffer ring 205 * @cb_page: Array of pages of copy buffers. Carved up according to 206 * %EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks. 207 * @txd: The hardware descriptor ring 208 * @ptr_mask: The size of the ring minus 1. 209 * @piobuf: PIO buffer region for this TX queue (shared with its partner). 210 * Size of the region is efx_piobuf_size. 211 * @piobuf_offset: Buffer offset to be specified in PIO descriptors 212 * @initialised: Has hardware queue been initialised? 213 * @timestamping: Is timestamping enabled for this channel? 214 * @xdp_tx: Is this an XDP tx queue? 215 * @read_count: Current read pointer. 216 * This is the number of buffers that have been removed from both rings. 217 * @old_write_count: The value of @write_count when last checked. 218 * This is here for performance reasons. The xmit path will 219 * only get the up-to-date value of @write_count if this 220 * variable indicates that the queue is empty. This is to 221 * avoid cache-line ping-pong between the xmit path and the 222 * completion path. 223 * @merge_events: Number of TX merged completion events 224 * @completed_timestamp_major: Top part of the most recent tx timestamp. 225 * @completed_timestamp_minor: Low part of the most recent tx timestamp. 226 * @insert_count: Current insert pointer 227 * This is the number of buffers that have been added to the 228 * software ring. 229 * @write_count: Current write pointer 230 * This is the number of buffers that have been added to the 231 * hardware ring. 232 * @packet_write_count: Completable write pointer 233 * This is the write pointer of the last packet written. 234 * Normally this will equal @write_count, but as option descriptors 235 * don't produce completion events, they won't update this. 236 * Filled in iff @efx->type->option_descriptors; only used for PIO. 237 * Thus, this is written and used on EF10, and neither on farch. 238 * @old_read_count: The value of read_count when last checked. 239 * This is here for performance reasons. The xmit path will 240 * only get the up-to-date value of read_count if this 241 * variable indicates that the queue is full. This is to 242 * avoid cache-line ping-pong between the xmit path and the 243 * completion path. 244 * @tso_bursts: Number of times TSO xmit invoked by kernel 245 * @tso_long_headers: Number of packets with headers too long for standard 246 * blocks 247 * @tso_packets: Number of packets via the TSO xmit path 248 * @tso_fallbacks: Number of times TSO fallback used 249 * @pushes: Number of times the TX push feature has been used 250 * @pio_packets: Number of times the TX PIO feature has been used 251 * @xmit_pending: Are any packets waiting to be pushed to the NIC 252 * @cb_packets: Number of times the TX copybreak feature has been used 253 * @notify_count: Count of notified descriptors to the NIC 254 * @empty_read_count: If the completion path has seen the queue as empty 255 * and the transmission path has not yet checked this, the value of 256 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0. 257 */ 258 struct efx_tx_queue { 259 /* Members which don't change on the fast path */ 260 struct efx_nic *efx ____cacheline_aligned_in_smp; 261 unsigned int queue; 262 unsigned int label; 263 unsigned int type; 264 unsigned int tso_version; 265 bool tso_encap; 266 struct efx_channel *channel; 267 struct netdev_queue *core_txq; 268 struct efx_tx_buffer *buffer; 269 struct efx_buffer *cb_page; 270 struct efx_special_buffer txd; 271 unsigned int ptr_mask; 272 void __iomem *piobuf; 273 unsigned int piobuf_offset; 274 bool initialised; 275 bool timestamping; 276 bool xdp_tx; 277 278 /* Members used mainly on the completion path */ 279 unsigned int read_count ____cacheline_aligned_in_smp; 280 unsigned int old_write_count; 281 unsigned int merge_events; 282 unsigned int bytes_compl; 283 unsigned int pkts_compl; 284 u32 completed_timestamp_major; 285 u32 completed_timestamp_minor; 286 287 /* Members used only on the xmit path */ 288 unsigned int insert_count ____cacheline_aligned_in_smp; 289 unsigned int write_count; 290 unsigned int packet_write_count; 291 unsigned int old_read_count; 292 unsigned int tso_bursts; 293 unsigned int tso_long_headers; 294 unsigned int tso_packets; 295 unsigned int tso_fallbacks; 296 unsigned int pushes; 297 unsigned int pio_packets; 298 bool xmit_pending; 299 unsigned int cb_packets; 300 unsigned int notify_count; 301 /* Statistics to supplement MAC stats */ 302 unsigned long tx_packets; 303 304 /* Members shared between paths and sometimes updated */ 305 unsigned int empty_read_count ____cacheline_aligned_in_smp; 306 #define EFX_EMPTY_COUNT_VALID 0x80000000 307 atomic_t flush_outstanding; 308 }; 309 310 #define EFX_TX_CB_ORDER 7 311 #define EFX_TX_CB_SIZE (1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN 312 313 /** 314 * struct efx_rx_buffer - An Efx RX data buffer 315 * @dma_addr: DMA base address of the buffer 316 * @page: The associated page buffer. 317 * Will be %NULL if the buffer slot is currently free. 318 * @page_offset: If pending: offset in @page of DMA base address. 319 * If completed: offset in @page of Ethernet header. 320 * @len: If pending: length for DMA descriptor. 321 * If completed: received length, excluding hash prefix. 322 * @flags: Flags for buffer and packet state. These are only set on the 323 * first buffer of a scattered packet. 324 */ 325 struct efx_rx_buffer { 326 dma_addr_t dma_addr; 327 struct page *page; 328 u16 page_offset; 329 u16 len; 330 u16 flags; 331 }; 332 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001 333 #define EFX_RX_PKT_CSUMMED 0x0002 334 #define EFX_RX_PKT_DISCARD 0x0004 335 #define EFX_RX_PKT_TCP 0x0040 336 #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */ 337 #define EFX_RX_PKT_CSUM_LEVEL 0x0200 338 339 /** 340 * struct efx_rx_page_state - Page-based rx buffer state 341 * 342 * Inserted at the start of every page allocated for receive buffers. 343 * Used to facilitate sharing dma mappings between recycled rx buffers 344 * and those passed up to the kernel. 345 * 346 * @dma_addr: The dma address of this page. 347 */ 348 struct efx_rx_page_state { 349 dma_addr_t dma_addr; 350 351 unsigned int __pad[] ____cacheline_aligned; 352 }; 353 354 /** 355 * struct efx_rx_queue - An Efx RX queue 356 * @efx: The associated Efx NIC 357 * @core_index: Index of network core RX queue. Will be >= 0 iff this 358 * is associated with a real RX queue. 359 * @buffer: The software buffer ring 360 * @rxd: The hardware descriptor ring 361 * @ptr_mask: The size of the ring minus 1. 362 * @refill_enabled: Enable refill whenever fill level is low 363 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as 364 * @rxq_flush_pending. 365 * @added_count: Number of buffers added to the receive queue. 366 * @notified_count: Number of buffers given to NIC (<= @added_count). 367 * @removed_count: Number of buffers removed from the receive queue. 368 * @scatter_n: Used by NIC specific receive code. 369 * @scatter_len: Used by NIC specific receive code. 370 * @page_ring: The ring to store DMA mapped pages for reuse. 371 * @page_add: Counter to calculate the write pointer for the recycle ring. 372 * @page_remove: Counter to calculate the read pointer for the recycle ring. 373 * @page_recycle_count: The number of pages that have been recycled. 374 * @page_recycle_failed: The number of pages that couldn't be recycled because 375 * the kernel still held a reference to them. 376 * @page_recycle_full: The number of pages that were released because the 377 * recycle ring was full. 378 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1. 379 * @max_fill: RX descriptor maximum fill level (<= ring size) 380 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill 381 * (<= @max_fill) 382 * @min_fill: RX descriptor minimum non-zero fill level. 383 * This records the minimum fill level observed when a ring 384 * refill was triggered. 385 * @recycle_count: RX buffer recycle counter. 386 * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). 387 * @xdp_rxq_info: XDP specific RX queue information. 388 * @xdp_rxq_info_valid: Is xdp_rxq_info valid data?. 389 */ 390 struct efx_rx_queue { 391 struct efx_nic *efx; 392 int core_index; 393 struct efx_rx_buffer *buffer; 394 struct efx_special_buffer rxd; 395 unsigned int ptr_mask; 396 bool refill_enabled; 397 bool flush_pending; 398 399 unsigned int added_count; 400 unsigned int notified_count; 401 unsigned int removed_count; 402 unsigned int scatter_n; 403 unsigned int scatter_len; 404 struct page **page_ring; 405 unsigned int page_add; 406 unsigned int page_remove; 407 unsigned int page_recycle_count; 408 unsigned int page_recycle_failed; 409 unsigned int page_recycle_full; 410 unsigned int page_ptr_mask; 411 unsigned int max_fill; 412 unsigned int fast_fill_trigger; 413 unsigned int min_fill; 414 unsigned int min_overfill; 415 unsigned int recycle_count; 416 struct timer_list slow_fill; 417 unsigned int slow_fill_count; 418 /* Statistics to supplement MAC stats */ 419 unsigned long rx_packets; 420 struct xdp_rxq_info xdp_rxq_info; 421 bool xdp_rxq_info_valid; 422 }; 423 424 enum efx_sync_events_state { 425 SYNC_EVENTS_DISABLED = 0, 426 SYNC_EVENTS_QUIESCENT, 427 SYNC_EVENTS_REQUESTED, 428 SYNC_EVENTS_VALID, 429 }; 430 431 /** 432 * struct efx_channel - An Efx channel 433 * 434 * A channel comprises an event queue, at least one TX queue, at least 435 * one RX queue, and an associated tasklet for processing the event 436 * queue. 437 * 438 * @efx: Associated Efx NIC 439 * @channel: Channel instance number 440 * @type: Channel type definition 441 * @eventq_init: Event queue initialised flag 442 * @enabled: Channel enabled indicator 443 * @irq: IRQ number (MSI and MSI-X only) 444 * @irq_moderation_us: IRQ moderation value (in microseconds) 445 * @napi_dev: Net device used with NAPI 446 * @napi_str: NAPI control structure 447 * @state: state for NAPI vs busy polling 448 * @state_lock: lock protecting @state 449 * @eventq: Event queue buffer 450 * @eventq_mask: Event queue pointer mask 451 * @eventq_read_ptr: Event queue read pointer 452 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel 453 * @irq_count: Number of IRQs since last adaptive moderation decision 454 * @irq_mod_score: IRQ moderation score 455 * @rfs_filter_count: number of accelerated RFS filters currently in place; 456 * equals the count of @rps_flow_id slots filled 457 * @rfs_last_expiry: value of jiffies last time some accelerated RFS filters 458 * were checked for expiry 459 * @rfs_expire_index: next accelerated RFS filter ID to check for expiry 460 * @n_rfs_succeeded: number of successful accelerated RFS filter insertions 461 * @n_rfs_failed: number of failed accelerated RFS filter insertions 462 * @filter_work: Work item for efx_filter_rfs_expire() 463 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS, 464 * indexed by filter ID 465 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors 466 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors 467 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors 468 * @n_rx_mcast_mismatch: Count of unmatched multicast frames 469 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors 470 * @n_rx_overlength: Count of RX_OVERLENGTH errors 471 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun 472 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to 473 * lack of descriptors 474 * @n_rx_merge_events: Number of RX merged completion events 475 * @n_rx_merge_packets: Number of RX packets completed by merged events 476 * @n_rx_xdp_drops: Count of RX packets intentionally dropped due to XDP 477 * @n_rx_xdp_bad_drops: Count of RX packets dropped due to XDP errors 478 * @n_rx_xdp_tx: Count of RX packets retransmitted due to XDP 479 * @n_rx_xdp_redirect: Count of RX packets redirected to a different NIC by XDP 480 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by 481 * __efx_rx_packet(), or zero if there is none 482 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered 483 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0 484 * @rx_list: list of SKBs from current RX, awaiting processing 485 * @rx_queue: RX queue for this channel 486 * @tx_queue: TX queues for this channel 487 * @tx_queue_by_type: pointers into @tx_queue, or %NULL, indexed by txq type 488 * @sync_events_state: Current state of sync events on this channel 489 * @sync_timestamp_major: Major part of the last ptp sync event 490 * @sync_timestamp_minor: Minor part of the last ptp sync event 491 */ 492 struct efx_channel { 493 struct efx_nic *efx; 494 int channel; 495 const struct efx_channel_type *type; 496 bool eventq_init; 497 bool enabled; 498 int irq; 499 unsigned int irq_moderation_us; 500 struct net_device *napi_dev; 501 struct napi_struct napi_str; 502 #ifdef CONFIG_NET_RX_BUSY_POLL 503 unsigned long busy_poll_state; 504 #endif 505 struct efx_special_buffer eventq; 506 unsigned int eventq_mask; 507 unsigned int eventq_read_ptr; 508 int event_test_cpu; 509 510 unsigned int irq_count; 511 unsigned int irq_mod_score; 512 #ifdef CONFIG_RFS_ACCEL 513 unsigned int rfs_filter_count; 514 unsigned int rfs_last_expiry; 515 unsigned int rfs_expire_index; 516 unsigned int n_rfs_succeeded; 517 unsigned int n_rfs_failed; 518 struct delayed_work filter_work; 519 #define RPS_FLOW_ID_INVALID 0xFFFFFFFF 520 u32 *rps_flow_id; 521 #endif 522 523 unsigned int n_rx_tobe_disc; 524 unsigned int n_rx_ip_hdr_chksum_err; 525 unsigned int n_rx_tcp_udp_chksum_err; 526 unsigned int n_rx_outer_ip_hdr_chksum_err; 527 unsigned int n_rx_outer_tcp_udp_chksum_err; 528 unsigned int n_rx_inner_ip_hdr_chksum_err; 529 unsigned int n_rx_inner_tcp_udp_chksum_err; 530 unsigned int n_rx_eth_crc_err; 531 unsigned int n_rx_mcast_mismatch; 532 unsigned int n_rx_frm_trunc; 533 unsigned int n_rx_overlength; 534 unsigned int n_skbuff_leaks; 535 unsigned int n_rx_nodesc_trunc; 536 unsigned int n_rx_merge_events; 537 unsigned int n_rx_merge_packets; 538 unsigned int n_rx_xdp_drops; 539 unsigned int n_rx_xdp_bad_drops; 540 unsigned int n_rx_xdp_tx; 541 unsigned int n_rx_xdp_redirect; 542 543 unsigned int rx_pkt_n_frags; 544 unsigned int rx_pkt_index; 545 546 struct list_head *rx_list; 547 548 struct efx_rx_queue rx_queue; 549 struct efx_tx_queue tx_queue[EFX_MAX_TXQ_PER_CHANNEL]; 550 struct efx_tx_queue *tx_queue_by_type[EFX_TXQ_TYPES]; 551 552 enum efx_sync_events_state sync_events_state; 553 u32 sync_timestamp_major; 554 u32 sync_timestamp_minor; 555 }; 556 557 /** 558 * struct efx_msi_context - Context for each MSI 559 * @efx: The associated NIC 560 * @index: Index of the channel/IRQ 561 * @name: Name of the channel/IRQ 562 * 563 * Unlike &struct efx_channel, this is never reallocated and is always 564 * safe for the IRQ handler to access. 565 */ 566 struct efx_msi_context { 567 struct efx_nic *efx; 568 unsigned int index; 569 char name[IFNAMSIZ + 6]; 570 }; 571 572 /** 573 * struct efx_channel_type - distinguishes traffic and extra channels 574 * @handle_no_channel: Handle failure to allocate an extra channel 575 * @pre_probe: Set up extra state prior to initialisation 576 * @post_remove: Tear down extra state after finalisation, if allocated. 577 * May be called on channels that have not been probed. 578 * @get_name: Generate the channel's name (used for its IRQ handler) 579 * @copy: Copy the channel state prior to reallocation. May be %NULL if 580 * reallocation is not supported. 581 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb() 582 * @want_txqs: Determine whether this channel should have TX queues 583 * created. If %NULL, TX queues are not created. 584 * @keep_eventq: Flag for whether event queue should be kept initialised 585 * while the device is stopped 586 * @want_pio: Flag for whether PIO buffers should be linked to this 587 * channel's TX queues. 588 */ 589 struct efx_channel_type { 590 void (*handle_no_channel)(struct efx_nic *); 591 int (*pre_probe)(struct efx_channel *); 592 void (*post_remove)(struct efx_channel *); 593 void (*get_name)(struct efx_channel *, char *buf, size_t len); 594 struct efx_channel *(*copy)(const struct efx_channel *); 595 bool (*receive_skb)(struct efx_channel *, struct sk_buff *); 596 bool (*want_txqs)(struct efx_channel *); 597 bool keep_eventq; 598 bool want_pio; 599 }; 600 601 enum efx_led_mode { 602 EFX_LED_OFF = 0, 603 EFX_LED_ON = 1, 604 EFX_LED_DEFAULT = 2 605 }; 606 607 #define STRING_TABLE_LOOKUP(val, member) \ 608 ((val) < member ## _max) ? member ## _names[val] : "(invalid)" 609 610 extern const char *const efx_loopback_mode_names[]; 611 extern const unsigned int efx_loopback_mode_max; 612 #define LOOPBACK_MODE(efx) \ 613 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) 614 615 extern const char *const efx_reset_type_names[]; 616 extern const unsigned int efx_reset_type_max; 617 #define RESET_TYPE(type) \ 618 STRING_TABLE_LOOKUP(type, efx_reset_type) 619 620 enum efx_int_mode { 621 /* Be careful if altering to correct macro below */ 622 EFX_INT_MODE_MSIX = 0, 623 EFX_INT_MODE_MSI = 1, 624 EFX_INT_MODE_LEGACY = 2, 625 EFX_INT_MODE_MAX /* Insert any new items before this */ 626 }; 627 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) 628 629 enum nic_state { 630 STATE_UNINIT = 0, /* device being probed/removed or is frozen */ 631 STATE_READY = 1, /* hardware ready and netdev registered */ 632 STATE_DISABLED = 2, /* device disabled due to hardware errors */ 633 STATE_RECOVERY = 3, /* device recovering from PCI error */ 634 }; 635 636 /* Forward declaration */ 637 struct efx_nic; 638 639 /* Pseudo bit-mask flow control field */ 640 #define EFX_FC_RX FLOW_CTRL_RX 641 #define EFX_FC_TX FLOW_CTRL_TX 642 #define EFX_FC_AUTO 4 643 644 /** 645 * struct efx_link_state - Current state of the link 646 * @up: Link is up 647 * @fd: Link is full-duplex 648 * @fc: Actual flow control flags 649 * @speed: Link speed (Mbps) 650 */ 651 struct efx_link_state { 652 bool up; 653 bool fd; 654 u8 fc; 655 unsigned int speed; 656 }; 657 658 static inline bool efx_link_state_equal(const struct efx_link_state *left, 659 const struct efx_link_state *right) 660 { 661 return left->up == right->up && left->fd == right->fd && 662 left->fc == right->fc && left->speed == right->speed; 663 } 664 665 /** 666 * enum efx_phy_mode - PHY operating mode flags 667 * @PHY_MODE_NORMAL: on and should pass traffic 668 * @PHY_MODE_TX_DISABLED: on with TX disabled 669 * @PHY_MODE_LOW_POWER: set to low power through MDIO 670 * @PHY_MODE_OFF: switched off through external control 671 * @PHY_MODE_SPECIAL: on but will not pass traffic 672 */ 673 enum efx_phy_mode { 674 PHY_MODE_NORMAL = 0, 675 PHY_MODE_TX_DISABLED = 1, 676 PHY_MODE_LOW_POWER = 2, 677 PHY_MODE_OFF = 4, 678 PHY_MODE_SPECIAL = 8, 679 }; 680 681 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) 682 { 683 return !!(mode & ~PHY_MODE_TX_DISABLED); 684 } 685 686 /** 687 * struct efx_hw_stat_desc - Description of a hardware statistic 688 * @name: Name of the statistic as visible through ethtool, or %NULL if 689 * it should not be exposed 690 * @dma_width: Width in bits (0 for non-DMA statistics) 691 * @offset: Offset within stats (ignored for non-DMA statistics) 692 */ 693 struct efx_hw_stat_desc { 694 const char *name; 695 u16 dma_width; 696 u16 offset; 697 }; 698 699 /* Number of bits used in a multicast filter hash address */ 700 #define EFX_MCAST_HASH_BITS 8 701 702 /* Number of (single-bit) entries in a multicast filter hash */ 703 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) 704 705 /* An Efx multicast filter hash */ 706 union efx_multicast_hash { 707 u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; 708 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; 709 }; 710 711 struct vfdi_status; 712 713 /* The reserved RSS context value */ 714 #define EFX_MCDI_RSS_CONTEXT_INVALID 0xffffffff 715 /** 716 * struct efx_rss_context - A user-defined RSS context for filtering 717 * @list: node of linked list on which this struct is stored 718 * @context_id: the RSS_CONTEXT_ID returned by MC firmware, or 719 * %EFX_MCDI_RSS_CONTEXT_INVALID if this context is not present on the NIC. 720 * For Siena, 0 if RSS is active, else %EFX_MCDI_RSS_CONTEXT_INVALID. 721 * @user_id: the rss_context ID exposed to userspace over ethtool. 722 * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled 723 * @rx_hash_key: Toeplitz hash key for this RSS context 724 * @indir_table: Indirection table for this RSS context 725 */ 726 struct efx_rss_context { 727 struct list_head list; 728 u32 context_id; 729 u32 user_id; 730 bool rx_hash_udp_4tuple; 731 u8 rx_hash_key[40]; 732 u32 rx_indir_table[128]; 733 }; 734 735 #ifdef CONFIG_RFS_ACCEL 736 /* Order of these is important, since filter_id >= %EFX_ARFS_FILTER_ID_PENDING 737 * is used to test if filter does or will exist. 738 */ 739 #define EFX_ARFS_FILTER_ID_PENDING -1 740 #define EFX_ARFS_FILTER_ID_ERROR -2 741 #define EFX_ARFS_FILTER_ID_REMOVING -3 742 /** 743 * struct efx_arfs_rule - record of an ARFS filter and its IDs 744 * @node: linkage into hash table 745 * @spec: details of the filter (used as key for hash table). Use efx->type to 746 * determine which member to use. 747 * @rxq_index: channel to which the filter will steer traffic. 748 * @arfs_id: filter ID which was returned to ARFS 749 * @filter_id: index in software filter table. May be 750 * %EFX_ARFS_FILTER_ID_PENDING if filter was not inserted yet, 751 * %EFX_ARFS_FILTER_ID_ERROR if filter insertion failed, or 752 * %EFX_ARFS_FILTER_ID_REMOVING if expiry is currently removing the filter. 753 */ 754 struct efx_arfs_rule { 755 struct hlist_node node; 756 struct efx_filter_spec spec; 757 u16 rxq_index; 758 u16 arfs_id; 759 s32 filter_id; 760 }; 761 762 /* Size chosen so that the table is one page (4kB) */ 763 #define EFX_ARFS_HASH_TABLE_SIZE 512 764 765 /** 766 * struct efx_async_filter_insertion - Request to asynchronously insert a filter 767 * @net_dev: Reference to the netdevice 768 * @spec: The filter to insert 769 * @work: Workitem for this request 770 * @rxq_index: Identifies the channel for which this request was made 771 * @flow_id: Identifies the kernel-side flow for which this request was made 772 */ 773 struct efx_async_filter_insertion { 774 struct net_device *net_dev; 775 struct efx_filter_spec spec; 776 struct work_struct work; 777 u16 rxq_index; 778 u32 flow_id; 779 }; 780 781 /* Maximum number of ARFS workitems that may be in flight on an efx_nic */ 782 #define EFX_RPS_MAX_IN_FLIGHT 8 783 #endif /* CONFIG_RFS_ACCEL */ 784 785 enum efx_xdp_tx_queues_mode { 786 EFX_XDP_TX_QUEUES_DEDICATED, /* one queue per core, locking not needed */ 787 EFX_XDP_TX_QUEUES_SHARED, /* each queue used by more than 1 core */ 788 EFX_XDP_TX_QUEUES_BORROWED /* queues borrowed from net stack */ 789 }; 790 791 /** 792 * struct efx_nic - an Efx NIC 793 * @name: Device name (net device name or bus id before net device registered) 794 * @pci_dev: The PCI device 795 * @node: List node for maintaning primary/secondary function lists 796 * @primary: &struct efx_nic instance for the primary function of this 797 * controller. May be the same structure, and may be %NULL if no 798 * primary function is bound. Serialised by rtnl_lock. 799 * @secondary_list: List of &struct efx_nic instances for the secondary PCI 800 * functions of the controller, if this is for the primary function. 801 * Serialised by rtnl_lock. 802 * @type: Controller type attributes 803 * @legacy_irq: IRQ number 804 * @workqueue: Workqueue for port reconfigures and the HW monitor. 805 * Work items do not hold and must not acquire RTNL. 806 * @workqueue_name: Name of workqueue 807 * @reset_work: Scheduled reset workitem 808 * @membase_phys: Memory BAR value as physical address 809 * @membase: Memory BAR value 810 * @vi_stride: step between per-VI registers / memory regions 811 * @interrupt_mode: Interrupt mode 812 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds 813 * @timer_max_ns: Interrupt timer maximum value, in nanoseconds 814 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues 815 * @irqs_hooked: Channel interrupts are hooked 816 * @irq_rx_mod_step_us: Step size for IRQ moderation for RX event queues 817 * @irq_rx_moderation_us: IRQ moderation time for RX event queues 818 * @msg_enable: Log message enable flags 819 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock. 820 * @reset_pending: Bitmask for pending resets 821 * @tx_queue: TX DMA queues 822 * @rx_queue: RX DMA queues 823 * @channel: Channels 824 * @msi_context: Context for each MSI 825 * @extra_channel_types: Types of extra (non-traffic) channels that 826 * should be allocated for this NIC 827 * @xdp_tx_queue_count: Number of entries in %xdp_tx_queues. 828 * @xdp_tx_queues: Array of pointers to tx queues used for XDP transmit. 829 * @xdp_txq_queues_mode: XDP TX queues sharing strategy. 830 * @rxq_entries: Size of receive queues requested by user. 831 * @txq_entries: Size of transmit queues requested by user. 832 * @txq_stop_thresh: TX queue fill level at or above which we stop it. 833 * @txq_wake_thresh: TX queue fill level at or below which we wake it. 834 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches 835 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches 836 * @sram_lim_qw: Qword address limit of SRAM 837 * @next_buffer_table: First available buffer table id 838 * @n_channels: Number of channels in use 839 * @n_rx_channels: Number of channels used for RX (= number of RX queues) 840 * @n_tx_channels: Number of channels used for TX 841 * @n_extra_tx_channels: Number of extra channels with TX queues 842 * @tx_queues_per_channel: number of TX queues probed on each channel 843 * @n_xdp_channels: Number of channels used for XDP TX 844 * @xdp_channel_offset: Offset of zeroth channel used for XPD TX. 845 * @xdp_tx_per_channel: Max number of TX queues on an XDP TX channel. 846 * @rx_ip_align: RX DMA address offset to have IP header aligned in 847 * in accordance with NET_IP_ALIGN 848 * @rx_dma_len: Current maximum RX DMA length 849 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer 850 * @rx_buffer_truesize: Amortised allocation size of an RX buffer, 851 * for use in sk_buff::truesize 852 * @rx_prefix_size: Size of RX prefix before packet data 853 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data 854 * (valid only if @rx_prefix_size != 0; always negative) 855 * @rx_packet_len_offset: Offset of RX packet length from start of packet data 856 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative) 857 * @rx_packet_ts_offset: Offset of timestamp from start of packet data 858 * (valid only if channel->sync_timestamps_enabled; always negative) 859 * @rx_scatter: Scatter mode enabled for receives 860 * @rss_context: Main RSS context. Its @list member is the head of the list of 861 * RSS contexts created by user requests 862 * @rss_lock: Protects custom RSS context software state in @rss_context.list 863 * @vport_id: The function's vport ID, only relevant for PFs 864 * @int_error_count: Number of internal errors seen recently 865 * @int_error_expire: Time at which error count will be expired 866 * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot 867 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will 868 * acknowledge but do nothing else. 869 * @irq_status: Interrupt status buffer 870 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 871 * @irq_level: IRQ level/index for IRQs not triggered by an event queue 872 * @selftest_work: Work item for asynchronous self-test 873 * @mtd_list: List of MTDs attached to the NIC 874 * @nic_data: Hardware dependent state 875 * @mcdi: Management-Controller-to-Driver Interface state 876 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, 877 * efx_monitor() and efx_reconfigure_port() 878 * @port_enabled: Port enabled indicator. 879 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and 880 * efx_mac_work() with kernel interfaces. Safe to read under any 881 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must 882 * be held to modify it. 883 * @port_initialized: Port initialized? 884 * @net_dev: Operating system network device. Consider holding the rtnl lock 885 * @fixed_features: Features which cannot be turned off 886 * @num_mac_stats: Number of MAC stats reported by firmware (MAC_STATS_NUM_STATS 887 * field of %MC_CMD_GET_CAPABILITIES_V4 response, or %MC_CMD_MAC_NSTATS) 888 * @stats_buffer: DMA buffer for statistics 889 * @phy_type: PHY type 890 * @phy_data: PHY private data (including PHY-specific stats) 891 * @mdio: PHY MDIO interface 892 * @mdio_bus: PHY MDIO bus ID (only used by Siena) 893 * @phy_mode: PHY operating mode. Serialised by @mac_lock. 894 * @link_advertising: Autonegotiation advertising flags 895 * @fec_config: Forward Error Correction configuration flags. For bit positions 896 * see &enum ethtool_fec_config_bits. 897 * @link_state: Current state of the link 898 * @n_link_state_changes: Number of times the link has changed state 899 * @unicast_filter: Flag for Falcon-arch simple unicast filter. 900 * Protected by @mac_lock. 901 * @multicast_hash: Multicast hash table for Falcon-arch. 902 * Protected by @mac_lock. 903 * @wanted_fc: Wanted flow control flags 904 * @fc_disable: When non-zero flow control is disabled. Typically used to 905 * ensure that network back pressure doesn't delay dma queue flushes. 906 * Serialised by the rtnl lock. 907 * @mac_work: Work item for changing MAC promiscuity and multicast hash 908 * @loopback_mode: Loopback status 909 * @loopback_modes: Supported loopback mode bitmask 910 * @loopback_selftest: Offline self-test private state 911 * @xdp_prog: Current XDP programme for this interface 912 * @filter_sem: Filter table rw_semaphore, protects existence of @filter_state 913 * @filter_state: Architecture-dependent filter table state 914 * @rps_mutex: Protects RPS state of all channels 915 * @rps_slot_map: bitmap of in-flight entries in @rps_slot 916 * @rps_slot: array of ARFS insertion requests for efx_filter_rfs_work() 917 * @rps_hash_lock: Protects ARFS filter mapping state (@rps_hash_table and 918 * @rps_next_id). 919 * @rps_hash_table: Mapping between ARFS filters and their various IDs 920 * @rps_next_id: next arfs_id for an ARFS filter 921 * @active_queues: Count of RX and TX queues that haven't been flushed and drained. 922 * @rxq_flush_pending: Count of number of receive queues that need to be flushed. 923 * Decremented when the efx_flush_rx_queue() is called. 924 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet 925 * completed (either success or failure). Not used when MCDI is used to 926 * flush receive queues. 927 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions. 928 * @vf_count: Number of VFs intended to be enabled. 929 * @vf_init_count: Number of VFs that have been fully initialised. 930 * @vi_scale: log2 number of vnics per VF. 931 * @ptp_data: PTP state data 932 * @ptp_warned: has this NIC seen and warned about unexpected PTP events? 933 * @vpd_sn: Serial number read from VPD 934 * @xdp_rxq_info_failed: Have any of the rx queues failed to initialise their 935 * xdp_rxq_info structures? 936 * @netdev_notifier: Netdevice notifier. 937 * @mem_bar: The BAR that is mapped into membase. 938 * @reg_base: Offset from the start of the bar to the function control window. 939 * @monitor_work: Hardware monitor workitem 940 * @biu_lock: BIU (bus interface unit) lock 941 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This 942 * field is used by efx_test_interrupts() to verify that an 943 * interrupt has occurred. 944 * @stats_lock: Statistics update lock. Must be held when calling 945 * efx_nic_type::{update,start,stop}_stats. 946 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb 947 * 948 * This is stored in the private area of the &struct net_device. 949 */ 950 struct efx_nic { 951 /* The following fields should be written very rarely */ 952 953 char name[IFNAMSIZ]; 954 struct list_head node; 955 struct efx_nic *primary; 956 struct list_head secondary_list; 957 struct pci_dev *pci_dev; 958 unsigned int port_num; 959 const struct efx_nic_type *type; 960 int legacy_irq; 961 bool eeh_disabled_legacy_irq; 962 struct workqueue_struct *workqueue; 963 char workqueue_name[16]; 964 struct work_struct reset_work; 965 resource_size_t membase_phys; 966 void __iomem *membase; 967 968 unsigned int vi_stride; 969 970 enum efx_int_mode interrupt_mode; 971 unsigned int timer_quantum_ns; 972 unsigned int timer_max_ns; 973 bool irq_rx_adaptive; 974 bool irqs_hooked; 975 unsigned int irq_mod_step_us; 976 unsigned int irq_rx_moderation_us; 977 u32 msg_enable; 978 979 enum nic_state state; 980 unsigned long reset_pending; 981 982 struct efx_channel *channel[EFX_MAX_CHANNELS]; 983 struct efx_msi_context msi_context[EFX_MAX_CHANNELS]; 984 const struct efx_channel_type * 985 extra_channel_type[EFX_MAX_EXTRA_CHANNELS]; 986 987 unsigned int xdp_tx_queue_count; 988 struct efx_tx_queue **xdp_tx_queues; 989 enum efx_xdp_tx_queues_mode xdp_txq_queues_mode; 990 991 unsigned rxq_entries; 992 unsigned txq_entries; 993 unsigned int txq_stop_thresh; 994 unsigned int txq_wake_thresh; 995 996 unsigned tx_dc_base; 997 unsigned rx_dc_base; 998 unsigned sram_lim_qw; 999 unsigned next_buffer_table; 1000 1001 unsigned int max_channels; 1002 unsigned int max_vis; 1003 unsigned int max_tx_channels; 1004 unsigned n_channels; 1005 unsigned n_rx_channels; 1006 unsigned rss_spread; 1007 unsigned tx_channel_offset; 1008 unsigned n_tx_channels; 1009 unsigned n_extra_tx_channels; 1010 unsigned int tx_queues_per_channel; 1011 unsigned int n_xdp_channels; 1012 unsigned int xdp_channel_offset; 1013 unsigned int xdp_tx_per_channel; 1014 unsigned int rx_ip_align; 1015 unsigned int rx_dma_len; 1016 unsigned int rx_buffer_order; 1017 unsigned int rx_buffer_truesize; 1018 unsigned int rx_page_buf_step; 1019 unsigned int rx_bufs_per_page; 1020 unsigned int rx_pages_per_batch; 1021 unsigned int rx_prefix_size; 1022 int rx_packet_hash_offset; 1023 int rx_packet_len_offset; 1024 int rx_packet_ts_offset; 1025 bool rx_scatter; 1026 struct efx_rss_context rss_context; 1027 struct mutex rss_lock; 1028 u32 vport_id; 1029 1030 unsigned int_error_count; 1031 unsigned long int_error_expire; 1032 1033 bool must_realloc_vis; 1034 bool irq_soft_enabled; 1035 struct efx_buffer irq_status; 1036 unsigned irq_zero_count; 1037 unsigned irq_level; 1038 struct delayed_work selftest_work; 1039 1040 #ifdef CONFIG_SFC_MTD 1041 struct list_head mtd_list; 1042 #endif 1043 1044 void *nic_data; 1045 struct efx_mcdi_data *mcdi; 1046 1047 struct mutex mac_lock; 1048 struct work_struct mac_work; 1049 bool port_enabled; 1050 1051 bool mc_bist_for_other_fn; 1052 bool port_initialized; 1053 struct net_device *net_dev; 1054 1055 netdev_features_t fixed_features; 1056 1057 u16 num_mac_stats; 1058 struct efx_buffer stats_buffer; 1059 u64 rx_nodesc_drops_total; 1060 u64 rx_nodesc_drops_while_down; 1061 bool rx_nodesc_drops_prev_state; 1062 1063 unsigned int phy_type; 1064 void *phy_data; 1065 struct mdio_if_info mdio; 1066 unsigned int mdio_bus; 1067 enum efx_phy_mode phy_mode; 1068 1069 __ETHTOOL_DECLARE_LINK_MODE_MASK(link_advertising); 1070 u32 fec_config; 1071 struct efx_link_state link_state; 1072 unsigned int n_link_state_changes; 1073 1074 bool unicast_filter; 1075 union efx_multicast_hash multicast_hash; 1076 u8 wanted_fc; 1077 unsigned fc_disable; 1078 1079 atomic_t rx_reset; 1080 enum efx_loopback_mode loopback_mode; 1081 u64 loopback_modes; 1082 1083 void *loopback_selftest; 1084 /* We access loopback_selftest immediately before running XDP, 1085 * so we want them next to each other. 1086 */ 1087 struct bpf_prog __rcu *xdp_prog; 1088 1089 struct rw_semaphore filter_sem; 1090 void *filter_state; 1091 #ifdef CONFIG_RFS_ACCEL 1092 struct mutex rps_mutex; 1093 unsigned long rps_slot_map; 1094 struct efx_async_filter_insertion rps_slot[EFX_RPS_MAX_IN_FLIGHT]; 1095 spinlock_t rps_hash_lock; 1096 struct hlist_head *rps_hash_table; 1097 u32 rps_next_id; 1098 #endif 1099 1100 atomic_t active_queues; 1101 atomic_t rxq_flush_pending; 1102 atomic_t rxq_flush_outstanding; 1103 wait_queue_head_t flush_wq; 1104 1105 #ifdef CONFIG_SFC_SRIOV 1106 unsigned vf_count; 1107 unsigned vf_init_count; 1108 unsigned vi_scale; 1109 #endif 1110 1111 struct efx_ptp_data *ptp_data; 1112 bool ptp_warned; 1113 1114 char *vpd_sn; 1115 bool xdp_rxq_info_failed; 1116 1117 struct notifier_block netdev_notifier; 1118 1119 unsigned int mem_bar; 1120 u32 reg_base; 1121 1122 /* The following fields may be written more often */ 1123 1124 struct delayed_work monitor_work ____cacheline_aligned_in_smp; 1125 spinlock_t biu_lock; 1126 int last_irq_cpu; 1127 spinlock_t stats_lock; 1128 atomic_t n_rx_noskb_drops; 1129 }; 1130 1131 static inline int efx_dev_registered(struct efx_nic *efx) 1132 { 1133 return efx->net_dev->reg_state == NETREG_REGISTERED; 1134 } 1135 1136 static inline unsigned int efx_port_num(struct efx_nic *efx) 1137 { 1138 return efx->port_num; 1139 } 1140 1141 struct efx_mtd_partition { 1142 struct list_head node; 1143 struct mtd_info mtd; 1144 const char *dev_type_name; 1145 const char *type_name; 1146 char name[IFNAMSIZ + 20]; 1147 }; 1148 1149 struct efx_udp_tunnel { 1150 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID 0xffff 1151 u16 type; /* TUNNEL_ENCAP_UDP_PORT_ENTRY_foo, see mcdi_pcol.h */ 1152 __be16 port; 1153 }; 1154 1155 /** 1156 * struct efx_nic_type - Efx device type definition 1157 * @mem_bar: Get the memory BAR 1158 * @mem_map_size: Get memory BAR mapped size 1159 * @probe: Probe the controller 1160 * @remove: Free resources allocated by probe() 1161 * @init: Initialise the controller 1162 * @dimension_resources: Dimension controller resources (buffer table, 1163 * and VIs once the available interrupt resources are clear) 1164 * @fini: Shut down the controller 1165 * @monitor: Periodic function for polling link state and hardware monitor 1166 * @map_reset_reason: Map ethtool reset reason to a reset method 1167 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible 1168 * @reset: Reset the controller hardware and possibly the PHY. This will 1169 * be called while the controller is uninitialised. 1170 * @probe_port: Probe the MAC and PHY 1171 * @remove_port: Free resources allocated by probe_port() 1172 * @handle_global_event: Handle a "global" event (may be %NULL) 1173 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues) 1174 * @prepare_flush: Prepare the hardware for flushing the DMA queues 1175 * (for Falcon architecture) 1176 * @finish_flush: Clean up after flushing the DMA queues (for Falcon 1177 * architecture) 1178 * @prepare_flr: Prepare for an FLR 1179 * @finish_flr: Clean up after an FLR 1180 * @describe_stats: Describe statistics for ethtool 1181 * @update_stats: Update statistics not provided by event handling. 1182 * Either argument may be %NULL. 1183 * @update_stats_atomic: Update statistics while in atomic context, if that 1184 * is more limiting than @update_stats. Otherwise, leave %NULL and 1185 * driver core will call @update_stats. 1186 * @start_stats: Start the regular fetching of statistics 1187 * @pull_stats: Pull stats from the NIC and wait until they arrive. 1188 * @stop_stats: Stop the regular fetching of statistics 1189 * @push_irq_moderation: Apply interrupt moderation value 1190 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY 1191 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL) 1192 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings 1193 * to the hardware. Serialised by the mac_lock. 1194 * @check_mac_fault: Check MAC fault state. True if fault present. 1195 * @get_wol: Get WoL configuration from driver state 1196 * @set_wol: Push WoL configuration to the NIC 1197 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) 1198 * @get_fec_stats: Get standard FEC statistics. 1199 * @test_chip: Test registers. May use efx_farch_test_registers(), and is 1200 * expected to reset the NIC. 1201 * @test_nvram: Test validity of NVRAM contents 1202 * @mcdi_request: Send an MCDI request with the given header and SDU. 1203 * The SDU length may be any value from 0 up to the protocol- 1204 * defined maximum, but its buffer will be padded to a multiple 1205 * of 4 bytes. 1206 * @mcdi_poll_response: Test whether an MCDI response is available. 1207 * @mcdi_read_response: Read the MCDI response PDU. The offset will 1208 * be a multiple of 4. The length may not be, but the buffer 1209 * will be padded so it is safe to round up. 1210 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so, 1211 * return an appropriate error code for aborting any current 1212 * request; otherwise return 0. 1213 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must 1214 * be separately enabled after this. 1215 * @irq_test_generate: Generate a test IRQ 1216 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event 1217 * queue must be separately disabled before this. 1218 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is 1219 * a pointer to the &struct efx_msi_context for the channel. 1220 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument 1221 * is a pointer to the &struct efx_nic. 1222 * @tx_probe: Allocate resources for TX queue (and select TXQ type) 1223 * @tx_init: Initialise TX queue on the NIC 1224 * @tx_remove: Free resources for TX queue 1225 * @tx_write: Write TX descriptors and doorbell 1226 * @tx_enqueue: Add an SKB to TX queue 1227 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC 1228 * @rx_pull_rss_config: Read RSS hash key and indirection table back from the NIC 1229 * @rx_push_rss_context_config: Write RSS hash key and indirection table for 1230 * user RSS context to the NIC 1231 * @rx_pull_rss_context_config: Read RSS hash key and indirection table for user 1232 * RSS context back from the NIC 1233 * @rx_probe: Allocate resources for RX queue 1234 * @rx_init: Initialise RX queue on the NIC 1235 * @rx_remove: Free resources for RX queue 1236 * @rx_write: Write RX descriptors and doorbell 1237 * @rx_defer_refill: Generate a refill reminder event 1238 * @rx_packet: Receive the queued RX buffer on a channel 1239 * @rx_buf_hash_valid: Determine whether the RX prefix contains a valid hash 1240 * @ev_probe: Allocate resources for event queue 1241 * @ev_init: Initialise event queue on the NIC 1242 * @ev_fini: Deinitialise event queue on the NIC 1243 * @ev_remove: Free resources for event queue 1244 * @ev_process: Process events for a queue, up to the given NAPI quota 1245 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ 1246 * @ev_test_generate: Generate a test event 1247 * @filter_table_probe: Probe filter capabilities and set up filter software state 1248 * @filter_table_restore: Restore filters removed from hardware 1249 * @filter_table_remove: Remove filters from hardware and tear down software state 1250 * @filter_update_rx_scatter: Update filters after change to rx scatter setting 1251 * @filter_insert: add or replace a filter 1252 * @filter_remove_safe: remove a filter by ID, carefully 1253 * @filter_get_safe: retrieve a filter by ID, carefully 1254 * @filter_clear_rx: Remove all RX filters whose priority is less than or 1255 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO 1256 * @filter_count_rx_used: Get the number of filters in use at a given priority 1257 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1 1258 * @filter_get_rx_ids: Get list of RX filters at a given priority 1259 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS. 1260 * This must check whether the specified table entry is used by RFS 1261 * and that rps_may_expire_flow() returns true for it. 1262 * @mtd_probe: Probe and add MTD partitions associated with this net device, 1263 * using efx_mtd_add() 1264 * @mtd_rename: Set an MTD partition name using the net device name 1265 * @mtd_read: Read from an MTD partition 1266 * @mtd_erase: Erase part of an MTD partition 1267 * @mtd_write: Write to an MTD partition 1268 * @mtd_sync: Wait for write-back to complete on MTD partition. This 1269 * also notifies the driver that a writer has finished using this 1270 * partition. 1271 * @ptp_write_host_time: Send host time to MC as part of sync protocol 1272 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX 1273 * timestamping, possibly only temporarily for the purposes of a reset. 1274 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags 1275 * and tx_type will already have been validated but this operation 1276 * must validate and update rx_filter. 1277 * @get_phys_port_id: Get the underlying physical port id. 1278 * @set_mac_address: Set the MAC address of the device 1279 * @tso_versions: Returns mask of firmware-assisted TSO versions supported. 1280 * If %NULL, then device does not support any TSO version. 1281 * @udp_tnl_push_ports: Push the list of UDP tunnel ports to the NIC if required. 1282 * @udp_tnl_has_port: Check if a port has been added as UDP tunnel 1283 * @print_additional_fwver: Dump NIC-specific additional FW version info 1284 * @sensor_event: Handle a sensor event from MCDI 1285 * @revision: Hardware architecture revision 1286 * @txd_ptr_tbl_base: TX descriptor ring base address 1287 * @rxd_ptr_tbl_base: RX descriptor ring base address 1288 * @buf_tbl_base: Buffer table base address 1289 * @evq_ptr_tbl_base: Event queue pointer table base address 1290 * @evq_rptr_tbl_base: Event queue read-pointer table base address 1291 * @max_dma_mask: Maximum possible DMA mask 1292 * @rx_prefix_size: Size of RX prefix before packet data 1293 * @rx_hash_offset: Offset of RX flow hash within prefix 1294 * @rx_ts_offset: Offset of timestamp within prefix 1295 * @rx_buffer_padding: Size of padding at end of RX packet 1296 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers 1297 * @always_rx_scatter: NIC will always scatter packets to multiple buffers 1298 * @option_descriptors: NIC supports TX option descriptors 1299 * @min_interrupt_mode: Lowest capability interrupt mode supported 1300 * from &enum efx_int_mode. 1301 * @timer_period_max: Maximum period of interrupt timer (in ticks) 1302 * @offload_features: net_device feature flags for protocol offload 1303 * features implemented in hardware 1304 * @mcdi_max_ver: Maximum MCDI version supported 1305 * @hwtstamp_filters: Mask of hardware timestamp filter types supported 1306 */ 1307 struct efx_nic_type { 1308 bool is_vf; 1309 unsigned int (*mem_bar)(struct efx_nic *efx); 1310 unsigned int (*mem_map_size)(struct efx_nic *efx); 1311 int (*probe)(struct efx_nic *efx); 1312 void (*remove)(struct efx_nic *efx); 1313 int (*init)(struct efx_nic *efx); 1314 int (*dimension_resources)(struct efx_nic *efx); 1315 void (*fini)(struct efx_nic *efx); 1316 void (*monitor)(struct efx_nic *efx); 1317 enum reset_type (*map_reset_reason)(enum reset_type reason); 1318 int (*map_reset_flags)(u32 *flags); 1319 int (*reset)(struct efx_nic *efx, enum reset_type method); 1320 int (*probe_port)(struct efx_nic *efx); 1321 void (*remove_port)(struct efx_nic *efx); 1322 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *); 1323 int (*fini_dmaq)(struct efx_nic *efx); 1324 void (*prepare_flush)(struct efx_nic *efx); 1325 void (*finish_flush)(struct efx_nic *efx); 1326 void (*prepare_flr)(struct efx_nic *efx); 1327 void (*finish_flr)(struct efx_nic *efx); 1328 size_t (*describe_stats)(struct efx_nic *efx, u8 *names); 1329 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats, 1330 struct rtnl_link_stats64 *core_stats); 1331 size_t (*update_stats_atomic)(struct efx_nic *efx, u64 *full_stats, 1332 struct rtnl_link_stats64 *core_stats); 1333 void (*start_stats)(struct efx_nic *efx); 1334 void (*pull_stats)(struct efx_nic *efx); 1335 void (*stop_stats)(struct efx_nic *efx); 1336 void (*push_irq_moderation)(struct efx_channel *channel); 1337 int (*reconfigure_port)(struct efx_nic *efx); 1338 void (*prepare_enable_fc_tx)(struct efx_nic *efx); 1339 int (*reconfigure_mac)(struct efx_nic *efx, bool mtu_only); 1340 bool (*check_mac_fault)(struct efx_nic *efx); 1341 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); 1342 int (*set_wol)(struct efx_nic *efx, u32 type); 1343 void (*resume_wol)(struct efx_nic *efx); 1344 void (*get_fec_stats)(struct efx_nic *efx, 1345 struct ethtool_fec_stats *fec_stats); 1346 unsigned int (*check_caps)(const struct efx_nic *efx, 1347 u8 flag, 1348 u32 offset); 1349 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests); 1350 int (*test_nvram)(struct efx_nic *efx); 1351 void (*mcdi_request)(struct efx_nic *efx, 1352 const efx_dword_t *hdr, size_t hdr_len, 1353 const efx_dword_t *sdu, size_t sdu_len); 1354 bool (*mcdi_poll_response)(struct efx_nic *efx); 1355 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu, 1356 size_t pdu_offset, size_t pdu_len); 1357 int (*mcdi_poll_reboot)(struct efx_nic *efx); 1358 void (*mcdi_reboot_detected)(struct efx_nic *efx); 1359 void (*irq_enable_master)(struct efx_nic *efx); 1360 int (*irq_test_generate)(struct efx_nic *efx); 1361 void (*irq_disable_non_ev)(struct efx_nic *efx); 1362 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id); 1363 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id); 1364 int (*tx_probe)(struct efx_tx_queue *tx_queue); 1365 void (*tx_init)(struct efx_tx_queue *tx_queue); 1366 void (*tx_remove)(struct efx_tx_queue *tx_queue); 1367 void (*tx_write)(struct efx_tx_queue *tx_queue); 1368 netdev_tx_t (*tx_enqueue)(struct efx_tx_queue *tx_queue, struct sk_buff *skb); 1369 unsigned int (*tx_limit_len)(struct efx_tx_queue *tx_queue, 1370 dma_addr_t dma_addr, unsigned int len); 1371 int (*rx_push_rss_config)(struct efx_nic *efx, bool user, 1372 const u32 *rx_indir_table, const u8 *key); 1373 int (*rx_pull_rss_config)(struct efx_nic *efx); 1374 int (*rx_push_rss_context_config)(struct efx_nic *efx, 1375 struct efx_rss_context *ctx, 1376 const u32 *rx_indir_table, 1377 const u8 *key); 1378 int (*rx_pull_rss_context_config)(struct efx_nic *efx, 1379 struct efx_rss_context *ctx); 1380 void (*rx_restore_rss_contexts)(struct efx_nic *efx); 1381 int (*rx_probe)(struct efx_rx_queue *rx_queue); 1382 void (*rx_init)(struct efx_rx_queue *rx_queue); 1383 void (*rx_remove)(struct efx_rx_queue *rx_queue); 1384 void (*rx_write)(struct efx_rx_queue *rx_queue); 1385 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue); 1386 void (*rx_packet)(struct efx_channel *channel); 1387 bool (*rx_buf_hash_valid)(const u8 *prefix); 1388 int (*ev_probe)(struct efx_channel *channel); 1389 int (*ev_init)(struct efx_channel *channel); 1390 void (*ev_fini)(struct efx_channel *channel); 1391 void (*ev_remove)(struct efx_channel *channel); 1392 int (*ev_process)(struct efx_channel *channel, int quota); 1393 void (*ev_read_ack)(struct efx_channel *channel); 1394 void (*ev_test_generate)(struct efx_channel *channel); 1395 int (*filter_table_probe)(struct efx_nic *efx); 1396 void (*filter_table_restore)(struct efx_nic *efx); 1397 void (*filter_table_remove)(struct efx_nic *efx); 1398 void (*filter_update_rx_scatter)(struct efx_nic *efx); 1399 s32 (*filter_insert)(struct efx_nic *efx, 1400 struct efx_filter_spec *spec, bool replace); 1401 int (*filter_remove_safe)(struct efx_nic *efx, 1402 enum efx_filter_priority priority, 1403 u32 filter_id); 1404 int (*filter_get_safe)(struct efx_nic *efx, 1405 enum efx_filter_priority priority, 1406 u32 filter_id, struct efx_filter_spec *); 1407 int (*filter_clear_rx)(struct efx_nic *efx, 1408 enum efx_filter_priority priority); 1409 u32 (*filter_count_rx_used)(struct efx_nic *efx, 1410 enum efx_filter_priority priority); 1411 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx); 1412 s32 (*filter_get_rx_ids)(struct efx_nic *efx, 1413 enum efx_filter_priority priority, 1414 u32 *buf, u32 size); 1415 #ifdef CONFIG_RFS_ACCEL 1416 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id, 1417 unsigned int index); 1418 #endif 1419 #ifdef CONFIG_SFC_MTD 1420 int (*mtd_probe)(struct efx_nic *efx); 1421 void (*mtd_rename)(struct efx_mtd_partition *part); 1422 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len, 1423 size_t *retlen, u8 *buffer); 1424 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len); 1425 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len, 1426 size_t *retlen, const u8 *buffer); 1427 int (*mtd_sync)(struct mtd_info *mtd); 1428 #endif 1429 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time); 1430 int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp); 1431 int (*ptp_set_ts_config)(struct efx_nic *efx, 1432 struct hwtstamp_config *init); 1433 int (*sriov_configure)(struct efx_nic *efx, int num_vfs); 1434 int (*vlan_rx_add_vid)(struct efx_nic *efx, __be16 proto, u16 vid); 1435 int (*vlan_rx_kill_vid)(struct efx_nic *efx, __be16 proto, u16 vid); 1436 int (*get_phys_port_id)(struct efx_nic *efx, 1437 struct netdev_phys_item_id *ppid); 1438 int (*sriov_init)(struct efx_nic *efx); 1439 void (*sriov_fini)(struct efx_nic *efx); 1440 bool (*sriov_wanted)(struct efx_nic *efx); 1441 void (*sriov_reset)(struct efx_nic *efx); 1442 void (*sriov_flr)(struct efx_nic *efx, unsigned vf_i); 1443 int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, const u8 *mac); 1444 int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan, 1445 u8 qos); 1446 int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i, 1447 bool spoofchk); 1448 int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i, 1449 struct ifla_vf_info *ivi); 1450 int (*sriov_set_vf_link_state)(struct efx_nic *efx, int vf_i, 1451 int link_state); 1452 int (*vswitching_probe)(struct efx_nic *efx); 1453 int (*vswitching_restore)(struct efx_nic *efx); 1454 void (*vswitching_remove)(struct efx_nic *efx); 1455 int (*get_mac_address)(struct efx_nic *efx, unsigned char *perm_addr); 1456 int (*set_mac_address)(struct efx_nic *efx); 1457 u32 (*tso_versions)(struct efx_nic *efx); 1458 int (*udp_tnl_push_ports)(struct efx_nic *efx); 1459 bool (*udp_tnl_has_port)(struct efx_nic *efx, __be16 port); 1460 size_t (*print_additional_fwver)(struct efx_nic *efx, char *buf, 1461 size_t len); 1462 void (*sensor_event)(struct efx_nic *efx, efx_qword_t *ev); 1463 1464 int revision; 1465 unsigned int txd_ptr_tbl_base; 1466 unsigned int rxd_ptr_tbl_base; 1467 unsigned int buf_tbl_base; 1468 unsigned int evq_ptr_tbl_base; 1469 unsigned int evq_rptr_tbl_base; 1470 u64 max_dma_mask; 1471 unsigned int rx_prefix_size; 1472 unsigned int rx_hash_offset; 1473 unsigned int rx_ts_offset; 1474 unsigned int rx_buffer_padding; 1475 bool can_rx_scatter; 1476 bool always_rx_scatter; 1477 bool option_descriptors; 1478 unsigned int min_interrupt_mode; 1479 unsigned int timer_period_max; 1480 netdev_features_t offload_features; 1481 int mcdi_max_ver; 1482 unsigned int max_rx_ip_filters; 1483 u32 hwtstamp_filters; 1484 unsigned int rx_hash_key_size; 1485 }; 1486 1487 /************************************************************************** 1488 * 1489 * Prototypes and inline functions 1490 * 1491 *************************************************************************/ 1492 1493 static inline struct efx_channel * 1494 efx_get_channel(struct efx_nic *efx, unsigned index) 1495 { 1496 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_channels); 1497 return efx->channel[index]; 1498 } 1499 1500 /* Iterate over all used channels */ 1501 #define efx_for_each_channel(_channel, _efx) \ 1502 for (_channel = (_efx)->channel[0]; \ 1503 _channel; \ 1504 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ 1505 (_efx)->channel[_channel->channel + 1] : NULL) 1506 1507 /* Iterate over all used channels in reverse */ 1508 #define efx_for_each_channel_rev(_channel, _efx) \ 1509 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \ 1510 _channel; \ 1511 _channel = _channel->channel ? \ 1512 (_efx)->channel[_channel->channel - 1] : NULL) 1513 1514 static inline struct efx_channel * 1515 efx_get_tx_channel(struct efx_nic *efx, unsigned int index) 1516 { 1517 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_tx_channels); 1518 return efx->channel[efx->tx_channel_offset + index]; 1519 } 1520 1521 static inline struct efx_channel * 1522 efx_get_xdp_channel(struct efx_nic *efx, unsigned int index) 1523 { 1524 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_xdp_channels); 1525 return efx->channel[efx->xdp_channel_offset + index]; 1526 } 1527 1528 static inline bool efx_channel_is_xdp_tx(struct efx_channel *channel) 1529 { 1530 return channel->channel - channel->efx->xdp_channel_offset < 1531 channel->efx->n_xdp_channels; 1532 } 1533 1534 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel) 1535 { 1536 return true; 1537 } 1538 1539 static inline unsigned int efx_channel_num_tx_queues(struct efx_channel *channel) 1540 { 1541 if (efx_channel_is_xdp_tx(channel)) 1542 return channel->efx->xdp_tx_per_channel; 1543 return channel->efx->tx_queues_per_channel; 1544 } 1545 1546 static inline struct efx_tx_queue * 1547 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned int type) 1548 { 1549 EFX_WARN_ON_ONCE_PARANOID(type >= EFX_TXQ_TYPES); 1550 return channel->tx_queue_by_type[type]; 1551 } 1552 1553 static inline struct efx_tx_queue * 1554 efx_get_tx_queue(struct efx_nic *efx, unsigned int index, unsigned int type) 1555 { 1556 struct efx_channel *channel = efx_get_tx_channel(efx, index); 1557 1558 return efx_channel_get_tx_queue(channel, type); 1559 } 1560 1561 /* Iterate over all TX queues belonging to a channel */ 1562 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ 1563 if (!efx_channel_has_tx_queues(_channel)) \ 1564 ; \ 1565 else \ 1566 for (_tx_queue = (_channel)->tx_queue; \ 1567 _tx_queue < (_channel)->tx_queue + \ 1568 efx_channel_num_tx_queues(_channel); \ 1569 _tx_queue++) 1570 1571 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel) 1572 { 1573 return channel->rx_queue.core_index >= 0; 1574 } 1575 1576 static inline struct efx_rx_queue * 1577 efx_channel_get_rx_queue(struct efx_channel *channel) 1578 { 1579 EFX_WARN_ON_ONCE_PARANOID(!efx_channel_has_rx_queue(channel)); 1580 return &channel->rx_queue; 1581 } 1582 1583 /* Iterate over all RX queues belonging to a channel */ 1584 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ 1585 if (!efx_channel_has_rx_queue(_channel)) \ 1586 ; \ 1587 else \ 1588 for (_rx_queue = &(_channel)->rx_queue; \ 1589 _rx_queue; \ 1590 _rx_queue = NULL) 1591 1592 static inline struct efx_channel * 1593 efx_rx_queue_channel(struct efx_rx_queue *rx_queue) 1594 { 1595 return container_of(rx_queue, struct efx_channel, rx_queue); 1596 } 1597 1598 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) 1599 { 1600 return efx_rx_queue_channel(rx_queue)->channel; 1601 } 1602 1603 /* Returns a pointer to the specified receive buffer in the RX 1604 * descriptor queue. 1605 */ 1606 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, 1607 unsigned int index) 1608 { 1609 return &rx_queue->buffer[index]; 1610 } 1611 1612 static inline struct efx_rx_buffer * 1613 efx_rx_buf_next(struct efx_rx_queue *rx_queue, struct efx_rx_buffer *rx_buf) 1614 { 1615 if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask))) 1616 return efx_rx_buffer(rx_queue, 0); 1617 else 1618 return rx_buf + 1; 1619 } 1620 1621 /** 1622 * EFX_MAX_FRAME_LEN - calculate maximum frame length 1623 * 1624 * This calculates the maximum frame length that will be used for a 1625 * given MTU. The frame length will be equal to the MTU plus a 1626 * constant amount of header space and padding. This is the quantity 1627 * that the net driver will program into the MAC as the maximum frame 1628 * length. 1629 * 1630 * The 10G MAC requires 8-byte alignment on the frame 1631 * length, so we round up to the nearest 8. 1632 * 1633 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an 1634 * XGMII cycle). If the frame length reaches the maximum value in the 1635 * same cycle, the XMAC can miss the IPG altogether. We work around 1636 * this by adding a further 16 bytes. 1637 */ 1638 #define EFX_FRAME_PAD 16 1639 #define EFX_MAX_FRAME_LEN(mtu) \ 1640 (ALIGN(((mtu) + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN + EFX_FRAME_PAD), 8)) 1641 1642 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb) 1643 { 1644 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP; 1645 } 1646 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb) 1647 { 1648 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1649 } 1650 1651 /* Get the max fill level of the TX queues on this channel */ 1652 static inline unsigned int 1653 efx_channel_tx_fill_level(struct efx_channel *channel) 1654 { 1655 struct efx_tx_queue *tx_queue; 1656 unsigned int fill_level = 0; 1657 1658 efx_for_each_channel_tx_queue(tx_queue, channel) 1659 fill_level = max(fill_level, 1660 tx_queue->insert_count - tx_queue->read_count); 1661 1662 return fill_level; 1663 } 1664 1665 /* Conservative approximation of efx_channel_tx_fill_level using cached value */ 1666 static inline unsigned int 1667 efx_channel_tx_old_fill_level(struct efx_channel *channel) 1668 { 1669 struct efx_tx_queue *tx_queue; 1670 unsigned int fill_level = 0; 1671 1672 efx_for_each_channel_tx_queue(tx_queue, channel) 1673 fill_level = max(fill_level, 1674 tx_queue->insert_count - tx_queue->old_read_count); 1675 1676 return fill_level; 1677 } 1678 1679 /* Get all supported features. 1680 * If a feature is not fixed, it is present in hw_features. 1681 * If a feature is fixed, it does not present in hw_features, but 1682 * always in features. 1683 */ 1684 static inline netdev_features_t efx_supported_features(const struct efx_nic *efx) 1685 { 1686 const struct net_device *net_dev = efx->net_dev; 1687 1688 return net_dev->features | net_dev->hw_features; 1689 } 1690 1691 /* Get the current TX queue insert index. */ 1692 static inline unsigned int 1693 efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue) 1694 { 1695 return tx_queue->insert_count & tx_queue->ptr_mask; 1696 } 1697 1698 /* Get a TX buffer. */ 1699 static inline struct efx_tx_buffer * 1700 __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue) 1701 { 1702 return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)]; 1703 } 1704 1705 /* Get a TX buffer, checking it's not currently in use. */ 1706 static inline struct efx_tx_buffer * 1707 efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue) 1708 { 1709 struct efx_tx_buffer *buffer = 1710 __efx_tx_queue_get_insert_buffer(tx_queue); 1711 1712 EFX_WARN_ON_ONCE_PARANOID(buffer->len); 1713 EFX_WARN_ON_ONCE_PARANOID(buffer->flags); 1714 EFX_WARN_ON_ONCE_PARANOID(buffer->unmap_len); 1715 1716 return buffer; 1717 } 1718 1719 #endif /* EFX_NET_DRIVER_H */ 1720