1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 /* Common definitions for all Efx net driver code */ 12 13 #ifndef EFX_NET_DRIVER_H 14 #define EFX_NET_DRIVER_H 15 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/ethtool.h> 19 #include <linux/if_vlan.h> 20 #include <linux/timer.h> 21 #include <linux/mdio.h> 22 #include <linux/list.h> 23 #include <linux/pci.h> 24 #include <linux/device.h> 25 #include <linux/highmem.h> 26 #include <linux/workqueue.h> 27 #include <linux/mutex.h> 28 #include <linux/rwsem.h> 29 #include <linux/vmalloc.h> 30 #include <linux/i2c.h> 31 #include <linux/mtd/mtd.h> 32 #include <net/busy_poll.h> 33 34 #include "enum.h" 35 #include "bitfield.h" 36 #include "filter.h" 37 38 /************************************************************************** 39 * 40 * Build definitions 41 * 42 **************************************************************************/ 43 44 #define EFX_DRIVER_VERSION "4.0" 45 46 #ifdef DEBUG 47 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) 48 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) 49 #else 50 #define EFX_BUG_ON_PARANOID(x) do {} while (0) 51 #define EFX_WARN_ON_PARANOID(x) do {} while (0) 52 #endif 53 54 /************************************************************************** 55 * 56 * Efx data structures 57 * 58 **************************************************************************/ 59 60 #define EFX_MAX_CHANNELS 32U 61 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS 62 #define EFX_EXTRA_CHANNEL_IOV 0 63 #define EFX_EXTRA_CHANNEL_PTP 1 64 #define EFX_MAX_EXTRA_CHANNELS 2U 65 66 /* Checksum generation is a per-queue option in hardware, so each 67 * queue visible to the networking core is backed by two hardware TX 68 * queues. */ 69 #define EFX_MAX_TX_TC 2 70 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS) 71 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */ 72 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */ 73 #define EFX_TXQ_TYPES 4 74 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS) 75 76 /* Maximum possible MTU the driver supports */ 77 #define EFX_MAX_MTU (9 * 1024) 78 79 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page, 80 * and should be a multiple of the cache line size. 81 */ 82 #define EFX_RX_USR_BUF_SIZE (2048 - 256) 83 84 /* If possible, we should ensure cache line alignment at start and end 85 * of every buffer. Otherwise, we just need to ensure 4-byte 86 * alignment of the network header. 87 */ 88 #if NET_IP_ALIGN == 0 89 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES 90 #else 91 #define EFX_RX_BUF_ALIGNMENT 4 92 #endif 93 94 /* Forward declare Precision Time Protocol (PTP) support structure. */ 95 struct efx_ptp_data; 96 struct hwtstamp_config; 97 98 struct efx_self_tests; 99 100 /** 101 * struct efx_buffer - A general-purpose DMA buffer 102 * @addr: host base address of the buffer 103 * @dma_addr: DMA base address of the buffer 104 * @len: Buffer length, in bytes 105 * 106 * The NIC uses these buffers for its interrupt status registers and 107 * MAC stats dumps. 108 */ 109 struct efx_buffer { 110 void *addr; 111 dma_addr_t dma_addr; 112 unsigned int len; 113 }; 114 115 /** 116 * struct efx_special_buffer - DMA buffer entered into buffer table 117 * @buf: Standard &struct efx_buffer 118 * @index: Buffer index within controller;s buffer table 119 * @entries: Number of buffer table entries 120 * 121 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE. 122 * Event and descriptor rings are addressed via one or more buffer 123 * table entries (and so can be physically non-contiguous, although we 124 * currently do not take advantage of that). On Falcon and Siena we 125 * have to take care of allocating and initialising the entries 126 * ourselves. On later hardware this is managed by the firmware and 127 * @index and @entries are left as 0. 128 */ 129 struct efx_special_buffer { 130 struct efx_buffer buf; 131 unsigned int index; 132 unsigned int entries; 133 }; 134 135 /** 136 * struct efx_tx_buffer - buffer state for a TX descriptor 137 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be 138 * freed when descriptor completes 139 * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be 140 * freed when descriptor completes. 141 * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor. 142 * @dma_addr: DMA address of the fragment. 143 * @flags: Flags for allocation and DMA mapping type 144 * @len: Length of this fragment. 145 * This field is zero when the queue slot is empty. 146 * @unmap_len: Length of this fragment to unmap 147 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping. 148 * Only valid if @unmap_len != 0. 149 */ 150 struct efx_tx_buffer { 151 union { 152 const struct sk_buff *skb; 153 void *heap_buf; 154 }; 155 union { 156 efx_qword_t option; 157 dma_addr_t dma_addr; 158 }; 159 unsigned short flags; 160 unsigned short len; 161 unsigned short unmap_len; 162 unsigned short dma_offset; 163 }; 164 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */ 165 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */ 166 #define EFX_TX_BUF_HEAP 4 /* buffer was allocated with kmalloc() */ 167 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */ 168 #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */ 169 170 /** 171 * struct efx_tx_queue - An Efx TX queue 172 * 173 * This is a ring buffer of TX fragments. 174 * Since the TX completion path always executes on the same 175 * CPU and the xmit path can operate on different CPUs, 176 * performance is increased by ensuring that the completion 177 * path and the xmit path operate on different cache lines. 178 * This is particularly important if the xmit path is always 179 * executing on one CPU which is different from the completion 180 * path. There is also a cache line for members which are 181 * read but not written on the fast path. 182 * 183 * @efx: The associated Efx NIC 184 * @queue: DMA queue number 185 * @channel: The associated channel 186 * @core_txq: The networking core TX queue structure 187 * @buffer: The software buffer ring 188 * @tsoh_page: Array of pages of TSO header buffers 189 * @txd: The hardware descriptor ring 190 * @ptr_mask: The size of the ring minus 1. 191 * @piobuf: PIO buffer region for this TX queue (shared with its partner). 192 * Size of the region is efx_piobuf_size. 193 * @piobuf_offset: Buffer offset to be specified in PIO descriptors 194 * @initialised: Has hardware queue been initialised? 195 * @read_count: Current read pointer. 196 * This is the number of buffers that have been removed from both rings. 197 * @old_write_count: The value of @write_count when last checked. 198 * This is here for performance reasons. The xmit path will 199 * only get the up-to-date value of @write_count if this 200 * variable indicates that the queue is empty. This is to 201 * avoid cache-line ping-pong between the xmit path and the 202 * completion path. 203 * @merge_events: Number of TX merged completion events 204 * @insert_count: Current insert pointer 205 * This is the number of buffers that have been added to the 206 * software ring. 207 * @write_count: Current write pointer 208 * This is the number of buffers that have been added to the 209 * hardware ring. 210 * @old_read_count: The value of read_count when last checked. 211 * This is here for performance reasons. The xmit path will 212 * only get the up-to-date value of read_count if this 213 * variable indicates that the queue is full. This is to 214 * avoid cache-line ping-pong between the xmit path and the 215 * completion path. 216 * @tso_bursts: Number of times TSO xmit invoked by kernel 217 * @tso_long_headers: Number of packets with headers too long for standard 218 * blocks 219 * @tso_packets: Number of packets via the TSO xmit path 220 * @pushes: Number of times the TX push feature has been used 221 * @pio_packets: Number of times the TX PIO feature has been used 222 * @empty_read_count: If the completion path has seen the queue as empty 223 * and the transmission path has not yet checked this, the value of 224 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0. 225 */ 226 struct efx_tx_queue { 227 /* Members which don't change on the fast path */ 228 struct efx_nic *efx ____cacheline_aligned_in_smp; 229 unsigned queue; 230 struct efx_channel *channel; 231 struct netdev_queue *core_txq; 232 struct efx_tx_buffer *buffer; 233 struct efx_buffer *tsoh_page; 234 struct efx_special_buffer txd; 235 unsigned int ptr_mask; 236 void __iomem *piobuf; 237 unsigned int piobuf_offset; 238 bool initialised; 239 240 /* Members used mainly on the completion path */ 241 unsigned int read_count ____cacheline_aligned_in_smp; 242 unsigned int old_write_count; 243 unsigned int merge_events; 244 245 /* Members used only on the xmit path */ 246 unsigned int insert_count ____cacheline_aligned_in_smp; 247 unsigned int write_count; 248 unsigned int old_read_count; 249 unsigned int tso_bursts; 250 unsigned int tso_long_headers; 251 unsigned int tso_packets; 252 unsigned int pushes; 253 unsigned int pio_packets; 254 /* Statistics to supplement MAC stats */ 255 unsigned long tx_packets; 256 257 /* Members shared between paths and sometimes updated */ 258 unsigned int empty_read_count ____cacheline_aligned_in_smp; 259 #define EFX_EMPTY_COUNT_VALID 0x80000000 260 atomic_t flush_outstanding; 261 }; 262 263 /** 264 * struct efx_rx_buffer - An Efx RX data buffer 265 * @dma_addr: DMA base address of the buffer 266 * @page: The associated page buffer. 267 * Will be %NULL if the buffer slot is currently free. 268 * @page_offset: If pending: offset in @page of DMA base address. 269 * If completed: offset in @page of Ethernet header. 270 * @len: If pending: length for DMA descriptor. 271 * If completed: received length, excluding hash prefix. 272 * @flags: Flags for buffer and packet state. These are only set on the 273 * first buffer of a scattered packet. 274 */ 275 struct efx_rx_buffer { 276 dma_addr_t dma_addr; 277 struct page *page; 278 u16 page_offset; 279 u16 len; 280 u16 flags; 281 }; 282 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001 283 #define EFX_RX_PKT_CSUMMED 0x0002 284 #define EFX_RX_PKT_DISCARD 0x0004 285 #define EFX_RX_PKT_TCP 0x0040 286 #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */ 287 288 /** 289 * struct efx_rx_page_state - Page-based rx buffer state 290 * 291 * Inserted at the start of every page allocated for receive buffers. 292 * Used to facilitate sharing dma mappings between recycled rx buffers 293 * and those passed up to the kernel. 294 * 295 * @dma_addr: The dma address of this page. 296 */ 297 struct efx_rx_page_state { 298 dma_addr_t dma_addr; 299 300 unsigned int __pad[0] ____cacheline_aligned; 301 }; 302 303 /** 304 * struct efx_rx_queue - An Efx RX queue 305 * @efx: The associated Efx NIC 306 * @core_index: Index of network core RX queue. Will be >= 0 iff this 307 * is associated with a real RX queue. 308 * @buffer: The software buffer ring 309 * @rxd: The hardware descriptor ring 310 * @ptr_mask: The size of the ring minus 1. 311 * @refill_enabled: Enable refill whenever fill level is low 312 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as 313 * @rxq_flush_pending. 314 * @added_count: Number of buffers added to the receive queue. 315 * @notified_count: Number of buffers given to NIC (<= @added_count). 316 * @removed_count: Number of buffers removed from the receive queue. 317 * @scatter_n: Used by NIC specific receive code. 318 * @scatter_len: Used by NIC specific receive code. 319 * @page_ring: The ring to store DMA mapped pages for reuse. 320 * @page_add: Counter to calculate the write pointer for the recycle ring. 321 * @page_remove: Counter to calculate the read pointer for the recycle ring. 322 * @page_recycle_count: The number of pages that have been recycled. 323 * @page_recycle_failed: The number of pages that couldn't be recycled because 324 * the kernel still held a reference to them. 325 * @page_recycle_full: The number of pages that were released because the 326 * recycle ring was full. 327 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1. 328 * @max_fill: RX descriptor maximum fill level (<= ring size) 329 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill 330 * (<= @max_fill) 331 * @min_fill: RX descriptor minimum non-zero fill level. 332 * This records the minimum fill level observed when a ring 333 * refill was triggered. 334 * @recycle_count: RX buffer recycle counter. 335 * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). 336 */ 337 struct efx_rx_queue { 338 struct efx_nic *efx; 339 int core_index; 340 struct efx_rx_buffer *buffer; 341 struct efx_special_buffer rxd; 342 unsigned int ptr_mask; 343 bool refill_enabled; 344 bool flush_pending; 345 346 unsigned int added_count; 347 unsigned int notified_count; 348 unsigned int removed_count; 349 unsigned int scatter_n; 350 unsigned int scatter_len; 351 struct page **page_ring; 352 unsigned int page_add; 353 unsigned int page_remove; 354 unsigned int page_recycle_count; 355 unsigned int page_recycle_failed; 356 unsigned int page_recycle_full; 357 unsigned int page_ptr_mask; 358 unsigned int max_fill; 359 unsigned int fast_fill_trigger; 360 unsigned int min_fill; 361 unsigned int min_overfill; 362 unsigned int recycle_count; 363 struct timer_list slow_fill; 364 unsigned int slow_fill_count; 365 /* Statistics to supplement MAC stats */ 366 unsigned long rx_packets; 367 }; 368 369 enum efx_sync_events_state { 370 SYNC_EVENTS_DISABLED = 0, 371 SYNC_EVENTS_QUIESCENT, 372 SYNC_EVENTS_REQUESTED, 373 SYNC_EVENTS_VALID, 374 }; 375 376 /** 377 * struct efx_channel - An Efx channel 378 * 379 * A channel comprises an event queue, at least one TX queue, at least 380 * one RX queue, and an associated tasklet for processing the event 381 * queue. 382 * 383 * @efx: Associated Efx NIC 384 * @channel: Channel instance number 385 * @type: Channel type definition 386 * @eventq_init: Event queue initialised flag 387 * @enabled: Channel enabled indicator 388 * @irq: IRQ number (MSI and MSI-X only) 389 * @irq_moderation: IRQ moderation value (in hardware ticks) 390 * @napi_dev: Net device used with NAPI 391 * @napi_str: NAPI control structure 392 * @state: state for NAPI vs busy polling 393 * @state_lock: lock protecting @state 394 * @eventq: Event queue buffer 395 * @eventq_mask: Event queue pointer mask 396 * @eventq_read_ptr: Event queue read pointer 397 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel 398 * @irq_count: Number of IRQs since last adaptive moderation decision 399 * @irq_mod_score: IRQ moderation score 400 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors 401 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors 402 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors 403 * @n_rx_mcast_mismatch: Count of unmatched multicast frames 404 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors 405 * @n_rx_overlength: Count of RX_OVERLENGTH errors 406 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun 407 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to 408 * lack of descriptors 409 * @n_rx_merge_events: Number of RX merged completion events 410 * @n_rx_merge_packets: Number of RX packets completed by merged events 411 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by 412 * __efx_rx_packet(), or zero if there is none 413 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered 414 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0 415 * @rx_queue: RX queue for this channel 416 * @tx_queue: TX queues for this channel 417 * @sync_events_state: Current state of sync events on this channel 418 * @sync_timestamp_major: Major part of the last ptp sync event 419 * @sync_timestamp_minor: Minor part of the last ptp sync event 420 */ 421 struct efx_channel { 422 struct efx_nic *efx; 423 int channel; 424 const struct efx_channel_type *type; 425 bool eventq_init; 426 bool enabled; 427 int irq; 428 unsigned int irq_moderation; 429 struct net_device *napi_dev; 430 struct napi_struct napi_str; 431 #ifdef CONFIG_NET_RX_BUSY_POLL 432 unsigned int state; 433 spinlock_t state_lock; 434 #define EFX_CHANNEL_STATE_IDLE 0 435 #define EFX_CHANNEL_STATE_NAPI (1 << 0) /* NAPI owns this channel */ 436 #define EFX_CHANNEL_STATE_POLL (1 << 1) /* poll owns this channel */ 437 #define EFX_CHANNEL_STATE_DISABLED (1 << 2) /* channel is disabled */ 438 #define EFX_CHANNEL_STATE_NAPI_YIELD (1 << 3) /* NAPI yielded this channel */ 439 #define EFX_CHANNEL_STATE_POLL_YIELD (1 << 4) /* poll yielded this channel */ 440 #define EFX_CHANNEL_OWNED \ 441 (EFX_CHANNEL_STATE_NAPI | EFX_CHANNEL_STATE_POLL) 442 #define EFX_CHANNEL_LOCKED \ 443 (EFX_CHANNEL_OWNED | EFX_CHANNEL_STATE_DISABLED) 444 #define EFX_CHANNEL_USER_PEND \ 445 (EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_POLL_YIELD) 446 #endif /* CONFIG_NET_RX_BUSY_POLL */ 447 struct efx_special_buffer eventq; 448 unsigned int eventq_mask; 449 unsigned int eventq_read_ptr; 450 int event_test_cpu; 451 452 unsigned int irq_count; 453 unsigned int irq_mod_score; 454 #ifdef CONFIG_RFS_ACCEL 455 unsigned int rfs_filters_added; 456 #endif 457 458 unsigned n_rx_tobe_disc; 459 unsigned n_rx_ip_hdr_chksum_err; 460 unsigned n_rx_tcp_udp_chksum_err; 461 unsigned n_rx_mcast_mismatch; 462 unsigned n_rx_frm_trunc; 463 unsigned n_rx_overlength; 464 unsigned n_skbuff_leaks; 465 unsigned int n_rx_nodesc_trunc; 466 unsigned int n_rx_merge_events; 467 unsigned int n_rx_merge_packets; 468 469 unsigned int rx_pkt_n_frags; 470 unsigned int rx_pkt_index; 471 472 struct efx_rx_queue rx_queue; 473 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES]; 474 475 enum efx_sync_events_state sync_events_state; 476 u32 sync_timestamp_major; 477 u32 sync_timestamp_minor; 478 }; 479 480 #ifdef CONFIG_NET_RX_BUSY_POLL 481 static inline void efx_channel_init_lock(struct efx_channel *channel) 482 { 483 spin_lock_init(&channel->state_lock); 484 } 485 486 /* Called from the device poll routine to get ownership of a channel. */ 487 static inline bool efx_channel_lock_napi(struct efx_channel *channel) 488 { 489 bool rc = true; 490 491 spin_lock_bh(&channel->state_lock); 492 if (channel->state & EFX_CHANNEL_LOCKED) { 493 WARN_ON(channel->state & EFX_CHANNEL_STATE_NAPI); 494 channel->state |= EFX_CHANNEL_STATE_NAPI_YIELD; 495 rc = false; 496 } else { 497 /* we don't care if someone yielded */ 498 channel->state = EFX_CHANNEL_STATE_NAPI; 499 } 500 spin_unlock_bh(&channel->state_lock); 501 return rc; 502 } 503 504 static inline void efx_channel_unlock_napi(struct efx_channel *channel) 505 { 506 spin_lock_bh(&channel->state_lock); 507 WARN_ON(channel->state & 508 (EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_NAPI_YIELD)); 509 510 channel->state &= EFX_CHANNEL_STATE_DISABLED; 511 spin_unlock_bh(&channel->state_lock); 512 } 513 514 /* Called from efx_busy_poll(). */ 515 static inline bool efx_channel_lock_poll(struct efx_channel *channel) 516 { 517 bool rc = true; 518 519 spin_lock_bh(&channel->state_lock); 520 if ((channel->state & EFX_CHANNEL_LOCKED)) { 521 channel->state |= EFX_CHANNEL_STATE_POLL_YIELD; 522 rc = false; 523 } else { 524 /* preserve yield marks */ 525 channel->state |= EFX_CHANNEL_STATE_POLL; 526 } 527 spin_unlock_bh(&channel->state_lock); 528 return rc; 529 } 530 531 /* Returns true if NAPI tried to get the channel while it was locked. */ 532 static inline void efx_channel_unlock_poll(struct efx_channel *channel) 533 { 534 spin_lock_bh(&channel->state_lock); 535 WARN_ON(channel->state & EFX_CHANNEL_STATE_NAPI); 536 537 /* will reset state to idle, unless channel is disabled */ 538 channel->state &= EFX_CHANNEL_STATE_DISABLED; 539 spin_unlock_bh(&channel->state_lock); 540 } 541 542 /* True if a socket is polling, even if it did not get the lock. */ 543 static inline bool efx_channel_busy_polling(struct efx_channel *channel) 544 { 545 WARN_ON(!(channel->state & EFX_CHANNEL_OWNED)); 546 return channel->state & EFX_CHANNEL_USER_PEND; 547 } 548 549 static inline void efx_channel_enable(struct efx_channel *channel) 550 { 551 spin_lock_bh(&channel->state_lock); 552 channel->state = EFX_CHANNEL_STATE_IDLE; 553 spin_unlock_bh(&channel->state_lock); 554 } 555 556 /* False if the channel is currently owned. */ 557 static inline bool efx_channel_disable(struct efx_channel *channel) 558 { 559 bool rc = true; 560 561 spin_lock_bh(&channel->state_lock); 562 if (channel->state & EFX_CHANNEL_OWNED) 563 rc = false; 564 channel->state |= EFX_CHANNEL_STATE_DISABLED; 565 spin_unlock_bh(&channel->state_lock); 566 567 return rc; 568 } 569 570 #else /* CONFIG_NET_RX_BUSY_POLL */ 571 572 static inline void efx_channel_init_lock(struct efx_channel *channel) 573 { 574 } 575 576 static inline bool efx_channel_lock_napi(struct efx_channel *channel) 577 { 578 return true; 579 } 580 581 static inline void efx_channel_unlock_napi(struct efx_channel *channel) 582 { 583 } 584 585 static inline bool efx_channel_lock_poll(struct efx_channel *channel) 586 { 587 return false; 588 } 589 590 static inline void efx_channel_unlock_poll(struct efx_channel *channel) 591 { 592 } 593 594 static inline bool efx_channel_busy_polling(struct efx_channel *channel) 595 { 596 return false; 597 } 598 599 static inline void efx_channel_enable(struct efx_channel *channel) 600 { 601 } 602 603 static inline bool efx_channel_disable(struct efx_channel *channel) 604 { 605 return true; 606 } 607 #endif /* CONFIG_NET_RX_BUSY_POLL */ 608 609 /** 610 * struct efx_msi_context - Context for each MSI 611 * @efx: The associated NIC 612 * @index: Index of the channel/IRQ 613 * @name: Name of the channel/IRQ 614 * 615 * Unlike &struct efx_channel, this is never reallocated and is always 616 * safe for the IRQ handler to access. 617 */ 618 struct efx_msi_context { 619 struct efx_nic *efx; 620 unsigned int index; 621 char name[IFNAMSIZ + 6]; 622 }; 623 624 /** 625 * struct efx_channel_type - distinguishes traffic and extra channels 626 * @handle_no_channel: Handle failure to allocate an extra channel 627 * @pre_probe: Set up extra state prior to initialisation 628 * @post_remove: Tear down extra state after finalisation, if allocated. 629 * May be called on channels that have not been probed. 630 * @get_name: Generate the channel's name (used for its IRQ handler) 631 * @copy: Copy the channel state prior to reallocation. May be %NULL if 632 * reallocation is not supported. 633 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb() 634 * @keep_eventq: Flag for whether event queue should be kept initialised 635 * while the device is stopped 636 */ 637 struct efx_channel_type { 638 void (*handle_no_channel)(struct efx_nic *); 639 int (*pre_probe)(struct efx_channel *); 640 void (*post_remove)(struct efx_channel *); 641 void (*get_name)(struct efx_channel *, char *buf, size_t len); 642 struct efx_channel *(*copy)(const struct efx_channel *); 643 bool (*receive_skb)(struct efx_channel *, struct sk_buff *); 644 bool keep_eventq; 645 }; 646 647 enum efx_led_mode { 648 EFX_LED_OFF = 0, 649 EFX_LED_ON = 1, 650 EFX_LED_DEFAULT = 2 651 }; 652 653 #define STRING_TABLE_LOOKUP(val, member) \ 654 ((val) < member ## _max) ? member ## _names[val] : "(invalid)" 655 656 extern const char *const efx_loopback_mode_names[]; 657 extern const unsigned int efx_loopback_mode_max; 658 #define LOOPBACK_MODE(efx) \ 659 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) 660 661 extern const char *const efx_reset_type_names[]; 662 extern const unsigned int efx_reset_type_max; 663 #define RESET_TYPE(type) \ 664 STRING_TABLE_LOOKUP(type, efx_reset_type) 665 666 enum efx_int_mode { 667 /* Be careful if altering to correct macro below */ 668 EFX_INT_MODE_MSIX = 0, 669 EFX_INT_MODE_MSI = 1, 670 EFX_INT_MODE_LEGACY = 2, 671 EFX_INT_MODE_MAX /* Insert any new items before this */ 672 }; 673 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) 674 675 enum nic_state { 676 STATE_UNINIT = 0, /* device being probed/removed or is frozen */ 677 STATE_READY = 1, /* hardware ready and netdev registered */ 678 STATE_DISABLED = 2, /* device disabled due to hardware errors */ 679 STATE_RECOVERY = 3, /* device recovering from PCI error */ 680 }; 681 682 /* Forward declaration */ 683 struct efx_nic; 684 685 /* Pseudo bit-mask flow control field */ 686 #define EFX_FC_RX FLOW_CTRL_RX 687 #define EFX_FC_TX FLOW_CTRL_TX 688 #define EFX_FC_AUTO 4 689 690 /** 691 * struct efx_link_state - Current state of the link 692 * @up: Link is up 693 * @fd: Link is full-duplex 694 * @fc: Actual flow control flags 695 * @speed: Link speed (Mbps) 696 */ 697 struct efx_link_state { 698 bool up; 699 bool fd; 700 u8 fc; 701 unsigned int speed; 702 }; 703 704 static inline bool efx_link_state_equal(const struct efx_link_state *left, 705 const struct efx_link_state *right) 706 { 707 return left->up == right->up && left->fd == right->fd && 708 left->fc == right->fc && left->speed == right->speed; 709 } 710 711 /** 712 * struct efx_phy_operations - Efx PHY operations table 713 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, 714 * efx->loopback_modes. 715 * @init: Initialise PHY 716 * @fini: Shut down PHY 717 * @reconfigure: Reconfigure PHY (e.g. for new link parameters) 718 * @poll: Update @link_state and report whether it changed. 719 * Serialised by the mac_lock. 720 * @get_settings: Get ethtool settings. Serialised by the mac_lock. 721 * @set_settings: Set ethtool settings. Serialised by the mac_lock. 722 * @set_npage_adv: Set abilities advertised in (Extended) Next Page 723 * (only needed where AN bit is set in mmds) 724 * @test_alive: Test that PHY is 'alive' (online) 725 * @test_name: Get the name of a PHY-specific test/result 726 * @run_tests: Run tests and record results as appropriate (offline). 727 * Flags are the ethtool tests flags. 728 */ 729 struct efx_phy_operations { 730 int (*probe) (struct efx_nic *efx); 731 int (*init) (struct efx_nic *efx); 732 void (*fini) (struct efx_nic *efx); 733 void (*remove) (struct efx_nic *efx); 734 int (*reconfigure) (struct efx_nic *efx); 735 bool (*poll) (struct efx_nic *efx); 736 void (*get_settings) (struct efx_nic *efx, 737 struct ethtool_cmd *ecmd); 738 int (*set_settings) (struct efx_nic *efx, 739 struct ethtool_cmd *ecmd); 740 void (*set_npage_adv) (struct efx_nic *efx, u32); 741 int (*test_alive) (struct efx_nic *efx); 742 const char *(*test_name) (struct efx_nic *efx, unsigned int index); 743 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); 744 int (*get_module_eeprom) (struct efx_nic *efx, 745 struct ethtool_eeprom *ee, 746 u8 *data); 747 int (*get_module_info) (struct efx_nic *efx, 748 struct ethtool_modinfo *modinfo); 749 }; 750 751 /** 752 * enum efx_phy_mode - PHY operating mode flags 753 * @PHY_MODE_NORMAL: on and should pass traffic 754 * @PHY_MODE_TX_DISABLED: on with TX disabled 755 * @PHY_MODE_LOW_POWER: set to low power through MDIO 756 * @PHY_MODE_OFF: switched off through external control 757 * @PHY_MODE_SPECIAL: on but will not pass traffic 758 */ 759 enum efx_phy_mode { 760 PHY_MODE_NORMAL = 0, 761 PHY_MODE_TX_DISABLED = 1, 762 PHY_MODE_LOW_POWER = 2, 763 PHY_MODE_OFF = 4, 764 PHY_MODE_SPECIAL = 8, 765 }; 766 767 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) 768 { 769 return !!(mode & ~PHY_MODE_TX_DISABLED); 770 } 771 772 /** 773 * struct efx_hw_stat_desc - Description of a hardware statistic 774 * @name: Name of the statistic as visible through ethtool, or %NULL if 775 * it should not be exposed 776 * @dma_width: Width in bits (0 for non-DMA statistics) 777 * @offset: Offset within stats (ignored for non-DMA statistics) 778 */ 779 struct efx_hw_stat_desc { 780 const char *name; 781 u16 dma_width; 782 u16 offset; 783 }; 784 785 /* Number of bits used in a multicast filter hash address */ 786 #define EFX_MCAST_HASH_BITS 8 787 788 /* Number of (single-bit) entries in a multicast filter hash */ 789 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) 790 791 /* An Efx multicast filter hash */ 792 union efx_multicast_hash { 793 u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; 794 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; 795 }; 796 797 struct vfdi_status; 798 799 /** 800 * struct efx_nic - an Efx NIC 801 * @name: Device name (net device name or bus id before net device registered) 802 * @pci_dev: The PCI device 803 * @node: List node for maintaning primary/secondary function lists 804 * @primary: &struct efx_nic instance for the primary function of this 805 * controller. May be the same structure, and may be %NULL if no 806 * primary function is bound. Serialised by rtnl_lock. 807 * @secondary_list: List of &struct efx_nic instances for the secondary PCI 808 * functions of the controller, if this is for the primary function. 809 * Serialised by rtnl_lock. 810 * @type: Controller type attributes 811 * @legacy_irq: IRQ number 812 * @workqueue: Workqueue for port reconfigures and the HW monitor. 813 * Work items do not hold and must not acquire RTNL. 814 * @workqueue_name: Name of workqueue 815 * @reset_work: Scheduled reset workitem 816 * @membase_phys: Memory BAR value as physical address 817 * @membase: Memory BAR value 818 * @interrupt_mode: Interrupt mode 819 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds 820 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues 821 * @irq_rx_moderation: IRQ moderation time for RX event queues 822 * @msg_enable: Log message enable flags 823 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock. 824 * @reset_pending: Bitmask for pending resets 825 * @tx_queue: TX DMA queues 826 * @rx_queue: RX DMA queues 827 * @channel: Channels 828 * @msi_context: Context for each MSI 829 * @extra_channel_types: Types of extra (non-traffic) channels that 830 * should be allocated for this NIC 831 * @rxq_entries: Size of receive queues requested by user. 832 * @txq_entries: Size of transmit queues requested by user. 833 * @txq_stop_thresh: TX queue fill level at or above which we stop it. 834 * @txq_wake_thresh: TX queue fill level at or below which we wake it. 835 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches 836 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches 837 * @sram_lim_qw: Qword address limit of SRAM 838 * @next_buffer_table: First available buffer table id 839 * @n_channels: Number of channels in use 840 * @n_rx_channels: Number of channels used for RX (= number of RX queues) 841 * @n_tx_channels: Number of channels used for TX 842 * @rx_ip_align: RX DMA address offset to have IP header aligned in 843 * in accordance with NET_IP_ALIGN 844 * @rx_dma_len: Current maximum RX DMA length 845 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer 846 * @rx_buffer_truesize: Amortised allocation size of an RX buffer, 847 * for use in sk_buff::truesize 848 * @rx_prefix_size: Size of RX prefix before packet data 849 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data 850 * (valid only if @rx_prefix_size != 0; always negative) 851 * @rx_packet_len_offset: Offset of RX packet length from start of packet data 852 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative) 853 * @rx_packet_ts_offset: Offset of timestamp from start of packet data 854 * (valid only if channel->sync_timestamps_enabled; always negative) 855 * @rx_hash_key: Toeplitz hash key for RSS 856 * @rx_indir_table: Indirection table for RSS 857 * @rx_scatter: Scatter mode enabled for receives 858 * @int_error_count: Number of internal errors seen recently 859 * @int_error_expire: Time at which error count will be expired 860 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will 861 * acknowledge but do nothing else. 862 * @irq_status: Interrupt status buffer 863 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 864 * @irq_level: IRQ level/index for IRQs not triggered by an event queue 865 * @selftest_work: Work item for asynchronous self-test 866 * @mtd_list: List of MTDs attached to the NIC 867 * @nic_data: Hardware dependent state 868 * @mcdi: Management-Controller-to-Driver Interface state 869 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, 870 * efx_monitor() and efx_reconfigure_port() 871 * @port_enabled: Port enabled indicator. 872 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and 873 * efx_mac_work() with kernel interfaces. Safe to read under any 874 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must 875 * be held to modify it. 876 * @port_initialized: Port initialized? 877 * @net_dev: Operating system network device. Consider holding the rtnl lock 878 * @stats_buffer: DMA buffer for statistics 879 * @phy_type: PHY type 880 * @phy_op: PHY interface 881 * @phy_data: PHY private data (including PHY-specific stats) 882 * @mdio: PHY MDIO interface 883 * @mdio_bus: PHY MDIO bus ID (only used by Siena) 884 * @phy_mode: PHY operating mode. Serialised by @mac_lock. 885 * @link_advertising: Autonegotiation advertising flags 886 * @link_state: Current state of the link 887 * @n_link_state_changes: Number of times the link has changed state 888 * @unicast_filter: Flag for Falcon-arch simple unicast filter. 889 * Protected by @mac_lock. 890 * @multicast_hash: Multicast hash table for Falcon-arch. 891 * Protected by @mac_lock. 892 * @wanted_fc: Wanted flow control flags 893 * @fc_disable: When non-zero flow control is disabled. Typically used to 894 * ensure that network back pressure doesn't delay dma queue flushes. 895 * Serialised by the rtnl lock. 896 * @mac_work: Work item for changing MAC promiscuity and multicast hash 897 * @loopback_mode: Loopback status 898 * @loopback_modes: Supported loopback mode bitmask 899 * @loopback_selftest: Offline self-test private state 900 * @filter_sem: Filter table rw_semaphore, for freeing the table 901 * @filter_lock: Filter table lock, for mere content changes 902 * @filter_state: Architecture-dependent filter table state 903 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS, 904 * indexed by filter ID 905 * @rps_expire_index: Next index to check for expiry in @rps_flow_id 906 * @active_queues: Count of RX and TX queues that haven't been flushed and drained. 907 * @rxq_flush_pending: Count of number of receive queues that need to be flushed. 908 * Decremented when the efx_flush_rx_queue() is called. 909 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet 910 * completed (either success or failure). Not used when MCDI is used to 911 * flush receive queues. 912 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions. 913 * @vf_count: Number of VFs intended to be enabled. 914 * @vf_init_count: Number of VFs that have been fully initialised. 915 * @vi_scale: log2 number of vnics per VF. 916 * @ptp_data: PTP state data 917 * @vpd_sn: Serial number read from VPD 918 * @monitor_work: Hardware monitor workitem 919 * @biu_lock: BIU (bus interface unit) lock 920 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This 921 * field is used by efx_test_interrupts() to verify that an 922 * interrupt has occurred. 923 * @stats_lock: Statistics update lock. Must be held when calling 924 * efx_nic_type::{update,start,stop}_stats. 925 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb 926 * 927 * This is stored in the private area of the &struct net_device. 928 */ 929 struct efx_nic { 930 /* The following fields should be written very rarely */ 931 932 char name[IFNAMSIZ]; 933 struct list_head node; 934 struct efx_nic *primary; 935 struct list_head secondary_list; 936 struct pci_dev *pci_dev; 937 unsigned int port_num; 938 const struct efx_nic_type *type; 939 int legacy_irq; 940 bool eeh_disabled_legacy_irq; 941 struct workqueue_struct *workqueue; 942 char workqueue_name[16]; 943 struct work_struct reset_work; 944 resource_size_t membase_phys; 945 void __iomem *membase; 946 947 enum efx_int_mode interrupt_mode; 948 unsigned int timer_quantum_ns; 949 bool irq_rx_adaptive; 950 unsigned int irq_rx_moderation; 951 u32 msg_enable; 952 953 enum nic_state state; 954 unsigned long reset_pending; 955 956 struct efx_channel *channel[EFX_MAX_CHANNELS]; 957 struct efx_msi_context msi_context[EFX_MAX_CHANNELS]; 958 const struct efx_channel_type * 959 extra_channel_type[EFX_MAX_EXTRA_CHANNELS]; 960 961 unsigned rxq_entries; 962 unsigned txq_entries; 963 unsigned int txq_stop_thresh; 964 unsigned int txq_wake_thresh; 965 966 unsigned tx_dc_base; 967 unsigned rx_dc_base; 968 unsigned sram_lim_qw; 969 unsigned next_buffer_table; 970 971 unsigned int max_channels; 972 unsigned n_channels; 973 unsigned n_rx_channels; 974 unsigned rss_spread; 975 unsigned tx_channel_offset; 976 unsigned n_tx_channels; 977 unsigned int rx_ip_align; 978 unsigned int rx_dma_len; 979 unsigned int rx_buffer_order; 980 unsigned int rx_buffer_truesize; 981 unsigned int rx_page_buf_step; 982 unsigned int rx_bufs_per_page; 983 unsigned int rx_pages_per_batch; 984 unsigned int rx_prefix_size; 985 int rx_packet_hash_offset; 986 int rx_packet_len_offset; 987 int rx_packet_ts_offset; 988 u8 rx_hash_key[40]; 989 u32 rx_indir_table[128]; 990 bool rx_scatter; 991 992 unsigned int_error_count; 993 unsigned long int_error_expire; 994 995 bool irq_soft_enabled; 996 struct efx_buffer irq_status; 997 unsigned irq_zero_count; 998 unsigned irq_level; 999 struct delayed_work selftest_work; 1000 1001 #ifdef CONFIG_SFC_MTD 1002 struct list_head mtd_list; 1003 #endif 1004 1005 void *nic_data; 1006 struct efx_mcdi_data *mcdi; 1007 1008 struct mutex mac_lock; 1009 struct work_struct mac_work; 1010 bool port_enabled; 1011 1012 bool mc_bist_for_other_fn; 1013 bool port_initialized; 1014 struct net_device *net_dev; 1015 1016 struct efx_buffer stats_buffer; 1017 u64 rx_nodesc_drops_total; 1018 u64 rx_nodesc_drops_while_down; 1019 bool rx_nodesc_drops_prev_state; 1020 1021 unsigned int phy_type; 1022 const struct efx_phy_operations *phy_op; 1023 void *phy_data; 1024 struct mdio_if_info mdio; 1025 unsigned int mdio_bus; 1026 enum efx_phy_mode phy_mode; 1027 1028 u32 link_advertising; 1029 struct efx_link_state link_state; 1030 unsigned int n_link_state_changes; 1031 1032 bool unicast_filter; 1033 union efx_multicast_hash multicast_hash; 1034 u8 wanted_fc; 1035 unsigned fc_disable; 1036 1037 atomic_t rx_reset; 1038 enum efx_loopback_mode loopback_mode; 1039 u64 loopback_modes; 1040 1041 void *loopback_selftest; 1042 1043 struct rw_semaphore filter_sem; 1044 spinlock_t filter_lock; 1045 void *filter_state; 1046 #ifdef CONFIG_RFS_ACCEL 1047 u32 *rps_flow_id; 1048 unsigned int rps_expire_index; 1049 #endif 1050 1051 atomic_t active_queues; 1052 atomic_t rxq_flush_pending; 1053 atomic_t rxq_flush_outstanding; 1054 wait_queue_head_t flush_wq; 1055 1056 #ifdef CONFIG_SFC_SRIOV 1057 unsigned vf_count; 1058 unsigned vf_init_count; 1059 unsigned vi_scale; 1060 #endif 1061 1062 struct efx_ptp_data *ptp_data; 1063 1064 char *vpd_sn; 1065 1066 /* The following fields may be written more often */ 1067 1068 struct delayed_work monitor_work ____cacheline_aligned_in_smp; 1069 spinlock_t biu_lock; 1070 int last_irq_cpu; 1071 spinlock_t stats_lock; 1072 atomic_t n_rx_noskb_drops; 1073 }; 1074 1075 static inline int efx_dev_registered(struct efx_nic *efx) 1076 { 1077 return efx->net_dev->reg_state == NETREG_REGISTERED; 1078 } 1079 1080 static inline unsigned int efx_port_num(struct efx_nic *efx) 1081 { 1082 return efx->port_num; 1083 } 1084 1085 struct efx_mtd_partition { 1086 struct list_head node; 1087 struct mtd_info mtd; 1088 const char *dev_type_name; 1089 const char *type_name; 1090 char name[IFNAMSIZ + 20]; 1091 }; 1092 1093 /** 1094 * struct efx_nic_type - Efx device type definition 1095 * @mem_bar: Get the memory BAR 1096 * @mem_map_size: Get memory BAR mapped size 1097 * @probe: Probe the controller 1098 * @remove: Free resources allocated by probe() 1099 * @init: Initialise the controller 1100 * @dimension_resources: Dimension controller resources (buffer table, 1101 * and VIs once the available interrupt resources are clear) 1102 * @fini: Shut down the controller 1103 * @monitor: Periodic function for polling link state and hardware monitor 1104 * @map_reset_reason: Map ethtool reset reason to a reset method 1105 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible 1106 * @reset: Reset the controller hardware and possibly the PHY. This will 1107 * be called while the controller is uninitialised. 1108 * @probe_port: Probe the MAC and PHY 1109 * @remove_port: Free resources allocated by probe_port() 1110 * @handle_global_event: Handle a "global" event (may be %NULL) 1111 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues) 1112 * @prepare_flush: Prepare the hardware for flushing the DMA queues 1113 * (for Falcon architecture) 1114 * @finish_flush: Clean up after flushing the DMA queues (for Falcon 1115 * architecture) 1116 * @prepare_flr: Prepare for an FLR 1117 * @finish_flr: Clean up after an FLR 1118 * @describe_stats: Describe statistics for ethtool 1119 * @update_stats: Update statistics not provided by event handling. 1120 * Either argument may be %NULL. 1121 * @start_stats: Start the regular fetching of statistics 1122 * @pull_stats: Pull stats from the NIC and wait until they arrive. 1123 * @stop_stats: Stop the regular fetching of statistics 1124 * @set_id_led: Set state of identifying LED or revert to automatic function 1125 * @push_irq_moderation: Apply interrupt moderation value 1126 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY 1127 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL) 1128 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings 1129 * to the hardware. Serialised by the mac_lock. 1130 * @check_mac_fault: Check MAC fault state. True if fault present. 1131 * @get_wol: Get WoL configuration from driver state 1132 * @set_wol: Push WoL configuration to the NIC 1133 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) 1134 * @test_chip: Test registers. May use efx_farch_test_registers(), and is 1135 * expected to reset the NIC. 1136 * @test_nvram: Test validity of NVRAM contents 1137 * @mcdi_request: Send an MCDI request with the given header and SDU. 1138 * The SDU length may be any value from 0 up to the protocol- 1139 * defined maximum, but its buffer will be padded to a multiple 1140 * of 4 bytes. 1141 * @mcdi_poll_response: Test whether an MCDI response is available. 1142 * @mcdi_read_response: Read the MCDI response PDU. The offset will 1143 * be a multiple of 4. The length may not be, but the buffer 1144 * will be padded so it is safe to round up. 1145 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so, 1146 * return an appropriate error code for aborting any current 1147 * request; otherwise return 0. 1148 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must 1149 * be separately enabled after this. 1150 * @irq_test_generate: Generate a test IRQ 1151 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event 1152 * queue must be separately disabled before this. 1153 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is 1154 * a pointer to the &struct efx_msi_context for the channel. 1155 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument 1156 * is a pointer to the &struct efx_nic. 1157 * @tx_probe: Allocate resources for TX queue 1158 * @tx_init: Initialise TX queue on the NIC 1159 * @tx_remove: Free resources for TX queue 1160 * @tx_write: Write TX descriptors and doorbell 1161 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC 1162 * @rx_probe: Allocate resources for RX queue 1163 * @rx_init: Initialise RX queue on the NIC 1164 * @rx_remove: Free resources for RX queue 1165 * @rx_write: Write RX descriptors and doorbell 1166 * @rx_defer_refill: Generate a refill reminder event 1167 * @ev_probe: Allocate resources for event queue 1168 * @ev_init: Initialise event queue on the NIC 1169 * @ev_fini: Deinitialise event queue on the NIC 1170 * @ev_remove: Free resources for event queue 1171 * @ev_process: Process events for a queue, up to the given NAPI quota 1172 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ 1173 * @ev_test_generate: Generate a test event 1174 * @filter_table_probe: Probe filter capabilities and set up filter software state 1175 * @filter_table_restore: Restore filters removed from hardware 1176 * @filter_table_remove: Remove filters from hardware and tear down software state 1177 * @filter_update_rx_scatter: Update filters after change to rx scatter setting 1178 * @filter_insert: add or replace a filter 1179 * @filter_remove_safe: remove a filter by ID, carefully 1180 * @filter_get_safe: retrieve a filter by ID, carefully 1181 * @filter_clear_rx: Remove all RX filters whose priority is less than or 1182 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO 1183 * @filter_count_rx_used: Get the number of filters in use at a given priority 1184 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1 1185 * @filter_get_rx_ids: Get list of RX filters at a given priority 1186 * @filter_rfs_insert: Add or replace a filter for RFS. This must be 1187 * atomic. The hardware change may be asynchronous but should 1188 * not be delayed for long. It may fail if this can't be done 1189 * atomically. 1190 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS. 1191 * This must check whether the specified table entry is used by RFS 1192 * and that rps_may_expire_flow() returns true for it. 1193 * @mtd_probe: Probe and add MTD partitions associated with this net device, 1194 * using efx_mtd_add() 1195 * @mtd_rename: Set an MTD partition name using the net device name 1196 * @mtd_read: Read from an MTD partition 1197 * @mtd_erase: Erase part of an MTD partition 1198 * @mtd_write: Write to an MTD partition 1199 * @mtd_sync: Wait for write-back to complete on MTD partition. This 1200 * also notifies the driver that a writer has finished using this 1201 * partition. 1202 * @ptp_write_host_time: Send host time to MC as part of sync protocol 1203 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX 1204 * timestamping, possibly only temporarily for the purposes of a reset. 1205 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags 1206 * and tx_type will already have been validated but this operation 1207 * must validate and update rx_filter. 1208 * @set_mac_address: Set the MAC address of the device 1209 * @revision: Hardware architecture revision 1210 * @txd_ptr_tbl_base: TX descriptor ring base address 1211 * @rxd_ptr_tbl_base: RX descriptor ring base address 1212 * @buf_tbl_base: Buffer table base address 1213 * @evq_ptr_tbl_base: Event queue pointer table base address 1214 * @evq_rptr_tbl_base: Event queue read-pointer table base address 1215 * @max_dma_mask: Maximum possible DMA mask 1216 * @rx_prefix_size: Size of RX prefix before packet data 1217 * @rx_hash_offset: Offset of RX flow hash within prefix 1218 * @rx_ts_offset: Offset of timestamp within prefix 1219 * @rx_buffer_padding: Size of padding at end of RX packet 1220 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers 1221 * @always_rx_scatter: NIC will always scatter packets to multiple buffers 1222 * @max_interrupt_mode: Highest capability interrupt mode supported 1223 * from &enum efx_init_mode. 1224 * @timer_period_max: Maximum period of interrupt timer (in ticks) 1225 * @offload_features: net_device feature flags for protocol offload 1226 * features implemented in hardware 1227 * @mcdi_max_ver: Maximum MCDI version supported 1228 * @hwtstamp_filters: Mask of hardware timestamp filter types supported 1229 */ 1230 struct efx_nic_type { 1231 bool is_vf; 1232 unsigned int mem_bar; 1233 unsigned int (*mem_map_size)(struct efx_nic *efx); 1234 int (*probe)(struct efx_nic *efx); 1235 void (*remove)(struct efx_nic *efx); 1236 int (*init)(struct efx_nic *efx); 1237 int (*dimension_resources)(struct efx_nic *efx); 1238 void (*fini)(struct efx_nic *efx); 1239 void (*monitor)(struct efx_nic *efx); 1240 enum reset_type (*map_reset_reason)(enum reset_type reason); 1241 int (*map_reset_flags)(u32 *flags); 1242 int (*reset)(struct efx_nic *efx, enum reset_type method); 1243 int (*probe_port)(struct efx_nic *efx); 1244 void (*remove_port)(struct efx_nic *efx); 1245 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *); 1246 int (*fini_dmaq)(struct efx_nic *efx); 1247 void (*prepare_flush)(struct efx_nic *efx); 1248 void (*finish_flush)(struct efx_nic *efx); 1249 void (*prepare_flr)(struct efx_nic *efx); 1250 void (*finish_flr)(struct efx_nic *efx); 1251 size_t (*describe_stats)(struct efx_nic *efx, u8 *names); 1252 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats, 1253 struct rtnl_link_stats64 *core_stats); 1254 void (*start_stats)(struct efx_nic *efx); 1255 void (*pull_stats)(struct efx_nic *efx); 1256 void (*stop_stats)(struct efx_nic *efx); 1257 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); 1258 void (*push_irq_moderation)(struct efx_channel *channel); 1259 int (*reconfigure_port)(struct efx_nic *efx); 1260 void (*prepare_enable_fc_tx)(struct efx_nic *efx); 1261 int (*reconfigure_mac)(struct efx_nic *efx); 1262 bool (*check_mac_fault)(struct efx_nic *efx); 1263 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); 1264 int (*set_wol)(struct efx_nic *efx, u32 type); 1265 void (*resume_wol)(struct efx_nic *efx); 1266 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests); 1267 int (*test_nvram)(struct efx_nic *efx); 1268 void (*mcdi_request)(struct efx_nic *efx, 1269 const efx_dword_t *hdr, size_t hdr_len, 1270 const efx_dword_t *sdu, size_t sdu_len); 1271 bool (*mcdi_poll_response)(struct efx_nic *efx); 1272 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu, 1273 size_t pdu_offset, size_t pdu_len); 1274 int (*mcdi_poll_reboot)(struct efx_nic *efx); 1275 void (*irq_enable_master)(struct efx_nic *efx); 1276 void (*irq_test_generate)(struct efx_nic *efx); 1277 void (*irq_disable_non_ev)(struct efx_nic *efx); 1278 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id); 1279 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id); 1280 int (*tx_probe)(struct efx_tx_queue *tx_queue); 1281 void (*tx_init)(struct efx_tx_queue *tx_queue); 1282 void (*tx_remove)(struct efx_tx_queue *tx_queue); 1283 void (*tx_write)(struct efx_tx_queue *tx_queue); 1284 int (*rx_push_rss_config)(struct efx_nic *efx, bool user, 1285 const u32 *rx_indir_table); 1286 int (*rx_probe)(struct efx_rx_queue *rx_queue); 1287 void (*rx_init)(struct efx_rx_queue *rx_queue); 1288 void (*rx_remove)(struct efx_rx_queue *rx_queue); 1289 void (*rx_write)(struct efx_rx_queue *rx_queue); 1290 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue); 1291 int (*ev_probe)(struct efx_channel *channel); 1292 int (*ev_init)(struct efx_channel *channel); 1293 void (*ev_fini)(struct efx_channel *channel); 1294 void (*ev_remove)(struct efx_channel *channel); 1295 int (*ev_process)(struct efx_channel *channel, int quota); 1296 void (*ev_read_ack)(struct efx_channel *channel); 1297 void (*ev_test_generate)(struct efx_channel *channel); 1298 int (*filter_table_probe)(struct efx_nic *efx); 1299 void (*filter_table_restore)(struct efx_nic *efx); 1300 void (*filter_table_remove)(struct efx_nic *efx); 1301 void (*filter_update_rx_scatter)(struct efx_nic *efx); 1302 s32 (*filter_insert)(struct efx_nic *efx, 1303 struct efx_filter_spec *spec, bool replace); 1304 int (*filter_remove_safe)(struct efx_nic *efx, 1305 enum efx_filter_priority priority, 1306 u32 filter_id); 1307 int (*filter_get_safe)(struct efx_nic *efx, 1308 enum efx_filter_priority priority, 1309 u32 filter_id, struct efx_filter_spec *); 1310 int (*filter_clear_rx)(struct efx_nic *efx, 1311 enum efx_filter_priority priority); 1312 u32 (*filter_count_rx_used)(struct efx_nic *efx, 1313 enum efx_filter_priority priority); 1314 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx); 1315 s32 (*filter_get_rx_ids)(struct efx_nic *efx, 1316 enum efx_filter_priority priority, 1317 u32 *buf, u32 size); 1318 #ifdef CONFIG_RFS_ACCEL 1319 s32 (*filter_rfs_insert)(struct efx_nic *efx, 1320 struct efx_filter_spec *spec); 1321 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id, 1322 unsigned int index); 1323 #endif 1324 #ifdef CONFIG_SFC_MTD 1325 int (*mtd_probe)(struct efx_nic *efx); 1326 void (*mtd_rename)(struct efx_mtd_partition *part); 1327 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len, 1328 size_t *retlen, u8 *buffer); 1329 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len); 1330 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len, 1331 size_t *retlen, const u8 *buffer); 1332 int (*mtd_sync)(struct mtd_info *mtd); 1333 #endif 1334 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time); 1335 int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp); 1336 int (*ptp_set_ts_config)(struct efx_nic *efx, 1337 struct hwtstamp_config *init); 1338 int (*sriov_configure)(struct efx_nic *efx, int num_vfs); 1339 int (*sriov_init)(struct efx_nic *efx); 1340 void (*sriov_fini)(struct efx_nic *efx); 1341 bool (*sriov_wanted)(struct efx_nic *efx); 1342 void (*sriov_reset)(struct efx_nic *efx); 1343 void (*sriov_flr)(struct efx_nic *efx, unsigned vf_i); 1344 int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, u8 *mac); 1345 int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan, 1346 u8 qos); 1347 int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i, 1348 bool spoofchk); 1349 int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i, 1350 struct ifla_vf_info *ivi); 1351 int (*sriov_set_vf_link_state)(struct efx_nic *efx, int vf_i, 1352 int link_state); 1353 int (*sriov_get_phys_port_id)(struct efx_nic *efx, 1354 struct netdev_phys_item_id *ppid); 1355 int (*vswitching_probe)(struct efx_nic *efx); 1356 int (*vswitching_restore)(struct efx_nic *efx); 1357 void (*vswitching_remove)(struct efx_nic *efx); 1358 int (*get_mac_address)(struct efx_nic *efx, unsigned char *perm_addr); 1359 int (*set_mac_address)(struct efx_nic *efx); 1360 1361 int revision; 1362 unsigned int txd_ptr_tbl_base; 1363 unsigned int rxd_ptr_tbl_base; 1364 unsigned int buf_tbl_base; 1365 unsigned int evq_ptr_tbl_base; 1366 unsigned int evq_rptr_tbl_base; 1367 u64 max_dma_mask; 1368 unsigned int rx_prefix_size; 1369 unsigned int rx_hash_offset; 1370 unsigned int rx_ts_offset; 1371 unsigned int rx_buffer_padding; 1372 bool can_rx_scatter; 1373 bool always_rx_scatter; 1374 unsigned int max_interrupt_mode; 1375 unsigned int timer_period_max; 1376 netdev_features_t offload_features; 1377 int mcdi_max_ver; 1378 unsigned int max_rx_ip_filters; 1379 u32 hwtstamp_filters; 1380 }; 1381 1382 /************************************************************************** 1383 * 1384 * Prototypes and inline functions 1385 * 1386 *************************************************************************/ 1387 1388 static inline struct efx_channel * 1389 efx_get_channel(struct efx_nic *efx, unsigned index) 1390 { 1391 EFX_BUG_ON_PARANOID(index >= efx->n_channels); 1392 return efx->channel[index]; 1393 } 1394 1395 /* Iterate over all used channels */ 1396 #define efx_for_each_channel(_channel, _efx) \ 1397 for (_channel = (_efx)->channel[0]; \ 1398 _channel; \ 1399 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ 1400 (_efx)->channel[_channel->channel + 1] : NULL) 1401 1402 /* Iterate over all used channels in reverse */ 1403 #define efx_for_each_channel_rev(_channel, _efx) \ 1404 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \ 1405 _channel; \ 1406 _channel = _channel->channel ? \ 1407 (_efx)->channel[_channel->channel - 1] : NULL) 1408 1409 static inline struct efx_tx_queue * 1410 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) 1411 { 1412 EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels || 1413 type >= EFX_TXQ_TYPES); 1414 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type]; 1415 } 1416 1417 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel) 1418 { 1419 return channel->channel - channel->efx->tx_channel_offset < 1420 channel->efx->n_tx_channels; 1421 } 1422 1423 static inline struct efx_tx_queue * 1424 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type) 1425 { 1426 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) || 1427 type >= EFX_TXQ_TYPES); 1428 return &channel->tx_queue[type]; 1429 } 1430 1431 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue) 1432 { 1433 return !(tx_queue->efx->net_dev->num_tc < 2 && 1434 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI); 1435 } 1436 1437 /* Iterate over all TX queues belonging to a channel */ 1438 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ 1439 if (!efx_channel_has_tx_queues(_channel)) \ 1440 ; \ 1441 else \ 1442 for (_tx_queue = (_channel)->tx_queue; \ 1443 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \ 1444 efx_tx_queue_used(_tx_queue); \ 1445 _tx_queue++) 1446 1447 /* Iterate over all possible TX queues belonging to a channel */ 1448 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \ 1449 if (!efx_channel_has_tx_queues(_channel)) \ 1450 ; \ 1451 else \ 1452 for (_tx_queue = (_channel)->tx_queue; \ 1453 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ 1454 _tx_queue++) 1455 1456 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel) 1457 { 1458 return channel->rx_queue.core_index >= 0; 1459 } 1460 1461 static inline struct efx_rx_queue * 1462 efx_channel_get_rx_queue(struct efx_channel *channel) 1463 { 1464 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel)); 1465 return &channel->rx_queue; 1466 } 1467 1468 /* Iterate over all RX queues belonging to a channel */ 1469 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ 1470 if (!efx_channel_has_rx_queue(_channel)) \ 1471 ; \ 1472 else \ 1473 for (_rx_queue = &(_channel)->rx_queue; \ 1474 _rx_queue; \ 1475 _rx_queue = NULL) 1476 1477 static inline struct efx_channel * 1478 efx_rx_queue_channel(struct efx_rx_queue *rx_queue) 1479 { 1480 return container_of(rx_queue, struct efx_channel, rx_queue); 1481 } 1482 1483 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) 1484 { 1485 return efx_rx_queue_channel(rx_queue)->channel; 1486 } 1487 1488 /* Returns a pointer to the specified receive buffer in the RX 1489 * descriptor queue. 1490 */ 1491 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, 1492 unsigned int index) 1493 { 1494 return &rx_queue->buffer[index]; 1495 } 1496 1497 /** 1498 * EFX_MAX_FRAME_LEN - calculate maximum frame length 1499 * 1500 * This calculates the maximum frame length that will be used for a 1501 * given MTU. The frame length will be equal to the MTU plus a 1502 * constant amount of header space and padding. This is the quantity 1503 * that the net driver will program into the MAC as the maximum frame 1504 * length. 1505 * 1506 * The 10G MAC requires 8-byte alignment on the frame 1507 * length, so we round up to the nearest 8. 1508 * 1509 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an 1510 * XGMII cycle). If the frame length reaches the maximum value in the 1511 * same cycle, the XMAC can miss the IPG altogether. We work around 1512 * this by adding a further 16 bytes. 1513 */ 1514 #define EFX_MAX_FRAME_LEN(mtu) \ 1515 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16) 1516 1517 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb) 1518 { 1519 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP; 1520 } 1521 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb) 1522 { 1523 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1524 } 1525 1526 #endif /* EFX_NET_DRIVER_H */ 1527