1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2009-2013 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 11 #ifndef MCDI_PCOL_H 12 #define MCDI_PCOL_H 13 14 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 15 /* Power-on reset state */ 16 #define MC_FW_STATE_POR (1) 17 /* If this is set in MC_RESET_STATE_REG then it should be 18 * possible to jump into IMEM without loading code from flash. */ 19 #define MC_FW_WARM_BOOT_OK (2) 20 /* The MC main image has started to boot. */ 21 #define MC_FW_STATE_BOOTING (4) 22 /* The Scheduler has started. */ 23 #define MC_FW_STATE_SCHED (8) 24 /* If this is set in MC_RESET_STATE_REG then it should be 25 * possible to jump into IMEM without loading code from flash. 26 * Unlike a warm boot, assume DMEM has been reloaded, so that 27 * the MC persistent data must be reinitialised. */ 28 #define MC_FW_TEPID_BOOT_OK (16) 29 /* We have entered the main firmware via recovery mode. This 30 * means that MC persistent data must be reinitialised, but that 31 * we shouldn't touch PCIe config. */ 32 #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32) 33 /* BIST state has been initialized */ 34 #define MC_FW_BIST_INIT_OK (128) 35 36 /* Siena MC shared memmory offsets */ 37 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 38 #define MC_SMEM_P0_DOORBELL_OFST 0x000 39 #define MC_SMEM_P1_DOORBELL_OFST 0x004 40 /* The rest of these are firmware-defined */ 41 #define MC_SMEM_P0_PDU_OFST 0x008 42 #define MC_SMEM_P1_PDU_OFST 0x108 43 #define MC_SMEM_PDU_LEN 0x100 44 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 45 #define MC_SMEM_P0_STATUS_OFST 0x7f8 46 #define MC_SMEM_P1_STATUS_OFST 0x7fc 47 48 /* Values to be written to the per-port status dword in shared 49 * memory on reboot and assert */ 50 #define MC_STATUS_DWORD_REBOOT (0xb007b007) 51 #define MC_STATUS_DWORD_ASSERT (0xdeaddead) 52 53 /* Check whether an mcfw version (in host order) belongs to a bootloader */ 54 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) 55 56 /* The current version of the MCDI protocol. 57 * 58 * Note that the ROM burnt into the card only talks V0, so at the very 59 * least every driver must support version 0 and MCDI_PCOL_VERSION 60 */ 61 #define MCDI_PCOL_VERSION 2 62 63 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 64 65 /* MCDI version 1 66 * 67 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit 68 * structure, filled in by the client. 69 * 70 * 0 7 8 16 20 22 23 24 31 71 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 72 * | | | 73 * | | \--- Response 74 * | \------- Error 75 * \------------------------------ Resync (always set) 76 * 77 * The client writes it's request into MC shared memory, and rings the 78 * doorbell. Each request is completed by either by the MC writting 79 * back into shared memory, or by writting out an event. 80 * 81 * All MCDI commands support completion by shared memory response. Each 82 * request may also contain additional data (accounted for by HEADER.LEN), 83 * and some response's may also contain additional data (again, accounted 84 * for by HEADER.LEN). 85 * 86 * Some MCDI commands support completion by event, in which any associated 87 * response data is included in the event. 88 * 89 * The protocol requires one response to be delivered for every request, a 90 * request should not be sent unless the response for the previous request 91 * has been received (either by polling shared memory, or by receiving 92 * an event). 93 */ 94 95 /** Request/Response structure */ 96 #define MCDI_HEADER_OFST 0 97 #define MCDI_HEADER_CODE_LBN 0 98 #define MCDI_HEADER_CODE_WIDTH 7 99 #define MCDI_HEADER_RESYNC_LBN 7 100 #define MCDI_HEADER_RESYNC_WIDTH 1 101 #define MCDI_HEADER_DATALEN_LBN 8 102 #define MCDI_HEADER_DATALEN_WIDTH 8 103 #define MCDI_HEADER_SEQ_LBN 16 104 #define MCDI_HEADER_SEQ_WIDTH 4 105 #define MCDI_HEADER_RSVD_LBN 20 106 #define MCDI_HEADER_RSVD_WIDTH 1 107 #define MCDI_HEADER_NOT_EPOCH_LBN 21 108 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 109 #define MCDI_HEADER_ERROR_LBN 22 110 #define MCDI_HEADER_ERROR_WIDTH 1 111 #define MCDI_HEADER_RESPONSE_LBN 23 112 #define MCDI_HEADER_RESPONSE_WIDTH 1 113 #define MCDI_HEADER_XFLAGS_LBN 24 114 #define MCDI_HEADER_XFLAGS_WIDTH 8 115 /* Request response using event */ 116 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 117 /* Request (and signal) early doorbell return */ 118 #define MCDI_HEADER_XFLAGS_DBRET 0x02 119 120 /* Maximum number of payload bytes */ 121 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc 122 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 123 124 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 125 126 127 /* The MC can generate events for two reasons: 128 * - To advance a shared memory request if XFLAGS_EVREQ was set 129 * - As a notification (link state, i2c event), controlled 130 * via MC_CMD_LOG_CTRL 131 * 132 * Both events share a common structure: 133 * 134 * 0 32 33 36 44 52 60 135 * | Data | Cont | Level | Src | Code | Rsvd | 136 * | 137 * \ There is another event pending in this notification 138 * 139 * If Code==CMDDONE, then the fields are further interpreted as: 140 * 141 * - LEVEL==INFO Command succeeded 142 * - LEVEL==ERR Command failed 143 * 144 * 0 8 16 24 32 145 * | Seq | Datalen | Errno | Rsvd | 146 * 147 * These fields are taken directly out of the standard MCDI header, i.e., 148 * LEVEL==ERR, Datalen == 0 => Reboot 149 * 150 * Events can be squirted out of the UART (using LOG_CTRL) without a 151 * MCDI header. An event can be distinguished from a MCDI response by 152 * examining the first byte which is 0xc0. This corresponds to the 153 * non-existent MCDI command MC_CMD_DEBUG_LOG. 154 * 155 * 0 7 8 156 * | command | Resync | = 0xc0 157 * 158 * Since the event is written in big-endian byte order, this works 159 * providing bits 56-63 of the event are 0xc0. 160 * 161 * 56 60 63 162 * | Rsvd | Code | = 0xc0 163 * 164 * Which means for convenience the event code is 0xc for all MC 165 * generated events. 166 */ 167 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 168 169 170 /* Operation not permitted. */ 171 #define MC_CMD_ERR_EPERM 1 172 /* Non-existent command target */ 173 #define MC_CMD_ERR_ENOENT 2 174 /* assert() has killed the MC */ 175 #define MC_CMD_ERR_EINTR 4 176 /* I/O failure */ 177 #define MC_CMD_ERR_EIO 5 178 /* Already exists */ 179 #define MC_CMD_ERR_EEXIST 6 180 /* Try again */ 181 #define MC_CMD_ERR_EAGAIN 11 182 /* Out of memory */ 183 #define MC_CMD_ERR_ENOMEM 12 184 /* Caller does not hold required locks */ 185 #define MC_CMD_ERR_EACCES 13 186 /* Resource is currently unavailable (e.g. lock contention) */ 187 #define MC_CMD_ERR_EBUSY 16 188 /* No such device */ 189 #define MC_CMD_ERR_ENODEV 19 190 /* Invalid argument to target */ 191 #define MC_CMD_ERR_EINVAL 22 192 /* Broken pipe */ 193 #define MC_CMD_ERR_EPIPE 32 194 /* Read-only */ 195 #define MC_CMD_ERR_EROFS 30 196 /* Out of range */ 197 #define MC_CMD_ERR_ERANGE 34 198 /* Non-recursive resource is already acquired */ 199 #define MC_CMD_ERR_EDEADLK 35 200 /* Operation not implemented */ 201 #define MC_CMD_ERR_ENOSYS 38 202 /* Operation timed out */ 203 #define MC_CMD_ERR_ETIME 62 204 /* Link has been severed */ 205 #define MC_CMD_ERR_ENOLINK 67 206 /* Protocol error */ 207 #define MC_CMD_ERR_EPROTO 71 208 /* Operation not supported */ 209 #define MC_CMD_ERR_ENOTSUP 95 210 /* Address not available */ 211 #define MC_CMD_ERR_EADDRNOTAVAIL 99 212 /* Not connected */ 213 #define MC_CMD_ERR_ENOTCONN 107 214 /* Operation already in progress */ 215 #define MC_CMD_ERR_EALREADY 114 216 217 /* Resource allocation failed. */ 218 #define MC_CMD_ERR_ALLOC_FAIL 0x1000 219 /* V-adaptor not found. */ 220 #define MC_CMD_ERR_NO_VADAPTOR 0x1001 221 /* EVB port not found. */ 222 #define MC_CMD_ERR_NO_EVB_PORT 0x1002 223 /* V-switch not found. */ 224 #define MC_CMD_ERR_NO_VSWITCH 0x1003 225 /* Too many VLAN tags. */ 226 #define MC_CMD_ERR_VLAN_LIMIT 0x1004 227 /* Bad PCI function number. */ 228 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 229 /* Invalid VLAN mode. */ 230 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 231 /* Invalid v-switch type. */ 232 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 233 /* Invalid v-port type. */ 234 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 235 /* MAC address exists. */ 236 #define MC_CMD_ERR_MAC_EXIST 0x1009 237 /* Slave core not present */ 238 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a 239 /* The datapath is disabled. */ 240 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b 241 /* The requesting client is not a function */ 242 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c 243 /* The requested operation might require the 244 command to be passed between MCs, and the 245 transport doesn't support that. Should 246 only ever been seen over the UART. */ 247 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d 248 /* VLAN tag(s) exists */ 249 #define MC_CMD_ERR_VLAN_EXIST 0x100e 250 /* No MAC address assigned to an EVB port */ 251 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f 252 /* Notifies the driver that the request has been relayed 253 * to an admin function for authorization. The driver should 254 * wait for a PROXY_RESPONSE event and then resend its request. 255 * This error code is followed by a 32-bit handle that 256 * helps matching it with the respective PROXY_RESPONSE event. */ 257 #define MC_CMD_ERR_PROXY_PENDING 0x1010 258 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4 259 /* The request cannot be passed for authorization because 260 * another request from the same function is currently being 261 * authorized. The drvier should try again later. */ 262 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011 263 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function 264 * that has enabled proxying or BLOCK_INDEX points to a function that 265 * doesn't await an authorization. */ 266 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012 267 /* This code is currently only used internally in FW. Its meaning is that 268 * an operation failed due to lack of SR-IOV privilege. 269 * Normally it is translated to EPERM by send_cmd_err(), 270 * but it may also be used to trigger some special mechanism 271 * for handling such case, e.g. to relay the failed request 272 * to a designated admin function for authorization. */ 273 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013 274 /* Workaround 26807 could not be turned on/off because some functions 275 * have already installed filters. See the comment at 276 * MC_CMD_WORKAROUND_BUG26807. */ 277 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 278 /* The clock whose frequency you've attempted to set set 279 * doesn't exist on this NIC */ 280 #define MC_CMD_ERR_NO_CLOCK 0x1015 281 /* Returned by MC_CMD_TESTASSERT if the action that should 282 * have caused an assertion failed to do so. */ 283 #define MC_CMD_ERR_UNREACHABLE 0x1016 284 /* This command needs to be processed in the background but there were no 285 * resources to do so. Send it again after a command has completed. */ 286 #define MC_CMD_ERR_QUEUE_FULL 0x1017 287 /* The operation could not be completed because the PCIe link has gone 288 * away. This error code is never expected to be returned over the TLP 289 * transport. */ 290 #define MC_CMD_ERR_NO_PCIE 0x1018 291 /* The operation could not be completed because the datapath has gone 292 * away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the 293 * datapath absence may be temporary*/ 294 #define MC_CMD_ERR_NO_DATAPATH 0x1019 295 296 #define MC_CMD_ERR_CODE_OFST 0 297 298 /* We define 8 "escape" commands to allow 299 for command number space extension */ 300 301 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 302 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 303 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 304 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 305 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 306 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 307 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 308 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 309 310 /* Vectors in the boot ROM */ 311 /* Point to the copycode entry point. */ 312 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) 313 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) 314 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4) 315 /* Points to the recovery mode entry point. */ 316 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) 317 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) 318 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4) 319 320 /* The command set exported by the boot ROM (MCDI v0) */ 321 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 322 (1 << MC_CMD_READ32) | \ 323 (1 << MC_CMD_WRITE32) | \ 324 (1 << MC_CMD_COPYCODE) | \ 325 (1 << MC_CMD_GET_VERSION), \ 326 0, 0, 0 } 327 328 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 329 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 330 331 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 332 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 333 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 334 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 335 336 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 337 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 338 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 339 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 340 341 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 342 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 343 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 344 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 345 346 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default 347 * stack ID (which must be in the range 1-255) along with an EVB port ID. 348 */ 349 #define EVB_STACK_ID(n) (((n) & 0xff) << 16) 350 351 352 /* Version 2 adds an optional argument to error returns: the errno value 353 * may be followed by the (0-based) number of the first argument that 354 * could not be processed. 355 */ 356 #define MC_CMD_ERR_ARG_OFST 4 357 358 /* No space */ 359 #define MC_CMD_ERR_ENOSPC 28 360 361 /* MCDI_EVENT structuredef */ 362 #define MCDI_EVENT_LEN 8 363 #define MCDI_EVENT_CONT_LBN 32 364 #define MCDI_EVENT_CONT_WIDTH 1 365 #define MCDI_EVENT_LEVEL_LBN 33 366 #define MCDI_EVENT_LEVEL_WIDTH 3 367 /* enum: Info. */ 368 #define MCDI_EVENT_LEVEL_INFO 0x0 369 /* enum: Warning. */ 370 #define MCDI_EVENT_LEVEL_WARN 0x1 371 /* enum: Error. */ 372 #define MCDI_EVENT_LEVEL_ERR 0x2 373 /* enum: Fatal. */ 374 #define MCDI_EVENT_LEVEL_FATAL 0x3 375 #define MCDI_EVENT_DATA_OFST 0 376 #define MCDI_EVENT_DATA_LEN 4 377 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 378 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 379 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 380 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 381 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 382 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 383 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 384 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 385 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 386 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 387 /* enum: Link is down or link speed could not be determined */ 388 #define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0 389 /* enum: 100Mbs */ 390 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 391 /* enum: 1Gbs */ 392 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 393 /* enum: 10Gbs */ 394 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 395 /* enum: 40Gbs */ 396 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 397 /* enum: 25Gbs */ 398 #define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5 399 /* enum: 50Gbs */ 400 #define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6 401 /* enum: 100Gbs */ 402 #define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7 403 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 404 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 405 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 406 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 407 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 408 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 409 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 410 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 411 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 412 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 413 #define MCDI_EVENT_FWALERT_DATA_LBN 8 414 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 415 #define MCDI_EVENT_FWALERT_REASON_LBN 0 416 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 417 /* enum: SRAM Access. */ 418 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 419 #define MCDI_EVENT_FLR_VF_LBN 0 420 #define MCDI_EVENT_FLR_VF_WIDTH 8 421 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 422 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 423 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 424 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 425 /* enum: Descriptor loader reported failure */ 426 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 427 /* enum: Descriptor ring empty and no EOP seen for packet */ 428 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 429 /* enum: Overlength packet */ 430 #define MCDI_EVENT_TX_ERR_2BIG 0x3 431 /* enum: Malformed option descriptor */ 432 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 433 /* enum: Option descriptor part way through a packet */ 434 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 435 /* enum: DMA or PIO data access error */ 436 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 437 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 438 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 439 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 440 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 441 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 442 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 443 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 444 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 445 /* enum: PLL lost lock */ 446 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 447 /* enum: Filter overflow (PDMA) */ 448 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 449 /* enum: FIFO overflow (FPGA) */ 450 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 451 /* enum: Merge queue overflow */ 452 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 453 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 454 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 455 /* enum: AOE failed to load - no valid image? */ 456 #define MCDI_EVENT_AOE_NO_LOAD 0x1 457 /* enum: AOE FC reported an exception */ 458 #define MCDI_EVENT_AOE_FC_ASSERT 0x2 459 /* enum: AOE FC watchdogged */ 460 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 461 /* enum: AOE FC failed to start */ 462 #define MCDI_EVENT_AOE_FC_NO_START 0x4 463 /* enum: Generic AOE fault - likely to have been reported via other means too 464 * but intended for use by aoex driver. 465 */ 466 #define MCDI_EVENT_AOE_FAULT 0x5 467 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ 468 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 469 /* enum: AOE loaded successfully */ 470 #define MCDI_EVENT_AOE_LOAD 0x7 471 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ 472 #define MCDI_EVENT_AOE_DMA 0x8 473 /* enum: AOE byteblaster connected/disconnected (Connection status in 474 * AOE_ERR_DATA) 475 */ 476 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 477 /* enum: DDR ECC status update */ 478 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa 479 /* enum: PTP status update */ 480 #define MCDI_EVENT_AOE_PTP_STATUS 0xb 481 /* enum: FPGA header incorrect */ 482 #define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc 483 /* enum: FPGA Powered Off due to error in powering up FPGA */ 484 #define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd 485 /* enum: AOE FPGA load failed due to MC to MUM communication failure */ 486 #define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe 487 /* enum: Notify that invalid flash type detected */ 488 #define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf 489 /* enum: Notify that the attempt to run FPGA Controller firmware timedout */ 490 #define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10 491 /* enum: Failure to probe one or more FPGA boot flash chips */ 492 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11 493 /* enum: FPGA boot-flash contains an invalid image header */ 494 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12 495 /* enum: Failed to program clocks required by the FPGA */ 496 #define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13 497 /* enum: Notify that FPGA Controller is alive to serve MCDI requests */ 498 #define MCDI_EVENT_AOE_FC_RUNNING 0x14 499 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 500 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 501 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8 502 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8 503 /* enum: FC Assert happened, but the register information is not available */ 504 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0 505 /* enum: The register information for FC Assert is ready for readinng by driver 506 */ 507 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1 508 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8 509 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8 510 /* enum: Reading from NV failed */ 511 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0 512 /* enum: Invalid Magic Number if FPGA header */ 513 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1 514 /* enum: Invalid Silicon type detected in header */ 515 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2 516 /* enum: Unsupported VRatio */ 517 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3 518 /* enum: Unsupported DDR Type */ 519 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4 520 /* enum: DDR Voltage out of supported range */ 521 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5 522 /* enum: Unsupported DDR speed */ 523 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6 524 /* enum: Unsupported DDR size */ 525 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7 526 /* enum: Unsupported DDR rank */ 527 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8 528 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8 529 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8 530 /* enum: Primary boot flash */ 531 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0 532 /* enum: Secondary boot flash */ 533 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1 534 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8 535 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8 536 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8 537 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8 538 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 539 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 540 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 541 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 542 #define MCDI_EVENT_RX_ERR_INFO_LBN 16 543 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 544 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 545 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 546 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 547 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 548 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 549 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 550 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0 551 #define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8 552 /* enum: MUM failed to load - no valid image? */ 553 #define MCDI_EVENT_MUM_NO_LOAD 0x1 554 /* enum: MUM f/w reported an exception */ 555 #define MCDI_EVENT_MUM_ASSERT 0x2 556 /* enum: MUM not kicking watchdog */ 557 #define MCDI_EVENT_MUM_WATCHDOG 0x3 558 #define MCDI_EVENT_MUM_ERR_DATA_LBN 8 559 #define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8 560 #define MCDI_EVENT_DBRET_SEQ_LBN 0 561 #define MCDI_EVENT_DBRET_SEQ_WIDTH 8 562 #define MCDI_EVENT_SUC_ERR_TYPE_LBN 0 563 #define MCDI_EVENT_SUC_ERR_TYPE_WIDTH 8 564 /* enum: Corrupted or bad SUC application. */ 565 #define MCDI_EVENT_SUC_BAD_APP 0x1 566 /* enum: SUC application reported an assert. */ 567 #define MCDI_EVENT_SUC_ASSERT 0x2 568 /* enum: SUC application reported an exception. */ 569 #define MCDI_EVENT_SUC_EXCEPTION 0x3 570 /* enum: SUC watchdog timer expired. */ 571 #define MCDI_EVENT_SUC_WATCHDOG 0x4 572 #define MCDI_EVENT_SUC_ERR_ADDRESS_LBN 8 573 #define MCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24 574 #define MCDI_EVENT_SUC_ERR_DATA_LBN 8 575 #define MCDI_EVENT_SUC_ERR_DATA_WIDTH 24 576 #define MCDI_EVENT_DATA_LBN 0 577 #define MCDI_EVENT_DATA_WIDTH 32 578 #define MCDI_EVENT_SRC_LBN 36 579 #define MCDI_EVENT_SRC_WIDTH 8 580 #define MCDI_EVENT_EV_CODE_LBN 60 581 #define MCDI_EVENT_EV_CODE_WIDTH 4 582 #define MCDI_EVENT_CODE_LBN 44 583 #define MCDI_EVENT_CODE_WIDTH 8 584 /* enum: Event generated by host software */ 585 #define MCDI_EVENT_SW_EVENT 0x0 586 /* enum: Bad assert. */ 587 #define MCDI_EVENT_CODE_BADSSERT 0x1 588 /* enum: PM Notice. */ 589 #define MCDI_EVENT_CODE_PMNOTICE 0x2 590 /* enum: Command done. */ 591 #define MCDI_EVENT_CODE_CMDDONE 0x3 592 /* enum: Link change. */ 593 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 594 /* enum: Sensor Event. */ 595 #define MCDI_EVENT_CODE_SENSOREVT 0x5 596 /* enum: Schedule error. */ 597 #define MCDI_EVENT_CODE_SCHEDERR 0x6 598 /* enum: Reboot. */ 599 #define MCDI_EVENT_CODE_REBOOT 0x7 600 /* enum: Mac stats DMA. */ 601 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 602 /* enum: Firmware alert. */ 603 #define MCDI_EVENT_CODE_FWALERT 0x9 604 /* enum: Function level reset. */ 605 #define MCDI_EVENT_CODE_FLR 0xa 606 /* enum: Transmit error */ 607 #define MCDI_EVENT_CODE_TX_ERR 0xb 608 /* enum: Tx flush has completed */ 609 #define MCDI_EVENT_CODE_TX_FLUSH 0xc 610 /* enum: PTP packet received timestamp */ 611 #define MCDI_EVENT_CODE_PTP_RX 0xd 612 /* enum: PTP NIC failure */ 613 #define MCDI_EVENT_CODE_PTP_FAULT 0xe 614 /* enum: PTP PPS event */ 615 #define MCDI_EVENT_CODE_PTP_PPS 0xf 616 /* enum: Rx flush has completed */ 617 #define MCDI_EVENT_CODE_RX_FLUSH 0x10 618 /* enum: Receive error */ 619 #define MCDI_EVENT_CODE_RX_ERR 0x11 620 /* enum: AOE fault */ 621 #define MCDI_EVENT_CODE_AOE 0x12 622 /* enum: Network port calibration failed (VCAL). */ 623 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 624 /* enum: HW PPS event */ 625 #define MCDI_EVENT_CODE_HW_PPS 0x14 626 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and 627 * a different format) 628 */ 629 #define MCDI_EVENT_CODE_MC_REBOOT 0x15 630 /* enum: the MC has detected a parity error */ 631 #define MCDI_EVENT_CODE_PAR_ERR 0x16 632 /* enum: the MC has detected a correctable error */ 633 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 634 /* enum: the MC has detected an uncorrectable error */ 635 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 636 /* enum: The MC has entered offline BIST mode */ 637 #define MCDI_EVENT_CODE_MC_BIST 0x19 638 /* enum: PTP tick event providing current NIC time */ 639 #define MCDI_EVENT_CODE_PTP_TIME 0x1a 640 /* enum: MUM fault */ 641 #define MCDI_EVENT_CODE_MUM 0x1b 642 /* enum: notify the designated PF of a new authorization request */ 643 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c 644 /* enum: notify a function that awaits an authorization that its request has 645 * been processed and it may now resend the command 646 */ 647 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d 648 /* enum: MCDI command accepted. New commands can be issued but this command is 649 * not done yet. 650 */ 651 #define MCDI_EVENT_CODE_DBRET 0x1e 652 /* enum: The MC has detected a fault on the SUC */ 653 #define MCDI_EVENT_CODE_SUC 0x1f 654 /* enum: Artificial event generated by host and posted via MC for test 655 * purposes. 656 */ 657 #define MCDI_EVENT_CODE_TESTGEN 0xfa 658 #define MCDI_EVENT_CMDDONE_DATA_OFST 0 659 #define MCDI_EVENT_CMDDONE_DATA_LEN 4 660 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 661 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 662 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 663 #define MCDI_EVENT_LINKCHANGE_DATA_LEN 4 664 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 665 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 666 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 667 #define MCDI_EVENT_SENSOREVT_DATA_LEN 4 668 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 669 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 670 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 671 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4 672 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 673 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 674 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 675 #define MCDI_EVENT_TX_ERR_DATA_LEN 4 676 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 677 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 678 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of 679 * timestamp 680 */ 681 #define MCDI_EVENT_PTP_SECONDS_OFST 0 682 #define MCDI_EVENT_PTP_SECONDS_LEN 4 683 #define MCDI_EVENT_PTP_SECONDS_LBN 0 684 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 685 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of 686 * timestamp 687 */ 688 #define MCDI_EVENT_PTP_MAJOR_OFST 0 689 #define MCDI_EVENT_PTP_MAJOR_LEN 4 690 #define MCDI_EVENT_PTP_MAJOR_LBN 0 691 #define MCDI_EVENT_PTP_MAJOR_WIDTH 32 692 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field 693 * of timestamp 694 */ 695 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 696 #define MCDI_EVENT_PTP_NANOSECONDS_LEN 4 697 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 698 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 699 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of 700 * timestamp 701 */ 702 #define MCDI_EVENT_PTP_MINOR_OFST 0 703 #define MCDI_EVENT_PTP_MINOR_LEN 4 704 #define MCDI_EVENT_PTP_MINOR_LBN 0 705 #define MCDI_EVENT_PTP_MINOR_WIDTH 32 706 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet 707 */ 708 #define MCDI_EVENT_PTP_UUID_OFST 0 709 #define MCDI_EVENT_PTP_UUID_LEN 4 710 #define MCDI_EVENT_PTP_UUID_LBN 0 711 #define MCDI_EVENT_PTP_UUID_WIDTH 32 712 #define MCDI_EVENT_RX_ERR_DATA_OFST 0 713 #define MCDI_EVENT_RX_ERR_DATA_LEN 4 714 #define MCDI_EVENT_RX_ERR_DATA_LBN 0 715 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 716 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 717 #define MCDI_EVENT_PAR_ERR_DATA_LEN 4 718 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 719 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 720 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 721 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4 722 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 723 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 724 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 725 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4 726 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 727 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 728 /* For CODE_PTP_TIME events, the major value of the PTP clock */ 729 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 730 #define MCDI_EVENT_PTP_TIME_MAJOR_LEN 4 731 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 732 #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 733 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ 734 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 735 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 736 /* For CODE_PTP_TIME events, most significant bits of the minor value of the 737 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_19. 738 */ 739 #define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_LBN 36 740 #define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_WIDTH 8 741 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 742 * whether the NIC clock has ever been set 743 */ 744 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36 745 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1 746 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 747 * whether the NIC and System clocks are in sync 748 */ 749 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37 750 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1 751 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of 752 * the minor value of the PTP clock 753 */ 754 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38 755 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6 756 /* For CODE_PTP_TIME events, most significant bits of the minor value of the 757 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_21. 758 */ 759 #define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_LBN 38 760 #define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_WIDTH 6 761 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0 762 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4 763 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0 764 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32 765 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0 766 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4 767 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0 768 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32 769 /* Zero means that the request has been completed or authorized, and the driver 770 * should resend it. A non-zero value means that the authorization has been 771 * denied, and gives the reason. Typically it will be EPERM. 772 */ 773 #define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36 774 #define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8 775 #define MCDI_EVENT_DBRET_DATA_OFST 0 776 #define MCDI_EVENT_DBRET_DATA_LEN 4 777 #define MCDI_EVENT_DBRET_DATA_LBN 0 778 #define MCDI_EVENT_DBRET_DATA_WIDTH 32 779 780 /* FCDI_EVENT structuredef */ 781 #define FCDI_EVENT_LEN 8 782 #define FCDI_EVENT_CONT_LBN 32 783 #define FCDI_EVENT_CONT_WIDTH 1 784 #define FCDI_EVENT_LEVEL_LBN 33 785 #define FCDI_EVENT_LEVEL_WIDTH 3 786 /* enum: Info. */ 787 #define FCDI_EVENT_LEVEL_INFO 0x0 788 /* enum: Warning. */ 789 #define FCDI_EVENT_LEVEL_WARN 0x1 790 /* enum: Error. */ 791 #define FCDI_EVENT_LEVEL_ERR 0x2 792 /* enum: Fatal. */ 793 #define FCDI_EVENT_LEVEL_FATAL 0x3 794 #define FCDI_EVENT_DATA_OFST 0 795 #define FCDI_EVENT_DATA_LEN 4 796 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 797 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 798 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ 799 #define FCDI_EVENT_LINK_UP 0x1 /* enum */ 800 #define FCDI_EVENT_DATA_LBN 0 801 #define FCDI_EVENT_DATA_WIDTH 32 802 #define FCDI_EVENT_SRC_LBN 36 803 #define FCDI_EVENT_SRC_WIDTH 8 804 #define FCDI_EVENT_EV_CODE_LBN 60 805 #define FCDI_EVENT_EV_CODE_WIDTH 4 806 #define FCDI_EVENT_CODE_LBN 44 807 #define FCDI_EVENT_CODE_WIDTH 8 808 /* enum: The FC was rebooted. */ 809 #define FCDI_EVENT_CODE_REBOOT 0x1 810 /* enum: Bad assert. */ 811 #define FCDI_EVENT_CODE_ASSERT 0x2 812 /* enum: DDR3 test result. */ 813 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 814 /* enum: Link status. */ 815 #define FCDI_EVENT_CODE_LINK_STATE 0x4 816 /* enum: A timed read is ready to be serviced. */ 817 #define FCDI_EVENT_CODE_TIMED_READ 0x5 818 /* enum: One or more PPS IN events */ 819 #define FCDI_EVENT_CODE_PPS_IN 0x6 820 /* enum: Tick event from PTP clock */ 821 #define FCDI_EVENT_CODE_PTP_TICK 0x7 822 /* enum: ECC error counters */ 823 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 824 /* enum: Current status of PTP */ 825 #define FCDI_EVENT_CODE_PTP_STATUS 0x9 826 /* enum: Port id config to map MC-FC port idx */ 827 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa 828 /* enum: Boot result or error code */ 829 #define FCDI_EVENT_CODE_BOOT_RESULT 0xb 830 #define FCDI_EVENT_REBOOT_SRC_LBN 36 831 #define FCDI_EVENT_REBOOT_SRC_WIDTH 8 832 #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */ 833 #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */ 834 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 835 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4 836 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 837 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 838 #define FCDI_EVENT_ASSERT_TYPE_LBN 36 839 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 840 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 841 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 842 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 843 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4 844 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 845 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 846 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 847 #define FCDI_EVENT_LINK_STATE_DATA_LEN 4 848 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 849 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 850 #define FCDI_EVENT_PTP_STATE_OFST 0 851 #define FCDI_EVENT_PTP_STATE_LEN 4 852 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ 853 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ 854 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ 855 #define FCDI_EVENT_PTP_STATE_LBN 0 856 #define FCDI_EVENT_PTP_STATE_WIDTH 32 857 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 858 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 859 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 860 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4 861 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 862 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 863 /* Index of MC port being referred to */ 864 #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 865 #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 866 /* FC Port index that matches the MC port index in SRC */ 867 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 868 #define FCDI_EVENT_PORT_CONFIG_DATA_LEN 4 869 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 870 #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 871 #define FCDI_EVENT_BOOT_RESULT_OFST 0 872 #define FCDI_EVENT_BOOT_RESULT_LEN 4 873 /* Enum values, see field(s): */ 874 /* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */ 875 #define FCDI_EVENT_BOOT_RESULT_LBN 0 876 #define FCDI_EVENT_BOOT_RESULT_WIDTH 32 877 878 /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events 879 * to the MC. Note that this structure | is overlayed over a normal FCDI event 880 * such that bits 32-63 containing | event code, level, source etc remain the 881 * same. In this case the data | field of the header is defined to be the 882 * number of timestamps 883 */ 884 #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 885 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 886 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) 887 /* Number of timestamps following */ 888 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 889 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4 890 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 891 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 892 /* Seconds field of a timestamp record */ 893 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 894 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4 895 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 896 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 897 /* Nanoseconds field of a timestamp record */ 898 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 899 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4 900 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 901 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 902 /* Timestamp records comprising the event */ 903 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 904 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 905 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 906 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 907 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 908 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 909 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 910 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 911 912 /* MUM_EVENT structuredef */ 913 #define MUM_EVENT_LEN 8 914 #define MUM_EVENT_CONT_LBN 32 915 #define MUM_EVENT_CONT_WIDTH 1 916 #define MUM_EVENT_LEVEL_LBN 33 917 #define MUM_EVENT_LEVEL_WIDTH 3 918 /* enum: Info. */ 919 #define MUM_EVENT_LEVEL_INFO 0x0 920 /* enum: Warning. */ 921 #define MUM_EVENT_LEVEL_WARN 0x1 922 /* enum: Error. */ 923 #define MUM_EVENT_LEVEL_ERR 0x2 924 /* enum: Fatal. */ 925 #define MUM_EVENT_LEVEL_FATAL 0x3 926 #define MUM_EVENT_DATA_OFST 0 927 #define MUM_EVENT_DATA_LEN 4 928 #define MUM_EVENT_SENSOR_ID_LBN 0 929 #define MUM_EVENT_SENSOR_ID_WIDTH 8 930 /* Enum values, see field(s): */ 931 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 932 #define MUM_EVENT_SENSOR_STATE_LBN 8 933 #define MUM_EVENT_SENSOR_STATE_WIDTH 8 934 #define MUM_EVENT_PORT_PHY_READY_LBN 0 935 #define MUM_EVENT_PORT_PHY_READY_WIDTH 1 936 #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1 937 #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1 938 #define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2 939 #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1 940 #define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3 941 #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1 942 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4 943 #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1 944 #define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5 945 #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1 946 #define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6 947 #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1 948 #define MUM_EVENT_DATA_LBN 0 949 #define MUM_EVENT_DATA_WIDTH 32 950 #define MUM_EVENT_SRC_LBN 36 951 #define MUM_EVENT_SRC_WIDTH 8 952 #define MUM_EVENT_EV_CODE_LBN 60 953 #define MUM_EVENT_EV_CODE_WIDTH 4 954 #define MUM_EVENT_CODE_LBN 44 955 #define MUM_EVENT_CODE_WIDTH 8 956 /* enum: The MUM was rebooted. */ 957 #define MUM_EVENT_CODE_REBOOT 0x1 958 /* enum: Bad assert. */ 959 #define MUM_EVENT_CODE_ASSERT 0x2 960 /* enum: Sensor failure. */ 961 #define MUM_EVENT_CODE_SENSOR 0x3 962 /* enum: Link fault has been asserted, or has cleared. */ 963 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4 964 #define MUM_EVENT_SENSOR_DATA_OFST 0 965 #define MUM_EVENT_SENSOR_DATA_LEN 4 966 #define MUM_EVENT_SENSOR_DATA_LBN 0 967 #define MUM_EVENT_SENSOR_DATA_WIDTH 32 968 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0 969 #define MUM_EVENT_PORT_PHY_FLAGS_LEN 4 970 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0 971 #define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32 972 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0 973 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4 974 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0 975 #define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32 976 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0 977 #define MUM_EVENT_PORT_PHY_CAPS_LEN 4 978 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0 979 #define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32 980 #define MUM_EVENT_PORT_PHY_TECH_OFST 0 981 #define MUM_EVENT_PORT_PHY_TECH_LEN 4 982 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */ 983 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */ 984 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */ 985 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */ 986 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */ 987 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */ 988 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */ 989 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */ 990 #define MUM_EVENT_PORT_PHY_TECH_LBN 0 991 #define MUM_EVENT_PORT_PHY_TECH_WIDTH 32 992 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36 993 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4 994 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */ 995 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */ 996 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */ 997 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */ 998 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */ 999 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 1000 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 1001 1002 1003 /***********************************/ 1004 /* MC_CMD_READ32 1005 * Read multiple 32byte words from MC memory. 1006 */ 1007 #define MC_CMD_READ32 0x1 1008 1009 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1010 1011 /* MC_CMD_READ32_IN msgrequest */ 1012 #define MC_CMD_READ32_IN_LEN 8 1013 #define MC_CMD_READ32_IN_ADDR_OFST 0 1014 #define MC_CMD_READ32_IN_ADDR_LEN 4 1015 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 1016 #define MC_CMD_READ32_IN_NUMWORDS_LEN 4 1017 1018 /* MC_CMD_READ32_OUT msgresponse */ 1019 #define MC_CMD_READ32_OUT_LENMIN 4 1020 #define MC_CMD_READ32_OUT_LENMAX 252 1021 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 1022 #define MC_CMD_READ32_OUT_BUFFER_OFST 0 1023 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 1024 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 1025 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 1026 1027 1028 /***********************************/ 1029 /* MC_CMD_WRITE32 1030 * Write multiple 32byte words to MC memory. 1031 */ 1032 #define MC_CMD_WRITE32 0x2 1033 1034 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE 1035 1036 /* MC_CMD_WRITE32_IN msgrequest */ 1037 #define MC_CMD_WRITE32_IN_LENMIN 8 1038 #define MC_CMD_WRITE32_IN_LENMAX 252 1039 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 1040 #define MC_CMD_WRITE32_IN_ADDR_OFST 0 1041 #define MC_CMD_WRITE32_IN_ADDR_LEN 4 1042 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 1043 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 1044 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 1045 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 1046 1047 /* MC_CMD_WRITE32_OUT msgresponse */ 1048 #define MC_CMD_WRITE32_OUT_LEN 0 1049 1050 1051 /***********************************/ 1052 /* MC_CMD_COPYCODE 1053 * Copy MC code between two locations and jump. 1054 */ 1055 #define MC_CMD_COPYCODE 0x3 1056 1057 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1058 1059 /* MC_CMD_COPYCODE_IN msgrequest */ 1060 #define MC_CMD_COPYCODE_IN_LEN 16 1061 /* Source address 1062 * 1063 * The main image should be entered via a copy of a single word from and to a 1064 * magic address, which controls various aspects of the boot. The magic address 1065 * is a bitfield, with each bit as documented below. 1066 */ 1067 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 1068 #define MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4 1069 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ 1070 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 1071 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and 1072 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below) 1073 */ 1074 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 1075 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, 1076 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see 1077 * below) 1078 */ 1079 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc 1080 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 1081 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 1082 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 1083 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 1084 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 1085 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 1086 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 1087 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 1088 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 1089 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 1090 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6 1091 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1 1092 /* Destination address */ 1093 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 1094 #define MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4 1095 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 1096 #define MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4 1097 /* Address of where to jump after copy. */ 1098 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 1099 #define MC_CMD_COPYCODE_IN_JUMP_LEN 4 1100 /* enum: Control should return to the caller rather than jumping */ 1101 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 1102 1103 /* MC_CMD_COPYCODE_OUT msgresponse */ 1104 #define MC_CMD_COPYCODE_OUT_LEN 0 1105 1106 1107 /***********************************/ 1108 /* MC_CMD_SET_FUNC 1109 * Select function for function-specific commands. 1110 */ 1111 #define MC_CMD_SET_FUNC 0x4 1112 1113 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE 1114 1115 /* MC_CMD_SET_FUNC_IN msgrequest */ 1116 #define MC_CMD_SET_FUNC_IN_LEN 4 1117 /* Set function */ 1118 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 1119 #define MC_CMD_SET_FUNC_IN_FUNC_LEN 4 1120 1121 /* MC_CMD_SET_FUNC_OUT msgresponse */ 1122 #define MC_CMD_SET_FUNC_OUT_LEN 0 1123 1124 1125 /***********************************/ 1126 /* MC_CMD_GET_BOOT_STATUS 1127 * Get the instruction address from which the MC booted. 1128 */ 1129 #define MC_CMD_GET_BOOT_STATUS 0x5 1130 1131 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1132 1133 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 1134 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 1135 1136 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 1137 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 1138 /* ?? */ 1139 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 1140 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4 1141 /* enum: indicates that the MC wasn't flash booted */ 1142 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef 1143 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 1144 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4 1145 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 1146 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 1147 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 1148 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 1149 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 1150 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 1151 1152 1153 /***********************************/ 1154 /* MC_CMD_GET_ASSERTS 1155 * Get (and optionally clear) the current assertion status. Only 1156 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other 1157 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS 1158 */ 1159 #define MC_CMD_GET_ASSERTS 0x6 1160 1161 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1162 1163 /* MC_CMD_GET_ASSERTS_IN msgrequest */ 1164 #define MC_CMD_GET_ASSERTS_IN_LEN 4 1165 /* Set to clear assertion */ 1166 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 1167 #define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4 1168 1169 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ 1170 #define MC_CMD_GET_ASSERTS_OUT_LEN 140 1171 /* Assertion status flag. */ 1172 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 1173 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4 1174 /* enum: No assertions have failed. */ 1175 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 1176 /* enum: A system-level assertion has failed. */ 1177 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 1178 /* enum: A thread-level assertion has failed. */ 1179 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 1180 /* enum: The system was reset by the watchdog. */ 1181 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 1182 /* enum: An illegal address trap stopped the system (huntington and later) */ 1183 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 1184 /* Failing PC value */ 1185 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 1186 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4 1187 /* Saved GP regs */ 1188 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 1189 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 1190 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 1191 /* enum: A magic value hinting that the value in this register at the time of 1192 * the failure has likely been lost. 1193 */ 1194 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 1195 /* Failing thread address */ 1196 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 1197 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4 1198 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 1199 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4 1200 1201 1202 /***********************************/ 1203 /* MC_CMD_LOG_CTRL 1204 * Configure the output stream for log events such as link state changes, 1205 * sensor notifications and MCDI completions 1206 */ 1207 #define MC_CMD_LOG_CTRL 0x7 1208 1209 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1210 1211 /* MC_CMD_LOG_CTRL_IN msgrequest */ 1212 #define MC_CMD_LOG_CTRL_IN_LEN 8 1213 /* Log destination */ 1214 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 1215 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4 1216 /* enum: UART. */ 1217 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 1218 /* enum: Event queue. */ 1219 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 1220 /* Legacy argument. Must be zero. */ 1221 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 1222 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4 1223 1224 /* MC_CMD_LOG_CTRL_OUT msgresponse */ 1225 #define MC_CMD_LOG_CTRL_OUT_LEN 0 1226 1227 1228 /***********************************/ 1229 /* MC_CMD_GET_VERSION 1230 * Get version information about the MC firmware. 1231 */ 1232 #define MC_CMD_GET_VERSION 0x8 1233 1234 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1235 1236 /* MC_CMD_GET_VERSION_IN msgrequest */ 1237 #define MC_CMD_GET_VERSION_IN_LEN 0 1238 1239 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ 1240 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 1241 /* placeholder, set to 0 */ 1242 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 1243 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4 1244 1245 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ 1246 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 1247 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 1248 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 1249 /* enum: Reserved version number to indicate "any" version. */ 1250 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff 1251 /* enum: Bootrom version value for Siena. */ 1252 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 1253 /* enum: Bootrom version value for Huntington. */ 1254 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 1255 /* enum: Bootrom version value for Medford2. */ 1256 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002 1257 1258 /* MC_CMD_GET_VERSION_OUT msgresponse */ 1259 #define MC_CMD_GET_VERSION_OUT_LEN 32 1260 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1261 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 1262 /* Enum values, see field(s): */ 1263 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1264 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 1265 #define MC_CMD_GET_VERSION_OUT_PCOL_LEN 4 1266 /* 128bit mask of functions supported by the current firmware */ 1267 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 1268 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 1269 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 1270 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 1271 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 1272 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 1273 1274 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ 1275 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 1276 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1277 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 1278 /* Enum values, see field(s): */ 1279 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1280 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 1281 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4 1282 /* 128bit mask of functions supported by the current firmware */ 1283 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 1284 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 1285 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 1286 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 1287 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 1288 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 1289 /* extra info */ 1290 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 1291 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 1292 1293 1294 /***********************************/ 1295 /* MC_CMD_PTP 1296 * Perform PTP operation 1297 */ 1298 #define MC_CMD_PTP 0xb 1299 1300 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1301 1302 /* MC_CMD_PTP_IN msgrequest */ 1303 #define MC_CMD_PTP_IN_LEN 1 1304 /* PTP operation code */ 1305 #define MC_CMD_PTP_IN_OP_OFST 0 1306 #define MC_CMD_PTP_IN_OP_LEN 1 1307 /* enum: Enable PTP packet timestamping operation. */ 1308 #define MC_CMD_PTP_OP_ENABLE 0x1 1309 /* enum: Disable PTP packet timestamping operation. */ 1310 #define MC_CMD_PTP_OP_DISABLE 0x2 1311 /* enum: Send a PTP packet. This operation is used on Siena and Huntington. 1312 * From Medford onwards it is not supported: on those platforms PTP transmit 1313 * timestamping is done using the fast path. 1314 */ 1315 #define MC_CMD_PTP_OP_TRANSMIT 0x3 1316 /* enum: Read the current NIC time. */ 1317 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 1318 /* enum: Get the current PTP status. Note that the clock frequency returned (in 1319 * Hz) is rounded to the nearest MHz (e.g. 666000000 for 666666666). 1320 */ 1321 #define MC_CMD_PTP_OP_STATUS 0x5 1322 /* enum: Adjust the PTP NIC's time. */ 1323 #define MC_CMD_PTP_OP_ADJUST 0x6 1324 /* enum: Synchronize host and NIC time. */ 1325 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 1326 /* enum: Basic manufacturing tests. Siena PTP adapters only. */ 1327 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 1328 /* enum: Packet based manufacturing tests. Siena PTP adapters only. */ 1329 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 1330 /* enum: Reset some of the PTP related statistics */ 1331 #define MC_CMD_PTP_OP_RESET_STATS 0xa 1332 /* enum: Debug operations to MC. */ 1333 #define MC_CMD_PTP_OP_DEBUG 0xb 1334 /* enum: Read an FPGA register. Siena PTP adapters only. */ 1335 #define MC_CMD_PTP_OP_FPGAREAD 0xc 1336 /* enum: Write an FPGA register. Siena PTP adapters only. */ 1337 #define MC_CMD_PTP_OP_FPGAWRITE 0xd 1338 /* enum: Apply an offset to the NIC clock */ 1339 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe 1340 /* enum: Change the frequency correction applied to the NIC clock */ 1341 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf 1342 /* enum: Set the MC packet filter VLAN tags for received PTP packets. 1343 * Deprecated for Huntington onwards. 1344 */ 1345 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 1346 /* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for 1347 * Huntington onwards. 1348 */ 1349 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 1350 /* enum: Set the MC packet filter Domain for received PTP packets. Deprecated 1351 * for Huntington onwards. 1352 */ 1353 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 1354 /* enum: Set the clock source. Required for snapper tests on Huntington and 1355 * Medford. Not implemented for Siena or Medford2. 1356 */ 1357 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 1358 /* enum: Reset value of Timer Reg. Not implemented. */ 1359 #define MC_CMD_PTP_OP_RST_CLK 0x14 1360 /* enum: Enable the forwarding of PPS events to the host */ 1361 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 1362 /* enum: Get the time format used by this NIC for PTP operations */ 1363 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 1364 /* enum: Get the clock attributes. NOTE- extended version of 1365 * MC_CMD_PTP_OP_GET_TIME_FORMAT 1366 */ 1367 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 1368 /* enum: Get corrections that should be applied to the various different 1369 * timestamps 1370 */ 1371 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 1372 /* enum: Subscribe to receive periodic time events indicating the current NIC 1373 * time 1374 */ 1375 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 1376 /* enum: Unsubscribe to stop receiving time events */ 1377 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 1378 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS 1379 * input on the same NIC. Siena PTP adapters only. 1380 */ 1381 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a 1382 /* enum: Set the PTP sync status. Status is used by firmware to report to event 1383 * subscribers. 1384 */ 1385 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b 1386 /* enum: Above this for future use. */ 1387 #define MC_CMD_PTP_OP_MAX 0x1c 1388 1389 /* MC_CMD_PTP_IN_ENABLE msgrequest */ 1390 #define MC_CMD_PTP_IN_ENABLE_LEN 16 1391 #define MC_CMD_PTP_IN_CMD_OFST 0 1392 #define MC_CMD_PTP_IN_CMD_LEN 4 1393 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 1394 #define MC_CMD_PTP_IN_PERIPH_ID_LEN 4 1395 /* Not used. Events are always sent to function relative queue 0. */ 1396 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 1397 #define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4 1398 /* PTP timestamping mode. Not used from Huntington onwards. */ 1399 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 1400 #define MC_CMD_PTP_IN_ENABLE_MODE_LEN 4 1401 /* enum: PTP, version 1 */ 1402 #define MC_CMD_PTP_MODE_V1 0x0 1403 /* enum: PTP, version 1, with VLAN headers - deprecated */ 1404 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 1405 /* enum: PTP, version 2 */ 1406 #define MC_CMD_PTP_MODE_V2 0x2 1407 /* enum: PTP, version 2, with VLAN headers - deprecated */ 1408 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 1409 /* enum: PTP, version 2, with improved UUID filtering */ 1410 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 1411 /* enum: FCoE (seconds and microseconds) */ 1412 #define MC_CMD_PTP_MODE_FCOE 0x5 1413 1414 /* MC_CMD_PTP_IN_DISABLE msgrequest */ 1415 #define MC_CMD_PTP_IN_DISABLE_LEN 8 1416 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1417 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1418 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1419 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1420 1421 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 1422 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 1423 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 1424 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 1425 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1426 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1427 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1428 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1429 /* Transmit packet length */ 1430 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 1431 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4 1432 /* Transmit packet data */ 1433 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 1434 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 1435 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 1436 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 1437 1438 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 1439 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 1440 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1441 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1442 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1443 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1444 1445 /* MC_CMD_PTP_IN_READ_NIC_TIME_V2 msgrequest */ 1446 #define MC_CMD_PTP_IN_READ_NIC_TIME_V2_LEN 8 1447 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1448 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1449 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1450 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1451 1452 /* MC_CMD_PTP_IN_STATUS msgrequest */ 1453 #define MC_CMD_PTP_IN_STATUS_LEN 8 1454 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1455 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1456 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1457 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1458 1459 /* MC_CMD_PTP_IN_ADJUST msgrequest */ 1460 #define MC_CMD_PTP_IN_ADJUST_LEN 24 1461 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1462 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1463 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1464 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1465 /* Frequency adjustment 40 bit fixed point ns */ 1466 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 1467 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 1468 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 1469 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 1470 /* enum: Number of fractional bits in frequency adjustment */ 1471 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 1472 /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ 1473 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES 1474 * field. 1475 */ 1476 #define MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c 1477 /* Time adjustment in seconds */ 1478 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 1479 #define MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4 1480 /* Time adjustment major value */ 1481 #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 1482 #define MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4 1483 /* Time adjustment in nanoseconds */ 1484 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 1485 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4 1486 /* Time adjustment minor value */ 1487 #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 1488 #define MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4 1489 1490 /* MC_CMD_PTP_IN_ADJUST_V2 msgrequest */ 1491 #define MC_CMD_PTP_IN_ADJUST_V2_LEN 28 1492 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1493 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1494 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1495 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1496 /* Frequency adjustment 40 bit fixed point ns */ 1497 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8 1498 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8 1499 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8 1500 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12 1501 /* enum: Number of fractional bits in frequency adjustment */ 1502 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ 1503 /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ 1504 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES 1505 * field. 1506 */ 1507 /* MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */ 1508 /* Time adjustment in seconds */ 1509 #define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_OFST 16 1510 #define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4 1511 /* Time adjustment major value */ 1512 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_OFST 16 1513 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4 1514 /* Time adjustment in nanoseconds */ 1515 #define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_OFST 20 1516 #define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4 1517 /* Time adjustment minor value */ 1518 #define MC_CMD_PTP_IN_ADJUST_V2_MINOR_OFST 20 1519 #define MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4 1520 /* Upper 32bits of major time offset adjustment */ 1521 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_OFST 24 1522 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4 1523 1524 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 1525 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 1526 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1527 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1528 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1529 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1530 /* Number of time readings to capture */ 1531 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 1532 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4 1533 /* Host address in which to write "synchronization started" indication (64 1534 * bits) 1535 */ 1536 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 1537 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 1538 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 1539 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 1540 1541 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 1542 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 1543 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1544 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1545 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1546 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1547 1548 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 1549 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 1550 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1551 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1552 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1553 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1554 /* Enable or disable packet testing */ 1555 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 1556 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4 1557 1558 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ 1559 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 1560 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1561 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1562 /* Reset PTP statistics */ 1563 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1564 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1565 1566 /* MC_CMD_PTP_IN_DEBUG msgrequest */ 1567 #define MC_CMD_PTP_IN_DEBUG_LEN 12 1568 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1569 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1570 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1571 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1572 /* Debug operations */ 1573 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 1574 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4 1575 1576 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ 1577 #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 1578 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1579 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1580 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1581 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1582 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 1583 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4 1584 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 1585 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4 1586 1587 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ 1588 #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 1589 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 1590 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) 1591 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1592 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1593 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1594 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1595 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 1596 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4 1597 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 1598 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 1599 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 1600 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 1601 1602 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ 1603 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 1604 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1605 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1606 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1607 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1608 /* Time adjustment in seconds */ 1609 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 1610 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4 1611 /* Time adjustment major value */ 1612 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 1613 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4 1614 /* Time adjustment in nanoseconds */ 1615 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 1616 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4 1617 /* Time adjustment minor value */ 1618 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 1619 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4 1620 1621 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2 msgrequest */ 1622 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_LEN 20 1623 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1624 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1625 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1626 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1627 /* Time adjustment in seconds */ 1628 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_OFST 8 1629 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4 1630 /* Time adjustment major value */ 1631 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_OFST 8 1632 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4 1633 /* Time adjustment in nanoseconds */ 1634 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_OFST 12 1635 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4 1636 /* Time adjustment minor value */ 1637 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_OFST 12 1638 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4 1639 /* Upper 32bits of major time offset adjustment */ 1640 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_OFST 16 1641 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4 1642 1643 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ 1644 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 1645 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1646 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1647 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1648 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1649 /* Frequency adjustment 40 bit fixed point ns */ 1650 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 1651 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 1652 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 1653 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 1654 /* Enum values, see field(s): */ 1655 /* MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */ 1656 1657 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ 1658 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 1659 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1660 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1661 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1662 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1663 /* Number of VLAN tags, 0 if not VLAN */ 1664 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 1665 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4 1666 /* Set of VLAN tags to filter against */ 1667 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 1668 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 1669 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 1670 1671 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ 1672 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 1673 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1674 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1675 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1676 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1677 /* 1 to enable UUID filtering, 0 to disable */ 1678 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 1679 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4 1680 /* UUID to filter against */ 1681 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 1682 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 1683 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 1684 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 1685 1686 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ 1687 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 1688 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1689 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1690 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1691 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1692 /* 1 to enable Domain filtering, 0 to disable */ 1693 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 1694 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4 1695 /* Domain number to filter against */ 1696 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 1697 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4 1698 1699 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ 1700 #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 1701 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1702 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1703 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1704 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1705 /* Set the clock source. */ 1706 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 1707 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4 1708 /* enum: Internal. */ 1709 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 1710 /* enum: External. */ 1711 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 1712 1713 /* MC_CMD_PTP_IN_RST_CLK msgrequest */ 1714 #define MC_CMD_PTP_IN_RST_CLK_LEN 8 1715 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1716 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1717 /* Reset value of Timer Reg. */ 1718 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1719 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1720 1721 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ 1722 #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 1723 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1724 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1725 /* Enable or disable */ 1726 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 1727 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4 1728 /* enum: Enable */ 1729 #define MC_CMD_PTP_ENABLE_PPS 0x0 1730 /* enum: Disable */ 1731 #define MC_CMD_PTP_DISABLE_PPS 0x1 1732 /* Not used. Events are always sent to function relative queue 0. */ 1733 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 1734 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4 1735 1736 /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ 1737 #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 1738 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1739 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1740 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1741 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1742 1743 /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ 1744 #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 1745 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1746 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1747 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1748 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1749 1750 /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ 1751 #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 1752 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1753 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1754 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1755 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1756 1757 /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ 1758 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 1759 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1760 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1761 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1762 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1763 /* Original field containing queue ID. Now extended to include flags. */ 1764 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 1765 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4 1766 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0 1767 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16 1768 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31 1769 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1 1770 1771 /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ 1772 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 1773 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1774 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1775 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1776 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1777 /* Unsubscribe options */ 1778 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 1779 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4 1780 /* enum: Unsubscribe a single queue */ 1781 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 1782 /* enum: Unsubscribe all queues */ 1783 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 1784 /* Event queue ID */ 1785 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 1786 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4 1787 1788 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ 1789 #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 1790 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1791 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1792 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1793 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1794 /* 1 to enable PPS test mode, 0 to disable and return result. */ 1795 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 1796 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4 1797 1798 /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */ 1799 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24 1800 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1801 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1802 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1803 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1804 /* NIC - Host System Clock Synchronization status */ 1805 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8 1806 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4 1807 /* enum: Host System clock and NIC clock are not in sync */ 1808 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0 1809 /* enum: Host System clock and NIC clock are synchronized */ 1810 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1 1811 /* If synchronized, number of seconds until clocks should be considered to be 1812 * no longer in sync. 1813 */ 1814 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12 1815 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4 1816 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16 1817 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4 1818 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 1819 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4 1820 1821 /* MC_CMD_PTP_OUT msgresponse */ 1822 #define MC_CMD_PTP_OUT_LEN 0 1823 1824 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 1825 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 1826 /* Value of seconds timestamp */ 1827 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 1828 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4 1829 /* Timestamp major value */ 1830 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 1831 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4 1832 /* Value of nanoseconds timestamp */ 1833 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 1834 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4 1835 /* Timestamp minor value */ 1836 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 1837 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4 1838 1839 /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ 1840 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 1841 1842 /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ 1843 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 1844 1845 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 1846 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 1847 /* Value of seconds timestamp */ 1848 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 1849 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4 1850 /* Timestamp major value */ 1851 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 1852 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4 1853 /* Value of nanoseconds timestamp */ 1854 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 1855 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4 1856 /* Timestamp minor value */ 1857 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 1858 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4 1859 1860 /* MC_CMD_PTP_OUT_READ_NIC_TIME_V2 msgresponse */ 1861 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_LEN 12 1862 /* Value of seconds timestamp */ 1863 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0 1864 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4 1865 /* Timestamp major value */ 1866 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0 1867 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4 1868 /* Value of nanoseconds timestamp */ 1869 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4 1870 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4 1871 /* Timestamp minor value */ 1872 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4 1873 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4 1874 /* Upper 32bits of major timestamp value */ 1875 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_OFST 8 1876 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4 1877 1878 /* MC_CMD_PTP_OUT_STATUS msgresponse */ 1879 #define MC_CMD_PTP_OUT_STATUS_LEN 64 1880 /* Frequency of NIC's hardware clock */ 1881 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 1882 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4 1883 /* Number of packets transmitted and timestamped */ 1884 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 1885 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4 1886 /* Number of packets received and timestamped */ 1887 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 1888 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4 1889 /* Number of packets timestamped by the FPGA */ 1890 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 1891 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4 1892 /* Number of packets filter matched */ 1893 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 1894 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4 1895 /* Number of packets not filter matched */ 1896 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 1897 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4 1898 /* Number of PPS overflows (noise on input?) */ 1899 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 1900 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4 1901 /* Number of PPS bad periods */ 1902 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 1903 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4 1904 /* Minimum period of PPS pulse in nanoseconds */ 1905 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 1906 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4 1907 /* Maximum period of PPS pulse in nanoseconds */ 1908 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 1909 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4 1910 /* Last period of PPS pulse in nanoseconds */ 1911 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 1912 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4 1913 /* Mean period of PPS pulse in nanoseconds */ 1914 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 1915 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4 1916 /* Minimum offset of PPS pulse in nanoseconds (signed) */ 1917 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 1918 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4 1919 /* Maximum offset of PPS pulse in nanoseconds (signed) */ 1920 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 1921 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4 1922 /* Last offset of PPS pulse in nanoseconds (signed) */ 1923 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 1924 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4 1925 /* Mean offset of PPS pulse in nanoseconds (signed) */ 1926 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 1927 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4 1928 1929 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 1930 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 1931 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 1932 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 1933 /* A set of host and NIC times */ 1934 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 1935 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 1936 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 1937 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 1938 /* Host time immediately before NIC's hardware clock read */ 1939 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 1940 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4 1941 /* Value of seconds timestamp */ 1942 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 1943 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4 1944 /* Timestamp major value */ 1945 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 1946 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4 1947 /* Value of nanoseconds timestamp */ 1948 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 1949 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4 1950 /* Timestamp minor value */ 1951 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 1952 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4 1953 /* Host time immediately after NIC's hardware clock read */ 1954 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 1955 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4 1956 /* Number of nanoseconds waited after reading NIC's hardware clock */ 1957 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 1958 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4 1959 1960 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 1961 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 1962 /* Results of testing */ 1963 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 1964 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4 1965 /* enum: Successful test */ 1966 #define MC_CMD_PTP_MANF_SUCCESS 0x0 1967 /* enum: FPGA load failed */ 1968 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 1969 /* enum: FPGA version invalid */ 1970 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 1971 /* enum: FPGA registers incorrect */ 1972 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 1973 /* enum: Oscillator possibly not working? */ 1974 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 1975 /* enum: Timestamps not increasing */ 1976 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 1977 /* enum: Mismatched packet count */ 1978 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 1979 /* enum: Mismatched packet count (Siena filter and FPGA) */ 1980 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 1981 /* enum: Not enough packets to perform timestamp check */ 1982 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 1983 /* enum: Timestamp trigger GPIO not working */ 1984 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 1985 /* enum: Insufficient PPS events to perform checks */ 1986 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa 1987 /* enum: PPS time event period not sufficiently close to 1s. */ 1988 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb 1989 /* enum: PPS time event nS reading not sufficiently close to zero. */ 1990 #define MC_CMD_PTP_MANF_PPS_NS 0xc 1991 /* enum: PTP peripheral registers incorrect */ 1992 #define MC_CMD_PTP_MANF_REGISTERS 0xd 1993 /* enum: Failed to read time from PTP peripheral */ 1994 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe 1995 /* Presence of external oscillator */ 1996 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 1997 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4 1998 1999 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 2000 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 2001 /* Results of testing */ 2002 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 2003 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4 2004 /* Number of packets received by FPGA */ 2005 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 2006 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4 2007 /* Number of packets received by Siena filters */ 2008 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 2009 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4 2010 2011 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ 2012 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 2013 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 2014 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) 2015 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 2016 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 2017 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 2018 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 2019 2020 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ 2021 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 2022 /* Time format required/used by for this NIC. Applies to all PTP MCDI 2023 * operations that pass times between the host and firmware. If this operation 2024 * is not supported (older firmware) a format of seconds and nanoseconds should 2025 * be assumed. Note this enum is deprecated. Do not add to it- use the 2026 * TIME_FORMAT field in MC_CMD_PTP_OUT_GET_ATTRIBUTES instead. 2027 */ 2028 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 2029 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4 2030 /* enum: Times are in seconds and nanoseconds */ 2031 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 2032 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 2033 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 2034 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 2035 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 2036 2037 /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ 2038 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24 2039 /* Time format required/used by for this NIC. Applies to all PTP MCDI 2040 * operations that pass times between the host and firmware. If this operation 2041 * is not supported (older firmware) a format of seconds and nanoseconds should 2042 * be assumed. 2043 */ 2044 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 2045 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4 2046 /* enum: Times are in seconds and nanoseconds */ 2047 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 2048 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 2049 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 2050 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 2051 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 2052 /* enum: Major register units are seconds, minor units are quarter nanoseconds 2053 */ 2054 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3 2055 /* Minimum acceptable value for a corrected synchronization timeset. When 2056 * comparing host and NIC clock times, the MC returns a set of samples that 2057 * contain the host start and end time, the MC time when the host start was 2058 * detected and the time the MC waited between reading the time and detecting 2059 * the host end. The corrected sync window is the difference between the host 2060 * end and start times minus the time that the MC waited for host end. 2061 */ 2062 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 2063 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4 2064 /* Various PTP capabilities */ 2065 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8 2066 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4 2067 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0 2068 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1 2069 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1 2070 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1 2071 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 2 2072 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1 2073 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 3 2074 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1 2075 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12 2076 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4 2077 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16 2078 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4 2079 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20 2080 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4 2081 2082 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ 2083 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 2084 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 2085 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 2086 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4 2087 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 2088 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 2089 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4 2090 /* Uncorrected error on PPS output in NIC clock format */ 2091 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 2092 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4 2093 /* Uncorrected error on PPS input in NIC clock format */ 2094 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 2095 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4 2096 2097 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */ 2098 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24 2099 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 2100 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0 2101 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4 2102 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 2103 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4 2104 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4 2105 /* Uncorrected error on PPS output in NIC clock format */ 2106 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8 2107 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4 2108 /* Uncorrected error on PPS input in NIC clock format */ 2109 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12 2110 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4 2111 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */ 2112 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16 2113 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4 2114 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */ 2115 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20 2116 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4 2117 2118 /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ 2119 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 2120 /* Results of testing */ 2121 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 2122 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4 2123 /* Enum values, see field(s): */ 2124 /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ 2125 2126 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ 2127 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 2128 2129 2130 /***********************************/ 2131 /* MC_CMD_CSR_READ32 2132 * Read 32bit words from the indirect memory map. 2133 */ 2134 #define MC_CMD_CSR_READ32 0xc 2135 2136 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2137 2138 /* MC_CMD_CSR_READ32_IN msgrequest */ 2139 #define MC_CMD_CSR_READ32_IN_LEN 12 2140 /* Address */ 2141 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 2142 #define MC_CMD_CSR_READ32_IN_ADDR_LEN 4 2143 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 2144 #define MC_CMD_CSR_READ32_IN_STEP_LEN 4 2145 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 2146 #define MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4 2147 2148 /* MC_CMD_CSR_READ32_OUT msgresponse */ 2149 #define MC_CMD_CSR_READ32_OUT_LENMIN 4 2150 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 2151 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 2152 /* The last dword is the status, not a value read */ 2153 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 2154 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 2155 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 2156 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 2157 2158 2159 /***********************************/ 2160 /* MC_CMD_CSR_WRITE32 2161 * Write 32bit dwords to the indirect memory map. 2162 */ 2163 #define MC_CMD_CSR_WRITE32 0xd 2164 2165 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2166 2167 /* MC_CMD_CSR_WRITE32_IN msgrequest */ 2168 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 2169 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 2170 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 2171 /* Address */ 2172 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 2173 #define MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4 2174 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 2175 #define MC_CMD_CSR_WRITE32_IN_STEP_LEN 4 2176 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 2177 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 2178 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 2179 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 2180 2181 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 2182 #define MC_CMD_CSR_WRITE32_OUT_LEN 4 2183 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 2184 #define MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4 2185 2186 2187 /***********************************/ 2188 /* MC_CMD_HP 2189 * These commands are used for HP related features. They are grouped under one 2190 * MCDI command to avoid creating too many MCDI commands. 2191 */ 2192 #define MC_CMD_HP 0x54 2193 2194 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2195 2196 /* MC_CMD_HP_IN msgrequest */ 2197 #define MC_CMD_HP_IN_LEN 16 2198 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at 2199 * the specified address with the specified interval.When address is NULL, 2200 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current 2201 * state / 2: (debug) Show temperature reported by one of the supported 2202 * sensors. 2203 */ 2204 #define MC_CMD_HP_IN_SUBCMD_OFST 0 2205 #define MC_CMD_HP_IN_SUBCMD_LEN 4 2206 /* enum: OCSD (Option Card Sensor Data) sub-command. */ 2207 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 2208 /* enum: Last known valid HP sub-command. */ 2209 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 2210 /* The address to the array of sensor fields. (Or NULL to use a sub-command.) 2211 */ 2212 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 2213 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 2214 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 2215 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 2216 /* The requested update interval, in seconds. (Or the sub-command if ADDR is 2217 * NULL.) 2218 */ 2219 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 2220 #define MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4 2221 2222 /* MC_CMD_HP_OUT msgresponse */ 2223 #define MC_CMD_HP_OUT_LEN 4 2224 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 2225 #define MC_CMD_HP_OUT_OCSD_STATUS_LEN 4 2226 /* enum: OCSD stopped for this card. */ 2227 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 2228 /* enum: OCSD was successfully started with the address provided. */ 2229 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 2230 /* enum: OCSD was already started for this card. */ 2231 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 2232 2233 2234 /***********************************/ 2235 /* MC_CMD_STACKINFO 2236 * Get stack information. 2237 */ 2238 #define MC_CMD_STACKINFO 0xf 2239 2240 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2241 2242 /* MC_CMD_STACKINFO_IN msgrequest */ 2243 #define MC_CMD_STACKINFO_IN_LEN 0 2244 2245 /* MC_CMD_STACKINFO_OUT msgresponse */ 2246 #define MC_CMD_STACKINFO_OUT_LENMIN 12 2247 #define MC_CMD_STACKINFO_OUT_LENMAX 252 2248 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 2249 /* (thread ptr, stack size, free space) for each thread in system */ 2250 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 2251 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 2252 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 2253 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 2254 2255 2256 /***********************************/ 2257 /* MC_CMD_MDIO_READ 2258 * MDIO register read. 2259 */ 2260 #define MC_CMD_MDIO_READ 0x10 2261 2262 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2263 2264 /* MC_CMD_MDIO_READ_IN msgrequest */ 2265 #define MC_CMD_MDIO_READ_IN_LEN 16 2266 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 2267 * external devices. 2268 */ 2269 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 2270 #define MC_CMD_MDIO_READ_IN_BUS_LEN 4 2271 /* enum: Internal. */ 2272 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 2273 /* enum: External. */ 2274 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 2275 /* Port address */ 2276 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 2277 #define MC_CMD_MDIO_READ_IN_PRTAD_LEN 4 2278 /* Device Address or clause 22. */ 2279 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 2280 #define MC_CMD_MDIO_READ_IN_DEVAD_LEN 4 2281 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 2282 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 2283 */ 2284 #define MC_CMD_MDIO_CLAUSE22 0x20 2285 /* Address */ 2286 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 2287 #define MC_CMD_MDIO_READ_IN_ADDR_LEN 4 2288 2289 /* MC_CMD_MDIO_READ_OUT msgresponse */ 2290 #define MC_CMD_MDIO_READ_OUT_LEN 8 2291 /* Value */ 2292 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 2293 #define MC_CMD_MDIO_READ_OUT_VALUE_LEN 4 2294 /* Status the MDIO commands return the raw status bits from the MDIO block. A 2295 * "good" transaction should have the DONE bit set and all other bits clear. 2296 */ 2297 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 2298 #define MC_CMD_MDIO_READ_OUT_STATUS_LEN 4 2299 /* enum: Good. */ 2300 #define MC_CMD_MDIO_STATUS_GOOD 0x8 2301 2302 2303 /***********************************/ 2304 /* MC_CMD_MDIO_WRITE 2305 * MDIO register write. 2306 */ 2307 #define MC_CMD_MDIO_WRITE 0x11 2308 2309 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2310 2311 /* MC_CMD_MDIO_WRITE_IN msgrequest */ 2312 #define MC_CMD_MDIO_WRITE_IN_LEN 20 2313 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 2314 * external devices. 2315 */ 2316 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 2317 #define MC_CMD_MDIO_WRITE_IN_BUS_LEN 4 2318 /* enum: Internal. */ 2319 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 2320 /* enum: External. */ 2321 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 2322 /* Port address */ 2323 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 2324 #define MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4 2325 /* Device Address or clause 22. */ 2326 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 2327 #define MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4 2328 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 2329 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 2330 */ 2331 /* MC_CMD_MDIO_CLAUSE22 0x20 */ 2332 /* Address */ 2333 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 2334 #define MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4 2335 /* Value */ 2336 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 2337 #define MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4 2338 2339 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 2340 #define MC_CMD_MDIO_WRITE_OUT_LEN 4 2341 /* Status; the MDIO commands return the raw status bits from the MDIO block. A 2342 * "good" transaction should have the DONE bit set and all other bits clear. 2343 */ 2344 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 2345 #define MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4 2346 /* enum: Good. */ 2347 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 2348 2349 2350 /***********************************/ 2351 /* MC_CMD_DBI_WRITE 2352 * Write DBI register(s). 2353 */ 2354 #define MC_CMD_DBI_WRITE 0x12 2355 2356 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2357 2358 /* MC_CMD_DBI_WRITE_IN msgrequest */ 2359 #define MC_CMD_DBI_WRITE_IN_LENMIN 12 2360 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 2361 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 2362 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset 2363 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. 2364 */ 2365 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 2366 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 2367 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 2368 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 2369 2370 /* MC_CMD_DBI_WRITE_OUT msgresponse */ 2371 #define MC_CMD_DBI_WRITE_OUT_LEN 0 2372 2373 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 2374 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 2375 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 2376 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4 2377 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 2378 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 2379 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 2380 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4 2381 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 2382 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 2383 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 2384 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 2385 #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 2386 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 2387 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 2388 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 2389 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 2390 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4 2391 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 2392 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 2393 2394 2395 /***********************************/ 2396 /* MC_CMD_PORT_READ32 2397 * Read a 32-bit register from the indirect port register map. The port to 2398 * access is implied by the Shared memory channel used. 2399 */ 2400 #define MC_CMD_PORT_READ32 0x14 2401 2402 /* MC_CMD_PORT_READ32_IN msgrequest */ 2403 #define MC_CMD_PORT_READ32_IN_LEN 4 2404 /* Address */ 2405 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 2406 #define MC_CMD_PORT_READ32_IN_ADDR_LEN 4 2407 2408 /* MC_CMD_PORT_READ32_OUT msgresponse */ 2409 #define MC_CMD_PORT_READ32_OUT_LEN 8 2410 /* Value */ 2411 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 2412 #define MC_CMD_PORT_READ32_OUT_VALUE_LEN 4 2413 /* Status */ 2414 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 2415 #define MC_CMD_PORT_READ32_OUT_STATUS_LEN 4 2416 2417 2418 /***********************************/ 2419 /* MC_CMD_PORT_WRITE32 2420 * Write a 32-bit register to the indirect port register map. The port to 2421 * access is implied by the Shared memory channel used. 2422 */ 2423 #define MC_CMD_PORT_WRITE32 0x15 2424 2425 /* MC_CMD_PORT_WRITE32_IN msgrequest */ 2426 #define MC_CMD_PORT_WRITE32_IN_LEN 8 2427 /* Address */ 2428 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 2429 #define MC_CMD_PORT_WRITE32_IN_ADDR_LEN 4 2430 /* Value */ 2431 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 2432 #define MC_CMD_PORT_WRITE32_IN_VALUE_LEN 4 2433 2434 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 2435 #define MC_CMD_PORT_WRITE32_OUT_LEN 4 2436 /* Status */ 2437 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 2438 #define MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4 2439 2440 2441 /***********************************/ 2442 /* MC_CMD_PORT_READ128 2443 * Read a 128-bit register from the indirect port register map. The port to 2444 * access is implied by the Shared memory channel used. 2445 */ 2446 #define MC_CMD_PORT_READ128 0x16 2447 2448 /* MC_CMD_PORT_READ128_IN msgrequest */ 2449 #define MC_CMD_PORT_READ128_IN_LEN 4 2450 /* Address */ 2451 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 2452 #define MC_CMD_PORT_READ128_IN_ADDR_LEN 4 2453 2454 /* MC_CMD_PORT_READ128_OUT msgresponse */ 2455 #define MC_CMD_PORT_READ128_OUT_LEN 20 2456 /* Value */ 2457 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 2458 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 2459 /* Status */ 2460 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 2461 #define MC_CMD_PORT_READ128_OUT_STATUS_LEN 4 2462 2463 2464 /***********************************/ 2465 /* MC_CMD_PORT_WRITE128 2466 * Write a 128-bit register to the indirect port register map. The port to 2467 * access is implied by the Shared memory channel used. 2468 */ 2469 #define MC_CMD_PORT_WRITE128 0x17 2470 2471 /* MC_CMD_PORT_WRITE128_IN msgrequest */ 2472 #define MC_CMD_PORT_WRITE128_IN_LEN 20 2473 /* Address */ 2474 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 2475 #define MC_CMD_PORT_WRITE128_IN_ADDR_LEN 4 2476 /* Value */ 2477 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 2478 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 2479 2480 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 2481 #define MC_CMD_PORT_WRITE128_OUT_LEN 4 2482 /* Status */ 2483 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 2484 #define MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4 2485 2486 /* MC_CMD_CAPABILITIES structuredef */ 2487 #define MC_CMD_CAPABILITIES_LEN 4 2488 /* Small buf table. */ 2489 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 2490 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 2491 /* Turbo mode (for Maranello). */ 2492 #define MC_CMD_CAPABILITIES_TURBO_LBN 1 2493 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 2494 /* Turbo mode active (for Maranello). */ 2495 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 2496 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 2497 /* PTP offload. */ 2498 #define MC_CMD_CAPABILITIES_PTP_LBN 3 2499 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 2500 /* AOE mode. */ 2501 #define MC_CMD_CAPABILITIES_AOE_LBN 4 2502 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 2503 /* AOE mode active. */ 2504 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 2505 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 2506 /* AOE mode active. */ 2507 #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 2508 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 2509 #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 2510 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 2511 2512 2513 /***********************************/ 2514 /* MC_CMD_GET_BOARD_CFG 2515 * Returns the MC firmware configuration structure. 2516 */ 2517 #define MC_CMD_GET_BOARD_CFG 0x18 2518 2519 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2520 2521 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 2522 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 2523 2524 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 2525 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 2526 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 2527 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 2528 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 2529 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4 2530 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 2531 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 2532 /* Capabilities for Siena Port0 (see struct MC_CMD_CAPABILITIES). Unused on 2533 * EF10 and later (use MC_CMD_GET_CAPABILITIES). 2534 */ 2535 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 2536 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4 2537 /* Capabilities for Siena Port1 (see struct MC_CMD_CAPABILITIES). Unused on 2538 * EF10 and later (use MC_CMD_GET_CAPABILITIES). 2539 */ 2540 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 2541 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4 2542 /* Base MAC address for Siena Port0. Unused on EF10 and later (use 2543 * MC_CMD_GET_MAC_ADDRESSES). 2544 */ 2545 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 2546 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 2547 /* Base MAC address for Siena Port1. Unused on EF10 and later (use 2548 * MC_CMD_GET_MAC_ADDRESSES). 2549 */ 2550 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 2551 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 2552 /* Size of MAC address pool for Siena Port0. Unused on EF10 and later (use 2553 * MC_CMD_GET_MAC_ADDRESSES). 2554 */ 2555 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 2556 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4 2557 /* Size of MAC address pool for Siena Port1. Unused on EF10 and later (use 2558 * MC_CMD_GET_MAC_ADDRESSES). 2559 */ 2560 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 2561 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4 2562 /* Increment between addresses in MAC address pool for Siena Port0. Unused on 2563 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES). 2564 */ 2565 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 2566 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4 2567 /* Increment between addresses in MAC address pool for Siena Port1. Unused on 2568 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES). 2569 */ 2570 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 2571 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4 2572 /* Siena only. This field contains a 16-bit value for each of the types of 2573 * NVRAM area. The values are defined in the firmware/mc/platform/.c file for a 2574 * specific board type, but otherwise have no meaning to the MC; they are used 2575 * by the driver to manage selection of appropriate firmware updates. Unused on 2576 * EF10 and later (use MC_CMD_NVRAM_METADATA). 2577 */ 2578 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 2579 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 2580 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 2581 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 2582 2583 2584 /***********************************/ 2585 /* MC_CMD_DBI_READX 2586 * Read DBI register(s) -- extended functionality 2587 */ 2588 #define MC_CMD_DBI_READX 0x19 2589 2590 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2591 2592 /* MC_CMD_DBI_READX_IN msgrequest */ 2593 #define MC_CMD_DBI_READX_IN_LENMIN 8 2594 #define MC_CMD_DBI_READX_IN_LENMAX 248 2595 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 2596 /* Each Read op consists of an address (offset 0), VF/CS2) */ 2597 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 2598 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 2599 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 2600 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 2601 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 2602 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 2603 2604 /* MC_CMD_DBI_READX_OUT msgresponse */ 2605 #define MC_CMD_DBI_READX_OUT_LENMIN 4 2606 #define MC_CMD_DBI_READX_OUT_LENMAX 252 2607 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 2608 /* Value */ 2609 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 2610 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 2611 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 2612 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 2613 2614 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ 2615 #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 2616 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 2617 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4 2618 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 2619 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 2620 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 2621 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4 2622 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 2623 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 2624 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 2625 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 2626 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 2627 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 2628 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 2629 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 2630 2631 2632 /***********************************/ 2633 /* MC_CMD_SET_RAND_SEED 2634 * Set the 16byte seed for the MC pseudo-random generator. 2635 */ 2636 #define MC_CMD_SET_RAND_SEED 0x1a 2637 2638 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2639 2640 /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 2641 #define MC_CMD_SET_RAND_SEED_IN_LEN 16 2642 /* Seed value. */ 2643 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 2644 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 2645 2646 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 2647 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 2648 2649 2650 /***********************************/ 2651 /* MC_CMD_LTSSM_HIST 2652 * Retrieve the history of the LTSSM, if the build supports it. 2653 */ 2654 #define MC_CMD_LTSSM_HIST 0x1b 2655 2656 /* MC_CMD_LTSSM_HIST_IN msgrequest */ 2657 #define MC_CMD_LTSSM_HIST_IN_LEN 0 2658 2659 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 2660 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 2661 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 2662 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 2663 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ 2664 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 2665 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 2666 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 2667 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 2668 2669 2670 /***********************************/ 2671 /* MC_CMD_DRV_ATTACH 2672 * Inform MCPU that this port is managed on the host (i.e. driver active). For 2673 * Huntington, also request the preferred datapath firmware to use if possible 2674 * (it may not be possible for this request to be fulfilled; the driver must 2675 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which 2676 * features are actually available). The FIRMWARE_ID field is ignored by older 2677 * platforms. 2678 */ 2679 #define MC_CMD_DRV_ATTACH 0x1c 2680 2681 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2682 2683 /* MC_CMD_DRV_ATTACH_IN msgrequest */ 2684 #define MC_CMD_DRV_ATTACH_IN_LEN 12 2685 /* new state to set if UPDATE=1 */ 2686 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 2687 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4 2688 #define MC_CMD_DRV_ATTACH_LBN 0 2689 #define MC_CMD_DRV_ATTACH_WIDTH 1 2690 #define MC_CMD_DRV_PREBOOT_LBN 1 2691 #define MC_CMD_DRV_PREBOOT_WIDTH 1 2692 /* 1 to set new state, or 0 to just report the existing state */ 2693 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 2694 #define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4 2695 /* preferred datapath firmware (for Huntington; ignored for Siena) */ 2696 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 2697 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4 2698 /* enum: Prefer to use full featured firmware */ 2699 #define MC_CMD_FW_FULL_FEATURED 0x0 2700 /* enum: Prefer to use firmware with fewer features but lower latency */ 2701 #define MC_CMD_FW_LOW_LATENCY 0x1 2702 /* enum: Prefer to use firmware for SolarCapture packed stream mode */ 2703 #define MC_CMD_FW_PACKED_STREAM 0x2 2704 /* enum: Prefer to use firmware with fewer features and simpler TX event 2705 * batching but higher TX packet rate 2706 */ 2707 #define MC_CMD_FW_HIGH_TX_RATE 0x3 2708 /* enum: Reserved value */ 2709 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 2710 /* enum: Prefer to use firmware with additional "rules engine" filtering 2711 * support 2712 */ 2713 #define MC_CMD_FW_RULES_ENGINE 0x5 2714 /* enum: Only this option is allowed for non-admin functions */ 2715 #define MC_CMD_FW_DONT_CARE 0xffffffff 2716 2717 /* MC_CMD_DRV_ATTACH_OUT msgresponse */ 2718 #define MC_CMD_DRV_ATTACH_OUT_LEN 4 2719 /* previous or existing state, see the bitmask at NEW_STATE */ 2720 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 2721 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4 2722 2723 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ 2724 #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 2725 /* previous or existing state, see the bitmask at NEW_STATE */ 2726 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 2727 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4 2728 /* Flags associated with this function */ 2729 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 2730 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4 2731 /* enum: Labels the lowest-numbered function visible to the OS */ 2732 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 2733 /* enum: The function can control the link state of the physical port it is 2734 * bound to. 2735 */ 2736 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 2737 /* enum: The function can perform privileged operations */ 2738 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 2739 /* enum: The function does not have an active port associated with it. The port 2740 * refers to the Sorrento external FPGA port. 2741 */ 2742 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3 2743 2744 2745 /***********************************/ 2746 /* MC_CMD_SHMUART 2747 * Route UART output to circular buffer in shared memory instead. 2748 */ 2749 #define MC_CMD_SHMUART 0x1f 2750 2751 /* MC_CMD_SHMUART_IN msgrequest */ 2752 #define MC_CMD_SHMUART_IN_LEN 4 2753 /* ??? */ 2754 #define MC_CMD_SHMUART_IN_FLAG_OFST 0 2755 #define MC_CMD_SHMUART_IN_FLAG_LEN 4 2756 2757 /* MC_CMD_SHMUART_OUT msgresponse */ 2758 #define MC_CMD_SHMUART_OUT_LEN 0 2759 2760 2761 /***********************************/ 2762 /* MC_CMD_PORT_RESET 2763 * Generic per-port reset. There is no equivalent for per-board reset. Locks 2764 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - 2765 * use MC_CMD_ENTITY_RESET instead. 2766 */ 2767 #define MC_CMD_PORT_RESET 0x20 2768 2769 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2770 2771 /* MC_CMD_PORT_RESET_IN msgrequest */ 2772 #define MC_CMD_PORT_RESET_IN_LEN 0 2773 2774 /* MC_CMD_PORT_RESET_OUT msgresponse */ 2775 #define MC_CMD_PORT_RESET_OUT_LEN 0 2776 2777 2778 /***********************************/ 2779 /* MC_CMD_ENTITY_RESET 2780 * Generic per-resource reset. There is no equivalent for per-board reset. 2781 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an 2782 * extended version of the deprecated MC_CMD_PORT_RESET with added fields. 2783 */ 2784 #define MC_CMD_ENTITY_RESET 0x20 2785 /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */ 2786 2787 /* MC_CMD_ENTITY_RESET_IN msgrequest */ 2788 #define MC_CMD_ENTITY_RESET_IN_LEN 4 2789 /* Optional flags field. Omitting this will perform a "legacy" reset action 2790 * (TBD). 2791 */ 2792 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 2793 #define MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4 2794 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 2795 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 2796 2797 /* MC_CMD_ENTITY_RESET_OUT msgresponse */ 2798 #define MC_CMD_ENTITY_RESET_OUT_LEN 0 2799 2800 2801 /***********************************/ 2802 /* MC_CMD_PCIE_CREDITS 2803 * Read instantaneous and minimum flow control thresholds. 2804 */ 2805 #define MC_CMD_PCIE_CREDITS 0x21 2806 2807 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 2808 #define MC_CMD_PCIE_CREDITS_IN_LEN 8 2809 /* poll period. 0 is disabled */ 2810 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 2811 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4 2812 /* wipe statistics */ 2813 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 2814 #define MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4 2815 2816 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 2817 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 2818 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 2819 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 2820 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 2821 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 2822 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 2823 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 2824 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 2825 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 2826 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 2827 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 2828 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 2829 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 2830 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 2831 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 2832 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 2833 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 2834 2835 2836 /***********************************/ 2837 /* MC_CMD_RXD_MONITOR 2838 * Get histogram of RX queue fill level. 2839 */ 2840 #define MC_CMD_RXD_MONITOR 0x22 2841 2842 /* MC_CMD_RXD_MONITOR_IN msgrequest */ 2843 #define MC_CMD_RXD_MONITOR_IN_LEN 12 2844 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 2845 #define MC_CMD_RXD_MONITOR_IN_QID_LEN 4 2846 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 2847 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4 2848 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 2849 #define MC_CMD_RXD_MONITOR_IN_WIPE_LEN 4 2850 2851 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 2852 #define MC_CMD_RXD_MONITOR_OUT_LEN 80 2853 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 2854 #define MC_CMD_RXD_MONITOR_OUT_QID_LEN 4 2855 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 2856 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4 2857 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 2858 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4 2859 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 2860 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4 2861 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 2862 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4 2863 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 2864 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4 2865 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 2866 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4 2867 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 2868 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4 2869 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 2870 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4 2871 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 2872 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4 2873 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 2874 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4 2875 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 2876 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4 2877 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 2878 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4 2879 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 2880 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4 2881 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 2882 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4 2883 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 2884 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4 2885 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 2886 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4 2887 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 2888 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4 2889 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 2890 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4 2891 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 2892 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4 2893 2894 2895 /***********************************/ 2896 /* MC_CMD_PUTS 2897 * Copy the given ASCII string out onto UART and/or out of the network port. 2898 */ 2899 #define MC_CMD_PUTS 0x23 2900 2901 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2902 2903 /* MC_CMD_PUTS_IN msgrequest */ 2904 #define MC_CMD_PUTS_IN_LENMIN 13 2905 #define MC_CMD_PUTS_IN_LENMAX 252 2906 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 2907 #define MC_CMD_PUTS_IN_DEST_OFST 0 2908 #define MC_CMD_PUTS_IN_DEST_LEN 4 2909 #define MC_CMD_PUTS_IN_UART_LBN 0 2910 #define MC_CMD_PUTS_IN_UART_WIDTH 1 2911 #define MC_CMD_PUTS_IN_PORT_LBN 1 2912 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 2913 #define MC_CMD_PUTS_IN_DHOST_OFST 4 2914 #define MC_CMD_PUTS_IN_DHOST_LEN 6 2915 #define MC_CMD_PUTS_IN_STRING_OFST 12 2916 #define MC_CMD_PUTS_IN_STRING_LEN 1 2917 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 2918 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 2919 2920 /* MC_CMD_PUTS_OUT msgresponse */ 2921 #define MC_CMD_PUTS_OUT_LEN 0 2922 2923 2924 /***********************************/ 2925 /* MC_CMD_GET_PHY_CFG 2926 * Report PHY configuration. This guarantees to succeed even if the PHY is in a 2927 * 'zombie' state. Locks required: None 2928 */ 2929 #define MC_CMD_GET_PHY_CFG 0x24 2930 2931 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2932 2933 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 2934 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 2935 2936 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 2937 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 2938 /* flags */ 2939 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 2940 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4 2941 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 2942 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 2943 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 2944 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 2945 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 2946 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 2947 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 2948 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 2949 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 2950 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 2951 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 2952 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 2953 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 2954 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 2955 /* ?? */ 2956 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 2957 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4 2958 /* Bitmask of supported capabilities */ 2959 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 2960 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4 2961 #define MC_CMD_PHY_CAP_10HDX_LBN 1 2962 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 2963 #define MC_CMD_PHY_CAP_10FDX_LBN 2 2964 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 2965 #define MC_CMD_PHY_CAP_100HDX_LBN 3 2966 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 2967 #define MC_CMD_PHY_CAP_100FDX_LBN 4 2968 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 2969 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 2970 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 2971 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 2972 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 2973 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 2974 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 2975 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 2976 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 2977 #define MC_CMD_PHY_CAP_ASYM_LBN 9 2978 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 2979 #define MC_CMD_PHY_CAP_AN_LBN 10 2980 #define MC_CMD_PHY_CAP_AN_WIDTH 1 2981 #define MC_CMD_PHY_CAP_40000FDX_LBN 11 2982 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 2983 #define MC_CMD_PHY_CAP_DDM_LBN 12 2984 #define MC_CMD_PHY_CAP_DDM_WIDTH 1 2985 #define MC_CMD_PHY_CAP_100000FDX_LBN 13 2986 #define MC_CMD_PHY_CAP_100000FDX_WIDTH 1 2987 #define MC_CMD_PHY_CAP_25000FDX_LBN 14 2988 #define MC_CMD_PHY_CAP_25000FDX_WIDTH 1 2989 #define MC_CMD_PHY_CAP_50000FDX_LBN 15 2990 #define MC_CMD_PHY_CAP_50000FDX_WIDTH 1 2991 #define MC_CMD_PHY_CAP_BASER_FEC_LBN 16 2992 #define MC_CMD_PHY_CAP_BASER_FEC_WIDTH 1 2993 #define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 17 2994 #define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1 2995 #define MC_CMD_PHY_CAP_RS_FEC_LBN 18 2996 #define MC_CMD_PHY_CAP_RS_FEC_WIDTH 1 2997 #define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 19 2998 #define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1 2999 #define MC_CMD_PHY_CAP_25G_BASER_FEC_LBN 20 3000 #define MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1 3001 #define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 21 3002 #define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1 3003 /* ?? */ 3004 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 3005 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4 3006 /* ?? */ 3007 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 3008 #define MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4 3009 /* ?? */ 3010 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 3011 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4 3012 /* ?? */ 3013 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 3014 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 3015 /* ?? */ 3016 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 3017 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4 3018 /* enum: Xaui. */ 3019 #define MC_CMD_MEDIA_XAUI 0x1 3020 /* enum: CX4. */ 3021 #define MC_CMD_MEDIA_CX4 0x2 3022 /* enum: KX4. */ 3023 #define MC_CMD_MEDIA_KX4 0x3 3024 /* enum: XFP Far. */ 3025 #define MC_CMD_MEDIA_XFP 0x4 3026 /* enum: SFP+. */ 3027 #define MC_CMD_MEDIA_SFP_PLUS 0x5 3028 /* enum: 10GBaseT. */ 3029 #define MC_CMD_MEDIA_BASE_T 0x6 3030 /* enum: QSFP+. */ 3031 #define MC_CMD_MEDIA_QSFP_PLUS 0x7 3032 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 3033 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4 3034 /* enum: Native clause 22 */ 3035 #define MC_CMD_MMD_CLAUSE22 0x0 3036 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 3037 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 3038 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 3039 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 3040 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 3041 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 3042 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 3043 /* enum: Clause22 proxied over clause45 by PHY. */ 3044 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d 3045 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 3046 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 3047 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 3048 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 3049 3050 3051 /***********************************/ 3052 /* MC_CMD_START_BIST 3053 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST 3054 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) 3055 */ 3056 #define MC_CMD_START_BIST 0x25 3057 3058 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3059 3060 /* MC_CMD_START_BIST_IN msgrequest */ 3061 #define MC_CMD_START_BIST_IN_LEN 4 3062 /* Type of test. */ 3063 #define MC_CMD_START_BIST_IN_TYPE_OFST 0 3064 #define MC_CMD_START_BIST_IN_TYPE_LEN 4 3065 /* enum: Run the PHY's short cable BIST. */ 3066 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 3067 /* enum: Run the PHY's long cable BIST. */ 3068 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 3069 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ 3070 #define MC_CMD_BPX_SERDES_BIST 0x3 3071 /* enum: Run the MC loopback tests. */ 3072 #define MC_CMD_MC_LOOPBACK_BIST 0x4 3073 /* enum: Run the PHY's standard BIST. */ 3074 #define MC_CMD_PHY_BIST 0x5 3075 /* enum: Run MC RAM test. */ 3076 #define MC_CMD_MC_MEM_BIST 0x6 3077 /* enum: Run Port RAM test. */ 3078 #define MC_CMD_PORT_MEM_BIST 0x7 3079 /* enum: Run register test. */ 3080 #define MC_CMD_REG_BIST 0x8 3081 3082 /* MC_CMD_START_BIST_OUT msgresponse */ 3083 #define MC_CMD_START_BIST_OUT_LEN 0 3084 3085 3086 /***********************************/ 3087 /* MC_CMD_POLL_BIST 3088 * Poll for BIST completion. Returns a single status code, and optionally some 3089 * PHY specific bist output. The driver should only consume the BIST output 3090 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't 3091 * successfully parse the BIST output, it should still respect the pass/Fail in 3092 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, 3093 * EACCES (if PHY_LOCK is not held). 3094 */ 3095 #define MC_CMD_POLL_BIST 0x26 3096 3097 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3098 3099 /* MC_CMD_POLL_BIST_IN msgrequest */ 3100 #define MC_CMD_POLL_BIST_IN_LEN 0 3101 3102 /* MC_CMD_POLL_BIST_OUT msgresponse */ 3103 #define MC_CMD_POLL_BIST_OUT_LEN 8 3104 /* result */ 3105 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 3106 #define MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 3107 /* enum: Running. */ 3108 #define MC_CMD_POLL_BIST_RUNNING 0x1 3109 /* enum: Passed. */ 3110 #define MC_CMD_POLL_BIST_PASSED 0x2 3111 /* enum: Failed. */ 3112 #define MC_CMD_POLL_BIST_FAILED 0x3 3113 /* enum: Timed-out. */ 3114 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 3115 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 3116 #define MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4 3117 3118 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 3119 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 3120 /* result */ 3121 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 3122 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */ 3123 /* Enum values, see field(s): */ 3124 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 3125 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 3126 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4 3127 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 3128 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4 3129 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 3130 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4 3131 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 3132 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4 3133 /* Status of each channel A */ 3134 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 3135 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4 3136 /* enum: Ok. */ 3137 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 3138 /* enum: Open. */ 3139 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 3140 /* enum: Intra-pair short. */ 3141 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 3142 /* enum: Inter-pair short. */ 3143 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 3144 /* enum: Busy. */ 3145 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 3146 /* Status of each channel B */ 3147 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 3148 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4 3149 /* Enum values, see field(s): */ 3150 /* CABLE_STATUS_A */ 3151 /* Status of each channel C */ 3152 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 3153 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4 3154 /* Enum values, see field(s): */ 3155 /* CABLE_STATUS_A */ 3156 /* Status of each channel D */ 3157 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 3158 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4 3159 /* Enum values, see field(s): */ 3160 /* CABLE_STATUS_A */ 3161 3162 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 3163 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 3164 /* result */ 3165 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 3166 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */ 3167 /* Enum values, see field(s): */ 3168 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 3169 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 3170 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4 3171 /* enum: Complete. */ 3172 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 3173 /* enum: Bus switch off I2C write. */ 3174 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 3175 /* enum: Bus switch off I2C no access IO exp. */ 3176 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 3177 /* enum: Bus switch off I2C no access module. */ 3178 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 3179 /* enum: IO exp I2C configure. */ 3180 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 3181 /* enum: Bus switch I2C no cross talk. */ 3182 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 3183 /* enum: Module presence. */ 3184 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 3185 /* enum: Module ID I2C access. */ 3186 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 3187 /* enum: Module ID sane value. */ 3188 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 3189 3190 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ 3191 #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 3192 /* result */ 3193 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 3194 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */ 3195 /* Enum values, see field(s): */ 3196 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 3197 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 3198 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4 3199 /* enum: Test has completed. */ 3200 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 3201 /* enum: RAM test - walk ones. */ 3202 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 3203 /* enum: RAM test - walk zeros. */ 3204 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 3205 /* enum: RAM test - walking inversions zeros/ones. */ 3206 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 3207 /* enum: RAM test - walking inversions checkerboard. */ 3208 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 3209 /* enum: Register test - set / clear individual bits. */ 3210 #define MC_CMD_POLL_BIST_MEM_REG 0x5 3211 /* enum: ECC error detected. */ 3212 #define MC_CMD_POLL_BIST_MEM_ECC 0x6 3213 /* Failure address, only valid if result is POLL_BIST_FAILED */ 3214 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 3215 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4 3216 /* Bus or address space to which the failure address corresponds */ 3217 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 3218 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4 3219 /* enum: MC MIPS bus. */ 3220 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 3221 /* enum: CSR IREG bus. */ 3222 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 3223 /* enum: RX0 DPCPU bus. */ 3224 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 3225 /* enum: TX0 DPCPU bus. */ 3226 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 3227 /* enum: TX1 DPCPU bus. */ 3228 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 3229 /* enum: RX0 DICPU bus. */ 3230 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 3231 /* enum: TX DICPU bus. */ 3232 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 3233 /* enum: RX1 DPCPU bus. */ 3234 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7 3235 /* enum: RX1 DICPU bus. */ 3236 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8 3237 /* Pattern written to RAM / register */ 3238 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 3239 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4 3240 /* Actual value read from RAM / register */ 3241 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 3242 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4 3243 /* ECC error mask */ 3244 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 3245 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4 3246 /* ECC parity error mask */ 3247 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 3248 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4 3249 /* ECC fatal error mask */ 3250 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 3251 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4 3252 3253 3254 /***********************************/ 3255 /* MC_CMD_FLUSH_RX_QUEUES 3256 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ 3257 * flushes should be initiated via this MCDI operation, rather than via 3258 * directly writing FLUSH_CMD. 3259 * 3260 * The flush is completed (either done/fail) asynchronously (after this command 3261 * returns). The driver must still wait for flush done/failure events as usual. 3262 */ 3263 #define MC_CMD_FLUSH_RX_QUEUES 0x27 3264 3265 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 3266 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 3267 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 3268 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 3269 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 3270 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 3271 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 3272 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 3273 3274 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 3275 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 3276 3277 3278 /***********************************/ 3279 /* MC_CMD_GET_LOOPBACK_MODES 3280 * Returns a bitmask of loopback modes available at each speed. 3281 */ 3282 #define MC_CMD_GET_LOOPBACK_MODES 0x28 3283 3284 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3285 3286 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 3287 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 3288 3289 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 3290 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 3291 /* Supported loopbacks. */ 3292 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 3293 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 3294 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 3295 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 3296 /* enum: None. */ 3297 #define MC_CMD_LOOPBACK_NONE 0x0 3298 /* enum: Data. */ 3299 #define MC_CMD_LOOPBACK_DATA 0x1 3300 /* enum: GMAC. */ 3301 #define MC_CMD_LOOPBACK_GMAC 0x2 3302 /* enum: XGMII. */ 3303 #define MC_CMD_LOOPBACK_XGMII 0x3 3304 /* enum: XGXS. */ 3305 #define MC_CMD_LOOPBACK_XGXS 0x4 3306 /* enum: XAUI. */ 3307 #define MC_CMD_LOOPBACK_XAUI 0x5 3308 /* enum: GMII. */ 3309 #define MC_CMD_LOOPBACK_GMII 0x6 3310 /* enum: SGMII. */ 3311 #define MC_CMD_LOOPBACK_SGMII 0x7 3312 /* enum: XGBR. */ 3313 #define MC_CMD_LOOPBACK_XGBR 0x8 3314 /* enum: XFI. */ 3315 #define MC_CMD_LOOPBACK_XFI 0x9 3316 /* enum: XAUI Far. */ 3317 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa 3318 /* enum: GMII Far. */ 3319 #define MC_CMD_LOOPBACK_GMII_FAR 0xb 3320 /* enum: SGMII Far. */ 3321 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc 3322 /* enum: XFI Far. */ 3323 #define MC_CMD_LOOPBACK_XFI_FAR 0xd 3324 /* enum: GPhy. */ 3325 #define MC_CMD_LOOPBACK_GPHY 0xe 3326 /* enum: PhyXS. */ 3327 #define MC_CMD_LOOPBACK_PHYXS 0xf 3328 /* enum: PCS. */ 3329 #define MC_CMD_LOOPBACK_PCS 0x10 3330 /* enum: PMA-PMD. */ 3331 #define MC_CMD_LOOPBACK_PMAPMD 0x11 3332 /* enum: Cross-Port. */ 3333 #define MC_CMD_LOOPBACK_XPORT 0x12 3334 /* enum: XGMII-Wireside. */ 3335 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 3336 /* enum: XAUI Wireside. */ 3337 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 3338 /* enum: XAUI Wireside Far. */ 3339 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 3340 /* enum: XAUI Wireside near. */ 3341 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 3342 /* enum: GMII Wireside. */ 3343 #define MC_CMD_LOOPBACK_GMII_WS 0x17 3344 /* enum: XFI Wireside. */ 3345 #define MC_CMD_LOOPBACK_XFI_WS 0x18 3346 /* enum: XFI Wireside Far. */ 3347 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 3348 /* enum: PhyXS Wireside. */ 3349 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a 3350 /* enum: PMA lanes MAC-Serdes. */ 3351 #define MC_CMD_LOOPBACK_PMA_INT 0x1b 3352 /* enum: KR Serdes Parallel (Encoder). */ 3353 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c 3354 /* enum: KR Serdes Serial. */ 3355 #define MC_CMD_LOOPBACK_SD_FAR 0x1d 3356 /* enum: PMA lanes MAC-Serdes Wireside. */ 3357 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e 3358 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 3359 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f 3360 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 3361 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 3362 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 3363 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 3364 /* enum: KR Serdes Serial Wireside. */ 3365 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 3366 /* enum: Near side of AOE Siena side port */ 3367 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 3368 /* enum: Medford Wireside datapath loopback */ 3369 #define MC_CMD_LOOPBACK_DATA_WS 0x24 3370 /* enum: Force link up without setting up any physical loopback (snapper use 3371 * only) 3372 */ 3373 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 3374 /* Supported loopbacks. */ 3375 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 3376 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 3377 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 3378 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 3379 /* Enum values, see field(s): */ 3380 /* 100M */ 3381 /* Supported loopbacks. */ 3382 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 3383 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 3384 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 3385 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 3386 /* Enum values, see field(s): */ 3387 /* 100M */ 3388 /* Supported loopbacks. */ 3389 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 3390 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 3391 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 3392 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 3393 /* Enum values, see field(s): */ 3394 /* 100M */ 3395 /* Supported loopbacks. */ 3396 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 3397 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 3398 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 3399 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 3400 /* Enum values, see field(s): */ 3401 /* 100M */ 3402 3403 /* MC_CMD_GET_LOOPBACK_MODES_OUT_V2 msgresponse: Supported loopback modes for 3404 * newer NICs with 25G/50G/100G support 3405 */ 3406 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN 64 3407 /* Supported loopbacks. */ 3408 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0 3409 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8 3410 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0 3411 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4 3412 /* enum: None. */ 3413 /* MC_CMD_LOOPBACK_NONE 0x0 */ 3414 /* enum: Data. */ 3415 /* MC_CMD_LOOPBACK_DATA 0x1 */ 3416 /* enum: GMAC. */ 3417 /* MC_CMD_LOOPBACK_GMAC 0x2 */ 3418 /* enum: XGMII. */ 3419 /* MC_CMD_LOOPBACK_XGMII 0x3 */ 3420 /* enum: XGXS. */ 3421 /* MC_CMD_LOOPBACK_XGXS 0x4 */ 3422 /* enum: XAUI. */ 3423 /* MC_CMD_LOOPBACK_XAUI 0x5 */ 3424 /* enum: GMII. */ 3425 /* MC_CMD_LOOPBACK_GMII 0x6 */ 3426 /* enum: SGMII. */ 3427 /* MC_CMD_LOOPBACK_SGMII 0x7 */ 3428 /* enum: XGBR. */ 3429 /* MC_CMD_LOOPBACK_XGBR 0x8 */ 3430 /* enum: XFI. */ 3431 /* MC_CMD_LOOPBACK_XFI 0x9 */ 3432 /* enum: XAUI Far. */ 3433 /* MC_CMD_LOOPBACK_XAUI_FAR 0xa */ 3434 /* enum: GMII Far. */ 3435 /* MC_CMD_LOOPBACK_GMII_FAR 0xb */ 3436 /* enum: SGMII Far. */ 3437 /* MC_CMD_LOOPBACK_SGMII_FAR 0xc */ 3438 /* enum: XFI Far. */ 3439 /* MC_CMD_LOOPBACK_XFI_FAR 0xd */ 3440 /* enum: GPhy. */ 3441 /* MC_CMD_LOOPBACK_GPHY 0xe */ 3442 /* enum: PhyXS. */ 3443 /* MC_CMD_LOOPBACK_PHYXS 0xf */ 3444 /* enum: PCS. */ 3445 /* MC_CMD_LOOPBACK_PCS 0x10 */ 3446 /* enum: PMA-PMD. */ 3447 /* MC_CMD_LOOPBACK_PMAPMD 0x11 */ 3448 /* enum: Cross-Port. */ 3449 /* MC_CMD_LOOPBACK_XPORT 0x12 */ 3450 /* enum: XGMII-Wireside. */ 3451 /* MC_CMD_LOOPBACK_XGMII_WS 0x13 */ 3452 /* enum: XAUI Wireside. */ 3453 /* MC_CMD_LOOPBACK_XAUI_WS 0x14 */ 3454 /* enum: XAUI Wireside Far. */ 3455 /* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */ 3456 /* enum: XAUI Wireside near. */ 3457 /* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */ 3458 /* enum: GMII Wireside. */ 3459 /* MC_CMD_LOOPBACK_GMII_WS 0x17 */ 3460 /* enum: XFI Wireside. */ 3461 /* MC_CMD_LOOPBACK_XFI_WS 0x18 */ 3462 /* enum: XFI Wireside Far. */ 3463 /* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */ 3464 /* enum: PhyXS Wireside. */ 3465 /* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */ 3466 /* enum: PMA lanes MAC-Serdes. */ 3467 /* MC_CMD_LOOPBACK_PMA_INT 0x1b */ 3468 /* enum: KR Serdes Parallel (Encoder). */ 3469 /* MC_CMD_LOOPBACK_SD_NEAR 0x1c */ 3470 /* enum: KR Serdes Serial. */ 3471 /* MC_CMD_LOOPBACK_SD_FAR 0x1d */ 3472 /* enum: PMA lanes MAC-Serdes Wireside. */ 3473 /* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */ 3474 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 3475 /* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */ 3476 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 3477 /* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */ 3478 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 3479 /* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */ 3480 /* enum: KR Serdes Serial Wireside. */ 3481 /* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */ 3482 /* enum: Near side of AOE Siena side port */ 3483 /* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */ 3484 /* enum: Medford Wireside datapath loopback */ 3485 /* MC_CMD_LOOPBACK_DATA_WS 0x24 */ 3486 /* enum: Force link up without setting up any physical loopback (snapper use 3487 * only) 3488 */ 3489 /* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */ 3490 /* Supported loopbacks. */ 3491 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8 3492 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8 3493 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8 3494 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12 3495 /* Enum values, see field(s): */ 3496 /* 100M */ 3497 /* Supported loopbacks. */ 3498 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16 3499 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8 3500 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16 3501 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20 3502 /* Enum values, see field(s): */ 3503 /* 100M */ 3504 /* Supported loopbacks. */ 3505 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24 3506 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8 3507 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24 3508 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28 3509 /* Enum values, see field(s): */ 3510 /* 100M */ 3511 /* Supported loopbacks. */ 3512 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32 3513 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8 3514 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32 3515 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36 3516 /* Enum values, see field(s): */ 3517 /* 100M */ 3518 /* Supported 25G loopbacks. */ 3519 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40 3520 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8 3521 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40 3522 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44 3523 /* Enum values, see field(s): */ 3524 /* 100M */ 3525 /* Supported 50 loopbacks. */ 3526 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48 3527 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8 3528 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48 3529 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52 3530 /* Enum values, see field(s): */ 3531 /* 100M */ 3532 /* Supported 100G loopbacks. */ 3533 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56 3534 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8 3535 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56 3536 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60 3537 /* Enum values, see field(s): */ 3538 /* 100M */ 3539 3540 3541 /***********************************/ 3542 /* MC_CMD_GET_LINK 3543 * Read the unified MAC/PHY link state. Locks required: None Return code: 0, 3544 * ETIME. 3545 */ 3546 #define MC_CMD_GET_LINK 0x29 3547 3548 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3549 3550 /* MC_CMD_GET_LINK_IN msgrequest */ 3551 #define MC_CMD_GET_LINK_IN_LEN 0 3552 3553 /* MC_CMD_GET_LINK_OUT msgresponse */ 3554 #define MC_CMD_GET_LINK_OUT_LEN 28 3555 /* near-side advertised capabilities */ 3556 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 3557 #define MC_CMD_GET_LINK_OUT_CAP_LEN 4 3558 /* link-partner advertised capabilities */ 3559 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 3560 #define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4 3561 /* Autonegotiated speed in mbit/s. The link may still be down even if this 3562 * reads non-zero. 3563 */ 3564 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 3565 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4 3566 /* Current loopback setting. */ 3567 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 3568 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4 3569 /* Enum values, see field(s): */ 3570 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 3571 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 3572 #define MC_CMD_GET_LINK_OUT_FLAGS_LEN 4 3573 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 3574 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 3575 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 3576 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 3577 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 3578 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 3579 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 3580 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 3581 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 3582 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 3583 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 3584 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 3585 /* This returns the negotiated flow control value. */ 3586 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 3587 #define MC_CMD_GET_LINK_OUT_FCNTL_LEN 4 3588 /* Enum values, see field(s): */ 3589 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 3590 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 3591 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4 3592 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 3593 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 3594 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 3595 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 3596 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 3597 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 3598 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 3599 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 3600 3601 3602 /***********************************/ 3603 /* MC_CMD_SET_LINK 3604 * Write the unified MAC/PHY link configuration. Locks required: None. Return 3605 * code: 0, EINVAL, ETIME 3606 */ 3607 #define MC_CMD_SET_LINK 0x2a 3608 3609 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK 3610 3611 /* MC_CMD_SET_LINK_IN msgrequest */ 3612 #define MC_CMD_SET_LINK_IN_LEN 16 3613 /* ??? */ 3614 #define MC_CMD_SET_LINK_IN_CAP_OFST 0 3615 #define MC_CMD_SET_LINK_IN_CAP_LEN 4 3616 /* Flags */ 3617 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 3618 #define MC_CMD_SET_LINK_IN_FLAGS_LEN 4 3619 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 3620 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 3621 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 3622 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 3623 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 3624 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 3625 /* Loopback mode. */ 3626 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 3627 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4 3628 /* Enum values, see field(s): */ 3629 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 3630 /* A loopback speed of "0" is supported, and means (choose any available 3631 * speed). 3632 */ 3633 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 3634 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4 3635 3636 /* MC_CMD_SET_LINK_OUT msgresponse */ 3637 #define MC_CMD_SET_LINK_OUT_LEN 0 3638 3639 3640 /***********************************/ 3641 /* MC_CMD_SET_ID_LED 3642 * Set identification LED state. Locks required: None. Return code: 0, EINVAL 3643 */ 3644 #define MC_CMD_SET_ID_LED 0x2b 3645 3646 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK 3647 3648 /* MC_CMD_SET_ID_LED_IN msgrequest */ 3649 #define MC_CMD_SET_ID_LED_IN_LEN 4 3650 /* Set LED state. */ 3651 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 3652 #define MC_CMD_SET_ID_LED_IN_STATE_LEN 4 3653 #define MC_CMD_LED_OFF 0x0 /* enum */ 3654 #define MC_CMD_LED_ON 0x1 /* enum */ 3655 #define MC_CMD_LED_DEFAULT 0x2 /* enum */ 3656 3657 /* MC_CMD_SET_ID_LED_OUT msgresponse */ 3658 #define MC_CMD_SET_ID_LED_OUT_LEN 0 3659 3660 3661 /***********************************/ 3662 /* MC_CMD_SET_MAC 3663 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL 3664 */ 3665 #define MC_CMD_SET_MAC 0x2c 3666 3667 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3668 3669 /* MC_CMD_SET_MAC_IN msgrequest */ 3670 #define MC_CMD_SET_MAC_IN_LEN 28 3671 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 3672 * EtherII, VLAN, bug16011 padding). 3673 */ 3674 #define MC_CMD_SET_MAC_IN_MTU_OFST 0 3675 #define MC_CMD_SET_MAC_IN_MTU_LEN 4 3676 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 3677 #define MC_CMD_SET_MAC_IN_DRAIN_LEN 4 3678 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 3679 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 3680 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 3681 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 3682 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 3683 #define MC_CMD_SET_MAC_IN_REJECT_LEN 4 3684 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 3685 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 3686 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 3687 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 3688 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 3689 #define MC_CMD_SET_MAC_IN_FCNTL_LEN 4 3690 /* enum: Flow control is off. */ 3691 #define MC_CMD_FCNTL_OFF 0x0 3692 /* enum: Respond to flow control. */ 3693 #define MC_CMD_FCNTL_RESPOND 0x1 3694 /* enum: Respond to and Issue flow control. */ 3695 #define MC_CMD_FCNTL_BIDIR 0x2 3696 /* enum: Auto neg flow control. */ 3697 #define MC_CMD_FCNTL_AUTO 0x3 3698 /* enum: Priority flow control (eftest builds only). */ 3699 #define MC_CMD_FCNTL_QBB 0x4 3700 /* enum: Issue flow control. */ 3701 #define MC_CMD_FCNTL_GENERATE 0x5 3702 #define MC_CMD_SET_MAC_IN_FLAGS_OFST 24 3703 #define MC_CMD_SET_MAC_IN_FLAGS_LEN 4 3704 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0 3705 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1 3706 3707 /* MC_CMD_SET_MAC_EXT_IN msgrequest */ 3708 #define MC_CMD_SET_MAC_EXT_IN_LEN 32 3709 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 3710 * EtherII, VLAN, bug16011 padding). 3711 */ 3712 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0 3713 #define MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4 3714 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4 3715 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4 3716 #define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8 3717 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8 3718 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8 3719 #define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12 3720 #define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16 3721 #define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4 3722 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0 3723 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1 3724 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1 3725 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1 3726 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20 3727 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4 3728 /* enum: Flow control is off. */ 3729 /* MC_CMD_FCNTL_OFF 0x0 */ 3730 /* enum: Respond to flow control. */ 3731 /* MC_CMD_FCNTL_RESPOND 0x1 */ 3732 /* enum: Respond to and Issue flow control. */ 3733 /* MC_CMD_FCNTL_BIDIR 0x2 */ 3734 /* enum: Auto neg flow control. */ 3735 /* MC_CMD_FCNTL_AUTO 0x3 */ 3736 /* enum: Priority flow control (eftest builds only). */ 3737 /* MC_CMD_FCNTL_QBB 0x4 */ 3738 /* enum: Issue flow control. */ 3739 /* MC_CMD_FCNTL_GENERATE 0x5 */ 3740 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24 3741 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4 3742 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0 3743 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1 3744 /* Select which parameters to configure. A parameter will only be modified if 3745 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in 3746 * capabilities then this field is ignored (and all flags are assumed to be 3747 * set). 3748 */ 3749 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28 3750 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4 3751 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0 3752 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1 3753 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1 3754 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1 3755 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2 3756 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1 3757 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3 3758 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1 3759 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4 3760 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1 3761 3762 /* MC_CMD_SET_MAC_OUT msgresponse */ 3763 #define MC_CMD_SET_MAC_OUT_LEN 0 3764 3765 /* MC_CMD_SET_MAC_V2_OUT msgresponse */ 3766 #define MC_CMD_SET_MAC_V2_OUT_LEN 4 3767 /* MTU as configured after processing the request. See comment at 3768 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL 3769 * to 0. 3770 */ 3771 #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0 3772 #define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4 3773 3774 3775 /***********************************/ 3776 /* MC_CMD_PHY_STATS 3777 * Get generic PHY statistics. This call returns the statistics for a generic 3778 * PHY in a sparse array (indexed by the enumerate). Each value is represented 3779 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the 3780 * statistics may be read from the message response. If DMA_ADDR != 0, then the 3781 * statistics are dmad to that (page-aligned location). Locks required: None. 3782 * Returns: 0, ETIME 3783 */ 3784 #define MC_CMD_PHY_STATS 0x2d 3785 3786 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK 3787 3788 /* MC_CMD_PHY_STATS_IN msgrequest */ 3789 #define MC_CMD_PHY_STATS_IN_LEN 8 3790 /* ??? */ 3791 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 3792 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 3793 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 3794 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 3795 3796 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 3797 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 3798 3799 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 3800 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 3801 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 3802 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 3803 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 3804 /* enum: OUI. */ 3805 #define MC_CMD_OUI 0x0 3806 /* enum: PMA-PMD Link Up. */ 3807 #define MC_CMD_PMA_PMD_LINK_UP 0x1 3808 /* enum: PMA-PMD RX Fault. */ 3809 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 3810 /* enum: PMA-PMD TX Fault. */ 3811 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 3812 /* enum: PMA-PMD Signal */ 3813 #define MC_CMD_PMA_PMD_SIGNAL 0x4 3814 /* enum: PMA-PMD SNR A. */ 3815 #define MC_CMD_PMA_PMD_SNR_A 0x5 3816 /* enum: PMA-PMD SNR B. */ 3817 #define MC_CMD_PMA_PMD_SNR_B 0x6 3818 /* enum: PMA-PMD SNR C. */ 3819 #define MC_CMD_PMA_PMD_SNR_C 0x7 3820 /* enum: PMA-PMD SNR D. */ 3821 #define MC_CMD_PMA_PMD_SNR_D 0x8 3822 /* enum: PCS Link Up. */ 3823 #define MC_CMD_PCS_LINK_UP 0x9 3824 /* enum: PCS RX Fault. */ 3825 #define MC_CMD_PCS_RX_FAULT 0xa 3826 /* enum: PCS TX Fault. */ 3827 #define MC_CMD_PCS_TX_FAULT 0xb 3828 /* enum: PCS BER. */ 3829 #define MC_CMD_PCS_BER 0xc 3830 /* enum: PCS Block Errors. */ 3831 #define MC_CMD_PCS_BLOCK_ERRORS 0xd 3832 /* enum: PhyXS Link Up. */ 3833 #define MC_CMD_PHYXS_LINK_UP 0xe 3834 /* enum: PhyXS RX Fault. */ 3835 #define MC_CMD_PHYXS_RX_FAULT 0xf 3836 /* enum: PhyXS TX Fault. */ 3837 #define MC_CMD_PHYXS_TX_FAULT 0x10 3838 /* enum: PhyXS Align. */ 3839 #define MC_CMD_PHYXS_ALIGN 0x11 3840 /* enum: PhyXS Sync. */ 3841 #define MC_CMD_PHYXS_SYNC 0x12 3842 /* enum: AN link-up. */ 3843 #define MC_CMD_AN_LINK_UP 0x13 3844 /* enum: AN Complete. */ 3845 #define MC_CMD_AN_COMPLETE 0x14 3846 /* enum: AN 10GBaseT Status. */ 3847 #define MC_CMD_AN_10GBT_STATUS 0x15 3848 /* enum: Clause 22 Link-Up. */ 3849 #define MC_CMD_CL22_LINK_UP 0x16 3850 /* enum: (Last entry) */ 3851 #define MC_CMD_PHY_NSTATS 0x17 3852 3853 3854 /***********************************/ 3855 /* MC_CMD_MAC_STATS 3856 * Get generic MAC statistics. This call returns unified statistics maintained 3857 * by the MC as it switches between the GMAC and XMAC. The MC will write out 3858 * all supported stats. The driver should zero initialise the buffer to 3859 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is 3860 * performed, and the statistics may be read from the message response. If 3861 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). 3862 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no 3863 * effect. Returns: 0, ETIME 3864 */ 3865 #define MC_CMD_MAC_STATS 0x2e 3866 3867 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3868 3869 /* MC_CMD_MAC_STATS_IN msgrequest */ 3870 #define MC_CMD_MAC_STATS_IN_LEN 20 3871 /* ??? */ 3872 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 3873 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 3874 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 3875 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 3876 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 3877 #define MC_CMD_MAC_STATS_IN_CMD_LEN 4 3878 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 3879 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 3880 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 3881 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 3882 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 3883 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 3884 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 3885 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 3886 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 3887 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 3888 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 3889 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 3890 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 3891 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 3892 /* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as 3893 * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not 3894 * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to 3895 * MC_CMD_MAC_NSTATS * sizeof(uint64_t) 3896 */ 3897 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 3898 #define MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4 3899 /* port id so vadapter stats can be provided */ 3900 #define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16 3901 #define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4 3902 3903 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 3904 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 3905 3906 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 3907 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 3908 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 3909 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 3910 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 3911 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 3912 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 3913 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 3914 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */ 3915 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 3916 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 3917 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 3918 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 3919 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 3920 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 3921 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 3922 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 3923 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 3924 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 3925 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 3926 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 3927 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 3928 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 3929 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 3930 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 3931 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 3932 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 3933 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 3934 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 3935 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 3936 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 3937 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 3938 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 3939 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 3940 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 3941 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 3942 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 3943 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 3944 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 3945 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 3946 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 3947 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 3948 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 3949 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 3950 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 3951 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 3952 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 3953 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 3954 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 3955 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 3956 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 3957 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 3958 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 3959 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 3960 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 3961 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 3962 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 3963 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 3964 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 3965 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 3966 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 3967 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 3968 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 3969 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 3970 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 3971 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 3972 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 3973 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 3974 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3975 * capability only. 3976 */ 3977 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c 3978 /* enum: PM discard_bb_overflow counter. Valid for EF10 with 3979 * PM_AND_RXDP_COUNTERS capability only. 3980 */ 3981 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d 3982 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3983 * capability only. 3984 */ 3985 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e 3986 /* enum: PM discard_vfifo_full counter. Valid for EF10 with 3987 * PM_AND_RXDP_COUNTERS capability only. 3988 */ 3989 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f 3990 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3991 * capability only. 3992 */ 3993 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40 3994 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3995 * capability only. 3996 */ 3997 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41 3998 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3999 * capability only. 4000 */ 4001 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 4002 /* enum: RXDP counter: Number of packets dropped due to the queue being 4003 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 4004 */ 4005 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 4006 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 4007 * with PM_AND_RXDP_COUNTERS capability only. 4008 */ 4009 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 4010 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with 4011 * PM_AND_RXDP_COUNTERS capability only. 4012 */ 4013 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 4014 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed. 4015 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 4016 */ 4017 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47 4018 /* enum: RXDP counter: Number of times the DPCPU waited for an existing 4019 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 4020 */ 4021 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48 4022 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */ 4023 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */ 4024 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */ 4025 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */ 4026 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */ 4027 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */ 4028 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */ 4029 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */ 4030 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */ 4031 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */ 4032 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */ 4033 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */ 4034 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */ 4035 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */ 4036 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */ 4037 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */ 4038 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */ 4039 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */ 4040 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */ 4041 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */ 4042 /* enum: Start of GMAC stats buffer space, for Siena only. */ 4043 #define MC_CMD_GMAC_DMABUF_START 0x40 4044 /* enum: End of GMAC stats buffer space, for Siena only. */ 4045 #define MC_CMD_GMAC_DMABUF_END 0x5f 4046 /* enum: GENERATION_END value, used together with GENERATION_START to verify 4047 * consistency of DMAd data. For legacy firmware / drivers without extended 4048 * stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS * 4049 * sizeof(uint64_t)), this entry holds the GENERATION_END value. Otherwise, 4050 * this value is invalid/ reserved and GENERATION_END is written as the last 4051 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that 4052 * this is consistent with the legacy behaviour, in the sense that entry 96 is 4053 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS * 4054 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details. 4055 */ 4056 #define MC_CMD_MAC_GENERATION_END 0x60 4057 #define MC_CMD_MAC_NSTATS 0x61 /* enum */ 4058 4059 /* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */ 4060 #define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0 4061 4062 /* MC_CMD_MAC_STATS_V2_OUT_NO_DMA msgresponse */ 4063 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V2*64))>>3) 4064 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0 4065 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8 4066 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0 4067 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4 4068 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2 4069 /* enum: Start of FEC stats buffer space, Medford2 and up */ 4070 #define MC_CMD_MAC_FEC_DMABUF_START 0x61 4071 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2) 4072 */ 4073 #define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61 4074 /* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2) 4075 */ 4076 #define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62 4077 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */ 4078 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63 4079 /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */ 4080 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64 4081 /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */ 4082 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65 4083 /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */ 4084 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66 4085 /* enum: This includes the space at offset 103 which is the final 4086 * GENERATION_END in a MAC_STATS_V2 response and otherwise unused. 4087 */ 4088 #define MC_CMD_MAC_NSTATS_V2 0x68 4089 /* Other enum values, see field(s): */ 4090 /* MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */ 4091 4092 /* MC_CMD_MAC_STATS_V3_OUT_DMA msgresponse */ 4093 #define MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 0 4094 4095 /* MC_CMD_MAC_STATS_V3_OUT_NO_DMA msgresponse */ 4096 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V3*64))>>3) 4097 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0 4098 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 8 4099 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0 4100 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4 4101 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3 4102 /* enum: Start of CTPIO stats buffer space, Medford2 and up */ 4103 #define MC_CMD_MAC_CTPIO_DMABUF_START 0x68 4104 /* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the 4105 * target VI 4106 */ 4107 #define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68 4108 /* enum: Number of times a CTPIO send wrote beyond frame end (informational 4109 * only) 4110 */ 4111 #define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69 4112 /* enum: Number of CTPIO failures because the TX doorbell was written before 4113 * the end of the frame data 4114 */ 4115 #define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a 4116 /* enum: Number of CTPIO failures because the internal FIFO overflowed */ 4117 #define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b 4118 /* enum: Number of CTPIO failures because the host did not deliver data fast 4119 * enough to avoid MAC underflow 4120 */ 4121 #define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c 4122 /* enum: Number of CTPIO failures because the host did not deliver all the 4123 * frame data within the timeout 4124 */ 4125 #define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d 4126 /* enum: Number of CTPIO failures because the frame data arrived out of order 4127 * or with gaps 4128 */ 4129 #define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e 4130 /* enum: Number of CTPIO failures because the host started a new frame before 4131 * completing the previous one 4132 */ 4133 #define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f 4134 /* enum: Number of CTPIO failures because a write was not a multiple of 32 bits 4135 * or not 32-bit aligned 4136 */ 4137 #define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70 4138 /* enum: Number of CTPIO fallbacks because another VI on the same port was 4139 * sending a CTPIO frame 4140 */ 4141 #define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71 4142 /* enum: Number of CTPIO fallbacks because target VI did not have CTPIO enabled 4143 */ 4144 #define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72 4145 /* enum: Number of CTPIO fallbacks because length in header was less than 29 4146 * bytes 4147 */ 4148 #define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73 4149 /* enum: Total number of successful CTPIO sends on this port */ 4150 #define MC_CMD_MAC_CTPIO_SUCCESS 0x74 4151 /* enum: Total number of CTPIO fallbacks on this port */ 4152 #define MC_CMD_MAC_CTPIO_FALLBACK 0x75 4153 /* enum: Total number of CTPIO poisoned frames on this port, whether erased or 4154 * not 4155 */ 4156 #define MC_CMD_MAC_CTPIO_POISON 0x76 4157 /* enum: Total number of CTPIO erased frames on this port */ 4158 #define MC_CMD_MAC_CTPIO_ERASE 0x77 4159 /* enum: This includes the space at offset 120 which is the final 4160 * GENERATION_END in a MAC_STATS_V3 response and otherwise unused. 4161 */ 4162 #define MC_CMD_MAC_NSTATS_V3 0x79 4163 /* Other enum values, see field(s): */ 4164 /* MC_CMD_MAC_STATS_V2_OUT_NO_DMA/STATISTICS */ 4165 4166 4167 /***********************************/ 4168 /* MC_CMD_SRIOV 4169 * to be documented 4170 */ 4171 #define MC_CMD_SRIOV 0x30 4172 4173 /* MC_CMD_SRIOV_IN msgrequest */ 4174 #define MC_CMD_SRIOV_IN_LEN 12 4175 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 4176 #define MC_CMD_SRIOV_IN_ENABLE_LEN 4 4177 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 4178 #define MC_CMD_SRIOV_IN_VI_BASE_LEN 4 4179 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 4180 #define MC_CMD_SRIOV_IN_VF_COUNT_LEN 4 4181 4182 /* MC_CMD_SRIOV_OUT msgresponse */ 4183 #define MC_CMD_SRIOV_OUT_LEN 8 4184 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 4185 #define MC_CMD_SRIOV_OUT_VI_SCALE_LEN 4 4186 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 4187 #define MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4 4188 4189 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 4190 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 4191 /* this is only used for the first record */ 4192 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 4193 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4 4194 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 4195 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 4196 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 4197 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4 4198 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 4199 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 4200 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 4201 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 4202 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 4203 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 4204 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 4205 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 4206 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 4207 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4 4208 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 4209 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 4210 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 4211 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 4212 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 4213 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 4214 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 4215 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 4216 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 4217 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 4218 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4 4219 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 4220 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 4221 4222 4223 /***********************************/ 4224 /* MC_CMD_MEMCPY 4225 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data 4226 * embedded directly in the command. 4227 * 4228 * A common pattern is for a client to use generation counts to signal a dma 4229 * update of a datastructure. To facilitate this, this MCDI operation can 4230 * contain multiple requests which are executed in strict order. Requests take 4231 * the form of duplicating the entire MCDI request continuously (including the 4232 * requests record, which is ignored in all but the first structure) 4233 * 4234 * The source data can either come from a DMA from the host, or it can be 4235 * embedded within the request directly, thereby eliminating a DMA read. To 4236 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and 4237 * ADDR_LO=offset, and inserts the data at %offset from the start of the 4238 * payload. It's the callers responsibility to ensure that the embedded data 4239 * doesn't overlap the records. 4240 * 4241 * Returns: 0, EINVAL (invalid RID) 4242 */ 4243 #define MC_CMD_MEMCPY 0x31 4244 4245 /* MC_CMD_MEMCPY_IN msgrequest */ 4246 #define MC_CMD_MEMCPY_IN_LENMIN 32 4247 #define MC_CMD_MEMCPY_IN_LENMAX 224 4248 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 4249 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ 4250 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 4251 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 4252 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 4253 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 4254 4255 /* MC_CMD_MEMCPY_OUT msgresponse */ 4256 #define MC_CMD_MEMCPY_OUT_LEN 0 4257 4258 4259 /***********************************/ 4260 /* MC_CMD_WOL_FILTER_SET 4261 * Set a WoL filter. 4262 */ 4263 #define MC_CMD_WOL_FILTER_SET 0x32 4264 4265 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK 4266 4267 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 4268 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 4269 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 4270 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 4271 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 4272 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 4273 /* A type value of 1 is unused. */ 4274 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 4275 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 4276 /* enum: Magic */ 4277 #define MC_CMD_WOL_TYPE_MAGIC 0x0 4278 /* enum: MS Windows Magic */ 4279 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 4280 /* enum: IPv4 Syn */ 4281 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 4282 /* enum: IPv6 Syn */ 4283 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 4284 /* enum: Bitmap */ 4285 #define MC_CMD_WOL_TYPE_BITMAP 0x5 4286 /* enum: Link */ 4287 #define MC_CMD_WOL_TYPE_LINK 0x6 4288 /* enum: (Above this for future use) */ 4289 #define MC_CMD_WOL_TYPE_MAX 0x7 4290 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 4291 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 4292 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 4293 4294 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 4295 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 4296 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4297 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4298 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4299 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4300 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 4301 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 4302 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 4303 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 4304 4305 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 4306 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 4307 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4308 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4309 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4310 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4311 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 4312 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4 4313 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 4314 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4 4315 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 4316 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 4317 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 4318 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 4319 4320 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 4321 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 4322 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4323 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4324 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4325 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4326 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 4327 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 4328 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 4329 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 4330 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 4331 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 4332 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 4333 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 4334 4335 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 4336 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 4337 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4338 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4339 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4340 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4341 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 4342 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 4343 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 4344 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 4345 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 4346 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 4347 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 4348 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 4349 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 4350 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 4351 4352 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 4353 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 4354 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4355 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4356 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4357 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4358 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 4359 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4 4360 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 4361 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 4362 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 4363 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 4364 4365 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 4366 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 4367 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 4368 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4 4369 4370 4371 /***********************************/ 4372 /* MC_CMD_WOL_FILTER_REMOVE 4373 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS 4374 */ 4375 #define MC_CMD_WOL_FILTER_REMOVE 0x33 4376 4377 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK 4378 4379 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 4380 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 4381 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 4382 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4 4383 4384 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 4385 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 4386 4387 4388 /***********************************/ 4389 /* MC_CMD_WOL_FILTER_RESET 4390 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, 4391 * ENOSYS 4392 */ 4393 #define MC_CMD_WOL_FILTER_RESET 0x34 4394 4395 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK 4396 4397 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 4398 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 4399 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 4400 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4 4401 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 4402 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 4403 4404 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 4405 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 4406 4407 4408 /***********************************/ 4409 /* MC_CMD_SET_MCAST_HASH 4410 * Set the MCAST hash value without otherwise reconfiguring the MAC 4411 */ 4412 #define MC_CMD_SET_MCAST_HASH 0x35 4413 4414 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 4415 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 4416 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 4417 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 4418 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 4419 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 4420 4421 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 4422 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 4423 4424 4425 /***********************************/ 4426 /* MC_CMD_NVRAM_TYPES 4427 * Return bitfield indicating available types of virtual NVRAM partitions. 4428 * Locks required: none. Returns: 0 4429 */ 4430 #define MC_CMD_NVRAM_TYPES 0x36 4431 4432 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4433 4434 /* MC_CMD_NVRAM_TYPES_IN msgrequest */ 4435 #define MC_CMD_NVRAM_TYPES_IN_LEN 0 4436 4437 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 4438 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 4439 /* Bit mask of supported types. */ 4440 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 4441 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4 4442 /* enum: Disabled callisto. */ 4443 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 4444 /* enum: MC firmware. */ 4445 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 4446 /* enum: MC backup firmware. */ 4447 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 4448 /* enum: Static configuration Port0. */ 4449 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 4450 /* enum: Static configuration Port1. */ 4451 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 4452 /* enum: Dynamic configuration Port0. */ 4453 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 4454 /* enum: Dynamic configuration Port1. */ 4455 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 4456 /* enum: Expansion Rom. */ 4457 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 4458 /* enum: Expansion Rom Configuration Port0. */ 4459 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 4460 /* enum: Expansion Rom Configuration Port1. */ 4461 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 4462 /* enum: Phy Configuration Port0. */ 4463 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa 4464 /* enum: Phy Configuration Port1. */ 4465 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb 4466 /* enum: Log. */ 4467 #define MC_CMD_NVRAM_TYPE_LOG 0xc 4468 /* enum: FPGA image. */ 4469 #define MC_CMD_NVRAM_TYPE_FPGA 0xd 4470 /* enum: FPGA backup image */ 4471 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe 4472 /* enum: FC firmware. */ 4473 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf 4474 /* enum: FC backup firmware. */ 4475 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 4476 /* enum: CPLD image. */ 4477 #define MC_CMD_NVRAM_TYPE_CPLD 0x11 4478 /* enum: Licensing information. */ 4479 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 4480 /* enum: FC Log. */ 4481 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 4482 /* enum: Additional flash on FPGA. */ 4483 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 4484 4485 4486 /***********************************/ 4487 /* MC_CMD_NVRAM_INFO 4488 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, 4489 * EINVAL (bad type). 4490 */ 4491 #define MC_CMD_NVRAM_INFO 0x37 4492 4493 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4494 4495 /* MC_CMD_NVRAM_INFO_IN msgrequest */ 4496 #define MC_CMD_NVRAM_INFO_IN_LEN 4 4497 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 4498 #define MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4 4499 /* Enum values, see field(s): */ 4500 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4501 4502 /* MC_CMD_NVRAM_INFO_OUT msgresponse */ 4503 #define MC_CMD_NVRAM_INFO_OUT_LEN 24 4504 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 4505 #define MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4 4506 /* Enum values, see field(s): */ 4507 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4508 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 4509 #define MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4 4510 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 4511 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4 4512 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 4513 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4 4514 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 4515 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 4516 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 4517 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 4518 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5 4519 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1 4520 #define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6 4521 #define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1 4522 #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 4523 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 4524 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 4525 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4 4526 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 4527 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4 4528 4529 /* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */ 4530 #define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28 4531 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0 4532 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4 4533 /* Enum values, see field(s): */ 4534 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4535 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4 4536 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4 4537 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8 4538 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4 4539 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12 4540 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4 4541 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0 4542 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1 4543 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1 4544 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1 4545 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5 4546 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1 4547 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7 4548 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1 4549 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16 4550 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4 4551 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20 4552 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4 4553 /* Writes must be multiples of this size. Added to support the MUM on Sorrento. 4554 */ 4555 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24 4556 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4 4557 4558 4559 /***********************************/ 4560 /* MC_CMD_NVRAM_UPDATE_START 4561 * Start a group of update operations on a virtual NVRAM partition. Locks 4562 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if 4563 * PHY_LOCK required and not held). 4564 */ 4565 #define MC_CMD_NVRAM_UPDATE_START 0x38 4566 4567 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4568 4569 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request. 4570 * Use NVRAM_UPDATE_START_V2_IN in new code 4571 */ 4572 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 4573 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 4574 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4 4575 /* Enum values, see field(s): */ 4576 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4577 4578 /* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START 4579 * request with additional flags indicating version of command in use. See 4580 * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use 4581 * paired up with NVRAM_UPDATE_FINISH_V2_IN. 4582 */ 4583 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8 4584 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0 4585 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4 4586 /* Enum values, see field(s): */ 4587 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4588 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4 4589 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4 4590 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 4591 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 4592 4593 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 4594 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 4595 4596 4597 /***********************************/ 4598 /* MC_CMD_NVRAM_READ 4599 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if 4600 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 4601 * PHY_LOCK required and not held) 4602 */ 4603 #define MC_CMD_NVRAM_READ 0x39 4604 4605 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4606 4607 /* MC_CMD_NVRAM_READ_IN msgrequest */ 4608 #define MC_CMD_NVRAM_READ_IN_LEN 12 4609 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 4610 #define MC_CMD_NVRAM_READ_IN_TYPE_LEN 4 4611 /* Enum values, see field(s): */ 4612 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4613 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 4614 #define MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4 4615 /* amount to read in bytes */ 4616 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 4617 #define MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4 4618 4619 /* MC_CMD_NVRAM_READ_IN_V2 msgrequest */ 4620 #define MC_CMD_NVRAM_READ_IN_V2_LEN 16 4621 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0 4622 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4 4623 /* Enum values, see field(s): */ 4624 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4625 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4 4626 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4 4627 /* amount to read in bytes */ 4628 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8 4629 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4 4630 /* Optional control info. If a partition is stored with an A/B versioning 4631 * scheme (i.e. in more than one physical partition in NVRAM) the host can set 4632 * this to control which underlying physical partition is used to read data 4633 * from. This allows it to perform a read-modify-write-verify with the write 4634 * lock continuously held by calling NVRAM_UPDATE_START, reading the old 4635 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then 4636 * verifying by reading with MODE=TARGET_BACKUP. 4637 */ 4638 #define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12 4639 #define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4 4640 /* enum: Same as omitting MODE: caller sees data in current partition unless it 4641 * holds the write lock in which case it sees data in the partition it is 4642 * updating. 4643 */ 4644 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0 4645 /* enum: Read from the current partition of an A/B pair, even if holding the 4646 * write lock. 4647 */ 4648 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1 4649 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B 4650 * pair 4651 */ 4652 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2 4653 4654 /* MC_CMD_NVRAM_READ_OUT msgresponse */ 4655 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 4656 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 4657 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 4658 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 4659 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 4660 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 4661 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 4662 4663 4664 /***********************************/ 4665 /* MC_CMD_NVRAM_WRITE 4666 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if 4667 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 4668 * PHY_LOCK required and not held) 4669 */ 4670 #define MC_CMD_NVRAM_WRITE 0x3a 4671 4672 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4673 4674 /* MC_CMD_NVRAM_WRITE_IN msgrequest */ 4675 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 4676 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 4677 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 4678 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 4679 #define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4 4680 /* Enum values, see field(s): */ 4681 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4682 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 4683 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4 4684 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 4685 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4 4686 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 4687 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 4688 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 4689 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 4690 4691 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 4692 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 4693 4694 4695 /***********************************/ 4696 /* MC_CMD_NVRAM_ERASE 4697 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if 4698 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 4699 * PHY_LOCK required and not held) 4700 */ 4701 #define MC_CMD_NVRAM_ERASE 0x3b 4702 4703 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4704 4705 /* MC_CMD_NVRAM_ERASE_IN msgrequest */ 4706 #define MC_CMD_NVRAM_ERASE_IN_LEN 12 4707 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 4708 #define MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4 4709 /* Enum values, see field(s): */ 4710 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4711 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 4712 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4 4713 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 4714 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4 4715 4716 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 4717 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 4718 4719 4720 /***********************************/ 4721 /* MC_CMD_NVRAM_UPDATE_FINISH 4722 * Finish a group of update operations on a virtual NVRAM partition. Locks 4723 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad 4724 * type/offset/length), EACCES (if PHY_LOCK required and not held) 4725 */ 4726 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 4727 4728 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4729 4730 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH 4731 * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code 4732 */ 4733 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 4734 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 4735 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4 4736 /* Enum values, see field(s): */ 4737 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4738 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 4739 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4 4740 4741 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH 4742 * request with additional flags indicating version of NVRAM_UPDATE commands in 4743 * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended 4744 * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN. 4745 */ 4746 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12 4747 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0 4748 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4 4749 /* Enum values, see field(s): */ 4750 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4751 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4 4752 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4 4753 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8 4754 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4 4755 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 4756 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 4757 4758 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH 4759 * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code 4760 */ 4761 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 4762 4763 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse: 4764 * 4765 * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure 4766 * firmware validation where applicable back to the host. 4767 * 4768 * Medford only: For signed firmware images, such as those for medford, the MC 4769 * firmware verifies the signature before marking the firmware image as valid. 4770 * This process takes a few seconds to complete. So is likely to take more than 4771 * the MCDI timeout. Hence signature verification is initiated when 4772 * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the 4773 * MCDI command is run in a background MCDI processing thread. This response 4774 * payload includes the results of the signature verification. Note that the 4775 * per-partition nvram lock in firmware is only released after the verification 4776 * has completed. 4777 */ 4778 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4 4779 /* Result of nvram update completion processing */ 4780 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0 4781 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4 4782 /* enum: Invalid return code; only non-zero values are defined. Defined as 4783 * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT. 4784 */ 4785 #define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0 4786 /* enum: Verify succeeded without any errors. */ 4787 #define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1 4788 /* enum: CMS format verification failed due to an internal error. */ 4789 #define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2 4790 /* enum: Invalid CMS format in image metadata. */ 4791 #define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3 4792 /* enum: Message digest verification failed due to an internal error. */ 4793 #define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4 4794 /* enum: Error in message digest calculated over the reflash-header, payload 4795 * and reflash-trailer. 4796 */ 4797 #define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5 4798 /* enum: Signature verification failed due to an internal error. */ 4799 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6 4800 /* enum: There are no valid signatures in the image. */ 4801 #define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7 4802 /* enum: Trusted approvers verification failed due to an internal error. */ 4803 #define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8 4804 /* enum: The Trusted approver's list is empty. */ 4805 #define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9 4806 /* enum: Signature chain verification failed due to an internal error. */ 4807 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa 4808 /* enum: The signers of the signatures in the image are not listed in the 4809 * Trusted approver's list. 4810 */ 4811 #define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb 4812 /* enum: The image contains a test-signed certificate, but the adapter accepts 4813 * only production signed images. 4814 */ 4815 #define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc 4816 /* enum: The image has a lower security level than the current firmware. */ 4817 #define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd 4818 4819 4820 /***********************************/ 4821 /* MC_CMD_REBOOT 4822 * Reboot the MC. 4823 * 4824 * The AFTER_ASSERTION flag is intended to be used when the driver notices an 4825 * assertion failure (at which point it is expected to perform a complete tear 4826 * down and reinitialise), to allow both ports to reset the MC once in an 4827 * atomic fashion. 4828 * 4829 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, 4830 * which means that they will automatically reboot out of the assertion 4831 * handler, so this is in practise an optional operation. It is still 4832 * recommended that drivers execute this to support custom firmwares with 4833 * REBOOT_ON_ASSERT=0. 4834 * 4835 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, 4836 * DATALEN=0 4837 */ 4838 #define MC_CMD_REBOOT 0x3d 4839 4840 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4841 4842 /* MC_CMD_REBOOT_IN msgrequest */ 4843 #define MC_CMD_REBOOT_IN_LEN 4 4844 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 4845 #define MC_CMD_REBOOT_IN_FLAGS_LEN 4 4846 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 4847 4848 /* MC_CMD_REBOOT_OUT msgresponse */ 4849 #define MC_CMD_REBOOT_OUT_LEN 0 4850 4851 4852 /***********************************/ 4853 /* MC_CMD_SCHEDINFO 4854 * Request scheduler info. Locks required: NONE. Returns: An array of 4855 * (timeslice,maximum overrun), one for each thread, in ascending order of 4856 * thread address. 4857 */ 4858 #define MC_CMD_SCHEDINFO 0x3e 4859 4860 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4861 4862 /* MC_CMD_SCHEDINFO_IN msgrequest */ 4863 #define MC_CMD_SCHEDINFO_IN_LEN 0 4864 4865 /* MC_CMD_SCHEDINFO_OUT msgresponse */ 4866 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 4867 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 4868 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 4869 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 4870 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 4871 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 4872 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 4873 4874 4875 /***********************************/ 4876 /* MC_CMD_REBOOT_MODE 4877 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot 4878 * mode to the specified value. Returns the old mode. 4879 */ 4880 #define MC_CMD_REBOOT_MODE 0x3f 4881 4882 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE 4883 4884 /* MC_CMD_REBOOT_MODE_IN msgrequest */ 4885 #define MC_CMD_REBOOT_MODE_IN_LEN 4 4886 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 4887 #define MC_CMD_REBOOT_MODE_IN_VALUE_LEN 4 4888 /* enum: Normal. */ 4889 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 4890 /* enum: Power-on Reset. */ 4891 #define MC_CMD_REBOOT_MODE_POR 0x2 4892 /* enum: Snapper. */ 4893 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 4894 /* enum: snapper fake POR */ 4895 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 4896 #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 4897 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 4898 4899 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 4900 #define MC_CMD_REBOOT_MODE_OUT_LEN 4 4901 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 4902 #define MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4 4903 4904 4905 /***********************************/ 4906 /* MC_CMD_SENSOR_INFO 4907 * Returns information about every available sensor. 4908 * 4909 * Each sensor has a single (16bit) value, and a corresponding state. The 4910 * mapping between value and state is nominally determined by the MC, but may 4911 * be implemented using up to 2 ranges per sensor. 4912 * 4913 * This call returns a mask (32bit) of the sensors that are supported by this 4914 * platform, then an array of sensor information structures, in order of sensor 4915 * type (but without gaps for unimplemented sensors). Each structure defines 4916 * the ranges for the corresponding sensor. An unused range is indicated by 4917 * equal limit values. If one range is used, a value outside that range results 4918 * in STATE_FATAL. If two ranges are used, a value outside the second range 4919 * results in STATE_FATAL while a value outside the first and inside the second 4920 * range results in STATE_WARNING. 4921 * 4922 * Sensor masks and sensor information arrays are organised into pages. For 4923 * backward compatibility, older host software can only use sensors in page 0. 4924 * Bit 32 in the sensor mask was previously unused, and is no reserved for use 4925 * as the next page flag. 4926 * 4927 * If the request does not contain a PAGE value then firmware will only return 4928 * page 0 of sensor information, with bit 31 in the sensor mask cleared. 4929 * 4930 * If the request contains a PAGE value then firmware responds with the sensor 4931 * mask and sensor information array for that page of sensors. In this case bit 4932 * 31 in the mask is set if another page exists. 4933 * 4934 * Locks required: None Returns: 0 4935 */ 4936 #define MC_CMD_SENSOR_INFO 0x41 4937 4938 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4939 4940 /* MC_CMD_SENSOR_INFO_IN msgrequest */ 4941 #define MC_CMD_SENSOR_INFO_IN_LEN 0 4942 4943 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ 4944 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 4945 /* Which page of sensors to report. 4946 * 4947 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). 4948 * 4949 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. 4950 */ 4951 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 4952 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4 4953 4954 /* MC_CMD_SENSOR_INFO_OUT msgresponse */ 4955 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 4956 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 4957 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 4958 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 4959 #define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4 4960 /* enum: Controller temperature: degC */ 4961 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 4962 /* enum: Phy common temperature: degC */ 4963 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 4964 /* enum: Controller cooling: bool */ 4965 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 4966 /* enum: Phy 0 temperature: degC */ 4967 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 4968 /* enum: Phy 0 cooling: bool */ 4969 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 4970 /* enum: Phy 1 temperature: degC */ 4971 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 4972 /* enum: Phy 1 cooling: bool */ 4973 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 4974 /* enum: 1.0v power: mV */ 4975 #define MC_CMD_SENSOR_IN_1V0 0x7 4976 /* enum: 1.2v power: mV */ 4977 #define MC_CMD_SENSOR_IN_1V2 0x8 4978 /* enum: 1.8v power: mV */ 4979 #define MC_CMD_SENSOR_IN_1V8 0x9 4980 /* enum: 2.5v power: mV */ 4981 #define MC_CMD_SENSOR_IN_2V5 0xa 4982 /* enum: 3.3v power: mV */ 4983 #define MC_CMD_SENSOR_IN_3V3 0xb 4984 /* enum: 12v power: mV */ 4985 #define MC_CMD_SENSOR_IN_12V0 0xc 4986 /* enum: 1.2v analogue power: mV */ 4987 #define MC_CMD_SENSOR_IN_1V2A 0xd 4988 /* enum: reference voltage: mV */ 4989 #define MC_CMD_SENSOR_IN_VREF 0xe 4990 /* enum: AOE FPGA power: mV */ 4991 #define MC_CMD_SENSOR_OUT_VAOE 0xf 4992 /* enum: AOE FPGA temperature: degC */ 4993 #define MC_CMD_SENSOR_AOE_TEMP 0x10 4994 /* enum: AOE FPGA PSU temperature: degC */ 4995 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 4996 /* enum: AOE PSU temperature: degC */ 4997 #define MC_CMD_SENSOR_PSU_TEMP 0x12 4998 /* enum: Fan 0 speed: RPM */ 4999 #define MC_CMD_SENSOR_FAN_0 0x13 5000 /* enum: Fan 1 speed: RPM */ 5001 #define MC_CMD_SENSOR_FAN_1 0x14 5002 /* enum: Fan 2 speed: RPM */ 5003 #define MC_CMD_SENSOR_FAN_2 0x15 5004 /* enum: Fan 3 speed: RPM */ 5005 #define MC_CMD_SENSOR_FAN_3 0x16 5006 /* enum: Fan 4 speed: RPM */ 5007 #define MC_CMD_SENSOR_FAN_4 0x17 5008 /* enum: AOE FPGA input power: mV */ 5009 #define MC_CMD_SENSOR_IN_VAOE 0x18 5010 /* enum: AOE FPGA current: mA */ 5011 #define MC_CMD_SENSOR_OUT_IAOE 0x19 5012 /* enum: AOE FPGA input current: mA */ 5013 #define MC_CMD_SENSOR_IN_IAOE 0x1a 5014 /* enum: NIC power consumption: W */ 5015 #define MC_CMD_SENSOR_NIC_POWER 0x1b 5016 /* enum: 0.9v power voltage: mV */ 5017 #define MC_CMD_SENSOR_IN_0V9 0x1c 5018 /* enum: 0.9v power current: mA */ 5019 #define MC_CMD_SENSOR_IN_I0V9 0x1d 5020 /* enum: 1.2v power current: mA */ 5021 #define MC_CMD_SENSOR_IN_I1V2 0x1e 5022 /* enum: Not a sensor: reserved for the next page flag */ 5023 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f 5024 /* enum: 0.9v power voltage (at ADC): mV */ 5025 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 5026 /* enum: Controller temperature 2: degC */ 5027 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 5028 /* enum: Voltage regulator internal temperature: degC */ 5029 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 5030 /* enum: 0.9V voltage regulator temperature: degC */ 5031 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 5032 /* enum: 1.2V voltage regulator temperature: degC */ 5033 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 5034 /* enum: controller internal temperature sensor voltage (internal ADC): mV */ 5035 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 5036 /* enum: controller internal temperature (internal ADC): degC */ 5037 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 5038 /* enum: controller internal temperature sensor voltage (external ADC): mV */ 5039 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 5040 /* enum: controller internal temperature (external ADC): degC */ 5041 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 5042 /* enum: ambient temperature: degC */ 5043 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 5044 /* enum: air flow: bool */ 5045 #define MC_CMD_SENSOR_AIRFLOW 0x2a 5046 /* enum: voltage between VSS08D and VSS08D at CSR: mV */ 5047 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b 5048 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ 5049 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c 5050 /* enum: Hotpoint temperature: degC */ 5051 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d 5052 /* enum: Port 0 PHY power switch over-current: bool */ 5053 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e 5054 /* enum: Port 1 PHY power switch over-current: bool */ 5055 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f 5056 /* enum: Mop-up microcontroller reference voltage (millivolts) */ 5057 #define MC_CMD_SENSOR_MUM_VCC 0x30 5058 /* enum: 0.9v power phase A voltage: mV */ 5059 #define MC_CMD_SENSOR_IN_0V9_A 0x31 5060 /* enum: 0.9v power phase A current: mA */ 5061 #define MC_CMD_SENSOR_IN_I0V9_A 0x32 5062 /* enum: 0.9V voltage regulator phase A temperature: degC */ 5063 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33 5064 /* enum: 0.9v power phase B voltage: mV */ 5065 #define MC_CMD_SENSOR_IN_0V9_B 0x34 5066 /* enum: 0.9v power phase B current: mA */ 5067 #define MC_CMD_SENSOR_IN_I0V9_B 0x35 5068 /* enum: 0.9V voltage regulator phase B temperature: degC */ 5069 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36 5070 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */ 5071 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37 5072 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */ 5073 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38 5074 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */ 5075 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 5076 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */ 5077 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a 5078 /* enum: CCOM RTS temperature: degC */ 5079 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b 5080 /* enum: Not a sensor: reserved for the next page flag */ 5081 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f 5082 /* enum: controller internal temperature sensor voltage on master core 5083 * (internal ADC): mV 5084 */ 5085 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40 5086 /* enum: controller internal temperature on master core (internal ADC): degC */ 5087 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41 5088 /* enum: controller internal temperature sensor voltage on master core 5089 * (external ADC): mV 5090 */ 5091 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42 5092 /* enum: controller internal temperature on master core (external ADC): degC */ 5093 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43 5094 /* enum: controller internal temperature on slave core sensor voltage (internal 5095 * ADC): mV 5096 */ 5097 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44 5098 /* enum: controller internal temperature on slave core (internal ADC): degC */ 5099 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45 5100 /* enum: controller internal temperature on slave core sensor voltage (external 5101 * ADC): mV 5102 */ 5103 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46 5104 /* enum: controller internal temperature on slave core (external ADC): degC */ 5105 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47 5106 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */ 5107 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49 5108 /* enum: Temperature of SODIMM 0 (if installed): degC */ 5109 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a 5110 /* enum: Temperature of SODIMM 1 (if installed): degC */ 5111 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b 5112 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */ 5113 #define MC_CMD_SENSOR_PHY0_VCC 0x4c 5114 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ 5115 #define MC_CMD_SENSOR_PHY1_VCC 0x4d 5116 /* enum: Controller die temperature (TDIODE): degC */ 5117 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e 5118 /* enum: Board temperature (front): degC */ 5119 #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f 5120 /* enum: Board temperature (back): degC */ 5121 #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50 5122 /* enum: 1.8v power current: mA */ 5123 #define MC_CMD_SENSOR_IN_I1V8 0x51 5124 /* enum: 2.5v power current: mA */ 5125 #define MC_CMD_SENSOR_IN_I2V5 0x52 5126 /* enum: 3.3v power current: mA */ 5127 #define MC_CMD_SENSOR_IN_I3V3 0x53 5128 /* enum: 12v power current: mA */ 5129 #define MC_CMD_SENSOR_IN_I12V0 0x54 5130 /* enum: 1.3v power: mV */ 5131 #define MC_CMD_SENSOR_IN_1V3 0x55 5132 /* enum: 1.3v power current: mA */ 5133 #define MC_CMD_SENSOR_IN_I1V3 0x56 5134 /* enum: Not a sensor: reserved for the next page flag */ 5135 #define MC_CMD_SENSOR_PAGE2_NEXT 0x5f 5136 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 5137 #define MC_CMD_SENSOR_ENTRY_OFST 4 5138 #define MC_CMD_SENSOR_ENTRY_LEN 8 5139 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 5140 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 5141 #define MC_CMD_SENSOR_ENTRY_MINNUM 0 5142 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 5143 5144 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ 5145 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 5146 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 5147 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) 5148 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 5149 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4 5150 /* Enum values, see field(s): */ 5151 /* MC_CMD_SENSOR_INFO_OUT */ 5152 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 5153 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 5154 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 5155 /* MC_CMD_SENSOR_ENTRY_OFST 4 */ 5156 /* MC_CMD_SENSOR_ENTRY_LEN 8 */ 5157 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ 5158 /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ 5159 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ 5160 /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ 5161 5162 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 5163 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 5164 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 5165 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 5166 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 5167 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 5168 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 5169 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 5170 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 5171 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 5172 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 5173 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 5174 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 5175 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 5176 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 5177 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 5178 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 5179 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 5180 5181 5182 /***********************************/ 5183 /* MC_CMD_READ_SENSORS 5184 * Returns the current reading from each sensor. DMAs an array of sensor 5185 * readings, in order of sensor type (but without gaps for unimplemented 5186 * sensors), into host memory. Each array element is a 5187 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. 5188 * 5189 * If the request does not contain the LENGTH field then only sensors 0 to 30 5190 * are reported, to avoid DMA buffer overflow in older host software. If the 5191 * sensor reading require more space than the LENGTH allows, then return 5192 * EINVAL. 5193 * 5194 * The MC will send a SENSOREVT event every time any sensor changes state. The 5195 * driver is responsible for ensuring that it doesn't miss any events. The 5196 * board will function normally if all sensors are in STATE_OK or 5197 * STATE_WARNING. Otherwise the board should not be expected to function. 5198 */ 5199 #define MC_CMD_READ_SENSORS 0x42 5200 5201 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5202 5203 /* MC_CMD_READ_SENSORS_IN msgrequest */ 5204 #define MC_CMD_READ_SENSORS_IN_LEN 8 5205 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 5206 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 5207 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 5208 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 5209 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 5210 5211 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ 5212 #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 5213 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 5214 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 5215 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 5216 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 5217 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 5218 /* Size in bytes of host buffer. */ 5219 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 5220 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4 5221 5222 /* MC_CMD_READ_SENSORS_OUT msgresponse */ 5223 #define MC_CMD_READ_SENSORS_OUT_LEN 0 5224 5225 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ 5226 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 5227 5228 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 5229 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 5230 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 5231 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 5232 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 5233 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 5234 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 5235 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 5236 /* enum: Ok. */ 5237 #define MC_CMD_SENSOR_STATE_OK 0x0 5238 /* enum: Breached warning threshold. */ 5239 #define MC_CMD_SENSOR_STATE_WARNING 0x1 5240 /* enum: Breached fatal threshold. */ 5241 #define MC_CMD_SENSOR_STATE_FATAL 0x2 5242 /* enum: Fault with sensor. */ 5243 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 5244 /* enum: Sensor is working but does not currently have a reading. */ 5245 #define MC_CMD_SENSOR_STATE_NO_READING 0x4 5246 /* enum: Sensor initialisation failed. */ 5247 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5 5248 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 5249 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 5250 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 5251 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 5252 /* Enum values, see field(s): */ 5253 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 5254 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 5255 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 5256 5257 5258 /***********************************/ 5259 /* MC_CMD_GET_PHY_STATE 5260 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot 5261 * (e.g. due to missing or corrupted firmware). Locks required: None. Return 5262 * code: 0 5263 */ 5264 #define MC_CMD_GET_PHY_STATE 0x43 5265 5266 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5267 5268 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 5269 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 5270 5271 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 5272 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 5273 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 5274 #define MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4 5275 /* enum: Ok. */ 5276 #define MC_CMD_PHY_STATE_OK 0x1 5277 /* enum: Faulty. */ 5278 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 5279 5280 5281 /***********************************/ 5282 /* MC_CMD_SETUP_8021QBB 5283 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 5284 * disable 802.Qbb for a given priority. 5285 */ 5286 #define MC_CMD_SETUP_8021QBB 0x44 5287 5288 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 5289 #define MC_CMD_SETUP_8021QBB_IN_LEN 32 5290 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 5291 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 5292 5293 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 5294 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 5295 5296 5297 /***********************************/ 5298 /* MC_CMD_WOL_FILTER_GET 5299 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS 5300 */ 5301 #define MC_CMD_WOL_FILTER_GET 0x45 5302 5303 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK 5304 5305 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 5306 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 5307 5308 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 5309 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 5310 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 5311 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4 5312 5313 5314 /***********************************/ 5315 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 5316 * Add a protocol offload to NIC for lights-out state. Locks required: None. 5317 * Returns: 0, ENOSYS 5318 */ 5319 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 5320 5321 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK 5322 5323 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 5324 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 5325 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 5326 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 5327 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 5328 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 5329 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 5330 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 5331 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 5332 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 5333 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 5334 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 5335 5336 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 5337 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 5338 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 5339 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */ 5340 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 5341 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 5342 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 5343 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4 5344 5345 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 5346 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 5347 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 5348 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */ 5349 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 5350 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 5351 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 5352 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 5353 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 5354 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 5355 5356 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 5357 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 5358 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 5359 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4 5360 5361 5362 /***********************************/ 5363 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 5364 * Remove a protocol offload from NIC for lights-out state. Locks required: 5365 * None. Returns: 0, ENOSYS 5366 */ 5367 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 5368 5369 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK 5370 5371 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 5372 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 5373 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 5374 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 5375 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 5376 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4 5377 5378 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 5379 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 5380 5381 5382 /***********************************/ 5383 /* MC_CMD_MAC_RESET_RESTORE 5384 * Restore MAC after block reset. Locks required: None. Returns: 0. 5385 */ 5386 #define MC_CMD_MAC_RESET_RESTORE 0x48 5387 5388 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 5389 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 5390 5391 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 5392 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 5393 5394 5395 /***********************************/ 5396 /* MC_CMD_TESTASSERT 5397 * Deliberately trigger an assert-detonation in the firmware for testing 5398 * purposes (i.e. to allow tests that the driver copes gracefully). Locks 5399 * required: None Returns: 0 5400 */ 5401 #define MC_CMD_TESTASSERT 0x49 5402 5403 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5404 5405 /* MC_CMD_TESTASSERT_IN msgrequest */ 5406 #define MC_CMD_TESTASSERT_IN_LEN 0 5407 5408 /* MC_CMD_TESTASSERT_OUT msgresponse */ 5409 #define MC_CMD_TESTASSERT_OUT_LEN 0 5410 5411 /* MC_CMD_TESTASSERT_V2_IN msgrequest */ 5412 #define MC_CMD_TESTASSERT_V2_IN_LEN 4 5413 /* How to provoke the assertion */ 5414 #define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0 5415 #define MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4 5416 /* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless 5417 * you're testing firmware, this is what you want. 5418 */ 5419 #define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0 5420 /* enum: Assert using assert(0); */ 5421 #define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1 5422 /* enum: Deliberately trigger a watchdog */ 5423 #define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2 5424 /* enum: Deliberately trigger a trap by loading from an invalid address */ 5425 #define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3 5426 /* enum: Deliberately trigger a trap by storing to an invalid address */ 5427 #define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4 5428 /* enum: Jump to an invalid address */ 5429 #define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5 5430 5431 /* MC_CMD_TESTASSERT_V2_OUT msgresponse */ 5432 #define MC_CMD_TESTASSERT_V2_OUT_LEN 0 5433 5434 5435 /***********************************/ 5436 /* MC_CMD_WORKAROUND 5437 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't 5438 * understand the given workaround number - which should not be treated as a 5439 * hard error by client code. This op does not imply any semantics about each 5440 * workaround, that's between the driver and the mcfw on a per-workaround 5441 * basis. Locks required: None. Returns: 0, EINVAL . 5442 */ 5443 #define MC_CMD_WORKAROUND 0x4a 5444 5445 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5446 5447 /* MC_CMD_WORKAROUND_IN msgrequest */ 5448 #define MC_CMD_WORKAROUND_IN_LEN 8 5449 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */ 5450 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 5451 #define MC_CMD_WORKAROUND_IN_TYPE_LEN 4 5452 /* enum: Bug 17230 work around. */ 5453 #define MC_CMD_WORKAROUND_BUG17230 0x1 5454 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 5455 #define MC_CMD_WORKAROUND_BUG35388 0x2 5456 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 5457 #define MC_CMD_WORKAROUND_BUG35017 0x3 5458 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 5459 #define MC_CMD_WORKAROUND_BUG41750 0x4 5460 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 5461 * - before adding code that queries this workaround, remember that there's 5462 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 5463 * and will hence (incorrectly) report that the bug doesn't exist. 5464 */ 5465 #define MC_CMD_WORKAROUND_BUG42008 0x5 5466 /* enum: Bug 26807 features present in firmware (multicast filter chaining) 5467 * This feature cannot be turned on/off while there are any filters already 5468 * present. The behaviour in such case depends on the acting client's privilege 5469 * level. If the client has the admin privilege, then all functions that have 5470 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise 5471 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT. 5472 */ 5473 #define MC_CMD_WORKAROUND_BUG26807 0x6 5474 /* enum: Bug 61265 work around (broken EVQ TMR writes). */ 5475 #define MC_CMD_WORKAROUND_BUG61265 0x7 5476 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable 5477 * the workaround 5478 */ 5479 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 5480 #define MC_CMD_WORKAROUND_IN_ENABLED_LEN 4 5481 5482 /* MC_CMD_WORKAROUND_OUT msgresponse */ 5483 #define MC_CMD_WORKAROUND_OUT_LEN 0 5484 5485 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used 5486 * when (TYPE == MC_CMD_WORKAROUND_BUG26807) 5487 */ 5488 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4 5489 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0 5490 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4 5491 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 5492 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1 5493 5494 5495 /***********************************/ 5496 /* MC_CMD_GET_PHY_MEDIA_INFO 5497 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for 5498 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG 5499 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the 5500 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 5501 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. 5502 * Anything else: currently undefined. Locks required: None. Return code: 0. 5503 */ 5504 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 5505 5506 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5507 5508 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 5509 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 5510 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 5511 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4 5512 5513 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 5514 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 5515 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 5516 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 5517 /* in bytes */ 5518 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 5519 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4 5520 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 5521 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 5522 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 5523 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 5524 5525 5526 /***********************************/ 5527 /* MC_CMD_NVRAM_TEST 5528 * Test a particular NVRAM partition for valid contents (where "valid" depends 5529 * on the type of partition). 5530 */ 5531 #define MC_CMD_NVRAM_TEST 0x4c 5532 5533 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5534 5535 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 5536 #define MC_CMD_NVRAM_TEST_IN_LEN 4 5537 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 5538 #define MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4 5539 /* Enum values, see field(s): */ 5540 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5541 5542 /* MC_CMD_NVRAM_TEST_OUT msgresponse */ 5543 #define MC_CMD_NVRAM_TEST_OUT_LEN 4 5544 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 5545 #define MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4 5546 /* enum: Passed. */ 5547 #define MC_CMD_NVRAM_TEST_PASS 0x0 5548 /* enum: Failed. */ 5549 #define MC_CMD_NVRAM_TEST_FAIL 0x1 5550 /* enum: Not supported. */ 5551 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 5552 5553 5554 /***********************************/ 5555 /* MC_CMD_MRSFP_TWEAK 5556 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. 5557 * I2C I/O expander bits are always read; if equaliser parameters are supplied, 5558 * they are configured first. Locks required: None. Return code: 0, EINVAL. 5559 */ 5560 #define MC_CMD_MRSFP_TWEAK 0x4d 5561 5562 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 5563 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 5564 /* 0-6 low->high de-emph. */ 5565 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 5566 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4 5567 /* 0-8 low->high ref.V */ 5568 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 5569 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4 5570 /* 0-8 0-8 low->high boost */ 5571 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 5572 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4 5573 /* 0-8 low->high ref.V */ 5574 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 5575 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4 5576 5577 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 5578 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 5579 5580 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 5581 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 5582 /* input bits */ 5583 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 5584 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4 5585 /* output bits */ 5586 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 5587 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4 5588 /* direction */ 5589 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 5590 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4 5591 /* enum: Out. */ 5592 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 5593 /* enum: In. */ 5594 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 5595 5596 5597 /***********************************/ 5598 /* MC_CMD_SENSOR_SET_LIMS 5599 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: 5600 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out 5601 * of range. 5602 */ 5603 #define MC_CMD_SENSOR_SET_LIMS 0x4e 5604 5605 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE 5606 5607 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 5608 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 5609 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 5610 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4 5611 /* Enum values, see field(s): */ 5612 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 5613 /* interpretation is is sensor-specific. */ 5614 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 5615 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4 5616 /* interpretation is is sensor-specific. */ 5617 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 5618 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4 5619 /* interpretation is is sensor-specific. */ 5620 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 5621 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4 5622 /* interpretation is is sensor-specific. */ 5623 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 5624 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4 5625 5626 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 5627 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 5628 5629 5630 /***********************************/ 5631 /* MC_CMD_GET_RESOURCE_LIMITS 5632 */ 5633 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 5634 5635 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 5636 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 5637 5638 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 5639 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 5640 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 5641 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4 5642 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 5643 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4 5644 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 5645 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4 5646 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 5647 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4 5648 5649 5650 /***********************************/ 5651 /* MC_CMD_NVRAM_PARTITIONS 5652 * Reads the list of available virtual NVRAM partition types. Locks required: 5653 * none. Returns: 0, EINVAL (bad type). 5654 */ 5655 #define MC_CMD_NVRAM_PARTITIONS 0x51 5656 5657 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5658 5659 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ 5660 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 5661 5662 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ 5663 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 5664 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 5665 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) 5666 /* total number of partitions */ 5667 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 5668 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4 5669 /* type ID code for each of NUM_PARTITIONS partitions */ 5670 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 5671 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 5672 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 5673 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 5674 5675 5676 /***********************************/ 5677 /* MC_CMD_NVRAM_METADATA 5678 * Reads soft metadata for a virtual NVRAM partition type. Locks required: 5679 * none. Returns: 0, EINVAL (bad type). 5680 */ 5681 #define MC_CMD_NVRAM_METADATA 0x52 5682 5683 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5684 5685 /* MC_CMD_NVRAM_METADATA_IN msgrequest */ 5686 #define MC_CMD_NVRAM_METADATA_IN_LEN 4 5687 /* Partition type ID code */ 5688 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 5689 #define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4 5690 5691 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */ 5692 #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 5693 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 5694 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) 5695 /* Partition type ID code */ 5696 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 5697 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4 5698 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 5699 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4 5700 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 5701 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 5702 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 5703 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 5704 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 5705 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 5706 /* Subtype ID code for content of this partition */ 5707 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 5708 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4 5709 /* 1st component of W.X.Y.Z version number for content of this partition */ 5710 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 5711 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 5712 /* 2nd component of W.X.Y.Z version number for content of this partition */ 5713 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 5714 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 5715 /* 3rd component of W.X.Y.Z version number for content of this partition */ 5716 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 5717 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 5718 /* 4th component of W.X.Y.Z version number for content of this partition */ 5719 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 5720 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 5721 /* Zero-terminated string describing the content of this partition */ 5722 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 5723 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 5724 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 5725 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 5726 5727 5728 /***********************************/ 5729 /* MC_CMD_GET_MAC_ADDRESSES 5730 * Returns the base MAC, count and stride for the requesting function 5731 */ 5732 #define MC_CMD_GET_MAC_ADDRESSES 0x55 5733 5734 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5735 5736 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ 5737 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 5738 5739 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ 5740 #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 5741 /* Base MAC address */ 5742 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 5743 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 5744 /* Padding */ 5745 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 5746 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 5747 /* Number of allocated MAC addresses */ 5748 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 5749 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4 5750 /* Spacing of allocated MAC addresses */ 5751 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 5752 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4 5753 5754 5755 /***********************************/ 5756 /* MC_CMD_CLP 5757 * Perform a CLP related operation 5758 */ 5759 #define MC_CMD_CLP 0x56 5760 5761 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5762 5763 /* MC_CMD_CLP_IN msgrequest */ 5764 #define MC_CMD_CLP_IN_LEN 4 5765 /* Sub operation */ 5766 #define MC_CMD_CLP_IN_OP_OFST 0 5767 #define MC_CMD_CLP_IN_OP_LEN 4 5768 /* enum: Return to factory default settings */ 5769 #define MC_CMD_CLP_OP_DEFAULT 0x1 5770 /* enum: Set MAC address */ 5771 #define MC_CMD_CLP_OP_SET_MAC 0x2 5772 /* enum: Get MAC address */ 5773 #define MC_CMD_CLP_OP_GET_MAC 0x3 5774 /* enum: Set UEFI/GPXE boot mode */ 5775 #define MC_CMD_CLP_OP_SET_BOOT 0x4 5776 /* enum: Get UEFI/GPXE boot mode */ 5777 #define MC_CMD_CLP_OP_GET_BOOT 0x5 5778 5779 /* MC_CMD_CLP_OUT msgresponse */ 5780 #define MC_CMD_CLP_OUT_LEN 0 5781 5782 /* MC_CMD_CLP_IN_DEFAULT msgrequest */ 5783 #define MC_CMD_CLP_IN_DEFAULT_LEN 4 5784 /* MC_CMD_CLP_IN_OP_OFST 0 */ 5785 /* MC_CMD_CLP_IN_OP_LEN 4 */ 5786 5787 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */ 5788 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0 5789 5790 /* MC_CMD_CLP_IN_SET_MAC msgrequest */ 5791 #define MC_CMD_CLP_IN_SET_MAC_LEN 12 5792 /* MC_CMD_CLP_IN_OP_OFST 0 */ 5793 /* MC_CMD_CLP_IN_OP_LEN 4 */ 5794 /* MAC address assigned to port */ 5795 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 5796 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 5797 /* Padding */ 5798 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 5799 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 5800 5801 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */ 5802 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0 5803 5804 /* MC_CMD_CLP_IN_GET_MAC msgrequest */ 5805 #define MC_CMD_CLP_IN_GET_MAC_LEN 4 5806 /* MC_CMD_CLP_IN_OP_OFST 0 */ 5807 /* MC_CMD_CLP_IN_OP_LEN 4 */ 5808 5809 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */ 5810 #define MC_CMD_CLP_OUT_GET_MAC_LEN 8 5811 /* MAC address assigned to port */ 5812 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 5813 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 5814 /* Padding */ 5815 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 5816 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 5817 5818 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */ 5819 #define MC_CMD_CLP_IN_SET_BOOT_LEN 5 5820 /* MC_CMD_CLP_IN_OP_OFST 0 */ 5821 /* MC_CMD_CLP_IN_OP_LEN 4 */ 5822 /* Boot flag */ 5823 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 5824 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 5825 5826 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ 5827 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 5828 5829 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */ 5830 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4 5831 /* MC_CMD_CLP_IN_OP_OFST 0 */ 5832 /* MC_CMD_CLP_IN_OP_LEN 4 */ 5833 5834 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ 5835 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 5836 /* Boot flag */ 5837 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 5838 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 5839 /* Padding */ 5840 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 5841 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 5842 5843 5844 /***********************************/ 5845 /* MC_CMD_MUM 5846 * Perform a MUM operation 5847 */ 5848 #define MC_CMD_MUM 0x57 5849 5850 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE 5851 5852 /* MC_CMD_MUM_IN msgrequest */ 5853 #define MC_CMD_MUM_IN_LEN 4 5854 #define MC_CMD_MUM_IN_OP_HDR_OFST 0 5855 #define MC_CMD_MUM_IN_OP_HDR_LEN 4 5856 #define MC_CMD_MUM_IN_OP_LBN 0 5857 #define MC_CMD_MUM_IN_OP_WIDTH 8 5858 /* enum: NULL MCDI command to MUM */ 5859 #define MC_CMD_MUM_OP_NULL 0x1 5860 /* enum: Get MUM version */ 5861 #define MC_CMD_MUM_OP_GET_VERSION 0x2 5862 /* enum: Issue raw I2C command to MUM */ 5863 #define MC_CMD_MUM_OP_RAW_CMD 0x3 5864 /* enum: Read from registers on devices connected to MUM. */ 5865 #define MC_CMD_MUM_OP_READ 0x4 5866 /* enum: Write to registers on devices connected to MUM. */ 5867 #define MC_CMD_MUM_OP_WRITE 0x5 5868 /* enum: Control UART logging. */ 5869 #define MC_CMD_MUM_OP_LOG 0x6 5870 /* enum: Operations on MUM GPIO lines */ 5871 #define MC_CMD_MUM_OP_GPIO 0x7 5872 /* enum: Get sensor readings from MUM */ 5873 #define MC_CMD_MUM_OP_READ_SENSORS 0x8 5874 /* enum: Initiate clock programming on the MUM */ 5875 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9 5876 /* enum: Initiate FPGA load from flash on the MUM */ 5877 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa 5878 /* enum: Request sensor reading from MUM ADC resulting from earlier request via 5879 * MUM ATB 5880 */ 5881 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb 5882 /* enum: Send commands relating to the QSFP ports via the MUM for PHY 5883 * operations 5884 */ 5885 #define MC_CMD_MUM_OP_QSFP 0xc 5886 /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage 5887 * level) from MUM 5888 */ 5889 #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd 5890 5891 /* MC_CMD_MUM_IN_NULL msgrequest */ 5892 #define MC_CMD_MUM_IN_NULL_LEN 4 5893 /* MUM cmd header */ 5894 #define MC_CMD_MUM_IN_CMD_OFST 0 5895 #define MC_CMD_MUM_IN_CMD_LEN 4 5896 5897 /* MC_CMD_MUM_IN_GET_VERSION msgrequest */ 5898 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4 5899 /* MUM cmd header */ 5900 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5901 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 5902 5903 /* MC_CMD_MUM_IN_READ msgrequest */ 5904 #define MC_CMD_MUM_IN_READ_LEN 16 5905 /* MUM cmd header */ 5906 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5907 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 5908 /* ID of (device connected to MUM) to read from registers of */ 5909 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4 5910 #define MC_CMD_MUM_IN_READ_DEVICE_LEN 4 5911 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 5912 #define MC_CMD_MUM_DEV_HITTITE 0x1 5913 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */ 5914 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2 5915 /* 32-bit address to read from */ 5916 #define MC_CMD_MUM_IN_READ_ADDR_OFST 8 5917 #define MC_CMD_MUM_IN_READ_ADDR_LEN 4 5918 /* Number of words to read. */ 5919 #define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12 5920 #define MC_CMD_MUM_IN_READ_NUMWORDS_LEN 4 5921 5922 /* MC_CMD_MUM_IN_WRITE msgrequest */ 5923 #define MC_CMD_MUM_IN_WRITE_LENMIN 16 5924 #define MC_CMD_MUM_IN_WRITE_LENMAX 252 5925 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) 5926 /* MUM cmd header */ 5927 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5928 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 5929 /* ID of (device connected to MUM) to write to registers of */ 5930 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4 5931 #define MC_CMD_MUM_IN_WRITE_DEVICE_LEN 4 5932 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 5933 /* MC_CMD_MUM_DEV_HITTITE 0x1 */ 5934 /* 32-bit address to write to */ 5935 #define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8 5936 #define MC_CMD_MUM_IN_WRITE_ADDR_LEN 4 5937 /* Words to write */ 5938 #define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12 5939 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4 5940 #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1 5941 #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60 5942 5943 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */ 5944 #define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17 5945 #define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252 5946 #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) 5947 /* MUM cmd header */ 5948 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5949 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 5950 /* MUM I2C cmd code */ 5951 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4 5952 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4 5953 /* Number of bytes to write */ 5954 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8 5955 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4 5956 /* Number of bytes to read */ 5957 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12 5958 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4 5959 /* Bytes to write */ 5960 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16 5961 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1 5962 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1 5963 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236 5964 5965 /* MC_CMD_MUM_IN_LOG msgrequest */ 5966 #define MC_CMD_MUM_IN_LOG_LEN 8 5967 /* MUM cmd header */ 5968 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5969 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 5970 #define MC_CMD_MUM_IN_LOG_OP_OFST 4 5971 #define MC_CMD_MUM_IN_LOG_OP_LEN 4 5972 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */ 5973 5974 /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */ 5975 #define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12 5976 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5977 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 5978 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */ 5979 /* MC_CMD_MUM_IN_LOG_OP_LEN 4 */ 5980 /* Enable/disable debug output to UART */ 5981 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8 5982 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4 5983 5984 /* MC_CMD_MUM_IN_GPIO msgrequest */ 5985 #define MC_CMD_MUM_IN_GPIO_LEN 8 5986 /* MUM cmd header */ 5987 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5988 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 5989 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4 5990 #define MC_CMD_MUM_IN_GPIO_HDR_LEN 4 5991 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0 5992 #define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8 5993 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */ 5994 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */ 5995 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */ 5996 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */ 5997 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */ 5998 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */ 5999 6000 /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */ 6001 #define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8 6002 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6003 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6004 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4 6005 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4 6006 6007 /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ 6008 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 6009 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6010 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6011 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 6012 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4 6013 /* The first 32-bit word to be written to the GPIO OUT register. */ 6014 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 6015 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4 6016 /* The second 32-bit word to be written to the GPIO OUT register. */ 6017 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 6018 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4 6019 6020 /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */ 6021 #define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8 6022 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6023 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6024 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4 6025 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4 6026 6027 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ 6028 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 6029 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6030 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6031 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 6032 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4 6033 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ 6034 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 6035 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4 6036 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ 6037 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 6038 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4 6039 6040 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */ 6041 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8 6042 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6043 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6044 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4 6045 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4 6046 6047 /* MC_CMD_MUM_IN_GPIO_OP msgrequest */ 6048 #define MC_CMD_MUM_IN_GPIO_OP_LEN 8 6049 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6050 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6051 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4 6052 #define MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4 6053 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8 6054 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8 6055 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */ 6056 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */ 6057 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */ 6058 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */ 6059 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16 6060 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8 6061 6062 /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */ 6063 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8 6064 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6065 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6066 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4 6067 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4 6068 6069 /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */ 6070 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8 6071 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6072 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6073 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4 6074 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4 6075 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24 6076 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8 6077 6078 /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */ 6079 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8 6080 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6081 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6082 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4 6083 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4 6084 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24 6085 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8 6086 6087 /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */ 6088 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8 6089 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6090 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6091 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4 6092 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4 6093 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24 6094 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8 6095 6096 /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */ 6097 #define MC_CMD_MUM_IN_READ_SENSORS_LEN 8 6098 /* MUM cmd header */ 6099 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6100 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6101 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4 6102 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4 6103 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0 6104 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8 6105 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8 6106 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8 6107 6108 /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */ 6109 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12 6110 /* MUM cmd header */ 6111 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6112 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6113 /* Bit-mask of clocks to be programmed */ 6114 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4 6115 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4 6116 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */ 6117 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */ 6118 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */ 6119 /* Control flags for clock programming */ 6120 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 6121 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4 6122 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 6123 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 6124 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1 6125 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1 6126 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2 6127 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1 6128 6129 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ 6130 #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 6131 /* MUM cmd header */ 6132 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6133 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6134 /* Enable/Disable FPGA config from flash */ 6135 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4 6136 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4 6137 6138 /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */ 6139 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4 6140 /* MUM cmd header */ 6141 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6142 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6143 6144 /* MC_CMD_MUM_IN_QSFP msgrequest */ 6145 #define MC_CMD_MUM_IN_QSFP_LEN 12 6146 /* MUM cmd header */ 6147 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6148 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6149 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4 6150 #define MC_CMD_MUM_IN_QSFP_HDR_LEN 4 6151 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0 6152 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4 6153 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */ 6154 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */ 6155 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */ 6156 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */ 6157 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */ 6158 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */ 6159 #define MC_CMD_MUM_IN_QSFP_IDX_OFST 8 6160 #define MC_CMD_MUM_IN_QSFP_IDX_LEN 4 6161 6162 /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */ 6163 #define MC_CMD_MUM_IN_QSFP_INIT_LEN 16 6164 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6165 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6166 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4 6167 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4 6168 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8 6169 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4 6170 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12 6171 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4 6172 6173 /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */ 6174 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24 6175 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6176 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6177 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4 6178 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4 6179 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8 6180 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4 6181 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12 6182 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4 6183 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16 6184 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4 6185 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20 6186 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4 6187 6188 /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */ 6189 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12 6190 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6191 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6192 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4 6193 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4 6194 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8 6195 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4 6196 6197 /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */ 6198 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16 6199 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6200 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6201 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4 6202 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4 6203 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8 6204 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4 6205 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12 6206 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4 6207 6208 /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */ 6209 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12 6210 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6211 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6212 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4 6213 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4 6214 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8 6215 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4 6216 6217 /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */ 6218 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12 6219 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6220 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6221 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 6222 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4 6223 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 6224 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4 6225 6226 /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */ 6227 #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4 6228 /* MUM cmd header */ 6229 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6230 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6231 6232 /* MC_CMD_MUM_OUT msgresponse */ 6233 #define MC_CMD_MUM_OUT_LEN 0 6234 6235 /* MC_CMD_MUM_OUT_NULL msgresponse */ 6236 #define MC_CMD_MUM_OUT_NULL_LEN 0 6237 6238 /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */ 6239 #define MC_CMD_MUM_OUT_GET_VERSION_LEN 12 6240 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0 6241 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4 6242 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4 6243 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8 6244 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4 6245 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8 6246 6247 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */ 6248 #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1 6249 #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252 6250 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) 6251 /* returned data */ 6252 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0 6253 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1 6254 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1 6255 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252 6256 6257 /* MC_CMD_MUM_OUT_READ msgresponse */ 6258 #define MC_CMD_MUM_OUT_READ_LENMIN 4 6259 #define MC_CMD_MUM_OUT_READ_LENMAX 252 6260 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) 6261 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0 6262 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4 6263 #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1 6264 #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63 6265 6266 /* MC_CMD_MUM_OUT_WRITE msgresponse */ 6267 #define MC_CMD_MUM_OUT_WRITE_LEN 0 6268 6269 /* MC_CMD_MUM_OUT_LOG msgresponse */ 6270 #define MC_CMD_MUM_OUT_LOG_LEN 0 6271 6272 /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */ 6273 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0 6274 6275 /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ 6276 #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 6277 /* The first 32-bit word read from the GPIO IN register. */ 6278 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 6279 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4 6280 /* The second 32-bit word read from the GPIO IN register. */ 6281 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 6282 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4 6283 6284 /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */ 6285 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0 6286 6287 /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ 6288 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 6289 /* The first 32-bit word read from the GPIO OUT register. */ 6290 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 6291 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4 6292 /* The second 32-bit word read from the GPIO OUT register. */ 6293 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 6294 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4 6295 6296 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */ 6297 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0 6298 6299 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */ 6300 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8 6301 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0 6302 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4 6303 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4 6304 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4 6305 6306 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */ 6307 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4 6308 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0 6309 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4 6310 6311 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */ 6312 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0 6313 6314 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */ 6315 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0 6316 6317 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */ 6318 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0 6319 6320 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */ 6321 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4 6322 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252 6323 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) 6324 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0 6325 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4 6326 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1 6327 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63 6328 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0 6329 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16 6330 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16 6331 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8 6332 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24 6333 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8 6334 6335 /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */ 6336 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4 6337 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0 6338 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4 6339 6340 /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */ 6341 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0 6342 6343 /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */ 6344 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4 6345 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0 6346 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4 6347 6348 /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */ 6349 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0 6350 6351 /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */ 6352 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8 6353 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0 6354 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4 6355 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4 6356 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4 6357 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0 6358 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1 6359 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1 6360 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1 6361 6362 /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */ 6363 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4 6364 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0 6365 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4 6366 6367 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */ 6368 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5 6369 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252 6370 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) 6371 /* in bytes */ 6372 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0 6373 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4 6374 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4 6375 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1 6376 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1 6377 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248 6378 6379 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */ 6380 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8 6381 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0 6382 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4 6383 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4 6384 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4 6385 6386 /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */ 6387 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 6388 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 6389 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4 6390 6391 /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */ 6392 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24 6393 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248 6394 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num)) 6395 /* Discrete (soldered) DDR resistor strap info */ 6396 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0 6397 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4 6398 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0 6399 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16 6400 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16 6401 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16 6402 /* Number of SODIMM info records */ 6403 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4 6404 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4 6405 /* Array of SODIMM info records */ 6406 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8 6407 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8 6408 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8 6409 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12 6410 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2 6411 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30 6412 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0 6413 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8 6414 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */ 6415 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0 6416 /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */ 6417 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1 6418 /* enum: Total number of SODIMM banks */ 6419 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2 6420 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8 6421 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8 6422 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16 6423 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4 6424 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20 6425 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4 6426 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */ 6427 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */ 6428 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */ 6429 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */ 6430 /* enum: Values 5-15 are reserved for future usage */ 6431 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4 6432 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24 6433 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8 6434 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32 6435 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16 6436 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48 6437 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4 6438 /* enum: No module present */ 6439 #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0 6440 /* enum: Module present supported and powered on */ 6441 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1 6442 /* enum: Module present but bad type */ 6443 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2 6444 /* enum: Module present but incompatible voltage */ 6445 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3 6446 /* enum: Module present but unknown SPD */ 6447 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4 6448 /* enum: Module present but slot cannot support it */ 6449 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5 6450 /* enum: Modules may or may not be present, but cannot establish contact by I2C 6451 */ 6452 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6 6453 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52 6454 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12 6455 6456 /* MC_CMD_RESOURCE_SPECIFIER enum */ 6457 /* enum: Any */ 6458 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff 6459 /* enum: None */ 6460 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe 6461 6462 /* EVB_PORT_ID structuredef */ 6463 #define EVB_PORT_ID_LEN 4 6464 #define EVB_PORT_ID_PORT_ID_OFST 0 6465 #define EVB_PORT_ID_PORT_ID_LEN 4 6466 /* enum: An invalid port handle. */ 6467 #define EVB_PORT_ID_NULL 0x0 6468 /* enum: The port assigned to this function.. */ 6469 #define EVB_PORT_ID_ASSIGNED 0x1000000 6470 /* enum: External network port 0 */ 6471 #define EVB_PORT_ID_MAC0 0x2000000 6472 /* enum: External network port 1 */ 6473 #define EVB_PORT_ID_MAC1 0x2000001 6474 /* enum: External network port 2 */ 6475 #define EVB_PORT_ID_MAC2 0x2000002 6476 /* enum: External network port 3 */ 6477 #define EVB_PORT_ID_MAC3 0x2000003 6478 #define EVB_PORT_ID_PORT_ID_LBN 0 6479 #define EVB_PORT_ID_PORT_ID_WIDTH 32 6480 6481 /* EVB_VLAN_TAG structuredef */ 6482 #define EVB_VLAN_TAG_LEN 2 6483 /* The VLAN tag value */ 6484 #define EVB_VLAN_TAG_VLAN_ID_LBN 0 6485 #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 6486 #define EVB_VLAN_TAG_MODE_LBN 12 6487 #define EVB_VLAN_TAG_MODE_WIDTH 4 6488 /* enum: Insert the VLAN. */ 6489 #define EVB_VLAN_TAG_INSERT 0x0 6490 /* enum: Replace the VLAN if already present. */ 6491 #define EVB_VLAN_TAG_REPLACE 0x1 6492 6493 /* BUFTBL_ENTRY structuredef */ 6494 #define BUFTBL_ENTRY_LEN 12 6495 /* the owner ID */ 6496 #define BUFTBL_ENTRY_OID_OFST 0 6497 #define BUFTBL_ENTRY_OID_LEN 2 6498 #define BUFTBL_ENTRY_OID_LBN 0 6499 #define BUFTBL_ENTRY_OID_WIDTH 16 6500 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ 6501 #define BUFTBL_ENTRY_PGSZ_OFST 2 6502 #define BUFTBL_ENTRY_PGSZ_LEN 2 6503 #define BUFTBL_ENTRY_PGSZ_LBN 16 6504 #define BUFTBL_ENTRY_PGSZ_WIDTH 16 6505 /* the raw 64-bit address field from the SMC, not adjusted for page size */ 6506 #define BUFTBL_ENTRY_RAWADDR_OFST 4 6507 #define BUFTBL_ENTRY_RAWADDR_LEN 8 6508 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 6509 #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 6510 #define BUFTBL_ENTRY_RAWADDR_LBN 32 6511 #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 6512 6513 /* NVRAM_PARTITION_TYPE structuredef */ 6514 #define NVRAM_PARTITION_TYPE_LEN 2 6515 #define NVRAM_PARTITION_TYPE_ID_OFST 0 6516 #define NVRAM_PARTITION_TYPE_ID_LEN 2 6517 /* enum: Primary MC firmware partition */ 6518 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 6519 /* enum: Secondary MC firmware partition */ 6520 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 6521 /* enum: Expansion ROM partition */ 6522 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 6523 /* enum: Static configuration TLV partition */ 6524 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 6525 /* enum: Dynamic configuration TLV partition */ 6526 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 6527 /* enum: Expansion ROM configuration data for port 0 */ 6528 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 6529 /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */ 6530 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600 6531 /* enum: Expansion ROM configuration data for port 1 */ 6532 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 6533 /* enum: Expansion ROM configuration data for port 2 */ 6534 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 6535 /* enum: Expansion ROM configuration data for port 3 */ 6536 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 6537 /* enum: Non-volatile log output partition */ 6538 #define NVRAM_PARTITION_TYPE_LOG 0x700 6539 /* enum: Non-volatile log output of second core on dual-core device */ 6540 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701 6541 /* enum: Device state dump output partition */ 6542 #define NVRAM_PARTITION_TYPE_DUMP 0x800 6543 /* enum: Application license key storage partition */ 6544 #define NVRAM_PARTITION_TYPE_LICENSE 0x900 6545 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ 6546 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 6547 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ 6548 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff 6549 /* enum: Primary FPGA partition */ 6550 #define NVRAM_PARTITION_TYPE_FPGA 0xb00 6551 /* enum: Secondary FPGA partition */ 6552 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01 6553 /* enum: FC firmware partition */ 6554 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02 6555 /* enum: FC License partition */ 6556 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03 6557 /* enum: Non-volatile log output partition for FC */ 6558 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04 6559 /* enum: MUM firmware partition */ 6560 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00 6561 /* enum: SUC firmware partition (this is intentionally an alias of 6562 * MUM_FIRMWARE) 6563 */ 6564 #define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00 6565 /* enum: MUM Non-volatile log output partition. */ 6566 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01 6567 /* enum: MUM Application table partition. */ 6568 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02 6569 /* enum: MUM boot rom partition. */ 6570 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03 6571 /* enum: MUM production signatures & calibration rom partition. */ 6572 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04 6573 /* enum: MUM user signatures & calibration rom partition. */ 6574 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05 6575 /* enum: MUM fuses and lockbits partition. */ 6576 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06 6577 /* enum: UEFI expansion ROM if separate from PXE */ 6578 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00 6579 /* enum: Used by the expansion ROM for logging */ 6580 #define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000 6581 /* enum: Used for XIP code of shmbooted images */ 6582 #define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100 6583 /* enum: Spare partition 2 */ 6584 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200 6585 /* enum: Manufacturing partition. Used during manufacture to pass information 6586 * between XJTAG and Manftest. 6587 */ 6588 #define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300 6589 /* enum: Spare partition 4 */ 6590 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400 6591 /* enum: Spare partition 5 */ 6592 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500 6593 /* enum: Partition for reporting MC status. See mc_flash_layout.h 6594 * medford_mc_status_hdr_t for layout on Medford. 6595 */ 6596 #define NVRAM_PARTITION_TYPE_STATUS 0x1600 6597 /* enum: Spare partition 13 */ 6598 #define NVRAM_PARTITION_TYPE_SPARE_13 0x1700 6599 /* enum: Spare partition 14 */ 6600 #define NVRAM_PARTITION_TYPE_SPARE_14 0x1800 6601 /* enum: Spare partition 15 */ 6602 #define NVRAM_PARTITION_TYPE_SPARE_15 0x1900 6603 /* enum: Spare partition 16 */ 6604 #define NVRAM_PARTITION_TYPE_SPARE_16 0x1a00 6605 /* enum: Factory defaults for dynamic configuration */ 6606 #define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00 6607 /* enum: Factory defaults for expansion ROM configuration */ 6608 #define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00 6609 /* enum: Field Replaceable Unit inventory information for use on IPMI 6610 * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a 6611 * subset of the information stored in this partition. 6612 */ 6613 #define NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00 6614 /* enum: Start of reserved value range (firmware may use for any purpose) */ 6615 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 6616 /* enum: End of reserved value range (firmware may use for any purpose) */ 6617 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd 6618 /* enum: Recovery partition map (provided if real map is missing or corrupt) */ 6619 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe 6620 /* enum: Partition map (real map as stored in flash) */ 6621 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff 6622 #define NVRAM_PARTITION_TYPE_ID_LBN 0 6623 #define NVRAM_PARTITION_TYPE_ID_WIDTH 16 6624 6625 /* LICENSED_APP_ID structuredef */ 6626 #define LICENSED_APP_ID_LEN 4 6627 #define LICENSED_APP_ID_ID_OFST 0 6628 #define LICENSED_APP_ID_ID_LEN 4 6629 /* enum: OpenOnload */ 6630 #define LICENSED_APP_ID_ONLOAD 0x1 6631 /* enum: PTP timestamping */ 6632 #define LICENSED_APP_ID_PTP 0x2 6633 /* enum: SolarCapture Pro */ 6634 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 6635 /* enum: SolarSecure filter engine */ 6636 #define LICENSED_APP_ID_SOLARSECURE 0x8 6637 /* enum: Performance monitor */ 6638 #define LICENSED_APP_ID_PERF_MONITOR 0x10 6639 /* enum: SolarCapture Live */ 6640 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20 6641 /* enum: Capture SolarSystem */ 6642 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40 6643 /* enum: Network Access Control */ 6644 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80 6645 /* enum: TCP Direct */ 6646 #define LICENSED_APP_ID_TCP_DIRECT 0x100 6647 /* enum: Low Latency */ 6648 #define LICENSED_APP_ID_LOW_LATENCY 0x200 6649 /* enum: SolarCapture Tap */ 6650 #define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400 6651 /* enum: Capture SolarSystem 40G */ 6652 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800 6653 /* enum: Capture SolarSystem 1G */ 6654 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000 6655 /* enum: ScaleOut Onload */ 6656 #define LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000 6657 /* enum: SCS Network Analytics Dashboard */ 6658 #define LICENSED_APP_ID_DSHBRD 0x4000 6659 /* enum: SolarCapture Trading Analytics */ 6660 #define LICENSED_APP_ID_SCATRD 0x8000 6661 #define LICENSED_APP_ID_ID_LBN 0 6662 #define LICENSED_APP_ID_ID_WIDTH 32 6663 6664 /* LICENSED_FEATURES structuredef */ 6665 #define LICENSED_FEATURES_LEN 8 6666 /* Bitmask of licensed firmware features */ 6667 #define LICENSED_FEATURES_MASK_OFST 0 6668 #define LICENSED_FEATURES_MASK_LEN 8 6669 #define LICENSED_FEATURES_MASK_LO_OFST 0 6670 #define LICENSED_FEATURES_MASK_HI_OFST 4 6671 #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0 6672 #define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1 6673 #define LICENSED_FEATURES_PIO_LBN 1 6674 #define LICENSED_FEATURES_PIO_WIDTH 1 6675 #define LICENSED_FEATURES_EVQ_TIMER_LBN 2 6676 #define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1 6677 #define LICENSED_FEATURES_CLOCK_LBN 3 6678 #define LICENSED_FEATURES_CLOCK_WIDTH 1 6679 #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4 6680 #define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1 6681 #define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5 6682 #define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1 6683 #define LICENSED_FEATURES_RX_SNIFF_LBN 6 6684 #define LICENSED_FEATURES_RX_SNIFF_WIDTH 1 6685 #define LICENSED_FEATURES_TX_SNIFF_LBN 7 6686 #define LICENSED_FEATURES_TX_SNIFF_WIDTH 1 6687 #define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8 6688 #define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1 6689 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9 6690 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 6691 #define LICENSED_FEATURES_MASK_LBN 0 6692 #define LICENSED_FEATURES_MASK_WIDTH 64 6693 6694 /* LICENSED_V3_APPS structuredef */ 6695 #define LICENSED_V3_APPS_LEN 8 6696 /* Bitmask of licensed applications */ 6697 #define LICENSED_V3_APPS_MASK_OFST 0 6698 #define LICENSED_V3_APPS_MASK_LEN 8 6699 #define LICENSED_V3_APPS_MASK_LO_OFST 0 6700 #define LICENSED_V3_APPS_MASK_HI_OFST 4 6701 #define LICENSED_V3_APPS_ONLOAD_LBN 0 6702 #define LICENSED_V3_APPS_ONLOAD_WIDTH 1 6703 #define LICENSED_V3_APPS_PTP_LBN 1 6704 #define LICENSED_V3_APPS_PTP_WIDTH 1 6705 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2 6706 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1 6707 #define LICENSED_V3_APPS_SOLARSECURE_LBN 3 6708 #define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1 6709 #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4 6710 #define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1 6711 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5 6712 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1 6713 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6 6714 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1 6715 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7 6716 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1 6717 #define LICENSED_V3_APPS_TCP_DIRECT_LBN 8 6718 #define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1 6719 #define LICENSED_V3_APPS_LOW_LATENCY_LBN 9 6720 #define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1 6721 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10 6722 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1 6723 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11 6724 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1 6725 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12 6726 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1 6727 #define LICENSED_V3_APPS_SCALEOUT_ONLOAD_LBN 13 6728 #define LICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 1 6729 #define LICENSED_V3_APPS_DSHBRD_LBN 14 6730 #define LICENSED_V3_APPS_DSHBRD_WIDTH 1 6731 #define LICENSED_V3_APPS_SCATRD_LBN 15 6732 #define LICENSED_V3_APPS_SCATRD_WIDTH 1 6733 #define LICENSED_V3_APPS_MASK_LBN 0 6734 #define LICENSED_V3_APPS_MASK_WIDTH 64 6735 6736 /* LICENSED_V3_FEATURES structuredef */ 6737 #define LICENSED_V3_FEATURES_LEN 8 6738 /* Bitmask of licensed firmware features */ 6739 #define LICENSED_V3_FEATURES_MASK_OFST 0 6740 #define LICENSED_V3_FEATURES_MASK_LEN 8 6741 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0 6742 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4 6743 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0 6744 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1 6745 #define LICENSED_V3_FEATURES_PIO_LBN 1 6746 #define LICENSED_V3_FEATURES_PIO_WIDTH 1 6747 #define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2 6748 #define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1 6749 #define LICENSED_V3_FEATURES_CLOCK_LBN 3 6750 #define LICENSED_V3_FEATURES_CLOCK_WIDTH 1 6751 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4 6752 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1 6753 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5 6754 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1 6755 #define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6 6756 #define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1 6757 #define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7 6758 #define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1 6759 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8 6760 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1 6761 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9 6762 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 6763 #define LICENSED_V3_FEATURES_MASK_LBN 0 6764 #define LICENSED_V3_FEATURES_MASK_WIDTH 64 6765 6766 /* TX_TIMESTAMP_EVENT structuredef */ 6767 #define TX_TIMESTAMP_EVENT_LEN 6 6768 /* lower 16 bits of timestamp data */ 6769 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0 6770 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2 6771 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0 6772 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16 6773 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp 6774 */ 6775 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3 6776 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1 6777 /* enum: This is a TX completion event, not a timestamp */ 6778 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0 6779 /* enum: This is a TX completion event for a CTPIO transmit. The event format 6780 * is the same as for TX_EV_COMPLETION. 6781 */ 6782 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11 6783 /* enum: This is the low part of a TX timestamp for a CTPIO transmission. The 6784 * event format is the same as for TX_EV_TSTAMP_LO 6785 */ 6786 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12 6787 /* enum: This is the high part of a TX timestamp for a CTPIO transmission. The 6788 * event format is the same as for TX_EV_TSTAMP_HI 6789 */ 6790 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13 6791 /* enum: This is the low part of a TX timestamp event */ 6792 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51 6793 /* enum: This is the high part of a TX timestamp event */ 6794 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52 6795 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24 6796 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8 6797 /* upper 16 bits of timestamp data */ 6798 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4 6799 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2 6800 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32 6801 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16 6802 6803 /* RSS_MODE structuredef */ 6804 #define RSS_MODE_LEN 1 6805 /* The RSS mode for a particular packet type is a value from 0 - 15 which can 6806 * be considered as 4 bits selecting which fields are included in the hash. (A 6807 * value 0 effectively disables RSS spreading for the packet type.) The YAML 6808 * generation tools require this structure to be a whole number of bytes wide, 6809 * but only 4 bits are relevant. 6810 */ 6811 #define RSS_MODE_HASH_SELECTOR_OFST 0 6812 #define RSS_MODE_HASH_SELECTOR_LEN 1 6813 #define RSS_MODE_HASH_SRC_ADDR_LBN 0 6814 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1 6815 #define RSS_MODE_HASH_DST_ADDR_LBN 1 6816 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1 6817 #define RSS_MODE_HASH_SRC_PORT_LBN 2 6818 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1 6819 #define RSS_MODE_HASH_DST_PORT_LBN 3 6820 #define RSS_MODE_HASH_DST_PORT_WIDTH 1 6821 #define RSS_MODE_HASH_SELECTOR_LBN 0 6822 #define RSS_MODE_HASH_SELECTOR_WIDTH 8 6823 6824 /* CTPIO_STATS_MAP structuredef */ 6825 #define CTPIO_STATS_MAP_LEN 4 6826 /* The (function relative) VI number */ 6827 #define CTPIO_STATS_MAP_VI_OFST 0 6828 #define CTPIO_STATS_MAP_VI_LEN 2 6829 #define CTPIO_STATS_MAP_VI_LBN 0 6830 #define CTPIO_STATS_MAP_VI_WIDTH 16 6831 /* The target bucket for the VI */ 6832 #define CTPIO_STATS_MAP_BUCKET_OFST 2 6833 #define CTPIO_STATS_MAP_BUCKET_LEN 2 6834 #define CTPIO_STATS_MAP_BUCKET_LBN 16 6835 #define CTPIO_STATS_MAP_BUCKET_WIDTH 16 6836 6837 6838 /***********************************/ 6839 /* MC_CMD_READ_REGS 6840 * Get a dump of the MCPU registers 6841 */ 6842 #define MC_CMD_READ_REGS 0x50 6843 6844 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE 6845 6846 /* MC_CMD_READ_REGS_IN msgrequest */ 6847 #define MC_CMD_READ_REGS_IN_LEN 0 6848 6849 /* MC_CMD_READ_REGS_OUT msgresponse */ 6850 #define MC_CMD_READ_REGS_OUT_LEN 308 6851 /* Whether the corresponding register entry contains a valid value */ 6852 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 6853 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 6854 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, 6855 * fir, fp) 6856 */ 6857 #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 6858 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 6859 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 6860 6861 6862 /***********************************/ 6863 /* MC_CMD_INIT_EVQ 6864 * Set up an event queue according to the supplied parameters. The IN arguments 6865 * end with an address for each 4k of host memory required to back the EVQ. 6866 */ 6867 #define MC_CMD_INIT_EVQ 0x80 6868 6869 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6870 6871 /* MC_CMD_INIT_EVQ_IN msgrequest */ 6872 #define MC_CMD_INIT_EVQ_IN_LENMIN 44 6873 #define MC_CMD_INIT_EVQ_IN_LENMAX 548 6874 #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) 6875 /* Size, in entries */ 6876 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 6877 #define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4 6878 /* Desired instance. Must be set to a specific instance, which is a function 6879 * local queue index. 6880 */ 6881 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 6882 #define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4 6883 /* The initial timer value. The load value is ignored if the timer mode is DIS. 6884 */ 6885 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 6886 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4 6887 /* The reload value is ignored in one-shot modes */ 6888 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 6889 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4 6890 /* tbd */ 6891 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 6892 #define MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4 6893 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 6894 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 6895 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 6896 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 6897 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 6898 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 6899 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 6900 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 6901 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 6902 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 6903 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 6904 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 6905 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6 6906 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1 6907 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 6908 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4 6909 /* enum: Disabled */ 6910 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 6911 /* enum: Immediate */ 6912 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 6913 /* enum: Triggered */ 6914 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 6915 /* enum: Hold-off */ 6916 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 6917 /* Target EVQ for wakeups if in wakeup mode. */ 6918 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 6919 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4 6920 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 6921 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 6922 * purposes. 6923 */ 6924 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 6925 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4 6926 /* Event Counter Mode. */ 6927 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 6928 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4 6929 /* enum: Disabled */ 6930 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 6931 /* enum: Disabled */ 6932 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 6933 /* enum: Disabled */ 6934 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 6935 /* enum: Disabled */ 6936 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 6937 /* Event queue packet count threshold. */ 6938 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 6939 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4 6940 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 6941 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 6942 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 6943 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 6944 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 6945 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 6946 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 6947 6948 /* MC_CMD_INIT_EVQ_OUT msgresponse */ 6949 #define MC_CMD_INIT_EVQ_OUT_LEN 4 6950 /* Only valid if INTRFLAG was true */ 6951 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 6952 #define MC_CMD_INIT_EVQ_OUT_IRQ_LEN 4 6953 6954 /* MC_CMD_INIT_EVQ_V2_IN msgrequest */ 6955 #define MC_CMD_INIT_EVQ_V2_IN_LENMIN 44 6956 #define MC_CMD_INIT_EVQ_V2_IN_LENMAX 548 6957 #define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num)) 6958 /* Size, in entries */ 6959 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0 6960 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4 6961 /* Desired instance. Must be set to a specific instance, which is a function 6962 * local queue index. 6963 */ 6964 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4 6965 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4 6966 /* The initial timer value. The load value is ignored if the timer mode is DIS. 6967 */ 6968 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8 6969 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4 6970 /* The reload value is ignored in one-shot modes */ 6971 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12 6972 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4 6973 /* tbd */ 6974 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16 6975 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4 6976 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0 6977 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1 6978 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1 6979 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1 6980 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2 6981 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1 6982 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3 6983 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1 6984 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4 6985 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1 6986 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5 6987 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1 6988 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6 6989 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1 6990 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7 6991 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4 6992 /* enum: All initialisation flags specified by host. */ 6993 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0 6994 /* enum: MEDFORD only. Certain initialisation flags specified by host may be 6995 * over-ridden by firmware based on licenses and firmware variant in order to 6996 * provide the lowest latency achievable. See 6997 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 6998 */ 6999 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1 7000 /* enum: MEDFORD only. Certain initialisation flags specified by host may be 7001 * over-ridden by firmware based on licenses and firmware variant in order to 7002 * provide the best throughput achievable. See 7003 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 7004 */ 7005 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2 7006 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by 7007 * firmware based on licenses and firmware variant. See 7008 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 7009 */ 7010 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3 7011 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20 7012 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4 7013 /* enum: Disabled */ 7014 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0 7015 /* enum: Immediate */ 7016 #define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1 7017 /* enum: Triggered */ 7018 #define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2 7019 /* enum: Hold-off */ 7020 #define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3 7021 /* Target EVQ for wakeups if in wakeup mode. */ 7022 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24 7023 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4 7024 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 7025 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 7026 * purposes. 7027 */ 7028 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24 7029 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4 7030 /* Event Counter Mode. */ 7031 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28 7032 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4 7033 /* enum: Disabled */ 7034 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0 7035 /* enum: Disabled */ 7036 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1 7037 /* enum: Disabled */ 7038 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2 7039 /* enum: Disabled */ 7040 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3 7041 /* Event queue packet count threshold. */ 7042 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32 7043 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4 7044 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7045 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36 7046 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8 7047 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36 7048 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40 7049 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1 7050 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64 7051 7052 /* MC_CMD_INIT_EVQ_V2_OUT msgresponse */ 7053 #define MC_CMD_INIT_EVQ_V2_OUT_LEN 8 7054 /* Only valid if INTRFLAG was true */ 7055 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0 7056 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4 7057 /* Actual configuration applied on the card */ 7058 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4 7059 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4 7060 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0 7061 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1 7062 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1 7063 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1 7064 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2 7065 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1 7066 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3 7067 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1 7068 7069 /* QUEUE_CRC_MODE structuredef */ 7070 #define QUEUE_CRC_MODE_LEN 1 7071 #define QUEUE_CRC_MODE_MODE_LBN 0 7072 #define QUEUE_CRC_MODE_MODE_WIDTH 4 7073 /* enum: No CRC. */ 7074 #define QUEUE_CRC_MODE_NONE 0x0 7075 /* enum: CRC Fiber channel over ethernet. */ 7076 #define QUEUE_CRC_MODE_FCOE 0x1 7077 /* enum: CRC (digest) iSCSI header only. */ 7078 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 7079 /* enum: CRC (digest) iSCSI header and payload. */ 7080 #define QUEUE_CRC_MODE_ISCSI 0x3 7081 /* enum: CRC Fiber channel over IP over ethernet. */ 7082 #define QUEUE_CRC_MODE_FCOIPOE 0x4 7083 /* enum: CRC MPA. */ 7084 #define QUEUE_CRC_MODE_MPA 0x5 7085 #define QUEUE_CRC_MODE_SPARE_LBN 4 7086 #define QUEUE_CRC_MODE_SPARE_WIDTH 4 7087 7088 7089 /***********************************/ 7090 /* MC_CMD_INIT_RXQ 7091 * set up a receive queue according to the supplied parameters. The IN 7092 * arguments end with an address for each 4k of host memory required to back 7093 * the RXQ. 7094 */ 7095 #define MC_CMD_INIT_RXQ 0x81 7096 7097 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7098 7099 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version 7100 * in new code. 7101 */ 7102 #define MC_CMD_INIT_RXQ_IN_LENMIN 36 7103 #define MC_CMD_INIT_RXQ_IN_LENMAX 252 7104 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) 7105 /* Size, in entries */ 7106 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 7107 #define MC_CMD_INIT_RXQ_IN_SIZE_LEN 4 7108 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 7109 */ 7110 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 7111 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4 7112 /* The value to put in the event data. Check hardware spec. for valid range. */ 7113 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 7114 #define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4 7115 /* Desired instance. Must be set to a specific instance, which is a function 7116 * local queue index. 7117 */ 7118 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 7119 #define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4 7120 /* There will be more flags here. */ 7121 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 7122 #define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4 7123 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 7124 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 7125 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 7126 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 7127 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 7128 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 7129 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 7130 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 7131 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 7132 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 7133 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 7134 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 7135 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 7136 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 7137 #define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10 7138 #define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1 7139 /* Owner ID to use if in buffer mode (zero if physical) */ 7140 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 7141 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4 7142 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7143 #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 7144 #define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4 7145 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7146 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 7147 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 7148 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 7149 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 7150 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 7151 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 7152 7153 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode 7154 * flags 7155 */ 7156 #define MC_CMD_INIT_RXQ_EXT_IN_LEN 544 7157 /* Size, in entries */ 7158 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0 7159 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4 7160 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 7161 */ 7162 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4 7163 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4 7164 /* The value to put in the event data. Check hardware spec. for valid range. */ 7165 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8 7166 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4 7167 /* Desired instance. Must be set to a specific instance, which is a function 7168 * local queue index. 7169 */ 7170 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12 7171 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4 7172 /* There will be more flags here. */ 7173 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16 7174 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4 7175 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 7176 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 7177 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1 7178 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1 7179 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2 7180 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 7181 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3 7182 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4 7183 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7 7184 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1 7185 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8 7186 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1 7187 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9 7188 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1 7189 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10 7190 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4 7191 /* enum: One packet per descriptor (for normal networking) */ 7192 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0 7193 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 7194 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1 7195 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14 7196 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 7197 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 7198 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 7199 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */ 7200 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */ 7201 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */ 7202 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */ 7203 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ 7204 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 7205 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 7206 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19 7207 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 7208 /* Owner ID to use if in buffer mode (zero if physical) */ 7209 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 7210 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4 7211 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7212 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24 7213 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4 7214 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7215 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28 7216 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8 7217 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28 7218 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32 7219 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64 7220 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 7221 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540 7222 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4 7223 7224 /* MC_CMD_INIT_RXQ_OUT msgresponse */ 7225 #define MC_CMD_INIT_RXQ_OUT_LEN 0 7226 7227 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */ 7228 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0 7229 7230 7231 /***********************************/ 7232 /* MC_CMD_INIT_TXQ 7233 */ 7234 #define MC_CMD_INIT_TXQ 0x82 7235 7236 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7237 7238 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version 7239 * in new code. 7240 */ 7241 #define MC_CMD_INIT_TXQ_IN_LENMIN 36 7242 #define MC_CMD_INIT_TXQ_IN_LENMAX 252 7243 #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) 7244 /* Size, in entries */ 7245 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 7246 #define MC_CMD_INIT_TXQ_IN_SIZE_LEN 4 7247 /* The EVQ to send events to. This is an index originally specified to 7248 * INIT_EVQ. 7249 */ 7250 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 7251 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4 7252 /* The value to put in the event data. Check hardware spec. for valid range. */ 7253 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 7254 #define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4 7255 /* Desired instance. Must be set to a specific instance, which is a function 7256 * local queue index. 7257 */ 7258 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 7259 #define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4 7260 /* There will be more flags here. */ 7261 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 7262 #define MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4 7263 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 7264 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 7265 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 7266 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 7267 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 7268 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 7269 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 7270 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 7271 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 7272 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 7273 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 7274 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 7275 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 7276 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 7277 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 7278 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 7279 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 7280 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 7281 /* Owner ID to use if in buffer mode (zero if physical) */ 7282 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 7283 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4 7284 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7285 #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 7286 #define MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4 7287 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7288 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 7289 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 7290 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 7291 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 7292 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 7293 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 7294 7295 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode 7296 * flags 7297 */ 7298 #define MC_CMD_INIT_TXQ_EXT_IN_LEN 544 7299 /* Size, in entries */ 7300 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0 7301 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4 7302 /* The EVQ to send events to. This is an index originally specified to 7303 * INIT_EVQ. 7304 */ 7305 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4 7306 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4 7307 /* The value to put in the event data. Check hardware spec. for valid range. */ 7308 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8 7309 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4 7310 /* Desired instance. Must be set to a specific instance, which is a function 7311 * local queue index. 7312 */ 7313 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12 7314 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4 7315 /* There will be more flags here. */ 7316 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16 7317 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4 7318 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 7319 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 7320 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1 7321 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1 7322 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2 7323 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 7324 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3 7325 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 7326 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4 7327 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4 7328 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8 7329 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 7330 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9 7331 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1 7332 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 7333 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 7334 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 7335 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 7336 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12 7337 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1 7338 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13 7339 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1 7340 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_LBN 14 7341 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_WIDTH 1 7342 /* Owner ID to use if in buffer mode (zero if physical) */ 7343 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 7344 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4 7345 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7346 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24 7347 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4 7348 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7349 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28 7350 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8 7351 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28 7352 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32 7353 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1 7354 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64 7355 /* Flags related to Qbb flow control mode. */ 7356 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540 7357 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4 7358 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0 7359 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1 7360 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1 7361 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3 7362 7363 /* MC_CMD_INIT_TXQ_OUT msgresponse */ 7364 #define MC_CMD_INIT_TXQ_OUT_LEN 0 7365 7366 7367 /***********************************/ 7368 /* MC_CMD_FINI_EVQ 7369 * Teardown an EVQ. 7370 * 7371 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first 7372 * or the operation will fail with EBUSY 7373 */ 7374 #define MC_CMD_FINI_EVQ 0x83 7375 7376 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7377 7378 /* MC_CMD_FINI_EVQ_IN msgrequest */ 7379 #define MC_CMD_FINI_EVQ_IN_LEN 4 7380 /* Instance of EVQ to destroy. Should be the same instance as that previously 7381 * passed to INIT_EVQ 7382 */ 7383 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 7384 #define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4 7385 7386 /* MC_CMD_FINI_EVQ_OUT msgresponse */ 7387 #define MC_CMD_FINI_EVQ_OUT_LEN 0 7388 7389 7390 /***********************************/ 7391 /* MC_CMD_FINI_RXQ 7392 * Teardown a RXQ. 7393 */ 7394 #define MC_CMD_FINI_RXQ 0x84 7395 7396 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7397 7398 /* MC_CMD_FINI_RXQ_IN msgrequest */ 7399 #define MC_CMD_FINI_RXQ_IN_LEN 4 7400 /* Instance of RXQ to destroy */ 7401 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 7402 #define MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4 7403 7404 /* MC_CMD_FINI_RXQ_OUT msgresponse */ 7405 #define MC_CMD_FINI_RXQ_OUT_LEN 0 7406 7407 7408 /***********************************/ 7409 /* MC_CMD_FINI_TXQ 7410 * Teardown a TXQ. 7411 */ 7412 #define MC_CMD_FINI_TXQ 0x85 7413 7414 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7415 7416 /* MC_CMD_FINI_TXQ_IN msgrequest */ 7417 #define MC_CMD_FINI_TXQ_IN_LEN 4 7418 /* Instance of TXQ to destroy */ 7419 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 7420 #define MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4 7421 7422 /* MC_CMD_FINI_TXQ_OUT msgresponse */ 7423 #define MC_CMD_FINI_TXQ_OUT_LEN 0 7424 7425 7426 /***********************************/ 7427 /* MC_CMD_DRIVER_EVENT 7428 * Generate an event on an EVQ belonging to the function issuing the command. 7429 */ 7430 #define MC_CMD_DRIVER_EVENT 0x86 7431 7432 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7433 7434 /* MC_CMD_DRIVER_EVENT_IN msgrequest */ 7435 #define MC_CMD_DRIVER_EVENT_IN_LEN 12 7436 /* Handle of target EVQ */ 7437 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 7438 #define MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4 7439 /* Bits 0 - 63 of event */ 7440 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 7441 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 7442 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 7443 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 7444 7445 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ 7446 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 7447 7448 7449 /***********************************/ 7450 /* MC_CMD_PROXY_CMD 7451 * Execute an arbitrary MCDI command on behalf of a different function, subject 7452 * to security restrictions. The command to be proxied follows immediately 7453 * afterward in the host buffer (or on the UART). This command supercedes 7454 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. 7455 */ 7456 #define MC_CMD_PROXY_CMD 0x5b 7457 7458 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7459 7460 /* MC_CMD_PROXY_CMD_IN msgrequest */ 7461 #define MC_CMD_PROXY_CMD_IN_LEN 4 7462 /* The handle of the target function. */ 7463 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 7464 #define MC_CMD_PROXY_CMD_IN_TARGET_LEN 4 7465 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 7466 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 7467 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 7468 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 7469 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ 7470 7471 /* MC_CMD_PROXY_CMD_OUT msgresponse */ 7472 #define MC_CMD_PROXY_CMD_OUT_LEN 0 7473 7474 /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to 7475 * manage proxied requests 7476 */ 7477 #define MC_PROXY_STATUS_BUFFER_LEN 16 7478 /* Handle allocated by the firmware for this proxy transaction */ 7479 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0 7480 #define MC_PROXY_STATUS_BUFFER_HANDLE_LEN 4 7481 /* enum: An invalid handle. */ 7482 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0 7483 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0 7484 #define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32 7485 /* The requesting physical function number */ 7486 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4 7487 #define MC_PROXY_STATUS_BUFFER_PF_LEN 2 7488 #define MC_PROXY_STATUS_BUFFER_PF_LBN 32 7489 #define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16 7490 /* The requesting virtual function number. Set to VF_NULL if the target is a 7491 * PF. 7492 */ 7493 #define MC_PROXY_STATUS_BUFFER_VF_OFST 6 7494 #define MC_PROXY_STATUS_BUFFER_VF_LEN 2 7495 #define MC_PROXY_STATUS_BUFFER_VF_LBN 48 7496 #define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16 7497 /* The target function RID. */ 7498 #define MC_PROXY_STATUS_BUFFER_RID_OFST 8 7499 #define MC_PROXY_STATUS_BUFFER_RID_LEN 2 7500 #define MC_PROXY_STATUS_BUFFER_RID_LBN 64 7501 #define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16 7502 /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */ 7503 #define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10 7504 #define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2 7505 #define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80 7506 #define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16 7507 /* If a request is authorized rather than carried out by the host, this is the 7508 * elevated privilege mask granted to the requesting function. 7509 */ 7510 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12 7511 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LEN 4 7512 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 7513 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 7514 7515 7516 /***********************************/ 7517 /* MC_CMD_PROXY_CONFIGURE 7518 * Enable/disable authorization of MCDI requests from unprivileged functions by 7519 * a designated admin function 7520 */ 7521 #define MC_CMD_PROXY_CONFIGURE 0x58 7522 7523 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7524 7525 /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */ 7526 #define MC_CMD_PROXY_CONFIGURE_IN_LEN 108 7527 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0 7528 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 4 7529 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0 7530 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1 7531 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7532 * of blocks, each of the size REQUEST_BLOCK_SIZE. 7533 */ 7534 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4 7535 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8 7536 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4 7537 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8 7538 /* Must be a power of 2 */ 7539 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12 7540 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4 7541 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7542 * of blocks, each of the size REPLY_BLOCK_SIZE. 7543 */ 7544 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16 7545 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8 7546 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16 7547 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20 7548 /* Must be a power of 2 */ 7549 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24 7550 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4 7551 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7552 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 7553 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 7554 */ 7555 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28 7556 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8 7557 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28 7558 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32 7559 /* Must be a power of 2, or zero if this buffer is not provided */ 7560 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36 7561 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4 7562 /* Applies to all three buffers */ 7563 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40 7564 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_LEN 4 7565 /* A bit mask defining which MCDI operations may be proxied */ 7566 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 7567 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 7568 7569 /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */ 7570 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112 7571 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0 7572 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 4 7573 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0 7574 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1 7575 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7576 * of blocks, each of the size REQUEST_BLOCK_SIZE. 7577 */ 7578 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4 7579 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8 7580 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4 7581 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8 7582 /* Must be a power of 2 */ 7583 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12 7584 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4 7585 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7586 * of blocks, each of the size REPLY_BLOCK_SIZE. 7587 */ 7588 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16 7589 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8 7590 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16 7591 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20 7592 /* Must be a power of 2 */ 7593 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24 7594 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4 7595 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7596 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 7597 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 7598 */ 7599 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28 7600 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8 7601 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28 7602 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32 7603 /* Must be a power of 2, or zero if this buffer is not provided */ 7604 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36 7605 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4 7606 /* Applies to all three buffers */ 7607 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40 7608 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_LEN 4 7609 /* A bit mask defining which MCDI operations may be proxied */ 7610 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44 7611 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64 7612 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108 7613 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_LEN 4 7614 7615 /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ 7616 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 7617 7618 7619 /***********************************/ 7620 /* MC_CMD_PROXY_COMPLETE 7621 * Tells FW that a requested proxy operation has either been completed (by 7622 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the 7623 * function that enabled proxying/authorization (by using 7624 * MC_CMD_PROXY_CONFIGURE). 7625 */ 7626 #define MC_CMD_PROXY_COMPLETE 0x5f 7627 7628 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7629 7630 /* MC_CMD_PROXY_COMPLETE_IN msgrequest */ 7631 #define MC_CMD_PROXY_COMPLETE_IN_LEN 12 7632 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0 7633 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_LEN 4 7634 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4 7635 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_LEN 4 7636 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply 7637 * is stored in the REPLY_BUFF. 7638 */ 7639 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0 7640 /* enum: The operation has been authorized. The originating function may now 7641 * try again. 7642 */ 7643 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1 7644 /* enum: The operation has been declined. */ 7645 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2 7646 /* enum: The authorization failed because the relevant application did not 7647 * respond in time. 7648 */ 7649 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3 7650 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8 7651 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_LEN 4 7652 7653 /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ 7654 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 7655 7656 7657 /***********************************/ 7658 /* MC_CMD_ALLOC_BUFTBL_CHUNK 7659 * Allocate a set of buffer table entries using the specified owner ID. This 7660 * operation allocates the required buffer table entries (and fails if it 7661 * cannot do so). The buffer table entries will initially be zeroed. 7662 */ 7663 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 7664 7665 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 7666 7667 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 7668 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 7669 /* Owner ID to use */ 7670 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 7671 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4 7672 /* Size of buffer table pages to use, in bytes (note that only a few values are 7673 * legal on any specific hardware). 7674 */ 7675 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 7676 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4 7677 7678 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 7679 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 7680 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 7681 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 4 7682 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 7683 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 4 7684 /* Buffer table IDs for use in DMA descriptors. */ 7685 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 7686 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4 7687 7688 7689 /***********************************/ 7690 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES 7691 * Reprogram a set of buffer table entries in the specified chunk. 7692 */ 7693 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 7694 7695 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 7696 7697 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 7698 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 7699 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 7700 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 7701 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 7702 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4 7703 /* ID */ 7704 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 7705 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4 7706 /* Num entries */ 7707 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 7708 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4 7709 /* Buffer table entry address */ 7710 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 7711 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 7712 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 7713 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 7714 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 7715 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 7716 7717 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 7718 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 7719 7720 7721 /***********************************/ 7722 /* MC_CMD_FREE_BUFTBL_CHUNK 7723 */ 7724 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 7725 7726 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 7727 7728 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 7729 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 7730 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 7731 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 4 7732 7733 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 7734 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 7735 7736 7737 /***********************************/ 7738 /* MC_CMD_FILTER_OP 7739 * Multiplexed MCDI call for filter operations 7740 */ 7741 #define MC_CMD_FILTER_OP 0x8a 7742 7743 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7744 7745 /* MC_CMD_FILTER_OP_IN msgrequest */ 7746 #define MC_CMD_FILTER_OP_IN_LEN 108 7747 /* identifies the type of operation requested */ 7748 #define MC_CMD_FILTER_OP_IN_OP_OFST 0 7749 #define MC_CMD_FILTER_OP_IN_OP_LEN 4 7750 /* enum: single-recipient filter insert */ 7751 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 7752 /* enum: single-recipient filter remove */ 7753 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 7754 /* enum: multi-recipient filter subscribe */ 7755 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 7756 /* enum: multi-recipient filter unsubscribe */ 7757 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 7758 /* enum: replace one recipient with another (warning - the filter handle may 7759 * change) 7760 */ 7761 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 7762 /* filter handle (for remove / unsubscribe operations) */ 7763 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 7764 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 7765 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 7766 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 7767 /* The port ID associated with the v-adaptor which should contain this filter. 7768 */ 7769 #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 7770 #define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4 7771 /* fields to include in match criteria */ 7772 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 7773 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4 7774 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 7775 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 7776 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 7777 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 7778 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 7779 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 7780 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 7781 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 7782 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 7783 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 7784 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 7785 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 7786 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 7787 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 7788 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 7789 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 7790 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 7791 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 7792 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 7793 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 7794 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 7795 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 7796 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 7797 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 7798 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 7799 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 7800 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 7801 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 7802 /* receive destination */ 7803 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 7804 #define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4 7805 /* enum: drop packets */ 7806 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 7807 /* enum: receive to host */ 7808 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 7809 /* enum: receive to MC */ 7810 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 7811 /* enum: loop back to TXDP 0 */ 7812 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 7813 /* enum: loop back to TXDP 1 */ 7814 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 7815 /* receive queue handle (for multiple queue modes, this is the base queue) */ 7816 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 7817 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4 7818 /* receive mode */ 7819 #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 7820 #define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4 7821 /* enum: receive to just the specified queue */ 7822 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 7823 /* enum: receive to multiple queues using RSS context */ 7824 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 7825 /* enum: receive to multiple queues using .1p mapping */ 7826 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 7827 /* enum: install a filter entry that will never match; for test purposes only 7828 */ 7829 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 7830 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 7831 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 7832 * MC_CMD_DOT1P_MAPPING_ALLOC. 7833 */ 7834 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 7835 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4 7836 /* transmit domain (reserved; set to 0) */ 7837 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 7838 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4 7839 /* transmit destination (either set the MAC and/or PM bits for explicit 7840 * control, or set this field to TX_DEST_DEFAULT for sensible default 7841 * behaviour) 7842 */ 7843 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 7844 #define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4 7845 /* enum: request default behaviour (based on filter type) */ 7846 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff 7847 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 7848 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 7849 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 7850 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 7851 /* source MAC address to match (as bytes in network order) */ 7852 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 7853 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 7854 /* source port to match (as bytes in network order) */ 7855 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 7856 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 7857 /* destination MAC address to match (as bytes in network order) */ 7858 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 7859 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 7860 /* destination port to match (as bytes in network order) */ 7861 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 7862 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 7863 /* Ethernet type to match (as bytes in network order) */ 7864 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 7865 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 7866 /* Inner VLAN tag to match (as bytes in network order) */ 7867 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 7868 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 7869 /* Outer VLAN tag to match (as bytes in network order) */ 7870 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 7871 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 7872 /* IP protocol to match (in low byte; set high byte to 0) */ 7873 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 7874 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 7875 /* Firmware defined register 0 to match (reserved; set to 0) */ 7876 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 7877 #define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4 7878 /* Firmware defined register 1 to match (reserved; set to 0) */ 7879 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 7880 #define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4 7881 /* source IP address to match (as bytes in network order; set last 12 bytes to 7882 * 0 for IPv4 address) 7883 */ 7884 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 7885 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 7886 /* destination IP address to match (as bytes in network order; set last 12 7887 * bytes to 0 for IPv4 address) 7888 */ 7889 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 7890 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 7891 7892 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to 7893 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is 7894 * supported on Medford only). 7895 */ 7896 #define MC_CMD_FILTER_OP_EXT_IN_LEN 172 7897 /* identifies the type of operation requested */ 7898 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0 7899 #define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4 7900 /* Enum values, see field(s): */ 7901 /* MC_CMD_FILTER_OP_IN/OP */ 7902 /* filter handle (for remove / unsubscribe operations) */ 7903 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4 7904 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8 7905 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4 7906 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8 7907 /* The port ID associated with the v-adaptor which should contain this filter. 7908 */ 7909 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12 7910 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4 7911 /* fields to include in match criteria */ 7912 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16 7913 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4 7914 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0 7915 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1 7916 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1 7917 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1 7918 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2 7919 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1 7920 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3 7921 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1 7922 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4 7923 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1 7924 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5 7925 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1 7926 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6 7927 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1 7928 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7 7929 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1 7930 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8 7931 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1 7932 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9 7933 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1 7934 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10 7935 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1 7936 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11 7937 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1 7938 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12 7939 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1 7940 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13 7941 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1 7942 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14 7943 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 7944 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15 7945 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 7946 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16 7947 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1 7948 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17 7949 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1 7950 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 7951 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 7952 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19 7953 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 7954 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 7955 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 7956 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21 7957 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 7958 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22 7959 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1 7960 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23 7961 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1 7962 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 7963 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 7964 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 7965 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 7966 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 7967 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 7968 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 7969 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 7970 /* receive destination */ 7971 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20 7972 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4 7973 /* enum: drop packets */ 7974 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0 7975 /* enum: receive to host */ 7976 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1 7977 /* enum: receive to MC */ 7978 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2 7979 /* enum: loop back to TXDP 0 */ 7980 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3 7981 /* enum: loop back to TXDP 1 */ 7982 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4 7983 /* receive queue handle (for multiple queue modes, this is the base queue) */ 7984 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24 7985 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4 7986 /* receive mode */ 7987 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28 7988 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4 7989 /* enum: receive to just the specified queue */ 7990 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0 7991 /* enum: receive to multiple queues using RSS context */ 7992 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1 7993 /* enum: receive to multiple queues using .1p mapping */ 7994 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2 7995 /* enum: install a filter entry that will never match; for test purposes only 7996 */ 7997 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 7998 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 7999 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 8000 * MC_CMD_DOT1P_MAPPING_ALLOC. 8001 */ 8002 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32 8003 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4 8004 /* transmit domain (reserved; set to 0) */ 8005 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36 8006 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4 8007 /* transmit destination (either set the MAC and/or PM bits for explicit 8008 * control, or set this field to TX_DEST_DEFAULT for sensible default 8009 * behaviour) 8010 */ 8011 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40 8012 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4 8013 /* enum: request default behaviour (based on filter type) */ 8014 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff 8015 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0 8016 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1 8017 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1 8018 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1 8019 /* source MAC address to match (as bytes in network order) */ 8020 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44 8021 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6 8022 /* source port to match (as bytes in network order) */ 8023 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50 8024 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2 8025 /* destination MAC address to match (as bytes in network order) */ 8026 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52 8027 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6 8028 /* destination port to match (as bytes in network order) */ 8029 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58 8030 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2 8031 /* Ethernet type to match (as bytes in network order) */ 8032 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60 8033 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2 8034 /* Inner VLAN tag to match (as bytes in network order) */ 8035 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62 8036 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2 8037 /* Outer VLAN tag to match (as bytes in network order) */ 8038 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64 8039 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2 8040 /* IP protocol to match (in low byte; set high byte to 0) */ 8041 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66 8042 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2 8043 /* Firmware defined register 0 to match (reserved; set to 0) */ 8044 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68 8045 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4 8046 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP 8047 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for 8048 * VXLAN/NVGRE, or 1 for Geneve) 8049 */ 8050 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72 8051 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4 8052 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0 8053 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24 8054 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24 8055 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8 8056 /* enum: Match VXLAN traffic with this VNI */ 8057 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0 8058 /* enum: Match Geneve traffic with this VNI */ 8059 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1 8060 /* enum: Reserved for experimental development use */ 8061 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe 8062 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0 8063 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24 8064 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24 8065 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8 8066 /* enum: Match NVGRE traffic with this VSID */ 8067 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0 8068 /* source IP address to match (as bytes in network order; set last 12 bytes to 8069 * 0 for IPv4 address) 8070 */ 8071 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76 8072 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16 8073 /* destination IP address to match (as bytes in network order; set last 12 8074 * bytes to 0 for IPv4 address) 8075 */ 8076 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92 8077 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16 8078 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network 8079 * order) 8080 */ 8081 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108 8082 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6 8083 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ 8084 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114 8085 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2 8086 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in 8087 * network order) 8088 */ 8089 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116 8090 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6 8091 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network 8092 * order) 8093 */ 8094 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122 8095 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2 8096 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) 8097 */ 8098 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124 8099 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2 8100 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) 8101 */ 8102 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126 8103 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2 8104 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) 8105 */ 8106 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128 8107 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2 8108 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to 8109 * 0) 8110 */ 8111 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130 8112 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2 8113 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set 8114 * to 0) 8115 */ 8116 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132 8117 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4 8118 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set 8119 * to 0) 8120 */ 8121 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136 8122 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4 8123 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network 8124 * order; set last 12 bytes to 0 for IPv4 address) 8125 */ 8126 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140 8127 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16 8128 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network 8129 * order; set last 12 bytes to 0 for IPv4 address) 8130 */ 8131 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156 8132 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16 8133 8134 /* MC_CMD_FILTER_OP_OUT msgresponse */ 8135 #define MC_CMD_FILTER_OP_OUT_LEN 12 8136 /* identifies the type of operation requested */ 8137 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 8138 #define MC_CMD_FILTER_OP_OUT_OP_LEN 4 8139 /* Enum values, see field(s): */ 8140 /* MC_CMD_FILTER_OP_IN/OP */ 8141 /* Returned filter handle (for insert / subscribe operations). Note that these 8142 * handles should be considered opaque to the host, although a value of 8143 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 8144 */ 8145 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 8146 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 8147 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 8148 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 8149 /* enum: guaranteed invalid filter handle (low 32 bits) */ 8150 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff 8151 /* enum: guaranteed invalid filter handle (high 32 bits) */ 8152 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff 8153 8154 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */ 8155 #define MC_CMD_FILTER_OP_EXT_OUT_LEN 12 8156 /* identifies the type of operation requested */ 8157 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0 8158 #define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4 8159 /* Enum values, see field(s): */ 8160 /* MC_CMD_FILTER_OP_EXT_IN/OP */ 8161 /* Returned filter handle (for insert / subscribe operations). Note that these 8162 * handles should be considered opaque to the host, although a value of 8163 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 8164 */ 8165 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4 8166 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8 8167 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4 8168 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8 8169 /* Enum values, see field(s): */ 8170 /* MC_CMD_FILTER_OP_OUT/HANDLE */ 8171 8172 8173 /***********************************/ 8174 /* MC_CMD_GET_PARSER_DISP_INFO 8175 * Get information related to the parser-dispatcher subsystem 8176 */ 8177 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 8178 8179 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8180 8181 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ 8182 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 8183 /* identifies the type of operation requested */ 8184 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 8185 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4 8186 /* enum: read the list of supported RX filter matches */ 8187 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 8188 /* enum: read flags indicating restrictions on filter insertion for the calling 8189 * client 8190 */ 8191 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2 8192 /* enum: read properties relating to security rules (Medford-only; for use by 8193 * SolarSecure apps, not directly by drivers. See SF-114946-SW.) 8194 */ 8195 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3 8196 /* enum: read the list of supported RX filter matches for VXLAN/NVGRE 8197 * encapsulated frames, which follow a different match sequence to normal 8198 * frames (Medford only) 8199 */ 8200 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4 8201 8202 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ 8203 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 8204 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 8205 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) 8206 /* identifies the type of operation requested */ 8207 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 8208 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4 8209 /* Enum values, see field(s): */ 8210 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 8211 /* number of supported match types */ 8212 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 8213 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4 8214 /* array of supported match types (valid MATCH_FIELDS values for 8215 * MC_CMD_FILTER_OP) sorted in decreasing priority order 8216 */ 8217 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 8218 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 8219 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 8220 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 8221 8222 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */ 8223 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8 8224 /* identifies the type of operation requested */ 8225 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0 8226 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4 8227 /* Enum values, see field(s): */ 8228 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 8229 /* bitfield of filter insertion restrictions */ 8230 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4 8231 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4 8232 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0 8233 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1 8234 8235 8236 /***********************************/ 8237 /* MC_CMD_PARSER_DISP_RW 8238 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging. 8239 * Please note that this interface is only of use to debug tools which have 8240 * knowledge of firmware and hardware data structures; nothing here is intended 8241 * for use by normal driver code. 8242 */ 8243 #define MC_CMD_PARSER_DISP_RW 0xe5 8244 8245 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8246 8247 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ 8248 #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 8249 /* identifies the target of the operation */ 8250 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 8251 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_LEN 4 8252 /* enum: RX dispatcher CPU */ 8253 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 8254 /* enum: TX dispatcher CPU */ 8255 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 8256 /* enum: Lookup engine (with original metadata format). Deprecated; used only 8257 * by cmdclient as a fallback for very old Huntington firmware, and not 8258 * supported in firmware beyond v6.4.0.1005. Use LUE_VERSIONED_METADATA 8259 * instead. 8260 */ 8261 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 8262 /* enum: Lookup engine (with requested metadata format) */ 8263 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 8264 /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */ 8265 #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0 8266 /* enum: RX1 dispatcher CPU (only valid for Medford) */ 8267 #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4 8268 /* enum: Miscellaneous other state (only valid for Medford) */ 8269 #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5 8270 /* identifies the type of operation requested */ 8271 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 8272 #define MC_CMD_PARSER_DISP_RW_IN_OP_LEN 4 8273 /* enum: Read a word of DICPU DMEM or a LUE entry */ 8274 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 8275 /* enum: Write a word of DICPU DMEM or a LUE entry. */ 8276 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 8277 /* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). */ 8278 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 8279 /* data memory address (DICPU targets) or LUE index (LUE targets) */ 8280 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 8281 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_LEN 4 8282 /* selector (for MISC_STATE target) */ 8283 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8 8284 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_LEN 4 8285 /* enum: Port to datapath mapping */ 8286 #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1 8287 /* value to write (for DMEM writes) */ 8288 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 8289 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_LEN 4 8290 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 8291 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 8292 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_LEN 4 8293 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 8294 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 8295 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_LEN 4 8296 /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */ 8297 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12 8298 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_LEN 4 8299 /* value to write (for LUE writes) */ 8300 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 8301 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 8302 8303 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ 8304 #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 8305 /* value read (for DMEM reads) */ 8306 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 8307 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_LEN 4 8308 /* value read (for LUE reads) */ 8309 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 8310 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 8311 /* up to 8 32-bit words of additional soft state from the LUE manager (the 8312 * exact content is firmware-dependent and intended only for debug use) 8313 */ 8314 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 8315 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 8316 /* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */ 8317 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0 8318 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4 8319 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4 8320 #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */ 8321 #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */ 8322 8323 8324 /***********************************/ 8325 /* MC_CMD_GET_PF_COUNT 8326 * Get number of PFs on the device. 8327 */ 8328 #define MC_CMD_GET_PF_COUNT 0xb6 8329 8330 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8331 8332 /* MC_CMD_GET_PF_COUNT_IN msgrequest */ 8333 #define MC_CMD_GET_PF_COUNT_IN_LEN 0 8334 8335 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 8336 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 8337 /* Identifies the number of PFs on the device. */ 8338 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 8339 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 8340 8341 8342 /***********************************/ 8343 /* MC_CMD_SET_PF_COUNT 8344 * Set number of PFs on the device. 8345 */ 8346 #define MC_CMD_SET_PF_COUNT 0xb7 8347 8348 /* MC_CMD_SET_PF_COUNT_IN msgrequest */ 8349 #define MC_CMD_SET_PF_COUNT_IN_LEN 4 8350 /* New number of PFs on the device. */ 8351 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 8352 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_LEN 4 8353 8354 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 8355 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 8356 8357 8358 /***********************************/ 8359 /* MC_CMD_GET_PORT_ASSIGNMENT 8360 * Get port assignment for current PCI function. 8361 */ 8362 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 8363 8364 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8365 8366 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ 8367 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 8368 8369 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ 8370 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 8371 /* Identifies the port assignment for this function. */ 8372 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 8373 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4 8374 8375 8376 /***********************************/ 8377 /* MC_CMD_SET_PORT_ASSIGNMENT 8378 * Set port assignment for current PCI function. 8379 */ 8380 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 8381 8382 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8383 8384 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 8385 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 8386 /* Identifies the port assignment for this function. */ 8387 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 8388 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4 8389 8390 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 8391 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 8392 8393 8394 /***********************************/ 8395 /* MC_CMD_ALLOC_VIS 8396 * Allocate VIs for current PCI function. 8397 */ 8398 #define MC_CMD_ALLOC_VIS 0x8b 8399 8400 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8401 8402 /* MC_CMD_ALLOC_VIS_IN msgrequest */ 8403 #define MC_CMD_ALLOC_VIS_IN_LEN 8 8404 /* The minimum number of VIs that is acceptable */ 8405 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 8406 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4 8407 /* The maximum number of VIs that would be useful */ 8408 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 8409 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4 8410 8411 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request. 8412 * Use extended version in new code. 8413 */ 8414 #define MC_CMD_ALLOC_VIS_OUT_LEN 8 8415 /* The number of VIs allocated on this function */ 8416 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 8417 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4 8418 /* The base absolute VI number allocated to this function. Required to 8419 * correctly interpret wakeup events. 8420 */ 8421 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 8422 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4 8423 8424 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */ 8425 #define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12 8426 /* The number of VIs allocated on this function */ 8427 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0 8428 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4 8429 /* The base absolute VI number allocated to this function. Required to 8430 * correctly interpret wakeup events. 8431 */ 8432 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4 8433 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4 8434 /* Function's port vi_shift value (always 0 on Huntington) */ 8435 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 8436 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4 8437 8438 8439 /***********************************/ 8440 /* MC_CMD_FREE_VIS 8441 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, 8442 * but not freed. 8443 */ 8444 #define MC_CMD_FREE_VIS 0x8c 8445 8446 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8447 8448 /* MC_CMD_FREE_VIS_IN msgrequest */ 8449 #define MC_CMD_FREE_VIS_IN_LEN 0 8450 8451 /* MC_CMD_FREE_VIS_OUT msgresponse */ 8452 #define MC_CMD_FREE_VIS_OUT_LEN 0 8453 8454 8455 /***********************************/ 8456 /* MC_CMD_GET_SRIOV_CFG 8457 * Get SRIOV config for this PF. 8458 */ 8459 #define MC_CMD_GET_SRIOV_CFG 0xba 8460 8461 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8462 8463 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ 8464 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 8465 8466 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ 8467 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 8468 /* Number of VFs currently enabled. */ 8469 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 8470 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4 8471 /* Max number of VFs before sriov stride and offset may need to be changed. */ 8472 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 8473 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4 8474 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 8475 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4 8476 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 8477 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 8478 /* RID offset of first VF from PF. */ 8479 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 8480 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4 8481 /* RID offset of each subsequent VF from the previous. */ 8482 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 8483 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4 8484 8485 8486 /***********************************/ 8487 /* MC_CMD_SET_SRIOV_CFG 8488 * Set SRIOV config for this PF. 8489 */ 8490 #define MC_CMD_SET_SRIOV_CFG 0xbb 8491 8492 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8493 8494 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 8495 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 8496 /* Number of VFs currently enabled. */ 8497 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 8498 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4 8499 /* Max number of VFs before sriov stride and offset may need to be changed. */ 8500 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 8501 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4 8502 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 8503 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4 8504 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 8505 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 8506 /* RID offset of first VF from PF, or 0 for no change, or 8507 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. 8508 */ 8509 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 8510 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4 8511 /* RID offset of each subsequent VF from the previous, 0 for no change, or 8512 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. 8513 */ 8514 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 8515 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4 8516 8517 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 8518 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 8519 8520 8521 /***********************************/ 8522 /* MC_CMD_GET_VI_ALLOC_INFO 8523 * Get information about number of VI's and base VI number allocated to this 8524 * function. 8525 */ 8526 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d 8527 8528 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8529 8530 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ 8531 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 8532 8533 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ 8534 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 8535 /* The number of VIs allocated on this function */ 8536 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 8537 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4 8538 /* The base absolute VI number allocated to this function. Required to 8539 * correctly interpret wakeup events. 8540 */ 8541 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 8542 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4 8543 /* Function's port vi_shift value (always 0 on Huntington) */ 8544 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 8545 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4 8546 8547 8548 /***********************************/ 8549 /* MC_CMD_DUMP_VI_STATE 8550 * For CmdClient use. Dump pertinent information on a specific absolute VI. 8551 */ 8552 #define MC_CMD_DUMP_VI_STATE 0x8e 8553 8554 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8555 8556 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ 8557 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 8558 /* The VI number to query. */ 8559 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 8560 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4 8561 8562 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ 8563 #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 8564 /* The PF part of the function owning this VI. */ 8565 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 8566 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 8567 /* The VF part of the function owning this VI. */ 8568 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 8569 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 8570 /* Base of VIs allocated to this function. */ 8571 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 8572 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 8573 /* Count of VIs allocated to the owner function. */ 8574 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 8575 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 8576 /* Base interrupt vector allocated to this function. */ 8577 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 8578 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 8579 /* Number of interrupt vectors allocated to this function. */ 8580 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 8581 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 8582 /* Raw evq ptr table data. */ 8583 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 8584 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 8585 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 8586 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 8587 /* Raw evq timer table data. */ 8588 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 8589 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 8590 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 8591 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 8592 /* Combined metadata field. */ 8593 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 8594 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4 8595 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 8596 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 8597 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 8598 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 8599 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 8600 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 8601 /* TXDPCPU raw table data for queue. */ 8602 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 8603 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 8604 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 8605 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 8606 /* TXDPCPU raw table data for queue. */ 8607 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 8608 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 8609 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 8610 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 8611 /* TXDPCPU raw table data for queue. */ 8612 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 8613 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 8614 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 8615 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 8616 /* Combined metadata field. */ 8617 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 8618 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 8619 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 8620 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 8621 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 8622 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 8623 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 8624 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 8625 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 8626 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 8627 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 8628 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 8629 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 8630 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 8631 /* RXDPCPU raw table data for queue. */ 8632 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 8633 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 8634 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 8635 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 8636 /* RXDPCPU raw table data for queue. */ 8637 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 8638 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 8639 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 8640 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 8641 /* Reserved, currently 0. */ 8642 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 8643 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 8644 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 8645 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 8646 /* Combined metadata field. */ 8647 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 8648 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 8649 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 8650 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 8651 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 8652 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 8653 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 8654 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 8655 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 8656 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 8657 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 8658 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 8659 8660 8661 /***********************************/ 8662 /* MC_CMD_ALLOC_PIOBUF 8663 * Allocate a push I/O buffer for later use with a tx queue. 8664 */ 8665 #define MC_CMD_ALLOC_PIOBUF 0x8f 8666 8667 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8668 8669 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ 8670 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 8671 8672 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ 8673 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 8674 /* Handle for allocated push I/O buffer. */ 8675 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 8676 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4 8677 8678 8679 /***********************************/ 8680 /* MC_CMD_FREE_PIOBUF 8681 * Free a push I/O buffer. 8682 */ 8683 #define MC_CMD_FREE_PIOBUF 0x90 8684 8685 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8686 8687 /* MC_CMD_FREE_PIOBUF_IN msgrequest */ 8688 #define MC_CMD_FREE_PIOBUF_IN_LEN 4 8689 /* Handle for allocated push I/O buffer. */ 8690 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 8691 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4 8692 8693 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ 8694 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 8695 8696 8697 /***********************************/ 8698 /* MC_CMD_GET_VI_TLP_PROCESSING 8699 * Get TLP steering and ordering information for a VI. 8700 */ 8701 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 8702 8703 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8704 8705 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ 8706 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 8707 /* VI number to get information for. */ 8708 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 8709 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4 8710 8711 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ 8712 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 8713 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 8714 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 8715 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 8716 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 8717 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 8718 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 8719 /* Use Relaxed ordering model for TLPs on this VI. */ 8720 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 8721 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 8722 /* Use ID based ordering for TLPs on this VI. */ 8723 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 8724 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 8725 /* Set no snoop bit for TLPs on this VI. */ 8726 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 8727 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 8728 /* Enable TPH for TLPs on this VI. */ 8729 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 8730 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 8731 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 8732 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4 8733 8734 8735 /***********************************/ 8736 /* MC_CMD_SET_VI_TLP_PROCESSING 8737 * Set TLP steering and ordering information for a VI. 8738 */ 8739 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 8740 8741 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8742 8743 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ 8744 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 8745 /* VI number to set information for. */ 8746 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 8747 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4 8748 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 8749 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 8750 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 8751 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 8752 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 8753 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 8754 /* Use Relaxed ordering model for TLPs on this VI. */ 8755 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 8756 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 8757 /* Use ID based ordering for TLPs on this VI. */ 8758 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 8759 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 8760 /* Set the no snoop bit for TLPs on this VI. */ 8761 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 8762 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 8763 /* Enable TPH for TLPs on this VI. */ 8764 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 8765 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 8766 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 8767 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 4 8768 8769 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ 8770 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 8771 8772 8773 /***********************************/ 8774 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS 8775 * Get global PCIe steering and transaction processing configuration. 8776 */ 8777 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc 8778 8779 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8780 8781 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 8782 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 8783 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 8784 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4 8785 /* enum: MISC. */ 8786 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 8787 /* enum: IDO. */ 8788 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 8789 /* enum: RO. */ 8790 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 8791 /* enum: TPH Type. */ 8792 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 8793 8794 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 8795 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 8796 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 8797 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_LEN 4 8798 /* Enum values, see field(s): */ 8799 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 8800 /* Amalgamated TLP info word. */ 8801 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 8802 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 4 8803 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 8804 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 8805 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 8806 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 8807 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 8808 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 8809 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 8810 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 8811 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 8812 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 8813 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 8814 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 8815 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 8816 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 8817 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 8818 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 8819 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 8820 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 8821 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 8822 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 8823 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 8824 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 8825 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 8826 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 8827 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 8828 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 8829 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 8830 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 8831 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 8832 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 8833 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 8834 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 8835 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 8836 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 8837 8838 8839 /***********************************/ 8840 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS 8841 * Set global PCIe steering and transaction processing configuration. 8842 */ 8843 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd 8844 8845 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8846 8847 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 8848 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 8849 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 8850 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4 8851 /* Enum values, see field(s): */ 8852 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 8853 /* Amalgamated TLP info word. */ 8854 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 8855 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 4 8856 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 8857 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 8858 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 8859 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 8860 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 8861 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 8862 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 8863 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 8864 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 8865 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 8866 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 8867 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 8868 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 8869 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 8870 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 8871 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 8872 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 8873 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 8874 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 8875 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 8876 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 8877 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 8878 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 8879 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 8880 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 8881 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 8882 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 8883 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 8884 8885 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 8886 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 8887 8888 8889 /***********************************/ 8890 /* MC_CMD_SATELLITE_DOWNLOAD 8891 * Download a new set of images to the satellite CPUs from the host. 8892 */ 8893 #define MC_CMD_SATELLITE_DOWNLOAD 0x91 8894 8895 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8896 8897 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs 8898 * are subtle, and so downloads must proceed in a number of phases. 8899 * 8900 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. 8901 * 8902 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download 8903 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should 8904 * be a checksum (a simple 32-bit sum) of the transferred data. An individual 8905 * download may be aborted using CHUNK_ID_ABORT. 8906 * 8907 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), 8908 * similar to PHASE_IMEMS. 8909 * 8910 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. 8911 * 8912 * After any error (a requested abort is not considered to be an error) the 8913 * sequence must be restarted from PHASE_RESET. 8914 */ 8915 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 8916 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 8917 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) 8918 /* Download phase. (Note: the IDLE phase is used internally and is never valid 8919 * in a command from the host.) 8920 */ 8921 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 8922 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_LEN 4 8923 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ 8924 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ 8925 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ 8926 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ 8927 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ 8928 /* Target for download. (These match the blob numbers defined in 8929 * mc_flash_layout.h.) 8930 */ 8931 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 8932 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_LEN 4 8933 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8934 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 8935 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8936 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 8937 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8938 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 8939 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8940 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 8941 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8942 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 8943 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8944 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 8945 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8946 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 8947 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8948 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 8949 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8950 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 8951 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8952 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 8953 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8954 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa 8955 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8956 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb 8957 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 8958 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc 8959 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 8960 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd 8961 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 8962 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe 8963 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 8964 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf 8965 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ 8966 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff 8967 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ 8968 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 8969 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LEN 4 8970 /* enum: Last chunk, containing checksum rather than data */ 8971 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff 8972 /* enum: Abort download of this item */ 8973 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe 8974 /* Length of this chunk in bytes */ 8975 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 8976 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_LEN 4 8977 /* Data for this chunk */ 8978 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 8979 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 8980 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 8981 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 8982 8983 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ 8984 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 8985 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 8986 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 8987 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_LEN 4 8988 /* Extra status information */ 8989 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 8990 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_LEN 4 8991 /* enum: Code download OK, completed. */ 8992 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 8993 /* enum: Code download aborted as requested. */ 8994 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 8995 /* enum: Code download OK so far, send next chunk. */ 8996 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 8997 /* enum: Download phases out of sequence */ 8998 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 8999 /* enum: Bad target for this phase */ 9000 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 9001 /* enum: Chunk ID out of sequence */ 9002 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 9003 /* enum: Chunk length zero or too large */ 9004 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 9005 /* enum: Checksum was incorrect */ 9006 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 9007 9008 9009 /***********************************/ 9010 /* MC_CMD_GET_CAPABILITIES 9011 * Get device capabilities. 9012 * 9013 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to 9014 * reference inherent device capabilities as opposed to current NVRAM config. 9015 */ 9016 #define MC_CMD_GET_CAPABILITIES 0xbe 9017 9018 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9019 9020 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */ 9021 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0 9022 9023 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ 9024 #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 9025 /* First word of flags. */ 9026 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 9027 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4 9028 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3 9029 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1 9030 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4 9031 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1 9032 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5 9033 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1 9034 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 9035 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 9036 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7 9037 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 9038 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8 9039 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 9040 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9 9041 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1 9042 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 9043 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 9044 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 9045 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 9046 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 9047 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 9048 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13 9049 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 9050 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14 9051 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1 9052 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 9053 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 9054 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16 9055 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1 9056 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17 9057 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1 9058 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18 9059 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1 9060 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 9061 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 9062 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 9063 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 9064 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 9065 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 9066 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 9067 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 9068 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 9069 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 9070 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 9071 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 9072 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 9073 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 9074 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 9075 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 9076 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 9077 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 9078 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28 9079 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1 9080 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 9081 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 9082 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30 9083 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1 9084 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31 9085 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1 9086 /* RxDPCPU firmware id. */ 9087 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 9088 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 9089 /* enum: Standard RXDP firmware */ 9090 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 9091 /* enum: Low latency RXDP firmware */ 9092 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 9093 /* enum: Packed stream RXDP firmware */ 9094 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2 9095 /* enum: Rules engine RXDP firmware */ 9096 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5 9097 /* enum: BIST RXDP firmware */ 9098 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a 9099 /* enum: RXDP Test firmware image 1 */ 9100 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 9101 /* enum: RXDP Test firmware image 2 */ 9102 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 9103 /* enum: RXDP Test firmware image 3 */ 9104 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 9105 /* enum: RXDP Test firmware image 4 */ 9106 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 9107 /* enum: RXDP Test firmware image 5 */ 9108 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 9109 /* enum: RXDP Test firmware image 6 */ 9110 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 9111 /* enum: RXDP Test firmware image 7 */ 9112 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 9113 /* enum: RXDP Test firmware image 8 */ 9114 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 9115 /* enum: RXDP Test firmware image 9 */ 9116 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 9117 /* enum: RXDP Test firmware image 10 */ 9118 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c 9119 /* TxDPCPU firmware id. */ 9120 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 9121 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 9122 /* enum: Standard TXDP firmware */ 9123 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 9124 /* enum: Low latency TXDP firmware */ 9125 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 9126 /* enum: High packet rate TXDP firmware */ 9127 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3 9128 /* enum: Rules engine TXDP firmware */ 9129 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5 9130 /* enum: BIST TXDP firmware */ 9131 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d 9132 /* enum: TXDP Test firmware image 1 */ 9133 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 9134 /* enum: TXDP Test firmware image 2 */ 9135 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 9136 /* enum: TXDP CSR bus test firmware */ 9137 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103 9138 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 9139 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 9140 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 9141 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 9142 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 9143 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 9144 /* enum: reserved value - do not use (may indicate alternative interpretation 9145 * of REV field in future) 9146 */ 9147 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0 9148 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 9149 * development only) 9150 */ 9151 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 9152 /* enum: RX PD firmware with approximately Siena-compatible behaviour 9153 * (Huntington development only) 9154 */ 9155 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 9156 /* enum: Full featured RX PD production firmware */ 9157 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 9158 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 9159 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 9160 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 9161 * (Huntington development only) 9162 */ 9163 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9164 /* enum: Low latency RX PD production firmware */ 9165 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 9166 /* enum: Packed stream RX PD production firmware */ 9167 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 9168 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 9169 * tests (Medford development only) 9170 */ 9171 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 9172 /* enum: Rules engine RX PD production firmware */ 9173 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 9174 /* enum: reserved value - do not use (bug69716) */ 9175 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED_9 0x9 9176 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9177 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 9178 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 9179 * encapsulations (Medford development only) 9180 */ 9181 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 9182 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 9183 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 9184 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 9185 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 9186 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 9187 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 9188 /* enum: reserved value - do not use (may indicate alternative interpretation 9189 * of REV field in future) 9190 */ 9191 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0 9192 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 9193 * development only) 9194 */ 9195 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 9196 /* enum: TX PD firmware with approximately Siena-compatible behaviour 9197 * (Huntington development only) 9198 */ 9199 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 9200 /* enum: Full featured TX PD production firmware */ 9201 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 9202 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 9203 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 9204 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 9205 * (Huntington development only) 9206 */ 9207 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9208 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 9209 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 9210 * tests (Medford development only) 9211 */ 9212 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 9213 /* enum: Rules engine TX PD production firmware */ 9214 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 9215 /* enum: reserved value - do not use (bug69716) */ 9216 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED_9 0x9 9217 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9218 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 9219 /* Hardware capabilities of NIC */ 9220 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 9221 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4 9222 /* Licensed capabilities */ 9223 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 9224 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4 9225 9226 /* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */ 9227 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0 9228 9229 /* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */ 9230 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72 9231 /* First word of flags. */ 9232 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0 9233 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4 9234 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3 9235 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1 9236 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4 9237 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1 9238 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5 9239 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1 9240 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 9241 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 9242 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7 9243 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 9244 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8 9245 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 9246 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9 9247 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1 9248 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 9249 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 9250 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 9251 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 9252 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 9253 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 9254 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13 9255 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 9256 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14 9257 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1 9258 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 9259 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 9260 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16 9261 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1 9262 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17 9263 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1 9264 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18 9265 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1 9266 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19 9267 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1 9268 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20 9269 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1 9270 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21 9271 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1 9272 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22 9273 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1 9274 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23 9275 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1 9276 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24 9277 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1 9278 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25 9279 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1 9280 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26 9281 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1 9282 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27 9283 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 9284 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28 9285 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1 9286 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 9287 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 9288 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30 9289 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1 9290 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31 9291 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1 9292 /* RxDPCPU firmware id. */ 9293 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4 9294 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2 9295 /* enum: Standard RXDP firmware */ 9296 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0 9297 /* enum: Low latency RXDP firmware */ 9298 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1 9299 /* enum: Packed stream RXDP firmware */ 9300 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2 9301 /* enum: Rules engine RXDP firmware */ 9302 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5 9303 /* enum: BIST RXDP firmware */ 9304 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a 9305 /* enum: RXDP Test firmware image 1 */ 9306 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 9307 /* enum: RXDP Test firmware image 2 */ 9308 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 9309 /* enum: RXDP Test firmware image 3 */ 9310 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 9311 /* enum: RXDP Test firmware image 4 */ 9312 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 9313 /* enum: RXDP Test firmware image 5 */ 9314 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105 9315 /* enum: RXDP Test firmware image 6 */ 9316 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 9317 /* enum: RXDP Test firmware image 7 */ 9318 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 9319 /* enum: RXDP Test firmware image 8 */ 9320 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 9321 /* enum: RXDP Test firmware image 9 */ 9322 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 9323 /* enum: RXDP Test firmware image 10 */ 9324 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c 9325 /* TxDPCPU firmware id. */ 9326 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6 9327 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2 9328 /* enum: Standard TXDP firmware */ 9329 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0 9330 /* enum: Low latency TXDP firmware */ 9331 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1 9332 /* enum: High packet rate TXDP firmware */ 9333 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3 9334 /* enum: Rules engine TXDP firmware */ 9335 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5 9336 /* enum: BIST TXDP firmware */ 9337 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d 9338 /* enum: TXDP Test firmware image 1 */ 9339 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 9340 /* enum: TXDP Test firmware image 2 */ 9341 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 9342 /* enum: TXDP CSR bus test firmware */ 9343 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103 9344 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8 9345 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2 9346 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0 9347 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12 9348 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12 9349 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 9350 /* enum: reserved value - do not use (may indicate alternative interpretation 9351 * of REV field in future) 9352 */ 9353 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0 9354 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 9355 * development only) 9356 */ 9357 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 9358 /* enum: RX PD firmware with approximately Siena-compatible behaviour 9359 * (Huntington development only) 9360 */ 9361 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 9362 /* enum: Full featured RX PD production firmware */ 9363 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 9364 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 9365 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3 9366 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 9367 * (Huntington development only) 9368 */ 9369 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9370 /* enum: Low latency RX PD production firmware */ 9371 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 9372 /* enum: Packed stream RX PD production firmware */ 9373 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 9374 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 9375 * tests (Medford development only) 9376 */ 9377 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 9378 /* enum: Rules engine RX PD production firmware */ 9379 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 9380 /* enum: reserved value - do not use (bug69716) */ 9381 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED_9 0x9 9382 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9383 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 9384 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 9385 * encapsulations (Medford development only) 9386 */ 9387 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 9388 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10 9389 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2 9390 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0 9391 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12 9392 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12 9393 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 9394 /* enum: reserved value - do not use (may indicate alternative interpretation 9395 * of REV field in future) 9396 */ 9397 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0 9398 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 9399 * development only) 9400 */ 9401 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 9402 /* enum: TX PD firmware with approximately Siena-compatible behaviour 9403 * (Huntington development only) 9404 */ 9405 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 9406 /* enum: Full featured TX PD production firmware */ 9407 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 9408 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 9409 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3 9410 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 9411 * (Huntington development only) 9412 */ 9413 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9414 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 9415 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 9416 * tests (Medford development only) 9417 */ 9418 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 9419 /* enum: Rules engine TX PD production firmware */ 9420 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 9421 /* enum: reserved value - do not use (bug69716) */ 9422 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED_9 0x9 9423 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9424 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 9425 /* Hardware capabilities of NIC */ 9426 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12 9427 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4 9428 /* Licensed capabilities */ 9429 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16 9430 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4 9431 /* Second word of flags. Not present on older firmware (check the length). */ 9432 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20 9433 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4 9434 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0 9435 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1 9436 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1 9437 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1 9438 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2 9439 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1 9440 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3 9441 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1 9442 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4 9443 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1 9444 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5 9445 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 9446 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 9447 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 9448 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7 9449 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1 9450 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8 9451 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 9452 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9 9453 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1 9454 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10 9455 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1 9456 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11 9457 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1 9458 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 9459 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 9460 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 13 9461 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1 9462 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 14 9463 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1 9464 #define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_LBN 15 9465 #define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_WIDTH 1 9466 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_LBN 16 9467 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_WIDTH 1 9468 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_LBN 17 9469 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 1 9470 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 9471 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 9472 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 9473 * on older firmware (check the length). 9474 */ 9475 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 9476 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 9477 /* One byte per PF containing the number of the external port assigned to this 9478 * PF, indexed by PF number. Special values indicate that a PF is either not 9479 * present or not assigned. 9480 */ 9481 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 9482 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 9483 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 9484 /* enum: The caller is not permitted to access information on this PF. */ 9485 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff 9486 /* enum: PF does not exist. */ 9487 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe 9488 /* enum: PF does exist but is not assigned to any external port. */ 9489 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd 9490 /* enum: This value indicates that PF is assigned, but it cannot be expressed 9491 * in this field. It is intended for a possible future situation where a more 9492 * complex scheme of PFs to ports mapping is being used. The future driver 9493 * should look for a new field supporting the new scheme. The current/old 9494 * driver should treat this value as PF_NOT_ASSIGNED. 9495 */ 9496 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 9497 /* One byte per PF containing the number of its VFs, indexed by PF number. A 9498 * special value indicates that a PF is not present. 9499 */ 9500 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42 9501 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1 9502 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16 9503 /* enum: The caller is not permitted to access information on this PF. */ 9504 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */ 9505 /* enum: PF does not exist. */ 9506 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */ 9507 /* Number of VIs available for each external port */ 9508 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58 9509 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2 9510 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4 9511 /* Size of RX descriptor cache expressed as binary logarithm The actual size 9512 * equals (2 ^ RX_DESC_CACHE_SIZE) 9513 */ 9514 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66 9515 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1 9516 /* Size of TX descriptor cache expressed as binary logarithm The actual size 9517 * equals (2 ^ TX_DESC_CACHE_SIZE) 9518 */ 9519 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67 9520 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1 9521 /* Total number of available PIO buffers */ 9522 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68 9523 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2 9524 /* Size of a single PIO buffer */ 9525 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70 9526 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2 9527 9528 /* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */ 9529 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 76 9530 /* First word of flags. */ 9531 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0 9532 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4 9533 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3 9534 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1 9535 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4 9536 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1 9537 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5 9538 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1 9539 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 9540 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 9541 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7 9542 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 9543 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8 9544 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 9545 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9 9546 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1 9547 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 9548 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 9549 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 9550 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 9551 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 9552 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 9553 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13 9554 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 9555 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14 9556 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1 9557 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 9558 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 9559 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16 9560 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1 9561 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17 9562 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1 9563 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18 9564 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1 9565 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19 9566 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1 9567 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20 9568 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1 9569 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21 9570 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1 9571 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22 9572 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1 9573 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23 9574 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1 9575 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24 9576 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1 9577 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25 9578 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1 9579 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26 9580 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1 9581 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27 9582 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 9583 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28 9584 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1 9585 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 9586 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 9587 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30 9588 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1 9589 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31 9590 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1 9591 /* RxDPCPU firmware id. */ 9592 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4 9593 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2 9594 /* enum: Standard RXDP firmware */ 9595 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0 9596 /* enum: Low latency RXDP firmware */ 9597 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1 9598 /* enum: Packed stream RXDP firmware */ 9599 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2 9600 /* enum: Rules engine RXDP firmware */ 9601 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5 9602 /* enum: BIST RXDP firmware */ 9603 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a 9604 /* enum: RXDP Test firmware image 1 */ 9605 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 9606 /* enum: RXDP Test firmware image 2 */ 9607 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 9608 /* enum: RXDP Test firmware image 3 */ 9609 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 9610 /* enum: RXDP Test firmware image 4 */ 9611 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 9612 /* enum: RXDP Test firmware image 5 */ 9613 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105 9614 /* enum: RXDP Test firmware image 6 */ 9615 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 9616 /* enum: RXDP Test firmware image 7 */ 9617 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 9618 /* enum: RXDP Test firmware image 8 */ 9619 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 9620 /* enum: RXDP Test firmware image 9 */ 9621 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 9622 /* enum: RXDP Test firmware image 10 */ 9623 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c 9624 /* TxDPCPU firmware id. */ 9625 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6 9626 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2 9627 /* enum: Standard TXDP firmware */ 9628 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0 9629 /* enum: Low latency TXDP firmware */ 9630 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1 9631 /* enum: High packet rate TXDP firmware */ 9632 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3 9633 /* enum: Rules engine TXDP firmware */ 9634 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5 9635 /* enum: BIST TXDP firmware */ 9636 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d 9637 /* enum: TXDP Test firmware image 1 */ 9638 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 9639 /* enum: TXDP Test firmware image 2 */ 9640 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 9641 /* enum: TXDP CSR bus test firmware */ 9642 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103 9643 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8 9644 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2 9645 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0 9646 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12 9647 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12 9648 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 9649 /* enum: reserved value - do not use (may indicate alternative interpretation 9650 * of REV field in future) 9651 */ 9652 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0 9653 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 9654 * development only) 9655 */ 9656 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 9657 /* enum: RX PD firmware with approximately Siena-compatible behaviour 9658 * (Huntington development only) 9659 */ 9660 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 9661 /* enum: Full featured RX PD production firmware */ 9662 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 9663 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 9664 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3 9665 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 9666 * (Huntington development only) 9667 */ 9668 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9669 /* enum: Low latency RX PD production firmware */ 9670 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 9671 /* enum: Packed stream RX PD production firmware */ 9672 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 9673 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 9674 * tests (Medford development only) 9675 */ 9676 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 9677 /* enum: Rules engine RX PD production firmware */ 9678 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 9679 /* enum: reserved value - do not use (bug69716) */ 9680 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED_9 0x9 9681 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9682 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 9683 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 9684 * encapsulations (Medford development only) 9685 */ 9686 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 9687 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10 9688 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2 9689 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0 9690 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12 9691 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12 9692 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 9693 /* enum: reserved value - do not use (may indicate alternative interpretation 9694 * of REV field in future) 9695 */ 9696 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0 9697 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 9698 * development only) 9699 */ 9700 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 9701 /* enum: TX PD firmware with approximately Siena-compatible behaviour 9702 * (Huntington development only) 9703 */ 9704 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 9705 /* enum: Full featured TX PD production firmware */ 9706 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 9707 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 9708 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3 9709 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 9710 * (Huntington development only) 9711 */ 9712 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9713 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 9714 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 9715 * tests (Medford development only) 9716 */ 9717 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 9718 /* enum: Rules engine TX PD production firmware */ 9719 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 9720 /* enum: reserved value - do not use (bug69716) */ 9721 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED_9 0x9 9722 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9723 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 9724 /* Hardware capabilities of NIC */ 9725 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12 9726 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4 9727 /* Licensed capabilities */ 9728 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16 9729 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4 9730 /* Second word of flags. Not present on older firmware (check the length). */ 9731 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20 9732 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4 9733 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0 9734 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1 9735 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1 9736 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1 9737 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2 9738 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1 9739 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3 9740 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1 9741 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4 9742 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1 9743 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5 9744 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 9745 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 9746 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 9747 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7 9748 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1 9749 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8 9750 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 9751 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9 9752 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1 9753 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10 9754 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1 9755 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11 9756 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1 9757 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 9758 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 9759 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 13 9760 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1 9761 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 14 9762 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1 9763 #define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_LBN 15 9764 #define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_WIDTH 1 9765 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_LBN 16 9766 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_WIDTH 1 9767 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_LBN 17 9768 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 1 9769 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 9770 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 9771 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 9772 * on older firmware (check the length). 9773 */ 9774 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 9775 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 9776 /* One byte per PF containing the number of the external port assigned to this 9777 * PF, indexed by PF number. Special values indicate that a PF is either not 9778 * present or not assigned. 9779 */ 9780 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 9781 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 9782 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 9783 /* enum: The caller is not permitted to access information on this PF. */ 9784 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff 9785 /* enum: PF does not exist. */ 9786 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe 9787 /* enum: PF does exist but is not assigned to any external port. */ 9788 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd 9789 /* enum: This value indicates that PF is assigned, but it cannot be expressed 9790 * in this field. It is intended for a possible future situation where a more 9791 * complex scheme of PFs to ports mapping is being used. The future driver 9792 * should look for a new field supporting the new scheme. The current/old 9793 * driver should treat this value as PF_NOT_ASSIGNED. 9794 */ 9795 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 9796 /* One byte per PF containing the number of its VFs, indexed by PF number. A 9797 * special value indicates that a PF is not present. 9798 */ 9799 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 42 9800 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1 9801 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16 9802 /* enum: The caller is not permitted to access information on this PF. */ 9803 /* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */ 9804 /* enum: PF does not exist. */ 9805 /* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */ 9806 /* Number of VIs available for each external port */ 9807 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58 9808 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2 9809 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4 9810 /* Size of RX descriptor cache expressed as binary logarithm The actual size 9811 * equals (2 ^ RX_DESC_CACHE_SIZE) 9812 */ 9813 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 66 9814 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1 9815 /* Size of TX descriptor cache expressed as binary logarithm The actual size 9816 * equals (2 ^ TX_DESC_CACHE_SIZE) 9817 */ 9818 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 67 9819 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1 9820 /* Total number of available PIO buffers */ 9821 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 68 9822 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 2 9823 /* Size of a single PIO buffer */ 9824 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 70 9825 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 2 9826 /* On chips later than Medford the amount of address space assigned to each VI 9827 * is configurable. This is a global setting that the driver must query to 9828 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 9829 * with 8k VI windows. 9830 */ 9831 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 72 9832 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1 9833 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 9834 * CTPIO is not mapped. 9835 */ 9836 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0 9837 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 9838 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1 9839 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 9840 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2 9841 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 9842 * (SF-115995-SW) in the present configuration of firmware and port mode. 9843 */ 9844 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 9845 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 9846 /* Number of buffers per adapter that can be used for VFIFO Stuffing 9847 * (SF-115995-SW) in the present configuration of firmware and port mode. 9848 */ 9849 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 9850 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 9851 9852 /* MC_CMD_GET_CAPABILITIES_V4_OUT msgresponse */ 9853 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LEN 78 9854 /* First word of flags. */ 9855 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0 9856 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4 9857 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_LBN 3 9858 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 1 9859 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4 9860 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 1 9861 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_LBN 5 9862 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 1 9863 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 9864 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 9865 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_LBN 7 9866 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 9867 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_LBN 8 9868 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 9869 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_LBN 9 9870 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 1 9871 #define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 9872 #define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 9873 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 9874 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 9875 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 9876 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 9877 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_LBN 13 9878 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 9879 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_LBN 14 9880 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 1 9881 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 9882 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 9883 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_LBN 16 9884 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 1 9885 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_LBN 17 9886 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 1 9887 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_LBN 18 9888 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 1 9889 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_LBN 19 9890 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 1 9891 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_LBN 20 9892 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 1 9893 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_LBN 21 9894 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 1 9895 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_LBN 22 9896 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 1 9897 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_LBN 23 9898 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 1 9899 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_LBN 24 9900 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 1 9901 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_LBN 25 9902 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 1 9903 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_LBN 26 9904 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 1 9905 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_LBN 27 9906 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 9907 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_LBN 28 9908 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 1 9909 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 9910 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 9911 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_LBN 30 9912 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 1 9913 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_LBN 31 9914 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 1 9915 /* RxDPCPU firmware id. */ 9916 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4 9917 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_LEN 2 9918 /* enum: Standard RXDP firmware */ 9919 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0 9920 /* enum: Low latency RXDP firmware */ 9921 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1 9922 /* enum: Packed stream RXDP firmware */ 9923 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2 9924 /* enum: Rules engine RXDP firmware */ 9925 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5 9926 /* enum: BIST RXDP firmware */ 9927 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a 9928 /* enum: RXDP Test firmware image 1 */ 9929 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 9930 /* enum: RXDP Test firmware image 2 */ 9931 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 9932 /* enum: RXDP Test firmware image 3 */ 9933 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 9934 /* enum: RXDP Test firmware image 4 */ 9935 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 9936 /* enum: RXDP Test firmware image 5 */ 9937 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105 9938 /* enum: RXDP Test firmware image 6 */ 9939 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 9940 /* enum: RXDP Test firmware image 7 */ 9941 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 9942 /* enum: RXDP Test firmware image 8 */ 9943 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 9944 /* enum: RXDP Test firmware image 9 */ 9945 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 9946 /* enum: RXDP Test firmware image 10 */ 9947 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c 9948 /* TxDPCPU firmware id. */ 9949 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_OFST 6 9950 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_LEN 2 9951 /* enum: Standard TXDP firmware */ 9952 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0 9953 /* enum: Low latency TXDP firmware */ 9954 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1 9955 /* enum: High packet rate TXDP firmware */ 9956 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3 9957 /* enum: Rules engine TXDP firmware */ 9958 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5 9959 /* enum: BIST TXDP firmware */ 9960 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d 9961 /* enum: TXDP Test firmware image 1 */ 9962 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 9963 /* enum: TXDP Test firmware image 2 */ 9964 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 9965 /* enum: TXDP CSR bus test firmware */ 9966 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103 9967 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 8 9968 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 2 9969 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0 9970 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_WIDTH 12 9971 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_LBN 12 9972 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 9973 /* enum: reserved value - do not use (may indicate alternative interpretation 9974 * of REV field in future) 9975 */ 9976 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0 9977 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 9978 * development only) 9979 */ 9980 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 9981 /* enum: RX PD firmware with approximately Siena-compatible behaviour 9982 * (Huntington development only) 9983 */ 9984 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 9985 /* enum: Full featured RX PD production firmware */ 9986 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 9987 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 9988 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3 9989 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 9990 * (Huntington development only) 9991 */ 9992 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9993 /* enum: Low latency RX PD production firmware */ 9994 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 9995 /* enum: Packed stream RX PD production firmware */ 9996 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 9997 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 9998 * tests (Medford development only) 9999 */ 10000 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10001 /* enum: Rules engine RX PD production firmware */ 10002 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 10003 /* enum: reserved value - do not use (bug69716) */ 10004 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED_9 0x9 10005 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10006 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10007 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 10008 * encapsulations (Medford development only) 10009 */ 10010 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10011 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 10 10012 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 2 10013 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0 10014 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10015 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10016 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10017 /* enum: reserved value - do not use (may indicate alternative interpretation 10018 * of REV field in future) 10019 */ 10020 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0 10021 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 10022 * development only) 10023 */ 10024 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10025 /* enum: TX PD firmware with approximately Siena-compatible behaviour 10026 * (Huntington development only) 10027 */ 10028 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10029 /* enum: Full featured TX PD production firmware */ 10030 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 10031 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10032 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10033 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 10034 * (Huntington development only) 10035 */ 10036 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10037 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10038 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 10039 * tests (Medford development only) 10040 */ 10041 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10042 /* enum: Rules engine TX PD production firmware */ 10043 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 10044 /* enum: reserved value - do not use (bug69716) */ 10045 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED_9 0x9 10046 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10047 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10048 /* Hardware capabilities of NIC */ 10049 #define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_OFST 12 10050 #define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4 10051 /* Licensed capabilities */ 10052 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_OFST 16 10053 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4 10054 /* Second word of flags. Not present on older firmware (check the length). */ 10055 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST 20 10056 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4 10057 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0 10058 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 1 10059 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 1 10060 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 1 10061 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_LBN 2 10062 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 1 10063 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_LBN 3 10064 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 1 10065 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4 10066 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 1 10067 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_LBN 5 10068 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 10069 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 10070 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 10071 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_LBN 7 10072 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 1 10073 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_LBN 8 10074 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 10075 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_LBN 9 10076 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 1 10077 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_LBN 10 10078 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 1 10079 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_LBN 11 10080 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 1 10081 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 10082 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 10083 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_LBN 13 10084 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 1 10085 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_LBN 14 10086 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1 10087 #define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN 15 10088 #define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_WIDTH 1 10089 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_LBN 16 10090 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_WIDTH 1 10091 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_LBN 17 10092 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 1 10093 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 10094 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 10095 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 10096 * on older firmware (check the length). 10097 */ 10098 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 10099 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 10100 /* One byte per PF containing the number of the external port assigned to this 10101 * PF, indexed by PF number. Special values indicate that a PF is either not 10102 * present or not assigned. 10103 */ 10104 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 10105 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 10106 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 10107 /* enum: The caller is not permitted to access information on this PF. */ 10108 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff 10109 /* enum: PF does not exist. */ 10110 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe 10111 /* enum: PF does exist but is not assigned to any external port. */ 10112 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd 10113 /* enum: This value indicates that PF is assigned, but it cannot be expressed 10114 * in this field. It is intended for a possible future situation where a more 10115 * complex scheme of PFs to ports mapping is being used. The future driver 10116 * should look for a new field supporting the new scheme. The current/old 10117 * driver should treat this value as PF_NOT_ASSIGNED. 10118 */ 10119 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 10120 /* One byte per PF containing the number of its VFs, indexed by PF number. A 10121 * special value indicates that a PF is not present. 10122 */ 10123 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_OFST 42 10124 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 1 10125 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_NUM 16 10126 /* enum: The caller is not permitted to access information on this PF. */ 10127 /* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */ 10128 /* enum: PF does not exist. */ 10129 /* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */ 10130 /* Number of VIs available for each external port */ 10131 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 58 10132 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 2 10133 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4 10134 /* Size of RX descriptor cache expressed as binary logarithm The actual size 10135 * equals (2 ^ RX_DESC_CACHE_SIZE) 10136 */ 10137 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_OFST 66 10138 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_LEN 1 10139 /* Size of TX descriptor cache expressed as binary logarithm The actual size 10140 * equals (2 ^ TX_DESC_CACHE_SIZE) 10141 */ 10142 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_OFST 67 10143 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_LEN 1 10144 /* Total number of available PIO buffers */ 10145 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_OFST 68 10146 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_LEN 2 10147 /* Size of a single PIO buffer */ 10148 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_OFST 70 10149 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_LEN 2 10150 /* On chips later than Medford the amount of address space assigned to each VI 10151 * is configurable. This is a global setting that the driver must query to 10152 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 10153 * with 8k VI windows. 10154 */ 10155 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_OFST 72 10156 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_LEN 1 10157 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 10158 * CTPIO is not mapped. 10159 */ 10160 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0 10161 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 10162 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1 10163 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 10164 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2 10165 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 10166 * (SF-115995-SW) in the present configuration of firmware and port mode. 10167 */ 10168 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 10169 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 10170 /* Number of buffers per adapter that can be used for VFIFO Stuffing 10171 * (SF-115995-SW) in the present configuration of firmware and port mode. 10172 */ 10173 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 10174 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 10175 /* Entry count in the MAC stats array, including the final GENERATION_END 10176 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to 10177 * hold at least this many 64-bit stats values, if they wish to receive all 10178 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the 10179 * stats array returned will be truncated. 10180 */ 10181 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_OFST 76 10182 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_LEN 2 10183 10184 10185 /***********************************/ 10186 /* MC_CMD_V2_EXTN 10187 * Encapsulation for a v2 extended command 10188 */ 10189 #define MC_CMD_V2_EXTN 0x7f 10190 10191 /* MC_CMD_V2_EXTN_IN msgrequest */ 10192 #define MC_CMD_V2_EXTN_IN_LEN 4 10193 /* the extended command number */ 10194 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 10195 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 10196 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 10197 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 10198 /* the actual length of the encapsulated command (which is not in the v1 10199 * header) 10200 */ 10201 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 10202 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 10203 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 10204 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6 10205 10206 10207 /***********************************/ 10208 /* MC_CMD_TCM_BUCKET_ALLOC 10209 * Allocate a pacer bucket (for qau rp or a snapper test) 10210 */ 10211 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 10212 10213 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10214 10215 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 10216 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 10217 10218 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 10219 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 10220 /* the bucket id */ 10221 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 10222 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4 10223 10224 10225 /***********************************/ 10226 /* MC_CMD_TCM_BUCKET_FREE 10227 * Free a pacer bucket 10228 */ 10229 #define MC_CMD_TCM_BUCKET_FREE 0xb3 10230 10231 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10232 10233 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 10234 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 10235 /* the bucket id */ 10236 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 10237 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 4 10238 10239 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 10240 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 10241 10242 10243 /***********************************/ 10244 /* MC_CMD_TCM_BUCKET_INIT 10245 * Initialise pacer bucket with a given rate 10246 */ 10247 #define MC_CMD_TCM_BUCKET_INIT 0xb4 10248 10249 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10250 10251 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ 10252 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 10253 /* the bucket id */ 10254 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 10255 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 4 10256 /* the rate in mbps */ 10257 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 10258 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 4 10259 10260 /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */ 10261 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12 10262 /* the bucket id */ 10263 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0 10264 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 4 10265 /* the rate in mbps */ 10266 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4 10267 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 4 10268 /* the desired maximum fill level */ 10269 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8 10270 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 4 10271 10272 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ 10273 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 10274 10275 10276 /***********************************/ 10277 /* MC_CMD_TCM_TXQ_INIT 10278 * Initialise txq in pacer with given options or set options 10279 */ 10280 #define MC_CMD_TCM_TXQ_INIT 0xb5 10281 10282 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10283 10284 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 10285 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 10286 /* the txq id */ 10287 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 10288 #define MC_CMD_TCM_TXQ_INIT_IN_QID_LEN 4 10289 /* the static priority associated with the txq */ 10290 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 10291 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 4 10292 /* bitmask of the priority queues this txq is inserted into when inserted. */ 10293 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 10294 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4 10295 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0 10296 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 10297 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1 10298 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1 10299 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2 10300 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1 10301 /* the reaction point (RP) bucket */ 10302 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 10303 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 4 10304 /* an already reserved bucket (typically set to bucket associated with outer 10305 * vswitch) 10306 */ 10307 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 10308 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 4 10309 /* an already reserved bucket (typically set to bucket associated with inner 10310 * vswitch) 10311 */ 10312 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 10313 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 4 10314 /* the min bucket (typically for ETS/minimum bandwidth) */ 10315 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 10316 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 4 10317 10318 /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */ 10319 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32 10320 /* the txq id */ 10321 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0 10322 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 4 10323 /* the static priority associated with the txq */ 10324 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4 10325 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 4 10326 /* bitmask of the priority queues this txq is inserted into when inserted. */ 10327 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8 10328 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4 10329 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0 10330 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 10331 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1 10332 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1 10333 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2 10334 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1 10335 /* the reaction point (RP) bucket */ 10336 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12 10337 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 4 10338 /* an already reserved bucket (typically set to bucket associated with outer 10339 * vswitch) 10340 */ 10341 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16 10342 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 4 10343 /* an already reserved bucket (typically set to bucket associated with inner 10344 * vswitch) 10345 */ 10346 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20 10347 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 4 10348 /* the min bucket (typically for ETS/minimum bandwidth) */ 10349 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24 10350 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 4 10351 /* the static priority associated with the txq */ 10352 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28 10353 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 4 10354 10355 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 10356 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 10357 10358 10359 /***********************************/ 10360 /* MC_CMD_LINK_PIOBUF 10361 * Link a push I/O buffer to a TxQ 10362 */ 10363 #define MC_CMD_LINK_PIOBUF 0x92 10364 10365 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10366 10367 /* MC_CMD_LINK_PIOBUF_IN msgrequest */ 10368 #define MC_CMD_LINK_PIOBUF_IN_LEN 8 10369 /* Handle for allocated push I/O buffer. */ 10370 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 10371 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4 10372 /* Function Local Instance (VI) number. */ 10373 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 10374 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4 10375 10376 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ 10377 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 10378 10379 10380 /***********************************/ 10381 /* MC_CMD_UNLINK_PIOBUF 10382 * Unlink a push I/O buffer from a TxQ 10383 */ 10384 #define MC_CMD_UNLINK_PIOBUF 0x93 10385 10386 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10387 10388 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ 10389 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 10390 /* Function Local Instance (VI) number. */ 10391 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 10392 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4 10393 10394 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ 10395 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 10396 10397 10398 /***********************************/ 10399 /* MC_CMD_VSWITCH_ALLOC 10400 * allocate and initialise a v-switch. 10401 */ 10402 #define MC_CMD_VSWITCH_ALLOC 0x94 10403 10404 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10405 10406 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ 10407 #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 10408 /* The port to connect to the v-switch's upstream port. */ 10409 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10410 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 10411 /* The type of v-switch to create. */ 10412 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 10413 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4 10414 /* enum: VLAN */ 10415 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 10416 /* enum: VEB */ 10417 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 10418 /* enum: VEPA (obsolete) */ 10419 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 10420 /* enum: MUX */ 10421 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4 10422 /* enum: Snapper specific; semantics TBD */ 10423 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5 10424 /* Flags controlling v-port creation */ 10425 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 10426 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4 10427 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 10428 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 10429 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators, 10430 * this must be one or greated, and the attached v-ports must have exactly this 10431 * number of tags. For other v-switch types, this must be zero of greater, and 10432 * is an upper limit on the number of VLAN tags for attached v-ports. An error 10433 * will be returned if existing configuration means we can't support attached 10434 * v-ports with this number of tags. 10435 */ 10436 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 10437 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4 10438 10439 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ 10440 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 10441 10442 10443 /***********************************/ 10444 /* MC_CMD_VSWITCH_FREE 10445 * de-allocate a v-switch. 10446 */ 10447 #define MC_CMD_VSWITCH_FREE 0x95 10448 10449 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10450 10451 /* MC_CMD_VSWITCH_FREE_IN msgrequest */ 10452 #define MC_CMD_VSWITCH_FREE_IN_LEN 4 10453 /* The port to which the v-switch is connected. */ 10454 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 10455 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4 10456 10457 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ 10458 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 10459 10460 10461 /***********************************/ 10462 /* MC_CMD_VSWITCH_QUERY 10463 * read some config of v-switch. For now this command is an empty placeholder. 10464 * It may be used to check if a v-switch is connected to a given EVB port (if 10465 * not, then the command returns ENOENT). 10466 */ 10467 #define MC_CMD_VSWITCH_QUERY 0x63 10468 10469 #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10470 10471 /* MC_CMD_VSWITCH_QUERY_IN msgrequest */ 10472 #define MC_CMD_VSWITCH_QUERY_IN_LEN 4 10473 /* The port to which the v-switch is connected. */ 10474 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 10475 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 4 10476 10477 /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */ 10478 #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0 10479 10480 10481 /***********************************/ 10482 /* MC_CMD_VPORT_ALLOC 10483 * allocate a v-port. 10484 */ 10485 #define MC_CMD_VPORT_ALLOC 0x96 10486 10487 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10488 10489 /* MC_CMD_VPORT_ALLOC_IN msgrequest */ 10490 #define MC_CMD_VPORT_ALLOC_IN_LEN 20 10491 /* The port to which the v-switch is connected. */ 10492 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10493 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 10494 /* The type of the new v-port. */ 10495 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 10496 #define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4 10497 /* enum: VLAN (obsolete) */ 10498 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 10499 /* enum: VEB (obsolete) */ 10500 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 10501 /* enum: VEPA (obsolete) */ 10502 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 10503 /* enum: A normal v-port receives packets which match a specified MAC and/or 10504 * VLAN. 10505 */ 10506 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 10507 /* enum: An expansion v-port packets traffic which don't match any other 10508 * v-port. 10509 */ 10510 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 10511 /* enum: An test v-port receives packets which match any filters installed by 10512 * its downstream components. 10513 */ 10514 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 10515 /* Flags controlling v-port creation */ 10516 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 10517 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4 10518 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 10519 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 10520 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1 10521 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1 10522 /* The number of VLAN tags to insert/remove. An error will be returned if 10523 * incompatible with the number of VLAN tags specified for the upstream 10524 * v-switch. 10525 */ 10526 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 10527 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4 10528 /* The actual VLAN tags to insert/remove */ 10529 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 10530 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4 10531 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 10532 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 10533 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 10534 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 10535 10536 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */ 10537 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4 10538 /* The handle of the new v-port */ 10539 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 10540 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4 10541 10542 10543 /***********************************/ 10544 /* MC_CMD_VPORT_FREE 10545 * de-allocate a v-port. 10546 */ 10547 #define MC_CMD_VPORT_FREE 0x97 10548 10549 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10550 10551 /* MC_CMD_VPORT_FREE_IN msgrequest */ 10552 #define MC_CMD_VPORT_FREE_IN_LEN 4 10553 /* The handle of the v-port */ 10554 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 10555 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4 10556 10557 /* MC_CMD_VPORT_FREE_OUT msgresponse */ 10558 #define MC_CMD_VPORT_FREE_OUT_LEN 0 10559 10560 10561 /***********************************/ 10562 /* MC_CMD_VADAPTOR_ALLOC 10563 * allocate a v-adaptor. 10564 */ 10565 #define MC_CMD_VADAPTOR_ALLOC 0x98 10566 10567 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10568 10569 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ 10570 #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30 10571 /* The port to connect to the v-adaptor's port. */ 10572 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10573 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 10574 /* Flags controlling v-adaptor creation */ 10575 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 10576 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4 10577 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 10578 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 10579 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1 10580 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10581 /* The number of VLAN tags to strip on receive */ 10582 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 10583 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4 10584 /* The number of VLAN tags to transparently insert/remove. */ 10585 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16 10586 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4 10587 /* The actual VLAN tags to insert/remove */ 10588 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20 10589 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4 10590 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0 10591 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16 10592 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16 10593 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16 10594 /* The MAC address to assign to this v-adaptor */ 10595 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24 10596 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6 10597 /* enum: Derive the MAC address from the upstream port */ 10598 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0 10599 10600 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ 10601 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 10602 10603 10604 /***********************************/ 10605 /* MC_CMD_VADAPTOR_FREE 10606 * de-allocate a v-adaptor. 10607 */ 10608 #define MC_CMD_VADAPTOR_FREE 0x99 10609 10610 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10611 10612 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */ 10613 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4 10614 /* The port to which the v-adaptor is connected. */ 10615 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 10616 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4 10617 10618 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ 10619 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 10620 10621 10622 /***********************************/ 10623 /* MC_CMD_VADAPTOR_SET_MAC 10624 * assign a new MAC address to a v-adaptor. 10625 */ 10626 #define MC_CMD_VADAPTOR_SET_MAC 0x5d 10627 10628 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10629 10630 /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */ 10631 #define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10 10632 /* The port to which the v-adaptor is connected. */ 10633 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 10634 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4 10635 /* The new MAC address to assign to this v-adaptor */ 10636 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4 10637 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6 10638 10639 /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ 10640 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 10641 10642 10643 /***********************************/ 10644 /* MC_CMD_VADAPTOR_GET_MAC 10645 * read the MAC address assigned to a v-adaptor. 10646 */ 10647 #define MC_CMD_VADAPTOR_GET_MAC 0x5e 10648 10649 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10650 10651 /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ 10652 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 10653 /* The port to which the v-adaptor is connected. */ 10654 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 10655 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 4 10656 10657 /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ 10658 #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 10659 /* The MAC address assigned to this v-adaptor */ 10660 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 10661 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 10662 10663 10664 /***********************************/ 10665 /* MC_CMD_VADAPTOR_QUERY 10666 * read some config of v-adaptor. 10667 */ 10668 #define MC_CMD_VADAPTOR_QUERY 0x61 10669 10670 #define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10671 10672 /* MC_CMD_VADAPTOR_QUERY_IN msgrequest */ 10673 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4 10674 /* The port to which the v-adaptor is connected. */ 10675 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 10676 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4 10677 10678 /* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */ 10679 #define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12 10680 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 10681 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0 10682 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4 10683 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */ 10684 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4 10685 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4 10686 /* The number of VLAN tags that may still be added */ 10687 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8 10688 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4 10689 10690 10691 /***********************************/ 10692 /* MC_CMD_EVB_PORT_ASSIGN 10693 * assign a port to a PCI function. 10694 */ 10695 #define MC_CMD_EVB_PORT_ASSIGN 0x9a 10696 10697 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10698 10699 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ 10700 #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 10701 /* The port to assign. */ 10702 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 10703 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4 10704 /* The target function to modify. */ 10705 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 10706 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4 10707 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 10708 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 10709 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 10710 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 10711 10712 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ 10713 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 10714 10715 10716 /***********************************/ 10717 /* MC_CMD_RDWR_A64_REGIONS 10718 * Assign the 64 bit region addresses. 10719 */ 10720 #define MC_CMD_RDWR_A64_REGIONS 0x9b 10721 10722 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10723 10724 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ 10725 #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 10726 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 10727 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 4 10728 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 10729 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 4 10730 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 10731 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 4 10732 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 10733 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 4 10734 /* Write enable bits 0-3, set to write, clear to read. */ 10735 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 10736 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 10737 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 10738 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 10739 10740 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included 10741 * regardless of state of write bits in the request. 10742 */ 10743 #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 10744 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 10745 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 4 10746 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 10747 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 4 10748 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 10749 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 4 10750 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 10751 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4 10752 10753 10754 /***********************************/ 10755 /* MC_CMD_ONLOAD_STACK_ALLOC 10756 * Allocate an Onload stack ID. 10757 */ 10758 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c 10759 10760 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10761 10762 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ 10763 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 10764 /* The handle of the owning upstream port */ 10765 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10766 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 10767 10768 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ 10769 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 10770 /* The handle of the new Onload stack */ 10771 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 10772 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4 10773 10774 10775 /***********************************/ 10776 /* MC_CMD_ONLOAD_STACK_FREE 10777 * Free an Onload stack ID. 10778 */ 10779 #define MC_CMD_ONLOAD_STACK_FREE 0x9d 10780 10781 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10782 10783 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ 10784 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 10785 /* The handle of the Onload stack */ 10786 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 10787 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 4 10788 10789 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ 10790 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 10791 10792 10793 /***********************************/ 10794 /* MC_CMD_RSS_CONTEXT_ALLOC 10795 * Allocate an RSS context. 10796 */ 10797 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e 10798 10799 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10800 10801 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ 10802 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 10803 /* The handle of the owning upstream port */ 10804 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10805 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 10806 /* The type of context to allocate */ 10807 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 10808 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4 10809 /* enum: Allocate a context for exclusive use. The key and indirection table 10810 * must be explicitly configured. 10811 */ 10812 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 10813 /* enum: Allocate a context for shared use; this will spread across a range of 10814 * queues, but the key and indirection table are pre-configured and may not be 10815 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. 10816 */ 10817 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 10818 /* Number of queues spanned by this context, in the range 1-64; valid offsets 10819 * in the indirection table will be in the range 0 to NUM_QUEUES-1. 10820 */ 10821 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 10822 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4 10823 10824 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ 10825 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 10826 /* The handle of the new RSS context. This should be considered opaque to the 10827 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 10828 * handle. 10829 */ 10830 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 10831 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4 10832 /* enum: guaranteed invalid RSS context handle value */ 10833 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff 10834 10835 10836 /***********************************/ 10837 /* MC_CMD_RSS_CONTEXT_FREE 10838 * Free an RSS context. 10839 */ 10840 #define MC_CMD_RSS_CONTEXT_FREE 0x9f 10841 10842 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10843 10844 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ 10845 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 10846 /* The handle of the RSS context */ 10847 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 10848 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4 10849 10850 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ 10851 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 10852 10853 10854 /***********************************/ 10855 /* MC_CMD_RSS_CONTEXT_SET_KEY 10856 * Set the Toeplitz hash key for an RSS context. 10857 */ 10858 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 10859 10860 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10861 10862 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ 10863 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 10864 /* The handle of the RSS context */ 10865 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 10866 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4 10867 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 10868 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 10869 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 10870 10871 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ 10872 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 10873 10874 10875 /***********************************/ 10876 /* MC_CMD_RSS_CONTEXT_GET_KEY 10877 * Get the Toeplitz hash key for an RSS context. 10878 */ 10879 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 10880 10881 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10882 10883 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ 10884 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 10885 /* The handle of the RSS context */ 10886 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 10887 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4 10888 10889 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ 10890 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 10891 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 10892 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 10893 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 10894 10895 10896 /***********************************/ 10897 /* MC_CMD_RSS_CONTEXT_SET_TABLE 10898 * Set the indirection table for an RSS context. 10899 */ 10900 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 10901 10902 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10903 10904 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ 10905 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 10906 /* The handle of the RSS context */ 10907 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 10908 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4 10909 /* The 128-byte indirection table (1 byte per entry) */ 10910 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 10911 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 10912 10913 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ 10914 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 10915 10916 10917 /***********************************/ 10918 /* MC_CMD_RSS_CONTEXT_GET_TABLE 10919 * Get the indirection table for an RSS context. 10920 */ 10921 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 10922 10923 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10924 10925 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ 10926 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 10927 /* The handle of the RSS context */ 10928 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 10929 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4 10930 10931 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ 10932 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 10933 /* The 128-byte indirection table (1 byte per entry) */ 10934 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 10935 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 10936 10937 10938 /***********************************/ 10939 /* MC_CMD_RSS_CONTEXT_SET_FLAGS 10940 * Set various control flags for an RSS context. 10941 */ 10942 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 10943 10944 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10945 10946 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ 10947 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 10948 /* The handle of the RSS context */ 10949 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 10950 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4 10951 /* Hash control flags. The _EN bits are always supported, but new modes are 10952 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES: 10953 * in this case, the MODE fields may be set to non-zero values, and will take 10954 * effect regardless of the settings of the _EN flags. See the RSS_MODE 10955 * structure for the meaning of the mode bits. Drivers must check the 10956 * capability before trying to set any _MODE fields, as older firmware will 10957 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In 10958 * the case where all the _MODE flags are zero, the _EN flags take effect, 10959 * providing backward compatibility for existing drivers. (Setting all _MODE 10960 * *and* all _EN flags to zero is valid, to disable RSS spreading for that 10961 * particular packet type.) 10962 */ 10963 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 10964 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4 10965 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 10966 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 10967 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 10968 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 10969 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 10970 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 10971 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 10972 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 10973 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4 10974 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4 10975 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8 10976 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4 10977 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12 10978 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4 10979 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16 10980 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4 10981 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20 10982 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4 10983 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24 10984 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4 10985 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28 10986 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4 10987 10988 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ 10989 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 10990 10991 10992 /***********************************/ 10993 /* MC_CMD_RSS_CONTEXT_GET_FLAGS 10994 * Get various control flags for an RSS context. 10995 */ 10996 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 10997 10998 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10999 11000 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ 11001 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 11002 /* The handle of the RSS context */ 11003 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 11004 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4 11005 11006 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ 11007 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 11008 /* Hash control flags. If all _MODE bits are zero (which will always be true 11009 * for older firmware which does not report the ADDITIONAL_RSS_MODES 11010 * capability), the _EN bits report the state. If any _MODE bits are non-zero 11011 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES) 11012 * then the _EN bits should be disregarded, although the _MODE flags are 11013 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS 11014 * context and in the case where the _EN flags were used in the SET. This 11015 * provides backward compatibility: old drivers will not be attempting to 11016 * derive any meaning from the _MODE bits (and can never set them to any value 11017 * not representable by the _EN bits); new drivers can always determine the 11018 * mode by looking only at the _MODE bits; the value returned by a GET can 11019 * always be used for a SET regardless of old/new driver vs. old/new firmware. 11020 */ 11021 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 11022 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4 11023 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 11024 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 11025 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 11026 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 11027 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 11028 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 11029 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 11030 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 11031 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4 11032 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4 11033 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8 11034 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4 11035 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12 11036 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4 11037 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16 11038 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4 11039 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20 11040 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4 11041 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24 11042 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4 11043 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 11044 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 11045 11046 11047 /***********************************/ 11048 /* MC_CMD_DOT1P_MAPPING_ALLOC 11049 * Allocate a .1p mapping. 11050 */ 11051 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 11052 11053 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11054 11055 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ 11056 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 11057 /* The handle of the owning upstream port */ 11058 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11059 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 11060 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed 11061 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and 11062 * referenced RSS contexts must span no more than this number. 11063 */ 11064 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 11065 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_LEN 4 11066 11067 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ 11068 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 11069 /* The handle of the new .1p mapping. This should be considered opaque to the 11070 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 11071 * handle. 11072 */ 11073 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 11074 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_LEN 4 11075 /* enum: guaranteed invalid .1p mapping handle value */ 11076 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff 11077 11078 11079 /***********************************/ 11080 /* MC_CMD_DOT1P_MAPPING_FREE 11081 * Free a .1p mapping. 11082 */ 11083 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 11084 11085 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11086 11087 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ 11088 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 11089 /* The handle of the .1p mapping */ 11090 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 11091 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_LEN 4 11092 11093 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ 11094 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 11095 11096 11097 /***********************************/ 11098 /* MC_CMD_DOT1P_MAPPING_SET_TABLE 11099 * Set the mapping table for a .1p mapping. 11100 */ 11101 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 11102 11103 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11104 11105 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ 11106 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 11107 /* The handle of the .1p mapping */ 11108 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 11109 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4 11110 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 11111 * handle) 11112 */ 11113 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 11114 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 11115 11116 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ 11117 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 11118 11119 11120 /***********************************/ 11121 /* MC_CMD_DOT1P_MAPPING_GET_TABLE 11122 * Get the mapping table for a .1p mapping. 11123 */ 11124 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 11125 11126 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11127 11128 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ 11129 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 11130 /* The handle of the .1p mapping */ 11131 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 11132 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4 11133 11134 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ 11135 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 11136 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 11137 * handle) 11138 */ 11139 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 11140 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 11141 11142 11143 /***********************************/ 11144 /* MC_CMD_GET_VECTOR_CFG 11145 * Get Interrupt Vector config for this PF. 11146 */ 11147 #define MC_CMD_GET_VECTOR_CFG 0xbf 11148 11149 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11150 11151 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 11152 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 11153 11154 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 11155 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 11156 /* Base absolute interrupt vector number. */ 11157 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 11158 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_LEN 4 11159 /* Number of interrupt vectors allocate to this PF. */ 11160 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 11161 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_LEN 4 11162 /* Number of interrupt vectors to allocate per VF. */ 11163 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 11164 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_LEN 4 11165 11166 11167 /***********************************/ 11168 /* MC_CMD_SET_VECTOR_CFG 11169 * Set Interrupt Vector config for this PF. 11170 */ 11171 #define MC_CMD_SET_VECTOR_CFG 0xc0 11172 11173 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11174 11175 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 11176 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 11177 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to 11178 * let the system find a suitable base. 11179 */ 11180 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 11181 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_LEN 4 11182 /* Number of interrupt vectors allocate to this PF. */ 11183 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 11184 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_LEN 4 11185 /* Number of interrupt vectors to allocate per VF. */ 11186 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 11187 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_LEN 4 11188 11189 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 11190 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 11191 11192 11193 /***********************************/ 11194 /* MC_CMD_VPORT_ADD_MAC_ADDRESS 11195 * Add a MAC address to a v-port 11196 */ 11197 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 11198 11199 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11200 11201 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ 11202 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 11203 /* The handle of the v-port */ 11204 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 11205 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4 11206 /* MAC address to add */ 11207 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 11208 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 11209 11210 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ 11211 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 11212 11213 11214 /***********************************/ 11215 /* MC_CMD_VPORT_DEL_MAC_ADDRESS 11216 * Delete a MAC address from a v-port 11217 */ 11218 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 11219 11220 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11221 11222 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ 11223 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 11224 /* The handle of the v-port */ 11225 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 11226 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4 11227 /* MAC address to add */ 11228 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 11229 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 11230 11231 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ 11232 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 11233 11234 11235 /***********************************/ 11236 /* MC_CMD_VPORT_GET_MAC_ADDRESSES 11237 * Delete a MAC address from a v-port 11238 */ 11239 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa 11240 11241 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11242 11243 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ 11244 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 11245 /* The handle of the v-port */ 11246 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 11247 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4 11248 11249 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ 11250 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 11251 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 11252 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) 11253 /* The number of MAC addresses returned */ 11254 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 11255 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4 11256 /* Array of MAC addresses */ 11257 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 11258 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 11259 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 11260 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 11261 11262 11263 /***********************************/ 11264 /* MC_CMD_VPORT_RECONFIGURE 11265 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port 11266 * has already been passed to another function (v-port's user), then that 11267 * function will be reset before applying the changes. 11268 */ 11269 #define MC_CMD_VPORT_RECONFIGURE 0xeb 11270 11271 #define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11272 11273 /* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */ 11274 #define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44 11275 /* The handle of the v-port */ 11276 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0 11277 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4 11278 /* Flags requesting what should be changed. */ 11279 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4 11280 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4 11281 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0 11282 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1 11283 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1 11284 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1 11285 /* The number of VLAN tags to insert/remove. An error will be returned if 11286 * incompatible with the number of VLAN tags specified for the upstream 11287 * v-switch. 11288 */ 11289 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8 11290 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4 11291 /* The actual VLAN tags to insert/remove */ 11292 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12 11293 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4 11294 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0 11295 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16 11296 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16 11297 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16 11298 /* The number of MAC addresses to add */ 11299 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16 11300 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4 11301 /* MAC addresses to add */ 11302 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20 11303 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6 11304 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4 11305 11306 /* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */ 11307 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4 11308 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0 11309 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4 11310 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0 11311 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1 11312 11313 11314 /***********************************/ 11315 /* MC_CMD_EVB_PORT_QUERY 11316 * read some config of v-port. 11317 */ 11318 #define MC_CMD_EVB_PORT_QUERY 0x62 11319 11320 #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11321 11322 /* MC_CMD_EVB_PORT_QUERY_IN msgrequest */ 11323 #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4 11324 /* The handle of the v-port */ 11325 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0 11326 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 4 11327 11328 /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */ 11329 #define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8 11330 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 11331 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0 11332 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 4 11333 /* The number of VLAN tags that may be used on a v-adaptor connected to this 11334 * EVB port. 11335 */ 11336 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4 11337 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4 11338 11339 11340 /***********************************/ 11341 /* MC_CMD_DUMP_BUFTBL_ENTRIES 11342 * Dump buffer table entries, mainly for command client debug use. Dumps 11343 * absolute entries, and does not use chunk handles. All entries must be in 11344 * range, and used for q page mapping, Although the latter restriction may be 11345 * lifted in future. 11346 */ 11347 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab 11348 11349 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_INSECURE 11350 11351 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ 11352 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 11353 /* Index of the first buffer table entry. */ 11354 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 11355 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4 11356 /* Number of buffer table entries to dump. */ 11357 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 11358 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4 11359 11360 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ 11361 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 11362 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 11363 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) 11364 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ 11365 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 11366 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 11367 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 11368 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 11369 11370 11371 /***********************************/ 11372 /* MC_CMD_SET_RXDP_CONFIG 11373 * Set global RXDP configuration settings 11374 */ 11375 #define MC_CMD_SET_RXDP_CONFIG 0xc1 11376 11377 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11378 11379 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ 11380 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 11381 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 11382 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_LEN 4 11383 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 11384 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 11385 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1 11386 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2 11387 /* enum: pad to 64 bytes */ 11388 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0 11389 /* enum: pad to 128 bytes (Medford only) */ 11390 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1 11391 /* enum: pad to 256 bytes (Medford only) */ 11392 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2 11393 11394 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ 11395 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 11396 11397 11398 /***********************************/ 11399 /* MC_CMD_GET_RXDP_CONFIG 11400 * Get global RXDP configuration settings 11401 */ 11402 #define MC_CMD_GET_RXDP_CONFIG 0xc2 11403 11404 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11405 11406 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ 11407 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 11408 11409 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ 11410 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 11411 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 11412 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_LEN 4 11413 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 11414 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 11415 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1 11416 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2 11417 /* Enum values, see field(s): */ 11418 /* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */ 11419 11420 11421 /***********************************/ 11422 /* MC_CMD_GET_CLOCK 11423 * Return the system and PDCPU clock frequencies. 11424 */ 11425 #define MC_CMD_GET_CLOCK 0xac 11426 11427 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11428 11429 /* MC_CMD_GET_CLOCK_IN msgrequest */ 11430 #define MC_CMD_GET_CLOCK_IN_LEN 0 11431 11432 /* MC_CMD_GET_CLOCK_OUT msgresponse */ 11433 #define MC_CMD_GET_CLOCK_OUT_LEN 8 11434 /* System frequency, MHz */ 11435 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 11436 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4 11437 /* DPCPU frequency, MHz */ 11438 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 11439 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4 11440 11441 11442 /***********************************/ 11443 /* MC_CMD_SET_CLOCK 11444 * Control the system and DPCPU clock frequencies. Changes are lost reboot. 11445 */ 11446 #define MC_CMD_SET_CLOCK 0xad 11447 11448 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_INSECURE 11449 11450 /* MC_CMD_SET_CLOCK_IN msgrequest */ 11451 #define MC_CMD_SET_CLOCK_IN_LEN 28 11452 /* Requested frequency in MHz for system clock domain */ 11453 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 11454 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_LEN 4 11455 /* enum: Leave the system clock domain frequency unchanged */ 11456 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0 11457 /* Requested frequency in MHz for inter-core clock domain */ 11458 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 11459 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_LEN 4 11460 /* enum: Leave the inter-core clock domain frequency unchanged */ 11461 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0 11462 /* Requested frequency in MHz for DPCPU clock domain */ 11463 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 11464 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_LEN 4 11465 /* enum: Leave the DPCPU clock domain frequency unchanged */ 11466 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0 11467 /* Requested frequency in MHz for PCS clock domain */ 11468 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12 11469 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_LEN 4 11470 /* enum: Leave the PCS clock domain frequency unchanged */ 11471 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0 11472 /* Requested frequency in MHz for MC clock domain */ 11473 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16 11474 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_LEN 4 11475 /* enum: Leave the MC clock domain frequency unchanged */ 11476 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0 11477 /* Requested frequency in MHz for rmon clock domain */ 11478 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20 11479 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_LEN 4 11480 /* enum: Leave the rmon clock domain frequency unchanged */ 11481 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0 11482 /* Requested frequency in MHz for vswitch clock domain */ 11483 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24 11484 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_LEN 4 11485 /* enum: Leave the vswitch clock domain frequency unchanged */ 11486 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0 11487 11488 /* MC_CMD_SET_CLOCK_OUT msgresponse */ 11489 #define MC_CMD_SET_CLOCK_OUT_LEN 28 11490 /* Resulting system frequency in MHz */ 11491 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 11492 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_LEN 4 11493 /* enum: The system clock domain doesn't exist */ 11494 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0 11495 /* Resulting inter-core frequency in MHz */ 11496 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 11497 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_LEN 4 11498 /* enum: The inter-core clock domain doesn't exist / isn't used */ 11499 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0 11500 /* Resulting DPCPU frequency in MHz */ 11501 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 11502 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_LEN 4 11503 /* enum: The dpcpu clock domain doesn't exist */ 11504 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0 11505 /* Resulting PCS frequency in MHz */ 11506 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12 11507 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_LEN 4 11508 /* enum: The PCS clock domain doesn't exist / isn't controlled */ 11509 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0 11510 /* Resulting MC frequency in MHz */ 11511 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16 11512 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_LEN 4 11513 /* enum: The MC clock domain doesn't exist / isn't controlled */ 11514 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0 11515 /* Resulting rmon frequency in MHz */ 11516 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20 11517 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_LEN 4 11518 /* enum: The rmon clock domain doesn't exist / isn't controlled */ 11519 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0 11520 /* Resulting vswitch frequency in MHz */ 11521 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24 11522 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_LEN 4 11523 /* enum: The vswitch clock domain doesn't exist / isn't controlled */ 11524 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 11525 11526 11527 /***********************************/ 11528 /* MC_CMD_DPCPU_RPC 11529 * Send an arbitrary DPCPU message. 11530 */ 11531 #define MC_CMD_DPCPU_RPC 0xae 11532 11533 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_INSECURE 11534 11535 /* MC_CMD_DPCPU_RPC_IN msgrequest */ 11536 #define MC_CMD_DPCPU_RPC_IN_LEN 36 11537 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 11538 #define MC_CMD_DPCPU_RPC_IN_CPU_LEN 4 11539 /* enum: RxDPCPU0 */ 11540 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0 11541 /* enum: TxDPCPU0 */ 11542 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 11543 /* enum: TxDPCPU1 */ 11544 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 11545 /* enum: RxDPCPU1 (Medford only) */ 11546 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3 11547 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of 11548 * DPCPU_RX0) 11549 */ 11550 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80 11551 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of 11552 * DPCPU_TX0) 11553 */ 11554 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81 11555 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be 11556 * initialised to zero 11557 */ 11558 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 11559 #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 11560 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 11561 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 11562 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ 11563 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ 11564 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ 11565 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ 11566 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ 11567 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ 11568 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ 11569 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ 11570 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ 11571 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 11572 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 11573 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 11574 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 11575 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 11576 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 11577 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 11578 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 11579 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 11580 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 11581 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ 11582 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ 11583 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ 11584 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ 11585 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ 11586 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 11587 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 11588 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 11589 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 11590 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 11591 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 11592 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 11593 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 11594 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ 11595 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ 11596 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ 11597 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 11598 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 11599 #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 11600 #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 11601 /* Register data to write. Only valid in write/write-read. */ 11602 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 11603 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_LEN 4 11604 /* Register address. */ 11605 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 11606 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_LEN 4 11607 11608 /* MC_CMD_DPCPU_RPC_OUT msgresponse */ 11609 #define MC_CMD_DPCPU_RPC_OUT_LEN 36 11610 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 11611 #define MC_CMD_DPCPU_RPC_OUT_RC_LEN 4 11612 /* DATA */ 11613 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 11614 #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 11615 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 11616 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 11617 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 11618 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 11619 #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 11620 #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 11621 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 11622 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_LEN 4 11623 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 11624 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_LEN 4 11625 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 11626 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_LEN 4 11627 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 11628 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_LEN 4 11629 11630 11631 /***********************************/ 11632 /* MC_CMD_TRIGGER_INTERRUPT 11633 * Trigger an interrupt by prodding the BIU. 11634 */ 11635 #define MC_CMD_TRIGGER_INTERRUPT 0xe3 11636 11637 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11638 11639 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ 11640 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 11641 /* Interrupt level relative to base for function. */ 11642 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 11643 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4 11644 11645 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ 11646 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 11647 11648 11649 /***********************************/ 11650 /* MC_CMD_SHMBOOT_OP 11651 * Special operations to support (for now) shmboot. 11652 */ 11653 #define MC_CMD_SHMBOOT_OP 0xe6 11654 11655 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11656 11657 /* MC_CMD_SHMBOOT_OP_IN msgrequest */ 11658 #define MC_CMD_SHMBOOT_OP_IN_LEN 4 11659 /* Identifies the operation to perform */ 11660 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0 11661 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4 11662 /* enum: Copy slave_data section to the slave core. (Greenport only) */ 11663 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0 11664 11665 /* MC_CMD_SHMBOOT_OP_OUT msgresponse */ 11666 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0 11667 11668 11669 /***********************************/ 11670 /* MC_CMD_CAP_BLK_READ 11671 * Read multiple 64bit words from capture block memory 11672 */ 11673 #define MC_CMD_CAP_BLK_READ 0xe7 11674 11675 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_INSECURE 11676 11677 /* MC_CMD_CAP_BLK_READ_IN msgrequest */ 11678 #define MC_CMD_CAP_BLK_READ_IN_LEN 12 11679 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 11680 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_LEN 4 11681 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 11682 #define MC_CMD_CAP_BLK_READ_IN_ADDR_LEN 4 11683 #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 11684 #define MC_CMD_CAP_BLK_READ_IN_COUNT_LEN 4 11685 11686 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */ 11687 #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 11688 #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 11689 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) 11690 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 11691 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 11692 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 11693 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 11694 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 11695 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 11696 11697 11698 /***********************************/ 11699 /* MC_CMD_DUMP_DO 11700 * Take a dump of the DUT state 11701 */ 11702 #define MC_CMD_DUMP_DO 0xe8 11703 11704 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_INSECURE 11705 11706 /* MC_CMD_DUMP_DO_IN msgrequest */ 11707 #define MC_CMD_DUMP_DO_IN_LEN 52 11708 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 11709 #define MC_CMD_DUMP_DO_IN_PADDING_LEN 4 11710 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 11711 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_LEN 4 11712 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ 11713 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ 11714 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 11715 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4 11716 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ 11717 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ 11718 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ 11719 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ 11720 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 11721 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 11722 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 11723 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4 11724 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 11725 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 11726 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 11727 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 11728 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 11729 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 11730 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ 11731 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 11732 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 11733 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 11734 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 11735 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ 11736 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 11737 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4 11738 /* enum: The uart port this command was received over (if using a uart 11739 * transport) 11740 */ 11741 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff 11742 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 11743 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4 11744 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 11745 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_LEN 4 11746 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ 11747 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ 11748 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 11749 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4 11750 /* Enum values, see field(s): */ 11751 /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 11752 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 11753 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 11754 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 11755 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4 11756 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 11757 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 11758 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 11759 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 11760 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 11761 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 11762 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 11763 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 11764 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 11765 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 11766 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 11767 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4 11768 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 11769 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4 11770 11771 /* MC_CMD_DUMP_DO_OUT msgresponse */ 11772 #define MC_CMD_DUMP_DO_OUT_LEN 4 11773 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 11774 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_LEN 4 11775 11776 11777 /***********************************/ 11778 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED 11779 * Configure unsolicited dumps 11780 */ 11781 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 11782 11783 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_INSECURE 11784 11785 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ 11786 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 11787 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 11788 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_LEN 4 11789 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 11790 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_LEN 4 11791 /* Enum values, see field(s): */ 11792 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ 11793 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 11794 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4 11795 /* Enum values, see field(s): */ 11796 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 11797 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 11798 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 11799 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 11800 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4 11801 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 11802 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 11803 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 11804 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 11805 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 11806 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 11807 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 11808 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 11809 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 11810 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 11811 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 11812 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4 11813 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 11814 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4 11815 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 11816 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_LEN 4 11817 /* Enum values, see field(s): */ 11818 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ 11819 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 11820 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4 11821 /* Enum values, see field(s): */ 11822 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 11823 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 11824 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 11825 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 11826 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4 11827 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 11828 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 11829 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 11830 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 11831 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 11832 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 11833 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 11834 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 11835 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 11836 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 11837 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 11838 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4 11839 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 11840 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4 11841 11842 11843 /***********************************/ 11844 /* MC_CMD_SET_PSU 11845 * Adjusts power supply parameters. This is a warranty-voiding operation. 11846 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if 11847 * the parameter is out of range. 11848 */ 11849 #define MC_CMD_SET_PSU 0xea 11850 11851 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE 11852 11853 /* MC_CMD_SET_PSU_IN msgrequest */ 11854 #define MC_CMD_SET_PSU_IN_LEN 12 11855 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 11856 #define MC_CMD_SET_PSU_IN_PARAM_LEN 4 11857 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ 11858 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 11859 #define MC_CMD_SET_PSU_IN_RAIL_LEN 4 11860 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ 11861 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ 11862 /* desired value, eg voltage in mV */ 11863 #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 11864 #define MC_CMD_SET_PSU_IN_VALUE_LEN 4 11865 11866 /* MC_CMD_SET_PSU_OUT msgresponse */ 11867 #define MC_CMD_SET_PSU_OUT_LEN 0 11868 11869 11870 /***********************************/ 11871 /* MC_CMD_GET_FUNCTION_INFO 11872 * Get function information. PF and VF number. 11873 */ 11874 #define MC_CMD_GET_FUNCTION_INFO 0xec 11875 11876 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11877 11878 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ 11879 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 11880 11881 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ 11882 #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 11883 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 11884 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4 11885 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 11886 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4 11887 11888 11889 /***********************************/ 11890 /* MC_CMD_ENABLE_OFFLINE_BIST 11891 * Enters offline BIST mode. All queues are torn down, chip enters quiescent 11892 * mode, calling function gets exclusive MCDI ownership. The only way out is 11893 * reboot. 11894 */ 11895 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed 11896 11897 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11898 11899 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ 11900 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 11901 11902 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ 11903 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 11904 11905 11906 /***********************************/ 11907 /* MC_CMD_UART_SEND_DATA 11908 * Send checksummed[sic] block of data over the uart. Response is a placeholder 11909 * should we wish to make this reliable; currently requests are fire-and- 11910 * forget. 11911 */ 11912 #define MC_CMD_UART_SEND_DATA 0xee 11913 11914 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11915 11916 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */ 11917 #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 11918 #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 11919 #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) 11920 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ 11921 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 11922 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_LEN 4 11923 /* Offset at which to write the data */ 11924 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 11925 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_LEN 4 11926 /* Length of data */ 11927 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 11928 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_LEN 4 11929 /* Reserved for future use */ 11930 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 11931 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_LEN 4 11932 #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 11933 #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 11934 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 11935 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 11936 11937 /* MC_CMD_UART_SEND_DATA_IN msgresponse */ 11938 #define MC_CMD_UART_SEND_DATA_IN_LEN 0 11939 11940 11941 /***********************************/ 11942 /* MC_CMD_UART_RECV_DATA 11943 * Request checksummed[sic] block of data over the uart. Only a placeholder, 11944 * subject to change and not currently implemented. 11945 */ 11946 #define MC_CMD_UART_RECV_DATA 0xef 11947 11948 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11949 11950 /* MC_CMD_UART_RECV_DATA_OUT msgrequest */ 11951 #define MC_CMD_UART_RECV_DATA_OUT_LEN 16 11952 /* CRC32 over OFFSET, LENGTH, RESERVED */ 11953 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 11954 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_LEN 4 11955 /* Offset from which to read the data */ 11956 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 11957 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_LEN 4 11958 /* Length of data */ 11959 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 11960 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_LEN 4 11961 /* Reserved for future use */ 11962 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 11963 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_LEN 4 11964 11965 /* MC_CMD_UART_RECV_DATA_IN msgresponse */ 11966 #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 11967 #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 11968 #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) 11969 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ 11970 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 11971 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_LEN 4 11972 /* Offset at which to write the data */ 11973 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 11974 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_LEN 4 11975 /* Length of data */ 11976 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 11977 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_LEN 4 11978 /* Reserved for future use */ 11979 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 11980 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_LEN 4 11981 #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 11982 #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 11983 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 11984 #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 11985 11986 11987 /***********************************/ 11988 /* MC_CMD_READ_FUSES 11989 * Read data programmed into the device One-Time-Programmable (OTP) Fuses 11990 */ 11991 #define MC_CMD_READ_FUSES 0xf0 11992 11993 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE 11994 11995 /* MC_CMD_READ_FUSES_IN msgrequest */ 11996 #define MC_CMD_READ_FUSES_IN_LEN 8 11997 /* Offset in OTP to read */ 11998 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 11999 #define MC_CMD_READ_FUSES_IN_OFFSET_LEN 4 12000 /* Length of data to read in bytes */ 12001 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 12002 #define MC_CMD_READ_FUSES_IN_LENGTH_LEN 4 12003 12004 /* MC_CMD_READ_FUSES_OUT msgresponse */ 12005 #define MC_CMD_READ_FUSES_OUT_LENMIN 4 12006 #define MC_CMD_READ_FUSES_OUT_LENMAX 252 12007 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) 12008 /* Length of returned OTP data in bytes */ 12009 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 12010 #define MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4 12011 /* Returned data */ 12012 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 12013 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 12014 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 12015 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 12016 12017 12018 /***********************************/ 12019 /* MC_CMD_KR_TUNE 12020 * Get or set KR Serdes RXEQ and TX Driver settings 12021 */ 12022 #define MC_CMD_KR_TUNE 0xf1 12023 12024 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12025 12026 /* MC_CMD_KR_TUNE_IN msgrequest */ 12027 #define MC_CMD_KR_TUNE_IN_LENMIN 4 12028 #define MC_CMD_KR_TUNE_IN_LENMAX 252 12029 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) 12030 /* Requested operation */ 12031 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 12032 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 12033 /* enum: Get current RXEQ settings */ 12034 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 12035 /* enum: Override RXEQ settings */ 12036 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 12037 /* enum: Get current TX Driver settings */ 12038 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 12039 /* enum: Override TX Driver settings */ 12040 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 12041 /* enum: Force KR Serdes reset / recalibration */ 12042 #define MC_CMD_KR_TUNE_IN_RECAL 0x4 12043 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid 12044 * signal. 12045 */ 12046 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 12047 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The 12048 * caller should call this command repeatedly after starting eye plot, until no 12049 * more data is returned. 12050 */ 12051 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 12052 /* enum: Read Figure Of Merit (eye quality, higher is better). */ 12053 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7 12054 /* Align the arguments to 32 bits */ 12055 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 12056 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 12057 /* Arguments specific to the operation */ 12058 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 12059 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 12060 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 12061 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 12062 12063 /* MC_CMD_KR_TUNE_OUT msgresponse */ 12064 #define MC_CMD_KR_TUNE_OUT_LEN 0 12065 12066 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ 12067 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 12068 /* Requested operation */ 12069 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 12070 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 12071 /* Align the arguments to 32 bits */ 12072 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 12073 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 12074 12075 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ 12076 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 12077 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 12078 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 12079 /* RXEQ Parameter */ 12080 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 12081 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 12082 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 12083 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 12084 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 12085 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 12086 /* enum: Attenuation (0-15, Huntington) */ 12087 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 12088 /* enum: CTLE Boost (0-15, Huntington) */ 12089 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 12090 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max 12091 * positive, Medford - 0-31) 12092 */ 12093 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 12094 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max 12095 * positive, Medford - 0-31) 12096 */ 12097 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 12098 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max 12099 * positive, Medford - 0-16) 12100 */ 12101 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 12102 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max 12103 * positive, Medford - 0-16) 12104 */ 12105 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 12106 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max 12107 * positive, Medford - 0-16) 12108 */ 12109 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 12110 /* enum: Edge DFE DLEV (0-128 for Medford) */ 12111 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 12112 /* enum: Variable Gain Amplifier (0-15, Medford) */ 12113 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8 12114 /* enum: CTLE EQ Capacitor (0-15, Medford) */ 12115 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 12116 /* enum: CTLE EQ Resistor (0-7, Medford) */ 12117 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 12118 /* enum: CTLE gain (0-31, Medford2) */ 12119 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN 0xb 12120 /* enum: CTLE pole (0-31, Medford2) */ 12121 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc 12122 /* enum: CTLE peaking (0-31, Medford2) */ 12123 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd 12124 /* enum: DFE Tap1 - even path (Medford2 - 6 bit signed (-29 - +29)) */ 12125 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe 12126 /* enum: DFE Tap1 - odd path (Medford2 - 6 bit signed (-29 - +29)) */ 12127 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf 12128 /* enum: DFE Tap2 (Medford2 - 6 bit signed (-20 - +20)) */ 12129 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10 12130 /* enum: DFE Tap3 (Medford2 - 6 bit signed (-20 - +20)) */ 12131 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11 12132 /* enum: DFE Tap4 (Medford2 - 6 bit signed (-20 - +20)) */ 12133 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12 12134 /* enum: DFE Tap5 (Medford2 - 6 bit signed (-24 - +24)) */ 12135 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13 12136 /* enum: DFE Tap6 (Medford2 - 6 bit signed (-24 - +24)) */ 12137 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14 12138 /* enum: DFE Tap7 (Medford2 - 6 bit signed (-24 - +24)) */ 12139 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15 12140 /* enum: DFE Tap8 (Medford2 - 6 bit signed (-24 - +24)) */ 12141 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16 12142 /* enum: DFE Tap9 (Medford2 - 6 bit signed (-24 - +24)) */ 12143 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17 12144 /* enum: DFE Tap10 (Medford2 - 6 bit signed (-24 - +24)) */ 12145 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18 12146 /* enum: DFE Tap11 (Medford2 - 6 bit signed (-24 - +24)) */ 12147 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19 12148 /* enum: DFE Tap12 (Medford2 - 6 bit signed (-24 - +24)) */ 12149 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a 12150 /* enum: I/Q clk offset (Medford2 - 4 bit signed (-5 - +5))) */ 12151 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b 12152 /* enum: Negative h1 polarity data sampler offset calibration code, even path 12153 * (Medford2 - 6 bit signed (-29 - +29))) 12154 */ 12155 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_EVEN 0x1c 12156 /* enum: Negative h1 polarity data sampler offset calibration code, odd path 12157 * (Medford2 - 6 bit signed (-29 - +29))) 12158 */ 12159 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_ODD 0x1d 12160 /* enum: Positive h1 polarity data sampler offset calibration code, even path 12161 * (Medford2 - 6 bit signed (-29 - +29))) 12162 */ 12163 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_EVEN 0x1e 12164 /* enum: Positive h1 polarity data sampler offset calibration code, odd path 12165 * (Medford2 - 6 bit signed (-29 - +29))) 12166 */ 12167 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_ODD 0x1f 12168 /* enum: CDR calibration loop code (Medford2) */ 12169 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_PVT 0x20 12170 /* enum: CDR integral loop code (Medford2) */ 12171 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_INTEG 0x21 12172 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 12173 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 12174 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 12175 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 12176 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 12177 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 12178 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 12179 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 12180 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 12181 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 12182 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 12183 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 12184 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 12185 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 12186 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 12187 12188 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ 12189 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 12190 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 12191 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 12192 /* Requested operation */ 12193 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 12194 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 12195 /* Align the arguments to 32 bits */ 12196 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 12197 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 12198 /* RXEQ Parameter */ 12199 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 12200 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 12201 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 12202 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 12203 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 12204 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 12205 /* Enum values, see field(s): */ 12206 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ 12207 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 12208 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 12209 /* Enum values, see field(s): */ 12210 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 12211 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 12212 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 12213 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 12214 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 12215 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 12216 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 12217 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 12218 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 12219 12220 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ 12221 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 12222 12223 /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ 12224 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 12225 /* Requested operation */ 12226 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 12227 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 12228 /* Align the arguments to 32 bits */ 12229 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 12230 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 12231 12232 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ 12233 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 12234 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 12235 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 12236 /* TXEQ Parameter */ 12237 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 12238 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 12239 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 12240 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 12241 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 12242 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 12243 /* enum: TX Amplitude (Huntington, Medford, Medford2) */ 12244 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 12245 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */ 12246 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 12247 /* enum: De-Emphasis Tap1 Fine */ 12248 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 12249 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */ 12250 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 12251 /* enum: De-Emphasis Tap2 Fine (Huntington) */ 12252 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 12253 /* enum: Pre-Emphasis Magnitude (Huntington) */ 12254 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 12255 /* enum: Pre-Emphasis Fine (Huntington) */ 12256 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 12257 /* enum: TX Slew Rate Coarse control (Huntington) */ 12258 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 12259 /* enum: TX Slew Rate Fine control (Huntington) */ 12260 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 12261 /* enum: TX Termination Impedance control (Huntington) */ 12262 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 12263 /* enum: TX Amplitude Fine control (Medford) */ 12264 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa 12265 /* enum: Pre-shoot Tap (Medford, Medford2) */ 12266 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb 12267 /* enum: De-emphasis Tap (Medford, Medford2) */ 12268 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc 12269 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 12270 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 12271 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ 12272 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ 12273 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ 12274 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ 12275 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 12276 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 12277 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 12278 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 12279 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 12280 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 12281 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 12282 12283 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ 12284 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 12285 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 12286 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) 12287 /* Requested operation */ 12288 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 12289 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 12290 /* Align the arguments to 32 bits */ 12291 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 12292 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 12293 /* TXEQ Parameter */ 12294 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 12295 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 12296 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 12297 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 12298 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 12299 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 12300 /* Enum values, see field(s): */ 12301 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ 12302 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 12303 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 12304 /* Enum values, see field(s): */ 12305 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ 12306 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 12307 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 12308 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 12309 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 12310 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 12311 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 12312 12313 /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ 12314 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 12315 12316 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ 12317 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 12318 /* Requested operation */ 12319 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 12320 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 12321 /* Align the arguments to 32 bits */ 12322 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 12323 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 12324 12325 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ 12326 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 12327 12328 /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ 12329 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 12330 /* Requested operation */ 12331 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 12332 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 12333 /* Align the arguments to 32 bits */ 12334 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 12335 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 12336 /* Port-relative lane to scan eye on */ 12337 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 12338 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_LEN 4 12339 12340 /* MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN msgrequest */ 12341 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LEN 12 12342 /* Requested operation */ 12343 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_OFST 0 12344 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_LEN 1 12345 /* Align the arguments to 32 bits */ 12346 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_OFST 1 12347 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_LEN 3 12348 /* Port-relative lane to scan eye on */ 12349 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4 12350 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4 12351 /* Scan duration / cycle count */ 12352 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_OFST 8 12353 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4 12354 12355 /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ 12356 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 12357 12358 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ 12359 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 12360 /* Requested operation */ 12361 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 12362 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 12363 /* Align the arguments to 32 bits */ 12364 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 12365 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 12366 12367 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 12368 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 12369 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 12370 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 12371 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 12372 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 12373 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 12374 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 12375 12376 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */ 12377 #define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8 12378 /* Requested operation */ 12379 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0 12380 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1 12381 /* Align the arguments to 32 bits */ 12382 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1 12383 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3 12384 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4 12385 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4 12386 12387 /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */ 12388 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4 12389 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0 12390 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4 12391 12392 12393 /***********************************/ 12394 /* MC_CMD_PCIE_TUNE 12395 * Get or set PCIE Serdes RXEQ and TX Driver settings 12396 */ 12397 #define MC_CMD_PCIE_TUNE 0xf2 12398 12399 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12400 12401 /* MC_CMD_PCIE_TUNE_IN msgrequest */ 12402 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 12403 #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 12404 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) 12405 /* Requested operation */ 12406 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 12407 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 12408 /* enum: Get current RXEQ settings */ 12409 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 12410 /* enum: Override RXEQ settings */ 12411 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 12412 /* enum: Get current TX Driver settings */ 12413 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 12414 /* enum: Override TX Driver settings */ 12415 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 12416 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ 12417 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 12418 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The 12419 * caller should call this command repeatedly after starting eye plot, until no 12420 * more data is returned. 12421 */ 12422 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 12423 /* enum: Enable the SERDES BIST and set it to generate a 200MHz square wave */ 12424 #define MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7 12425 /* Align the arguments to 32 bits */ 12426 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 12427 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 12428 /* Arguments specific to the operation */ 12429 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 12430 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 12431 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 12432 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 12433 12434 /* MC_CMD_PCIE_TUNE_OUT msgresponse */ 12435 #define MC_CMD_PCIE_TUNE_OUT_LEN 0 12436 12437 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ 12438 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 12439 /* Requested operation */ 12440 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 12441 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 12442 /* Align the arguments to 32 bits */ 12443 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 12444 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 12445 12446 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ 12447 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 12448 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 12449 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 12450 /* RXEQ Parameter */ 12451 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 12452 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 12453 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 12454 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 12455 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 12456 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 12457 /* enum: Attenuation (0-15) */ 12458 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 12459 /* enum: CTLE Boost (0-15) */ 12460 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 12461 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 12462 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 12463 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 12464 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 12465 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 12466 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 12467 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 12468 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 12469 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 12470 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 12471 /* enum: DFE DLev */ 12472 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7 12473 /* enum: Figure of Merit */ 12474 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8 12475 /* enum: CTLE EQ Capacitor (HF Gain) */ 12476 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 12477 /* enum: CTLE EQ Resistor (DC Gain) */ 12478 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 12479 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 12480 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5 12481 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 12482 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 12483 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 12484 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 12485 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ 12486 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ 12487 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ 12488 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ 12489 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */ 12490 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */ 12491 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */ 12492 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */ 12493 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */ 12494 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */ 12495 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */ 12496 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */ 12497 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */ 12498 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13 12499 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 12500 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14 12501 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10 12502 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 12503 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 12504 12505 /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */ 12506 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8 12507 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252 12508 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 12509 /* Requested operation */ 12510 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0 12511 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1 12512 /* Align the arguments to 32 bits */ 12513 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1 12514 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3 12515 /* RXEQ Parameter */ 12516 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4 12517 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4 12518 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 12519 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 12520 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 12521 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 12522 /* Enum values, see field(s): */ 12523 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */ 12524 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 12525 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5 12526 /* Enum values, see field(s): */ 12527 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 12528 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13 12529 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 12530 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14 12531 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2 12532 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 12533 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 12534 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 12535 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 12536 12537 /* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */ 12538 #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0 12539 12540 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ 12541 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 12542 /* Requested operation */ 12543 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 12544 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 12545 /* Align the arguments to 32 bits */ 12546 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 12547 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 12548 12549 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ 12550 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 12551 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 12552 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 12553 /* RXEQ Parameter */ 12554 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 12555 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 12556 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 12557 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 12558 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 12559 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 12560 /* enum: TxMargin (PIPE) */ 12561 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 12562 /* enum: TxSwing (PIPE) */ 12563 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 12564 /* enum: De-emphasis coefficient C(-1) (PIPE) */ 12565 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 12566 /* enum: De-emphasis coefficient C(0) (PIPE) */ 12567 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 12568 /* enum: De-emphasis coefficient C(+1) (PIPE) */ 12569 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 12570 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 12571 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 12572 /* Enum values, see field(s): */ 12573 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 12574 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 12575 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 12576 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 12577 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 12578 12579 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ 12580 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 12581 /* Requested operation */ 12582 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 12583 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 12584 /* Align the arguments to 32 bits */ 12585 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 12586 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 12587 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 12588 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_LEN 4 12589 12590 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ 12591 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 12592 12593 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ 12594 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 12595 /* Requested operation */ 12596 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 12597 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 12598 /* Align the arguments to 32 bits */ 12599 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 12600 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 12601 12602 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 12603 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 12604 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 12605 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 12606 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 12607 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 12608 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 12609 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 12610 12611 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN msgrequest */ 12612 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0 12613 12614 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT msgrequest */ 12615 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0 12616 12617 12618 /***********************************/ 12619 /* MC_CMD_LICENSING 12620 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 12621 * - not used for V3 licensing 12622 */ 12623 #define MC_CMD_LICENSING 0xf3 12624 12625 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12626 12627 /* MC_CMD_LICENSING_IN msgrequest */ 12628 #define MC_CMD_LICENSING_IN_LEN 4 12629 /* identifies the type of operation requested */ 12630 #define MC_CMD_LICENSING_IN_OP_OFST 0 12631 #define MC_CMD_LICENSING_IN_OP_LEN 4 12632 /* enum: re-read and apply licenses after a license key partition update; note 12633 * that this operation returns a zero-length response 12634 */ 12635 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 12636 /* enum: report counts of installed licenses */ 12637 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 12638 12639 /* MC_CMD_LICENSING_OUT msgresponse */ 12640 #define MC_CMD_LICENSING_OUT_LEN 28 12641 /* count of application keys which are valid */ 12642 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 12643 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4 12644 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with 12645 * MC_CMD_FC_OP_LICENSE) 12646 */ 12647 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 12648 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4 12649 /* count of application keys which are invalid due to being blacklisted */ 12650 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 12651 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4 12652 /* count of application keys which are invalid due to being unverifiable */ 12653 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 12654 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4 12655 /* count of application keys which are invalid due to being for the wrong node 12656 */ 12657 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 12658 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4 12659 /* licensing state (for diagnostics; the exact meaning of the bits in this 12660 * field are private to the firmware) 12661 */ 12662 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 12663 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4 12664 /* licensing subsystem self-test report (for manftest) */ 12665 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 12666 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4 12667 /* enum: licensing subsystem self-test failed */ 12668 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 12669 /* enum: licensing subsystem self-test passed */ 12670 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 12671 12672 12673 /***********************************/ 12674 /* MC_CMD_LICENSING_V3 12675 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 12676 * - V3 licensing (Medford) 12677 */ 12678 #define MC_CMD_LICENSING_V3 0xd0 12679 12680 #define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12681 12682 /* MC_CMD_LICENSING_V3_IN msgrequest */ 12683 #define MC_CMD_LICENSING_V3_IN_LEN 4 12684 /* identifies the type of operation requested */ 12685 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0 12686 #define MC_CMD_LICENSING_V3_IN_OP_LEN 4 12687 /* enum: re-read and apply licenses after a license key partition update; note 12688 * that this operation returns a zero-length response 12689 */ 12690 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0 12691 /* enum: report counts of installed licenses Returns EAGAIN if license 12692 * processing (updating) has been started but not yet completed. 12693 */ 12694 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1 12695 12696 /* MC_CMD_LICENSING_V3_OUT msgresponse */ 12697 #define MC_CMD_LICENSING_V3_OUT_LEN 88 12698 /* count of keys which are valid */ 12699 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0 12700 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4 12701 /* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with 12702 * MC_CMD_FC_OP_LICENSE) 12703 */ 12704 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4 12705 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4 12706 /* count of keys which are invalid due to being unverifiable */ 12707 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8 12708 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4 12709 /* count of keys which are invalid due to being for the wrong node */ 12710 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12 12711 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4 12712 /* licensing state (for diagnostics; the exact meaning of the bits in this 12713 * field are private to the firmware) 12714 */ 12715 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16 12716 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4 12717 /* licensing subsystem self-test report (for manftest) */ 12718 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20 12719 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4 12720 /* enum: licensing subsystem self-test failed */ 12721 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0 12722 /* enum: licensing subsystem self-test passed */ 12723 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1 12724 /* bitmask of licensed applications */ 12725 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24 12726 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8 12727 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24 12728 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28 12729 /* reserved for future use */ 12730 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32 12731 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24 12732 /* bitmask of licensed features */ 12733 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56 12734 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8 12735 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56 12736 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60 12737 /* reserved for future use */ 12738 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64 12739 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24 12740 12741 12742 /***********************************/ 12743 /* MC_CMD_LICENSING_GET_ID_V3 12744 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license 12745 * partition - V3 licensing (Medford) 12746 */ 12747 #define MC_CMD_LICENSING_GET_ID_V3 0xd1 12748 12749 #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12750 12751 /* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */ 12752 #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0 12753 12754 /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */ 12755 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8 12756 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252 12757 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num)) 12758 /* type of license (eg 3) */ 12759 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0 12760 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4 12761 /* length of the license ID (in bytes) */ 12762 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4 12763 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 4 12764 /* the unique license ID of the adapter */ 12765 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8 12766 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1 12767 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0 12768 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244 12769 12770 12771 /***********************************/ 12772 /* MC_CMD_MC2MC_PROXY 12773 * Execute an arbitrary MCDI command on the slave MC of a dual-core device. 12774 * This will fail on a single-core system. 12775 */ 12776 #define MC_CMD_MC2MC_PROXY 0xf4 12777 12778 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12779 12780 /* MC_CMD_MC2MC_PROXY_IN msgrequest */ 12781 #define MC_CMD_MC2MC_PROXY_IN_LEN 0 12782 12783 /* MC_CMD_MC2MC_PROXY_OUT msgresponse */ 12784 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0 12785 12786 12787 /***********************************/ 12788 /* MC_CMD_GET_LICENSED_APP_STATE 12789 * Query the state of an individual licensed application. (Note that the actual 12790 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation 12791 * or a reboot of the MC.) Not used for V3 licensing 12792 */ 12793 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5 12794 12795 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12796 12797 /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ 12798 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 12799 /* application ID to query (LICENSED_APP_ID_xxx) */ 12800 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 12801 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4 12802 12803 /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ 12804 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 12805 /* state of this application */ 12806 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 12807 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4 12808 /* enum: no (or invalid) license is present for the application */ 12809 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 12810 /* enum: a valid license is present for the application */ 12811 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 12812 12813 12814 /***********************************/ 12815 /* MC_CMD_GET_LICENSED_V3_APP_STATE 12816 * Query the state of an individual licensed application. (Note that the actual 12817 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 12818 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 12819 */ 12820 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2 12821 12822 #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12823 12824 /* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */ 12825 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8 12826 /* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit 12827 * mask 12828 */ 12829 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0 12830 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8 12831 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0 12832 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4 12833 12834 /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */ 12835 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4 12836 /* state of this application */ 12837 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0 12838 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4 12839 /* enum: no (or invalid) license is present for the application */ 12840 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0 12841 /* enum: a valid license is present for the application */ 12842 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1 12843 12844 12845 /***********************************/ 12846 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES 12847 * Query the state of one or more licensed features. (Note that the actual 12848 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 12849 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 12850 */ 12851 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3 12852 12853 #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12854 12855 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */ 12856 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8 12857 /* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or 12858 * more bits set 12859 */ 12860 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0 12861 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8 12862 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0 12863 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4 12864 12865 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */ 12866 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8 12867 /* states of these features - bit set for licensed, clear for not licensed */ 12868 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0 12869 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8 12870 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0 12871 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4 12872 12873 12874 /***********************************/ 12875 /* MC_CMD_LICENSED_APP_OP 12876 * Perform an action for an individual licensed application - not used for V3 12877 * licensing. 12878 */ 12879 #define MC_CMD_LICENSED_APP_OP 0xf6 12880 12881 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12882 12883 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */ 12884 #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 12885 #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 12886 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) 12887 /* application ID */ 12888 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 12889 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4 12890 /* the type of operation requested */ 12891 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 12892 #define MC_CMD_LICENSED_APP_OP_IN_OP_LEN 4 12893 /* enum: validate application */ 12894 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 12895 /* enum: mask application */ 12896 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1 12897 /* arguments specific to this particular operation */ 12898 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 12899 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 12900 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 12901 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 12902 12903 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ 12904 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 12905 #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 12906 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) 12907 /* result specific to this particular operation */ 12908 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 12909 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 12910 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 12911 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 12912 12913 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ 12914 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 12915 /* application ID */ 12916 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 12917 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 4 12918 /* the type of operation requested */ 12919 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 12920 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 4 12921 /* validation challenge */ 12922 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 12923 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 12924 12925 /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ 12926 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 12927 /* feature expiry (time_t) */ 12928 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 12929 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 4 12930 /* validation response */ 12931 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 12932 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 12933 12934 /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */ 12935 #define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12 12936 /* application ID */ 12937 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0 12938 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 4 12939 /* the type of operation requested */ 12940 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4 12941 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 4 12942 /* flag */ 12943 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8 12944 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 4 12945 12946 /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ 12947 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 12948 12949 12950 /***********************************/ 12951 /* MC_CMD_LICENSED_V3_VALIDATE_APP 12952 * Perform validation for an individual licensed application - V3 licensing 12953 * (Medford) 12954 */ 12955 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4 12956 12957 #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12958 12959 /* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */ 12960 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 56 12961 /* challenge for validation (384 bits) */ 12962 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0 12963 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 48 12964 /* application ID expressed as a single bit mask */ 12965 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48 12966 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8 12967 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48 12968 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52 12969 12970 /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */ 12971 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116 12972 /* validation response to challenge in the form of ECDSA signature consisting 12973 * of two 384-bit integers, r and s, in big-endian order. The signature signs a 12974 * SHA-384 digest of a message constructed from the concatenation of the input 12975 * message and the remaining fields of this output message, e.g. challenge[48 12976 * bytes] ... expiry_time[4 bytes] ... 12977 */ 12978 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0 12979 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96 12980 /* application expiry time */ 12981 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96 12982 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 4 12983 /* application expiry units */ 12984 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100 12985 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4 12986 /* enum: expiry units are accounting units */ 12987 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0 12988 /* enum: expiry units are calendar days */ 12989 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1 12990 /* base MAC address of the NIC stored in NVRAM (note that this is a constant 12991 * value for a given NIC regardless which function is calling, effectively this 12992 * is PF0 base MAC address) 12993 */ 12994 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_OFST 104 12995 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_LEN 6 12996 /* MAC address of v-adaptor associated with the client. If no such v-adapator 12997 * exists, then the field is filled with 0xFF. 12998 */ 12999 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 110 13000 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 6 13001 13002 13003 /***********************************/ 13004 /* MC_CMD_LICENSED_V3_MASK_FEATURES 13005 * Mask features - V3 licensing (Medford) 13006 */ 13007 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5 13008 13009 #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13010 13011 /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */ 13012 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12 13013 /* mask to be applied to features to be changed */ 13014 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0 13015 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8 13016 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0 13017 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4 13018 /* whether to turn on or turn off the masked features */ 13019 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8 13020 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4 13021 /* enum: turn the features off */ 13022 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0 13023 /* enum: turn the features back on */ 13024 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1 13025 13026 /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */ 13027 #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0 13028 13029 13030 /***********************************/ 13031 /* MC_CMD_LICENSING_V3_TEMPORARY 13032 * Perform operations to support installation of a single temporary license in 13033 * the adapter, in addition to those found in the licensing partition. See 13034 * SF-116124-SW for an overview of how this could be used. The license is 13035 * stored in MC persistent data and so will survive a MC reboot, but will be 13036 * erased when the adapter is power cycled 13037 */ 13038 #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6 13039 13040 #define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13041 13042 /* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */ 13043 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4 13044 /* operation code */ 13045 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0 13046 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 4 13047 /* enum: install a new license, overwriting any existing temporary license. 13048 * This is an asynchronous operation owing to the time taken to validate an 13049 * ECDSA license 13050 */ 13051 #define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0 13052 /* enum: clear the license immediately rather than waiting for the next power 13053 * cycle 13054 */ 13055 #define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1 13056 /* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET 13057 * operation 13058 */ 13059 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2 13060 13061 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */ 13062 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164 13063 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0 13064 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 4 13065 /* ECDSA license and signature */ 13066 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4 13067 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160 13068 13069 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */ 13070 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4 13071 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0 13072 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 4 13073 13074 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */ 13075 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4 13076 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0 13077 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 4 13078 13079 /* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */ 13080 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12 13081 /* status code */ 13082 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0 13083 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4 13084 /* enum: finished validating and installing license */ 13085 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0 13086 /* enum: license validation and installation in progress */ 13087 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1 13088 /* enum: licensing error. More specific error messages are not provided to 13089 * avoid exposing details of the licensing system to the client 13090 */ 13091 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2 13092 /* bitmask of licensed features */ 13093 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4 13094 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8 13095 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4 13096 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8 13097 13098 13099 /***********************************/ 13100 /* MC_CMD_SET_PORT_SNIFF_CONFIG 13101 * Configure RX port sniffing for the physical port associated with the calling 13102 * function. Only a privileged function may change the port sniffing 13103 * configuration. A copy of all traffic delivered to the host (non-promiscuous 13104 * mode) or all traffic arriving at the port (promiscuous mode) may be 13105 * delivered to a specific queue, or a set of queues with RSS. 13106 */ 13107 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 13108 13109 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13110 13111 /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ 13112 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 13113 /* configuration flags */ 13114 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 13115 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4 13116 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 13117 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 13118 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 13119 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 13120 /* receive queue handle (for RSS mode, this is the base queue) */ 13121 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 13122 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4 13123 /* receive mode */ 13124 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 13125 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4 13126 /* enum: receive to just the specified queue */ 13127 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 13128 /* enum: receive to multiple queues using RSS context */ 13129 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 13130 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 13131 * that these handles should be considered opaque to the host, although a value 13132 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 13133 */ 13134 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 13135 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4 13136 13137 /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ 13138 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 13139 13140 13141 /***********************************/ 13142 /* MC_CMD_GET_PORT_SNIFF_CONFIG 13143 * Obtain the current RX port sniffing configuration for the physical port 13144 * associated with the calling function. Only a privileged function may read 13145 * the configuration. 13146 */ 13147 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 13148 13149 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13150 13151 /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ 13152 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 13153 13154 /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ 13155 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 13156 /* configuration flags */ 13157 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 13158 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4 13159 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 13160 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 13161 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 13162 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 13163 /* receiving queue handle (for RSS mode, this is the base queue) */ 13164 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 13165 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4 13166 /* receive mode */ 13167 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 13168 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4 13169 /* enum: receiving to just the specified queue */ 13170 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 13171 /* enum: receiving to multiple queues using RSS context */ 13172 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 13173 /* RSS context (for RX_MODE_RSS) */ 13174 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 13175 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4 13176 13177 13178 /***********************************/ 13179 /* MC_CMD_SET_PARSER_DISP_CONFIG 13180 * Change configuration related to the parser-dispatcher subsystem. 13181 */ 13182 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9 13183 13184 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13185 13186 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */ 13187 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12 13188 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252 13189 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num)) 13190 /* the type of configuration setting to change */ 13191 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 13192 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4 13193 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible 13194 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.) 13195 */ 13196 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0 13197 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the 13198 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single 13199 * boolean.) 13200 */ 13201 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1 13202 /* handle for the entity to update: queue handle, EVB port ID, etc. depending 13203 * on the type of configuration setting being changed 13204 */ 13205 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 13206 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4 13207 /* new value: the details depend on the type of configuration setting being 13208 * changed 13209 */ 13210 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8 13211 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4 13212 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1 13213 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61 13214 13215 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ 13216 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 13217 13218 13219 /***********************************/ 13220 /* MC_CMD_GET_PARSER_DISP_CONFIG 13221 * Read configuration related to the parser-dispatcher subsystem. 13222 */ 13223 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa 13224 13225 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13226 13227 /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */ 13228 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8 13229 /* the type of configuration setting to read */ 13230 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 13231 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4 13232 /* Enum values, see field(s): */ 13233 /* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */ 13234 /* handle for the entity to query: queue handle, EVB port ID, etc. depending on 13235 * the type of configuration setting being read 13236 */ 13237 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 13238 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4 13239 13240 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */ 13241 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4 13242 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252 13243 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) 13244 /* current value: the details depend on the type of configuration setting being 13245 * read 13246 */ 13247 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0 13248 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4 13249 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 13250 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 13251 13252 13253 /***********************************/ 13254 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG 13255 * Configure TX port sniffing for the physical port associated with the calling 13256 * function. Only a privileged function may change the port sniffing 13257 * configuration. A copy of all traffic transmitted through the port may be 13258 * delivered to a specific queue, or a set of queues with RSS. Note that these 13259 * packets are delivered with transmit timestamps in the packet prefix, not 13260 * receive timestamps, so it is likely that the queue(s) will need to be 13261 * dedicated as TX sniff receivers. 13262 */ 13263 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb 13264 13265 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13266 13267 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 13268 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16 13269 /* configuration flags */ 13270 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 13271 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4 13272 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 13273 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 13274 /* receive queue handle (for RSS mode, this is the base queue) */ 13275 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 13276 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4 13277 /* receive mode */ 13278 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 13279 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4 13280 /* enum: receive to just the specified queue */ 13281 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 13282 /* enum: receive to multiple queues using RSS context */ 13283 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 13284 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 13285 * that these handles should be considered opaque to the host, although a value 13286 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 13287 */ 13288 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 13289 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4 13290 13291 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 13292 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 13293 13294 13295 /***********************************/ 13296 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG 13297 * Obtain the current TX port sniffing configuration for the physical port 13298 * associated with the calling function. Only a privileged function may read 13299 * the configuration. 13300 */ 13301 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc 13302 13303 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13304 13305 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 13306 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0 13307 13308 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 13309 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16 13310 /* configuration flags */ 13311 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 13312 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4 13313 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 13314 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 13315 /* receiving queue handle (for RSS mode, this is the base queue) */ 13316 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 13317 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4 13318 /* receive mode */ 13319 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 13320 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4 13321 /* enum: receiving to just the specified queue */ 13322 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 13323 /* enum: receiving to multiple queues using RSS context */ 13324 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 13325 /* RSS context (for RX_MODE_RSS) */ 13326 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 13327 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4 13328 13329 13330 /***********************************/ 13331 /* MC_CMD_RMON_STATS_RX_ERRORS 13332 * Per queue rx error stats. 13333 */ 13334 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe 13335 13336 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13337 13338 /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */ 13339 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8 13340 /* The rx queue to get stats for. */ 13341 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0 13342 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_LEN 4 13343 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4 13344 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_LEN 4 13345 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0 13346 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1 13347 13348 /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */ 13349 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16 13350 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0 13351 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_LEN 4 13352 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4 13353 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_LEN 4 13354 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8 13355 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_LEN 4 13356 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 13357 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_LEN 4 13358 13359 13360 /***********************************/ 13361 /* MC_CMD_GET_PCIE_RESOURCE_INFO 13362 * Find out about available PCIE resources 13363 */ 13364 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd 13365 13366 #define MC_CMD_0xfd_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13367 13368 /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */ 13369 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0 13370 13371 /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */ 13372 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28 13373 /* The maximum number of PFs the device can expose */ 13374 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0 13375 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_LEN 4 13376 /* The maximum number of VFs the device can expose in total */ 13377 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4 13378 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_LEN 4 13379 /* The maximum number of MSI-X vectors the device can provide in total */ 13380 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8 13381 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_LEN 4 13382 /* the number of MSI-X vectors the device will allocate by default to each PF 13383 */ 13384 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12 13385 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_LEN 4 13386 /* the number of MSI-X vectors the device will allocate by default to each VF 13387 */ 13388 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16 13389 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_LEN 4 13390 /* the maximum number of MSI-X vectors the device can allocate to any one PF */ 13391 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20 13392 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_LEN 4 13393 /* the maximum number of MSI-X vectors the device can allocate to any one VF */ 13394 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 13395 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_LEN 4 13396 13397 13398 /***********************************/ 13399 /* MC_CMD_GET_PORT_MODES 13400 * Find out about available port modes 13401 */ 13402 #define MC_CMD_GET_PORT_MODES 0xff 13403 13404 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13405 13406 /* MC_CMD_GET_PORT_MODES_IN msgrequest */ 13407 #define MC_CMD_GET_PORT_MODES_IN_LEN 0 13408 13409 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */ 13410 #define MC_CMD_GET_PORT_MODES_OUT_LEN 12 13411 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */ 13412 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0 13413 #define MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4 13414 /* Default (canonical) board mode */ 13415 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4 13416 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 4 13417 /* Current board mode */ 13418 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 13419 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4 13420 13421 13422 /***********************************/ 13423 /* MC_CMD_READ_ATB 13424 * Sample voltages on the ATB 13425 */ 13426 #define MC_CMD_READ_ATB 0x100 13427 13428 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13429 13430 /* MC_CMD_READ_ATB_IN msgrequest */ 13431 #define MC_CMD_READ_ATB_IN_LEN 16 13432 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0 13433 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_LEN 4 13434 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */ 13435 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */ 13436 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */ 13437 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4 13438 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_LEN 4 13439 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8 13440 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_LEN 4 13441 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12 13442 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_LEN 4 13443 13444 /* MC_CMD_READ_ATB_OUT msgresponse */ 13445 #define MC_CMD_READ_ATB_OUT_LEN 4 13446 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 13447 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_LEN 4 13448 13449 13450 /***********************************/ 13451 /* MC_CMD_GET_WORKAROUNDS 13452 * Read the list of all implemented and all currently enabled workarounds. The 13453 * enums here must correspond with those in MC_CMD_WORKAROUND. 13454 */ 13455 #define MC_CMD_GET_WORKAROUNDS 0x59 13456 13457 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13458 13459 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */ 13460 #define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8 13461 /* Each workaround is represented by a single bit according to the enums below. 13462 */ 13463 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0 13464 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4 13465 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4 13466 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4 13467 /* enum: Bug 17230 work around. */ 13468 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2 13469 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 13470 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4 13471 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 13472 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8 13473 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 13474 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10 13475 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 13476 * - before adding code that queries this workaround, remember that there's 13477 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 13478 * and will hence (incorrectly) report that the bug doesn't exist. 13479 */ 13480 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20 13481 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */ 13482 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40 13483 /* enum: Bug 61265 work around (broken EVQ TMR writes). */ 13484 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80 13485 13486 13487 /***********************************/ 13488 /* MC_CMD_PRIVILEGE_MASK 13489 * Read/set privileges of an arbitrary PCIe function 13490 */ 13491 #define MC_CMD_PRIVILEGE_MASK 0x5a 13492 13493 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13494 13495 /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */ 13496 #define MC_CMD_PRIVILEGE_MASK_IN_LEN 8 13497 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF 13498 * 1,3 = 0x00030001 13499 */ 13500 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0 13501 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4 13502 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0 13503 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16 13504 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16 13505 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16 13506 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */ 13507 /* New privilege mask to be set. The mask will only be changed if the MSB is 13508 * set to 1. 13509 */ 13510 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4 13511 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4 13512 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */ 13513 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */ 13514 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */ 13515 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */ 13516 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */ 13517 /* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */ 13518 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 13519 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */ 13520 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */ 13521 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */ 13522 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */ 13523 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */ 13524 /* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC 13525 * adress. 13526 */ 13527 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800 13528 /* enum: Privilege that allows a Function to change the MAC address configured 13529 * in its associated vAdapter/vPort. 13530 */ 13531 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000 13532 /* enum: Privilege that allows a Function to install filters that specify VLANs 13533 * that are not in the permit list for the associated vPort. This privilege is 13534 * primarily to support ESX where vPorts are created that restrict traffic to 13535 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT. 13536 */ 13537 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000 13538 /* enum: Privilege for insecure commands. Commands that belong to this group 13539 * are not permitted on secure adapters regardless of the privilege mask. 13540 */ 13541 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000 13542 /* enum: Set this bit to indicate that a new privilege mask is to be set, 13543 * otherwise the command will only read the existing mask. 13544 */ 13545 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000 13546 13547 /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */ 13548 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4 13549 /* For an admin function, always all the privileges are reported. */ 13550 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0 13551 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4 13552 13553 13554 /***********************************/ 13555 /* MC_CMD_LINK_STATE_MODE 13556 * Read/set link state mode of a VF 13557 */ 13558 #define MC_CMD_LINK_STATE_MODE 0x5c 13559 13560 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13561 13562 /* MC_CMD_LINK_STATE_MODE_IN msgrequest */ 13563 #define MC_CMD_LINK_STATE_MODE_IN_LEN 8 13564 /* The target function to have its link state mode read or set, must be a VF 13565 * e.g. VF 1,3 = 0x00030001 13566 */ 13567 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0 13568 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4 13569 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0 13570 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16 13571 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16 13572 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16 13573 /* New link state mode to be set */ 13574 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4 13575 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4 13576 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */ 13577 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */ 13578 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */ 13579 /* enum: Use this value to just read the existing setting without modifying it. 13580 */ 13581 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff 13582 13583 /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */ 13584 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4 13585 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 13586 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4 13587 13588 13589 /***********************************/ 13590 /* MC_CMD_GET_SNAPSHOT_LENGTH 13591 * Obtain the current range of allowable values for the SNAPSHOT_LENGTH 13592 * parameter to MC_CMD_INIT_RXQ. 13593 */ 13594 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101 13595 13596 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13597 13598 /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */ 13599 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0 13600 13601 /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */ 13602 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8 13603 /* Minimum acceptable snapshot length. */ 13604 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0 13605 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_LEN 4 13606 /* Maximum acceptable snapshot length. */ 13607 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 13608 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_LEN 4 13609 13610 13611 /***********************************/ 13612 /* MC_CMD_FUSE_DIAGS 13613 * Additional fuse diagnostics 13614 */ 13615 #define MC_CMD_FUSE_DIAGS 0x102 13616 13617 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13618 13619 /* MC_CMD_FUSE_DIAGS_IN msgrequest */ 13620 #define MC_CMD_FUSE_DIAGS_IN_LEN 0 13621 13622 /* MC_CMD_FUSE_DIAGS_OUT msgresponse */ 13623 #define MC_CMD_FUSE_DIAGS_OUT_LEN 48 13624 /* Total number of mismatched bits between pairs in area 0 */ 13625 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0 13626 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 4 13627 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */ 13628 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4 13629 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 4 13630 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */ 13631 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8 13632 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 4 13633 /* Checksum of data after logical OR of pairs in area 0 */ 13634 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12 13635 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 4 13636 /* Total number of mismatched bits between pairs in area 1 */ 13637 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16 13638 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 4 13639 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */ 13640 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20 13641 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 4 13642 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */ 13643 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24 13644 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 4 13645 /* Checksum of data after logical OR of pairs in area 1 */ 13646 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28 13647 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 4 13648 /* Total number of mismatched bits between pairs in area 2 */ 13649 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32 13650 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 4 13651 /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */ 13652 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36 13653 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 4 13654 /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */ 13655 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40 13656 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 4 13657 /* Checksum of data after logical OR of pairs in area 2 */ 13658 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 13659 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4 13660 13661 13662 /***********************************/ 13663 /* MC_CMD_PRIVILEGE_MODIFY 13664 * Modify the privileges of a set of PCIe functions. Note that this operation 13665 * only effects non-admin functions unless the admin privilege itself is 13666 * included in one of the masks provided. 13667 */ 13668 #define MC_CMD_PRIVILEGE_MODIFY 0x60 13669 13670 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13671 13672 /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */ 13673 #define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16 13674 /* The groups of functions to have their privilege masks modified. */ 13675 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0 13676 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4 13677 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */ 13678 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */ 13679 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */ 13680 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */ 13681 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */ 13682 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */ 13683 /* For VFS_OF_PF specify the PF, for ONE specify the target function */ 13684 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4 13685 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4 13686 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0 13687 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16 13688 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16 13689 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16 13690 /* Privileges to be added to the target functions. For privilege definitions 13691 * refer to the command MC_CMD_PRIVILEGE_MASK 13692 */ 13693 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8 13694 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 4 13695 /* Privileges to be removed from the target functions. For privilege 13696 * definitions refer to the command MC_CMD_PRIVILEGE_MASK 13697 */ 13698 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12 13699 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 4 13700 13701 /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ 13702 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 13703 13704 13705 /***********************************/ 13706 /* MC_CMD_XPM_READ_BYTES 13707 * Read XPM memory 13708 */ 13709 #define MC_CMD_XPM_READ_BYTES 0x103 13710 13711 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13712 13713 /* MC_CMD_XPM_READ_BYTES_IN msgrequest */ 13714 #define MC_CMD_XPM_READ_BYTES_IN_LEN 8 13715 /* Start address (byte) */ 13716 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0 13717 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_LEN 4 13718 /* Count (bytes) */ 13719 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4 13720 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_LEN 4 13721 13722 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */ 13723 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0 13724 #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252 13725 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) 13726 /* Data */ 13727 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0 13728 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1 13729 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 13730 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 13731 13732 13733 /***********************************/ 13734 /* MC_CMD_XPM_WRITE_BYTES 13735 * Write XPM memory 13736 */ 13737 #define MC_CMD_XPM_WRITE_BYTES 0x104 13738 13739 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13740 13741 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */ 13742 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8 13743 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252 13744 #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) 13745 /* Start address (byte) */ 13746 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0 13747 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_LEN 4 13748 /* Count (bytes) */ 13749 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4 13750 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_LEN 4 13751 /* Data */ 13752 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8 13753 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1 13754 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0 13755 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244 13756 13757 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ 13758 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 13759 13760 13761 /***********************************/ 13762 /* MC_CMD_XPM_READ_SECTOR 13763 * Read XPM sector 13764 */ 13765 #define MC_CMD_XPM_READ_SECTOR 0x105 13766 13767 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13768 13769 /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */ 13770 #define MC_CMD_XPM_READ_SECTOR_IN_LEN 8 13771 /* Sector index */ 13772 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0 13773 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_LEN 4 13774 /* Sector size */ 13775 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4 13776 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_LEN 4 13777 13778 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */ 13779 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4 13780 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36 13781 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) 13782 /* Sector type */ 13783 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0 13784 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4 13785 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */ 13786 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */ 13787 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */ 13788 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA 0x3 /* enum */ 13789 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */ 13790 /* Sector data */ 13791 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4 13792 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1 13793 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 13794 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 13795 13796 13797 /***********************************/ 13798 /* MC_CMD_XPM_WRITE_SECTOR 13799 * Write XPM sector 13800 */ 13801 #define MC_CMD_XPM_WRITE_SECTOR 0x106 13802 13803 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13804 13805 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */ 13806 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12 13807 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44 13808 #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) 13809 /* If writing fails due to an uncorrectable error, try up to RETRIES following 13810 * sectors (or until no more space available). If 0, only one write attempt is 13811 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair 13812 * mechanism. 13813 */ 13814 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0 13815 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1 13816 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1 13817 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3 13818 /* Sector type */ 13819 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 13820 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_LEN 4 13821 /* Enum values, see field(s): */ 13822 /* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ 13823 /* Sector size */ 13824 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 13825 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_LEN 4 13826 /* Sector data */ 13827 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12 13828 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1 13829 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0 13830 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32 13831 13832 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */ 13833 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4 13834 /* New sector index */ 13835 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 13836 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_LEN 4 13837 13838 13839 /***********************************/ 13840 /* MC_CMD_XPM_INVALIDATE_SECTOR 13841 * Invalidate XPM sector 13842 */ 13843 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107 13844 13845 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13846 13847 /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */ 13848 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4 13849 /* Sector index */ 13850 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0 13851 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_LEN 4 13852 13853 /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ 13854 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 13855 13856 13857 /***********************************/ 13858 /* MC_CMD_XPM_BLANK_CHECK 13859 * Blank-check XPM memory and report bad locations 13860 */ 13861 #define MC_CMD_XPM_BLANK_CHECK 0x108 13862 13863 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13864 13865 /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */ 13866 #define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8 13867 /* Start address (byte) */ 13868 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0 13869 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_LEN 4 13870 /* Count (bytes) */ 13871 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4 13872 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_LEN 4 13873 13874 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */ 13875 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4 13876 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252 13877 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) 13878 /* Total number of bad (non-blank) locations */ 13879 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0 13880 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_LEN 4 13881 /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit 13882 * into MCDI response) 13883 */ 13884 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4 13885 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2 13886 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 13887 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 13888 13889 13890 /***********************************/ 13891 /* MC_CMD_XPM_REPAIR 13892 * Blank-check and repair XPM memory 13893 */ 13894 #define MC_CMD_XPM_REPAIR 0x109 13895 13896 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13897 13898 /* MC_CMD_XPM_REPAIR_IN msgrequest */ 13899 #define MC_CMD_XPM_REPAIR_IN_LEN 8 13900 /* Start address (byte) */ 13901 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0 13902 #define MC_CMD_XPM_REPAIR_IN_ADDR_LEN 4 13903 /* Count (bytes) */ 13904 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4 13905 #define MC_CMD_XPM_REPAIR_IN_COUNT_LEN 4 13906 13907 /* MC_CMD_XPM_REPAIR_OUT msgresponse */ 13908 #define MC_CMD_XPM_REPAIR_OUT_LEN 0 13909 13910 13911 /***********************************/ 13912 /* MC_CMD_XPM_DECODER_TEST 13913 * Test XPM memory address decoders for gross manufacturing defects. Can only 13914 * be performed on an unprogrammed part. 13915 */ 13916 #define MC_CMD_XPM_DECODER_TEST 0x10a 13917 13918 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13919 13920 /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */ 13921 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0 13922 13923 /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ 13924 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 13925 13926 13927 /***********************************/ 13928 /* MC_CMD_XPM_WRITE_TEST 13929 * XPM memory write test. Test XPM write logic for gross manufacturing defects 13930 * by writing to a dedicated test row. There are 16 locations in the test row 13931 * and the test can only be performed on locations that have not been 13932 * previously used (i.e. can be run at most 16 times). The test will pick the 13933 * first available location to use, or fail with ENOSPC if none left. 13934 */ 13935 #define MC_CMD_XPM_WRITE_TEST 0x10b 13936 13937 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13938 13939 /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */ 13940 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0 13941 13942 /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ 13943 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 13944 13945 13946 /***********************************/ 13947 /* MC_CMD_EXEC_SIGNED 13948 * Check the CMAC of the contents of IMEM and DMEM against the value supplied 13949 * and if correct begin execution from the start of IMEM. The caller supplies a 13950 * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC 13951 * computation runs from the start of IMEM, and from the start of DMEM + 16k, 13952 * to match flash booting. The command will respond with EINVAL if the CMAC 13953 * does match, otherwise it will respond with success before it jumps to IMEM. 13954 */ 13955 #define MC_CMD_EXEC_SIGNED 0x10c 13956 13957 #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13958 13959 /* MC_CMD_EXEC_SIGNED_IN msgrequest */ 13960 #define MC_CMD_EXEC_SIGNED_IN_LEN 28 13961 /* the length of code to include in the CMAC */ 13962 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0 13963 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_LEN 4 13964 /* the length of date to include in the CMAC */ 13965 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4 13966 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_LEN 4 13967 /* the XPM sector containing the key to use */ 13968 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8 13969 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_LEN 4 13970 /* the expected CMAC value */ 13971 #define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12 13972 #define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16 13973 13974 /* MC_CMD_EXEC_SIGNED_OUT msgresponse */ 13975 #define MC_CMD_EXEC_SIGNED_OUT_LEN 0 13976 13977 13978 /***********************************/ 13979 /* MC_CMD_PREPARE_SIGNED 13980 * Prepare to upload a signed image. This will scrub the specified length of 13981 * the data region, which must be at least as large as the DATALEN supplied to 13982 * MC_CMD_EXEC_SIGNED. 13983 */ 13984 #define MC_CMD_PREPARE_SIGNED 0x10d 13985 13986 #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13987 13988 /* MC_CMD_PREPARE_SIGNED_IN msgrequest */ 13989 #define MC_CMD_PREPARE_SIGNED_IN_LEN 4 13990 /* the length of data area to clear */ 13991 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0 13992 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_LEN 4 13993 13994 /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */ 13995 #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0 13996 13997 13998 /* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */ 13999 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4 14000 /* UDP port (the standard ports are named below but any port may be used) */ 14001 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0 14002 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2 14003 /* enum: the IANA allocated UDP port for VXLAN */ 14004 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5 14005 /* enum: the IANA allocated UDP port for Geneve */ 14006 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1 14007 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0 14008 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16 14009 /* tunnel encapsulation protocol (only those named below are supported) */ 14010 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2 14011 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2 14012 /* enum: This port will be used for VXLAN on both IPv4 and IPv6 */ 14013 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0 14014 /* enum: This port will be used for Geneve on both IPv4 and IPv6 */ 14015 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1 14016 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16 14017 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16 14018 14019 14020 /***********************************/ 14021 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 14022 * Configure UDP ports for tunnel encapsulation hardware acceleration. The 14023 * parser-dispatcher will attempt to parse traffic on these ports as tunnel 14024 * encapsulation PDUs and filter them using the tunnel encapsulation filter 14025 * chain rather than the standard filter chain. Note that this command can 14026 * cause all functions to see a reset. (Available on Medford only.) 14027 */ 14028 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117 14029 14030 #define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14031 14032 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */ 14033 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4 14034 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68 14035 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num)) 14036 /* Flags */ 14037 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0 14038 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2 14039 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0 14040 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1 14041 /* The number of entries in the ENTRIES array */ 14042 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2 14043 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2 14044 /* Entries defining the UDP port to protocol mapping, each laid out as a 14045 * TUNNEL_ENCAP_UDP_PORT_ENTRY 14046 */ 14047 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4 14048 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4 14049 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0 14050 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16 14051 14052 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */ 14053 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2 14054 /* Flags */ 14055 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0 14056 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2 14057 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0 14058 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1 14059 14060 14061 /***********************************/ 14062 /* MC_CMD_RX_BALANCING 14063 * Configure a port upconverter to distribute the packets on both RX engines. 14064 * Packets are distributed based on a table with the destination vFIFO. The 14065 * index of the table is a hash of source and destination of IPV4 and VLAN 14066 * priority. 14067 */ 14068 #define MC_CMD_RX_BALANCING 0x118 14069 14070 #define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14071 14072 /* MC_CMD_RX_BALANCING_IN msgrequest */ 14073 #define MC_CMD_RX_BALANCING_IN_LEN 16 14074 /* The RX port whose upconverter table will be modified */ 14075 #define MC_CMD_RX_BALANCING_IN_PORT_OFST 0 14076 #define MC_CMD_RX_BALANCING_IN_PORT_LEN 4 14077 /* The VLAN priority associated to the table index and vFIFO */ 14078 #define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4 14079 #define MC_CMD_RX_BALANCING_IN_PRIORITY_LEN 4 14080 /* The resulting bit of SRC^DST for indexing the table */ 14081 #define MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8 14082 #define MC_CMD_RX_BALANCING_IN_SRC_DST_LEN 4 14083 /* The RX engine to which the vFIFO in the table entry will point to */ 14084 #define MC_CMD_RX_BALANCING_IN_ENG_OFST 12 14085 #define MC_CMD_RX_BALANCING_IN_ENG_LEN 4 14086 14087 /* MC_CMD_RX_BALANCING_OUT msgresponse */ 14088 #define MC_CMD_RX_BALANCING_OUT_LEN 0 14089 14090 14091 /***********************************/ 14092 /* MC_CMD_NVRAM_PRIVATE_APPEND 14093 * Append a single TLV to the MC_USAGE_TLV partition. Returns MC_CMD_ERR_EEXIST 14094 * if the tag is already present. 14095 */ 14096 #define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c 14097 14098 #define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14099 14100 /* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */ 14101 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9 14102 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252 14103 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num)) 14104 /* The tag to be appended */ 14105 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0 14106 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_LEN 4 14107 /* The length of the data */ 14108 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4 14109 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_LEN 4 14110 /* The data to be contained in the TLV structure */ 14111 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_OFST 8 14112 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1 14113 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1 14114 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM 244 14115 14116 /* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */ 14117 #define MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0 14118 14119 14120 /***********************************/ 14121 /* MC_CMD_XPM_VERIFY_CONTENTS 14122 * Verify that the contents of the XPM memory is correct (Medford only). This 14123 * is used during manufacture to check that the XPM memory has been programmed 14124 * correctly at ATE. 14125 */ 14126 #define MC_CMD_XPM_VERIFY_CONTENTS 0x11b 14127 14128 #define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14129 14130 /* MC_CMD_XPM_VERIFY_CONTENTS_IN msgrequest */ 14131 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4 14132 /* Data type to be checked */ 14133 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0 14134 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_LEN 4 14135 14136 /* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */ 14137 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12 14138 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252 14139 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num)) 14140 /* Number of sectors found (test builds only) */ 14141 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0 14142 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_LEN 4 14143 /* Number of bytes found (test builds only) */ 14144 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4 14145 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_LEN 4 14146 /* Length of signature */ 14147 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_OFST 8 14148 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_LEN 4 14149 /* Signature */ 14150 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_OFST 12 14151 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1 14152 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0 14153 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240 14154 14155 14156 /***********************************/ 14157 /* MC_CMD_SET_EVQ_TMR 14158 * Update the timer load, timer reload and timer mode values for a given EVQ. 14159 * The requested timer values (in TMR_LOAD_REQ_NS and TMR_RELOAD_REQ_NS) will 14160 * be rounded up to the granularity supported by the hardware, then truncated 14161 * to the range supported by the hardware. The resulting value after the 14162 * rounding and truncation will be returned to the caller (in TMR_LOAD_ACT_NS 14163 * and TMR_RELOAD_ACT_NS). 14164 */ 14165 #define MC_CMD_SET_EVQ_TMR 0x120 14166 14167 #define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14168 14169 /* MC_CMD_SET_EVQ_TMR_IN msgrequest */ 14170 #define MC_CMD_SET_EVQ_TMR_IN_LEN 16 14171 /* Function-relative queue instance */ 14172 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0 14173 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_LEN 4 14174 /* Requested value for timer load (in nanoseconds) */ 14175 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4 14176 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_LEN 4 14177 /* Requested value for timer reload (in nanoseconds) */ 14178 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8 14179 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_LEN 4 14180 /* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */ 14181 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12 14182 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_LEN 4 14183 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */ 14184 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */ 14185 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */ 14186 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */ 14187 14188 /* MC_CMD_SET_EVQ_TMR_OUT msgresponse */ 14189 #define MC_CMD_SET_EVQ_TMR_OUT_LEN 8 14190 /* Actual value for timer load (in nanoseconds) */ 14191 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0 14192 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_LEN 4 14193 /* Actual value for timer reload (in nanoseconds) */ 14194 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4 14195 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_LEN 4 14196 14197 14198 /***********************************/ 14199 /* MC_CMD_GET_EVQ_TMR_PROPERTIES 14200 * Query properties about the event queue timers. 14201 */ 14202 #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122 14203 14204 #define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14205 14206 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_IN msgrequest */ 14207 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0 14208 14209 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT msgresponse */ 14210 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36 14211 /* Reserved for future use. */ 14212 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0 14213 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_LEN 4 14214 /* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in 14215 * nanoseconds) for each increment of the timer load/reload count. The 14216 * requested duration of a timer is this value multiplied by the timer 14217 * load/reload count. 14218 */ 14219 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4 14220 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_LEN 4 14221 /* For timers updated via writes to EVQ_TMR_REG, this is the maximum value 14222 * allowed for timer load/reload counts. 14223 */ 14224 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8 14225 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_LEN 4 14226 /* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a 14227 * multiple of this step size will be rounded in an implementation defined 14228 * manner. 14229 */ 14230 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12 14231 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_LEN 4 14232 /* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only 14233 * meaningful if MC_CMD_SET_EVQ_TMR is implemented. 14234 */ 14235 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16 14236 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_LEN 4 14237 /* Timer durations requested via MCDI that are not a multiple of this step size 14238 * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented. 14239 */ 14240 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20 14241 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_LEN 4 14242 /* For timers updated using the bug35388 workaround, this is the time interval 14243 * (in nanoseconds) for each increment of the timer load/reload count. The 14244 * requested duration of a timer is this value multiplied by the timer 14245 * load/reload count. This field is only meaningful if the bug35388 workaround 14246 * is enabled. 14247 */ 14248 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24 14249 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_LEN 4 14250 /* For timers updated using the bug35388 workaround, this is the maximum value 14251 * allowed for timer load/reload counts. This field is only meaningful if the 14252 * bug35388 workaround is enabled. 14253 */ 14254 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28 14255 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_LEN 4 14256 /* For timers updated using the bug35388 workaround, timer load/reload counts 14257 * not a multiple of this step size will be rounded in an implementation 14258 * defined manner. This field is only meaningful if the bug35388 workaround is 14259 * enabled. 14260 */ 14261 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32 14262 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4 14263 14264 14265 /***********************************/ 14266 /* MC_CMD_ALLOCATE_TX_VFIFO_CP 14267 * When we use the TX_vFIFO_ULL mode, we can allocate common pools using the 14268 * non used switch buffers. 14269 */ 14270 #define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d 14271 14272 #define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14273 14274 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */ 14275 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20 14276 /* Desired instance. Must be set to a specific instance, which is a function 14277 * local queue index. 14278 */ 14279 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0 14280 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4 14281 /* Will the common pool be used as TX_vFIFO_ULL (1) */ 14282 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4 14283 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_LEN 4 14284 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */ 14285 /* enum: Using this interface without TX_vFIFO_ULL is not supported for now */ 14286 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0 14287 /* Number of buffers to reserve for the common pool */ 14288 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8 14289 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_LEN 4 14290 /* TX datapath to which the Common Pool is connected to. */ 14291 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12 14292 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_LEN 4 14293 /* enum: Extracts information from function */ 14294 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 14295 /* Network port or RX Engine to which the common pool connects. */ 14296 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16 14297 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_LEN 4 14298 /* enum: Extracts information from function */ 14299 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */ 14300 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */ 14301 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */ 14302 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */ 14303 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */ 14304 /* enum: To enable Switch loopback with Rx engine 0 */ 14305 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4 14306 /* enum: To enable Switch loopback with Rx engine 1 */ 14307 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5 14308 14309 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 14310 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4 14311 /* ID of the common pool allocated */ 14312 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0 14313 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_LEN 4 14314 14315 14316 /***********************************/ 14317 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 14318 * When we use the TX_vFIFO_ULL mode, we can allocate vFIFOs using the 14319 * previously allocated common pools. 14320 */ 14321 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e 14322 14323 #define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14324 14325 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */ 14326 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20 14327 /* Common pool previously allocated to which the new vFIFO will be associated 14328 */ 14329 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0 14330 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_LEN 4 14331 /* Port or RX engine to associate the vFIFO egress */ 14332 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4 14333 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_LEN 4 14334 /* enum: Extracts information from common pool */ 14335 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1 14336 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */ 14337 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */ 14338 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */ 14339 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */ 14340 /* enum: To enable Switch loopback with Rx engine 0 */ 14341 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4 14342 /* enum: To enable Switch loopback with Rx engine 1 */ 14343 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5 14344 /* Minimum number of buffers that the pool must have */ 14345 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8 14346 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_LEN 4 14347 /* enum: Do not check the space available */ 14348 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0 14349 /* Will the vFIFO be used as TX_vFIFO_ULL */ 14350 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12 14351 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_LEN 4 14352 /* Network priority of the vFIFO,if applicable */ 14353 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16 14354 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_LEN 4 14355 /* enum: Search for the lowest unused priority */ 14356 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1 14357 14358 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT msgresponse */ 14359 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8 14360 /* Short vFIFO ID */ 14361 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0 14362 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_LEN 4 14363 /* Network priority of the vFIFO */ 14364 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4 14365 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_LEN 4 14366 14367 14368 /***********************************/ 14369 /* MC_CMD_TEARDOWN_TX_VFIFO_VF 14370 * This interface clears the configuration of the given vFIFO and leaves it 14371 * ready to be re-used. 14372 */ 14373 #define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f 14374 14375 #define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14376 14377 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */ 14378 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4 14379 /* Short vFIFO ID */ 14380 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0 14381 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_LEN 4 14382 14383 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */ 14384 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0 14385 14386 14387 /***********************************/ 14388 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP 14389 * This interface clears the configuration of the given common pool and leaves 14390 * it ready to be re-used. 14391 */ 14392 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121 14393 14394 #define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14395 14396 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */ 14397 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4 14398 /* Common pool ID given when pool allocated */ 14399 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0 14400 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_LEN 4 14401 14402 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 14403 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0 14404 14405 14406 /***********************************/ 14407 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 14408 * This interface allows the host to find out how many common pool buffers are 14409 * not yet assigned. 14410 */ 14411 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124 14412 14413 #define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14414 14415 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN msgrequest */ 14416 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0 14417 14418 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT msgresponse */ 14419 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_LEN 8 14420 /* Available buffers for the ENG to NET vFIFOs. */ 14421 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0 14422 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_LEN 4 14423 /* Available buffers for the ENG to ENG and NET to ENG vFIFOs. */ 14424 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4 14425 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_LEN 4 14426 14427 14428 #endif /* MCDI_PCOL_H */ 14429