1 /****************************************************************************
2  * Driver for Solarflare network controllers and boards
3  * Copyright 2009-2013 Solarflare Communications Inc.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License version 2 as published
7  * by the Free Software Foundation, incorporated herein by reference.
8  */
9 
10 
11 #ifndef MCDI_PCOL_H
12 #define MCDI_PCOL_H
13 
14 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */
15 /* Power-on reset state */
16 #define MC_FW_STATE_POR (1)
17 /* If this is set in MC_RESET_STATE_REG then it should be
18  * possible to jump into IMEM without loading code from flash. */
19 #define MC_FW_WARM_BOOT_OK (2)
20 /* The MC main image has started to boot. */
21 #define MC_FW_STATE_BOOTING (4)
22 /* The Scheduler has started. */
23 #define MC_FW_STATE_SCHED (8)
24 /* If this is set in MC_RESET_STATE_REG then it should be
25  * possible to jump into IMEM without loading code from flash.
26  * Unlike a warm boot, assume DMEM has been reloaded, so that
27  * the MC persistent data must be reinitialised. */
28 #define MC_FW_TEPID_BOOT_OK (16)
29 /* We have entered the main firmware via recovery mode.  This
30  * means that MC persistent data must be reinitialised, but that
31  * we shouldn't touch PCIe config. */
32 #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32)
33 /* BIST state has been initialized */
34 #define MC_FW_BIST_INIT_OK (128)
35 
36 /* Siena MC shared memmory offsets */
37 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 #define	MC_SMEM_P0_DOORBELL_OFST	0x000
39 #define	MC_SMEM_P1_DOORBELL_OFST	0x004
40 /* The rest of these are firmware-defined */
41 #define	MC_SMEM_P0_PDU_OFST		0x008
42 #define	MC_SMEM_P1_PDU_OFST		0x108
43 #define	MC_SMEM_PDU_LEN			0x100
44 #define	MC_SMEM_P0_PTP_TIME_OFST	0x7f0
45 #define	MC_SMEM_P0_STATUS_OFST		0x7f8
46 #define	MC_SMEM_P1_STATUS_OFST		0x7fc
47 
48 /* Values to be written to the per-port status dword in shared
49  * memory on reboot and assert */
50 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
51 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
52 
53 /* Check whether an mcfw version (in host order) belongs to a bootloader */
54 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)
55 
56 /* The current version of the MCDI protocol.
57  *
58  * Note that the ROM burnt into the card only talks V0, so at the very
59  * least every driver must support version 0 and MCDI_PCOL_VERSION
60  */
61 #define MCDI_PCOL_VERSION 2
62 
63 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */
64 
65 /* MCDI version 1
66  *
67  * Each MCDI request starts with an MCDI_HEADER, which is a 32bit
68  * structure, filled in by the client.
69  *
70  *       0       7  8     16    20     22  23  24    31
71  *      | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |
72  *               |                      |   |
73  *               |                      |   \--- Response
74  *               |                      \------- Error
75  *               \------------------------------ Resync (always set)
76  *
77  * The client writes it's request into MC shared memory, and rings the
78  * doorbell. Each request is completed by either by the MC writting
79  * back into shared memory, or by writting out an event.
80  *
81  * All MCDI commands support completion by shared memory response. Each
82  * request may also contain additional data (accounted for by HEADER.LEN),
83  * and some response's may also contain additional data (again, accounted
84  * for by HEADER.LEN).
85  *
86  * Some MCDI commands support completion by event, in which any associated
87  * response data is included in the event.
88  *
89  * The protocol requires one response to be delivered for every request, a
90  * request should not be sent unless the response for the previous request
91  * has been received (either by polling shared memory, or by receiving
92  * an event).
93  */
94 
95 /** Request/Response structure */
96 #define MCDI_HEADER_OFST 0
97 #define MCDI_HEADER_CODE_LBN 0
98 #define MCDI_HEADER_CODE_WIDTH 7
99 #define MCDI_HEADER_RESYNC_LBN 7
100 #define MCDI_HEADER_RESYNC_WIDTH 1
101 #define MCDI_HEADER_DATALEN_LBN 8
102 #define MCDI_HEADER_DATALEN_WIDTH 8
103 #define MCDI_HEADER_SEQ_LBN 16
104 #define MCDI_HEADER_SEQ_WIDTH 4
105 #define MCDI_HEADER_RSVD_LBN 20
106 #define MCDI_HEADER_RSVD_WIDTH 1
107 #define MCDI_HEADER_NOT_EPOCH_LBN 21
108 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1
109 #define MCDI_HEADER_ERROR_LBN 22
110 #define MCDI_HEADER_ERROR_WIDTH 1
111 #define MCDI_HEADER_RESPONSE_LBN 23
112 #define MCDI_HEADER_RESPONSE_WIDTH 1
113 #define MCDI_HEADER_XFLAGS_LBN 24
114 #define MCDI_HEADER_XFLAGS_WIDTH 8
115 /* Request response using event */
116 #define MCDI_HEADER_XFLAGS_EVREQ 0x01
117 /* Request (and signal) early doorbell return */
118 #define MCDI_HEADER_XFLAGS_DBRET 0x02
119 
120 /* Maximum number of payload bytes */
121 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
122 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400
123 
124 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2
125 
126 
127 /* The MC can generate events for two reasons:
128  *   - To advance a shared memory request if XFLAGS_EVREQ was set
129  *   - As a notification (link state, i2c event), controlled
130  *     via MC_CMD_LOG_CTRL
131  *
132  * Both events share a common structure:
133  *
134  *  0      32     33      36    44     52     60
135  * | Data | Cont | Level | Src | Code | Rsvd |
136  *           |
137  *           \ There is another event pending in this notification
138  *
139  * If Code==CMDDONE, then the fields are further interpreted as:
140  *
141  *   - LEVEL==INFO    Command succeeded
142  *   - LEVEL==ERR     Command failed
143  *
144  *    0     8         16      24     32
145  *   | Seq | Datalen | Errno | Rsvd |
146  *
147  *   These fields are taken directly out of the standard MCDI header, i.e.,
148  *   LEVEL==ERR, Datalen == 0 => Reboot
149  *
150  * Events can be squirted out of the UART (using LOG_CTRL) without a
151  * MCDI header.  An event can be distinguished from a MCDI response by
152  * examining the first byte which is 0xc0.  This corresponds to the
153  * non-existent MCDI command MC_CMD_DEBUG_LOG.
154  *
155  *      0         7        8
156  *     | command | Resync |     = 0xc0
157  *
158  * Since the event is written in big-endian byte order, this works
159  * providing bits 56-63 of the event are 0xc0.
160  *
161  *      56     60  63
162  *     | Rsvd | Code |    = 0xc0
163  *
164  * Which means for convenience the event code is 0xc for all MC
165  * generated events.
166  */
167 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
168 
169 
170 /* Operation not permitted. */
171 #define MC_CMD_ERR_EPERM 1
172 /* Non-existent command target */
173 #define MC_CMD_ERR_ENOENT 2
174 /* assert() has killed the MC */
175 #define MC_CMD_ERR_EINTR 4
176 /* I/O failure */
177 #define MC_CMD_ERR_EIO 5
178 /* Already exists */
179 #define MC_CMD_ERR_EEXIST 6
180 /* Try again */
181 #define MC_CMD_ERR_EAGAIN 11
182 /* Out of memory */
183 #define MC_CMD_ERR_ENOMEM 12
184 /* Caller does not hold required locks */
185 #define MC_CMD_ERR_EACCES 13
186 /* Resource is currently unavailable (e.g. lock contention) */
187 #define MC_CMD_ERR_EBUSY 16
188 /* No such device */
189 #define MC_CMD_ERR_ENODEV 19
190 /* Invalid argument to target */
191 #define MC_CMD_ERR_EINVAL 22
192 /* Broken pipe */
193 #define MC_CMD_ERR_EPIPE 32
194 /* Read-only */
195 #define MC_CMD_ERR_EROFS 30
196 /* Out of range */
197 #define MC_CMD_ERR_ERANGE 34
198 /* Non-recursive resource is already acquired */
199 #define MC_CMD_ERR_EDEADLK 35
200 /* Operation not implemented */
201 #define MC_CMD_ERR_ENOSYS 38
202 /* Operation timed out */
203 #define MC_CMD_ERR_ETIME 62
204 /* Link has been severed */
205 #define MC_CMD_ERR_ENOLINK 67
206 /* Protocol error */
207 #define MC_CMD_ERR_EPROTO 71
208 /* Operation not supported */
209 #define MC_CMD_ERR_ENOTSUP 95
210 /* Address not available */
211 #define MC_CMD_ERR_EADDRNOTAVAIL 99
212 /* Not connected */
213 #define MC_CMD_ERR_ENOTCONN 107
214 /* Operation already in progress */
215 #define MC_CMD_ERR_EALREADY 114
216 
217 /* Resource allocation failed. */
218 #define MC_CMD_ERR_ALLOC_FAIL  0x1000
219 /* V-adaptor not found. */
220 #define MC_CMD_ERR_NO_VADAPTOR 0x1001
221 /* EVB port not found. */
222 #define MC_CMD_ERR_NO_EVB_PORT 0x1002
223 /* V-switch not found. */
224 #define MC_CMD_ERR_NO_VSWITCH  0x1003
225 /* Too many VLAN tags. */
226 #define MC_CMD_ERR_VLAN_LIMIT  0x1004
227 /* Bad PCI function number. */
228 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
229 /* Invalid VLAN mode. */
230 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
231 /* Invalid v-switch type. */
232 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
233 /* Invalid v-port type. */
234 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
235 /* MAC address exists. */
236 #define MC_CMD_ERR_MAC_EXIST 0x1009
237 /* Slave core not present */
238 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
239 /* The datapath is disabled. */
240 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b
241 /* The requesting client is not a function */
242 #define MC_CMD_ERR_CLIENT_NOT_FN  0x100c
243 /* The requested operation might require the
244    command to be passed between MCs, and the
245    transport doesn't support that.  Should
246    only ever been seen over the UART. */
247 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d
248 /* VLAN tag(s) exists */
249 #define MC_CMD_ERR_VLAN_EXIST 0x100e
250 /* No MAC address assigned to an EVB port */
251 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f
252 /* Notifies the driver that the request has been relayed
253  * to an admin function for authorization. The driver should
254  * wait for a PROXY_RESPONSE event and then resend its request.
255  * This error code is followed by a 32-bit handle that
256  * helps matching it with the respective PROXY_RESPONSE event. */
257 #define MC_CMD_ERR_PROXY_PENDING 0x1010
258 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4
259 /* The request cannot be passed for authorization because
260  * another request from the same function is currently being
261  * authorized. The drvier should try again later. */
262 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011
263 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function
264  * that has enabled proxying or BLOCK_INDEX points to a function that
265  * doesn't await an authorization. */
266 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012
267 /* This code is currently only used internally in FW. Its meaning is that
268  * an operation failed due to lack of SR-IOV privilege.
269  * Normally it is translated to EPERM by send_cmd_err(),
270  * but it may also be used to trigger some special mechanism
271  * for handling such case, e.g. to relay the failed request
272  * to a designated admin function for authorization. */
273 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013
274 /* Workaround 26807 could not be turned on/off because some functions
275  * have already installed filters. See the comment at
276  * MC_CMD_WORKAROUND_BUG26807.
277  * May also returned for other operations such as sub-variant switching. */
278 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014
279 /* The clock whose frequency you've attempted to set set
280  * doesn't exist on this NIC */
281 #define MC_CMD_ERR_NO_CLOCK 0x1015
282 /* Returned by MC_CMD_TESTASSERT if the action that should
283  * have caused an assertion failed to do so.  */
284 #define MC_CMD_ERR_UNREACHABLE 0x1016
285 /* This command needs to be processed in the background but there were no
286  * resources to do so. Send it again after a command has completed. */
287 #define MC_CMD_ERR_QUEUE_FULL 0x1017
288 /* The operation could not be completed because the PCIe link has gone
289  * away.  This error code is never expected to be returned over the TLP
290  * transport. */
291 #define MC_CMD_ERR_NO_PCIE 0x1018
292 /* The operation could not be completed because the datapath has gone
293  * away.  This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the
294  * datapath absence may be temporary*/
295 #define MC_CMD_ERR_NO_DATAPATH 0x1019
296 /* The operation could not complete because some VIs are allocated */
297 #define MC_CMD_ERR_VIS_PRESENT 0x101a
298 /* The operation could not complete because some PIO buffers are allocated */
299 #define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b
300 
301 #define MC_CMD_ERR_CODE_OFST 0
302 
303 /* We define 8 "escape" commands to allow
304    for command number space extension */
305 
306 #define MC_CMD_CMD_SPACE_ESCAPE_0	      0x78
307 #define MC_CMD_CMD_SPACE_ESCAPE_1	      0x79
308 #define MC_CMD_CMD_SPACE_ESCAPE_2	      0x7A
309 #define MC_CMD_CMD_SPACE_ESCAPE_3	      0x7B
310 #define MC_CMD_CMD_SPACE_ESCAPE_4	      0x7C
311 #define MC_CMD_CMD_SPACE_ESCAPE_5	      0x7D
312 #define MC_CMD_CMD_SPACE_ESCAPE_6	      0x7E
313 #define MC_CMD_CMD_SPACE_ESCAPE_7	      0x7F
314 
315 /* Vectors in the boot ROM */
316 /* Point to the copycode entry point. */
317 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
318 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
319 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)
320 /* Points to the recovery mode entry point. Misnamed but kept for compatibility. */
321 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
322 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
323 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)
324 /* Points to the recovery mode entry point. Same as above, but the right name. */
325 #define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)
326 #define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)
327 #define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)
328 
329 /* Points to noflash mode entry point. */
330 #define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)
331 
332 /* The command set exported by the boot ROM (MCDI v0) */
333 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS {		\
334 	(1 << MC_CMD_READ32)	|			\
335 	(1 << MC_CMD_WRITE32)	|			\
336 	(1 << MC_CMD_COPYCODE)	|			\
337 	(1 << MC_CMD_GET_VERSION),			\
338 	0, 0, 0 }
339 
340 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x)		\
341 	(MC_CMD_SENSOR_ENTRY_OFST + (_x))
342 
343 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n)		\
344 	(MC_CMD_DBI_WRITE_IN_DBIWROP_OFST +		\
345 	 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST +		\
346 	 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
347 
348 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n)		\
349 	(MC_CMD_DBI_WRITE_IN_DBIWROP_OFST +		\
350 	 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST +	\
351 	 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
352 
353 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n)		\
354 	(MC_CMD_DBI_WRITE_IN_DBIWROP_OFST +		\
355 	 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST +		\
356 	 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
357 
358 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default
359  * stack ID (which must be in the range 1-255) along with an EVB port ID.
360  */
361 #define EVB_STACK_ID(n)  (((n) & 0xff) << 16)
362 
363 
364 /* Version 2 adds an optional argument to error returns: the errno value
365  * may be followed by the (0-based) number of the first argument that
366  * could not be processed.
367  */
368 #define MC_CMD_ERR_ARG_OFST 4
369 
370 /* No space */
371 #define MC_CMD_ERR_ENOSPC 28
372 
373 /* MCDI_EVENT structuredef */
374 #define    MCDI_EVENT_LEN 8
375 #define       MCDI_EVENT_CONT_LBN 32
376 #define       MCDI_EVENT_CONT_WIDTH 1
377 #define       MCDI_EVENT_LEVEL_LBN 33
378 #define       MCDI_EVENT_LEVEL_WIDTH 3
379 /* enum: Info. */
380 #define          MCDI_EVENT_LEVEL_INFO 0x0
381 /* enum: Warning. */
382 #define          MCDI_EVENT_LEVEL_WARN 0x1
383 /* enum: Error. */
384 #define          MCDI_EVENT_LEVEL_ERR 0x2
385 /* enum: Fatal. */
386 #define          MCDI_EVENT_LEVEL_FATAL 0x3
387 #define       MCDI_EVENT_DATA_OFST 0
388 #define       MCDI_EVENT_DATA_LEN 4
389 #define        MCDI_EVENT_CMDDONE_SEQ_LBN 0
390 #define        MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
391 #define        MCDI_EVENT_CMDDONE_DATALEN_LBN 8
392 #define        MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8
393 #define        MCDI_EVENT_CMDDONE_ERRNO_LBN 16
394 #define        MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8
395 #define        MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
396 #define        MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
397 #define        MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
398 #define        MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
399 /* enum: Link is down or link speed could not be determined */
400 #define          MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0
401 /* enum: 100Mbs */
402 #define          MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
403 /* enum: 1Gbs */
404 #define          MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
405 /* enum: 10Gbs */
406 #define          MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
407 /* enum: 40Gbs */
408 #define          MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
409 /* enum: 25Gbs */
410 #define          MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5
411 /* enum: 50Gbs */
412 #define          MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6
413 /* enum: 100Gbs */
414 #define          MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7
415 #define        MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
416 #define        MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
417 #define        MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
418 #define        MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
419 #define        MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
420 #define        MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
421 #define        MCDI_EVENT_SENSOREVT_STATE_LBN 8
422 #define        MCDI_EVENT_SENSOREVT_STATE_WIDTH 8
423 #define        MCDI_EVENT_SENSOREVT_VALUE_LBN 16
424 #define        MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16
425 #define        MCDI_EVENT_FWALERT_DATA_LBN 8
426 #define        MCDI_EVENT_FWALERT_DATA_WIDTH 24
427 #define        MCDI_EVENT_FWALERT_REASON_LBN 0
428 #define        MCDI_EVENT_FWALERT_REASON_WIDTH 8
429 /* enum: SRAM Access. */
430 #define          MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
431 #define        MCDI_EVENT_FLR_VF_LBN 0
432 #define        MCDI_EVENT_FLR_VF_WIDTH 8
433 #define        MCDI_EVENT_TX_ERR_TXQ_LBN 0
434 #define        MCDI_EVENT_TX_ERR_TXQ_WIDTH 12
435 #define        MCDI_EVENT_TX_ERR_TYPE_LBN 12
436 #define        MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
437 /* enum: Descriptor loader reported failure */
438 #define          MCDI_EVENT_TX_ERR_DL_FAIL 0x1
439 /* enum: Descriptor ring empty and no EOP seen for packet */
440 #define          MCDI_EVENT_TX_ERR_NO_EOP 0x2
441 /* enum: Overlength packet */
442 #define          MCDI_EVENT_TX_ERR_2BIG 0x3
443 /* enum: Malformed option descriptor */
444 #define          MCDI_EVENT_TX_BAD_OPTDESC 0x5
445 /* enum: Option descriptor part way through a packet */
446 #define          MCDI_EVENT_TX_OPT_IN_PKT 0x8
447 /* enum: DMA or PIO data access error */
448 #define          MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
449 #define        MCDI_EVENT_TX_ERR_INFO_LBN 16
450 #define        MCDI_EVENT_TX_ERR_INFO_WIDTH 16
451 #define        MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12
452 #define        MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1
453 #define        MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
454 #define        MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12
455 #define        MCDI_EVENT_PTP_ERR_TYPE_LBN 0
456 #define        MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8
457 /* enum: PLL lost lock */
458 #define          MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
459 /* enum: Filter overflow (PDMA) */
460 #define          MCDI_EVENT_PTP_ERR_FILTER 0x2
461 /* enum: FIFO overflow (FPGA) */
462 #define          MCDI_EVENT_PTP_ERR_FIFO 0x3
463 /* enum: Merge queue overflow */
464 #define          MCDI_EVENT_PTP_ERR_QUEUE 0x4
465 #define        MCDI_EVENT_AOE_ERR_TYPE_LBN 0
466 #define        MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8
467 /* enum: AOE failed to load - no valid image? */
468 #define          MCDI_EVENT_AOE_NO_LOAD 0x1
469 /* enum: AOE FC reported an exception */
470 #define          MCDI_EVENT_AOE_FC_ASSERT 0x2
471 /* enum: AOE FC watchdogged */
472 #define          MCDI_EVENT_AOE_FC_WATCHDOG 0x3
473 /* enum: AOE FC failed to start */
474 #define          MCDI_EVENT_AOE_FC_NO_START 0x4
475 /* enum: Generic AOE fault - likely to have been reported via other means too
476  * but intended for use by aoex driver.
477  */
478 #define          MCDI_EVENT_AOE_FAULT 0x5
479 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */
480 #define          MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
481 /* enum: AOE loaded successfully */
482 #define          MCDI_EVENT_AOE_LOAD 0x7
483 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */
484 #define          MCDI_EVENT_AOE_DMA 0x8
485 /* enum: AOE byteblaster connected/disconnected (Connection status in
486  * AOE_ERR_DATA)
487  */
488 #define          MCDI_EVENT_AOE_BYTEBLASTER 0x9
489 /* enum: DDR ECC status update */
490 #define          MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa
491 /* enum: PTP status update */
492 #define          MCDI_EVENT_AOE_PTP_STATUS 0xb
493 /* enum: FPGA header incorrect */
494 #define          MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc
495 /* enum: FPGA Powered Off due to error in powering up FPGA */
496 #define          MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd
497 /* enum: AOE FPGA load failed due to MC to MUM communication failure */
498 #define          MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe
499 /* enum: Notify that invalid flash type detected */
500 #define          MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf
501 /* enum: Notify that the attempt to run FPGA Controller firmware timedout */
502 #define          MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10
503 /* enum: Failure to probe one or more FPGA boot flash chips */
504 #define          MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11
505 /* enum: FPGA boot-flash contains an invalid image header */
506 #define          MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12
507 /* enum: Failed to program clocks required by the FPGA */
508 #define          MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13
509 /* enum: Notify that FPGA Controller is alive to serve MCDI requests */
510 #define          MCDI_EVENT_AOE_FC_RUNNING 0x14
511 #define        MCDI_EVENT_AOE_ERR_DATA_LBN 8
512 #define        MCDI_EVENT_AOE_ERR_DATA_WIDTH 8
513 #define        MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8
514 #define        MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8
515 /* enum: FC Assert happened, but the register information is not available */
516 #define          MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0
517 /* enum: The register information for FC Assert is ready for readinng by driver
518  */
519 #define          MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1
520 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8
521 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8
522 /* enum: Reading from NV failed */
523 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0
524 /* enum: Invalid Magic Number if FPGA header */
525 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1
526 /* enum: Invalid Silicon type detected in header */
527 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2
528 /* enum: Unsupported VRatio */
529 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3
530 /* enum: Unsupported DDR Type */
531 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4
532 /* enum: DDR Voltage out of supported range */
533 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5
534 /* enum: Unsupported DDR speed */
535 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6
536 /* enum: Unsupported DDR size */
537 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7
538 /* enum: Unsupported DDR rank */
539 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8
540 #define        MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8
541 #define        MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8
542 /* enum: Primary boot flash */
543 #define          MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0
544 /* enum: Secondary boot flash */
545 #define          MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1
546 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8
547 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8
548 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8
549 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8
550 #define        MCDI_EVENT_RX_ERR_RXQ_LBN 0
551 #define        MCDI_EVENT_RX_ERR_RXQ_WIDTH 12
552 #define        MCDI_EVENT_RX_ERR_TYPE_LBN 12
553 #define        MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
554 #define        MCDI_EVENT_RX_ERR_INFO_LBN 16
555 #define        MCDI_EVENT_RX_ERR_INFO_WIDTH 16
556 #define        MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12
557 #define        MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1
558 #define        MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
559 #define        MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12
560 #define        MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
561 #define        MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16
562 #define        MCDI_EVENT_MUM_ERR_TYPE_LBN 0
563 #define        MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8
564 /* enum: MUM failed to load - no valid image? */
565 #define          MCDI_EVENT_MUM_NO_LOAD 0x1
566 /* enum: MUM f/w reported an exception */
567 #define          MCDI_EVENT_MUM_ASSERT 0x2
568 /* enum: MUM not kicking watchdog */
569 #define          MCDI_EVENT_MUM_WATCHDOG 0x3
570 #define        MCDI_EVENT_MUM_ERR_DATA_LBN 8
571 #define        MCDI_EVENT_MUM_ERR_DATA_WIDTH 8
572 #define        MCDI_EVENT_DBRET_SEQ_LBN 0
573 #define        MCDI_EVENT_DBRET_SEQ_WIDTH 8
574 #define        MCDI_EVENT_SUC_ERR_TYPE_LBN 0
575 #define        MCDI_EVENT_SUC_ERR_TYPE_WIDTH 8
576 /* enum: Corrupted or bad SUC application. */
577 #define          MCDI_EVENT_SUC_BAD_APP 0x1
578 /* enum: SUC application reported an assert. */
579 #define          MCDI_EVENT_SUC_ASSERT 0x2
580 /* enum: SUC application reported an exception. */
581 #define          MCDI_EVENT_SUC_EXCEPTION 0x3
582 /* enum: SUC watchdog timer expired. */
583 #define          MCDI_EVENT_SUC_WATCHDOG 0x4
584 #define        MCDI_EVENT_SUC_ERR_ADDRESS_LBN 8
585 #define        MCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24
586 #define        MCDI_EVENT_SUC_ERR_DATA_LBN 8
587 #define        MCDI_EVENT_SUC_ERR_DATA_WIDTH 24
588 #define       MCDI_EVENT_DATA_LBN 0
589 #define       MCDI_EVENT_DATA_WIDTH 32
590 #define       MCDI_EVENT_SRC_LBN 36
591 #define       MCDI_EVENT_SRC_WIDTH 8
592 #define       MCDI_EVENT_EV_CODE_LBN 60
593 #define       MCDI_EVENT_EV_CODE_WIDTH 4
594 #define       MCDI_EVENT_CODE_LBN 44
595 #define       MCDI_EVENT_CODE_WIDTH 8
596 /* enum: Event generated by host software */
597 #define          MCDI_EVENT_SW_EVENT 0x0
598 /* enum: Bad assert. */
599 #define          MCDI_EVENT_CODE_BADSSERT 0x1
600 /* enum: PM Notice. */
601 #define          MCDI_EVENT_CODE_PMNOTICE 0x2
602 /* enum: Command done. */
603 #define          MCDI_EVENT_CODE_CMDDONE 0x3
604 /* enum: Link change. */
605 #define          MCDI_EVENT_CODE_LINKCHANGE 0x4
606 /* enum: Sensor Event. */
607 #define          MCDI_EVENT_CODE_SENSOREVT 0x5
608 /* enum: Schedule error. */
609 #define          MCDI_EVENT_CODE_SCHEDERR 0x6
610 /* enum: Reboot. */
611 #define          MCDI_EVENT_CODE_REBOOT 0x7
612 /* enum: Mac stats DMA. */
613 #define          MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
614 /* enum: Firmware alert. */
615 #define          MCDI_EVENT_CODE_FWALERT 0x9
616 /* enum: Function level reset. */
617 #define          MCDI_EVENT_CODE_FLR 0xa
618 /* enum: Transmit error */
619 #define          MCDI_EVENT_CODE_TX_ERR 0xb
620 /* enum: Tx flush has completed */
621 #define          MCDI_EVENT_CODE_TX_FLUSH 0xc
622 /* enum: PTP packet received timestamp */
623 #define          MCDI_EVENT_CODE_PTP_RX 0xd
624 /* enum: PTP NIC failure */
625 #define          MCDI_EVENT_CODE_PTP_FAULT 0xe
626 /* enum: PTP PPS event */
627 #define          MCDI_EVENT_CODE_PTP_PPS 0xf
628 /* enum: Rx flush has completed */
629 #define          MCDI_EVENT_CODE_RX_FLUSH 0x10
630 /* enum: Receive error */
631 #define          MCDI_EVENT_CODE_RX_ERR 0x11
632 /* enum: AOE fault */
633 #define          MCDI_EVENT_CODE_AOE 0x12
634 /* enum: Network port calibration failed (VCAL). */
635 #define          MCDI_EVENT_CODE_VCAL_FAIL 0x13
636 /* enum: HW PPS event */
637 #define          MCDI_EVENT_CODE_HW_PPS 0x14
638 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and
639  * a different format)
640  */
641 #define          MCDI_EVENT_CODE_MC_REBOOT 0x15
642 /* enum: the MC has detected a parity error */
643 #define          MCDI_EVENT_CODE_PAR_ERR 0x16
644 /* enum: the MC has detected a correctable error */
645 #define          MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
646 /* enum: the MC has detected an uncorrectable error */
647 #define          MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
648 /* enum: The MC has entered offline BIST mode */
649 #define          MCDI_EVENT_CODE_MC_BIST 0x19
650 /* enum: PTP tick event providing current NIC time */
651 #define          MCDI_EVENT_CODE_PTP_TIME 0x1a
652 /* enum: MUM fault */
653 #define          MCDI_EVENT_CODE_MUM 0x1b
654 /* enum: notify the designated PF of a new authorization request */
655 #define          MCDI_EVENT_CODE_PROXY_REQUEST 0x1c
656 /* enum: notify a function that awaits an authorization that its request has
657  * been processed and it may now resend the command
658  */
659 #define          MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d
660 /* enum: MCDI command accepted. New commands can be issued but this command is
661  * not done yet.
662  */
663 #define          MCDI_EVENT_CODE_DBRET 0x1e
664 /* enum: The MC has detected a fault on the SUC */
665 #define          MCDI_EVENT_CODE_SUC 0x1f
666 /* enum: Artificial event generated by host and posted via MC for test
667  * purposes.
668  */
669 #define          MCDI_EVENT_CODE_TESTGEN 0xfa
670 #define       MCDI_EVENT_CMDDONE_DATA_OFST 0
671 #define       MCDI_EVENT_CMDDONE_DATA_LEN 4
672 #define       MCDI_EVENT_CMDDONE_DATA_LBN 0
673 #define       MCDI_EVENT_CMDDONE_DATA_WIDTH 32
674 #define       MCDI_EVENT_LINKCHANGE_DATA_OFST 0
675 #define       MCDI_EVENT_LINKCHANGE_DATA_LEN 4
676 #define       MCDI_EVENT_LINKCHANGE_DATA_LBN 0
677 #define       MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32
678 #define       MCDI_EVENT_SENSOREVT_DATA_OFST 0
679 #define       MCDI_EVENT_SENSOREVT_DATA_LEN 4
680 #define       MCDI_EVENT_SENSOREVT_DATA_LBN 0
681 #define       MCDI_EVENT_SENSOREVT_DATA_WIDTH 32
682 #define       MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
683 #define       MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4
684 #define       MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
685 #define       MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32
686 #define       MCDI_EVENT_TX_ERR_DATA_OFST 0
687 #define       MCDI_EVENT_TX_ERR_DATA_LEN 4
688 #define       MCDI_EVENT_TX_ERR_DATA_LBN 0
689 #define       MCDI_EVENT_TX_ERR_DATA_WIDTH 32
690 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of
691  * timestamp
692  */
693 #define       MCDI_EVENT_PTP_SECONDS_OFST 0
694 #define       MCDI_EVENT_PTP_SECONDS_LEN 4
695 #define       MCDI_EVENT_PTP_SECONDS_LBN 0
696 #define       MCDI_EVENT_PTP_SECONDS_WIDTH 32
697 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of
698  * timestamp
699  */
700 #define       MCDI_EVENT_PTP_MAJOR_OFST 0
701 #define       MCDI_EVENT_PTP_MAJOR_LEN 4
702 #define       MCDI_EVENT_PTP_MAJOR_LBN 0
703 #define       MCDI_EVENT_PTP_MAJOR_WIDTH 32
704 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field
705  * of timestamp
706  */
707 #define       MCDI_EVENT_PTP_NANOSECONDS_OFST 0
708 #define       MCDI_EVENT_PTP_NANOSECONDS_LEN 4
709 #define       MCDI_EVENT_PTP_NANOSECONDS_LBN 0
710 #define       MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32
711 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of
712  * timestamp
713  */
714 #define       MCDI_EVENT_PTP_MINOR_OFST 0
715 #define       MCDI_EVENT_PTP_MINOR_LEN 4
716 #define       MCDI_EVENT_PTP_MINOR_LBN 0
717 #define       MCDI_EVENT_PTP_MINOR_WIDTH 32
718 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet
719  */
720 #define       MCDI_EVENT_PTP_UUID_OFST 0
721 #define       MCDI_EVENT_PTP_UUID_LEN 4
722 #define       MCDI_EVENT_PTP_UUID_LBN 0
723 #define       MCDI_EVENT_PTP_UUID_WIDTH 32
724 #define       MCDI_EVENT_RX_ERR_DATA_OFST 0
725 #define       MCDI_EVENT_RX_ERR_DATA_LEN 4
726 #define       MCDI_EVENT_RX_ERR_DATA_LBN 0
727 #define       MCDI_EVENT_RX_ERR_DATA_WIDTH 32
728 #define       MCDI_EVENT_PAR_ERR_DATA_OFST 0
729 #define       MCDI_EVENT_PAR_ERR_DATA_LEN 4
730 #define       MCDI_EVENT_PAR_ERR_DATA_LBN 0
731 #define       MCDI_EVENT_PAR_ERR_DATA_WIDTH 32
732 #define       MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
733 #define       MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4
734 #define       MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
735 #define       MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32
736 #define       MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
737 #define       MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4
738 #define       MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
739 #define       MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32
740 /* For CODE_PTP_TIME events, the major value of the PTP clock */
741 #define       MCDI_EVENT_PTP_TIME_MAJOR_OFST 0
742 #define       MCDI_EVENT_PTP_TIME_MAJOR_LEN 4
743 #define       MCDI_EVENT_PTP_TIME_MAJOR_LBN 0
744 #define       MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32
745 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */
746 #define       MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36
747 #define       MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8
748 /* For CODE_PTP_TIME events, most significant bits of the minor value of the
749  * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_19.
750  */
751 #define       MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_LBN 36
752 #define       MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_WIDTH 8
753 /* For CODE_PTP_TIME events where report sync status is enabled, indicates
754  * whether the NIC clock has ever been set
755  */
756 #define       MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36
757 #define       MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1
758 /* For CODE_PTP_TIME events where report sync status is enabled, indicates
759  * whether the NIC and System clocks are in sync
760  */
761 #define       MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37
762 #define       MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1
763 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of
764  * the minor value of the PTP clock
765  */
766 #define       MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38
767 #define       MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6
768 /* For CODE_PTP_TIME events, most significant bits of the minor value of the
769  * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_21.
770  */
771 #define       MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_LBN 38
772 #define       MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_WIDTH 6
773 #define       MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0
774 #define       MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4
775 #define       MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0
776 #define       MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32
777 #define       MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0
778 #define       MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4
779 #define       MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0
780 #define       MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32
781 /* Zero means that the request has been completed or authorized, and the driver
782  * should resend it. A non-zero value means that the authorization has been
783  * denied, and gives the reason. Typically it will be EPERM.
784  */
785 #define       MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36
786 #define       MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8
787 #define       MCDI_EVENT_DBRET_DATA_OFST 0
788 #define       MCDI_EVENT_DBRET_DATA_LEN 4
789 #define       MCDI_EVENT_DBRET_DATA_LBN 0
790 #define       MCDI_EVENT_DBRET_DATA_WIDTH 32
791 
792 /* FCDI_EVENT structuredef */
793 #define    FCDI_EVENT_LEN 8
794 #define       FCDI_EVENT_CONT_LBN 32
795 #define       FCDI_EVENT_CONT_WIDTH 1
796 #define       FCDI_EVENT_LEVEL_LBN 33
797 #define       FCDI_EVENT_LEVEL_WIDTH 3
798 /* enum: Info. */
799 #define          FCDI_EVENT_LEVEL_INFO 0x0
800 /* enum: Warning. */
801 #define          FCDI_EVENT_LEVEL_WARN 0x1
802 /* enum: Error. */
803 #define          FCDI_EVENT_LEVEL_ERR 0x2
804 /* enum: Fatal. */
805 #define          FCDI_EVENT_LEVEL_FATAL 0x3
806 #define       FCDI_EVENT_DATA_OFST 0
807 #define       FCDI_EVENT_DATA_LEN 4
808 #define        FCDI_EVENT_LINK_STATE_STATUS_LBN 0
809 #define        FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1
810 #define          FCDI_EVENT_LINK_DOWN 0x0 /* enum */
811 #define          FCDI_EVENT_LINK_UP 0x1 /* enum */
812 #define       FCDI_EVENT_DATA_LBN 0
813 #define       FCDI_EVENT_DATA_WIDTH 32
814 #define       FCDI_EVENT_SRC_LBN 36
815 #define       FCDI_EVENT_SRC_WIDTH 8
816 #define       FCDI_EVENT_EV_CODE_LBN 60
817 #define       FCDI_EVENT_EV_CODE_WIDTH 4
818 #define       FCDI_EVENT_CODE_LBN 44
819 #define       FCDI_EVENT_CODE_WIDTH 8
820 /* enum: The FC was rebooted. */
821 #define          FCDI_EVENT_CODE_REBOOT 0x1
822 /* enum: Bad assert. */
823 #define          FCDI_EVENT_CODE_ASSERT 0x2
824 /* enum: DDR3 test result. */
825 #define          FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3
826 /* enum: Link status. */
827 #define          FCDI_EVENT_CODE_LINK_STATE 0x4
828 /* enum: A timed read is ready to be serviced. */
829 #define          FCDI_EVENT_CODE_TIMED_READ 0x5
830 /* enum: One or more PPS IN events */
831 #define          FCDI_EVENT_CODE_PPS_IN 0x6
832 /* enum: Tick event from PTP clock */
833 #define          FCDI_EVENT_CODE_PTP_TICK 0x7
834 /* enum: ECC error counters */
835 #define          FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8
836 /* enum: Current status of PTP */
837 #define          FCDI_EVENT_CODE_PTP_STATUS 0x9
838 /* enum: Port id config to map MC-FC port idx */
839 #define          FCDI_EVENT_CODE_PORT_CONFIG 0xa
840 /* enum: Boot result or error code */
841 #define          FCDI_EVENT_CODE_BOOT_RESULT 0xb
842 #define       FCDI_EVENT_REBOOT_SRC_LBN 36
843 #define       FCDI_EVENT_REBOOT_SRC_WIDTH 8
844 #define          FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */
845 #define          FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */
846 #define       FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0
847 #define       FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4
848 #define       FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0
849 #define       FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32
850 #define       FCDI_EVENT_ASSERT_TYPE_LBN 36
851 #define       FCDI_EVENT_ASSERT_TYPE_WIDTH 8
852 #define       FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36
853 #define       FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8
854 #define       FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0
855 #define       FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4
856 #define       FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0
857 #define       FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32
858 #define       FCDI_EVENT_LINK_STATE_DATA_OFST 0
859 #define       FCDI_EVENT_LINK_STATE_DATA_LEN 4
860 #define       FCDI_EVENT_LINK_STATE_DATA_LBN 0
861 #define       FCDI_EVENT_LINK_STATE_DATA_WIDTH 32
862 #define       FCDI_EVENT_PTP_STATE_OFST 0
863 #define       FCDI_EVENT_PTP_STATE_LEN 4
864 #define          FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */
865 #define          FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */
866 #define          FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */
867 #define       FCDI_EVENT_PTP_STATE_LBN 0
868 #define       FCDI_EVENT_PTP_STATE_WIDTH 32
869 #define       FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36
870 #define       FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8
871 #define       FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0
872 #define       FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4
873 #define       FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0
874 #define       FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32
875 /* Index of MC port being referred to */
876 #define       FCDI_EVENT_PORT_CONFIG_SRC_LBN 36
877 #define       FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8
878 /* FC Port index that matches the MC port index in SRC */
879 #define       FCDI_EVENT_PORT_CONFIG_DATA_OFST 0
880 #define       FCDI_EVENT_PORT_CONFIG_DATA_LEN 4
881 #define       FCDI_EVENT_PORT_CONFIG_DATA_LBN 0
882 #define       FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32
883 #define       FCDI_EVENT_BOOT_RESULT_OFST 0
884 #define       FCDI_EVENT_BOOT_RESULT_LEN 4
885 /*            Enum values, see field(s): */
886 /*               MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */
887 #define       FCDI_EVENT_BOOT_RESULT_LBN 0
888 #define       FCDI_EVENT_BOOT_RESULT_WIDTH 32
889 
890 /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events
891  * to the MC. Note that this structure | is overlayed over a normal FCDI event
892  * such that bits 32-63 containing | event code, level, source etc remain the
893  * same. In this case the data | field of the header is defined to be the
894  * number of timestamps
895  */
896 #define    FCDI_EXTENDED_EVENT_PPS_LENMIN 16
897 #define    FCDI_EXTENDED_EVENT_PPS_LENMAX 248
898 #define    FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num))
899 /* Number of timestamps following */
900 #define       FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
901 #define       FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4
902 #define       FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0
903 #define       FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32
904 /* Seconds field of a timestamp record */
905 #define       FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8
906 #define       FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4
907 #define       FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64
908 #define       FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32
909 /* Nanoseconds field of a timestamp record */
910 #define       FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12
911 #define       FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4
912 #define       FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96
913 #define       FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32
914 /* Timestamp records comprising the event */
915 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8
916 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8
917 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8
918 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12
919 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1
920 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30
921 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64
922 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64
923 
924 /* MUM_EVENT structuredef */
925 #define    MUM_EVENT_LEN 8
926 #define       MUM_EVENT_CONT_LBN 32
927 #define       MUM_EVENT_CONT_WIDTH 1
928 #define       MUM_EVENT_LEVEL_LBN 33
929 #define       MUM_EVENT_LEVEL_WIDTH 3
930 /* enum: Info. */
931 #define          MUM_EVENT_LEVEL_INFO 0x0
932 /* enum: Warning. */
933 #define          MUM_EVENT_LEVEL_WARN 0x1
934 /* enum: Error. */
935 #define          MUM_EVENT_LEVEL_ERR 0x2
936 /* enum: Fatal. */
937 #define          MUM_EVENT_LEVEL_FATAL 0x3
938 #define       MUM_EVENT_DATA_OFST 0
939 #define       MUM_EVENT_DATA_LEN 4
940 #define        MUM_EVENT_SENSOR_ID_LBN 0
941 #define        MUM_EVENT_SENSOR_ID_WIDTH 8
942 /*             Enum values, see field(s): */
943 /*                MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
944 #define        MUM_EVENT_SENSOR_STATE_LBN 8
945 #define        MUM_EVENT_SENSOR_STATE_WIDTH 8
946 #define        MUM_EVENT_PORT_PHY_READY_LBN 0
947 #define        MUM_EVENT_PORT_PHY_READY_WIDTH 1
948 #define        MUM_EVENT_PORT_PHY_LINK_UP_LBN 1
949 #define        MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1
950 #define        MUM_EVENT_PORT_PHY_TX_LOL_LBN 2
951 #define        MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1
952 #define        MUM_EVENT_PORT_PHY_RX_LOL_LBN 3
953 #define        MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1
954 #define        MUM_EVENT_PORT_PHY_TX_LOS_LBN 4
955 #define        MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1
956 #define        MUM_EVENT_PORT_PHY_RX_LOS_LBN 5
957 #define        MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1
958 #define        MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6
959 #define        MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1
960 #define       MUM_EVENT_DATA_LBN 0
961 #define       MUM_EVENT_DATA_WIDTH 32
962 #define       MUM_EVENT_SRC_LBN 36
963 #define       MUM_EVENT_SRC_WIDTH 8
964 #define       MUM_EVENT_EV_CODE_LBN 60
965 #define       MUM_EVENT_EV_CODE_WIDTH 4
966 #define       MUM_EVENT_CODE_LBN 44
967 #define       MUM_EVENT_CODE_WIDTH 8
968 /* enum: The MUM was rebooted. */
969 #define          MUM_EVENT_CODE_REBOOT 0x1
970 /* enum: Bad assert. */
971 #define          MUM_EVENT_CODE_ASSERT 0x2
972 /* enum: Sensor failure. */
973 #define          MUM_EVENT_CODE_SENSOR 0x3
974 /* enum: Link fault has been asserted, or has cleared. */
975 #define          MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4
976 #define       MUM_EVENT_SENSOR_DATA_OFST 0
977 #define       MUM_EVENT_SENSOR_DATA_LEN 4
978 #define       MUM_EVENT_SENSOR_DATA_LBN 0
979 #define       MUM_EVENT_SENSOR_DATA_WIDTH 32
980 #define       MUM_EVENT_PORT_PHY_FLAGS_OFST 0
981 #define       MUM_EVENT_PORT_PHY_FLAGS_LEN 4
982 #define       MUM_EVENT_PORT_PHY_FLAGS_LBN 0
983 #define       MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32
984 #define       MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0
985 #define       MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4
986 #define       MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0
987 #define       MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32
988 #define       MUM_EVENT_PORT_PHY_CAPS_OFST 0
989 #define       MUM_EVENT_PORT_PHY_CAPS_LEN 4
990 #define       MUM_EVENT_PORT_PHY_CAPS_LBN 0
991 #define       MUM_EVENT_PORT_PHY_CAPS_WIDTH 32
992 #define       MUM_EVENT_PORT_PHY_TECH_OFST 0
993 #define       MUM_EVENT_PORT_PHY_TECH_LEN 4
994 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */
995 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */
996 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */
997 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */
998 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */
999 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */
1000 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */
1001 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */
1002 #define       MUM_EVENT_PORT_PHY_TECH_LBN 0
1003 #define       MUM_EVENT_PORT_PHY_TECH_WIDTH 32
1004 #define       MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36
1005 #define       MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4
1006 #define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */
1007 #define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */
1008 #define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */
1009 #define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */
1010 #define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */
1011 #define       MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40
1012 #define       MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4
1013 
1014 
1015 /***********************************/
1016 /* MC_CMD_READ32
1017  * Read multiple 32byte words from MC memory. Note - this command really
1018  * belongs to INSECURE category but is required by shmboot. The command handler
1019  * has additional checks to reject insecure calls.
1020  */
1021 #define MC_CMD_READ32 0x1
1022 
1023 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1024 
1025 /* MC_CMD_READ32_IN msgrequest */
1026 #define    MC_CMD_READ32_IN_LEN 8
1027 #define       MC_CMD_READ32_IN_ADDR_OFST 0
1028 #define       MC_CMD_READ32_IN_ADDR_LEN 4
1029 #define       MC_CMD_READ32_IN_NUMWORDS_OFST 4
1030 #define       MC_CMD_READ32_IN_NUMWORDS_LEN 4
1031 
1032 /* MC_CMD_READ32_OUT msgresponse */
1033 #define    MC_CMD_READ32_OUT_LENMIN 4
1034 #define    MC_CMD_READ32_OUT_LENMAX 252
1035 #define    MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
1036 #define       MC_CMD_READ32_OUT_BUFFER_OFST 0
1037 #define       MC_CMD_READ32_OUT_BUFFER_LEN 4
1038 #define       MC_CMD_READ32_OUT_BUFFER_MINNUM 1
1039 #define       MC_CMD_READ32_OUT_BUFFER_MAXNUM 63
1040 
1041 
1042 /***********************************/
1043 /* MC_CMD_WRITE32
1044  * Write multiple 32byte words to MC memory.
1045  */
1046 #define MC_CMD_WRITE32 0x2
1047 
1048 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1049 
1050 /* MC_CMD_WRITE32_IN msgrequest */
1051 #define    MC_CMD_WRITE32_IN_LENMIN 8
1052 #define    MC_CMD_WRITE32_IN_LENMAX 252
1053 #define    MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
1054 #define       MC_CMD_WRITE32_IN_ADDR_OFST 0
1055 #define       MC_CMD_WRITE32_IN_ADDR_LEN 4
1056 #define       MC_CMD_WRITE32_IN_BUFFER_OFST 4
1057 #define       MC_CMD_WRITE32_IN_BUFFER_LEN 4
1058 #define       MC_CMD_WRITE32_IN_BUFFER_MINNUM 1
1059 #define       MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62
1060 
1061 /* MC_CMD_WRITE32_OUT msgresponse */
1062 #define    MC_CMD_WRITE32_OUT_LEN 0
1063 
1064 
1065 /***********************************/
1066 /* MC_CMD_COPYCODE
1067  * Copy MC code between two locations and jump. Note - this command really
1068  * belongs to INSECURE category but is required by shmboot. The command handler
1069  * has additional checks to reject insecure calls.
1070  */
1071 #define MC_CMD_COPYCODE 0x3
1072 
1073 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1074 
1075 /* MC_CMD_COPYCODE_IN msgrequest */
1076 #define    MC_CMD_COPYCODE_IN_LEN 16
1077 /* Source address
1078  *
1079  * The main image should be entered via a copy of a single word from and to a
1080  * magic address, which controls various aspects of the boot. The magic address
1081  * is a bitfield, with each bit as documented below.
1082  */
1083 #define       MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
1084 #define       MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4
1085 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */
1086 #define          MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000
1087 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and
1088  * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below)
1089  */
1090 #define          MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0
1091 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT,
1092  * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see
1093  * below)
1094  */
1095 #define          MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc
1096 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17
1097 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1
1098 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2
1099 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1
1100 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3
1101 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1
1102 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4
1103 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1
1104 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5
1105 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1
1106 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6
1107 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1
1108 /* Destination address */
1109 #define       MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
1110 #define       MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4
1111 #define       MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8
1112 #define       MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4
1113 /* Address of where to jump after copy. */
1114 #define       MC_CMD_COPYCODE_IN_JUMP_OFST 12
1115 #define       MC_CMD_COPYCODE_IN_JUMP_LEN 4
1116 /* enum: Control should return to the caller rather than jumping */
1117 #define          MC_CMD_COPYCODE_JUMP_NONE 0x1
1118 
1119 /* MC_CMD_COPYCODE_OUT msgresponse */
1120 #define    MC_CMD_COPYCODE_OUT_LEN 0
1121 
1122 
1123 /***********************************/
1124 /* MC_CMD_SET_FUNC
1125  * Select function for function-specific commands.
1126  */
1127 #define MC_CMD_SET_FUNC 0x4
1128 
1129 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1130 
1131 /* MC_CMD_SET_FUNC_IN msgrequest */
1132 #define    MC_CMD_SET_FUNC_IN_LEN 4
1133 /* Set function */
1134 #define       MC_CMD_SET_FUNC_IN_FUNC_OFST 0
1135 #define       MC_CMD_SET_FUNC_IN_FUNC_LEN 4
1136 
1137 /* MC_CMD_SET_FUNC_OUT msgresponse */
1138 #define    MC_CMD_SET_FUNC_OUT_LEN 0
1139 
1140 
1141 /***********************************/
1142 /* MC_CMD_GET_BOOT_STATUS
1143  * Get the instruction address from which the MC booted.
1144  */
1145 #define MC_CMD_GET_BOOT_STATUS 0x5
1146 
1147 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1148 
1149 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */
1150 #define    MC_CMD_GET_BOOT_STATUS_IN_LEN 0
1151 
1152 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */
1153 #define    MC_CMD_GET_BOOT_STATUS_OUT_LEN 8
1154 /* ?? */
1155 #define       MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
1156 #define       MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4
1157 /* enum: indicates that the MC wasn't flash booted */
1158 #define          MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
1159 #define       MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
1160 #define       MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4
1161 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
1162 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
1163 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1
1164 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1
1165 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2
1166 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1
1167 
1168 
1169 /***********************************/
1170 /* MC_CMD_GET_ASSERTS
1171  * Get (and optionally clear) the current assertion status. Only
1172  * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other
1173  * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS
1174  */
1175 #define MC_CMD_GET_ASSERTS 0x6
1176 
1177 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1178 
1179 /* MC_CMD_GET_ASSERTS_IN msgrequest */
1180 #define    MC_CMD_GET_ASSERTS_IN_LEN 4
1181 /* Set to clear assertion */
1182 #define       MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
1183 #define       MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4
1184 
1185 /* MC_CMD_GET_ASSERTS_OUT msgresponse */
1186 #define    MC_CMD_GET_ASSERTS_OUT_LEN 140
1187 /* Assertion status flag. */
1188 #define       MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
1189 #define       MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4
1190 /* enum: No assertions have failed. */
1191 #define          MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1
1192 /* enum: A system-level assertion has failed. */
1193 #define          MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2
1194 /* enum: A thread-level assertion has failed. */
1195 #define          MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3
1196 /* enum: The system was reset by the watchdog. */
1197 #define          MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4
1198 /* enum: An illegal address trap stopped the system (huntington and later) */
1199 #define          MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5
1200 /* Failing PC value */
1201 #define       MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
1202 #define       MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4
1203 /* Saved GP regs */
1204 #define       MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8
1205 #define       MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
1206 #define       MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31
1207 /* enum: A magic value hinting that the value in this register at the time of
1208  * the failure has likely been lost.
1209  */
1210 #define          MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057
1211 /* Failing thread address */
1212 #define       MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132
1213 #define       MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4
1214 #define       MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136
1215 #define       MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4
1216 
1217 
1218 /***********************************/
1219 /* MC_CMD_LOG_CTRL
1220  * Configure the output stream for log events such as link state changes,
1221  * sensor notifications and MCDI completions
1222  */
1223 #define MC_CMD_LOG_CTRL 0x7
1224 
1225 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1226 
1227 /* MC_CMD_LOG_CTRL_IN msgrequest */
1228 #define    MC_CMD_LOG_CTRL_IN_LEN 8
1229 /* Log destination */
1230 #define       MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
1231 #define       MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4
1232 /* enum: UART. */
1233 #define          MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1
1234 /* enum: Event queue. */
1235 #define          MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2
1236 /* Legacy argument. Must be zero. */
1237 #define       MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
1238 #define       MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4
1239 
1240 /* MC_CMD_LOG_CTRL_OUT msgresponse */
1241 #define    MC_CMD_LOG_CTRL_OUT_LEN 0
1242 
1243 
1244 /***********************************/
1245 /* MC_CMD_GET_VERSION
1246  * Get version information about the MC firmware.
1247  */
1248 #define MC_CMD_GET_VERSION 0x8
1249 
1250 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1251 
1252 /* MC_CMD_GET_VERSION_IN msgrequest */
1253 #define    MC_CMD_GET_VERSION_IN_LEN 0
1254 
1255 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */
1256 #define    MC_CMD_GET_VERSION_EXT_IN_LEN 4
1257 /* placeholder, set to 0 */
1258 #define       MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0
1259 #define       MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4
1260 
1261 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */
1262 #define    MC_CMD_GET_VERSION_V0_OUT_LEN 4
1263 #define       MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
1264 #define       MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4
1265 /* enum: Reserved version number to indicate "any" version. */
1266 #define          MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
1267 /* enum: Bootrom version value for Siena. */
1268 #define          MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000
1269 /* enum: Bootrom version value for Huntington. */
1270 #define          MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001
1271 /* enum: Bootrom version value for Medford2. */
1272 #define          MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002
1273 
1274 /* MC_CMD_GET_VERSION_OUT msgresponse */
1275 #define    MC_CMD_GET_VERSION_OUT_LEN 32
1276 /*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1277 /*            MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
1278 /*            Enum values, see field(s): */
1279 /*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
1280 #define       MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
1281 #define       MC_CMD_GET_VERSION_OUT_PCOL_LEN 4
1282 /* 128bit mask of functions supported by the current firmware */
1283 #define       MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8
1284 #define       MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16
1285 #define       MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
1286 #define       MC_CMD_GET_VERSION_OUT_VERSION_LEN 8
1287 #define       MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
1288 #define       MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
1289 
1290 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */
1291 #define    MC_CMD_GET_VERSION_EXT_OUT_LEN 48
1292 /*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1293 /*            MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
1294 /*            Enum values, see field(s): */
1295 /*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
1296 #define       MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4
1297 #define       MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4
1298 /* 128bit mask of functions supported by the current firmware */
1299 #define       MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8
1300 #define       MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16
1301 #define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24
1302 #define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8
1303 #define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24
1304 #define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28
1305 /* extra info */
1306 #define       MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32
1307 #define       MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16
1308 
1309 
1310 /***********************************/
1311 /* MC_CMD_PTP
1312  * Perform PTP operation
1313  */
1314 #define MC_CMD_PTP 0xb
1315 
1316 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1317 
1318 /* MC_CMD_PTP_IN msgrequest */
1319 #define    MC_CMD_PTP_IN_LEN 1
1320 /* PTP operation code */
1321 #define       MC_CMD_PTP_IN_OP_OFST 0
1322 #define       MC_CMD_PTP_IN_OP_LEN 1
1323 /* enum: Enable PTP packet timestamping operation. */
1324 #define          MC_CMD_PTP_OP_ENABLE 0x1
1325 /* enum: Disable PTP packet timestamping operation. */
1326 #define          MC_CMD_PTP_OP_DISABLE 0x2
1327 /* enum: Send a PTP packet. This operation is used on Siena and Huntington.
1328  * From Medford onwards it is not supported: on those platforms PTP transmit
1329  * timestamping is done using the fast path.
1330  */
1331 #define          MC_CMD_PTP_OP_TRANSMIT 0x3
1332 /* enum: Read the current NIC time. */
1333 #define          MC_CMD_PTP_OP_READ_NIC_TIME 0x4
1334 /* enum: Get the current PTP status. Note that the clock frequency returned (in
1335  * Hz) is rounded to the nearest MHz (e.g. 666000000 for 666666666).
1336  */
1337 #define          MC_CMD_PTP_OP_STATUS 0x5
1338 /* enum: Adjust the PTP NIC's time. */
1339 #define          MC_CMD_PTP_OP_ADJUST 0x6
1340 /* enum: Synchronize host and NIC time. */
1341 #define          MC_CMD_PTP_OP_SYNCHRONIZE 0x7
1342 /* enum: Basic manufacturing tests. Siena PTP adapters only. */
1343 #define          MC_CMD_PTP_OP_MANFTEST_BASIC 0x8
1344 /* enum: Packet based manufacturing tests. Siena PTP adapters only. */
1345 #define          MC_CMD_PTP_OP_MANFTEST_PACKET 0x9
1346 /* enum: Reset some of the PTP related statistics */
1347 #define          MC_CMD_PTP_OP_RESET_STATS 0xa
1348 /* enum: Debug operations to MC. */
1349 #define          MC_CMD_PTP_OP_DEBUG 0xb
1350 /* enum: Read an FPGA register. Siena PTP adapters only. */
1351 #define          MC_CMD_PTP_OP_FPGAREAD 0xc
1352 /* enum: Write an FPGA register. Siena PTP adapters only. */
1353 #define          MC_CMD_PTP_OP_FPGAWRITE 0xd
1354 /* enum: Apply an offset to the NIC clock */
1355 #define          MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe
1356 /* enum: Change the frequency correction applied to the NIC clock */
1357 #define          MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf
1358 /* enum: Set the MC packet filter VLAN tags for received PTP packets.
1359  * Deprecated for Huntington onwards.
1360  */
1361 #define          MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10
1362 /* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for
1363  * Huntington onwards.
1364  */
1365 #define          MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11
1366 /* enum: Set the MC packet filter Domain for received PTP packets. Deprecated
1367  * for Huntington onwards.
1368  */
1369 #define          MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12
1370 /* enum: Set the clock source. Required for snapper tests on Huntington and
1371  * Medford. Not implemented for Siena or Medford2.
1372  */
1373 #define          MC_CMD_PTP_OP_SET_CLK_SRC 0x13
1374 /* enum: Reset value of Timer Reg. Not implemented. */
1375 #define          MC_CMD_PTP_OP_RST_CLK 0x14
1376 /* enum: Enable the forwarding of PPS events to the host */
1377 #define          MC_CMD_PTP_OP_PPS_ENABLE 0x15
1378 /* enum: Get the time format used by this NIC for PTP operations */
1379 #define          MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16
1380 /* enum: Get the clock attributes. NOTE- extended version of
1381  * MC_CMD_PTP_OP_GET_TIME_FORMAT
1382  */
1383 #define          MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16
1384 /* enum: Get corrections that should be applied to the various different
1385  * timestamps
1386  */
1387 #define          MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17
1388 /* enum: Subscribe to receive periodic time events indicating the current NIC
1389  * time
1390  */
1391 #define          MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18
1392 /* enum: Unsubscribe to stop receiving time events */
1393 #define          MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19
1394 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS
1395  * input on the same NIC. Siena PTP adapters only.
1396  */
1397 #define          MC_CMD_PTP_OP_MANFTEST_PPS 0x1a
1398 /* enum: Set the PTP sync status. Status is used by firmware to report to event
1399  * subscribers.
1400  */
1401 #define          MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b
1402 /* enum: Above this for future use. */
1403 #define          MC_CMD_PTP_OP_MAX 0x1c
1404 
1405 /* MC_CMD_PTP_IN_ENABLE msgrequest */
1406 #define    MC_CMD_PTP_IN_ENABLE_LEN 16
1407 #define       MC_CMD_PTP_IN_CMD_OFST 0
1408 #define       MC_CMD_PTP_IN_CMD_LEN 4
1409 #define       MC_CMD_PTP_IN_PERIPH_ID_OFST 4
1410 #define       MC_CMD_PTP_IN_PERIPH_ID_LEN 4
1411 /* Not used. Events are always sent to function relative queue 0. */
1412 #define       MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8
1413 #define       MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4
1414 /* PTP timestamping mode. Not used from Huntington onwards. */
1415 #define       MC_CMD_PTP_IN_ENABLE_MODE_OFST 12
1416 #define       MC_CMD_PTP_IN_ENABLE_MODE_LEN 4
1417 /* enum: PTP, version 1 */
1418 #define          MC_CMD_PTP_MODE_V1 0x0
1419 /* enum: PTP, version 1, with VLAN headers - deprecated */
1420 #define          MC_CMD_PTP_MODE_V1_VLAN 0x1
1421 /* enum: PTP, version 2 */
1422 #define          MC_CMD_PTP_MODE_V2 0x2
1423 /* enum: PTP, version 2, with VLAN headers - deprecated */
1424 #define          MC_CMD_PTP_MODE_V2_VLAN 0x3
1425 /* enum: PTP, version 2, with improved UUID filtering */
1426 #define          MC_CMD_PTP_MODE_V2_ENHANCED 0x4
1427 /* enum: FCoE (seconds and microseconds) */
1428 #define          MC_CMD_PTP_MODE_FCOE 0x5
1429 
1430 /* MC_CMD_PTP_IN_DISABLE msgrequest */
1431 #define    MC_CMD_PTP_IN_DISABLE_LEN 8
1432 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1433 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1434 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1435 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1436 
1437 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */
1438 #define    MC_CMD_PTP_IN_TRANSMIT_LENMIN 13
1439 #define    MC_CMD_PTP_IN_TRANSMIT_LENMAX 252
1440 #define    MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
1441 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1442 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1443 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1444 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1445 /* Transmit packet length */
1446 #define       MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8
1447 #define       MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4
1448 /* Transmit packet data */
1449 #define       MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12
1450 #define       MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
1451 #define       MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
1452 #define       MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240
1453 
1454 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */
1455 #define    MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8
1456 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1457 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1458 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1459 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1460 
1461 /* MC_CMD_PTP_IN_READ_NIC_TIME_V2 msgrequest */
1462 #define    MC_CMD_PTP_IN_READ_NIC_TIME_V2_LEN 8
1463 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1464 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1465 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1466 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1467 
1468 /* MC_CMD_PTP_IN_STATUS msgrequest */
1469 #define    MC_CMD_PTP_IN_STATUS_LEN 8
1470 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1471 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1472 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1473 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1474 
1475 /* MC_CMD_PTP_IN_ADJUST msgrequest */
1476 #define    MC_CMD_PTP_IN_ADJUST_LEN 24
1477 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1478 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1479 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1480 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1481 /* Frequency adjustment 40 bit fixed point ns */
1482 #define       MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
1483 #define       MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
1484 #define       MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
1485 #define       MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
1486 /* enum: Number of fractional bits in frequency adjustment */
1487 #define          MC_CMD_PTP_IN_ADJUST_BITS 0x28
1488 /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
1489  * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES
1490  * field.
1491  */
1492 #define          MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c
1493 /* Time adjustment in seconds */
1494 #define       MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16
1495 #define       MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4
1496 /* Time adjustment major value */
1497 #define       MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16
1498 #define       MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4
1499 /* Time adjustment in nanoseconds */
1500 #define       MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20
1501 #define       MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4
1502 /* Time adjustment minor value */
1503 #define       MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20
1504 #define       MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4
1505 
1506 /* MC_CMD_PTP_IN_ADJUST_V2 msgrequest */
1507 #define    MC_CMD_PTP_IN_ADJUST_V2_LEN 28
1508 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1509 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1510 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1511 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1512 /* Frequency adjustment 40 bit fixed point ns */
1513 #define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8
1514 #define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8
1515 #define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8
1516 #define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12
1517 /* enum: Number of fractional bits in frequency adjustment */
1518 /*               MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
1519 /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
1520  * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES
1521  * field.
1522  */
1523 /*               MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */
1524 /* Time adjustment in seconds */
1525 #define       MC_CMD_PTP_IN_ADJUST_V2_SECONDS_OFST 16
1526 #define       MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4
1527 /* Time adjustment major value */
1528 #define       MC_CMD_PTP_IN_ADJUST_V2_MAJOR_OFST 16
1529 #define       MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4
1530 /* Time adjustment in nanoseconds */
1531 #define       MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_OFST 20
1532 #define       MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4
1533 /* Time adjustment minor value */
1534 #define       MC_CMD_PTP_IN_ADJUST_V2_MINOR_OFST 20
1535 #define       MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4
1536 /* Upper 32bits of major time offset adjustment */
1537 #define       MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_OFST 24
1538 #define       MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4
1539 
1540 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */
1541 #define    MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20
1542 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1543 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1544 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1545 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1546 /* Number of time readings to capture */
1547 #define       MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8
1548 #define       MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4
1549 /* Host address in which to write "synchronization started" indication (64
1550  * bits)
1551  */
1552 #define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
1553 #define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
1554 #define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
1555 #define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16
1556 
1557 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */
1558 #define    MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8
1559 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1560 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1561 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1562 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1563 
1564 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */
1565 #define    MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12
1566 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1567 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1568 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1569 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1570 /* Enable or disable packet testing */
1571 #define       MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
1572 #define       MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4
1573 
1574 /* MC_CMD_PTP_IN_RESET_STATS msgrequest: Reset PTP statistics */
1575 #define    MC_CMD_PTP_IN_RESET_STATS_LEN 8
1576 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1577 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1578 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1579 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1580 
1581 /* MC_CMD_PTP_IN_DEBUG msgrequest */
1582 #define    MC_CMD_PTP_IN_DEBUG_LEN 12
1583 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1584 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1585 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1586 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1587 /* Debug operations */
1588 #define       MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8
1589 #define       MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4
1590 
1591 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */
1592 #define    MC_CMD_PTP_IN_FPGAREAD_LEN 16
1593 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1594 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1595 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1596 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1597 #define       MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8
1598 #define       MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4
1599 #define       MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12
1600 #define       MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4
1601 
1602 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */
1603 #define    MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13
1604 #define    MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252
1605 #define    MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))
1606 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1607 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1608 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1609 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1610 #define       MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8
1611 #define       MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4
1612 #define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12
1613 #define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1
1614 #define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1
1615 #define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240
1616 
1617 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */
1618 #define    MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16
1619 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1620 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1621 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1622 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1623 /* Time adjustment in seconds */
1624 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8
1625 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4
1626 /* Time adjustment major value */
1627 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8
1628 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4
1629 /* Time adjustment in nanoseconds */
1630 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12
1631 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4
1632 /* Time adjustment minor value */
1633 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12
1634 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4
1635 
1636 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2 msgrequest */
1637 #define    MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_LEN 20
1638 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1639 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1640 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1641 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1642 /* Time adjustment in seconds */
1643 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_OFST 8
1644 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4
1645 /* Time adjustment major value */
1646 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_OFST 8
1647 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4
1648 /* Time adjustment in nanoseconds */
1649 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_OFST 12
1650 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4
1651 /* Time adjustment minor value */
1652 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_OFST 12
1653 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4
1654 /* Upper 32bits of major time offset adjustment */
1655 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_OFST 16
1656 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4
1657 
1658 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */
1659 #define    MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16
1660 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1661 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1662 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1663 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1664 /* Frequency adjustment 40 bit fixed point ns */
1665 #define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8
1666 #define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8
1667 #define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8
1668 #define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12
1669 /*            Enum values, see field(s): */
1670 /*               MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */
1671 
1672 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */
1673 #define    MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24
1674 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1675 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1676 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1677 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1678 /* Number of VLAN tags, 0 if not VLAN */
1679 #define       MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8
1680 #define       MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4
1681 /* Set of VLAN tags to filter against */
1682 #define       MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12
1683 #define       MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
1684 #define       MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3
1685 
1686 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */
1687 #define    MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20
1688 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1689 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1690 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1691 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1692 /* 1 to enable UUID filtering, 0 to disable */
1693 #define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8
1694 #define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4
1695 /* UUID to filter against */
1696 #define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12
1697 #define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8
1698 #define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12
1699 #define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16
1700 
1701 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */
1702 #define    MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16
1703 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1704 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1705 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1706 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1707 /* 1 to enable Domain filtering, 0 to disable */
1708 #define       MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8
1709 #define       MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4
1710 /* Domain number to filter against */
1711 #define       MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12
1712 #define       MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4
1713 
1714 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */
1715 #define    MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12
1716 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1717 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1718 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1719 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1720 /* Set the clock source. */
1721 #define       MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8
1722 #define       MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4
1723 /* enum: Internal. */
1724 #define          MC_CMD_PTP_CLK_SRC_INTERNAL 0x0
1725 /* enum: External. */
1726 #define          MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
1727 
1728 /* MC_CMD_PTP_IN_RST_CLK msgrequest: Reset value of Timer Reg. */
1729 #define    MC_CMD_PTP_IN_RST_CLK_LEN 8
1730 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1731 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1732 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1733 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1734 
1735 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */
1736 #define    MC_CMD_PTP_IN_PPS_ENABLE_LEN 12
1737 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1738 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1739 /* Enable or disable */
1740 #define       MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
1741 #define       MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4
1742 /* enum: Enable */
1743 #define          MC_CMD_PTP_ENABLE_PPS 0x0
1744 /* enum: Disable */
1745 #define          MC_CMD_PTP_DISABLE_PPS 0x1
1746 /* Not used. Events are always sent to function relative queue 0. */
1747 #define       MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8
1748 #define       MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4
1749 
1750 /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */
1751 #define    MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8
1752 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1753 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1754 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1755 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1756 
1757 /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */
1758 #define    MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8
1759 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1760 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1761 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1762 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1763 
1764 /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */
1765 #define    MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8
1766 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1767 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1768 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1769 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1770 
1771 /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */
1772 #define    MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12
1773 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1774 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1775 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1776 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1777 /* Original field containing queue ID. Now extended to include flags. */
1778 #define       MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8
1779 #define       MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4
1780 #define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0
1781 #define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16
1782 #define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31
1783 #define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1
1784 
1785 /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */
1786 #define    MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16
1787 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1788 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1789 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1790 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1791 /* Unsubscribe options */
1792 #define       MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8
1793 #define       MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4
1794 /* enum: Unsubscribe a single queue */
1795 #define          MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0
1796 /* enum: Unsubscribe all queues */
1797 #define          MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1
1798 /* Event queue ID */
1799 #define       MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12
1800 #define       MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4
1801 
1802 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */
1803 #define    MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12
1804 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1805 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1806 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1807 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1808 /* 1 to enable PPS test mode, 0 to disable and return result. */
1809 #define       MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8
1810 #define       MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4
1811 
1812 /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */
1813 #define    MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24
1814 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1815 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1816 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1817 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1818 /* NIC - Host System Clock Synchronization status */
1819 #define       MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8
1820 #define       MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4
1821 /* enum: Host System clock and NIC clock are not in sync */
1822 #define          MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0
1823 /* enum: Host System clock and NIC clock are synchronized */
1824 #define          MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1
1825 /* If synchronized, number of seconds until clocks should be considered to be
1826  * no longer in sync.
1827  */
1828 #define       MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12
1829 #define       MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4
1830 #define       MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16
1831 #define       MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4
1832 #define       MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20
1833 #define       MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4
1834 
1835 /* MC_CMD_PTP_OUT msgresponse */
1836 #define    MC_CMD_PTP_OUT_LEN 0
1837 
1838 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */
1839 #define    MC_CMD_PTP_OUT_TRANSMIT_LEN 8
1840 /* Value of seconds timestamp */
1841 #define       MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
1842 #define       MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4
1843 /* Timestamp major value */
1844 #define       MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0
1845 #define       MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4
1846 /* Value of nanoseconds timestamp */
1847 #define       MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
1848 #define       MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4
1849 /* Timestamp minor value */
1850 #define       MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4
1851 #define       MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4
1852 
1853 /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */
1854 #define    MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0
1855 
1856 /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */
1857 #define    MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0
1858 
1859 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */
1860 #define    MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8
1861 /* Value of seconds timestamp */
1862 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
1863 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4
1864 /* Timestamp major value */
1865 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0
1866 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4
1867 /* Value of nanoseconds timestamp */
1868 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
1869 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4
1870 /* Timestamp minor value */
1871 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4
1872 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4
1873 
1874 /* MC_CMD_PTP_OUT_READ_NIC_TIME_V2 msgresponse */
1875 #define    MC_CMD_PTP_OUT_READ_NIC_TIME_V2_LEN 12
1876 /* Value of seconds timestamp */
1877 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0
1878 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4
1879 /* Timestamp major value */
1880 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0
1881 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4
1882 /* Value of nanoseconds timestamp */
1883 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4
1884 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4
1885 /* Timestamp minor value */
1886 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4
1887 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4
1888 /* Upper 32bits of major timestamp value */
1889 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_OFST 8
1890 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4
1891 
1892 /* MC_CMD_PTP_OUT_STATUS msgresponse */
1893 #define    MC_CMD_PTP_OUT_STATUS_LEN 64
1894 /* Frequency of NIC's hardware clock */
1895 #define       MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
1896 #define       MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4
1897 /* Number of packets transmitted and timestamped */
1898 #define       MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
1899 #define       MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4
1900 /* Number of packets received and timestamped */
1901 #define       MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8
1902 #define       MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4
1903 /* Number of packets timestamped by the FPGA */
1904 #define       MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12
1905 #define       MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4
1906 /* Number of packets filter matched */
1907 #define       MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16
1908 #define       MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4
1909 /* Number of packets not filter matched */
1910 #define       MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20
1911 #define       MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4
1912 /* Number of PPS overflows (noise on input?) */
1913 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24
1914 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4
1915 /* Number of PPS bad periods */
1916 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28
1917 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4
1918 /* Minimum period of PPS pulse in nanoseconds */
1919 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32
1920 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4
1921 /* Maximum period of PPS pulse in nanoseconds */
1922 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36
1923 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4
1924 /* Last period of PPS pulse in nanoseconds */
1925 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40
1926 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4
1927 /* Mean period of PPS pulse in nanoseconds */
1928 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44
1929 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4
1930 /* Minimum offset of PPS pulse in nanoseconds (signed) */
1931 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48
1932 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4
1933 /* Maximum offset of PPS pulse in nanoseconds (signed) */
1934 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52
1935 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4
1936 /* Last offset of PPS pulse in nanoseconds (signed) */
1937 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56
1938 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4
1939 /* Mean offset of PPS pulse in nanoseconds (signed) */
1940 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60
1941 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4
1942 
1943 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */
1944 #define    MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20
1945 #define    MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240
1946 #define    MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
1947 /* A set of host and NIC times */
1948 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
1949 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20
1950 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
1951 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12
1952 /* Host time immediately before NIC's hardware clock read */
1953 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
1954 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4
1955 /* Value of seconds timestamp */
1956 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
1957 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4
1958 /* Timestamp major value */
1959 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4
1960 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4
1961 /* Value of nanoseconds timestamp */
1962 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8
1963 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4
1964 /* Timestamp minor value */
1965 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8
1966 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4
1967 /* Host time immediately after NIC's hardware clock read */
1968 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12
1969 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4
1970 /* Number of nanoseconds waited after reading NIC's hardware clock */
1971 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16
1972 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4
1973 
1974 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */
1975 #define    MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8
1976 /* Results of testing */
1977 #define       MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
1978 #define       MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4
1979 /* enum: Successful test */
1980 #define          MC_CMD_PTP_MANF_SUCCESS 0x0
1981 /* enum: FPGA load failed */
1982 #define          MC_CMD_PTP_MANF_FPGA_LOAD 0x1
1983 /* enum: FPGA version invalid */
1984 #define          MC_CMD_PTP_MANF_FPGA_VERSION 0x2
1985 /* enum: FPGA registers incorrect */
1986 #define          MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3
1987 /* enum: Oscillator possibly not working? */
1988 #define          MC_CMD_PTP_MANF_OSCILLATOR 0x4
1989 /* enum: Timestamps not increasing */
1990 #define          MC_CMD_PTP_MANF_TIMESTAMPS 0x5
1991 /* enum: Mismatched packet count */
1992 #define          MC_CMD_PTP_MANF_PACKET_COUNT 0x6
1993 /* enum: Mismatched packet count (Siena filter and FPGA) */
1994 #define          MC_CMD_PTP_MANF_FILTER_COUNT 0x7
1995 /* enum: Not enough packets to perform timestamp check */
1996 #define          MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8
1997 /* enum: Timestamp trigger GPIO not working */
1998 #define          MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9
1999 /* enum: Insufficient PPS events to perform checks */
2000 #define          MC_CMD_PTP_MANF_PPS_ENOUGH 0xa
2001 /* enum: PPS time event period not sufficiently close to 1s. */
2002 #define          MC_CMD_PTP_MANF_PPS_PERIOD 0xb
2003 /* enum: PPS time event nS reading not sufficiently close to zero. */
2004 #define          MC_CMD_PTP_MANF_PPS_NS 0xc
2005 /* enum: PTP peripheral registers incorrect */
2006 #define          MC_CMD_PTP_MANF_REGISTERS 0xd
2007 /* enum: Failed to read time from PTP peripheral */
2008 #define          MC_CMD_PTP_MANF_CLOCK_READ 0xe
2009 /* Presence of external oscillator */
2010 #define       MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
2011 #define       MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4
2012 
2013 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */
2014 #define    MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12
2015 /* Results of testing */
2016 #define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
2017 #define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4
2018 /* Number of packets received by FPGA */
2019 #define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
2020 #define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4
2021 /* Number of packets received by Siena filters */
2022 #define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8
2023 #define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4
2024 
2025 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */
2026 #define    MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1
2027 #define    MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252
2028 #define    MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
2029 #define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
2030 #define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1
2031 #define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1
2032 #define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252
2033 
2034 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */
2035 #define    MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4
2036 /* Time format required/used by for this NIC. Applies to all PTP MCDI
2037  * operations that pass times between the host and firmware. If this operation
2038  * is not supported (older firmware) a format of seconds and nanoseconds should
2039  * be assumed. Note this enum is deprecated. Do not add to it- use the
2040  * TIME_FORMAT field in MC_CMD_PTP_OUT_GET_ATTRIBUTES instead.
2041  */
2042 #define       MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0
2043 #define       MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4
2044 /* enum: Times are in seconds and nanoseconds */
2045 #define          MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0
2046 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
2047 #define          MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1
2048 /* enum: Major register has units of seconds, minor 2^-27s per tick */
2049 #define          MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2
2050 
2051 /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */
2052 #define    MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24
2053 /* Time format required/used by for this NIC. Applies to all PTP MCDI
2054  * operations that pass times between the host and firmware. If this operation
2055  * is not supported (older firmware) a format of seconds and nanoseconds should
2056  * be assumed.
2057  */
2058 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0
2059 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4
2060 /* enum: Times are in seconds and nanoseconds */
2061 #define          MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0
2062 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
2063 #define          MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1
2064 /* enum: Major register has units of seconds, minor 2^-27s per tick */
2065 #define          MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2
2066 /* enum: Major register units are seconds, minor units are quarter nanoseconds
2067  */
2068 #define          MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3
2069 /* Minimum acceptable value for a corrected synchronization timeset. When
2070  * comparing host and NIC clock times, the MC returns a set of samples that
2071  * contain the host start and end time, the MC time when the host start was
2072  * detected and the time the MC waited between reading the time and detecting
2073  * the host end. The corrected sync window is the difference between the host
2074  * end and start times minus the time that the MC waited for host end.
2075  */
2076 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4
2077 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4
2078 /* Various PTP capabilities */
2079 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8
2080 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4
2081 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0
2082 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1
2083 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1
2084 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1
2085 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 2
2086 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1
2087 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 3
2088 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1
2089 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12
2090 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4
2091 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16
2092 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4
2093 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20
2094 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4
2095 
2096 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */
2097 #define    MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16
2098 /* Uncorrected error on PTP transmit timestamps in NIC clock format */
2099 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0
2100 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4
2101 /* Uncorrected error on PTP receive timestamps in NIC clock format */
2102 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4
2103 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4
2104 /* Uncorrected error on PPS output in NIC clock format */
2105 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8
2106 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4
2107 /* Uncorrected error on PPS input in NIC clock format */
2108 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12
2109 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4
2110 
2111 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */
2112 #define    MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24
2113 /* Uncorrected error on PTP transmit timestamps in NIC clock format */
2114 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0
2115 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4
2116 /* Uncorrected error on PTP receive timestamps in NIC clock format */
2117 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4
2118 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4
2119 /* Uncorrected error on PPS output in NIC clock format */
2120 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8
2121 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4
2122 /* Uncorrected error on PPS input in NIC clock format */
2123 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12
2124 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4
2125 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */
2126 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16
2127 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4
2128 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */
2129 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20
2130 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4
2131 
2132 /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */
2133 #define    MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4
2134 /* Results of testing */
2135 #define       MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0
2136 #define       MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4
2137 /*            Enum values, see field(s): */
2138 /*               MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */
2139 
2140 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */
2141 #define    MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0
2142 
2143 
2144 /***********************************/
2145 /* MC_CMD_CSR_READ32
2146  * Read 32bit words from the indirect memory map.
2147  */
2148 #define MC_CMD_CSR_READ32 0xc
2149 
2150 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2151 
2152 /* MC_CMD_CSR_READ32_IN msgrequest */
2153 #define    MC_CMD_CSR_READ32_IN_LEN 12
2154 /* Address */
2155 #define       MC_CMD_CSR_READ32_IN_ADDR_OFST 0
2156 #define       MC_CMD_CSR_READ32_IN_ADDR_LEN 4
2157 #define       MC_CMD_CSR_READ32_IN_STEP_OFST 4
2158 #define       MC_CMD_CSR_READ32_IN_STEP_LEN 4
2159 #define       MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8
2160 #define       MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4
2161 
2162 /* MC_CMD_CSR_READ32_OUT msgresponse */
2163 #define    MC_CMD_CSR_READ32_OUT_LENMIN 4
2164 #define    MC_CMD_CSR_READ32_OUT_LENMAX 252
2165 #define    MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
2166 /* The last dword is the status, not a value read */
2167 #define       MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
2168 #define       MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
2169 #define       MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1
2170 #define       MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63
2171 
2172 
2173 /***********************************/
2174 /* MC_CMD_CSR_WRITE32
2175  * Write 32bit dwords to the indirect memory map.
2176  */
2177 #define MC_CMD_CSR_WRITE32 0xd
2178 
2179 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2180 
2181 /* MC_CMD_CSR_WRITE32_IN msgrequest */
2182 #define    MC_CMD_CSR_WRITE32_IN_LENMIN 12
2183 #define    MC_CMD_CSR_WRITE32_IN_LENMAX 252
2184 #define    MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
2185 /* Address */
2186 #define       MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
2187 #define       MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4
2188 #define       MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
2189 #define       MC_CMD_CSR_WRITE32_IN_STEP_LEN 4
2190 #define       MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8
2191 #define       MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
2192 #define       MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1
2193 #define       MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61
2194 
2195 /* MC_CMD_CSR_WRITE32_OUT msgresponse */
2196 #define    MC_CMD_CSR_WRITE32_OUT_LEN 4
2197 #define       MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
2198 #define       MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4
2199 
2200 
2201 /***********************************/
2202 /* MC_CMD_HP
2203  * These commands are used for HP related features. They are grouped under one
2204  * MCDI command to avoid creating too many MCDI commands.
2205  */
2206 #define MC_CMD_HP 0x54
2207 
2208 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN
2209 
2210 /* MC_CMD_HP_IN msgrequest */
2211 #define    MC_CMD_HP_IN_LEN 16
2212 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at
2213  * the specified address with the specified interval.When address is NULL,
2214  * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current
2215  * state / 2: (debug) Show temperature reported by one of the supported
2216  * sensors.
2217  */
2218 #define       MC_CMD_HP_IN_SUBCMD_OFST 0
2219 #define       MC_CMD_HP_IN_SUBCMD_LEN 4
2220 /* enum: OCSD (Option Card Sensor Data) sub-command. */
2221 #define          MC_CMD_HP_IN_OCSD_SUBCMD 0x0
2222 /* enum: Last known valid HP sub-command. */
2223 #define          MC_CMD_HP_IN_LAST_SUBCMD 0x0
2224 /* The address to the array of sensor fields. (Or NULL to use a sub-command.)
2225  */
2226 #define       MC_CMD_HP_IN_OCSD_ADDR_OFST 4
2227 #define       MC_CMD_HP_IN_OCSD_ADDR_LEN 8
2228 #define       MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
2229 #define       MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8
2230 /* The requested update interval, in seconds. (Or the sub-command if ADDR is
2231  * NULL.)
2232  */
2233 #define       MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12
2234 #define       MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4
2235 
2236 /* MC_CMD_HP_OUT msgresponse */
2237 #define    MC_CMD_HP_OUT_LEN 4
2238 #define       MC_CMD_HP_OUT_OCSD_STATUS_OFST 0
2239 #define       MC_CMD_HP_OUT_OCSD_STATUS_LEN 4
2240 /* enum: OCSD stopped for this card. */
2241 #define          MC_CMD_HP_OUT_OCSD_STOPPED 0x1
2242 /* enum: OCSD was successfully started with the address provided. */
2243 #define          MC_CMD_HP_OUT_OCSD_STARTED 0x2
2244 /* enum: OCSD was already started for this card. */
2245 #define          MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3
2246 
2247 
2248 /***********************************/
2249 /* MC_CMD_STACKINFO
2250  * Get stack information.
2251  */
2252 #define MC_CMD_STACKINFO 0xf
2253 
2254 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN
2255 
2256 /* MC_CMD_STACKINFO_IN msgrequest */
2257 #define    MC_CMD_STACKINFO_IN_LEN 0
2258 
2259 /* MC_CMD_STACKINFO_OUT msgresponse */
2260 #define    MC_CMD_STACKINFO_OUT_LENMIN 12
2261 #define    MC_CMD_STACKINFO_OUT_LENMAX 252
2262 #define    MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
2263 /* (thread ptr, stack size, free space) for each thread in system */
2264 #define       MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
2265 #define       MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12
2266 #define       MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1
2267 #define       MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21
2268 
2269 
2270 /***********************************/
2271 /* MC_CMD_MDIO_READ
2272  * MDIO register read.
2273  */
2274 #define MC_CMD_MDIO_READ 0x10
2275 
2276 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2277 
2278 /* MC_CMD_MDIO_READ_IN msgrequest */
2279 #define    MC_CMD_MDIO_READ_IN_LEN 16
2280 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for
2281  * external devices.
2282  */
2283 #define       MC_CMD_MDIO_READ_IN_BUS_OFST 0
2284 #define       MC_CMD_MDIO_READ_IN_BUS_LEN 4
2285 /* enum: Internal. */
2286 #define          MC_CMD_MDIO_BUS_INTERNAL 0x0
2287 /* enum: External. */
2288 #define          MC_CMD_MDIO_BUS_EXTERNAL 0x1
2289 /* Port address */
2290 #define       MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
2291 #define       MC_CMD_MDIO_READ_IN_PRTAD_LEN 4
2292 /* Device Address or clause 22. */
2293 #define       MC_CMD_MDIO_READ_IN_DEVAD_OFST 8
2294 #define       MC_CMD_MDIO_READ_IN_DEVAD_LEN 4
2295 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
2296  * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
2297  */
2298 #define          MC_CMD_MDIO_CLAUSE22 0x20
2299 /* Address */
2300 #define       MC_CMD_MDIO_READ_IN_ADDR_OFST 12
2301 #define       MC_CMD_MDIO_READ_IN_ADDR_LEN 4
2302 
2303 /* MC_CMD_MDIO_READ_OUT msgresponse */
2304 #define    MC_CMD_MDIO_READ_OUT_LEN 8
2305 /* Value */
2306 #define       MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
2307 #define       MC_CMD_MDIO_READ_OUT_VALUE_LEN 4
2308 /* Status the MDIO commands return the raw status bits from the MDIO block. A
2309  * "good" transaction should have the DONE bit set and all other bits clear.
2310  */
2311 #define       MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
2312 #define       MC_CMD_MDIO_READ_OUT_STATUS_LEN 4
2313 /* enum: Good. */
2314 #define          MC_CMD_MDIO_STATUS_GOOD 0x8
2315 
2316 
2317 /***********************************/
2318 /* MC_CMD_MDIO_WRITE
2319  * MDIO register write.
2320  */
2321 #define MC_CMD_MDIO_WRITE 0x11
2322 
2323 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN
2324 
2325 /* MC_CMD_MDIO_WRITE_IN msgrequest */
2326 #define    MC_CMD_MDIO_WRITE_IN_LEN 20
2327 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for
2328  * external devices.
2329  */
2330 #define       MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
2331 #define       MC_CMD_MDIO_WRITE_IN_BUS_LEN 4
2332 /* enum: Internal. */
2333 /*               MC_CMD_MDIO_BUS_INTERNAL 0x0 */
2334 /* enum: External. */
2335 /*               MC_CMD_MDIO_BUS_EXTERNAL 0x1 */
2336 /* Port address */
2337 #define       MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
2338 #define       MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4
2339 /* Device Address or clause 22. */
2340 #define       MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8
2341 #define       MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4
2342 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
2343  * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
2344  */
2345 /*               MC_CMD_MDIO_CLAUSE22 0x20 */
2346 /* Address */
2347 #define       MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12
2348 #define       MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4
2349 /* Value */
2350 #define       MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16
2351 #define       MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4
2352 
2353 /* MC_CMD_MDIO_WRITE_OUT msgresponse */
2354 #define    MC_CMD_MDIO_WRITE_OUT_LEN 4
2355 /* Status; the MDIO commands return the raw status bits from the MDIO block. A
2356  * "good" transaction should have the DONE bit set and all other bits clear.
2357  */
2358 #define       MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
2359 #define       MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4
2360 /* enum: Good. */
2361 /*               MC_CMD_MDIO_STATUS_GOOD 0x8 */
2362 
2363 
2364 /***********************************/
2365 /* MC_CMD_DBI_WRITE
2366  * Write DBI register(s).
2367  */
2368 #define MC_CMD_DBI_WRITE 0x12
2369 
2370 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2371 
2372 /* MC_CMD_DBI_WRITE_IN msgrequest */
2373 #define    MC_CMD_DBI_WRITE_IN_LENMIN 12
2374 #define    MC_CMD_DBI_WRITE_IN_LENMAX 252
2375 #define    MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
2376 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset
2377  * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF.
2378  */
2379 #define       MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0
2380 #define       MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12
2381 #define       MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1
2382 #define       MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21
2383 
2384 /* MC_CMD_DBI_WRITE_OUT msgresponse */
2385 #define    MC_CMD_DBI_WRITE_OUT_LEN 0
2386 
2387 /* MC_CMD_DBIWROP_TYPEDEF structuredef */
2388 #define    MC_CMD_DBIWROP_TYPEDEF_LEN 12
2389 #define       MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0
2390 #define       MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4
2391 #define       MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0
2392 #define       MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32
2393 #define       MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4
2394 #define       MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4
2395 #define        MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16
2396 #define        MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16
2397 #define        MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15
2398 #define        MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1
2399 #define        MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14
2400 #define        MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1
2401 #define       MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32
2402 #define       MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32
2403 #define       MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8
2404 #define       MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4
2405 #define       MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64
2406 #define       MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32
2407 
2408 
2409 /***********************************/
2410 /* MC_CMD_PORT_READ32
2411  * Read a 32-bit register from the indirect port register map. The port to
2412  * access is implied by the Shared memory channel used.
2413  */
2414 #define MC_CMD_PORT_READ32 0x14
2415 
2416 /* MC_CMD_PORT_READ32_IN msgrequest */
2417 #define    MC_CMD_PORT_READ32_IN_LEN 4
2418 /* Address */
2419 #define       MC_CMD_PORT_READ32_IN_ADDR_OFST 0
2420 #define       MC_CMD_PORT_READ32_IN_ADDR_LEN 4
2421 
2422 /* MC_CMD_PORT_READ32_OUT msgresponse */
2423 #define    MC_CMD_PORT_READ32_OUT_LEN 8
2424 /* Value */
2425 #define       MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
2426 #define       MC_CMD_PORT_READ32_OUT_VALUE_LEN 4
2427 /* Status */
2428 #define       MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
2429 #define       MC_CMD_PORT_READ32_OUT_STATUS_LEN 4
2430 
2431 
2432 /***********************************/
2433 /* MC_CMD_PORT_WRITE32
2434  * Write a 32-bit register to the indirect port register map. The port to
2435  * access is implied by the Shared memory channel used.
2436  */
2437 #define MC_CMD_PORT_WRITE32 0x15
2438 
2439 /* MC_CMD_PORT_WRITE32_IN msgrequest */
2440 #define    MC_CMD_PORT_WRITE32_IN_LEN 8
2441 /* Address */
2442 #define       MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
2443 #define       MC_CMD_PORT_WRITE32_IN_ADDR_LEN 4
2444 /* Value */
2445 #define       MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
2446 #define       MC_CMD_PORT_WRITE32_IN_VALUE_LEN 4
2447 
2448 /* MC_CMD_PORT_WRITE32_OUT msgresponse */
2449 #define    MC_CMD_PORT_WRITE32_OUT_LEN 4
2450 /* Status */
2451 #define       MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
2452 #define       MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4
2453 
2454 
2455 /***********************************/
2456 /* MC_CMD_PORT_READ128
2457  * Read a 128-bit register from the indirect port register map. The port to
2458  * access is implied by the Shared memory channel used.
2459  */
2460 #define MC_CMD_PORT_READ128 0x16
2461 
2462 /* MC_CMD_PORT_READ128_IN msgrequest */
2463 #define    MC_CMD_PORT_READ128_IN_LEN 4
2464 /* Address */
2465 #define       MC_CMD_PORT_READ128_IN_ADDR_OFST 0
2466 #define       MC_CMD_PORT_READ128_IN_ADDR_LEN 4
2467 
2468 /* MC_CMD_PORT_READ128_OUT msgresponse */
2469 #define    MC_CMD_PORT_READ128_OUT_LEN 20
2470 /* Value */
2471 #define       MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
2472 #define       MC_CMD_PORT_READ128_OUT_VALUE_LEN 16
2473 /* Status */
2474 #define       MC_CMD_PORT_READ128_OUT_STATUS_OFST 16
2475 #define       MC_CMD_PORT_READ128_OUT_STATUS_LEN 4
2476 
2477 
2478 /***********************************/
2479 /* MC_CMD_PORT_WRITE128
2480  * Write a 128-bit register to the indirect port register map. The port to
2481  * access is implied by the Shared memory channel used.
2482  */
2483 #define MC_CMD_PORT_WRITE128 0x17
2484 
2485 /* MC_CMD_PORT_WRITE128_IN msgrequest */
2486 #define    MC_CMD_PORT_WRITE128_IN_LEN 20
2487 /* Address */
2488 #define       MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
2489 #define       MC_CMD_PORT_WRITE128_IN_ADDR_LEN 4
2490 /* Value */
2491 #define       MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
2492 #define       MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16
2493 
2494 /* MC_CMD_PORT_WRITE128_OUT msgresponse */
2495 #define    MC_CMD_PORT_WRITE128_OUT_LEN 4
2496 /* Status */
2497 #define       MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
2498 #define       MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4
2499 
2500 /* MC_CMD_CAPABILITIES structuredef */
2501 #define    MC_CMD_CAPABILITIES_LEN 4
2502 /* Small buf table. */
2503 #define       MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0
2504 #define       MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1
2505 /* Turbo mode (for Maranello). */
2506 #define       MC_CMD_CAPABILITIES_TURBO_LBN 1
2507 #define       MC_CMD_CAPABILITIES_TURBO_WIDTH 1
2508 /* Turbo mode active (for Maranello). */
2509 #define       MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2
2510 #define       MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1
2511 /* PTP offload. */
2512 #define       MC_CMD_CAPABILITIES_PTP_LBN 3
2513 #define       MC_CMD_CAPABILITIES_PTP_WIDTH 1
2514 /* AOE mode. */
2515 #define       MC_CMD_CAPABILITIES_AOE_LBN 4
2516 #define       MC_CMD_CAPABILITIES_AOE_WIDTH 1
2517 /* AOE mode active. */
2518 #define       MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5
2519 #define       MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1
2520 /* AOE mode active. */
2521 #define       MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6
2522 #define       MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1
2523 #define       MC_CMD_CAPABILITIES_RESERVED_LBN 7
2524 #define       MC_CMD_CAPABILITIES_RESERVED_WIDTH 25
2525 
2526 
2527 /***********************************/
2528 /* MC_CMD_GET_BOARD_CFG
2529  * Returns the MC firmware configuration structure.
2530  */
2531 #define MC_CMD_GET_BOARD_CFG 0x18
2532 
2533 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2534 
2535 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */
2536 #define    MC_CMD_GET_BOARD_CFG_IN_LEN 0
2537 
2538 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */
2539 #define    MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96
2540 #define    MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136
2541 #define    MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))
2542 #define       MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
2543 #define       MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4
2544 #define       MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
2545 #define       MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32
2546 /* Capabilities for Siena Port0 (see struct MC_CMD_CAPABILITIES). Unused on
2547  * EF10 and later (use MC_CMD_GET_CAPABILITIES).
2548  */
2549 #define       MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36
2550 #define       MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4
2551 /* Capabilities for Siena Port1 (see struct MC_CMD_CAPABILITIES). Unused on
2552  * EF10 and later (use MC_CMD_GET_CAPABILITIES).
2553  */
2554 #define       MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40
2555 #define       MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4
2556 /* Base MAC address for Siena Port0. Unused on EF10 and later (use
2557  * MC_CMD_GET_MAC_ADDRESSES).
2558  */
2559 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44
2560 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6
2561 /* Base MAC address for Siena Port1. Unused on EF10 and later (use
2562  * MC_CMD_GET_MAC_ADDRESSES).
2563  */
2564 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50
2565 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6
2566 /* Size of MAC address pool for Siena Port0. Unused on EF10 and later (use
2567  * MC_CMD_GET_MAC_ADDRESSES).
2568  */
2569 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56
2570 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4
2571 /* Size of MAC address pool for Siena Port1. Unused on EF10 and later (use
2572  * MC_CMD_GET_MAC_ADDRESSES).
2573  */
2574 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60
2575 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4
2576 /* Increment between addresses in MAC address pool for Siena Port0. Unused on
2577  * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
2578  */
2579 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64
2580 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4
2581 /* Increment between addresses in MAC address pool for Siena Port1. Unused on
2582  * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
2583  */
2584 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68
2585 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4
2586 /* Siena only. This field contains a 16-bit value for each of the types of
2587  * NVRAM area. The values are defined in the firmware/mc/platform/.c file for a
2588  * specific board type, but otherwise have no meaning to the MC; they are used
2589  * by the driver to manage selection of appropriate firmware updates. Unused on
2590  * EF10 and later (use MC_CMD_NVRAM_METADATA).
2591  */
2592 #define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72
2593 #define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2
2594 #define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12
2595 #define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32
2596 
2597 
2598 /***********************************/
2599 /* MC_CMD_DBI_READX
2600  * Read DBI register(s) -- extended functionality
2601  */
2602 #define MC_CMD_DBI_READX 0x19
2603 
2604 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2605 
2606 /* MC_CMD_DBI_READX_IN msgrequest */
2607 #define    MC_CMD_DBI_READX_IN_LENMIN 8
2608 #define    MC_CMD_DBI_READX_IN_LENMAX 248
2609 #define    MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
2610 /* Each Read op consists of an address (offset 0), VF/CS2) */
2611 #define       MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
2612 #define       MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
2613 #define       MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
2614 #define       MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
2615 #define       MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
2616 #define       MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31
2617 
2618 /* MC_CMD_DBI_READX_OUT msgresponse */
2619 #define    MC_CMD_DBI_READX_OUT_LENMIN 4
2620 #define    MC_CMD_DBI_READX_OUT_LENMAX 252
2621 #define    MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
2622 /* Value */
2623 #define       MC_CMD_DBI_READX_OUT_VALUE_OFST 0
2624 #define       MC_CMD_DBI_READX_OUT_VALUE_LEN 4
2625 #define       MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1
2626 #define       MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63
2627 
2628 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */
2629 #define    MC_CMD_DBIRDOP_TYPEDEF_LEN 8
2630 #define       MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0
2631 #define       MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4
2632 #define       MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0
2633 #define       MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32
2634 #define       MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4
2635 #define       MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4
2636 #define        MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16
2637 #define        MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16
2638 #define        MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15
2639 #define        MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1
2640 #define        MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14
2641 #define        MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1
2642 #define       MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32
2643 #define       MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32
2644 
2645 
2646 /***********************************/
2647 /* MC_CMD_SET_RAND_SEED
2648  * Set the 16byte seed for the MC pseudo-random generator.
2649  */
2650 #define MC_CMD_SET_RAND_SEED 0x1a
2651 
2652 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2653 
2654 /* MC_CMD_SET_RAND_SEED_IN msgrequest */
2655 #define    MC_CMD_SET_RAND_SEED_IN_LEN 16
2656 /* Seed value. */
2657 #define       MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
2658 #define       MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16
2659 
2660 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */
2661 #define    MC_CMD_SET_RAND_SEED_OUT_LEN 0
2662 
2663 
2664 /***********************************/
2665 /* MC_CMD_LTSSM_HIST
2666  * Retrieve the history of the LTSSM, if the build supports it.
2667  */
2668 #define MC_CMD_LTSSM_HIST 0x1b
2669 
2670 /* MC_CMD_LTSSM_HIST_IN msgrequest */
2671 #define    MC_CMD_LTSSM_HIST_IN_LEN 0
2672 
2673 /* MC_CMD_LTSSM_HIST_OUT msgresponse */
2674 #define    MC_CMD_LTSSM_HIST_OUT_LENMIN 0
2675 #define    MC_CMD_LTSSM_HIST_OUT_LENMAX 252
2676 #define    MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
2677 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */
2678 #define       MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
2679 #define       MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
2680 #define       MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
2681 #define       MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63
2682 
2683 
2684 /***********************************/
2685 /* MC_CMD_DRV_ATTACH
2686  * Inform MCPU that this port is managed on the host (i.e. driver active). For
2687  * Huntington, also request the preferred datapath firmware to use if possible
2688  * (it may not be possible for this request to be fulfilled; the driver must
2689  * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which
2690  * features are actually available). The FIRMWARE_ID field is ignored by older
2691  * platforms.
2692  */
2693 #define MC_CMD_DRV_ATTACH 0x1c
2694 
2695 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2696 
2697 /* MC_CMD_DRV_ATTACH_IN msgrequest */
2698 #define    MC_CMD_DRV_ATTACH_IN_LEN 12
2699 /* new state to set if UPDATE=1 */
2700 #define       MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
2701 #define       MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4
2702 #define        MC_CMD_DRV_ATTACH_LBN 0
2703 #define        MC_CMD_DRV_ATTACH_WIDTH 1
2704 #define        MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0
2705 #define        MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1
2706 #define        MC_CMD_DRV_PREBOOT_LBN 1
2707 #define        MC_CMD_DRV_PREBOOT_WIDTH 1
2708 #define        MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1
2709 #define        MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1
2710 #define        MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 2
2711 #define        MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1
2712 #define        MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_LBN 3
2713 #define        MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 1
2714 /* 1 to set new state, or 0 to just report the existing state */
2715 #define       MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
2716 #define       MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
2717 /* preferred datapath firmware (for Huntington; ignored for Siena) */
2718 #define       MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8
2719 #define       MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4
2720 /* enum: Prefer to use full featured firmware */
2721 #define          MC_CMD_FW_FULL_FEATURED 0x0
2722 /* enum: Prefer to use firmware with fewer features but lower latency */
2723 #define          MC_CMD_FW_LOW_LATENCY 0x1
2724 /* enum: Prefer to use firmware for SolarCapture packed stream mode */
2725 #define          MC_CMD_FW_PACKED_STREAM 0x2
2726 /* enum: Prefer to use firmware with fewer features and simpler TX event
2727  * batching but higher TX packet rate
2728  */
2729 #define          MC_CMD_FW_HIGH_TX_RATE 0x3
2730 /* enum: Reserved value */
2731 #define          MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4
2732 /* enum: Prefer to use firmware with additional "rules engine" filtering
2733  * support
2734  */
2735 #define          MC_CMD_FW_RULES_ENGINE 0x5
2736 /* enum: Prefer to use firmware with additional DPDK support */
2737 #define          MC_CMD_FW_DPDK 0x6
2738 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
2739  * bug69716)
2740  */
2741 #define          MC_CMD_FW_L3XUDP 0x7
2742 /* enum: Only this option is allowed for non-admin functions */
2743 #define          MC_CMD_FW_DONT_CARE 0xffffffff
2744 
2745 /* MC_CMD_DRV_ATTACH_OUT msgresponse */
2746 #define    MC_CMD_DRV_ATTACH_OUT_LEN 4
2747 /* previous or existing state, see the bitmask at NEW_STATE */
2748 #define       MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
2749 #define       MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4
2750 
2751 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */
2752 #define    MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8
2753 /* previous or existing state, see the bitmask at NEW_STATE */
2754 #define       MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0
2755 #define       MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4
2756 /* Flags associated with this function */
2757 #define       MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4
2758 #define       MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4
2759 /* enum: Labels the lowest-numbered function visible to the OS */
2760 #define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0
2761 /* enum: The function can control the link state of the physical port it is
2762  * bound to.
2763  */
2764 #define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1
2765 /* enum: The function can perform privileged operations */
2766 #define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2
2767 /* enum: The function does not have an active port associated with it. The port
2768  * refers to the Sorrento external FPGA port.
2769  */
2770 #define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3
2771 /* enum: If set, indicates that VI spreading is currently enabled. Will always
2772  * indicate the current state, regardless of the value in the WANT_VI_SPREADING
2773  * input.
2774  */
2775 #define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4
2776 
2777 
2778 /***********************************/
2779 /* MC_CMD_SHMUART
2780  * Route UART output to circular buffer in shared memory instead.
2781  */
2782 #define MC_CMD_SHMUART 0x1f
2783 
2784 /* MC_CMD_SHMUART_IN msgrequest */
2785 #define    MC_CMD_SHMUART_IN_LEN 4
2786 /* ??? */
2787 #define       MC_CMD_SHMUART_IN_FLAG_OFST 0
2788 #define       MC_CMD_SHMUART_IN_FLAG_LEN 4
2789 
2790 /* MC_CMD_SHMUART_OUT msgresponse */
2791 #define    MC_CMD_SHMUART_OUT_LEN 0
2792 
2793 
2794 /***********************************/
2795 /* MC_CMD_PORT_RESET
2796  * Generic per-port reset. There is no equivalent for per-board reset. Locks
2797  * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
2798  * use MC_CMD_ENTITY_RESET instead.
2799  */
2800 #define MC_CMD_PORT_RESET 0x20
2801 
2802 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2803 
2804 /* MC_CMD_PORT_RESET_IN msgrequest */
2805 #define    MC_CMD_PORT_RESET_IN_LEN 0
2806 
2807 /* MC_CMD_PORT_RESET_OUT msgresponse */
2808 #define    MC_CMD_PORT_RESET_OUT_LEN 0
2809 
2810 
2811 /***********************************/
2812 /* MC_CMD_ENTITY_RESET
2813  * Generic per-resource reset. There is no equivalent for per-board reset.
2814  * Locks required: None; Return code: 0, ETIME. NOTE: This command is an
2815  * extended version of the deprecated MC_CMD_PORT_RESET with added fields.
2816  */
2817 #define MC_CMD_ENTITY_RESET 0x20
2818 /*      MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */
2819 
2820 /* MC_CMD_ENTITY_RESET_IN msgrequest */
2821 #define    MC_CMD_ENTITY_RESET_IN_LEN 4
2822 /* Optional flags field. Omitting this will perform a "legacy" reset action
2823  * (TBD).
2824  */
2825 #define       MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
2826 #define       MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4
2827 #define        MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
2828 #define        MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1
2829 
2830 /* MC_CMD_ENTITY_RESET_OUT msgresponse */
2831 #define    MC_CMD_ENTITY_RESET_OUT_LEN 0
2832 
2833 
2834 /***********************************/
2835 /* MC_CMD_PCIE_CREDITS
2836  * Read instantaneous and minimum flow control thresholds.
2837  */
2838 #define MC_CMD_PCIE_CREDITS 0x21
2839 
2840 /* MC_CMD_PCIE_CREDITS_IN msgrequest */
2841 #define    MC_CMD_PCIE_CREDITS_IN_LEN 8
2842 /* poll period. 0 is disabled */
2843 #define       MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0
2844 #define       MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4
2845 /* wipe statistics */
2846 #define       MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4
2847 #define       MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4
2848 
2849 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */
2850 #define    MC_CMD_PCIE_CREDITS_OUT_LEN 16
2851 #define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0
2852 #define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2
2853 #define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2
2854 #define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2
2855 #define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4
2856 #define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2
2857 #define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6
2858 #define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2
2859 #define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8
2860 #define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2
2861 #define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10
2862 #define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2
2863 #define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12
2864 #define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2
2865 #define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14
2866 #define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2
2867 
2868 
2869 /***********************************/
2870 /* MC_CMD_RXD_MONITOR
2871  * Get histogram of RX queue fill level.
2872  */
2873 #define MC_CMD_RXD_MONITOR 0x22
2874 
2875 /* MC_CMD_RXD_MONITOR_IN msgrequest */
2876 #define    MC_CMD_RXD_MONITOR_IN_LEN 12
2877 #define       MC_CMD_RXD_MONITOR_IN_QID_OFST 0
2878 #define       MC_CMD_RXD_MONITOR_IN_QID_LEN 4
2879 #define       MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4
2880 #define       MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4
2881 #define       MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8
2882 #define       MC_CMD_RXD_MONITOR_IN_WIPE_LEN 4
2883 
2884 /* MC_CMD_RXD_MONITOR_OUT msgresponse */
2885 #define    MC_CMD_RXD_MONITOR_OUT_LEN 80
2886 #define       MC_CMD_RXD_MONITOR_OUT_QID_OFST 0
2887 #define       MC_CMD_RXD_MONITOR_OUT_QID_LEN 4
2888 #define       MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4
2889 #define       MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4
2890 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8
2891 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4
2892 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12
2893 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4
2894 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16
2895 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4
2896 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20
2897 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4
2898 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24
2899 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4
2900 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28
2901 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4
2902 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32
2903 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4
2904 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36
2905 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4
2906 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40
2907 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4
2908 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44
2909 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4
2910 #define       MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48
2911 #define       MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4
2912 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52
2913 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4
2914 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56
2915 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4
2916 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60
2917 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4
2918 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64
2919 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4
2920 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68
2921 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4
2922 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72
2923 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4
2924 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76
2925 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4
2926 
2927 
2928 /***********************************/
2929 /* MC_CMD_PUTS
2930  * Copy the given ASCII string out onto UART and/or out of the network port.
2931  */
2932 #define MC_CMD_PUTS 0x23
2933 
2934 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2935 
2936 /* MC_CMD_PUTS_IN msgrequest */
2937 #define    MC_CMD_PUTS_IN_LENMIN 13
2938 #define    MC_CMD_PUTS_IN_LENMAX 252
2939 #define    MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
2940 #define       MC_CMD_PUTS_IN_DEST_OFST 0
2941 #define       MC_CMD_PUTS_IN_DEST_LEN 4
2942 #define        MC_CMD_PUTS_IN_UART_LBN 0
2943 #define        MC_CMD_PUTS_IN_UART_WIDTH 1
2944 #define        MC_CMD_PUTS_IN_PORT_LBN 1
2945 #define        MC_CMD_PUTS_IN_PORT_WIDTH 1
2946 #define       MC_CMD_PUTS_IN_DHOST_OFST 4
2947 #define       MC_CMD_PUTS_IN_DHOST_LEN 6
2948 #define       MC_CMD_PUTS_IN_STRING_OFST 12
2949 #define       MC_CMD_PUTS_IN_STRING_LEN 1
2950 #define       MC_CMD_PUTS_IN_STRING_MINNUM 1
2951 #define       MC_CMD_PUTS_IN_STRING_MAXNUM 240
2952 
2953 /* MC_CMD_PUTS_OUT msgresponse */
2954 #define    MC_CMD_PUTS_OUT_LEN 0
2955 
2956 
2957 /***********************************/
2958 /* MC_CMD_GET_PHY_CFG
2959  * Report PHY configuration. This guarantees to succeed even if the PHY is in a
2960  * 'zombie' state. Locks required: None
2961  */
2962 #define MC_CMD_GET_PHY_CFG 0x24
2963 
2964 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2965 
2966 /* MC_CMD_GET_PHY_CFG_IN msgrequest */
2967 #define    MC_CMD_GET_PHY_CFG_IN_LEN 0
2968 
2969 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */
2970 #define    MC_CMD_GET_PHY_CFG_OUT_LEN 72
2971 /* flags */
2972 #define       MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
2973 #define       MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4
2974 #define        MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
2975 #define        MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
2976 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
2977 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
2978 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2
2979 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
2980 #define        MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3
2981 #define        MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
2982 #define        MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
2983 #define        MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
2984 #define        MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5
2985 #define        MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
2986 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6
2987 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
2988 /* ?? */
2989 #define       MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
2990 #define       MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4
2991 /* Bitmask of supported capabilities */
2992 #define       MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8
2993 #define       MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4
2994 #define        MC_CMD_PHY_CAP_10HDX_LBN 1
2995 #define        MC_CMD_PHY_CAP_10HDX_WIDTH 1
2996 #define        MC_CMD_PHY_CAP_10FDX_LBN 2
2997 #define        MC_CMD_PHY_CAP_10FDX_WIDTH 1
2998 #define        MC_CMD_PHY_CAP_100HDX_LBN 3
2999 #define        MC_CMD_PHY_CAP_100HDX_WIDTH 1
3000 #define        MC_CMD_PHY_CAP_100FDX_LBN 4
3001 #define        MC_CMD_PHY_CAP_100FDX_WIDTH 1
3002 #define        MC_CMD_PHY_CAP_1000HDX_LBN 5
3003 #define        MC_CMD_PHY_CAP_1000HDX_WIDTH 1
3004 #define        MC_CMD_PHY_CAP_1000FDX_LBN 6
3005 #define        MC_CMD_PHY_CAP_1000FDX_WIDTH 1
3006 #define        MC_CMD_PHY_CAP_10000FDX_LBN 7
3007 #define        MC_CMD_PHY_CAP_10000FDX_WIDTH 1
3008 #define        MC_CMD_PHY_CAP_PAUSE_LBN 8
3009 #define        MC_CMD_PHY_CAP_PAUSE_WIDTH 1
3010 #define        MC_CMD_PHY_CAP_ASYM_LBN 9
3011 #define        MC_CMD_PHY_CAP_ASYM_WIDTH 1
3012 #define        MC_CMD_PHY_CAP_AN_LBN 10
3013 #define        MC_CMD_PHY_CAP_AN_WIDTH 1
3014 #define        MC_CMD_PHY_CAP_40000FDX_LBN 11
3015 #define        MC_CMD_PHY_CAP_40000FDX_WIDTH 1
3016 #define        MC_CMD_PHY_CAP_DDM_LBN 12
3017 #define        MC_CMD_PHY_CAP_DDM_WIDTH 1
3018 #define        MC_CMD_PHY_CAP_100000FDX_LBN 13
3019 #define        MC_CMD_PHY_CAP_100000FDX_WIDTH 1
3020 #define        MC_CMD_PHY_CAP_25000FDX_LBN 14
3021 #define        MC_CMD_PHY_CAP_25000FDX_WIDTH 1
3022 #define        MC_CMD_PHY_CAP_50000FDX_LBN 15
3023 #define        MC_CMD_PHY_CAP_50000FDX_WIDTH 1
3024 #define        MC_CMD_PHY_CAP_BASER_FEC_LBN 16
3025 #define        MC_CMD_PHY_CAP_BASER_FEC_WIDTH 1
3026 #define        MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 17
3027 #define        MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1
3028 #define        MC_CMD_PHY_CAP_RS_FEC_LBN 18
3029 #define        MC_CMD_PHY_CAP_RS_FEC_WIDTH 1
3030 #define        MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 19
3031 #define        MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1
3032 #define        MC_CMD_PHY_CAP_25G_BASER_FEC_LBN 20
3033 #define        MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1
3034 #define        MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 21
3035 #define        MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1
3036 /* ?? */
3037 #define       MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12
3038 #define       MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4
3039 /* ?? */
3040 #define       MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16
3041 #define       MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4
3042 /* ?? */
3043 #define       MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20
3044 #define       MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4
3045 /* ?? */
3046 #define       MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24
3047 #define       MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20
3048 /* ?? */
3049 #define       MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44
3050 #define       MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4
3051 /* enum: Xaui. */
3052 #define          MC_CMD_MEDIA_XAUI 0x1
3053 /* enum: CX4. */
3054 #define          MC_CMD_MEDIA_CX4 0x2
3055 /* enum: KX4. */
3056 #define          MC_CMD_MEDIA_KX4 0x3
3057 /* enum: XFP Far. */
3058 #define          MC_CMD_MEDIA_XFP 0x4
3059 /* enum: SFP+. */
3060 #define          MC_CMD_MEDIA_SFP_PLUS 0x5
3061 /* enum: 10GBaseT. */
3062 #define          MC_CMD_MEDIA_BASE_T 0x6
3063 /* enum: QSFP+. */
3064 #define          MC_CMD_MEDIA_QSFP_PLUS 0x7
3065 #define       MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48
3066 #define       MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4
3067 /* enum: Native clause 22 */
3068 #define          MC_CMD_MMD_CLAUSE22 0x0
3069 #define          MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
3070 #define          MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
3071 #define          MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
3072 #define          MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
3073 #define          MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
3074 #define          MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
3075 #define          MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
3076 /* enum: Clause22 proxied over clause45 by PHY. */
3077 #define          MC_CMD_MMD_CLAUSE45_C22EXT 0x1d
3078 #define          MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
3079 #define          MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
3080 #define       MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52
3081 #define       MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20
3082 
3083 
3084 /***********************************/
3085 /* MC_CMD_START_BIST
3086  * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST
3087  * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
3088  */
3089 #define MC_CMD_START_BIST 0x25
3090 
3091 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3092 
3093 /* MC_CMD_START_BIST_IN msgrequest */
3094 #define    MC_CMD_START_BIST_IN_LEN 4
3095 /* Type of test. */
3096 #define       MC_CMD_START_BIST_IN_TYPE_OFST 0
3097 #define       MC_CMD_START_BIST_IN_TYPE_LEN 4
3098 /* enum: Run the PHY's short cable BIST. */
3099 #define          MC_CMD_PHY_BIST_CABLE_SHORT 0x1
3100 /* enum: Run the PHY's long cable BIST. */
3101 #define          MC_CMD_PHY_BIST_CABLE_LONG 0x2
3102 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */
3103 #define          MC_CMD_BPX_SERDES_BIST 0x3
3104 /* enum: Run the MC loopback tests. */
3105 #define          MC_CMD_MC_LOOPBACK_BIST 0x4
3106 /* enum: Run the PHY's standard BIST. */
3107 #define          MC_CMD_PHY_BIST 0x5
3108 /* enum: Run MC RAM test. */
3109 #define          MC_CMD_MC_MEM_BIST 0x6
3110 /* enum: Run Port RAM test. */
3111 #define          MC_CMD_PORT_MEM_BIST 0x7
3112 /* enum: Run register test. */
3113 #define          MC_CMD_REG_BIST 0x8
3114 
3115 /* MC_CMD_START_BIST_OUT msgresponse */
3116 #define    MC_CMD_START_BIST_OUT_LEN 0
3117 
3118 
3119 /***********************************/
3120 /* MC_CMD_POLL_BIST
3121  * Poll for BIST completion. Returns a single status code, and optionally some
3122  * PHY specific bist output. The driver should only consume the BIST output
3123  * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't
3124  * successfully parse the BIST output, it should still respect the pass/Fail in
3125  * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,
3126  * EACCES (if PHY_LOCK is not held).
3127  */
3128 #define MC_CMD_POLL_BIST 0x26
3129 
3130 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3131 
3132 /* MC_CMD_POLL_BIST_IN msgrequest */
3133 #define    MC_CMD_POLL_BIST_IN_LEN 0
3134 
3135 /* MC_CMD_POLL_BIST_OUT msgresponse */
3136 #define    MC_CMD_POLL_BIST_OUT_LEN 8
3137 /* result */
3138 #define       MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
3139 #define       MC_CMD_POLL_BIST_OUT_RESULT_LEN 4
3140 /* enum: Running. */
3141 #define          MC_CMD_POLL_BIST_RUNNING 0x1
3142 /* enum: Passed. */
3143 #define          MC_CMD_POLL_BIST_PASSED 0x2
3144 /* enum: Failed. */
3145 #define          MC_CMD_POLL_BIST_FAILED 0x3
3146 /* enum: Timed-out. */
3147 #define          MC_CMD_POLL_BIST_TIMEOUT 0x4
3148 #define       MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
3149 #define       MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4
3150 
3151 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */
3152 #define    MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36
3153 /* result */
3154 /*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3155 /*            MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3156 /*            Enum values, see field(s): */
3157 /*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
3158 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
3159 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4
3160 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8
3161 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4
3162 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12
3163 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4
3164 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16
3165 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4
3166 /* Status of each channel A */
3167 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20
3168 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4
3169 /* enum: Ok. */
3170 #define          MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1
3171 /* enum: Open. */
3172 #define          MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2
3173 /* enum: Intra-pair short. */
3174 #define          MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3
3175 /* enum: Inter-pair short. */
3176 #define          MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4
3177 /* enum: Busy. */
3178 #define          MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9
3179 /* Status of each channel B */
3180 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24
3181 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4
3182 /*            Enum values, see field(s): */
3183 /*               CABLE_STATUS_A */
3184 /* Status of each channel C */
3185 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28
3186 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4
3187 /*            Enum values, see field(s): */
3188 /*               CABLE_STATUS_A */
3189 /* Status of each channel D */
3190 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32
3191 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4
3192 /*            Enum values, see field(s): */
3193 /*               CABLE_STATUS_A */
3194 
3195 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */
3196 #define    MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8
3197 /* result */
3198 /*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3199 /*            MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3200 /*            Enum values, see field(s): */
3201 /*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
3202 #define       MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
3203 #define       MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4
3204 /* enum: Complete. */
3205 #define          MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0
3206 /* enum: Bus switch off I2C write. */
3207 #define          MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1
3208 /* enum: Bus switch off I2C no access IO exp. */
3209 #define          MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2
3210 /* enum: Bus switch off I2C no access module. */
3211 #define          MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3
3212 /* enum: IO exp I2C configure. */
3213 #define          MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4
3214 /* enum: Bus switch I2C no cross talk. */
3215 #define          MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5
3216 /* enum: Module presence. */
3217 #define          MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6
3218 /* enum: Module ID I2C access. */
3219 #define          MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7
3220 /* enum: Module ID sane value. */
3221 #define          MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8
3222 
3223 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */
3224 #define    MC_CMD_POLL_BIST_OUT_MEM_LEN 36
3225 /* result */
3226 /*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3227 /*            MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3228 /*            Enum values, see field(s): */
3229 /*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
3230 #define       MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4
3231 #define       MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4
3232 /* enum: Test has completed. */
3233 #define          MC_CMD_POLL_BIST_MEM_COMPLETE 0x0
3234 /* enum: RAM test - walk ones. */
3235 #define          MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1
3236 /* enum: RAM test - walk zeros. */
3237 #define          MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2
3238 /* enum: RAM test - walking inversions zeros/ones. */
3239 #define          MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3
3240 /* enum: RAM test - walking inversions checkerboard. */
3241 #define          MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4
3242 /* enum: Register test - set / clear individual bits. */
3243 #define          MC_CMD_POLL_BIST_MEM_REG 0x5
3244 /* enum: ECC error detected. */
3245 #define          MC_CMD_POLL_BIST_MEM_ECC 0x6
3246 /* Failure address, only valid if result is POLL_BIST_FAILED */
3247 #define       MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8
3248 #define       MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4
3249 /* Bus or address space to which the failure address corresponds */
3250 #define       MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12
3251 #define       MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4
3252 /* enum: MC MIPS bus. */
3253 #define          MC_CMD_POLL_BIST_MEM_BUS_MC 0x0
3254 /* enum: CSR IREG bus. */
3255 #define          MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1
3256 /* enum: RX0 DPCPU bus. */
3257 #define          MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2
3258 /* enum: TX0 DPCPU bus. */
3259 #define          MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3
3260 /* enum: TX1 DPCPU bus. */
3261 #define          MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4
3262 /* enum: RX0 DICPU bus. */
3263 #define          MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5
3264 /* enum: TX DICPU bus. */
3265 #define          MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6
3266 /* enum: RX1 DPCPU bus. */
3267 #define          MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7
3268 /* enum: RX1 DICPU bus. */
3269 #define          MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8
3270 /* Pattern written to RAM / register */
3271 #define       MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16
3272 #define       MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4
3273 /* Actual value read from RAM / register */
3274 #define       MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20
3275 #define       MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4
3276 /* ECC error mask */
3277 #define       MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24
3278 #define       MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4
3279 /* ECC parity error mask */
3280 #define       MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28
3281 #define       MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4
3282 /* ECC fatal error mask */
3283 #define       MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32
3284 #define       MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4
3285 
3286 
3287 /***********************************/
3288 /* MC_CMD_FLUSH_RX_QUEUES
3289  * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ
3290  * flushes should be initiated via this MCDI operation, rather than via
3291  * directly writing FLUSH_CMD.
3292  *
3293  * The flush is completed (either done/fail) asynchronously (after this command
3294  * returns). The driver must still wait for flush done/failure events as usual.
3295  */
3296 #define MC_CMD_FLUSH_RX_QUEUES 0x27
3297 
3298 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */
3299 #define    MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
3300 #define    MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252
3301 #define    MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
3302 #define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
3303 #define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
3304 #define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1
3305 #define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63
3306 
3307 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */
3308 #define    MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0
3309 
3310 
3311 /***********************************/
3312 /* MC_CMD_GET_LOOPBACK_MODES
3313  * Returns a bitmask of loopback modes available at each speed.
3314  */
3315 #define MC_CMD_GET_LOOPBACK_MODES 0x28
3316 
3317 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3318 
3319 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */
3320 #define    MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
3321 
3322 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */
3323 #define    MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40
3324 /* Supported loopbacks. */
3325 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
3326 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8
3327 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
3328 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
3329 /* enum: None. */
3330 #define          MC_CMD_LOOPBACK_NONE 0x0
3331 /* enum: Data. */
3332 #define          MC_CMD_LOOPBACK_DATA 0x1
3333 /* enum: GMAC. */
3334 #define          MC_CMD_LOOPBACK_GMAC 0x2
3335 /* enum: XGMII. */
3336 #define          MC_CMD_LOOPBACK_XGMII 0x3
3337 /* enum: XGXS. */
3338 #define          MC_CMD_LOOPBACK_XGXS 0x4
3339 /* enum: XAUI. */
3340 #define          MC_CMD_LOOPBACK_XAUI 0x5
3341 /* enum: GMII. */
3342 #define          MC_CMD_LOOPBACK_GMII 0x6
3343 /* enum: SGMII. */
3344 #define          MC_CMD_LOOPBACK_SGMII 0x7
3345 /* enum: XGBR. */
3346 #define          MC_CMD_LOOPBACK_XGBR 0x8
3347 /* enum: XFI. */
3348 #define          MC_CMD_LOOPBACK_XFI 0x9
3349 /* enum: XAUI Far. */
3350 #define          MC_CMD_LOOPBACK_XAUI_FAR 0xa
3351 /* enum: GMII Far. */
3352 #define          MC_CMD_LOOPBACK_GMII_FAR 0xb
3353 /* enum: SGMII Far. */
3354 #define          MC_CMD_LOOPBACK_SGMII_FAR 0xc
3355 /* enum: XFI Far. */
3356 #define          MC_CMD_LOOPBACK_XFI_FAR 0xd
3357 /* enum: GPhy. */
3358 #define          MC_CMD_LOOPBACK_GPHY 0xe
3359 /* enum: PhyXS. */
3360 #define          MC_CMD_LOOPBACK_PHYXS 0xf
3361 /* enum: PCS. */
3362 #define          MC_CMD_LOOPBACK_PCS 0x10
3363 /* enum: PMA-PMD. */
3364 #define          MC_CMD_LOOPBACK_PMAPMD 0x11
3365 /* enum: Cross-Port. */
3366 #define          MC_CMD_LOOPBACK_XPORT 0x12
3367 /* enum: XGMII-Wireside. */
3368 #define          MC_CMD_LOOPBACK_XGMII_WS 0x13
3369 /* enum: XAUI Wireside. */
3370 #define          MC_CMD_LOOPBACK_XAUI_WS 0x14
3371 /* enum: XAUI Wireside Far. */
3372 #define          MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
3373 /* enum: XAUI Wireside near. */
3374 #define          MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
3375 /* enum: GMII Wireside. */
3376 #define          MC_CMD_LOOPBACK_GMII_WS 0x17
3377 /* enum: XFI Wireside. */
3378 #define          MC_CMD_LOOPBACK_XFI_WS 0x18
3379 /* enum: XFI Wireside Far. */
3380 #define          MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
3381 /* enum: PhyXS Wireside. */
3382 #define          MC_CMD_LOOPBACK_PHYXS_WS 0x1a
3383 /* enum: PMA lanes MAC-Serdes. */
3384 #define          MC_CMD_LOOPBACK_PMA_INT 0x1b
3385 /* enum: KR Serdes Parallel (Encoder). */
3386 #define          MC_CMD_LOOPBACK_SD_NEAR 0x1c
3387 /* enum: KR Serdes Serial. */
3388 #define          MC_CMD_LOOPBACK_SD_FAR 0x1d
3389 /* enum: PMA lanes MAC-Serdes Wireside. */
3390 #define          MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
3391 /* enum: KR Serdes Parallel Wireside (Full PCS). */
3392 #define          MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
3393 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
3394 #define          MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
3395 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
3396 #define          MC_CMD_LOOPBACK_SD_FEP_WS 0x21
3397 /* enum: KR Serdes Serial Wireside. */
3398 #define          MC_CMD_LOOPBACK_SD_FES_WS 0x22
3399 /* enum: Near side of AOE Siena side port */
3400 #define          MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
3401 /* enum: Medford Wireside datapath loopback */
3402 #define          MC_CMD_LOOPBACK_DATA_WS 0x24
3403 /* enum: Force link up without setting up any physical loopback (snapper use
3404  * only)
3405  */
3406 #define          MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25
3407 /* Supported loopbacks. */
3408 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
3409 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
3410 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8
3411 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12
3412 /*            Enum values, see field(s): */
3413 /*               100M */
3414 /* Supported loopbacks. */
3415 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16
3416 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8
3417 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16
3418 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20
3419 /*            Enum values, see field(s): */
3420 /*               100M */
3421 /* Supported loopbacks. */
3422 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24
3423 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8
3424 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24
3425 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28
3426 /*            Enum values, see field(s): */
3427 /*               100M */
3428 /* Supported loopbacks. */
3429 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32
3430 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8
3431 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32
3432 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36
3433 /*            Enum values, see field(s): */
3434 /*               100M */
3435 
3436 /* MC_CMD_GET_LOOPBACK_MODES_OUT_V2 msgresponse: Supported loopback modes for
3437  * newer NICs with 25G/50G/100G support
3438  */
3439 #define    MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN 64
3440 /* Supported loopbacks. */
3441 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0
3442 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8
3443 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
3444 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
3445 /* enum: None. */
3446 /*               MC_CMD_LOOPBACK_NONE 0x0 */
3447 /* enum: Data. */
3448 /*               MC_CMD_LOOPBACK_DATA 0x1 */
3449 /* enum: GMAC. */
3450 /*               MC_CMD_LOOPBACK_GMAC 0x2 */
3451 /* enum: XGMII. */
3452 /*               MC_CMD_LOOPBACK_XGMII 0x3 */
3453 /* enum: XGXS. */
3454 /*               MC_CMD_LOOPBACK_XGXS 0x4 */
3455 /* enum: XAUI. */
3456 /*               MC_CMD_LOOPBACK_XAUI 0x5 */
3457 /* enum: GMII. */
3458 /*               MC_CMD_LOOPBACK_GMII 0x6 */
3459 /* enum: SGMII. */
3460 /*               MC_CMD_LOOPBACK_SGMII 0x7 */
3461 /* enum: XGBR. */
3462 /*               MC_CMD_LOOPBACK_XGBR 0x8 */
3463 /* enum: XFI. */
3464 /*               MC_CMD_LOOPBACK_XFI 0x9 */
3465 /* enum: XAUI Far. */
3466 /*               MC_CMD_LOOPBACK_XAUI_FAR 0xa */
3467 /* enum: GMII Far. */
3468 /*               MC_CMD_LOOPBACK_GMII_FAR 0xb */
3469 /* enum: SGMII Far. */
3470 /*               MC_CMD_LOOPBACK_SGMII_FAR 0xc */
3471 /* enum: XFI Far. */
3472 /*               MC_CMD_LOOPBACK_XFI_FAR 0xd */
3473 /* enum: GPhy. */
3474 /*               MC_CMD_LOOPBACK_GPHY 0xe */
3475 /* enum: PhyXS. */
3476 /*               MC_CMD_LOOPBACK_PHYXS 0xf */
3477 /* enum: PCS. */
3478 /*               MC_CMD_LOOPBACK_PCS 0x10 */
3479 /* enum: PMA-PMD. */
3480 /*               MC_CMD_LOOPBACK_PMAPMD 0x11 */
3481 /* enum: Cross-Port. */
3482 /*               MC_CMD_LOOPBACK_XPORT 0x12 */
3483 /* enum: XGMII-Wireside. */
3484 /*               MC_CMD_LOOPBACK_XGMII_WS 0x13 */
3485 /* enum: XAUI Wireside. */
3486 /*               MC_CMD_LOOPBACK_XAUI_WS 0x14 */
3487 /* enum: XAUI Wireside Far. */
3488 /*               MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
3489 /* enum: XAUI Wireside near. */
3490 /*               MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
3491 /* enum: GMII Wireside. */
3492 /*               MC_CMD_LOOPBACK_GMII_WS 0x17 */
3493 /* enum: XFI Wireside. */
3494 /*               MC_CMD_LOOPBACK_XFI_WS 0x18 */
3495 /* enum: XFI Wireside Far. */
3496 /*               MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
3497 /* enum: PhyXS Wireside. */
3498 /*               MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
3499 /* enum: PMA lanes MAC-Serdes. */
3500 /*               MC_CMD_LOOPBACK_PMA_INT 0x1b */
3501 /* enum: KR Serdes Parallel (Encoder). */
3502 /*               MC_CMD_LOOPBACK_SD_NEAR 0x1c */
3503 /* enum: KR Serdes Serial. */
3504 /*               MC_CMD_LOOPBACK_SD_FAR 0x1d */
3505 /* enum: PMA lanes MAC-Serdes Wireside. */
3506 /*               MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
3507 /* enum: KR Serdes Parallel Wireside (Full PCS). */
3508 /*               MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
3509 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
3510 /*               MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
3511 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
3512 /*               MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
3513 /* enum: KR Serdes Serial Wireside. */
3514 /*               MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
3515 /* enum: Near side of AOE Siena side port */
3516 /*               MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
3517 /* enum: Medford Wireside datapath loopback */
3518 /*               MC_CMD_LOOPBACK_DATA_WS 0x24 */
3519 /* enum: Force link up without setting up any physical loopback (snapper use
3520  * only)
3521  */
3522 /*               MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
3523 /* Supported loopbacks. */
3524 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8
3525 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8
3526 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8
3527 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12
3528 /*            Enum values, see field(s): */
3529 /*               100M */
3530 /* Supported loopbacks. */
3531 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16
3532 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8
3533 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16
3534 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20
3535 /*            Enum values, see field(s): */
3536 /*               100M */
3537 /* Supported loopbacks. */
3538 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24
3539 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8
3540 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24
3541 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28
3542 /*            Enum values, see field(s): */
3543 /*               100M */
3544 /* Supported loopbacks. */
3545 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32
3546 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8
3547 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32
3548 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36
3549 /*            Enum values, see field(s): */
3550 /*               100M */
3551 /* Supported 25G loopbacks. */
3552 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40
3553 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8
3554 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40
3555 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44
3556 /*            Enum values, see field(s): */
3557 /*               100M */
3558 /* Supported 50 loopbacks. */
3559 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48
3560 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8
3561 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48
3562 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52
3563 /*            Enum values, see field(s): */
3564 /*               100M */
3565 /* Supported 100G loopbacks. */
3566 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56
3567 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8
3568 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56
3569 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60
3570 /*            Enum values, see field(s): */
3571 /*               100M */
3572 
3573 /* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */
3574 #define    AN_TYPE_LEN 4
3575 #define       AN_TYPE_TYPE_OFST 0
3576 #define       AN_TYPE_TYPE_LEN 4
3577 /* enum: None, AN disabled or not supported */
3578 #define          MC_CMD_AN_NONE 0x0
3579 /* enum: Clause 28 - BASE-T */
3580 #define          MC_CMD_AN_CLAUSE28 0x1
3581 /* enum: Clause 37 - BASE-X */
3582 #define          MC_CMD_AN_CLAUSE37 0x2
3583 /* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable
3584  * assemblies. Includes Clause 72/Clause 92 link-training.
3585  */
3586 #define          MC_CMD_AN_CLAUSE73 0x3
3587 #define       AN_TYPE_TYPE_LBN 0
3588 #define       AN_TYPE_TYPE_WIDTH 32
3589 
3590 /* FEC_TYPE structuredef: Forward error correction types defined in IEEE802.3
3591  */
3592 #define    FEC_TYPE_LEN 4
3593 #define       FEC_TYPE_TYPE_OFST 0
3594 #define       FEC_TYPE_TYPE_LEN 4
3595 /* enum: No FEC */
3596 #define          MC_CMD_FEC_NONE 0x0
3597 /* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */
3598 #define          MC_CMD_FEC_BASER 0x1
3599 /* enum: Clause 91/Clause 108 Reed-Solomon FEC */
3600 #define          MC_CMD_FEC_RS 0x2
3601 #define       FEC_TYPE_TYPE_LBN 0
3602 #define       FEC_TYPE_TYPE_WIDTH 32
3603 
3604 
3605 /***********************************/
3606 /* MC_CMD_GET_LINK
3607  * Read the unified MAC/PHY link state. Locks required: None Return code: 0,
3608  * ETIME.
3609  */
3610 #define MC_CMD_GET_LINK 0x29
3611 
3612 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3613 
3614 /* MC_CMD_GET_LINK_IN msgrequest */
3615 #define    MC_CMD_GET_LINK_IN_LEN 0
3616 
3617 /* MC_CMD_GET_LINK_OUT msgresponse */
3618 #define    MC_CMD_GET_LINK_OUT_LEN 28
3619 /* Near-side advertised capabilities. Refer to
3620  * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
3621  */
3622 #define       MC_CMD_GET_LINK_OUT_CAP_OFST 0
3623 #define       MC_CMD_GET_LINK_OUT_CAP_LEN 4
3624 /* Link-partner advertised capabilities. Refer to
3625  * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
3626  */
3627 #define       MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
3628 #define       MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4
3629 /* Autonegotiated speed in mbit/s. The link may still be down even if this
3630  * reads non-zero.
3631  */
3632 #define       MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8
3633 #define       MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4
3634 /* Current loopback setting. */
3635 #define       MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12
3636 #define       MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4
3637 /*            Enum values, see field(s): */
3638 /*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
3639 #define       MC_CMD_GET_LINK_OUT_FLAGS_OFST 16
3640 #define       MC_CMD_GET_LINK_OUT_FLAGS_LEN 4
3641 #define        MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
3642 #define        MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
3643 #define        MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
3644 #define        MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
3645 #define        MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2
3646 #define        MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
3647 #define        MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3
3648 #define        MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
3649 #define        MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6
3650 #define        MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1
3651 #define        MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7
3652 #define        MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1
3653 /* This returns the negotiated flow control value. */
3654 #define       MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
3655 #define       MC_CMD_GET_LINK_OUT_FCNTL_LEN 4
3656 /*            Enum values, see field(s): */
3657 /*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
3658 #define       MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
3659 #define       MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4
3660 #define        MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
3661 #define        MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
3662 #define        MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
3663 #define        MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
3664 #define        MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2
3665 #define        MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
3666 #define        MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3
3667 #define        MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
3668 
3669 /* MC_CMD_GET_LINK_OUT_V2 msgresponse: Extended link state information */
3670 #define    MC_CMD_GET_LINK_OUT_V2_LEN 44
3671 /* Near-side advertised capabilities. Refer to
3672  * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
3673  */
3674 #define       MC_CMD_GET_LINK_OUT_V2_CAP_OFST 0
3675 #define       MC_CMD_GET_LINK_OUT_V2_CAP_LEN 4
3676 /* Link-partner advertised capabilities. Refer to
3677  * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
3678  */
3679 #define       MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 4
3680 #define       MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 4
3681 /* Autonegotiated speed in mbit/s. The link may still be down even if this
3682  * reads non-zero.
3683  */
3684 #define       MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_OFST 8
3685 #define       MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 4
3686 /* Current loopback setting. */
3687 #define       MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_OFST 12
3688 #define       MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 4
3689 /*            Enum values, see field(s): */
3690 /*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
3691 #define       MC_CMD_GET_LINK_OUT_V2_FLAGS_OFST 16
3692 #define       MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4
3693 #define        MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0
3694 #define        MC_CMD_GET_LINK_OUT_V2_LINK_UP_WIDTH 1
3695 #define        MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_LBN 1
3696 #define        MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_WIDTH 1
3697 #define        MC_CMD_GET_LINK_OUT_V2_BPX_LINK_LBN 2
3698 #define        MC_CMD_GET_LINK_OUT_V2_BPX_LINK_WIDTH 1
3699 #define        MC_CMD_GET_LINK_OUT_V2_PHY_LINK_LBN 3
3700 #define        MC_CMD_GET_LINK_OUT_V2_PHY_LINK_WIDTH 1
3701 #define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_LBN 6
3702 #define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_WIDTH 1
3703 #define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_LBN 7
3704 #define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_WIDTH 1
3705 /* This returns the negotiated flow control value. */
3706 #define       MC_CMD_GET_LINK_OUT_V2_FCNTL_OFST 20
3707 #define       MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4
3708 /*            Enum values, see field(s): */
3709 /*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
3710 #define       MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 24
3711 #define       MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4
3712 /*             MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */
3713 /*             MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 */
3714 /*             MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 */
3715 /*             MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 */
3716 /*             MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 */
3717 /*             MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 */
3718 /*             MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 */
3719 /*             MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 */
3720 /* True local device capabilities (taking into account currently used PMD/MDI,
3721  * e.g. plugged-in module). In general, subset of
3722  * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP, but may include extra _FEC_REQUEST
3723  * bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal
3724  * to SUPPORTED_CAP for non-pluggable PMDs. Refer to
3725  * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
3726  */
3727 #define       MC_CMD_GET_LINK_OUT_V2_LD_CAP_OFST 28
3728 #define       MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 4
3729 /* Auto-negotiation type used on the link */
3730 #define       MC_CMD_GET_LINK_OUT_V2_AN_TYPE_OFST 32
3731 #define       MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 4
3732 /*            Enum values, see field(s): */
3733 /*               AN_TYPE/TYPE */
3734 /* Forward error correction used on the link */
3735 #define       MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_OFST 36
3736 #define       MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 4
3737 /*            Enum values, see field(s): */
3738 /*               FEC_TYPE/TYPE */
3739 #define       MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_OFST 40
3740 #define       MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4
3741 #define        MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0
3742 #define        MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_WIDTH 1
3743 #define        MC_CMD_GET_LINK_OUT_V2_PMD_READY_LBN 1
3744 #define        MC_CMD_GET_LINK_OUT_V2_PMD_READY_WIDTH 1
3745 #define        MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_LBN 2
3746 #define        MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_WIDTH 1
3747 #define        MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_LBN 3
3748 #define        MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_WIDTH 1
3749 #define        MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4
3750 #define        MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_WIDTH 1
3751 #define        MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_LBN 5
3752 #define        MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_WIDTH 1
3753 #define        MC_CMD_GET_LINK_OUT_V2_HI_BER_LBN 6
3754 #define        MC_CMD_GET_LINK_OUT_V2_HI_BER_WIDTH 1
3755 #define        MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_LBN 7
3756 #define        MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_WIDTH 1
3757 #define        MC_CMD_GET_LINK_OUT_V2_AN_DONE_LBN 8
3758 #define        MC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 1
3759 
3760 
3761 /***********************************/
3762 /* MC_CMD_SET_LINK
3763  * Write the unified MAC/PHY link configuration. Locks required: None. Return
3764  * code: 0, EINVAL, ETIME
3765  */
3766 #define MC_CMD_SET_LINK 0x2a
3767 
3768 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK
3769 
3770 /* MC_CMD_SET_LINK_IN msgrequest */
3771 #define    MC_CMD_SET_LINK_IN_LEN 16
3772 /* Near-side advertised capabilities. Refer to
3773  * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
3774  */
3775 #define       MC_CMD_SET_LINK_IN_CAP_OFST 0
3776 #define       MC_CMD_SET_LINK_IN_CAP_LEN 4
3777 /* Flags */
3778 #define       MC_CMD_SET_LINK_IN_FLAGS_OFST 4
3779 #define       MC_CMD_SET_LINK_IN_FLAGS_LEN 4
3780 #define        MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
3781 #define        MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1
3782 #define        MC_CMD_SET_LINK_IN_POWEROFF_LBN 1
3783 #define        MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1
3784 #define        MC_CMD_SET_LINK_IN_TXDIS_LBN 2
3785 #define        MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1
3786 /* Loopback mode. */
3787 #define       MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8
3788 #define       MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4
3789 /*            Enum values, see field(s): */
3790 /*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
3791 /* A loopback speed of "0" is supported, and means (choose any available
3792  * speed).
3793  */
3794 #define       MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12
3795 #define       MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4
3796 
3797 /* MC_CMD_SET_LINK_OUT msgresponse */
3798 #define    MC_CMD_SET_LINK_OUT_LEN 0
3799 
3800 
3801 /***********************************/
3802 /* MC_CMD_SET_ID_LED
3803  * Set identification LED state. Locks required: None. Return code: 0, EINVAL
3804  */
3805 #define MC_CMD_SET_ID_LED 0x2b
3806 
3807 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK
3808 
3809 /* MC_CMD_SET_ID_LED_IN msgrequest */
3810 #define    MC_CMD_SET_ID_LED_IN_LEN 4
3811 /* Set LED state. */
3812 #define       MC_CMD_SET_ID_LED_IN_STATE_OFST 0
3813 #define       MC_CMD_SET_ID_LED_IN_STATE_LEN 4
3814 #define          MC_CMD_LED_OFF 0x0 /* enum */
3815 #define          MC_CMD_LED_ON 0x1 /* enum */
3816 #define          MC_CMD_LED_DEFAULT 0x2 /* enum */
3817 
3818 /* MC_CMD_SET_ID_LED_OUT msgresponse */
3819 #define    MC_CMD_SET_ID_LED_OUT_LEN 0
3820 
3821 
3822 /***********************************/
3823 /* MC_CMD_SET_MAC
3824  * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
3825  */
3826 #define MC_CMD_SET_MAC 0x2c
3827 
3828 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3829 
3830 /* MC_CMD_SET_MAC_IN msgrequest */
3831 #define    MC_CMD_SET_MAC_IN_LEN 28
3832 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
3833  * EtherII, VLAN, bug16011 padding).
3834  */
3835 #define       MC_CMD_SET_MAC_IN_MTU_OFST 0
3836 #define       MC_CMD_SET_MAC_IN_MTU_LEN 4
3837 #define       MC_CMD_SET_MAC_IN_DRAIN_OFST 4
3838 #define       MC_CMD_SET_MAC_IN_DRAIN_LEN 4
3839 #define       MC_CMD_SET_MAC_IN_ADDR_OFST 8
3840 #define       MC_CMD_SET_MAC_IN_ADDR_LEN 8
3841 #define       MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
3842 #define       MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
3843 #define       MC_CMD_SET_MAC_IN_REJECT_OFST 16
3844 #define       MC_CMD_SET_MAC_IN_REJECT_LEN 4
3845 #define        MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
3846 #define        MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
3847 #define        MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
3848 #define        MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
3849 #define       MC_CMD_SET_MAC_IN_FCNTL_OFST 20
3850 #define       MC_CMD_SET_MAC_IN_FCNTL_LEN 4
3851 /* enum: Flow control is off. */
3852 #define          MC_CMD_FCNTL_OFF 0x0
3853 /* enum: Respond to flow control. */
3854 #define          MC_CMD_FCNTL_RESPOND 0x1
3855 /* enum: Respond to and Issue flow control. */
3856 #define          MC_CMD_FCNTL_BIDIR 0x2
3857 /* enum: Auto neg flow control. */
3858 #define          MC_CMD_FCNTL_AUTO 0x3
3859 /* enum: Priority flow control (eftest builds only). */
3860 #define          MC_CMD_FCNTL_QBB 0x4
3861 /* enum: Issue flow control. */
3862 #define          MC_CMD_FCNTL_GENERATE 0x5
3863 #define       MC_CMD_SET_MAC_IN_FLAGS_OFST 24
3864 #define       MC_CMD_SET_MAC_IN_FLAGS_LEN 4
3865 #define        MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0
3866 #define        MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1
3867 
3868 /* MC_CMD_SET_MAC_EXT_IN msgrequest */
3869 #define    MC_CMD_SET_MAC_EXT_IN_LEN 32
3870 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
3871  * EtherII, VLAN, bug16011 padding).
3872  */
3873 #define       MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0
3874 #define       MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4
3875 #define       MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4
3876 #define       MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4
3877 #define       MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8
3878 #define       MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8
3879 #define       MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8
3880 #define       MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12
3881 #define       MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16
3882 #define       MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4
3883 #define        MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0
3884 #define        MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1
3885 #define        MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1
3886 #define        MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1
3887 #define       MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20
3888 #define       MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4
3889 /* enum: Flow control is off. */
3890 /*               MC_CMD_FCNTL_OFF 0x0 */
3891 /* enum: Respond to flow control. */
3892 /*               MC_CMD_FCNTL_RESPOND 0x1 */
3893 /* enum: Respond to and Issue flow control. */
3894 /*               MC_CMD_FCNTL_BIDIR 0x2 */
3895 /* enum: Auto neg flow control. */
3896 /*               MC_CMD_FCNTL_AUTO 0x3 */
3897 /* enum: Priority flow control (eftest builds only). */
3898 /*               MC_CMD_FCNTL_QBB 0x4 */
3899 /* enum: Issue flow control. */
3900 /*               MC_CMD_FCNTL_GENERATE 0x5 */
3901 #define       MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24
3902 #define       MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4
3903 #define        MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0
3904 #define        MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1
3905 /* Select which parameters to configure. A parameter will only be modified if
3906  * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in
3907  * capabilities then this field is ignored (and all flags are assumed to be
3908  * set).
3909  */
3910 #define       MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28
3911 #define       MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4
3912 #define        MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0
3913 #define        MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1
3914 #define        MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1
3915 #define        MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1
3916 #define        MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2
3917 #define        MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1
3918 #define        MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3
3919 #define        MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1
3920 #define        MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
3921 #define        MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1
3922 
3923 /* MC_CMD_SET_MAC_OUT msgresponse */
3924 #define    MC_CMD_SET_MAC_OUT_LEN 0
3925 
3926 /* MC_CMD_SET_MAC_V2_OUT msgresponse */
3927 #define    MC_CMD_SET_MAC_V2_OUT_LEN 4
3928 /* MTU as configured after processing the request. See comment at
3929  * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL
3930  * to 0.
3931  */
3932 #define       MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0
3933 #define       MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4
3934 
3935 
3936 /***********************************/
3937 /* MC_CMD_PHY_STATS
3938  * Get generic PHY statistics. This call returns the statistics for a generic
3939  * PHY in a sparse array (indexed by the enumerate). Each value is represented
3940  * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the
3941  * statistics may be read from the message response. If DMA_ADDR != 0, then the
3942  * statistics are dmad to that (page-aligned location). Locks required: None.
3943  * Returns: 0, ETIME
3944  */
3945 #define MC_CMD_PHY_STATS 0x2d
3946 
3947 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK
3948 
3949 /* MC_CMD_PHY_STATS_IN msgrequest */
3950 #define    MC_CMD_PHY_STATS_IN_LEN 8
3951 /* ??? */
3952 #define       MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
3953 #define       MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8
3954 #define       MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
3955 #define       MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
3956 
3957 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */
3958 #define    MC_CMD_PHY_STATS_OUT_DMA_LEN 0
3959 
3960 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */
3961 #define    MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3)
3962 #define       MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
3963 #define       MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
3964 #define       MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS
3965 /* enum: OUI. */
3966 #define          MC_CMD_OUI 0x0
3967 /* enum: PMA-PMD Link Up. */
3968 #define          MC_CMD_PMA_PMD_LINK_UP 0x1
3969 /* enum: PMA-PMD RX Fault. */
3970 #define          MC_CMD_PMA_PMD_RX_FAULT 0x2
3971 /* enum: PMA-PMD TX Fault. */
3972 #define          MC_CMD_PMA_PMD_TX_FAULT 0x3
3973 /* enum: PMA-PMD Signal */
3974 #define          MC_CMD_PMA_PMD_SIGNAL 0x4
3975 /* enum: PMA-PMD SNR A. */
3976 #define          MC_CMD_PMA_PMD_SNR_A 0x5
3977 /* enum: PMA-PMD SNR B. */
3978 #define          MC_CMD_PMA_PMD_SNR_B 0x6
3979 /* enum: PMA-PMD SNR C. */
3980 #define          MC_CMD_PMA_PMD_SNR_C 0x7
3981 /* enum: PMA-PMD SNR D. */
3982 #define          MC_CMD_PMA_PMD_SNR_D 0x8
3983 /* enum: PCS Link Up. */
3984 #define          MC_CMD_PCS_LINK_UP 0x9
3985 /* enum: PCS RX Fault. */
3986 #define          MC_CMD_PCS_RX_FAULT 0xa
3987 /* enum: PCS TX Fault. */
3988 #define          MC_CMD_PCS_TX_FAULT 0xb
3989 /* enum: PCS BER. */
3990 #define          MC_CMD_PCS_BER 0xc
3991 /* enum: PCS Block Errors. */
3992 #define          MC_CMD_PCS_BLOCK_ERRORS 0xd
3993 /* enum: PhyXS Link Up. */
3994 #define          MC_CMD_PHYXS_LINK_UP 0xe
3995 /* enum: PhyXS RX Fault. */
3996 #define          MC_CMD_PHYXS_RX_FAULT 0xf
3997 /* enum: PhyXS TX Fault. */
3998 #define          MC_CMD_PHYXS_TX_FAULT 0x10
3999 /* enum: PhyXS Align. */
4000 #define          MC_CMD_PHYXS_ALIGN 0x11
4001 /* enum: PhyXS Sync. */
4002 #define          MC_CMD_PHYXS_SYNC 0x12
4003 /* enum: AN link-up. */
4004 #define          MC_CMD_AN_LINK_UP 0x13
4005 /* enum: AN Complete. */
4006 #define          MC_CMD_AN_COMPLETE 0x14
4007 /* enum: AN 10GBaseT Status. */
4008 #define          MC_CMD_AN_10GBT_STATUS 0x15
4009 /* enum: Clause 22 Link-Up. */
4010 #define          MC_CMD_CL22_LINK_UP 0x16
4011 /* enum: (Last entry) */
4012 #define          MC_CMD_PHY_NSTATS 0x17
4013 
4014 
4015 /***********************************/
4016 /* MC_CMD_MAC_STATS
4017  * Get generic MAC statistics. This call returns unified statistics maintained
4018  * by the MC as it switches between the GMAC and XMAC. The MC will write out
4019  * all supported stats. The driver should zero initialise the buffer to
4020  * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is
4021  * performed, and the statistics may be read from the message response. If
4022  * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
4023  * Locks required: None. The PERIODIC_CLEAR option is not used and now has no
4024  * effect. Returns: 0, ETIME
4025  */
4026 #define MC_CMD_MAC_STATS 0x2e
4027 
4028 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4029 
4030 /* MC_CMD_MAC_STATS_IN msgrequest */
4031 #define    MC_CMD_MAC_STATS_IN_LEN 20
4032 /* ??? */
4033 #define       MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
4034 #define       MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8
4035 #define       MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
4036 #define       MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
4037 #define       MC_CMD_MAC_STATS_IN_CMD_OFST 8
4038 #define       MC_CMD_MAC_STATS_IN_CMD_LEN 4
4039 #define        MC_CMD_MAC_STATS_IN_DMA_LBN 0
4040 #define        MC_CMD_MAC_STATS_IN_DMA_WIDTH 1
4041 #define        MC_CMD_MAC_STATS_IN_CLEAR_LBN 1
4042 #define        MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1
4043 #define        MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2
4044 #define        MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1
4045 #define        MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3
4046 #define        MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1
4047 #define        MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
4048 #define        MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1
4049 #define        MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5
4050 #define        MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1
4051 #define        MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16
4052 #define        MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16
4053 /* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as
4054  * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not
4055  * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to
4056  * MC_CMD_MAC_NSTATS * sizeof(uint64_t)
4057  */
4058 #define       MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12
4059 #define       MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4
4060 /* port id so vadapter stats can be provided */
4061 #define       MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16
4062 #define       MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4
4063 
4064 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */
4065 #define    MC_CMD_MAC_STATS_OUT_DMA_LEN 0
4066 
4067 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */
4068 #define    MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
4069 #define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
4070 #define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8
4071 #define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
4072 #define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
4073 #define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
4074 #define          MC_CMD_MAC_GENERATION_START 0x0 /* enum */
4075 #define          MC_CMD_MAC_DMABUF_START 0x1 /* enum */
4076 #define          MC_CMD_MAC_TX_PKTS 0x1 /* enum */
4077 #define          MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
4078 #define          MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
4079 #define          MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
4080 #define          MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
4081 #define          MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
4082 #define          MC_CMD_MAC_TX_BYTES 0x7 /* enum */
4083 #define          MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
4084 #define          MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
4085 #define          MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
4086 #define          MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
4087 #define          MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
4088 #define          MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
4089 #define          MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
4090 #define          MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
4091 #define          MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
4092 #define          MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
4093 #define          MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
4094 #define          MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
4095 #define          MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
4096 #define          MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
4097 #define          MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
4098 #define          MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
4099 #define          MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
4100 #define          MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
4101 #define          MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
4102 #define          MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
4103 #define          MC_CMD_MAC_RX_PKTS 0x1c /* enum */
4104 #define          MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
4105 #define          MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
4106 #define          MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
4107 #define          MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
4108 #define          MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
4109 #define          MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
4110 #define          MC_CMD_MAC_RX_BYTES 0x23 /* enum */
4111 #define          MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
4112 #define          MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
4113 #define          MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
4114 #define          MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
4115 #define          MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
4116 #define          MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
4117 #define          MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
4118 #define          MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
4119 #define          MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
4120 #define          MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
4121 #define          MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
4122 #define          MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
4123 #define          MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
4124 #define          MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
4125 #define          MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
4126 #define          MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
4127 #define          MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
4128 #define          MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
4129 #define          MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
4130 #define          MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
4131 #define          MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
4132 #define          MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
4133 #define          MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
4134 #define          MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
4135 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4136  * capability only.
4137  */
4138 #define          MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
4139 /* enum: PM discard_bb_overflow counter. Valid for EF10 with
4140  * PM_AND_RXDP_COUNTERS capability only.
4141  */
4142 #define          MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
4143 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4144  * capability only.
4145  */
4146 #define          MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
4147 /* enum: PM discard_vfifo_full counter. Valid for EF10 with
4148  * PM_AND_RXDP_COUNTERS capability only.
4149  */
4150 #define          MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
4151 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4152  * capability only.
4153  */
4154 #define          MC_CMD_MAC_PM_TRUNC_QBB 0x40
4155 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4156  * capability only.
4157  */
4158 #define          MC_CMD_MAC_PM_DISCARD_QBB 0x41
4159 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4160  * capability only.
4161  */
4162 #define          MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
4163 /* enum: RXDP counter: Number of packets dropped due to the queue being
4164  * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
4165  */
4166 #define          MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
4167 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10
4168  * with PM_AND_RXDP_COUNTERS capability only.
4169  */
4170 #define          MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
4171 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
4172  * PM_AND_RXDP_COUNTERS capability only.
4173  */
4174 #define          MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
4175 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed.
4176  * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
4177  */
4178 #define          MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
4179 /* enum: RXDP counter: Number of times the DPCPU waited for an existing
4180  * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
4181  */
4182 #define          MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
4183 #define          MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
4184 #define          MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
4185 #define          MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
4186 #define          MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
4187 #define          MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
4188 #define          MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
4189 #define          MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
4190 #define          MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
4191 #define          MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
4192 #define          MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
4193 #define          MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
4194 #define          MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
4195 #define          MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
4196 #define          MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
4197 #define          MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
4198 #define          MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
4199 #define          MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
4200 #define          MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
4201 #define          MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
4202 #define          MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
4203 /* enum: Start of GMAC stats buffer space, for Siena only. */
4204 #define          MC_CMD_GMAC_DMABUF_START 0x40
4205 /* enum: End of GMAC stats buffer space, for Siena only. */
4206 #define          MC_CMD_GMAC_DMABUF_END 0x5f
4207 /* enum: GENERATION_END value, used together with GENERATION_START to verify
4208  * consistency of DMAd data. For legacy firmware / drivers without extended
4209  * stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS *
4210  * sizeof(uint64_t)), this entry holds the GENERATION_END value. Otherwise,
4211  * this value is invalid/ reserved and GENERATION_END is written as the last
4212  * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that
4213  * this is consistent with the legacy behaviour, in the sense that entry 96 is
4214  * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS *
4215  * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.
4216  */
4217 #define          MC_CMD_MAC_GENERATION_END 0x60
4218 #define          MC_CMD_MAC_NSTATS 0x61 /* enum */
4219 
4220 /* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */
4221 #define    MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0
4222 
4223 /* MC_CMD_MAC_STATS_V2_OUT_NO_DMA msgresponse */
4224 #define    MC_CMD_MAC_STATS_V2_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V2*64))>>3)
4225 #define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0
4226 #define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8
4227 #define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0
4228 #define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
4229 #define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2
4230 /* enum: Start of FEC stats buffer space, Medford2 and up */
4231 #define          MC_CMD_MAC_FEC_DMABUF_START 0x61
4232 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)
4233  */
4234 #define          MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61
4235 /* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)
4236  */
4237 #define          MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62
4238 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
4239 #define          MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63
4240 /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
4241 #define          MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64
4242 /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
4243 #define          MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65
4244 /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
4245 #define          MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66
4246 /* enum: This includes the space at offset 103 which is the final
4247  * GENERATION_END in a MAC_STATS_V2 response and otherwise unused.
4248  */
4249 #define          MC_CMD_MAC_NSTATS_V2 0x68
4250 /*            Other enum values, see field(s): */
4251 /*               MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */
4252 
4253 /* MC_CMD_MAC_STATS_V3_OUT_DMA msgresponse */
4254 #define    MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 0
4255 
4256 /* MC_CMD_MAC_STATS_V3_OUT_NO_DMA msgresponse */
4257 #define    MC_CMD_MAC_STATS_V3_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V3*64))>>3)
4258 #define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0
4259 #define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 8
4260 #define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0
4261 #define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4
4262 #define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3
4263 /* enum: Start of CTPIO stats buffer space, Medford2 and up */
4264 #define          MC_CMD_MAC_CTPIO_DMABUF_START 0x68
4265 /* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the
4266  * target VI
4267  */
4268 #define          MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68
4269 /* enum: Number of times a CTPIO send wrote beyond frame end (informational
4270  * only)
4271  */
4272 #define          MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69
4273 /* enum: Number of CTPIO failures because the TX doorbell was written before
4274  * the end of the frame data
4275  */
4276 #define          MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a
4277 /* enum: Number of CTPIO failures because the internal FIFO overflowed */
4278 #define          MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b
4279 /* enum: Number of CTPIO failures because the host did not deliver data fast
4280  * enough to avoid MAC underflow
4281  */
4282 #define          MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c
4283 /* enum: Number of CTPIO failures because the host did not deliver all the
4284  * frame data within the timeout
4285  */
4286 #define          MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d
4287 /* enum: Number of CTPIO failures because the frame data arrived out of order
4288  * or with gaps
4289  */
4290 #define          MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e
4291 /* enum: Number of CTPIO failures because the host started a new frame before
4292  * completing the previous one
4293  */
4294 #define          MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f
4295 /* enum: Number of CTPIO failures because a write was not a multiple of 32 bits
4296  * or not 32-bit aligned
4297  */
4298 #define          MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70
4299 /* enum: Number of CTPIO fallbacks because another VI on the same port was
4300  * sending a CTPIO frame
4301  */
4302 #define          MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71
4303 /* enum: Number of CTPIO fallbacks because target VI did not have CTPIO enabled
4304  */
4305 #define          MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72
4306 /* enum: Number of CTPIO fallbacks because length in header was less than 29
4307  * bytes
4308  */
4309 #define          MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73
4310 /* enum: Total number of successful CTPIO sends on this port */
4311 #define          MC_CMD_MAC_CTPIO_SUCCESS 0x74
4312 /* enum: Total number of CTPIO fallbacks on this port */
4313 #define          MC_CMD_MAC_CTPIO_FALLBACK 0x75
4314 /* enum: Total number of CTPIO poisoned frames on this port, whether erased or
4315  * not
4316  */
4317 #define          MC_CMD_MAC_CTPIO_POISON 0x76
4318 /* enum: Total number of CTPIO erased frames on this port */
4319 #define          MC_CMD_MAC_CTPIO_ERASE 0x77
4320 /* enum: This includes the space at offset 120 which is the final
4321  * GENERATION_END in a MAC_STATS_V3 response and otherwise unused.
4322  */
4323 #define          MC_CMD_MAC_NSTATS_V3 0x79
4324 /*            Other enum values, see field(s): */
4325 /*               MC_CMD_MAC_STATS_V2_OUT_NO_DMA/STATISTICS */
4326 
4327 
4328 /***********************************/
4329 /* MC_CMD_SRIOV
4330  * to be documented
4331  */
4332 #define MC_CMD_SRIOV 0x30
4333 
4334 /* MC_CMD_SRIOV_IN msgrequest */
4335 #define    MC_CMD_SRIOV_IN_LEN 12
4336 #define       MC_CMD_SRIOV_IN_ENABLE_OFST 0
4337 #define       MC_CMD_SRIOV_IN_ENABLE_LEN 4
4338 #define       MC_CMD_SRIOV_IN_VI_BASE_OFST 4
4339 #define       MC_CMD_SRIOV_IN_VI_BASE_LEN 4
4340 #define       MC_CMD_SRIOV_IN_VF_COUNT_OFST 8
4341 #define       MC_CMD_SRIOV_IN_VF_COUNT_LEN 4
4342 
4343 /* MC_CMD_SRIOV_OUT msgresponse */
4344 #define    MC_CMD_SRIOV_OUT_LEN 8
4345 #define       MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0
4346 #define       MC_CMD_SRIOV_OUT_VI_SCALE_LEN 4
4347 #define       MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4
4348 #define       MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4
4349 
4350 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */
4351 #define    MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32
4352 /* this is only used for the first record */
4353 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0
4354 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4
4355 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0
4356 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32
4357 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4
4358 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4
4359 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32
4360 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32
4361 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8
4362 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8
4363 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8
4364 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12
4365 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64
4366 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64
4367 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16
4368 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4
4369 #define          MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
4370 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128
4371 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32
4372 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20
4373 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8
4374 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20
4375 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24
4376 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160
4377 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64
4378 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28
4379 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4
4380 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224
4381 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32
4382 
4383 
4384 /***********************************/
4385 /* MC_CMD_MEMCPY
4386  * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data
4387  * embedded directly in the command.
4388  *
4389  * A common pattern is for a client to use generation counts to signal a dma
4390  * update of a datastructure. To facilitate this, this MCDI operation can
4391  * contain multiple requests which are executed in strict order. Requests take
4392  * the form of duplicating the entire MCDI request continuously (including the
4393  * requests record, which is ignored in all but the first structure)
4394  *
4395  * The source data can either come from a DMA from the host, or it can be
4396  * embedded within the request directly, thereby eliminating a DMA read. To
4397  * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and
4398  * ADDR_LO=offset, and inserts the data at %offset from the start of the
4399  * payload. It's the callers responsibility to ensure that the embedded data
4400  * doesn't overlap the records.
4401  *
4402  * Returns: 0, EINVAL (invalid RID)
4403  */
4404 #define MC_CMD_MEMCPY 0x31
4405 
4406 /* MC_CMD_MEMCPY_IN msgrequest */
4407 #define    MC_CMD_MEMCPY_IN_LENMIN 32
4408 #define    MC_CMD_MEMCPY_IN_LENMAX 224
4409 #define    MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
4410 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */
4411 #define       MC_CMD_MEMCPY_IN_RECORD_OFST 0
4412 #define       MC_CMD_MEMCPY_IN_RECORD_LEN 32
4413 #define       MC_CMD_MEMCPY_IN_RECORD_MINNUM 1
4414 #define       MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7
4415 
4416 /* MC_CMD_MEMCPY_OUT msgresponse */
4417 #define    MC_CMD_MEMCPY_OUT_LEN 0
4418 
4419 
4420 /***********************************/
4421 /* MC_CMD_WOL_FILTER_SET
4422  * Set a WoL filter.
4423  */
4424 #define MC_CMD_WOL_FILTER_SET 0x32
4425 
4426 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK
4427 
4428 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */
4429 #define    MC_CMD_WOL_FILTER_SET_IN_LEN 192
4430 #define       MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
4431 #define       MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4
4432 #define          MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
4433 #define          MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
4434 /* A type value of 1 is unused. */
4435 #define       MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
4436 #define       MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4
4437 /* enum: Magic */
4438 #define          MC_CMD_WOL_TYPE_MAGIC 0x0
4439 /* enum: MS Windows Magic */
4440 #define          MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
4441 /* enum: IPv4 Syn */
4442 #define          MC_CMD_WOL_TYPE_IPV4_SYN 0x3
4443 /* enum: IPv6 Syn */
4444 #define          MC_CMD_WOL_TYPE_IPV6_SYN 0x4
4445 /* enum: Bitmap */
4446 #define          MC_CMD_WOL_TYPE_BITMAP 0x5
4447 /* enum: Link */
4448 #define          MC_CMD_WOL_TYPE_LINK 0x6
4449 /* enum: (Above this for future use) */
4450 #define          MC_CMD_WOL_TYPE_MAX 0x7
4451 #define       MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8
4452 #define       MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
4453 #define       MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46
4454 
4455 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */
4456 #define    MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16
4457 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4458 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
4459 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
4460 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
4461 #define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8
4462 #define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8
4463 #define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8
4464 #define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12
4465 
4466 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */
4467 #define    MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20
4468 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4469 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
4470 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
4471 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
4472 #define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8
4473 #define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4
4474 #define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12
4475 #define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4
4476 #define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16
4477 #define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2
4478 #define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18
4479 #define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2
4480 
4481 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */
4482 #define    MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44
4483 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4484 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
4485 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
4486 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
4487 #define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8
4488 #define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16
4489 #define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24
4490 #define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16
4491 #define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40
4492 #define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2
4493 #define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42
4494 #define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2
4495 
4496 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */
4497 #define    MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187
4498 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4499 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
4500 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
4501 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
4502 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8
4503 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48
4504 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56
4505 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128
4506 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184
4507 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1
4508 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185
4509 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1
4510 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186
4511 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1
4512 
4513 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */
4514 #define    MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12
4515 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4516 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
4517 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
4518 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
4519 #define       MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8
4520 #define       MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4
4521 #define        MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
4522 #define        MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
4523 #define        MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
4524 #define        MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1
4525 
4526 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */
4527 #define    MC_CMD_WOL_FILTER_SET_OUT_LEN 4
4528 #define       MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
4529 #define       MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4
4530 
4531 
4532 /***********************************/
4533 /* MC_CMD_WOL_FILTER_REMOVE
4534  * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
4535  */
4536 #define MC_CMD_WOL_FILTER_REMOVE 0x33
4537 
4538 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK
4539 
4540 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */
4541 #define    MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
4542 #define       MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
4543 #define       MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4
4544 
4545 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */
4546 #define    MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
4547 
4548 
4549 /***********************************/
4550 /* MC_CMD_WOL_FILTER_RESET
4551  * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,
4552  * ENOSYS
4553  */
4554 #define MC_CMD_WOL_FILTER_RESET 0x34
4555 
4556 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK
4557 
4558 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */
4559 #define    MC_CMD_WOL_FILTER_RESET_IN_LEN 4
4560 #define       MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
4561 #define       MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4
4562 #define          MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
4563 #define          MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
4564 
4565 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */
4566 #define    MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
4567 
4568 
4569 /***********************************/
4570 /* MC_CMD_SET_MCAST_HASH
4571  * Set the MCAST hash value without otherwise reconfiguring the MAC
4572  */
4573 #define MC_CMD_SET_MCAST_HASH 0x35
4574 
4575 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */
4576 #define    MC_CMD_SET_MCAST_HASH_IN_LEN 32
4577 #define       MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
4578 #define       MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16
4579 #define       MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16
4580 #define       MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16
4581 
4582 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */
4583 #define    MC_CMD_SET_MCAST_HASH_OUT_LEN 0
4584 
4585 
4586 /***********************************/
4587 /* MC_CMD_NVRAM_TYPES
4588  * Return bitfield indicating available types of virtual NVRAM partitions.
4589  * Locks required: none. Returns: 0
4590  */
4591 #define MC_CMD_NVRAM_TYPES 0x36
4592 
4593 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4594 
4595 /* MC_CMD_NVRAM_TYPES_IN msgrequest */
4596 #define    MC_CMD_NVRAM_TYPES_IN_LEN 0
4597 
4598 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */
4599 #define    MC_CMD_NVRAM_TYPES_OUT_LEN 4
4600 /* Bit mask of supported types. */
4601 #define       MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
4602 #define       MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4
4603 /* enum: Disabled callisto. */
4604 #define          MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0
4605 /* enum: MC firmware. */
4606 #define          MC_CMD_NVRAM_TYPE_MC_FW 0x1
4607 /* enum: MC backup firmware. */
4608 #define          MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2
4609 /* enum: Static configuration Port0. */
4610 #define          MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3
4611 /* enum: Static configuration Port1. */
4612 #define          MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4
4613 /* enum: Dynamic configuration Port0. */
4614 #define          MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5
4615 /* enum: Dynamic configuration Port1. */
4616 #define          MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6
4617 /* enum: Expansion Rom. */
4618 #define          MC_CMD_NVRAM_TYPE_EXP_ROM 0x7
4619 /* enum: Expansion Rom Configuration Port0. */
4620 #define          MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8
4621 /* enum: Expansion Rom Configuration Port1. */
4622 #define          MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9
4623 /* enum: Phy Configuration Port0. */
4624 #define          MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa
4625 /* enum: Phy Configuration Port1. */
4626 #define          MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb
4627 /* enum: Log. */
4628 #define          MC_CMD_NVRAM_TYPE_LOG 0xc
4629 /* enum: FPGA image. */
4630 #define          MC_CMD_NVRAM_TYPE_FPGA 0xd
4631 /* enum: FPGA backup image */
4632 #define          MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe
4633 /* enum: FC firmware. */
4634 #define          MC_CMD_NVRAM_TYPE_FC_FW 0xf
4635 /* enum: FC backup firmware. */
4636 #define          MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10
4637 /* enum: CPLD image. */
4638 #define          MC_CMD_NVRAM_TYPE_CPLD 0x11
4639 /* enum: Licensing information. */
4640 #define          MC_CMD_NVRAM_TYPE_LICENSE 0x12
4641 /* enum: FC Log. */
4642 #define          MC_CMD_NVRAM_TYPE_FC_LOG 0x13
4643 /* enum: Additional flash on FPGA. */
4644 #define          MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14
4645 
4646 
4647 /***********************************/
4648 /* MC_CMD_NVRAM_INFO
4649  * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,
4650  * EINVAL (bad type).
4651  */
4652 #define MC_CMD_NVRAM_INFO 0x37
4653 
4654 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4655 
4656 /* MC_CMD_NVRAM_INFO_IN msgrequest */
4657 #define    MC_CMD_NVRAM_INFO_IN_LEN 4
4658 #define       MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
4659 #define       MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4
4660 /*            Enum values, see field(s): */
4661 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4662 
4663 /* MC_CMD_NVRAM_INFO_OUT msgresponse */
4664 #define    MC_CMD_NVRAM_INFO_OUT_LEN 24
4665 #define       MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
4666 #define       MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4
4667 /*            Enum values, see field(s): */
4668 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4669 #define       MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
4670 #define       MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4
4671 #define       MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8
4672 #define       MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4
4673 #define       MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12
4674 #define       MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4
4675 #define        MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
4676 #define        MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
4677 #define        MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1
4678 #define        MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1
4679 #define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
4680 #define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
4681 #define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5
4682 #define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1
4683 #define        MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6
4684 #define        MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1
4685 #define        MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7
4686 #define        MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1
4687 #define       MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16
4688 #define       MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4
4689 #define       MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20
4690 #define       MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4
4691 
4692 /* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */
4693 #define    MC_CMD_NVRAM_INFO_V2_OUT_LEN 28
4694 #define       MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0
4695 #define       MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4
4696 /*            Enum values, see field(s): */
4697 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4698 #define       MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4
4699 #define       MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4
4700 #define       MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8
4701 #define       MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4
4702 #define       MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12
4703 #define       MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4
4704 #define        MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0
4705 #define        MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1
4706 #define        MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1
4707 #define        MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1
4708 #define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
4709 #define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
4710 #define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5
4711 #define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1
4712 #define        MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7
4713 #define        MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1
4714 #define       MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16
4715 #define       MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4
4716 #define       MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20
4717 #define       MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4
4718 /* Writes must be multiples of this size. Added to support the MUM on Sorrento.
4719  */
4720 #define       MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24
4721 #define       MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4
4722 
4723 
4724 /***********************************/
4725 /* MC_CMD_NVRAM_UPDATE_START
4726  * Start a group of update operations on a virtual NVRAM partition. Locks
4727  * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if
4728  * PHY_LOCK required and not held). In an adapter bound to a TSA controller,
4729  * MC_CMD_NVRAM_UPDATE_START can only be used on a subset of partition types
4730  * i.e. static config, dynamic config and expansion ROM config. Attempting to
4731  * perform this operation on a restricted partition will return the error
4732  * EPERM.
4733  */
4734 #define MC_CMD_NVRAM_UPDATE_START 0x38
4735 
4736 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4737 
4738 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request.
4739  * Use NVRAM_UPDATE_START_V2_IN in new code
4740  */
4741 #define    MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
4742 #define       MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
4743 #define       MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4
4744 /*            Enum values, see field(s): */
4745 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4746 
4747 /* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START
4748  * request with additional flags indicating version of command in use. See
4749  * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use
4750  * paired up with NVRAM_UPDATE_FINISH_V2_IN.
4751  */
4752 #define    MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8
4753 #define       MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0
4754 #define       MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4
4755 /*            Enum values, see field(s): */
4756 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4757 #define       MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4
4758 #define       MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4
4759 #define        MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
4760 #define        MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
4761 
4762 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */
4763 #define    MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
4764 
4765 
4766 /***********************************/
4767 /* MC_CMD_NVRAM_READ
4768  * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if
4769  * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
4770  * PHY_LOCK required and not held)
4771  */
4772 #define MC_CMD_NVRAM_READ 0x39
4773 
4774 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4775 
4776 /* MC_CMD_NVRAM_READ_IN msgrequest */
4777 #define    MC_CMD_NVRAM_READ_IN_LEN 12
4778 #define       MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
4779 #define       MC_CMD_NVRAM_READ_IN_TYPE_LEN 4
4780 /*            Enum values, see field(s): */
4781 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4782 #define       MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
4783 #define       MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4
4784 /* amount to read in bytes */
4785 #define       MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8
4786 #define       MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4
4787 
4788 /* MC_CMD_NVRAM_READ_IN_V2 msgrequest */
4789 #define    MC_CMD_NVRAM_READ_IN_V2_LEN 16
4790 #define       MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0
4791 #define       MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4
4792 /*            Enum values, see field(s): */
4793 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4794 #define       MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4
4795 #define       MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4
4796 /* amount to read in bytes */
4797 #define       MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8
4798 #define       MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4
4799 /* Optional control info. If a partition is stored with an A/B versioning
4800  * scheme (i.e. in more than one physical partition in NVRAM) the host can set
4801  * this to control which underlying physical partition is used to read data
4802  * from. This allows it to perform a read-modify-write-verify with the write
4803  * lock continuously held by calling NVRAM_UPDATE_START, reading the old
4804  * contents using MODE=TARGET_CURRENT, overwriting the old partition and then
4805  * verifying by reading with MODE=TARGET_BACKUP.
4806  */
4807 #define       MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12
4808 #define       MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4
4809 /* enum: Same as omitting MODE: caller sees data in current partition unless it
4810  * holds the write lock in which case it sees data in the partition it is
4811  * updating.
4812  */
4813 #define          MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0
4814 /* enum: Read from the current partition of an A/B pair, even if holding the
4815  * write lock.
4816  */
4817 #define          MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1
4818 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B
4819  * pair
4820  */
4821 #define          MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2
4822 
4823 /* MC_CMD_NVRAM_READ_OUT msgresponse */
4824 #define    MC_CMD_NVRAM_READ_OUT_LENMIN 1
4825 #define    MC_CMD_NVRAM_READ_OUT_LENMAX 252
4826 #define    MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
4827 #define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
4828 #define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
4829 #define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
4830 #define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252
4831 
4832 
4833 /***********************************/
4834 /* MC_CMD_NVRAM_WRITE
4835  * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if
4836  * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
4837  * PHY_LOCK required and not held)
4838  */
4839 #define MC_CMD_NVRAM_WRITE 0x3a
4840 
4841 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4842 
4843 /* MC_CMD_NVRAM_WRITE_IN msgrequest */
4844 #define    MC_CMD_NVRAM_WRITE_IN_LENMIN 13
4845 #define    MC_CMD_NVRAM_WRITE_IN_LENMAX 252
4846 #define    MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
4847 #define       MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
4848 #define       MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4
4849 /*            Enum values, see field(s): */
4850 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4851 #define       MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
4852 #define       MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4
4853 #define       MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8
4854 #define       MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4
4855 #define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12
4856 #define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1
4857 #define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1
4858 #define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240
4859 
4860 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */
4861 #define    MC_CMD_NVRAM_WRITE_OUT_LEN 0
4862 
4863 
4864 /***********************************/
4865 /* MC_CMD_NVRAM_ERASE
4866  * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if
4867  * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
4868  * PHY_LOCK required and not held)
4869  */
4870 #define MC_CMD_NVRAM_ERASE 0x3b
4871 
4872 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4873 
4874 /* MC_CMD_NVRAM_ERASE_IN msgrequest */
4875 #define    MC_CMD_NVRAM_ERASE_IN_LEN 12
4876 #define       MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
4877 #define       MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4
4878 /*            Enum values, see field(s): */
4879 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4880 #define       MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
4881 #define       MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4
4882 #define       MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8
4883 #define       MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4
4884 
4885 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */
4886 #define    MC_CMD_NVRAM_ERASE_OUT_LEN 0
4887 
4888 
4889 /***********************************/
4890 /* MC_CMD_NVRAM_UPDATE_FINISH
4891  * Finish a group of update operations on a virtual NVRAM partition. Locks
4892  * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/
4893  * length), EACCES (if PHY_LOCK required and not held). In an adapter bound to
4894  * a TSA controller, MC_CMD_NVRAM_UPDATE_FINISH can only be used on a subset of
4895  * partition types i.e. static config, dynamic config and expansion ROM config.
4896  * Attempting to perform this operation on a restricted partition will return
4897  * the error EPERM.
4898  */
4899 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
4900 
4901 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4902 
4903 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH
4904  * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code
4905  */
4906 #define    MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8
4907 #define       MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
4908 #define       MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4
4909 /*            Enum values, see field(s): */
4910 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4911 #define       MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
4912 #define       MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4
4913 
4914 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH
4915  * request with additional flags indicating version of NVRAM_UPDATE commands in
4916  * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended
4917  * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN.
4918  */
4919 #define    MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12
4920 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0
4921 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4
4922 /*            Enum values, see field(s): */
4923 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4924 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4
4925 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4
4926 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8
4927 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4
4928 #define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
4929 #define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
4930 
4931 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH
4932  * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code
4933  */
4934 #define    MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
4935 
4936 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse:
4937  *
4938  * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure
4939  * firmware validation where applicable back to the host.
4940  *
4941  * Medford only: For signed firmware images, such as those for medford, the MC
4942  * firmware verifies the signature before marking the firmware image as valid.
4943  * This process takes a few seconds to complete. So is likely to take more than
4944  * the MCDI timeout. Hence signature verification is initiated when
4945  * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the
4946  * MCDI command is run in a background MCDI processing thread. This response
4947  * payload includes the results of the signature verification. Note that the
4948  * per-partition nvram lock in firmware is only released after the verification
4949  * has completed.
4950  */
4951 #define    MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4
4952 /* Result of nvram update completion processing */
4953 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0
4954 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4
4955 /* enum: Invalid return code; only non-zero values are defined. Defined as
4956  * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT.
4957  */
4958 #define          MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0
4959 /* enum: Verify succeeded without any errors. */
4960 #define          MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1
4961 /* enum: CMS format verification failed due to an internal error. */
4962 #define          MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2
4963 /* enum: Invalid CMS format in image metadata. */
4964 #define          MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3
4965 /* enum: Message digest verification failed due to an internal error. */
4966 #define          MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4
4967 /* enum: Error in message digest calculated over the reflash-header, payload
4968  * and reflash-trailer.
4969  */
4970 #define          MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5
4971 /* enum: Signature verification failed due to an internal error. */
4972 #define          MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6
4973 /* enum: There are no valid signatures in the image. */
4974 #define          MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7
4975 /* enum: Trusted approvers verification failed due to an internal error. */
4976 #define          MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8
4977 /* enum: The Trusted approver's list is empty. */
4978 #define          MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9
4979 /* enum: Signature chain verification failed due to an internal error. */
4980 #define          MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa
4981 /* enum: The signers of the signatures in the image are not listed in the
4982  * Trusted approver's list.
4983  */
4984 #define          MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb
4985 /* enum: The image contains a test-signed certificate, but the adapter accepts
4986  * only production signed images.
4987  */
4988 #define          MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc
4989 /* enum: The image has a lower security level than the current firmware. */
4990 #define          MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd
4991 
4992 
4993 /***********************************/
4994 /* MC_CMD_REBOOT
4995  * Reboot the MC.
4996  *
4997  * The AFTER_ASSERTION flag is intended to be used when the driver notices an
4998  * assertion failure (at which point it is expected to perform a complete tear
4999  * down and reinitialise), to allow both ports to reset the MC once in an
5000  * atomic fashion.
5001  *
5002  * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,
5003  * which means that they will automatically reboot out of the assertion
5004  * handler, so this is in practise an optional operation. It is still
5005  * recommended that drivers execute this to support custom firmwares with
5006  * REBOOT_ON_ASSERT=0.
5007  *
5008  * Locks required: NONE Returns: Nothing. You get back a response with ERR=1,
5009  * DATALEN=0
5010  */
5011 #define MC_CMD_REBOOT 0x3d
5012 
5013 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5014 
5015 /* MC_CMD_REBOOT_IN msgrequest */
5016 #define    MC_CMD_REBOOT_IN_LEN 4
5017 #define       MC_CMD_REBOOT_IN_FLAGS_OFST 0
5018 #define       MC_CMD_REBOOT_IN_FLAGS_LEN 4
5019 #define          MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
5020 
5021 /* MC_CMD_REBOOT_OUT msgresponse */
5022 #define    MC_CMD_REBOOT_OUT_LEN 0
5023 
5024 
5025 /***********************************/
5026 /* MC_CMD_SCHEDINFO
5027  * Request scheduler info. Locks required: NONE. Returns: An array of
5028  * (timeslice,maximum overrun), one for each thread, in ascending order of
5029  * thread address.
5030  */
5031 #define MC_CMD_SCHEDINFO 0x3e
5032 
5033 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5034 
5035 /* MC_CMD_SCHEDINFO_IN msgrequest */
5036 #define    MC_CMD_SCHEDINFO_IN_LEN 0
5037 
5038 /* MC_CMD_SCHEDINFO_OUT msgresponse */
5039 #define    MC_CMD_SCHEDINFO_OUT_LENMIN 4
5040 #define    MC_CMD_SCHEDINFO_OUT_LENMAX 252
5041 #define    MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
5042 #define       MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
5043 #define       MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
5044 #define       MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1
5045 #define       MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63
5046 
5047 
5048 /***********************************/
5049 /* MC_CMD_REBOOT_MODE
5050  * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot
5051  * mode to the specified value. Returns the old mode.
5052  */
5053 #define MC_CMD_REBOOT_MODE 0x3f
5054 
5055 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE
5056 
5057 /* MC_CMD_REBOOT_MODE_IN msgrequest */
5058 #define    MC_CMD_REBOOT_MODE_IN_LEN 4
5059 #define       MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
5060 #define       MC_CMD_REBOOT_MODE_IN_VALUE_LEN 4
5061 /* enum: Normal. */
5062 #define          MC_CMD_REBOOT_MODE_NORMAL 0x0
5063 /* enum: Power-on Reset. */
5064 #define          MC_CMD_REBOOT_MODE_POR 0x2
5065 /* enum: Snapper. */
5066 #define          MC_CMD_REBOOT_MODE_SNAPPER 0x3
5067 /* enum: snapper fake POR */
5068 #define          MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4
5069 #define        MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7
5070 #define        MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1
5071 
5072 /* MC_CMD_REBOOT_MODE_OUT msgresponse */
5073 #define    MC_CMD_REBOOT_MODE_OUT_LEN 4
5074 #define       MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
5075 #define       MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4
5076 
5077 
5078 /***********************************/
5079 /* MC_CMD_SENSOR_INFO
5080  * Returns information about every available sensor.
5081  *
5082  * Each sensor has a single (16bit) value, and a corresponding state. The
5083  * mapping between value and state is nominally determined by the MC, but may
5084  * be implemented using up to 2 ranges per sensor.
5085  *
5086  * This call returns a mask (32bit) of the sensors that are supported by this
5087  * platform, then an array of sensor information structures, in order of sensor
5088  * type (but without gaps for unimplemented sensors). Each structure defines
5089  * the ranges for the corresponding sensor. An unused range is indicated by
5090  * equal limit values. If one range is used, a value outside that range results
5091  * in STATE_FATAL. If two ranges are used, a value outside the second range
5092  * results in STATE_FATAL while a value outside the first and inside the second
5093  * range results in STATE_WARNING.
5094  *
5095  * Sensor masks and sensor information arrays are organised into pages. For
5096  * backward compatibility, older host software can only use sensors in page 0.
5097  * Bit 32 in the sensor mask was previously unused, and is no reserved for use
5098  * as the next page flag.
5099  *
5100  * If the request does not contain a PAGE value then firmware will only return
5101  * page 0 of sensor information, with bit 31 in the sensor mask cleared.
5102  *
5103  * If the request contains a PAGE value then firmware responds with the sensor
5104  * mask and sensor information array for that page of sensors. In this case bit
5105  * 31 in the mask is set if another page exists.
5106  *
5107  * Locks required: None Returns: 0
5108  */
5109 #define MC_CMD_SENSOR_INFO 0x41
5110 
5111 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5112 
5113 /* MC_CMD_SENSOR_INFO_IN msgrequest */
5114 #define    MC_CMD_SENSOR_INFO_IN_LEN 0
5115 
5116 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */
5117 #define    MC_CMD_SENSOR_INFO_EXT_IN_LEN 4
5118 /* Which page of sensors to report.
5119  *
5120  * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
5121  *
5122  * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
5123  */
5124 #define       MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0
5125 #define       MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4
5126 
5127 /* MC_CMD_SENSOR_INFO_OUT msgresponse */
5128 #define    MC_CMD_SENSOR_INFO_OUT_LENMIN 4
5129 #define    MC_CMD_SENSOR_INFO_OUT_LENMAX 252
5130 #define    MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
5131 #define       MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
5132 #define       MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4
5133 /* enum: Controller temperature: degC */
5134 #define          MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
5135 /* enum: Phy common temperature: degC */
5136 #define          MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
5137 /* enum: Controller cooling: bool */
5138 #define          MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
5139 /* enum: Phy 0 temperature: degC */
5140 #define          MC_CMD_SENSOR_PHY0_TEMP 0x3
5141 /* enum: Phy 0 cooling: bool */
5142 #define          MC_CMD_SENSOR_PHY0_COOLING 0x4
5143 /* enum: Phy 1 temperature: degC */
5144 #define          MC_CMD_SENSOR_PHY1_TEMP 0x5
5145 /* enum: Phy 1 cooling: bool */
5146 #define          MC_CMD_SENSOR_PHY1_COOLING 0x6
5147 /* enum: 1.0v power: mV */
5148 #define          MC_CMD_SENSOR_IN_1V0 0x7
5149 /* enum: 1.2v power: mV */
5150 #define          MC_CMD_SENSOR_IN_1V2 0x8
5151 /* enum: 1.8v power: mV */
5152 #define          MC_CMD_SENSOR_IN_1V8 0x9
5153 /* enum: 2.5v power: mV */
5154 #define          MC_CMD_SENSOR_IN_2V5 0xa
5155 /* enum: 3.3v power: mV */
5156 #define          MC_CMD_SENSOR_IN_3V3 0xb
5157 /* enum: 12v power: mV */
5158 #define          MC_CMD_SENSOR_IN_12V0 0xc
5159 /* enum: 1.2v analogue power: mV */
5160 #define          MC_CMD_SENSOR_IN_1V2A 0xd
5161 /* enum: reference voltage: mV */
5162 #define          MC_CMD_SENSOR_IN_VREF 0xe
5163 /* enum: AOE FPGA power: mV */
5164 #define          MC_CMD_SENSOR_OUT_VAOE 0xf
5165 /* enum: AOE FPGA temperature: degC */
5166 #define          MC_CMD_SENSOR_AOE_TEMP 0x10
5167 /* enum: AOE FPGA PSU temperature: degC */
5168 #define          MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
5169 /* enum: AOE PSU temperature: degC */
5170 #define          MC_CMD_SENSOR_PSU_TEMP 0x12
5171 /* enum: Fan 0 speed: RPM */
5172 #define          MC_CMD_SENSOR_FAN_0 0x13
5173 /* enum: Fan 1 speed: RPM */
5174 #define          MC_CMD_SENSOR_FAN_1 0x14
5175 /* enum: Fan 2 speed: RPM */
5176 #define          MC_CMD_SENSOR_FAN_2 0x15
5177 /* enum: Fan 3 speed: RPM */
5178 #define          MC_CMD_SENSOR_FAN_3 0x16
5179 /* enum: Fan 4 speed: RPM */
5180 #define          MC_CMD_SENSOR_FAN_4 0x17
5181 /* enum: AOE FPGA input power: mV */
5182 #define          MC_CMD_SENSOR_IN_VAOE 0x18
5183 /* enum: AOE FPGA current: mA */
5184 #define          MC_CMD_SENSOR_OUT_IAOE 0x19
5185 /* enum: AOE FPGA input current: mA */
5186 #define          MC_CMD_SENSOR_IN_IAOE 0x1a
5187 /* enum: NIC power consumption: W */
5188 #define          MC_CMD_SENSOR_NIC_POWER 0x1b
5189 /* enum: 0.9v power voltage: mV */
5190 #define          MC_CMD_SENSOR_IN_0V9 0x1c
5191 /* enum: 0.9v power current: mA */
5192 #define          MC_CMD_SENSOR_IN_I0V9 0x1d
5193 /* enum: 1.2v power current: mA */
5194 #define          MC_CMD_SENSOR_IN_I1V2 0x1e
5195 /* enum: Not a sensor: reserved for the next page flag */
5196 #define          MC_CMD_SENSOR_PAGE0_NEXT 0x1f
5197 /* enum: 0.9v power voltage (at ADC): mV */
5198 #define          MC_CMD_SENSOR_IN_0V9_ADC 0x20
5199 /* enum: Controller temperature 2: degC */
5200 #define          MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
5201 /* enum: Voltage regulator internal temperature: degC */
5202 #define          MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
5203 /* enum: 0.9V voltage regulator temperature: degC */
5204 #define          MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
5205 /* enum: 1.2V voltage regulator temperature: degC */
5206 #define          MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
5207 /* enum: controller internal temperature sensor voltage (internal ADC): mV */
5208 #define          MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
5209 /* enum: controller internal temperature (internal ADC): degC */
5210 #define          MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
5211 /* enum: controller internal temperature sensor voltage (external ADC): mV */
5212 #define          MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
5213 /* enum: controller internal temperature (external ADC): degC */
5214 #define          MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
5215 /* enum: ambient temperature: degC */
5216 #define          MC_CMD_SENSOR_AMBIENT_TEMP 0x29
5217 /* enum: air flow: bool */
5218 #define          MC_CMD_SENSOR_AIRFLOW 0x2a
5219 /* enum: voltage between VSS08D and VSS08D at CSR: mV */
5220 #define          MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
5221 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */
5222 #define          MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
5223 /* enum: Hotpoint temperature: degC */
5224 #define          MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d
5225 /* enum: Port 0 PHY power switch over-current: bool */
5226 #define          MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e
5227 /* enum: Port 1 PHY power switch over-current: bool */
5228 #define          MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f
5229 /* enum: Mop-up microcontroller reference voltage: mV */
5230 #define          MC_CMD_SENSOR_MUM_VCC 0x30
5231 /* enum: 0.9v power phase A voltage: mV */
5232 #define          MC_CMD_SENSOR_IN_0V9_A 0x31
5233 /* enum: 0.9v power phase A current: mA */
5234 #define          MC_CMD_SENSOR_IN_I0V9_A 0x32
5235 /* enum: 0.9V voltage regulator phase A temperature: degC */
5236 #define          MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33
5237 /* enum: 0.9v power phase B voltage: mV */
5238 #define          MC_CMD_SENSOR_IN_0V9_B 0x34
5239 /* enum: 0.9v power phase B current: mA */
5240 #define          MC_CMD_SENSOR_IN_I0V9_B 0x35
5241 /* enum: 0.9V voltage regulator phase B temperature: degC */
5242 #define          MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36
5243 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */
5244 #define          MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37
5245 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */
5246 #define          MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38
5247 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */
5248 #define          MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39
5249 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */
5250 #define          MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a
5251 /* enum: CCOM RTS temperature: degC */
5252 #define          MC_CMD_SENSOR_CONTROLLER_RTS 0x3b
5253 /* enum: Not a sensor: reserved for the next page flag */
5254 #define          MC_CMD_SENSOR_PAGE1_NEXT 0x3f
5255 /* enum: controller internal temperature sensor voltage on master core
5256  * (internal ADC): mV
5257  */
5258 #define          MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40
5259 /* enum: controller internal temperature on master core (internal ADC): degC */
5260 #define          MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41
5261 /* enum: controller internal temperature sensor voltage on master core
5262  * (external ADC): mV
5263  */
5264 #define          MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42
5265 /* enum: controller internal temperature on master core (external ADC): degC */
5266 #define          MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43
5267 /* enum: controller internal temperature on slave core sensor voltage (internal
5268  * ADC): mV
5269  */
5270 #define          MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44
5271 /* enum: controller internal temperature on slave core (internal ADC): degC */
5272 #define          MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45
5273 /* enum: controller internal temperature on slave core sensor voltage (external
5274  * ADC): mV
5275  */
5276 #define          MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46
5277 /* enum: controller internal temperature on slave core (external ADC): degC */
5278 #define          MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47
5279 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */
5280 #define          MC_CMD_SENSOR_SODIMM_VOUT 0x49
5281 /* enum: Temperature of SODIMM 0 (if installed): degC */
5282 #define          MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a
5283 /* enum: Temperature of SODIMM 1 (if installed): degC */
5284 #define          MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b
5285 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */
5286 #define          MC_CMD_SENSOR_PHY0_VCC 0x4c
5287 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */
5288 #define          MC_CMD_SENSOR_PHY1_VCC 0x4d
5289 /* enum: Controller die temperature (TDIODE): degC */
5290 #define          MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e
5291 /* enum: Board temperature (front): degC */
5292 #define          MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f
5293 /* enum: Board temperature (back): degC */
5294 #define          MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50
5295 /* enum: 1.8v power current: mA */
5296 #define          MC_CMD_SENSOR_IN_I1V8 0x51
5297 /* enum: 2.5v power current: mA */
5298 #define          MC_CMD_SENSOR_IN_I2V5 0x52
5299 /* enum: 3.3v power current: mA */
5300 #define          MC_CMD_SENSOR_IN_I3V3 0x53
5301 /* enum: 12v power current: mA */
5302 #define          MC_CMD_SENSOR_IN_I12V0 0x54
5303 /* enum: 1.3v power: mV */
5304 #define          MC_CMD_SENSOR_IN_1V3 0x55
5305 /* enum: 1.3v power current: mA */
5306 #define          MC_CMD_SENSOR_IN_I1V3 0x56
5307 /* enum: Not a sensor: reserved for the next page flag */
5308 #define          MC_CMD_SENSOR_PAGE2_NEXT 0x5f
5309 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
5310 #define       MC_CMD_SENSOR_ENTRY_OFST 4
5311 #define       MC_CMD_SENSOR_ENTRY_LEN 8
5312 #define       MC_CMD_SENSOR_ENTRY_LO_OFST 4
5313 #define       MC_CMD_SENSOR_ENTRY_HI_OFST 8
5314 #define       MC_CMD_SENSOR_ENTRY_MINNUM 0
5315 #define       MC_CMD_SENSOR_ENTRY_MAXNUM 31
5316 
5317 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */
5318 #define    MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4
5319 #define    MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252
5320 #define    MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
5321 #define       MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
5322 #define       MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4
5323 /*            Enum values, see field(s): */
5324 /*               MC_CMD_SENSOR_INFO_OUT */
5325 #define        MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31
5326 #define        MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1
5327 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
5328 /*            MC_CMD_SENSOR_ENTRY_OFST 4 */
5329 /*            MC_CMD_SENSOR_ENTRY_LEN 8 */
5330 /*            MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
5331 /*            MC_CMD_SENSOR_ENTRY_HI_OFST 8 */
5332 /*            MC_CMD_SENSOR_ENTRY_MINNUM 0 */
5333 /*            MC_CMD_SENSOR_ENTRY_MAXNUM 31 */
5334 
5335 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */
5336 #define    MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8
5337 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
5338 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2
5339 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
5340 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16
5341 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2
5342 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2
5343 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16
5344 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16
5345 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
5346 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2
5347 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32
5348 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16
5349 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6
5350 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2
5351 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48
5352 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16
5353 
5354 
5355 /***********************************/
5356 /* MC_CMD_READ_SENSORS
5357  * Returns the current reading from each sensor. DMAs an array of sensor
5358  * readings, in order of sensor type (but without gaps for unimplemented
5359  * sensors), into host memory. Each array element is a
5360  * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword.
5361  *
5362  * If the request does not contain the LENGTH field then only sensors 0 to 30
5363  * are reported, to avoid DMA buffer overflow in older host software. If the
5364  * sensor reading require more space than the LENGTH allows, then return
5365  * EINVAL.
5366  *
5367  * The MC will send a SENSOREVT event every time any sensor changes state. The
5368  * driver is responsible for ensuring that it doesn't miss any events. The
5369  * board will function normally if all sensors are in STATE_OK or
5370  * STATE_WARNING. Otherwise the board should not be expected to function.
5371  */
5372 #define MC_CMD_READ_SENSORS 0x42
5373 
5374 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5375 
5376 /* MC_CMD_READ_SENSORS_IN msgrequest */
5377 #define    MC_CMD_READ_SENSORS_IN_LEN 8
5378 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */
5379 #define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
5380 #define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
5381 #define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
5382 #define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
5383 
5384 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */
5385 #define    MC_CMD_READ_SENSORS_EXT_IN_LEN 12
5386 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */
5387 #define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
5388 #define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8
5389 #define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
5390 #define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
5391 /* Size in bytes of host buffer. */
5392 #define       MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8
5393 #define       MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4
5394 
5395 /* MC_CMD_READ_SENSORS_OUT msgresponse */
5396 #define    MC_CMD_READ_SENSORS_OUT_LEN 0
5397 
5398 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */
5399 #define    MC_CMD_READ_SENSORS_EXT_OUT_LEN 0
5400 
5401 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */
5402 #define    MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4
5403 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
5404 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2
5405 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
5406 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16
5407 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2
5408 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1
5409 /* enum: Ok. */
5410 #define          MC_CMD_SENSOR_STATE_OK 0x0
5411 /* enum: Breached warning threshold. */
5412 #define          MC_CMD_SENSOR_STATE_WARNING 0x1
5413 /* enum: Breached fatal threshold. */
5414 #define          MC_CMD_SENSOR_STATE_FATAL 0x2
5415 /* enum: Fault with sensor. */
5416 #define          MC_CMD_SENSOR_STATE_BROKEN 0x3
5417 /* enum: Sensor is working but does not currently have a reading. */
5418 #define          MC_CMD_SENSOR_STATE_NO_READING 0x4
5419 /* enum: Sensor initialisation failed. */
5420 #define          MC_CMD_SENSOR_STATE_INIT_FAILED 0x5
5421 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16
5422 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8
5423 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3
5424 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1
5425 /*            Enum values, see field(s): */
5426 /*               MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
5427 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24
5428 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8
5429 
5430 
5431 /***********************************/
5432 /* MC_CMD_GET_PHY_STATE
5433  * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot
5434  * (e.g. due to missing or corrupted firmware). Locks required: None. Return
5435  * code: 0
5436  */
5437 #define MC_CMD_GET_PHY_STATE 0x43
5438 
5439 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5440 
5441 /* MC_CMD_GET_PHY_STATE_IN msgrequest */
5442 #define    MC_CMD_GET_PHY_STATE_IN_LEN 0
5443 
5444 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */
5445 #define    MC_CMD_GET_PHY_STATE_OUT_LEN 4
5446 #define       MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
5447 #define       MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4
5448 /* enum: Ok. */
5449 #define          MC_CMD_PHY_STATE_OK 0x1
5450 /* enum: Faulty. */
5451 #define          MC_CMD_PHY_STATE_ZOMBIE 0x2
5452 
5453 
5454 /***********************************/
5455 /* MC_CMD_SETUP_8021QBB
5456  * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to
5457  * disable 802.Qbb for a given priority.
5458  */
5459 #define MC_CMD_SETUP_8021QBB 0x44
5460 
5461 /* MC_CMD_SETUP_8021QBB_IN msgrequest */
5462 #define    MC_CMD_SETUP_8021QBB_IN_LEN 32
5463 #define       MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0
5464 #define       MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32
5465 
5466 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */
5467 #define    MC_CMD_SETUP_8021QBB_OUT_LEN 0
5468 
5469 
5470 /***********************************/
5471 /* MC_CMD_WOL_FILTER_GET
5472  * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
5473  */
5474 #define MC_CMD_WOL_FILTER_GET 0x45
5475 
5476 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK
5477 
5478 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */
5479 #define    MC_CMD_WOL_FILTER_GET_IN_LEN 0
5480 
5481 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */
5482 #define    MC_CMD_WOL_FILTER_GET_OUT_LEN 4
5483 #define       MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
5484 #define       MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4
5485 
5486 
5487 /***********************************/
5488 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD
5489  * Add a protocol offload to NIC for lights-out state. Locks required: None.
5490  * Returns: 0, ENOSYS
5491  */
5492 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
5493 
5494 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK
5495 
5496 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */
5497 #define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8
5498 #define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252
5499 #define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
5500 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
5501 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
5502 #define          MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
5503 #define          MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
5504 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
5505 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
5506 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1
5507 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62
5508 
5509 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */
5510 #define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14
5511 /*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
5512 /*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
5513 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4
5514 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6
5515 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10
5516 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4
5517 
5518 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */
5519 #define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42
5520 /*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
5521 /*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
5522 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4
5523 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6
5524 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10
5525 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16
5526 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26
5527 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16
5528 
5529 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */
5530 #define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
5531 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
5532 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4
5533 
5534 
5535 /***********************************/
5536 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD
5537  * Remove a protocol offload from NIC for lights-out state. Locks required:
5538  * None. Returns: 0, ENOSYS
5539  */
5540 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
5541 
5542 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK
5543 
5544 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */
5545 #define    MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8
5546 #define       MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
5547 #define       MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
5548 #define       MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
5549 #define       MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4
5550 
5551 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */
5552 #define    MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0
5553 
5554 
5555 /***********************************/
5556 /* MC_CMD_MAC_RESET_RESTORE
5557  * Restore MAC after block reset. Locks required: None. Returns: 0.
5558  */
5559 #define MC_CMD_MAC_RESET_RESTORE 0x48
5560 
5561 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */
5562 #define    MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
5563 
5564 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */
5565 #define    MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0
5566 
5567 
5568 /***********************************/
5569 /* MC_CMD_TESTASSERT
5570  * Deliberately trigger an assert-detonation in the firmware for testing
5571  * purposes (i.e. to allow tests that the driver copes gracefully). Locks
5572  * required: None Returns: 0
5573  */
5574 #define MC_CMD_TESTASSERT 0x49
5575 
5576 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5577 
5578 /* MC_CMD_TESTASSERT_IN msgrequest */
5579 #define    MC_CMD_TESTASSERT_IN_LEN 0
5580 
5581 /* MC_CMD_TESTASSERT_OUT msgresponse */
5582 #define    MC_CMD_TESTASSERT_OUT_LEN 0
5583 
5584 /* MC_CMD_TESTASSERT_V2_IN msgrequest */
5585 #define    MC_CMD_TESTASSERT_V2_IN_LEN 4
5586 /* How to provoke the assertion */
5587 #define       MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0
5588 #define       MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4
5589 /* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless
5590  * you're testing firmware, this is what you want.
5591  */
5592 #define          MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0
5593 /* enum: Assert using assert(0); */
5594 #define          MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1
5595 /* enum: Deliberately trigger a watchdog */
5596 #define          MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2
5597 /* enum: Deliberately trigger a trap by loading from an invalid address */
5598 #define          MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3
5599 /* enum: Deliberately trigger a trap by storing to an invalid address */
5600 #define          MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4
5601 /* enum: Jump to an invalid address */
5602 #define          MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5
5603 
5604 /* MC_CMD_TESTASSERT_V2_OUT msgresponse */
5605 #define    MC_CMD_TESTASSERT_V2_OUT_LEN 0
5606 
5607 
5608 /***********************************/
5609 /* MC_CMD_WORKAROUND
5610  * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't
5611  * understand the given workaround number - which should not be treated as a
5612  * hard error by client code. This op does not imply any semantics about each
5613  * workaround, that's between the driver and the mcfw on a per-workaround
5614  * basis. Locks required: None. Returns: 0, EINVAL .
5615  */
5616 #define MC_CMD_WORKAROUND 0x4a
5617 
5618 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5619 
5620 /* MC_CMD_WORKAROUND_IN msgrequest */
5621 #define    MC_CMD_WORKAROUND_IN_LEN 8
5622 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */
5623 #define       MC_CMD_WORKAROUND_IN_TYPE_OFST 0
5624 #define       MC_CMD_WORKAROUND_IN_TYPE_LEN 4
5625 /* enum: Bug 17230 work around. */
5626 #define          MC_CMD_WORKAROUND_BUG17230 0x1
5627 /* enum: Bug 35388 work around (unsafe EVQ writes). */
5628 #define          MC_CMD_WORKAROUND_BUG35388 0x2
5629 /* enum: Bug35017 workaround (A64 tables must be identity map) */
5630 #define          MC_CMD_WORKAROUND_BUG35017 0x3
5631 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
5632 #define          MC_CMD_WORKAROUND_BUG41750 0x4
5633 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
5634  * - before adding code that queries this workaround, remember that there's
5635  * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
5636  * and will hence (incorrectly) report that the bug doesn't exist.
5637  */
5638 #define          MC_CMD_WORKAROUND_BUG42008 0x5
5639 /* enum: Bug 26807 features present in firmware (multicast filter chaining)
5640  * This feature cannot be turned on/off while there are any filters already
5641  * present. The behaviour in such case depends on the acting client's privilege
5642  * level. If the client has the admin privilege, then all functions that have
5643  * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise
5644  * the command will fail with MC_CMD_ERR_FILTERS_PRESENT.
5645  */
5646 #define          MC_CMD_WORKAROUND_BUG26807 0x6
5647 /* enum: Bug 61265 work around (broken EVQ TMR writes). */
5648 #define          MC_CMD_WORKAROUND_BUG61265 0x7
5649 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable
5650  * the workaround
5651  */
5652 #define       MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
5653 #define       MC_CMD_WORKAROUND_IN_ENABLED_LEN 4
5654 
5655 /* MC_CMD_WORKAROUND_OUT msgresponse */
5656 #define    MC_CMD_WORKAROUND_OUT_LEN 0
5657 
5658 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used
5659  * when (TYPE == MC_CMD_WORKAROUND_BUG26807)
5660  */
5661 #define    MC_CMD_WORKAROUND_EXT_OUT_LEN 4
5662 #define       MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0
5663 #define       MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4
5664 #define        MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0
5665 #define        MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1
5666 
5667 
5668 /***********************************/
5669 /* MC_CMD_GET_PHY_MEDIA_INFO
5670  * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for
5671  * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG
5672  * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the
5673  * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1
5674  * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
5675  * Anything else: currently undefined. Locks required: None. Return code: 0.
5676  */
5677 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
5678 
5679 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5680 
5681 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */
5682 #define    MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
5683 #define       MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
5684 #define       MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4
5685 
5686 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */
5687 #define    MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5
5688 #define    MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252
5689 #define    MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
5690 /* in bytes */
5691 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
5692 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4
5693 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
5694 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1
5695 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1
5696 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248
5697 
5698 
5699 /***********************************/
5700 /* MC_CMD_NVRAM_TEST
5701  * Test a particular NVRAM partition for valid contents (where "valid" depends
5702  * on the type of partition).
5703  */
5704 #define MC_CMD_NVRAM_TEST 0x4c
5705 
5706 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5707 
5708 /* MC_CMD_NVRAM_TEST_IN msgrequest */
5709 #define    MC_CMD_NVRAM_TEST_IN_LEN 4
5710 #define       MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
5711 #define       MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4
5712 /*            Enum values, see field(s): */
5713 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
5714 
5715 /* MC_CMD_NVRAM_TEST_OUT msgresponse */
5716 #define    MC_CMD_NVRAM_TEST_OUT_LEN 4
5717 #define       MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
5718 #define       MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4
5719 /* enum: Passed. */
5720 #define          MC_CMD_NVRAM_TEST_PASS 0x0
5721 /* enum: Failed. */
5722 #define          MC_CMD_NVRAM_TEST_FAIL 0x1
5723 /* enum: Not supported. */
5724 #define          MC_CMD_NVRAM_TEST_NOTSUPP 0x2
5725 
5726 
5727 /***********************************/
5728 /* MC_CMD_MRSFP_TWEAK
5729  * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds.
5730  * I2C I/O expander bits are always read; if equaliser parameters are supplied,
5731  * they are configured first. Locks required: None. Return code: 0, EINVAL.
5732  */
5733 #define MC_CMD_MRSFP_TWEAK 0x4d
5734 
5735 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */
5736 #define    MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16
5737 /* 0-6 low->high de-emph. */
5738 #define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0
5739 #define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4
5740 /* 0-8 low->high ref.V */
5741 #define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4
5742 #define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4
5743 /* 0-8 0-8 low->high boost */
5744 #define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8
5745 #define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4
5746 /* 0-8 low->high ref.V */
5747 #define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12
5748 #define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4
5749 
5750 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */
5751 #define    MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0
5752 
5753 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */
5754 #define    MC_CMD_MRSFP_TWEAK_OUT_LEN 12
5755 /* input bits */
5756 #define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0
5757 #define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4
5758 /* output bits */
5759 #define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4
5760 #define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4
5761 /* direction */
5762 #define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8
5763 #define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4
5764 /* enum: Out. */
5765 #define          MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0
5766 /* enum: In. */
5767 #define          MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1
5768 
5769 
5770 /***********************************/
5771 /* MC_CMD_SENSOR_SET_LIMS
5772  * Adjusts the sensor limits. This is a warranty-voiding operation. Returns:
5773  * ENOENT if the sensor specified does not exist, EINVAL if the limits are out
5774  * of range.
5775  */
5776 #define MC_CMD_SENSOR_SET_LIMS 0x4e
5777 
5778 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE
5779 
5780 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */
5781 #define    MC_CMD_SENSOR_SET_LIMS_IN_LEN 20
5782 #define       MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
5783 #define       MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4
5784 /*            Enum values, see field(s): */
5785 /*               MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
5786 /* interpretation is is sensor-specific. */
5787 #define       MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
5788 #define       MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4
5789 /* interpretation is is sensor-specific. */
5790 #define       MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8
5791 #define       MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4
5792 /* interpretation is is sensor-specific. */
5793 #define       MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12
5794 #define       MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4
5795 /* interpretation is is sensor-specific. */
5796 #define       MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16
5797 #define       MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4
5798 
5799 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */
5800 #define    MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0
5801 
5802 
5803 /***********************************/
5804 /* MC_CMD_GET_RESOURCE_LIMITS
5805  */
5806 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f
5807 
5808 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
5809 #define    MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
5810 
5811 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */
5812 #define    MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16
5813 #define       MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
5814 #define       MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4
5815 #define       MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4
5816 #define       MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4
5817 #define       MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8
5818 #define       MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4
5819 #define       MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12
5820 #define       MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4
5821 
5822 
5823 /***********************************/
5824 /* MC_CMD_NVRAM_PARTITIONS
5825  * Reads the list of available virtual NVRAM partition types. Locks required:
5826  * none. Returns: 0, EINVAL (bad type).
5827  */
5828 #define MC_CMD_NVRAM_PARTITIONS 0x51
5829 
5830 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5831 
5832 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */
5833 #define    MC_CMD_NVRAM_PARTITIONS_IN_LEN 0
5834 
5835 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */
5836 #define    MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4
5837 #define    MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252
5838 #define    MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
5839 /* total number of partitions */
5840 #define       MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
5841 #define       MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4
5842 /* type ID code for each of NUM_PARTITIONS partitions */
5843 #define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4
5844 #define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4
5845 #define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0
5846 #define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62
5847 
5848 
5849 /***********************************/
5850 /* MC_CMD_NVRAM_METADATA
5851  * Reads soft metadata for a virtual NVRAM partition type. Locks required:
5852  * none. Returns: 0, EINVAL (bad type).
5853  */
5854 #define MC_CMD_NVRAM_METADATA 0x52
5855 
5856 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5857 
5858 /* MC_CMD_NVRAM_METADATA_IN msgrequest */
5859 #define    MC_CMD_NVRAM_METADATA_IN_LEN 4
5860 /* Partition type ID code */
5861 #define       MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0
5862 #define       MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4
5863 
5864 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */
5865 #define    MC_CMD_NVRAM_METADATA_OUT_LENMIN 20
5866 #define    MC_CMD_NVRAM_METADATA_OUT_LENMAX 252
5867 #define    MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))
5868 /* Partition type ID code */
5869 #define       MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
5870 #define       MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4
5871 #define       MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4
5872 #define       MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4
5873 #define        MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0
5874 #define        MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1
5875 #define        MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1
5876 #define        MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1
5877 #define        MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2
5878 #define        MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1
5879 /* Subtype ID code for content of this partition */
5880 #define       MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8
5881 #define       MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4
5882 /* 1st component of W.X.Y.Z version number for content of this partition */
5883 #define       MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12
5884 #define       MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2
5885 /* 2nd component of W.X.Y.Z version number for content of this partition */
5886 #define       MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14
5887 #define       MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2
5888 /* 3rd component of W.X.Y.Z version number for content of this partition */
5889 #define       MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16
5890 #define       MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2
5891 /* 4th component of W.X.Y.Z version number for content of this partition */
5892 #define       MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18
5893 #define       MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2
5894 /* Zero-terminated string describing the content of this partition */
5895 #define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20
5896 #define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1
5897 #define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0
5898 #define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232
5899 
5900 
5901 /***********************************/
5902 /* MC_CMD_GET_MAC_ADDRESSES
5903  * Returns the base MAC, count and stride for the requesting function
5904  */
5905 #define MC_CMD_GET_MAC_ADDRESSES 0x55
5906 
5907 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5908 
5909 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */
5910 #define    MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0
5911 
5912 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */
5913 #define    MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16
5914 /* Base MAC address */
5915 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0
5916 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6
5917 /* Padding */
5918 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6
5919 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2
5920 /* Number of allocated MAC addresses */
5921 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8
5922 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4
5923 /* Spacing of allocated MAC addresses */
5924 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12
5925 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4
5926 
5927 
5928 /***********************************/
5929 /* MC_CMD_CLP
5930  * Perform a CLP related operation
5931  */
5932 #define MC_CMD_CLP 0x56
5933 
5934 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5935 
5936 /* MC_CMD_CLP_IN msgrequest */
5937 #define    MC_CMD_CLP_IN_LEN 4
5938 /* Sub operation */
5939 #define       MC_CMD_CLP_IN_OP_OFST 0
5940 #define       MC_CMD_CLP_IN_OP_LEN 4
5941 /* enum: Return to factory default settings */
5942 #define          MC_CMD_CLP_OP_DEFAULT 0x1
5943 /* enum: Set MAC address */
5944 #define          MC_CMD_CLP_OP_SET_MAC 0x2
5945 /* enum: Get MAC address */
5946 #define          MC_CMD_CLP_OP_GET_MAC 0x3
5947 /* enum: Set UEFI/GPXE boot mode */
5948 #define          MC_CMD_CLP_OP_SET_BOOT 0x4
5949 /* enum: Get UEFI/GPXE boot mode */
5950 #define          MC_CMD_CLP_OP_GET_BOOT 0x5
5951 
5952 /* MC_CMD_CLP_OUT msgresponse */
5953 #define    MC_CMD_CLP_OUT_LEN 0
5954 
5955 /* MC_CMD_CLP_IN_DEFAULT msgrequest */
5956 #define    MC_CMD_CLP_IN_DEFAULT_LEN 4
5957 /*            MC_CMD_CLP_IN_OP_OFST 0 */
5958 /*            MC_CMD_CLP_IN_OP_LEN 4 */
5959 
5960 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */
5961 #define    MC_CMD_CLP_OUT_DEFAULT_LEN 0
5962 
5963 /* MC_CMD_CLP_IN_SET_MAC msgrequest */
5964 #define    MC_CMD_CLP_IN_SET_MAC_LEN 12
5965 /*            MC_CMD_CLP_IN_OP_OFST 0 */
5966 /*            MC_CMD_CLP_IN_OP_LEN 4 */
5967 /* MAC address assigned to port */
5968 #define       MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4
5969 #define       MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6
5970 /* Padding */
5971 #define       MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10
5972 #define       MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2
5973 
5974 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */
5975 #define    MC_CMD_CLP_OUT_SET_MAC_LEN 0
5976 
5977 /* MC_CMD_CLP_IN_GET_MAC msgrequest */
5978 #define    MC_CMD_CLP_IN_GET_MAC_LEN 4
5979 /*            MC_CMD_CLP_IN_OP_OFST 0 */
5980 /*            MC_CMD_CLP_IN_OP_LEN 4 */
5981 
5982 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */
5983 #define    MC_CMD_CLP_OUT_GET_MAC_LEN 8
5984 /* MAC address assigned to port */
5985 #define       MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0
5986 #define       MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6
5987 /* Padding */
5988 #define       MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6
5989 #define       MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2
5990 
5991 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */
5992 #define    MC_CMD_CLP_IN_SET_BOOT_LEN 5
5993 /*            MC_CMD_CLP_IN_OP_OFST 0 */
5994 /*            MC_CMD_CLP_IN_OP_LEN 4 */
5995 /* Boot flag */
5996 #define       MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4
5997 #define       MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1
5998 
5999 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */
6000 #define    MC_CMD_CLP_OUT_SET_BOOT_LEN 0
6001 
6002 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */
6003 #define    MC_CMD_CLP_IN_GET_BOOT_LEN 4
6004 /*            MC_CMD_CLP_IN_OP_OFST 0 */
6005 /*            MC_CMD_CLP_IN_OP_LEN 4 */
6006 
6007 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */
6008 #define    MC_CMD_CLP_OUT_GET_BOOT_LEN 4
6009 /* Boot flag */
6010 #define       MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0
6011 #define       MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1
6012 /* Padding */
6013 #define       MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1
6014 #define       MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3
6015 
6016 
6017 /***********************************/
6018 /* MC_CMD_MUM
6019  * Perform a MUM operation
6020  */
6021 #define MC_CMD_MUM 0x57
6022 
6023 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE
6024 
6025 /* MC_CMD_MUM_IN msgrequest */
6026 #define    MC_CMD_MUM_IN_LEN 4
6027 #define       MC_CMD_MUM_IN_OP_HDR_OFST 0
6028 #define       MC_CMD_MUM_IN_OP_HDR_LEN 4
6029 #define        MC_CMD_MUM_IN_OP_LBN 0
6030 #define        MC_CMD_MUM_IN_OP_WIDTH 8
6031 /* enum: NULL MCDI command to MUM */
6032 #define          MC_CMD_MUM_OP_NULL 0x1
6033 /* enum: Get MUM version */
6034 #define          MC_CMD_MUM_OP_GET_VERSION 0x2
6035 /* enum: Issue raw I2C command to MUM */
6036 #define          MC_CMD_MUM_OP_RAW_CMD 0x3
6037 /* enum: Read from registers on devices connected to MUM. */
6038 #define          MC_CMD_MUM_OP_READ 0x4
6039 /* enum: Write to registers on devices connected to MUM. */
6040 #define          MC_CMD_MUM_OP_WRITE 0x5
6041 /* enum: Control UART logging. */
6042 #define          MC_CMD_MUM_OP_LOG 0x6
6043 /* enum: Operations on MUM GPIO lines */
6044 #define          MC_CMD_MUM_OP_GPIO 0x7
6045 /* enum: Get sensor readings from MUM */
6046 #define          MC_CMD_MUM_OP_READ_SENSORS 0x8
6047 /* enum: Initiate clock programming on the MUM */
6048 #define          MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9
6049 /* enum: Initiate FPGA load from flash on the MUM */
6050 #define          MC_CMD_MUM_OP_FPGA_LOAD 0xa
6051 /* enum: Request sensor reading from MUM ADC resulting from earlier request via
6052  * MUM ATB
6053  */
6054 #define          MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb
6055 /* enum: Send commands relating to the QSFP ports via the MUM for PHY
6056  * operations
6057  */
6058 #define          MC_CMD_MUM_OP_QSFP 0xc
6059 /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage
6060  * level) from MUM
6061  */
6062 #define          MC_CMD_MUM_OP_READ_DDR_INFO 0xd
6063 
6064 /* MC_CMD_MUM_IN_NULL msgrequest */
6065 #define    MC_CMD_MUM_IN_NULL_LEN 4
6066 /* MUM cmd header */
6067 #define       MC_CMD_MUM_IN_CMD_OFST 0
6068 #define       MC_CMD_MUM_IN_CMD_LEN 4
6069 
6070 /* MC_CMD_MUM_IN_GET_VERSION msgrequest */
6071 #define    MC_CMD_MUM_IN_GET_VERSION_LEN 4
6072 /* MUM cmd header */
6073 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6074 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6075 
6076 /* MC_CMD_MUM_IN_READ msgrequest */
6077 #define    MC_CMD_MUM_IN_READ_LEN 16
6078 /* MUM cmd header */
6079 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6080 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6081 /* ID of (device connected to MUM) to read from registers of */
6082 #define       MC_CMD_MUM_IN_READ_DEVICE_OFST 4
6083 #define       MC_CMD_MUM_IN_READ_DEVICE_LEN 4
6084 /* enum: Hittite HMC1035 clock generator on Sorrento board */
6085 #define          MC_CMD_MUM_DEV_HITTITE 0x1
6086 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */
6087 #define          MC_CMD_MUM_DEV_HITTITE_NIC 0x2
6088 /* 32-bit address to read from */
6089 #define       MC_CMD_MUM_IN_READ_ADDR_OFST 8
6090 #define       MC_CMD_MUM_IN_READ_ADDR_LEN 4
6091 /* Number of words to read. */
6092 #define       MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12
6093 #define       MC_CMD_MUM_IN_READ_NUMWORDS_LEN 4
6094 
6095 /* MC_CMD_MUM_IN_WRITE msgrequest */
6096 #define    MC_CMD_MUM_IN_WRITE_LENMIN 16
6097 #define    MC_CMD_MUM_IN_WRITE_LENMAX 252
6098 #define    MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))
6099 /* MUM cmd header */
6100 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6101 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6102 /* ID of (device connected to MUM) to write to registers of */
6103 #define       MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4
6104 #define       MC_CMD_MUM_IN_WRITE_DEVICE_LEN 4
6105 /* enum: Hittite HMC1035 clock generator on Sorrento board */
6106 /*               MC_CMD_MUM_DEV_HITTITE 0x1 */
6107 /* 32-bit address to write to */
6108 #define       MC_CMD_MUM_IN_WRITE_ADDR_OFST 8
6109 #define       MC_CMD_MUM_IN_WRITE_ADDR_LEN 4
6110 /* Words to write */
6111 #define       MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12
6112 #define       MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4
6113 #define       MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1
6114 #define       MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60
6115 
6116 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */
6117 #define    MC_CMD_MUM_IN_RAW_CMD_LENMIN 17
6118 #define    MC_CMD_MUM_IN_RAW_CMD_LENMAX 252
6119 #define    MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num))
6120 /* MUM cmd header */
6121 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6122 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6123 /* MUM I2C cmd code */
6124 #define       MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4
6125 #define       MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4
6126 /* Number of bytes to write */
6127 #define       MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8
6128 #define       MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4
6129 /* Number of bytes to read */
6130 #define       MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12
6131 #define       MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4
6132 /* Bytes to write */
6133 #define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16
6134 #define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1
6135 #define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1
6136 #define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236
6137 
6138 /* MC_CMD_MUM_IN_LOG msgrequest */
6139 #define    MC_CMD_MUM_IN_LOG_LEN 8
6140 /* MUM cmd header */
6141 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6142 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6143 #define       MC_CMD_MUM_IN_LOG_OP_OFST 4
6144 #define       MC_CMD_MUM_IN_LOG_OP_LEN 4
6145 #define          MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */
6146 
6147 /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */
6148 #define    MC_CMD_MUM_IN_LOG_OP_UART_LEN 12
6149 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6150 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6151 /*            MC_CMD_MUM_IN_LOG_OP_OFST 4 */
6152 /*            MC_CMD_MUM_IN_LOG_OP_LEN 4 */
6153 /* Enable/disable debug output to UART */
6154 #define       MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8
6155 #define       MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4
6156 
6157 /* MC_CMD_MUM_IN_GPIO msgrequest */
6158 #define    MC_CMD_MUM_IN_GPIO_LEN 8
6159 /* MUM cmd header */
6160 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6161 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6162 #define       MC_CMD_MUM_IN_GPIO_HDR_OFST 4
6163 #define       MC_CMD_MUM_IN_GPIO_HDR_LEN 4
6164 #define        MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0
6165 #define        MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8
6166 #define          MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */
6167 #define          MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */
6168 #define          MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */
6169 #define          MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */
6170 #define          MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */
6171 #define          MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */
6172 
6173 /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */
6174 #define    MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8
6175 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6176 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6177 #define       MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4
6178 #define       MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4
6179 
6180 /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */
6181 #define    MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16
6182 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6183 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6184 #define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4
6185 #define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4
6186 /* The first 32-bit word to be written to the GPIO OUT register. */
6187 #define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8
6188 #define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4
6189 /* The second 32-bit word to be written to the GPIO OUT register. */
6190 #define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12
6191 #define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4
6192 
6193 /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */
6194 #define    MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8
6195 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6196 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6197 #define       MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4
6198 #define       MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4
6199 
6200 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */
6201 #define    MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16
6202 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6203 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6204 #define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4
6205 #define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4
6206 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */
6207 #define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8
6208 #define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4
6209 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */
6210 #define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12
6211 #define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4
6212 
6213 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */
6214 #define    MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8
6215 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6216 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6217 #define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4
6218 #define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4
6219 
6220 /* MC_CMD_MUM_IN_GPIO_OP msgrequest */
6221 #define    MC_CMD_MUM_IN_GPIO_OP_LEN 8
6222 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6223 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6224 #define       MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4
6225 #define       MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4
6226 #define        MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8
6227 #define        MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8
6228 #define          MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */
6229 #define          MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */
6230 #define          MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */
6231 #define          MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */
6232 #define        MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16
6233 #define        MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8
6234 
6235 /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */
6236 #define    MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8
6237 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6238 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6239 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4
6240 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4
6241 
6242 /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */
6243 #define    MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8
6244 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6245 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6246 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4
6247 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4
6248 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24
6249 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8
6250 
6251 /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */
6252 #define    MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8
6253 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6254 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6255 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4
6256 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4
6257 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24
6258 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8
6259 
6260 /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */
6261 #define    MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8
6262 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6263 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6264 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4
6265 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4
6266 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24
6267 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8
6268 
6269 /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */
6270 #define    MC_CMD_MUM_IN_READ_SENSORS_LEN 8
6271 /* MUM cmd header */
6272 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6273 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6274 #define       MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4
6275 #define       MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4
6276 #define        MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0
6277 #define        MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8
6278 #define        MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8
6279 #define        MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8
6280 
6281 /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */
6282 #define    MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12
6283 /* MUM cmd header */
6284 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6285 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6286 /* Bit-mask of clocks to be programmed */
6287 #define       MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4
6288 #define       MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4
6289 #define          MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */
6290 #define          MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */
6291 #define          MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */
6292 /* Control flags for clock programming */
6293 #define       MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8
6294 #define       MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4
6295 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0
6296 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1
6297 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1
6298 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1
6299 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2
6300 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1
6301 
6302 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */
6303 #define    MC_CMD_MUM_IN_FPGA_LOAD_LEN 8
6304 /* MUM cmd header */
6305 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6306 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6307 /* Enable/Disable FPGA config from flash */
6308 #define       MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4
6309 #define       MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4
6310 
6311 /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */
6312 #define    MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4
6313 /* MUM cmd header */
6314 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6315 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6316 
6317 /* MC_CMD_MUM_IN_QSFP msgrequest */
6318 #define    MC_CMD_MUM_IN_QSFP_LEN 12
6319 /* MUM cmd header */
6320 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6321 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6322 #define       MC_CMD_MUM_IN_QSFP_HDR_OFST 4
6323 #define       MC_CMD_MUM_IN_QSFP_HDR_LEN 4
6324 #define        MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0
6325 #define        MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4
6326 #define          MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */
6327 #define          MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */
6328 #define          MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */
6329 #define          MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */
6330 #define          MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */
6331 #define          MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */
6332 #define       MC_CMD_MUM_IN_QSFP_IDX_OFST 8
6333 #define       MC_CMD_MUM_IN_QSFP_IDX_LEN 4
6334 
6335 /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */
6336 #define    MC_CMD_MUM_IN_QSFP_INIT_LEN 16
6337 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6338 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6339 #define       MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4
6340 #define       MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4
6341 #define       MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8
6342 #define       MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4
6343 #define       MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12
6344 #define       MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4
6345 
6346 /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */
6347 #define    MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24
6348 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6349 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6350 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4
6351 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4
6352 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8
6353 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4
6354 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12
6355 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4
6356 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16
6357 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4
6358 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20
6359 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4
6360 
6361 /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */
6362 #define    MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12
6363 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6364 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6365 #define       MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4
6366 #define       MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4
6367 #define       MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8
6368 #define       MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4
6369 
6370 /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */
6371 #define    MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16
6372 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6373 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6374 #define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4
6375 #define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4
6376 #define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8
6377 #define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4
6378 #define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12
6379 #define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4
6380 
6381 /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */
6382 #define    MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12
6383 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6384 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6385 #define       MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4
6386 #define       MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4
6387 #define       MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8
6388 #define       MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4
6389 
6390 /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */
6391 #define    MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12
6392 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6393 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6394 #define       MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4
6395 #define       MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4
6396 #define       MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8
6397 #define       MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4
6398 
6399 /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */
6400 #define    MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4
6401 /* MUM cmd header */
6402 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6403 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6404 
6405 /* MC_CMD_MUM_OUT msgresponse */
6406 #define    MC_CMD_MUM_OUT_LEN 0
6407 
6408 /* MC_CMD_MUM_OUT_NULL msgresponse */
6409 #define    MC_CMD_MUM_OUT_NULL_LEN 0
6410 
6411 /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */
6412 #define    MC_CMD_MUM_OUT_GET_VERSION_LEN 12
6413 #define       MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0
6414 #define       MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4
6415 #define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4
6416 #define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8
6417 #define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4
6418 #define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8
6419 
6420 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */
6421 #define    MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1
6422 #define    MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252
6423 #define    MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))
6424 /* returned data */
6425 #define       MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0
6426 #define       MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1
6427 #define       MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1
6428 #define       MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252
6429 
6430 /* MC_CMD_MUM_OUT_READ msgresponse */
6431 #define    MC_CMD_MUM_OUT_READ_LENMIN 4
6432 #define    MC_CMD_MUM_OUT_READ_LENMAX 252
6433 #define    MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))
6434 #define       MC_CMD_MUM_OUT_READ_BUFFER_OFST 0
6435 #define       MC_CMD_MUM_OUT_READ_BUFFER_LEN 4
6436 #define       MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1
6437 #define       MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63
6438 
6439 /* MC_CMD_MUM_OUT_WRITE msgresponse */
6440 #define    MC_CMD_MUM_OUT_WRITE_LEN 0
6441 
6442 /* MC_CMD_MUM_OUT_LOG msgresponse */
6443 #define    MC_CMD_MUM_OUT_LOG_LEN 0
6444 
6445 /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */
6446 #define    MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0
6447 
6448 /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */
6449 #define    MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8
6450 /* The first 32-bit word read from the GPIO IN register. */
6451 #define       MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0
6452 #define       MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4
6453 /* The second 32-bit word read from the GPIO IN register. */
6454 #define       MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4
6455 #define       MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4
6456 
6457 /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */
6458 #define    MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0
6459 
6460 /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */
6461 #define    MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8
6462 /* The first 32-bit word read from the GPIO OUT register. */
6463 #define       MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0
6464 #define       MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4
6465 /* The second 32-bit word read from the GPIO OUT register. */
6466 #define       MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4
6467 #define       MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4
6468 
6469 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */
6470 #define    MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0
6471 
6472 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */
6473 #define    MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8
6474 #define       MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0
6475 #define       MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4
6476 #define       MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4
6477 #define       MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4
6478 
6479 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */
6480 #define    MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4
6481 #define       MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0
6482 #define       MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4
6483 
6484 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */
6485 #define    MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0
6486 
6487 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */
6488 #define    MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0
6489 
6490 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */
6491 #define    MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0
6492 
6493 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */
6494 #define    MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4
6495 #define    MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252
6496 #define    MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))
6497 #define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0
6498 #define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4
6499 #define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1
6500 #define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63
6501 #define        MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0
6502 #define        MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16
6503 #define        MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16
6504 #define        MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8
6505 #define        MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24
6506 #define        MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8
6507 
6508 /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */
6509 #define    MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4
6510 #define       MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0
6511 #define       MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4
6512 
6513 /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */
6514 #define    MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0
6515 
6516 /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */
6517 #define    MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4
6518 #define       MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0
6519 #define       MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4
6520 
6521 /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */
6522 #define    MC_CMD_MUM_OUT_QSFP_INIT_LEN 0
6523 
6524 /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */
6525 #define    MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8
6526 #define       MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0
6527 #define       MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4
6528 #define       MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4
6529 #define       MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4
6530 #define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0
6531 #define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1
6532 #define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1
6533 #define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1
6534 
6535 /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */
6536 #define    MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4
6537 #define       MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0
6538 #define       MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4
6539 
6540 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */
6541 #define    MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5
6542 #define    MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252
6543 #define    MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))
6544 /* in bytes */
6545 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0
6546 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4
6547 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4
6548 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1
6549 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1
6550 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248
6551 
6552 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */
6553 #define    MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8
6554 #define       MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0
6555 #define       MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4
6556 #define       MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4
6557 #define       MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4
6558 
6559 /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */
6560 #define    MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4
6561 #define       MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0
6562 #define       MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4
6563 
6564 /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */
6565 #define    MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24
6566 #define    MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248
6567 #define    MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num))
6568 /* Discrete (soldered) DDR resistor strap info */
6569 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0
6570 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4
6571 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0
6572 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16
6573 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16
6574 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16
6575 /* Number of SODIMM info records */
6576 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4
6577 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4
6578 /* Array of SODIMM info records */
6579 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8
6580 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8
6581 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8
6582 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12
6583 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2
6584 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30
6585 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0
6586 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8
6587 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */
6588 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0
6589 /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */
6590 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1
6591 /* enum: Total number of SODIMM banks */
6592 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2
6593 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8
6594 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8
6595 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16
6596 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4
6597 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20
6598 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4
6599 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */
6600 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */
6601 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */
6602 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */
6603 /* enum: Values 5-15 are reserved for future usage */
6604 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4
6605 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24
6606 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8
6607 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32
6608 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16
6609 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48
6610 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4
6611 /* enum: No module present */
6612 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0
6613 /* enum: Module present supported and powered on */
6614 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1
6615 /* enum: Module present but bad type */
6616 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2
6617 /* enum: Module present but incompatible voltage */
6618 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3
6619 /* enum: Module present but unknown SPD */
6620 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4
6621 /* enum: Module present but slot cannot support it */
6622 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5
6623 /* enum: Modules may or may not be present, but cannot establish contact by I2C
6624  */
6625 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6
6626 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52
6627 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12
6628 
6629 /* MC_CMD_RESOURCE_SPECIFIER enum */
6630 /* enum: Any */
6631 #define          MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
6632 /* enum: None */
6633 #define          MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe
6634 
6635 /* EVB_PORT_ID structuredef */
6636 #define    EVB_PORT_ID_LEN 4
6637 #define       EVB_PORT_ID_PORT_ID_OFST 0
6638 #define       EVB_PORT_ID_PORT_ID_LEN 4
6639 /* enum: An invalid port handle. */
6640 #define          EVB_PORT_ID_NULL 0x0
6641 /* enum: The port assigned to this function.. */
6642 #define          EVB_PORT_ID_ASSIGNED 0x1000000
6643 /* enum: External network port 0 */
6644 #define          EVB_PORT_ID_MAC0 0x2000000
6645 /* enum: External network port 1 */
6646 #define          EVB_PORT_ID_MAC1 0x2000001
6647 /* enum: External network port 2 */
6648 #define          EVB_PORT_ID_MAC2 0x2000002
6649 /* enum: External network port 3 */
6650 #define          EVB_PORT_ID_MAC3 0x2000003
6651 #define       EVB_PORT_ID_PORT_ID_LBN 0
6652 #define       EVB_PORT_ID_PORT_ID_WIDTH 32
6653 
6654 /* EVB_VLAN_TAG structuredef */
6655 #define    EVB_VLAN_TAG_LEN 2
6656 /* The VLAN tag value */
6657 #define       EVB_VLAN_TAG_VLAN_ID_LBN 0
6658 #define       EVB_VLAN_TAG_VLAN_ID_WIDTH 12
6659 #define       EVB_VLAN_TAG_MODE_LBN 12
6660 #define       EVB_VLAN_TAG_MODE_WIDTH 4
6661 /* enum: Insert the VLAN. */
6662 #define          EVB_VLAN_TAG_INSERT 0x0
6663 /* enum: Replace the VLAN if already present. */
6664 #define          EVB_VLAN_TAG_REPLACE 0x1
6665 
6666 /* BUFTBL_ENTRY structuredef */
6667 #define    BUFTBL_ENTRY_LEN 12
6668 /* the owner ID */
6669 #define       BUFTBL_ENTRY_OID_OFST 0
6670 #define       BUFTBL_ENTRY_OID_LEN 2
6671 #define       BUFTBL_ENTRY_OID_LBN 0
6672 #define       BUFTBL_ENTRY_OID_WIDTH 16
6673 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */
6674 #define       BUFTBL_ENTRY_PGSZ_OFST 2
6675 #define       BUFTBL_ENTRY_PGSZ_LEN 2
6676 #define       BUFTBL_ENTRY_PGSZ_LBN 16
6677 #define       BUFTBL_ENTRY_PGSZ_WIDTH 16
6678 /* the raw 64-bit address field from the SMC, not adjusted for page size */
6679 #define       BUFTBL_ENTRY_RAWADDR_OFST 4
6680 #define       BUFTBL_ENTRY_RAWADDR_LEN 8
6681 #define       BUFTBL_ENTRY_RAWADDR_LO_OFST 4
6682 #define       BUFTBL_ENTRY_RAWADDR_HI_OFST 8
6683 #define       BUFTBL_ENTRY_RAWADDR_LBN 32
6684 #define       BUFTBL_ENTRY_RAWADDR_WIDTH 64
6685 
6686 /* NVRAM_PARTITION_TYPE structuredef */
6687 #define    NVRAM_PARTITION_TYPE_LEN 2
6688 #define       NVRAM_PARTITION_TYPE_ID_OFST 0
6689 #define       NVRAM_PARTITION_TYPE_ID_LEN 2
6690 /* enum: Primary MC firmware partition */
6691 #define          NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
6692 /* enum: Secondary MC firmware partition */
6693 #define          NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
6694 /* enum: Expansion ROM partition */
6695 #define          NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
6696 /* enum: Static configuration TLV partition */
6697 #define          NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
6698 /* enum: Dynamic configuration TLV partition */
6699 #define          NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
6700 /* enum: Expansion ROM configuration data for port 0 */
6701 #define          NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
6702 /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */
6703 #define          NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600
6704 /* enum: Expansion ROM configuration data for port 1 */
6705 #define          NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
6706 /* enum: Expansion ROM configuration data for port 2 */
6707 #define          NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
6708 /* enum: Expansion ROM configuration data for port 3 */
6709 #define          NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
6710 /* enum: Non-volatile log output partition */
6711 #define          NVRAM_PARTITION_TYPE_LOG 0x700
6712 /* enum: Non-volatile log output of second core on dual-core device */
6713 #define          NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
6714 /* enum: Device state dump output partition */
6715 #define          NVRAM_PARTITION_TYPE_DUMP 0x800
6716 /* enum: Application license key storage partition */
6717 #define          NVRAM_PARTITION_TYPE_LICENSE 0x900
6718 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */
6719 #define          NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
6720 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */
6721 #define          NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
6722 /* enum: Primary FPGA partition */
6723 #define          NVRAM_PARTITION_TYPE_FPGA 0xb00
6724 /* enum: Secondary FPGA partition */
6725 #define          NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01
6726 /* enum: FC firmware partition */
6727 #define          NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02
6728 /* enum: FC License partition */
6729 #define          NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
6730 /* enum: Non-volatile log output partition for FC */
6731 #define          NVRAM_PARTITION_TYPE_FC_LOG 0xb04
6732 /* enum: MUM firmware partition */
6733 #define          NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
6734 /* enum: SUC firmware partition (this is intentionally an alias of
6735  * MUM_FIRMWARE)
6736  */
6737 #define          NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
6738 /* enum: MUM Non-volatile log output partition. */
6739 #define          NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
6740 /* enum: MUM Application table partition. */
6741 #define          NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
6742 /* enum: MUM boot rom partition. */
6743 #define          NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03
6744 /* enum: MUM production signatures & calibration rom partition. */
6745 #define          NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04
6746 /* enum: MUM user signatures & calibration rom partition. */
6747 #define          NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05
6748 /* enum: MUM fuses and lockbits partition. */
6749 #define          NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06
6750 /* enum: UEFI expansion ROM if separate from PXE */
6751 #define          NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
6752 /* enum: Used by the expansion ROM for logging */
6753 #define          NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
6754 /* enum: Used for XIP code of shmbooted images */
6755 #define          NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
6756 /* enum: Spare partition 2 */
6757 #define          NVRAM_PARTITION_TYPE_SPARE_2 0x1200
6758 /* enum: Manufacturing partition. Used during manufacture to pass information
6759  * between XJTAG and Manftest.
6760  */
6761 #define          NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
6762 /* enum: Spare partition 4 */
6763 #define          NVRAM_PARTITION_TYPE_SPARE_4 0x1400
6764 /* enum: Spare partition 5 */
6765 #define          NVRAM_PARTITION_TYPE_SPARE_5 0x1500
6766 /* enum: Partition for reporting MC status. See mc_flash_layout.h
6767  * medford_mc_status_hdr_t for layout on Medford.
6768  */
6769 #define          NVRAM_PARTITION_TYPE_STATUS 0x1600
6770 /* enum: Spare partition 13 */
6771 #define          NVRAM_PARTITION_TYPE_SPARE_13 0x1700
6772 /* enum: Spare partition 14 */
6773 #define          NVRAM_PARTITION_TYPE_SPARE_14 0x1800
6774 /* enum: Spare partition 15 */
6775 #define          NVRAM_PARTITION_TYPE_SPARE_15 0x1900
6776 /* enum: Spare partition 16 */
6777 #define          NVRAM_PARTITION_TYPE_SPARE_16 0x1a00
6778 /* enum: Factory defaults for dynamic configuration */
6779 #define          NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00
6780 /* enum: Factory defaults for expansion ROM configuration */
6781 #define          NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00
6782 /* enum: Field Replaceable Unit inventory information for use on IPMI
6783  * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a
6784  * subset of the information stored in this partition.
6785  */
6786 #define          NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00
6787 /* enum: Bundle image partition */
6788 #define          NVRAM_PARTITION_TYPE_BUNDLE 0x1e00
6789 /* enum: Bundle metadata partition that holds additional information related to
6790  * a bundle update in TLV format
6791  */
6792 #define          NVRAM_PARTITION_TYPE_BUNDLE_METADATA 0x1e01
6793 /* enum: Bundle update non-volatile log output partition */
6794 #define          NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02
6795 /* enum: Start of reserved value range (firmware may use for any purpose) */
6796 #define          NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
6797 /* enum: End of reserved value range (firmware may use for any purpose) */
6798 #define          NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
6799 /* enum: Recovery partition map (provided if real map is missing or corrupt) */
6800 #define          NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
6801 /* enum: Partition map (real map as stored in flash) */
6802 #define          NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
6803 #define       NVRAM_PARTITION_TYPE_ID_LBN 0
6804 #define       NVRAM_PARTITION_TYPE_ID_WIDTH 16
6805 
6806 /* LICENSED_APP_ID structuredef */
6807 #define    LICENSED_APP_ID_LEN 4
6808 #define       LICENSED_APP_ID_ID_OFST 0
6809 #define       LICENSED_APP_ID_ID_LEN 4
6810 /* enum: OpenOnload */
6811 #define          LICENSED_APP_ID_ONLOAD 0x1
6812 /* enum: PTP timestamping */
6813 #define          LICENSED_APP_ID_PTP 0x2
6814 /* enum: SolarCapture Pro */
6815 #define          LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4
6816 /* enum: SolarSecure filter engine */
6817 #define          LICENSED_APP_ID_SOLARSECURE 0x8
6818 /* enum: Performance monitor */
6819 #define          LICENSED_APP_ID_PERF_MONITOR 0x10
6820 /* enum: SolarCapture Live */
6821 #define          LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20
6822 /* enum: Capture SolarSystem */
6823 #define          LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40
6824 /* enum: Network Access Control */
6825 #define          LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80
6826 /* enum: TCP Direct */
6827 #define          LICENSED_APP_ID_TCP_DIRECT 0x100
6828 /* enum: Low Latency */
6829 #define          LICENSED_APP_ID_LOW_LATENCY 0x200
6830 /* enum: SolarCapture Tap */
6831 #define          LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400
6832 /* enum: Capture SolarSystem 40G */
6833 #define          LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800
6834 /* enum: Capture SolarSystem 1G */
6835 #define          LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000
6836 /* enum: ScaleOut Onload */
6837 #define          LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000
6838 /* enum: SCS Network Analytics Dashboard */
6839 #define          LICENSED_APP_ID_DSHBRD 0x4000
6840 /* enum: SolarCapture Trading Analytics */
6841 #define          LICENSED_APP_ID_SCATRD 0x8000
6842 #define       LICENSED_APP_ID_ID_LBN 0
6843 #define       LICENSED_APP_ID_ID_WIDTH 32
6844 
6845 /* LICENSED_FEATURES structuredef */
6846 #define    LICENSED_FEATURES_LEN 8
6847 /* Bitmask of licensed firmware features */
6848 #define       LICENSED_FEATURES_MASK_OFST 0
6849 #define       LICENSED_FEATURES_MASK_LEN 8
6850 #define       LICENSED_FEATURES_MASK_LO_OFST 0
6851 #define       LICENSED_FEATURES_MASK_HI_OFST 4
6852 #define        LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0
6853 #define        LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1
6854 #define        LICENSED_FEATURES_PIO_LBN 1
6855 #define        LICENSED_FEATURES_PIO_WIDTH 1
6856 #define        LICENSED_FEATURES_EVQ_TIMER_LBN 2
6857 #define        LICENSED_FEATURES_EVQ_TIMER_WIDTH 1
6858 #define        LICENSED_FEATURES_CLOCK_LBN 3
6859 #define        LICENSED_FEATURES_CLOCK_WIDTH 1
6860 #define        LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4
6861 #define        LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1
6862 #define        LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5
6863 #define        LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1
6864 #define        LICENSED_FEATURES_RX_SNIFF_LBN 6
6865 #define        LICENSED_FEATURES_RX_SNIFF_WIDTH 1
6866 #define        LICENSED_FEATURES_TX_SNIFF_LBN 7
6867 #define        LICENSED_FEATURES_TX_SNIFF_WIDTH 1
6868 #define        LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8
6869 #define        LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1
6870 #define        LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9
6871 #define        LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
6872 #define       LICENSED_FEATURES_MASK_LBN 0
6873 #define       LICENSED_FEATURES_MASK_WIDTH 64
6874 
6875 /* LICENSED_V3_APPS structuredef */
6876 #define    LICENSED_V3_APPS_LEN 8
6877 /* Bitmask of licensed applications */
6878 #define       LICENSED_V3_APPS_MASK_OFST 0
6879 #define       LICENSED_V3_APPS_MASK_LEN 8
6880 #define       LICENSED_V3_APPS_MASK_LO_OFST 0
6881 #define       LICENSED_V3_APPS_MASK_HI_OFST 4
6882 #define        LICENSED_V3_APPS_ONLOAD_LBN 0
6883 #define        LICENSED_V3_APPS_ONLOAD_WIDTH 1
6884 #define        LICENSED_V3_APPS_PTP_LBN 1
6885 #define        LICENSED_V3_APPS_PTP_WIDTH 1
6886 #define        LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2
6887 #define        LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1
6888 #define        LICENSED_V3_APPS_SOLARSECURE_LBN 3
6889 #define        LICENSED_V3_APPS_SOLARSECURE_WIDTH 1
6890 #define        LICENSED_V3_APPS_PERF_MONITOR_LBN 4
6891 #define        LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1
6892 #define        LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5
6893 #define        LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1
6894 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6
6895 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1
6896 #define        LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7
6897 #define        LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1
6898 #define        LICENSED_V3_APPS_TCP_DIRECT_LBN 8
6899 #define        LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1
6900 #define        LICENSED_V3_APPS_LOW_LATENCY_LBN 9
6901 #define        LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1
6902 #define        LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10
6903 #define        LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1
6904 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11
6905 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1
6906 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12
6907 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1
6908 #define        LICENSED_V3_APPS_SCALEOUT_ONLOAD_LBN 13
6909 #define        LICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 1
6910 #define        LICENSED_V3_APPS_DSHBRD_LBN 14
6911 #define        LICENSED_V3_APPS_DSHBRD_WIDTH 1
6912 #define        LICENSED_V3_APPS_SCATRD_LBN 15
6913 #define        LICENSED_V3_APPS_SCATRD_WIDTH 1
6914 #define       LICENSED_V3_APPS_MASK_LBN 0
6915 #define       LICENSED_V3_APPS_MASK_WIDTH 64
6916 
6917 /* LICENSED_V3_FEATURES structuredef */
6918 #define    LICENSED_V3_FEATURES_LEN 8
6919 /* Bitmask of licensed firmware features */
6920 #define       LICENSED_V3_FEATURES_MASK_OFST 0
6921 #define       LICENSED_V3_FEATURES_MASK_LEN 8
6922 #define       LICENSED_V3_FEATURES_MASK_LO_OFST 0
6923 #define       LICENSED_V3_FEATURES_MASK_HI_OFST 4
6924 #define        LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
6925 #define        LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1
6926 #define        LICENSED_V3_FEATURES_PIO_LBN 1
6927 #define        LICENSED_V3_FEATURES_PIO_WIDTH 1
6928 #define        LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2
6929 #define        LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1
6930 #define        LICENSED_V3_FEATURES_CLOCK_LBN 3
6931 #define        LICENSED_V3_FEATURES_CLOCK_WIDTH 1
6932 #define        LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4
6933 #define        LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1
6934 #define        LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5
6935 #define        LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1
6936 #define        LICENSED_V3_FEATURES_RX_SNIFF_LBN 6
6937 #define        LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1
6938 #define        LICENSED_V3_FEATURES_TX_SNIFF_LBN 7
6939 #define        LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1
6940 #define        LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8
6941 #define        LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1
6942 #define        LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9
6943 #define        LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
6944 #define       LICENSED_V3_FEATURES_MASK_LBN 0
6945 #define       LICENSED_V3_FEATURES_MASK_WIDTH 64
6946 
6947 /* TX_TIMESTAMP_EVENT structuredef */
6948 #define    TX_TIMESTAMP_EVENT_LEN 6
6949 /* lower 16 bits of timestamp data */
6950 #define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0
6951 #define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2
6952 #define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0
6953 #define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16
6954 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp
6955  */
6956 #define       TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3
6957 #define       TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1
6958 /* enum: This is a TX completion event, not a timestamp */
6959 #define          TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0
6960 /* enum: This is a TX completion event for a CTPIO transmit. The event format
6961  * is the same as for TX_EV_COMPLETION.
6962  */
6963 #define          TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11
6964 /* enum: This is the low part of a TX timestamp for a CTPIO transmission. The
6965  * event format is the same as for TX_EV_TSTAMP_LO
6966  */
6967 #define          TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12
6968 /* enum: This is the high part of a TX timestamp for a CTPIO transmission. The
6969  * event format is the same as for TX_EV_TSTAMP_HI
6970  */
6971 #define          TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13
6972 /* enum: This is the low part of a TX timestamp event */
6973 #define          TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51
6974 /* enum: This is the high part of a TX timestamp event */
6975 #define          TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52
6976 #define       TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24
6977 #define       TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8
6978 /* upper 16 bits of timestamp data */
6979 #define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4
6980 #define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2
6981 #define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32
6982 #define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16
6983 
6984 /* RSS_MODE structuredef */
6985 #define    RSS_MODE_LEN 1
6986 /* The RSS mode for a particular packet type is a value from 0 - 15 which can
6987  * be considered as 4 bits selecting which fields are included in the hash. (A
6988  * value 0 effectively disables RSS spreading for the packet type.) The YAML
6989  * generation tools require this structure to be a whole number of bytes wide,
6990  * but only 4 bits are relevant.
6991  */
6992 #define       RSS_MODE_HASH_SELECTOR_OFST 0
6993 #define       RSS_MODE_HASH_SELECTOR_LEN 1
6994 #define        RSS_MODE_HASH_SRC_ADDR_LBN 0
6995 #define        RSS_MODE_HASH_SRC_ADDR_WIDTH 1
6996 #define        RSS_MODE_HASH_DST_ADDR_LBN 1
6997 #define        RSS_MODE_HASH_DST_ADDR_WIDTH 1
6998 #define        RSS_MODE_HASH_SRC_PORT_LBN 2
6999 #define        RSS_MODE_HASH_SRC_PORT_WIDTH 1
7000 #define        RSS_MODE_HASH_DST_PORT_LBN 3
7001 #define        RSS_MODE_HASH_DST_PORT_WIDTH 1
7002 #define       RSS_MODE_HASH_SELECTOR_LBN 0
7003 #define       RSS_MODE_HASH_SELECTOR_WIDTH 8
7004 
7005 /* CTPIO_STATS_MAP structuredef */
7006 #define    CTPIO_STATS_MAP_LEN 4
7007 /* The (function relative) VI number */
7008 #define       CTPIO_STATS_MAP_VI_OFST 0
7009 #define       CTPIO_STATS_MAP_VI_LEN 2
7010 #define       CTPIO_STATS_MAP_VI_LBN 0
7011 #define       CTPIO_STATS_MAP_VI_WIDTH 16
7012 /* The target bucket for the VI */
7013 #define       CTPIO_STATS_MAP_BUCKET_OFST 2
7014 #define       CTPIO_STATS_MAP_BUCKET_LEN 2
7015 #define       CTPIO_STATS_MAP_BUCKET_LBN 16
7016 #define       CTPIO_STATS_MAP_BUCKET_WIDTH 16
7017 
7018 
7019 /***********************************/
7020 /* MC_CMD_READ_REGS
7021  * Get a dump of the MCPU registers
7022  */
7023 #define MC_CMD_READ_REGS 0x50
7024 
7025 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE
7026 
7027 /* MC_CMD_READ_REGS_IN msgrequest */
7028 #define    MC_CMD_READ_REGS_IN_LEN 0
7029 
7030 /* MC_CMD_READ_REGS_OUT msgresponse */
7031 #define    MC_CMD_READ_REGS_OUT_LEN 308
7032 /* Whether the corresponding register entry contains a valid value */
7033 #define       MC_CMD_READ_REGS_OUT_MASK_OFST 0
7034 #define       MC_CMD_READ_REGS_OUT_MASK_LEN 16
7035 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr,
7036  * fir, fp)
7037  */
7038 #define       MC_CMD_READ_REGS_OUT_REGS_OFST 16
7039 #define       MC_CMD_READ_REGS_OUT_REGS_LEN 4
7040 #define       MC_CMD_READ_REGS_OUT_REGS_NUM 73
7041 
7042 
7043 /***********************************/
7044 /* MC_CMD_INIT_EVQ
7045  * Set up an event queue according to the supplied parameters. The IN arguments
7046  * end with an address for each 4k of host memory required to back the EVQ.
7047  */
7048 #define MC_CMD_INIT_EVQ 0x80
7049 
7050 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7051 
7052 /* MC_CMD_INIT_EVQ_IN msgrequest */
7053 #define    MC_CMD_INIT_EVQ_IN_LENMIN 44
7054 #define    MC_CMD_INIT_EVQ_IN_LENMAX 548
7055 #define    MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num))
7056 /* Size, in entries */
7057 #define       MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
7058 #define       MC_CMD_INIT_EVQ_IN_SIZE_LEN 4
7059 /* Desired instance. Must be set to a specific instance, which is a function
7060  * local queue index.
7061  */
7062 #define       MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
7063 #define       MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4
7064 /* The initial timer value. The load value is ignored if the timer mode is DIS.
7065  */
7066 #define       MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8
7067 #define       MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4
7068 /* The reload value is ignored in one-shot modes */
7069 #define       MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12
7070 #define       MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4
7071 /* tbd */
7072 #define       MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16
7073 #define       MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4
7074 #define        MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
7075 #define        MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1
7076 #define        MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1
7077 #define        MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1
7078 #define        MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2
7079 #define        MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1
7080 #define        MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3
7081 #define        MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1
7082 #define        MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4
7083 #define        MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1
7084 #define        MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5
7085 #define        MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1
7086 #define        MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6
7087 #define        MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1
7088 #define       MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20
7089 #define       MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4
7090 /* enum: Disabled */
7091 #define          MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0
7092 /* enum: Immediate */
7093 #define          MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1
7094 /* enum: Triggered */
7095 #define          MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2
7096 /* enum: Hold-off */
7097 #define          MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3
7098 /* Target EVQ for wakeups if in wakeup mode. */
7099 #define       MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24
7100 #define       MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4
7101 /* Target interrupt if in interrupting mode (note union with target EVQ). Use
7102  * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
7103  * purposes.
7104  */
7105 #define       MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24
7106 #define       MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4
7107 /* Event Counter Mode. */
7108 #define       MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28
7109 #define       MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4
7110 /* enum: Disabled */
7111 #define          MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0
7112 /* enum: Disabled */
7113 #define          MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1
7114 /* enum: Disabled */
7115 #define          MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2
7116 /* enum: Disabled */
7117 #define          MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3
7118 /* Event queue packet count threshold. */
7119 #define       MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32
7120 #define       MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4
7121 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7122 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36
7123 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8
7124 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36
7125 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40
7126 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
7127 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64
7128 
7129 /* MC_CMD_INIT_EVQ_OUT msgresponse */
7130 #define    MC_CMD_INIT_EVQ_OUT_LEN 4
7131 /* Only valid if INTRFLAG was true */
7132 #define       MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
7133 #define       MC_CMD_INIT_EVQ_OUT_IRQ_LEN 4
7134 
7135 /* MC_CMD_INIT_EVQ_V2_IN msgrequest */
7136 #define    MC_CMD_INIT_EVQ_V2_IN_LENMIN 44
7137 #define    MC_CMD_INIT_EVQ_V2_IN_LENMAX 548
7138 #define    MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num))
7139 /* Size, in entries */
7140 #define       MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
7141 #define       MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4
7142 /* Desired instance. Must be set to a specific instance, which is a function
7143  * local queue index.
7144  */
7145 #define       MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4
7146 #define       MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4
7147 /* The initial timer value. The load value is ignored if the timer mode is DIS.
7148  */
7149 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8
7150 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4
7151 /* The reload value is ignored in one-shot modes */
7152 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12
7153 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4
7154 /* tbd */
7155 #define       MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16
7156 #define       MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4
7157 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0
7158 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1
7159 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1
7160 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1
7161 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2
7162 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1
7163 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3
7164 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1
7165 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4
7166 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1
7167 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5
7168 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1
7169 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6
7170 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1
7171 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7
7172 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4
7173 /* enum: All initialisation flags specified by host. */
7174 #define          MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0
7175 /* enum: MEDFORD only. Certain initialisation flags specified by host may be
7176  * over-ridden by firmware based on licenses and firmware variant in order to
7177  * provide the lowest latency achievable. See
7178  * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
7179  */
7180 #define          MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1
7181 /* enum: MEDFORD only. Certain initialisation flags specified by host may be
7182  * over-ridden by firmware based on licenses and firmware variant in order to
7183  * provide the best throughput achievable. See
7184  * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
7185  */
7186 #define          MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2
7187 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
7188  * firmware based on licenses and firmware variant. See
7189  * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
7190  */
7191 #define          MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3
7192 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20
7193 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4
7194 /* enum: Disabled */
7195 #define          MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0
7196 /* enum: Immediate */
7197 #define          MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1
7198 /* enum: Triggered */
7199 #define          MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2
7200 /* enum: Hold-off */
7201 #define          MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3
7202 /* Target EVQ for wakeups if in wakeup mode. */
7203 #define       MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24
7204 #define       MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4
7205 /* Target interrupt if in interrupting mode (note union with target EVQ). Use
7206  * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
7207  * purposes.
7208  */
7209 #define       MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24
7210 #define       MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4
7211 /* Event Counter Mode. */
7212 #define       MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28
7213 #define       MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4
7214 /* enum: Disabled */
7215 #define          MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0
7216 /* enum: Disabled */
7217 #define          MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1
7218 /* enum: Disabled */
7219 #define          MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2
7220 /* enum: Disabled */
7221 #define          MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3
7222 /* Event queue packet count threshold. */
7223 #define       MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32
7224 #define       MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4
7225 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7226 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36
7227 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8
7228 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36
7229 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40
7230 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1
7231 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64
7232 
7233 /* MC_CMD_INIT_EVQ_V2_OUT msgresponse */
7234 #define    MC_CMD_INIT_EVQ_V2_OUT_LEN 8
7235 /* Only valid if INTRFLAG was true */
7236 #define       MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0
7237 #define       MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4
7238 /* Actual configuration applied on the card */
7239 #define       MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4
7240 #define       MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4
7241 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0
7242 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1
7243 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1
7244 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1
7245 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2
7246 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1
7247 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3
7248 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1
7249 
7250 /* QUEUE_CRC_MODE structuredef */
7251 #define    QUEUE_CRC_MODE_LEN 1
7252 #define       QUEUE_CRC_MODE_MODE_LBN 0
7253 #define       QUEUE_CRC_MODE_MODE_WIDTH 4
7254 /* enum: No CRC. */
7255 #define          QUEUE_CRC_MODE_NONE 0x0
7256 /* enum: CRC Fiber channel over ethernet. */
7257 #define          QUEUE_CRC_MODE_FCOE 0x1
7258 /* enum: CRC (digest) iSCSI header only. */
7259 #define          QUEUE_CRC_MODE_ISCSI_HDR 0x2
7260 /* enum: CRC (digest) iSCSI header and payload. */
7261 #define          QUEUE_CRC_MODE_ISCSI 0x3
7262 /* enum: CRC Fiber channel over IP over ethernet. */
7263 #define          QUEUE_CRC_MODE_FCOIPOE 0x4
7264 /* enum: CRC MPA. */
7265 #define          QUEUE_CRC_MODE_MPA 0x5
7266 #define       QUEUE_CRC_MODE_SPARE_LBN 4
7267 #define       QUEUE_CRC_MODE_SPARE_WIDTH 4
7268 
7269 
7270 /***********************************/
7271 /* MC_CMD_INIT_RXQ
7272  * set up a receive queue according to the supplied parameters. The IN
7273  * arguments end with an address for each 4k of host memory required to back
7274  * the RXQ.
7275  */
7276 #define MC_CMD_INIT_RXQ 0x81
7277 
7278 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7279 
7280 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version
7281  * in new code.
7282  */
7283 #define    MC_CMD_INIT_RXQ_IN_LENMIN 36
7284 #define    MC_CMD_INIT_RXQ_IN_LENMAX 252
7285 #define    MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num))
7286 /* Size, in entries */
7287 #define       MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
7288 #define       MC_CMD_INIT_RXQ_IN_SIZE_LEN 4
7289 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ
7290  */
7291 #define       MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
7292 #define       MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4
7293 /* The value to put in the event data. Check hardware spec. for valid range. */
7294 #define       MC_CMD_INIT_RXQ_IN_LABEL_OFST 8
7295 #define       MC_CMD_INIT_RXQ_IN_LABEL_LEN 4
7296 /* Desired instance. Must be set to a specific instance, which is a function
7297  * local queue index.
7298  */
7299 #define       MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12
7300 #define       MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4
7301 /* There will be more flags here. */
7302 #define       MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16
7303 #define       MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4
7304 #define        MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
7305 #define        MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1
7306 #define        MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1
7307 #define        MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1
7308 #define        MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2
7309 #define        MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1
7310 #define        MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3
7311 #define        MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
7312 #define        MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7
7313 #define        MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1
7314 #define        MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8
7315 #define        MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1
7316 #define        MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9
7317 #define        MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1
7318 #define        MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10
7319 #define        MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1
7320 /* Owner ID to use if in buffer mode (zero if physical) */
7321 #define       MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20
7322 #define       MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4
7323 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
7324 #define       MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24
7325 #define       MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4
7326 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7327 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28
7328 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8
7329 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28
7330 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32
7331 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
7332 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28
7333 
7334 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode
7335  * flags
7336  */
7337 #define    MC_CMD_INIT_RXQ_EXT_IN_LEN 544
7338 /* Size, in entries */
7339 #define       MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0
7340 #define       MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4
7341 /* The EVQ to send events to. This is an index originally specified to
7342  * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
7343  */
7344 #define       MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4
7345 #define       MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4
7346 /* The value to put in the event data. Check hardware spec. for valid range.
7347  * This field is ignored if DMA_MODE == EQUAL_STRIDE_PACKED_STREAM or DMA_MODE
7348  * == PACKED_STREAM.
7349  */
7350 #define       MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8
7351 #define       MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4
7352 /* Desired instance. Must be set to a specific instance, which is a function
7353  * local queue index.
7354  */
7355 #define       MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12
7356 #define       MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4
7357 /* There will be more flags here. */
7358 #define       MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16
7359 #define       MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4
7360 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
7361 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
7362 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1
7363 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1
7364 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2
7365 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
7366 #define        MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3
7367 #define        MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4
7368 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7
7369 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1
7370 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8
7371 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1
7372 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9
7373 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1
7374 #define        MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10
7375 #define        MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4
7376 /* enum: One packet per descriptor (for normal networking) */
7377 #define          MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0
7378 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */
7379 #define          MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1
7380 /* enum: Pack multiple packets into large descriptors using the format designed
7381  * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
7382  * multiple fixed-size packet buffers within each bucket. For a full
7383  * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
7384  * firmware.
7385  */
7386 #define          MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
7387 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14
7388 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
7389 #define        MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
7390 #define        MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
7391 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */
7392 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */
7393 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */
7394 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */
7395 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */
7396 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
7397 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
7398 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19
7399 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
7400 /* Owner ID to use if in buffer mode (zero if physical) */
7401 #define       MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20
7402 #define       MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4
7403 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
7404 #define       MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24
7405 #define       MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4
7406 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7407 #define       MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28
7408 #define       MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8
7409 #define       MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28
7410 #define       MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32
7411 #define       MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64
7412 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
7413 #define       MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540
7414 #define       MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4
7415 
7416 /* MC_CMD_INIT_RXQ_V3_IN msgrequest */
7417 #define    MC_CMD_INIT_RXQ_V3_IN_LEN 560
7418 /* Size, in entries */
7419 #define       MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 0
7420 #define       MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 4
7421 /* The EVQ to send events to. This is an index originally specified to
7422  * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
7423  */
7424 #define       MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4
7425 #define       MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4
7426 /* The value to put in the event data. Check hardware spec. for valid range.
7427  * This field is ignored if DMA_MODE == EQUAL_STRIDE_PACKED_STREAM or DMA_MODE
7428  * == PACKED_STREAM.
7429  */
7430 #define       MC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 8
7431 #define       MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4
7432 /* Desired instance. Must be set to a specific instance, which is a function
7433  * local queue index.
7434  */
7435 #define       MC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 12
7436 #define       MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4
7437 /* There will be more flags here. */
7438 #define       MC_CMD_INIT_RXQ_V3_IN_FLAGS_OFST 16
7439 #define       MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4
7440 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0
7441 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 1
7442 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 1
7443 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 1
7444 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_LBN 2
7445 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 1
7446 #define        MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_LBN 3
7447 #define        MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4
7448 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_LBN 7
7449 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 1
7450 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_LBN 8
7451 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 1
7452 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_LBN 9
7453 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 1
7454 #define        MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_LBN 10
7455 #define        MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4
7456 /* enum: One packet per descriptor (for normal networking) */
7457 #define          MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0
7458 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */
7459 #define          MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1
7460 /* enum: Pack multiple packets into large descriptors using the format designed
7461  * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
7462  * multiple fixed-size packet buffers within each bucket. For a full
7463  * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
7464  * firmware.
7465  */
7466 #define          MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
7467 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_LBN 14
7468 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
7469 #define        MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
7470 #define        MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
7471 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */
7472 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */
7473 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */
7474 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */
7475 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */
7476 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
7477 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
7478 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_LBN 19
7479 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
7480 /* Owner ID to use if in buffer mode (zero if physical) */
7481 #define       MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 20
7482 #define       MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4
7483 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
7484 #define       MC_CMD_INIT_RXQ_V3_IN_PORT_ID_OFST 24
7485 #define       MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 4
7486 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7487 #define       MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 28
7488 #define       MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 8
7489 #define       MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 28
7490 #define       MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 32
7491 #define       MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_NUM 64
7492 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
7493 #define       MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 540
7494 #define       MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4
7495 /* The number of packet buffers that will be contained within each
7496  * EQUAL_STRIDE_PACKED_STREAM format bucket supplied by the driver. This field
7497  * is ignored unless DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.
7498  */
7499 #define       MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544
7500 #define       MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
7501 /* The length in bytes of the area in each packet buffer that can be written to
7502  * by the adapter. This is used to store the packet prefix and the packet
7503  * payload. This length does not include any end padding added by the driver.
7504  * This field is ignored unless DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.
7505  */
7506 #define       MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_OFST 548
7507 #define       MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4
7508 /* The length in bytes of a single packet buffer within a
7509  * EQUAL_STRIDE_PACKED_STREAM format bucket. This field is ignored unless
7510  * DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.
7511  */
7512 #define       MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_OFST 552
7513 #define       MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4
7514 /* The maximum time in nanoseconds that the datapath will be backpressured if
7515  * there are no RX descriptors available. If the timeout is reached and there
7516  * are still no descriptors then the packet will be dropped. A timeout of 0
7517  * means the datapath will never be blocked. This field is ignored unless
7518  * DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.
7519  */
7520 #define       MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556
7521 #define       MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
7522 
7523 /* MC_CMD_INIT_RXQ_OUT msgresponse */
7524 #define    MC_CMD_INIT_RXQ_OUT_LEN 0
7525 
7526 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */
7527 #define    MC_CMD_INIT_RXQ_EXT_OUT_LEN 0
7528 
7529 /* MC_CMD_INIT_RXQ_V3_OUT msgresponse */
7530 #define    MC_CMD_INIT_RXQ_V3_OUT_LEN 0
7531 
7532 
7533 /***********************************/
7534 /* MC_CMD_INIT_TXQ
7535  */
7536 #define MC_CMD_INIT_TXQ 0x82
7537 
7538 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7539 
7540 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version
7541  * in new code.
7542  */
7543 #define    MC_CMD_INIT_TXQ_IN_LENMIN 36
7544 #define    MC_CMD_INIT_TXQ_IN_LENMAX 252
7545 #define    MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num))
7546 /* Size, in entries */
7547 #define       MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
7548 #define       MC_CMD_INIT_TXQ_IN_SIZE_LEN 4
7549 /* The EVQ to send events to. This is an index originally specified to
7550  * INIT_EVQ.
7551  */
7552 #define       MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
7553 #define       MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4
7554 /* The value to put in the event data. Check hardware spec. for valid range. */
7555 #define       MC_CMD_INIT_TXQ_IN_LABEL_OFST 8
7556 #define       MC_CMD_INIT_TXQ_IN_LABEL_LEN 4
7557 /* Desired instance. Must be set to a specific instance, which is a function
7558  * local queue index.
7559  */
7560 #define       MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12
7561 #define       MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4
7562 /* There will be more flags here. */
7563 #define       MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16
7564 #define       MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4
7565 #define        MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
7566 #define        MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1
7567 #define        MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1
7568 #define        MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1
7569 #define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2
7570 #define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
7571 #define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3
7572 #define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
7573 #define        MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
7574 #define        MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
7575 #define        MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8
7576 #define        MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1
7577 #define        MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9
7578 #define        MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1
7579 #define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
7580 #define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
7581 #define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
7582 #define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
7583 /* Owner ID to use if in buffer mode (zero if physical) */
7584 #define       MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20
7585 #define       MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4
7586 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
7587 #define       MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24
7588 #define       MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4
7589 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7590 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28
7591 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8
7592 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28
7593 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32
7594 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
7595 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28
7596 
7597 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode
7598  * flags
7599  */
7600 #define    MC_CMD_INIT_TXQ_EXT_IN_LEN 544
7601 /* Size, in entries */
7602 #define       MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0
7603 #define       MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4
7604 /* The EVQ to send events to. This is an index originally specified to
7605  * INIT_EVQ.
7606  */
7607 #define       MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4
7608 #define       MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4
7609 /* The value to put in the event data. Check hardware spec. for valid range. */
7610 #define       MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8
7611 #define       MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4
7612 /* Desired instance. Must be set to a specific instance, which is a function
7613  * local queue index.
7614  */
7615 #define       MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12
7616 #define       MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4
7617 /* There will be more flags here. */
7618 #define       MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16
7619 #define       MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4
7620 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
7621 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
7622 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1
7623 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1
7624 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2
7625 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
7626 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3
7627 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
7628 #define        MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4
7629 #define        MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4
7630 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8
7631 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
7632 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9
7633 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1
7634 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
7635 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
7636 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
7637 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
7638 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12
7639 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1
7640 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13
7641 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1
7642 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_LBN 14
7643 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_WIDTH 1
7644 /* Owner ID to use if in buffer mode (zero if physical) */
7645 #define       MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20
7646 #define       MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4
7647 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
7648 #define       MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24
7649 #define       MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4
7650 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7651 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28
7652 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8
7653 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28
7654 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32
7655 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1
7656 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64
7657 /* Flags related to Qbb flow control mode. */
7658 #define       MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540
7659 #define       MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4
7660 #define        MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0
7661 #define        MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1
7662 #define        MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1
7663 #define        MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3
7664 
7665 /* MC_CMD_INIT_TXQ_OUT msgresponse */
7666 #define    MC_CMD_INIT_TXQ_OUT_LEN 0
7667 
7668 
7669 /***********************************/
7670 /* MC_CMD_FINI_EVQ
7671  * Teardown an EVQ.
7672  *
7673  * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first
7674  * or the operation will fail with EBUSY
7675  */
7676 #define MC_CMD_FINI_EVQ 0x83
7677 
7678 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7679 
7680 /* MC_CMD_FINI_EVQ_IN msgrequest */
7681 #define    MC_CMD_FINI_EVQ_IN_LEN 4
7682 /* Instance of EVQ to destroy. Should be the same instance as that previously
7683  * passed to INIT_EVQ
7684  */
7685 #define       MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
7686 #define       MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4
7687 
7688 /* MC_CMD_FINI_EVQ_OUT msgresponse */
7689 #define    MC_CMD_FINI_EVQ_OUT_LEN 0
7690 
7691 
7692 /***********************************/
7693 /* MC_CMD_FINI_RXQ
7694  * Teardown a RXQ.
7695  */
7696 #define MC_CMD_FINI_RXQ 0x84
7697 
7698 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7699 
7700 /* MC_CMD_FINI_RXQ_IN msgrequest */
7701 #define    MC_CMD_FINI_RXQ_IN_LEN 4
7702 /* Instance of RXQ to destroy */
7703 #define       MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
7704 #define       MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4
7705 
7706 /* MC_CMD_FINI_RXQ_OUT msgresponse */
7707 #define    MC_CMD_FINI_RXQ_OUT_LEN 0
7708 
7709 
7710 /***********************************/
7711 /* MC_CMD_FINI_TXQ
7712  * Teardown a TXQ.
7713  */
7714 #define MC_CMD_FINI_TXQ 0x85
7715 
7716 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7717 
7718 /* MC_CMD_FINI_TXQ_IN msgrequest */
7719 #define    MC_CMD_FINI_TXQ_IN_LEN 4
7720 /* Instance of TXQ to destroy */
7721 #define       MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
7722 #define       MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4
7723 
7724 /* MC_CMD_FINI_TXQ_OUT msgresponse */
7725 #define    MC_CMD_FINI_TXQ_OUT_LEN 0
7726 
7727 
7728 /***********************************/
7729 /* MC_CMD_DRIVER_EVENT
7730  * Generate an event on an EVQ belonging to the function issuing the command.
7731  */
7732 #define MC_CMD_DRIVER_EVENT 0x86
7733 
7734 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7735 
7736 /* MC_CMD_DRIVER_EVENT_IN msgrequest */
7737 #define    MC_CMD_DRIVER_EVENT_IN_LEN 12
7738 /* Handle of target EVQ */
7739 #define       MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0
7740 #define       MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4
7741 /* Bits 0 - 63 of event */
7742 #define       MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
7743 #define       MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8
7744 #define       MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
7745 #define       MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8
7746 
7747 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */
7748 #define    MC_CMD_DRIVER_EVENT_OUT_LEN 0
7749 
7750 
7751 /***********************************/
7752 /* MC_CMD_PROXY_CMD
7753  * Execute an arbitrary MCDI command on behalf of a different function, subject
7754  * to security restrictions. The command to be proxied follows immediately
7755  * afterward in the host buffer (or on the UART). This command supercedes
7756  * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated.
7757  */
7758 #define MC_CMD_PROXY_CMD 0x5b
7759 
7760 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7761 
7762 /* MC_CMD_PROXY_CMD_IN msgrequest */
7763 #define    MC_CMD_PROXY_CMD_IN_LEN 4
7764 /* The handle of the target function. */
7765 #define       MC_CMD_PROXY_CMD_IN_TARGET_OFST 0
7766 #define       MC_CMD_PROXY_CMD_IN_TARGET_LEN 4
7767 #define        MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0
7768 #define        MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16
7769 #define        MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16
7770 #define        MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16
7771 #define          MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */
7772 
7773 /* MC_CMD_PROXY_CMD_OUT msgresponse */
7774 #define    MC_CMD_PROXY_CMD_OUT_LEN 0
7775 
7776 /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to
7777  * manage proxied requests
7778  */
7779 #define    MC_PROXY_STATUS_BUFFER_LEN 16
7780 /* Handle allocated by the firmware for this proxy transaction */
7781 #define       MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0
7782 #define       MC_PROXY_STATUS_BUFFER_HANDLE_LEN 4
7783 /* enum: An invalid handle. */
7784 #define          MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0
7785 #define       MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0
7786 #define       MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32
7787 /* The requesting physical function number */
7788 #define       MC_PROXY_STATUS_BUFFER_PF_OFST 4
7789 #define       MC_PROXY_STATUS_BUFFER_PF_LEN 2
7790 #define       MC_PROXY_STATUS_BUFFER_PF_LBN 32
7791 #define       MC_PROXY_STATUS_BUFFER_PF_WIDTH 16
7792 /* The requesting virtual function number. Set to VF_NULL if the target is a
7793  * PF.
7794  */
7795 #define       MC_PROXY_STATUS_BUFFER_VF_OFST 6
7796 #define       MC_PROXY_STATUS_BUFFER_VF_LEN 2
7797 #define       MC_PROXY_STATUS_BUFFER_VF_LBN 48
7798 #define       MC_PROXY_STATUS_BUFFER_VF_WIDTH 16
7799 /* The target function RID. */
7800 #define       MC_PROXY_STATUS_BUFFER_RID_OFST 8
7801 #define       MC_PROXY_STATUS_BUFFER_RID_LEN 2
7802 #define       MC_PROXY_STATUS_BUFFER_RID_LBN 64
7803 #define       MC_PROXY_STATUS_BUFFER_RID_WIDTH 16
7804 /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */
7805 #define       MC_PROXY_STATUS_BUFFER_STATUS_OFST 10
7806 #define       MC_PROXY_STATUS_BUFFER_STATUS_LEN 2
7807 #define       MC_PROXY_STATUS_BUFFER_STATUS_LBN 80
7808 #define       MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16
7809 /* If a request is authorized rather than carried out by the host, this is the
7810  * elevated privilege mask granted to the requesting function.
7811  */
7812 #define       MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12
7813 #define       MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LEN 4
7814 #define       MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96
7815 #define       MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32
7816 
7817 
7818 /***********************************/
7819 /* MC_CMD_PROXY_CONFIGURE
7820  * Enable/disable authorization of MCDI requests from unprivileged functions by
7821  * a designated admin function
7822  */
7823 #define MC_CMD_PROXY_CONFIGURE 0x58
7824 
7825 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7826 
7827 /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */
7828 #define    MC_CMD_PROXY_CONFIGURE_IN_LEN 108
7829 #define       MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0
7830 #define       MC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 4
7831 #define        MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0
7832 #define        MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1
7833 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7834  * of blocks, each of the size REQUEST_BLOCK_SIZE.
7835  */
7836 #define       MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4
7837 #define       MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8
7838 #define       MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4
7839 #define       MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8
7840 /* Must be a power of 2 */
7841 #define       MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12
7842 #define       MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4
7843 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7844  * of blocks, each of the size REPLY_BLOCK_SIZE.
7845  */
7846 #define       MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16
7847 #define       MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8
7848 #define       MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16
7849 #define       MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20
7850 /* Must be a power of 2 */
7851 #define       MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24
7852 #define       MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4
7853 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7854  * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if
7855  * host intends to complete proxied operations by using MC_CMD_PROXY_CMD.
7856  */
7857 #define       MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28
7858 #define       MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8
7859 #define       MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28
7860 #define       MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32
7861 /* Must be a power of 2, or zero if this buffer is not provided */
7862 #define       MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36
7863 #define       MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4
7864 /* Applies to all three buffers */
7865 #define       MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40
7866 #define       MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_LEN 4
7867 /* A bit mask defining which MCDI operations may be proxied */
7868 #define       MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44
7869 #define       MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64
7870 
7871 /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */
7872 #define    MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112
7873 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0
7874 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 4
7875 #define        MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0
7876 #define        MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1
7877 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7878  * of blocks, each of the size REQUEST_BLOCK_SIZE.
7879  */
7880 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4
7881 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8
7882 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4
7883 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8
7884 /* Must be a power of 2 */
7885 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12
7886 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4
7887 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7888  * of blocks, each of the size REPLY_BLOCK_SIZE.
7889  */
7890 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16
7891 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8
7892 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16
7893 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20
7894 /* Must be a power of 2 */
7895 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24
7896 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4
7897 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7898  * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if
7899  * host intends to complete proxied operations by using MC_CMD_PROXY_CMD.
7900  */
7901 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28
7902 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8
7903 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28
7904 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32
7905 /* Must be a power of 2, or zero if this buffer is not provided */
7906 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36
7907 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4
7908 /* Applies to all three buffers */
7909 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40
7910 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_LEN 4
7911 /* A bit mask defining which MCDI operations may be proxied */
7912 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44
7913 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64
7914 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108
7915 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_LEN 4
7916 
7917 /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */
7918 #define    MC_CMD_PROXY_CONFIGURE_OUT_LEN 0
7919 
7920 
7921 /***********************************/
7922 /* MC_CMD_PROXY_COMPLETE
7923  * Tells FW that a requested proxy operation has either been completed (by
7924  * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the
7925  * function that enabled proxying/authorization (by using
7926  * MC_CMD_PROXY_CONFIGURE).
7927  */
7928 #define MC_CMD_PROXY_COMPLETE 0x5f
7929 
7930 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7931 
7932 /* MC_CMD_PROXY_COMPLETE_IN msgrequest */
7933 #define    MC_CMD_PROXY_COMPLETE_IN_LEN 12
7934 #define       MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0
7935 #define       MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_LEN 4
7936 #define       MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4
7937 #define       MC_CMD_PROXY_COMPLETE_IN_STATUS_LEN 4
7938 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply
7939  * is stored in the REPLY_BUFF.
7940  */
7941 #define          MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0
7942 /* enum: The operation has been authorized. The originating function may now
7943  * try again.
7944  */
7945 #define          MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1
7946 /* enum: The operation has been declined. */
7947 #define          MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2
7948 /* enum: The authorization failed because the relevant application did not
7949  * respond in time.
7950  */
7951 #define          MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3
7952 #define       MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8
7953 #define       MC_CMD_PROXY_COMPLETE_IN_HANDLE_LEN 4
7954 
7955 /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */
7956 #define    MC_CMD_PROXY_COMPLETE_OUT_LEN 0
7957 
7958 
7959 /***********************************/
7960 /* MC_CMD_ALLOC_BUFTBL_CHUNK
7961  * Allocate a set of buffer table entries using the specified owner ID. This
7962  * operation allocates the required buffer table entries (and fails if it
7963  * cannot do so). The buffer table entries will initially be zeroed.
7964  */
7965 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87
7966 
7967 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
7968 
7969 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */
7970 #define    MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8
7971 /* Owner ID to use */
7972 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0
7973 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4
7974 /* Size of buffer table pages to use, in bytes (note that only a few values are
7975  * legal on any specific hardware).
7976  */
7977 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4
7978 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4
7979 
7980 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */
7981 #define    MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12
7982 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0
7983 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 4
7984 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4
7985 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 4
7986 /* Buffer table IDs for use in DMA descriptors. */
7987 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8
7988 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4
7989 
7990 
7991 /***********************************/
7992 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES
7993  * Reprogram a set of buffer table entries in the specified chunk.
7994  */
7995 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88
7996 
7997 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
7998 
7999 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */
8000 #define    MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20
8001 #define    MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268
8002 #define    MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num))
8003 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0
8004 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4
8005 /* ID */
8006 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4
8007 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4
8008 /* Num entries */
8009 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8
8010 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4
8011 /* Buffer table entry address */
8012 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12
8013 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8
8014 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12
8015 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16
8016 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1
8017 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32
8018 
8019 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */
8020 #define    MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0
8021 
8022 
8023 /***********************************/
8024 /* MC_CMD_FREE_BUFTBL_CHUNK
8025  */
8026 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89
8027 
8028 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
8029 
8030 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */
8031 #define    MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4
8032 #define       MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0
8033 #define       MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 4
8034 
8035 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */
8036 #define    MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0
8037 
8038 
8039 /***********************************/
8040 /* MC_CMD_FILTER_OP
8041  * Multiplexed MCDI call for filter operations
8042  */
8043 #define MC_CMD_FILTER_OP 0x8a
8044 
8045 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8046 
8047 /* MC_CMD_FILTER_OP_IN msgrequest */
8048 #define    MC_CMD_FILTER_OP_IN_LEN 108
8049 /* identifies the type of operation requested */
8050 #define       MC_CMD_FILTER_OP_IN_OP_OFST 0
8051 #define       MC_CMD_FILTER_OP_IN_OP_LEN 4
8052 /* enum: single-recipient filter insert */
8053 #define          MC_CMD_FILTER_OP_IN_OP_INSERT 0x0
8054 /* enum: single-recipient filter remove */
8055 #define          MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1
8056 /* enum: multi-recipient filter subscribe */
8057 #define          MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2
8058 /* enum: multi-recipient filter unsubscribe */
8059 #define          MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3
8060 /* enum: replace one recipient with another (warning - the filter handle may
8061  * change)
8062  */
8063 #define          MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4
8064 /* filter handle (for remove / unsubscribe operations) */
8065 #define       MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
8066 #define       MC_CMD_FILTER_OP_IN_HANDLE_LEN 8
8067 #define       MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
8068 #define       MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8
8069 /* The port ID associated with the v-adaptor which should contain this filter.
8070  */
8071 #define       MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12
8072 #define       MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4
8073 /* fields to include in match criteria */
8074 #define       MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16
8075 #define       MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4
8076 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
8077 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1
8078 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1
8079 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1
8080 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2
8081 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1
8082 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3
8083 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1
8084 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
8085 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1
8086 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5
8087 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1
8088 #define        MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6
8089 #define        MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1
8090 #define        MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7
8091 #define        MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1
8092 #define        MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8
8093 #define        MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1
8094 #define        MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9
8095 #define        MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1
8096 #define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10
8097 #define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1
8098 #define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11
8099 #define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1
8100 #define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
8101 #define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
8102 #define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
8103 #define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
8104 /* receive destination */
8105 #define       MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20
8106 #define       MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4
8107 /* enum: drop packets */
8108 #define          MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0
8109 /* enum: receive to host */
8110 #define          MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1
8111 /* enum: receive to MC */
8112 #define          MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2
8113 /* enum: loop back to TXDP 0 */
8114 #define          MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3
8115 /* enum: loop back to TXDP 1 */
8116 #define          MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4
8117 /* receive queue handle (for multiple queue modes, this is the base queue) */
8118 #define       MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24
8119 #define       MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4
8120 /* receive mode */
8121 #define       MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28
8122 #define       MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4
8123 /* enum: receive to just the specified queue */
8124 #define          MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0
8125 /* enum: receive to multiple queues using RSS context */
8126 #define          MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1
8127 /* enum: receive to multiple queues using .1p mapping */
8128 #define          MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2
8129 /* enum: install a filter entry that will never match; for test purposes only
8130  */
8131 #define          MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
8132 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
8133  * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
8134  * MC_CMD_DOT1P_MAPPING_ALLOC.
8135  */
8136 #define       MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32
8137 #define       MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4
8138 /* transmit domain (reserved; set to 0) */
8139 #define       MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36
8140 #define       MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4
8141 /* transmit destination (either set the MAC and/or PM bits for explicit
8142  * control, or set this field to TX_DEST_DEFAULT for sensible default
8143  * behaviour)
8144  */
8145 #define       MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40
8146 #define       MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4
8147 /* enum: request default behaviour (based on filter type) */
8148 #define          MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
8149 #define        MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
8150 #define        MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1
8151 #define        MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1
8152 #define        MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1
8153 /* source MAC address to match (as bytes in network order) */
8154 #define       MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44
8155 #define       MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6
8156 /* source port to match (as bytes in network order) */
8157 #define       MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50
8158 #define       MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2
8159 /* destination MAC address to match (as bytes in network order) */
8160 #define       MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52
8161 #define       MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6
8162 /* destination port to match (as bytes in network order) */
8163 #define       MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58
8164 #define       MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2
8165 /* Ethernet type to match (as bytes in network order) */
8166 #define       MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60
8167 #define       MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2
8168 /* Inner VLAN tag to match (as bytes in network order) */
8169 #define       MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62
8170 #define       MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2
8171 /* Outer VLAN tag to match (as bytes in network order) */
8172 #define       MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64
8173 #define       MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2
8174 /* IP protocol to match (in low byte; set high byte to 0) */
8175 #define       MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66
8176 #define       MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2
8177 /* Firmware defined register 0 to match (reserved; set to 0) */
8178 #define       MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68
8179 #define       MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4
8180 /* Firmware defined register 1 to match (reserved; set to 0) */
8181 #define       MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72
8182 #define       MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4
8183 /* source IP address to match (as bytes in network order; set last 12 bytes to
8184  * 0 for IPv4 address)
8185  */
8186 #define       MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76
8187 #define       MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16
8188 /* destination IP address to match (as bytes in network order; set last 12
8189  * bytes to 0 for IPv4 address)
8190  */
8191 #define       MC_CMD_FILTER_OP_IN_DST_IP_OFST 92
8192 #define       MC_CMD_FILTER_OP_IN_DST_IP_LEN 16
8193 
8194 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to
8195  * include handling of VXLAN/NVGRE encapsulated frame filtering (which is
8196  * supported on Medford only).
8197  */
8198 #define    MC_CMD_FILTER_OP_EXT_IN_LEN 172
8199 /* identifies the type of operation requested */
8200 #define       MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0
8201 #define       MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4
8202 /*            Enum values, see field(s): */
8203 /*               MC_CMD_FILTER_OP_IN/OP */
8204 /* filter handle (for remove / unsubscribe operations) */
8205 #define       MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4
8206 #define       MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8
8207 #define       MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4
8208 #define       MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8
8209 /* The port ID associated with the v-adaptor which should contain this filter.
8210  */
8211 #define       MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12
8212 #define       MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4
8213 /* fields to include in match criteria */
8214 #define       MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16
8215 #define       MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4
8216 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0
8217 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1
8218 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1
8219 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1
8220 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2
8221 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1
8222 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3
8223 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1
8224 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4
8225 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1
8226 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5
8227 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1
8228 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6
8229 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1
8230 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7
8231 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1
8232 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8
8233 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1
8234 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9
8235 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1
8236 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10
8237 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1
8238 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11
8239 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1
8240 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12
8241 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1
8242 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13
8243 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1
8244 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14
8245 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
8246 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15
8247 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
8248 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16
8249 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1
8250 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17
8251 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1
8252 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18
8253 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
8254 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19
8255 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
8256 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20
8257 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
8258 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21
8259 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
8260 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22
8261 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1
8262 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23
8263 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1
8264 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24
8265 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
8266 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25
8267 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
8268 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
8269 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
8270 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
8271 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
8272 /* receive destination */
8273 #define       MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20
8274 #define       MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4
8275 /* enum: drop packets */
8276 #define          MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0
8277 /* enum: receive to host */
8278 #define          MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1
8279 /* enum: receive to MC */
8280 #define          MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2
8281 /* enum: loop back to TXDP 0 */
8282 #define          MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3
8283 /* enum: loop back to TXDP 1 */
8284 #define          MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4
8285 /* receive queue handle (for multiple queue modes, this is the base queue) */
8286 #define       MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24
8287 #define       MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4
8288 /* receive mode */
8289 #define       MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28
8290 #define       MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4
8291 /* enum: receive to just the specified queue */
8292 #define          MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0
8293 /* enum: receive to multiple queues using RSS context */
8294 #define          MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1
8295 /* enum: receive to multiple queues using .1p mapping */
8296 #define          MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2
8297 /* enum: install a filter entry that will never match; for test purposes only
8298  */
8299 #define          MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
8300 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
8301  * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
8302  * MC_CMD_DOT1P_MAPPING_ALLOC.
8303  */
8304 #define       MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32
8305 #define       MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4
8306 /* transmit domain (reserved; set to 0) */
8307 #define       MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36
8308 #define       MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4
8309 /* transmit destination (either set the MAC and/or PM bits for explicit
8310  * control, or set this field to TX_DEST_DEFAULT for sensible default
8311  * behaviour)
8312  */
8313 #define       MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40
8314 #define       MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4
8315 /* enum: request default behaviour (based on filter type) */
8316 #define          MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff
8317 #define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0
8318 #define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1
8319 #define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1
8320 #define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1
8321 /* source MAC address to match (as bytes in network order) */
8322 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44
8323 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6
8324 /* source port to match (as bytes in network order) */
8325 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50
8326 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2
8327 /* destination MAC address to match (as bytes in network order) */
8328 #define       MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52
8329 #define       MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6
8330 /* destination port to match (as bytes in network order) */
8331 #define       MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58
8332 #define       MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2
8333 /* Ethernet type to match (as bytes in network order) */
8334 #define       MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60
8335 #define       MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2
8336 /* Inner VLAN tag to match (as bytes in network order) */
8337 #define       MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62
8338 #define       MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2
8339 /* Outer VLAN tag to match (as bytes in network order) */
8340 #define       MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64
8341 #define       MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2
8342 /* IP protocol to match (in low byte; set high byte to 0) */
8343 #define       MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66
8344 #define       MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2
8345 /* Firmware defined register 0 to match (reserved; set to 0) */
8346 #define       MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68
8347 #define       MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4
8348 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP
8349  * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
8350  * VXLAN/NVGRE, or 1 for Geneve)
8351  */
8352 #define       MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72
8353 #define       MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4
8354 #define        MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0
8355 #define        MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24
8356 #define        MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24
8357 #define        MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8
8358 /* enum: Match VXLAN traffic with this VNI */
8359 #define          MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0
8360 /* enum: Match Geneve traffic with this VNI */
8361 #define          MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1
8362 /* enum: Reserved for experimental development use */
8363 #define          MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe
8364 #define        MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0
8365 #define        MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24
8366 #define        MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24
8367 #define        MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8
8368 /* enum: Match NVGRE traffic with this VSID */
8369 #define          MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0
8370 /* source IP address to match (as bytes in network order; set last 12 bytes to
8371  * 0 for IPv4 address)
8372  */
8373 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76
8374 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16
8375 /* destination IP address to match (as bytes in network order; set last 12
8376  * bytes to 0 for IPv4 address)
8377  */
8378 #define       MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92
8379 #define       MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16
8380 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network
8381  * order)
8382  */
8383 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108
8384 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6
8385 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */
8386 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114
8387 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2
8388 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in
8389  * network order)
8390  */
8391 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116
8392 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6
8393 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network
8394  * order)
8395  */
8396 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122
8397 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2
8398 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)
8399  */
8400 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124
8401 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2
8402 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)
8403  */
8404 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126
8405 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2
8406 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)
8407  */
8408 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128
8409 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2
8410 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to
8411  * 0)
8412  */
8413 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130
8414 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2
8415 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
8416  * to 0)
8417  */
8418 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132
8419 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4
8420 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
8421  * to 0)
8422  */
8423 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136
8424 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4
8425 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network
8426  * order; set last 12 bytes to 0 for IPv4 address)
8427  */
8428 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140
8429 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16
8430 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network
8431  * order; set last 12 bytes to 0 for IPv4 address)
8432  */
8433 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156
8434 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16
8435 
8436 /* MC_CMD_FILTER_OP_V3_IN msgrequest: FILTER_OP extension to support additional
8437  * filter actions for Intel's DPDK (Data Plane Development Kit, dpdk.org) via
8438  * its rte_flow API. This extension is only useful with the sfc_efx driver
8439  * included as part of DPDK, used in conjunction with the dpdk datapath
8440  * firmware variant.
8441  */
8442 #define    MC_CMD_FILTER_OP_V3_IN_LEN 180
8443 /* identifies the type of operation requested */
8444 #define       MC_CMD_FILTER_OP_V3_IN_OP_OFST 0
8445 #define       MC_CMD_FILTER_OP_V3_IN_OP_LEN 4
8446 /*            Enum values, see field(s): */
8447 /*               MC_CMD_FILTER_OP_IN/OP */
8448 /* filter handle (for remove / unsubscribe operations) */
8449 #define       MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4
8450 #define       MC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 8
8451 #define       MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4
8452 #define       MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 8
8453 /* The port ID associated with the v-adaptor which should contain this filter.
8454  */
8455 #define       MC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 12
8456 #define       MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 4
8457 /* fields to include in match criteria */
8458 #define       MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_OFST 16
8459 #define       MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4
8460 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0
8461 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 1
8462 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 1
8463 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 1
8464 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_LBN 2
8465 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 1
8466 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_LBN 3
8467 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 1
8468 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4
8469 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 1
8470 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_LBN 5
8471 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 1
8472 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_LBN 6
8473 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 1
8474 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_LBN 7
8475 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 1
8476 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_LBN 8
8477 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 1
8478 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_LBN 9
8479 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 1
8480 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_LBN 10
8481 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 1
8482 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_LBN 11
8483 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 1
8484 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_LBN 12
8485 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 1
8486 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_LBN 13
8487 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 1
8488 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_LBN 14
8489 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
8490 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_LBN 15
8491 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
8492 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_LBN 16
8493 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 1
8494 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_LBN 17
8495 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 1
8496 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_LBN 18
8497 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
8498 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_LBN 19
8499 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
8500 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_LBN 20
8501 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
8502 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_LBN 21
8503 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
8504 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_LBN 22
8505 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 1
8506 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_LBN 23
8507 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 1
8508 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24
8509 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
8510 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25
8511 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
8512 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
8513 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
8514 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
8515 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
8516 /* receive destination */
8517 #define       MC_CMD_FILTER_OP_V3_IN_RX_DEST_OFST 20
8518 #define       MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4
8519 /* enum: drop packets */
8520 #define          MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0
8521 /* enum: receive to host */
8522 #define          MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1
8523 /* enum: receive to MC */
8524 #define          MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2
8525 /* enum: loop back to TXDP 0 */
8526 #define          MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3
8527 /* enum: loop back to TXDP 1 */
8528 #define          MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4
8529 /* receive queue handle (for multiple queue modes, this is the base queue) */
8530 #define       MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_OFST 24
8531 #define       MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4
8532 /* receive mode */
8533 #define       MC_CMD_FILTER_OP_V3_IN_RX_MODE_OFST 28
8534 #define       MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4
8535 /* enum: receive to just the specified queue */
8536 #define          MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0
8537 /* enum: receive to multiple queues using RSS context */
8538 #define          MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1
8539 /* enum: receive to multiple queues using .1p mapping */
8540 #define          MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2
8541 /* enum: install a filter entry that will never match; for test purposes only
8542  */
8543 #define          MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
8544 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
8545  * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
8546  * MC_CMD_DOT1P_MAPPING_ALLOC.
8547  */
8548 #define       MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_OFST 32
8549 #define       MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 4
8550 /* transmit domain (reserved; set to 0) */
8551 #define       MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_OFST 36
8552 #define       MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 4
8553 /* transmit destination (either set the MAC and/or PM bits for explicit
8554  * control, or set this field to TX_DEST_DEFAULT for sensible default
8555  * behaviour)
8556  */
8557 #define       MC_CMD_FILTER_OP_V3_IN_TX_DEST_OFST 40
8558 #define       MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4
8559 /* enum: request default behaviour (based on filter type) */
8560 #define          MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff
8561 #define        MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0
8562 #define        MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 1
8563 #define        MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 1
8564 #define        MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 1
8565 /* source MAC address to match (as bytes in network order) */
8566 #define       MC_CMD_FILTER_OP_V3_IN_SRC_MAC_OFST 44
8567 #define       MC_CMD_FILTER_OP_V3_IN_SRC_MAC_LEN 6
8568 /* source port to match (as bytes in network order) */
8569 #define       MC_CMD_FILTER_OP_V3_IN_SRC_PORT_OFST 50
8570 #define       MC_CMD_FILTER_OP_V3_IN_SRC_PORT_LEN 2
8571 /* destination MAC address to match (as bytes in network order) */
8572 #define       MC_CMD_FILTER_OP_V3_IN_DST_MAC_OFST 52
8573 #define       MC_CMD_FILTER_OP_V3_IN_DST_MAC_LEN 6
8574 /* destination port to match (as bytes in network order) */
8575 #define       MC_CMD_FILTER_OP_V3_IN_DST_PORT_OFST 58
8576 #define       MC_CMD_FILTER_OP_V3_IN_DST_PORT_LEN 2
8577 /* Ethernet type to match (as bytes in network order) */
8578 #define       MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_OFST 60
8579 #define       MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_LEN 2
8580 /* Inner VLAN tag to match (as bytes in network order) */
8581 #define       MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_OFST 62
8582 #define       MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_LEN 2
8583 /* Outer VLAN tag to match (as bytes in network order) */
8584 #define       MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_OFST 64
8585 #define       MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_LEN 2
8586 /* IP protocol to match (in low byte; set high byte to 0) */
8587 #define       MC_CMD_FILTER_OP_V3_IN_IP_PROTO_OFST 66
8588 #define       MC_CMD_FILTER_OP_V3_IN_IP_PROTO_LEN 2
8589 /* Firmware defined register 0 to match (reserved; set to 0) */
8590 #define       MC_CMD_FILTER_OP_V3_IN_FWDEF0_OFST 68
8591 #define       MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 4
8592 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP
8593  * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
8594  * VXLAN/NVGRE, or 1 for Geneve)
8595  */
8596 #define       MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_OFST 72
8597 #define       MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4
8598 #define        MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0
8599 #define        MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_WIDTH 24
8600 #define        MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_LBN 24
8601 #define        MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_WIDTH 8
8602 /* enum: Match VXLAN traffic with this VNI */
8603 #define          MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0
8604 /* enum: Match Geneve traffic with this VNI */
8605 #define          MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1
8606 /* enum: Reserved for experimental development use */
8607 #define          MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe
8608 #define        MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0
8609 #define        MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_WIDTH 24
8610 #define        MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_LBN 24
8611 #define        MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_WIDTH 8
8612 /* enum: Match NVGRE traffic with this VSID */
8613 #define          MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0
8614 /* source IP address to match (as bytes in network order; set last 12 bytes to
8615  * 0 for IPv4 address)
8616  */
8617 #define       MC_CMD_FILTER_OP_V3_IN_SRC_IP_OFST 76
8618 #define       MC_CMD_FILTER_OP_V3_IN_SRC_IP_LEN 16
8619 /* destination IP address to match (as bytes in network order; set last 12
8620  * bytes to 0 for IPv4 address)
8621  */
8622 #define       MC_CMD_FILTER_OP_V3_IN_DST_IP_OFST 92
8623 #define       MC_CMD_FILTER_OP_V3_IN_DST_IP_LEN 16
8624 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network
8625  * order)
8626  */
8627 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_OFST 108
8628 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_LEN 6
8629 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */
8630 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_OFST 114
8631 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_LEN 2
8632 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in
8633  * network order)
8634  */
8635 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_OFST 116
8636 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_LEN 6
8637 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network
8638  * order)
8639  */
8640 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_OFST 122
8641 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_LEN 2
8642 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)
8643  */
8644 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_OFST 124
8645 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_LEN 2
8646 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)
8647  */
8648 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_OFST 126
8649 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_LEN 2
8650 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)
8651  */
8652 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_OFST 128
8653 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_LEN 2
8654 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to
8655  * 0)
8656  */
8657 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_OFST 130
8658 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_LEN 2
8659 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
8660  * to 0)
8661  */
8662 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_OFST 132
8663 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 4
8664 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
8665  * to 0)
8666  */
8667 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_OFST 136
8668 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 4
8669 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network
8670  * order; set last 12 bytes to 0 for IPv4 address)
8671  */
8672 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_OFST 140
8673 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_LEN 16
8674 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network
8675  * order; set last 12 bytes to 0 for IPv4 address)
8676  */
8677 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 156
8678 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 16
8679 /* Set an action for all packets matching this filter. The DPDK driver and dpdk
8680  * f/w variant use their own specific delivery structures, which are documented
8681  * in the DPDK Firmware Driver Interface (SF-119419-TC). Requesting anything
8682  * other than MATCH_ACTION_NONE when the NIC is running another f/w variant
8683  * will cause the filter insertion to fail with ENOTSUP.
8684  */
8685 #define       MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_OFST 172
8686 #define       MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4
8687 /* enum: do nothing extra */
8688 #define          MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0
8689 /* enum: Set the match flag in the packet prefix for packets matching the
8690  * filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to
8691  * support the DPDK rte_flow "FLAG" action.
8692  */
8693 #define          MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1
8694 /* enum: Insert MATCH_MARK_VALUE into the packet prefix for packets matching
8695  * the filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to
8696  * support the DPDK rte_flow "MARK" action.
8697  */
8698 #define          MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2
8699 /* the mark value for MATCH_ACTION_MARK */
8700 #define       MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_OFST 176
8701 #define       MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4
8702 
8703 /* MC_CMD_FILTER_OP_OUT msgresponse */
8704 #define    MC_CMD_FILTER_OP_OUT_LEN 12
8705 /* identifies the type of operation requested */
8706 #define       MC_CMD_FILTER_OP_OUT_OP_OFST 0
8707 #define       MC_CMD_FILTER_OP_OUT_OP_LEN 4
8708 /*            Enum values, see field(s): */
8709 /*               MC_CMD_FILTER_OP_IN/OP */
8710 /* Returned filter handle (for insert / subscribe operations). Note that these
8711  * handles should be considered opaque to the host, although a value of
8712  * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
8713  */
8714 #define       MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
8715 #define       MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8
8716 #define       MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
8717 #define       MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8
8718 /* enum: guaranteed invalid filter handle (low 32 bits) */
8719 #define          MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
8720 /* enum: guaranteed invalid filter handle (high 32 bits) */
8721 #define          MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff
8722 
8723 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */
8724 #define    MC_CMD_FILTER_OP_EXT_OUT_LEN 12
8725 /* identifies the type of operation requested */
8726 #define       MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0
8727 #define       MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4
8728 /*            Enum values, see field(s): */
8729 /*               MC_CMD_FILTER_OP_EXT_IN/OP */
8730 /* Returned filter handle (for insert / subscribe operations). Note that these
8731  * handles should be considered opaque to the host, although a value of
8732  * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
8733  */
8734 #define       MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4
8735 #define       MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8
8736 #define       MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4
8737 #define       MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8
8738 /*            Enum values, see field(s): */
8739 /*               MC_CMD_FILTER_OP_OUT/HANDLE */
8740 
8741 
8742 /***********************************/
8743 /* MC_CMD_GET_PARSER_DISP_INFO
8744  * Get information related to the parser-dispatcher subsystem
8745  */
8746 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4
8747 
8748 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8749 
8750 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */
8751 #define    MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4
8752 /* identifies the type of operation requested */
8753 #define       MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0
8754 #define       MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4
8755 /* enum: read the list of supported RX filter matches */
8756 #define          MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1
8757 /* enum: read flags indicating restrictions on filter insertion for the calling
8758  * client
8759  */
8760 #define          MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2
8761 /* enum: read properties relating to security rules (Medford-only; for use by
8762  * SolarSecure apps, not directly by drivers. See SF-114946-SW.)
8763  */
8764 #define          MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3
8765 /* enum: read the list of supported RX filter matches for VXLAN/NVGRE
8766  * encapsulated frames, which follow a different match sequence to normal
8767  * frames (Medford only)
8768  */
8769 #define          MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4
8770 
8771 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */
8772 #define    MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8
8773 #define    MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252
8774 #define    MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))
8775 /* identifies the type of operation requested */
8776 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0
8777 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4
8778 /*            Enum values, see field(s): */
8779 /*               MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
8780 /* number of supported match types */
8781 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4
8782 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4
8783 /* array of supported match types (valid MATCH_FIELDS values for
8784  * MC_CMD_FILTER_OP) sorted in decreasing priority order
8785  */
8786 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8
8787 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4
8788 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0
8789 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61
8790 
8791 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */
8792 #define    MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8
8793 /* identifies the type of operation requested */
8794 #define       MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0
8795 #define       MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4
8796 /*            Enum values, see field(s): */
8797 /*               MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
8798 /* bitfield of filter insertion restrictions */
8799 #define       MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4
8800 #define       MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4
8801 #define        MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0
8802 #define        MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1
8803 
8804 
8805 /***********************************/
8806 /* MC_CMD_PARSER_DISP_RW
8807  * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging.
8808  * Please note that this interface is only of use to debug tools which have
8809  * knowledge of firmware and hardware data structures; nothing here is intended
8810  * for use by normal driver code. Note that although this command is in the
8811  * Admin privilege group, in tamperproof adapters, only read operations are
8812  * permitted.
8813  */
8814 #define MC_CMD_PARSER_DISP_RW 0xe5
8815 
8816 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8817 
8818 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */
8819 #define    MC_CMD_PARSER_DISP_RW_IN_LEN 32
8820 /* identifies the target of the operation */
8821 #define       MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0
8822 #define       MC_CMD_PARSER_DISP_RW_IN_TARGET_LEN 4
8823 /* enum: RX dispatcher CPU */
8824 #define          MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0
8825 /* enum: TX dispatcher CPU */
8826 #define          MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1
8827 /* enum: Lookup engine (with original metadata format). Deprecated; used only
8828  * by cmdclient as a fallback for very old Huntington firmware, and not
8829  * supported in firmware beyond v6.4.0.1005. Use LUE_VERSIONED_METADATA
8830  * instead.
8831  */
8832 #define          MC_CMD_PARSER_DISP_RW_IN_LUE 0x2
8833 /* enum: Lookup engine (with requested metadata format) */
8834 #define          MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3
8835 /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */
8836 #define          MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0
8837 /* enum: RX1 dispatcher CPU (only valid for Medford) */
8838 #define          MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4
8839 /* enum: Miscellaneous other state (only valid for Medford) */
8840 #define          MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5
8841 /* identifies the type of operation requested */
8842 #define       MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4
8843 #define       MC_CMD_PARSER_DISP_RW_IN_OP_LEN 4
8844 /* enum: Read a word of DICPU DMEM or a LUE entry */
8845 #define          MC_CMD_PARSER_DISP_RW_IN_READ 0x0
8846 /* enum: Write a word of DICPU DMEM or a LUE entry. Not permitted on
8847  * tamperproof adapters.
8848  */
8849 #define          MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1
8850 /* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not
8851  * permitted on tamperproof adapters.
8852  */
8853 #define          MC_CMD_PARSER_DISP_RW_IN_RMW 0x2
8854 /* data memory address (DICPU targets) or LUE index (LUE targets) */
8855 #define       MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8
8856 #define       MC_CMD_PARSER_DISP_RW_IN_ADDRESS_LEN 4
8857 /* selector (for MISC_STATE target) */
8858 #define       MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8
8859 #define       MC_CMD_PARSER_DISP_RW_IN_SELECTOR_LEN 4
8860 /* enum: Port to datapath mapping */
8861 #define          MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1
8862 /* value to write (for DMEM writes) */
8863 #define       MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12
8864 #define       MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_LEN 4
8865 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */
8866 #define       MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12
8867 #define       MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_LEN 4
8868 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */
8869 #define       MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16
8870 #define       MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_LEN 4
8871 /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */
8872 #define       MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12
8873 #define       MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_LEN 4
8874 /* value to write (for LUE writes) */
8875 #define       MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12
8876 #define       MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20
8877 
8878 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */
8879 #define    MC_CMD_PARSER_DISP_RW_OUT_LEN 52
8880 /* value read (for DMEM reads) */
8881 #define       MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0
8882 #define       MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_LEN 4
8883 /* value read (for LUE reads) */
8884 #define       MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0
8885 #define       MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20
8886 /* up to 8 32-bit words of additional soft state from the LUE manager (the
8887  * exact content is firmware-dependent and intended only for debug use)
8888  */
8889 #define       MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20
8890 #define       MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32
8891 /* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */
8892 #define       MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0
8893 #define       MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4
8894 #define       MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4
8895 #define          MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */
8896 #define          MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */
8897 
8898 
8899 /***********************************/
8900 /* MC_CMD_GET_PF_COUNT
8901  * Get number of PFs on the device.
8902  */
8903 #define MC_CMD_GET_PF_COUNT 0xb6
8904 
8905 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8906 
8907 /* MC_CMD_GET_PF_COUNT_IN msgrequest */
8908 #define    MC_CMD_GET_PF_COUNT_IN_LEN 0
8909 
8910 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */
8911 #define    MC_CMD_GET_PF_COUNT_OUT_LEN 1
8912 /* Identifies the number of PFs on the device. */
8913 #define       MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0
8914 #define       MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1
8915 
8916 
8917 /***********************************/
8918 /* MC_CMD_SET_PF_COUNT
8919  * Set number of PFs on the device.
8920  */
8921 #define MC_CMD_SET_PF_COUNT 0xb7
8922 
8923 /* MC_CMD_SET_PF_COUNT_IN msgrequest */
8924 #define    MC_CMD_SET_PF_COUNT_IN_LEN 4
8925 /* New number of PFs on the device. */
8926 #define       MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0
8927 #define       MC_CMD_SET_PF_COUNT_IN_PF_COUNT_LEN 4
8928 
8929 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */
8930 #define    MC_CMD_SET_PF_COUNT_OUT_LEN 0
8931 
8932 
8933 /***********************************/
8934 /* MC_CMD_GET_PORT_ASSIGNMENT
8935  * Get port assignment for current PCI function.
8936  */
8937 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
8938 
8939 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8940 
8941 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */
8942 #define    MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
8943 
8944 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */
8945 #define    MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
8946 /* Identifies the port assignment for this function. */
8947 #define       MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
8948 #define       MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4
8949 
8950 
8951 /***********************************/
8952 /* MC_CMD_SET_PORT_ASSIGNMENT
8953  * Set port assignment for current PCI function.
8954  */
8955 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9
8956 
8957 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8958 
8959 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */
8960 #define    MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4
8961 /* Identifies the port assignment for this function. */
8962 #define       MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0
8963 #define       MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4
8964 
8965 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */
8966 #define    MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0
8967 
8968 
8969 /***********************************/
8970 /* MC_CMD_ALLOC_VIS
8971  * Allocate VIs for current PCI function.
8972  */
8973 #define MC_CMD_ALLOC_VIS 0x8b
8974 
8975 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8976 
8977 /* MC_CMD_ALLOC_VIS_IN msgrequest */
8978 #define    MC_CMD_ALLOC_VIS_IN_LEN 8
8979 /* The minimum number of VIs that is acceptable */
8980 #define       MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0
8981 #define       MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4
8982 /* The maximum number of VIs that would be useful */
8983 #define       MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4
8984 #define       MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4
8985 
8986 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.
8987  * Use extended version in new code.
8988  */
8989 #define    MC_CMD_ALLOC_VIS_OUT_LEN 8
8990 /* The number of VIs allocated on this function */
8991 #define       MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0
8992 #define       MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4
8993 /* The base absolute VI number allocated to this function. Required to
8994  * correctly interpret wakeup events.
8995  */
8996 #define       MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4
8997 #define       MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4
8998 
8999 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */
9000 #define    MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12
9001 /* The number of VIs allocated on this function */
9002 #define       MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0
9003 #define       MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4
9004 /* The base absolute VI number allocated to this function. Required to
9005  * correctly interpret wakeup events.
9006  */
9007 #define       MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4
9008 #define       MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4
9009 /* Function's port vi_shift value (always 0 on Huntington) */
9010 #define       MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8
9011 #define       MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4
9012 
9013 
9014 /***********************************/
9015 /* MC_CMD_FREE_VIS
9016  * Free VIs for current PCI function. Any linked PIO buffers will be unlinked,
9017  * but not freed.
9018  */
9019 #define MC_CMD_FREE_VIS 0x8c
9020 
9021 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9022 
9023 /* MC_CMD_FREE_VIS_IN msgrequest */
9024 #define    MC_CMD_FREE_VIS_IN_LEN 0
9025 
9026 /* MC_CMD_FREE_VIS_OUT msgresponse */
9027 #define    MC_CMD_FREE_VIS_OUT_LEN 0
9028 
9029 
9030 /***********************************/
9031 /* MC_CMD_GET_SRIOV_CFG
9032  * Get SRIOV config for this PF.
9033  */
9034 #define MC_CMD_GET_SRIOV_CFG 0xba
9035 
9036 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9037 
9038 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */
9039 #define    MC_CMD_GET_SRIOV_CFG_IN_LEN 0
9040 
9041 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */
9042 #define    MC_CMD_GET_SRIOV_CFG_OUT_LEN 20
9043 /* Number of VFs currently enabled. */
9044 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0
9045 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4
9046 /* Max number of VFs before sriov stride and offset may need to be changed. */
9047 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4
9048 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4
9049 #define       MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8
9050 #define       MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4
9051 #define        MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
9052 #define        MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1
9053 /* RID offset of first VF from PF. */
9054 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12
9055 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4
9056 /* RID offset of each subsequent VF from the previous. */
9057 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16
9058 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4
9059 
9060 
9061 /***********************************/
9062 /* MC_CMD_SET_SRIOV_CFG
9063  * Set SRIOV config for this PF.
9064  */
9065 #define MC_CMD_SET_SRIOV_CFG 0xbb
9066 
9067 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
9068 
9069 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */
9070 #define    MC_CMD_SET_SRIOV_CFG_IN_LEN 20
9071 /* Number of VFs currently enabled. */
9072 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0
9073 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4
9074 /* Max number of VFs before sriov stride and offset may need to be changed. */
9075 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4
9076 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4
9077 #define       MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8
9078 #define       MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4
9079 #define        MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0
9080 #define        MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1
9081 /* RID offset of first VF from PF, or 0 for no change, or
9082  * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset.
9083  */
9084 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12
9085 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4
9086 /* RID offset of each subsequent VF from the previous, 0 for no change, or
9087  * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride.
9088  */
9089 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16
9090 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4
9091 
9092 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */
9093 #define    MC_CMD_SET_SRIOV_CFG_OUT_LEN 0
9094 
9095 
9096 /***********************************/
9097 /* MC_CMD_GET_VI_ALLOC_INFO
9098  * Get information about number of VI's and base VI number allocated to this
9099  * function.
9100  */
9101 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d
9102 
9103 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9104 
9105 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */
9106 #define    MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0
9107 
9108 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */
9109 #define    MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12
9110 /* The number of VIs allocated on this function */
9111 #define       MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0
9112 #define       MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4
9113 /* The base absolute VI number allocated to this function. Required to
9114  * correctly interpret wakeup events.
9115  */
9116 #define       MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4
9117 #define       MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4
9118 /* Function's port vi_shift value (always 0 on Huntington) */
9119 #define       MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8
9120 #define       MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4
9121 
9122 
9123 /***********************************/
9124 /* MC_CMD_DUMP_VI_STATE
9125  * For CmdClient use. Dump pertinent information on a specific absolute VI.
9126  */
9127 #define MC_CMD_DUMP_VI_STATE 0x8e
9128 
9129 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9130 
9131 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */
9132 #define    MC_CMD_DUMP_VI_STATE_IN_LEN 4
9133 /* The VI number to query. */
9134 #define       MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0
9135 #define       MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4
9136 
9137 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */
9138 #define    MC_CMD_DUMP_VI_STATE_OUT_LEN 96
9139 /* The PF part of the function owning this VI. */
9140 #define       MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0
9141 #define       MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2
9142 /* The VF part of the function owning this VI. */
9143 #define       MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2
9144 #define       MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2
9145 /* Base of VIs allocated to this function. */
9146 #define       MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4
9147 #define       MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2
9148 /* Count of VIs allocated to the owner function. */
9149 #define       MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6
9150 #define       MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2
9151 /* Base interrupt vector allocated to this function. */
9152 #define       MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8
9153 #define       MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2
9154 /* Number of interrupt vectors allocated to this function. */
9155 #define       MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10
9156 #define       MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2
9157 /* Raw evq ptr table data. */
9158 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12
9159 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8
9160 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12
9161 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16
9162 /* Raw evq timer table data. */
9163 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20
9164 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8
9165 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20
9166 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24
9167 /* Combined metadata field. */
9168 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28
9169 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4
9170 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0
9171 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16
9172 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16
9173 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8
9174 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24
9175 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8
9176 /* TXDPCPU raw table data for queue. */
9177 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32
9178 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8
9179 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32
9180 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36
9181 /* TXDPCPU raw table data for queue. */
9182 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40
9183 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8
9184 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40
9185 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44
9186 /* TXDPCPU raw table data for queue. */
9187 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48
9188 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8
9189 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48
9190 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52
9191 /* Combined metadata field. */
9192 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56
9193 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8
9194 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56
9195 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60
9196 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0
9197 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16
9198 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16
9199 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8
9200 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24
9201 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8
9202 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32
9203 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8
9204 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40
9205 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24
9206 /* RXDPCPU raw table data for queue. */
9207 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64
9208 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8
9209 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64
9210 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68
9211 /* RXDPCPU raw table data for queue. */
9212 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72
9213 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8
9214 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72
9215 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76
9216 /* Reserved, currently 0. */
9217 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80
9218 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8
9219 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80
9220 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84
9221 /* Combined metadata field. */
9222 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88
9223 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8
9224 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88
9225 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92
9226 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0
9227 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16
9228 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16
9229 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8
9230 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24
9231 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8
9232 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32
9233 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8
9234 
9235 
9236 /***********************************/
9237 /* MC_CMD_ALLOC_PIOBUF
9238  * Allocate a push I/O buffer for later use with a tx queue.
9239  */
9240 #define MC_CMD_ALLOC_PIOBUF 0x8f
9241 
9242 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
9243 
9244 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */
9245 #define    MC_CMD_ALLOC_PIOBUF_IN_LEN 0
9246 
9247 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */
9248 #define    MC_CMD_ALLOC_PIOBUF_OUT_LEN 4
9249 /* Handle for allocated push I/O buffer. */
9250 #define       MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0
9251 #define       MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4
9252 
9253 
9254 /***********************************/
9255 /* MC_CMD_FREE_PIOBUF
9256  * Free a push I/O buffer.
9257  */
9258 #define MC_CMD_FREE_PIOBUF 0x90
9259 
9260 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
9261 
9262 /* MC_CMD_FREE_PIOBUF_IN msgrequest */
9263 #define    MC_CMD_FREE_PIOBUF_IN_LEN 4
9264 /* Handle for allocated push I/O buffer. */
9265 #define       MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
9266 #define       MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
9267 
9268 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */
9269 #define    MC_CMD_FREE_PIOBUF_OUT_LEN 0
9270 
9271 
9272 /***********************************/
9273 /* MC_CMD_GET_VI_TLP_PROCESSING
9274  * Get TLP steering and ordering information for a VI.
9275  */
9276 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0
9277 
9278 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9279 
9280 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */
9281 #define    MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4
9282 /* VI number to get information for. */
9283 #define       MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
9284 #define       MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
9285 
9286 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */
9287 #define    MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4
9288 /* Transaction processing steering hint 1 for use with the Rx Queue. */
9289 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0
9290 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1
9291 /* Transaction processing steering hint 2 for use with the Ev Queue. */
9292 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1
9293 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1
9294 /* Use Relaxed ordering model for TLPs on this VI. */
9295 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16
9296 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1
9297 /* Use ID based ordering for TLPs on this VI. */
9298 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17
9299 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1
9300 /* Set no snoop bit for TLPs on this VI. */
9301 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18
9302 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1
9303 /* Enable TPH for TLPs on this VI. */
9304 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19
9305 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1
9306 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0
9307 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4
9308 
9309 
9310 /***********************************/
9311 /* MC_CMD_SET_VI_TLP_PROCESSING
9312  * Set TLP steering and ordering information for a VI.
9313  */
9314 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1
9315 
9316 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9317 
9318 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */
9319 #define    MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8
9320 /* VI number to set information for. */
9321 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
9322 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
9323 /* Transaction processing steering hint 1 for use with the Rx Queue. */
9324 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4
9325 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1
9326 /* Transaction processing steering hint 2 for use with the Ev Queue. */
9327 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5
9328 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1
9329 /* Use Relaxed ordering model for TLPs on this VI. */
9330 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48
9331 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1
9332 /* Use ID based ordering for TLPs on this VI. */
9333 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49
9334 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1
9335 /* Set the no snoop bit for TLPs on this VI. */
9336 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50
9337 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1
9338 /* Enable TPH for TLPs on this VI. */
9339 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51
9340 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1
9341 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4
9342 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 4
9343 
9344 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */
9345 #define    MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0
9346 
9347 
9348 /***********************************/
9349 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS
9350  * Get global PCIe steering and transaction processing configuration.
9351  */
9352 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc
9353 
9354 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
9355 
9356 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */
9357 #define    MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4
9358 #define       MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
9359 #define       MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
9360 /* enum: MISC. */
9361 #define          MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0
9362 /* enum: IDO. */
9363 #define          MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1
9364 /* enum: RO. */
9365 #define          MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2
9366 /* enum: TPH Type. */
9367 #define          MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3
9368 
9369 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
9370 #define    MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8
9371 #define       MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0
9372 #define       MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_LEN 4
9373 /*            Enum values, see field(s): */
9374 /*               MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */
9375 /* Amalgamated TLP info word. */
9376 #define       MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4
9377 #define       MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 4
9378 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0
9379 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1
9380 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1
9381 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31
9382 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0
9383 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1
9384 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1
9385 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1
9386 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2
9387 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1
9388 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3
9389 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1
9390 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4
9391 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28
9392 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0
9393 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1
9394 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1
9395 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1
9396 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2
9397 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1
9398 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3
9399 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29
9400 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0
9401 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
9402 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2
9403 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2
9404 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4
9405 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2
9406 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6
9407 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2
9408 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8
9409 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2
9410 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9
9411 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23
9412 
9413 
9414 /***********************************/
9415 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS
9416  * Set global PCIe steering and transaction processing configuration.
9417  */
9418 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd
9419 
9420 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN
9421 
9422 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */
9423 #define    MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8
9424 #define       MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
9425 #define       MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
9426 /*            Enum values, see field(s): */
9427 /*               MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */
9428 /* Amalgamated TLP info word. */
9429 #define       MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4
9430 #define       MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 4
9431 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0
9432 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1
9433 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0
9434 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1
9435 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1
9436 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1
9437 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2
9438 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1
9439 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3
9440 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1
9441 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0
9442 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1
9443 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1
9444 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1
9445 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2
9446 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1
9447 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0
9448 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
9449 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2
9450 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2
9451 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4
9452 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2
9453 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6
9454 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2
9455 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8
9456 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2
9457 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10
9458 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22
9459 
9460 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
9461 #define    MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0
9462 
9463 
9464 /***********************************/
9465 /* MC_CMD_SATELLITE_DOWNLOAD
9466  * Download a new set of images to the satellite CPUs from the host.
9467  */
9468 #define MC_CMD_SATELLITE_DOWNLOAD 0x91
9469 
9470 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN
9471 
9472 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs
9473  * are subtle, and so downloads must proceed in a number of phases.
9474  *
9475  * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0.
9476  *
9477  * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download
9478  * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should
9479  * be a checksum (a simple 32-bit sum) of the transferred data. An individual
9480  * download may be aborted using CHUNK_ID_ABORT.
9481  *
9482  * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15),
9483  * similar to PHASE_IMEMS.
9484  *
9485  * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0.
9486  *
9487  * After any error (a requested abort is not considered to be an error) the
9488  * sequence must be restarted from PHASE_RESET.
9489  */
9490 #define    MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20
9491 #define    MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252
9492 #define    MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num))
9493 /* Download phase. (Note: the IDLE phase is used internally and is never valid
9494  * in a command from the host.)
9495  */
9496 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0
9497 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_LEN 4
9498 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */
9499 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */
9500 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */
9501 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */
9502 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */
9503 /* Target for download. (These match the blob numbers defined in
9504  * mc_flash_layout.h.)
9505  */
9506 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4
9507 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_LEN 4
9508 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9509 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0
9510 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9511 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1
9512 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9513 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2
9514 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9515 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3
9516 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9517 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4
9518 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9519 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5
9520 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9521 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6
9522 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9523 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7
9524 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9525 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8
9526 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9527 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9
9528 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9529 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa
9530 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9531 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb
9532 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
9533 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc
9534 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
9535 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd
9536 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
9537 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe
9538 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
9539 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf
9540 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */
9541 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff
9542 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */
9543 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8
9544 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LEN 4
9545 /* enum: Last chunk, containing checksum rather than data */
9546 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff
9547 /* enum: Abort download of this item */
9548 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe
9549 /* Length of this chunk in bytes */
9550 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12
9551 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_LEN 4
9552 /* Data for this chunk */
9553 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16
9554 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4
9555 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1
9556 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59
9557 
9558 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */
9559 #define    MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8
9560 /* Same as MC_CMD_ERR field, but included as 0 in success cases */
9561 #define       MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0
9562 #define       MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_LEN 4
9563 /* Extra status information */
9564 #define       MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4
9565 #define       MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_LEN 4
9566 /* enum: Code download OK, completed. */
9567 #define          MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0
9568 /* enum: Code download aborted as requested. */
9569 #define          MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1
9570 /* enum: Code download OK so far, send next chunk. */
9571 #define          MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2
9572 /* enum: Download phases out of sequence */
9573 #define          MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100
9574 /* enum: Bad target for this phase */
9575 #define          MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101
9576 /* enum: Chunk ID out of sequence */
9577 #define          MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200
9578 /* enum: Chunk length zero or too large */
9579 #define          MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201
9580 /* enum: Checksum was incorrect */
9581 #define          MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300
9582 
9583 
9584 /***********************************/
9585 /* MC_CMD_GET_CAPABILITIES
9586  * Get device capabilities.
9587  *
9588  * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to
9589  * reference inherent device capabilities as opposed to current NVRAM config.
9590  */
9591 #define MC_CMD_GET_CAPABILITIES 0xbe
9592 
9593 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9594 
9595 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */
9596 #define    MC_CMD_GET_CAPABILITIES_IN_LEN 0
9597 
9598 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */
9599 #define    MC_CMD_GET_CAPABILITIES_OUT_LEN 20
9600 /* First word of flags. */
9601 #define       MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0
9602 #define       MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4
9603 #define        MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3
9604 #define        MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1
9605 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4
9606 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1
9607 #define        MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5
9608 #define        MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1
9609 #define        MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
9610 #define        MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
9611 #define        MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7
9612 #define        MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
9613 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8
9614 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
9615 #define        MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9
9616 #define        MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1
9617 #define        MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
9618 #define        MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
9619 #define        MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
9620 #define        MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
9621 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
9622 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
9623 #define        MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13
9624 #define        MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
9625 #define        MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14
9626 #define        MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1
9627 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
9628 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
9629 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16
9630 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1
9631 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17
9632 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1
9633 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18
9634 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1
9635 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19
9636 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1
9637 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20
9638 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1
9639 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21
9640 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1
9641 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22
9642 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1
9643 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23
9644 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1
9645 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24
9646 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1
9647 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25
9648 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1
9649 #define        MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26
9650 #define        MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1
9651 #define        MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27
9652 #define        MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
9653 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28
9654 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1
9655 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
9656 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
9657 #define        MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30
9658 #define        MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1
9659 #define        MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31
9660 #define        MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1
9661 /* RxDPCPU firmware id. */
9662 #define       MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4
9663 #define       MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2
9664 /* enum: Standard RXDP firmware */
9665 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0
9666 /* enum: Low latency RXDP firmware */
9667 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1
9668 /* enum: Packed stream RXDP firmware */
9669 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2
9670 /* enum: Rules engine RXDP firmware */
9671 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5
9672 /* enum: DPDK RXDP firmware */
9673 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6
9674 /* enum: BIST RXDP firmware */
9675 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a
9676 /* enum: RXDP Test firmware image 1 */
9677 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
9678 /* enum: RXDP Test firmware image 2 */
9679 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
9680 /* enum: RXDP Test firmware image 3 */
9681 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
9682 /* enum: RXDP Test firmware image 4 */
9683 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
9684 /* enum: RXDP Test firmware image 5 */
9685 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105
9686 /* enum: RXDP Test firmware image 6 */
9687 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
9688 /* enum: RXDP Test firmware image 7 */
9689 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
9690 /* enum: RXDP Test firmware image 8 */
9691 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
9692 /* enum: RXDP Test firmware image 9 */
9693 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
9694 /* enum: RXDP Test firmware image 10 */
9695 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c
9696 /* TxDPCPU firmware id. */
9697 #define       MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6
9698 #define       MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2
9699 /* enum: Standard TXDP firmware */
9700 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0
9701 /* enum: Low latency TXDP firmware */
9702 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1
9703 /* enum: High packet rate TXDP firmware */
9704 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3
9705 /* enum: Rules engine TXDP firmware */
9706 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5
9707 /* enum: DPDK TXDP firmware */
9708 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6
9709 /* enum: BIST TXDP firmware */
9710 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d
9711 /* enum: TXDP Test firmware image 1 */
9712 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
9713 /* enum: TXDP Test firmware image 2 */
9714 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
9715 /* enum: TXDP CSR bus test firmware */
9716 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103
9717 #define       MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8
9718 #define       MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2
9719 #define        MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0
9720 #define        MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12
9721 #define        MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12
9722 #define        MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
9723 /* enum: reserved value - do not use (may indicate alternative interpretation
9724  * of REV field in future)
9725  */
9726 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0
9727 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
9728  * development only)
9729  */
9730 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
9731 /* enum: RX PD firmware with approximately Siena-compatible behaviour
9732  * (Huntington development only)
9733  */
9734 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
9735 /* enum: Full featured RX PD production firmware */
9736 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
9737 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9738 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3
9739 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
9740  * (Huntington development only)
9741  */
9742 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
9743 /* enum: Low latency RX PD production firmware */
9744 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
9745 /* enum: Packed stream RX PD production firmware */
9746 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
9747 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
9748  * tests (Medford development only)
9749  */
9750 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
9751 /* enum: Rules engine RX PD production firmware */
9752 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
9753 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
9754 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x9
9755 /* enum: DPDK RX PD production firmware */
9756 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa
9757 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
9758 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
9759 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
9760  * encapsulations (Medford development only)
9761  */
9762 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
9763 #define       MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10
9764 #define       MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2
9765 #define        MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0
9766 #define        MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12
9767 #define        MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12
9768 #define        MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
9769 /* enum: reserved value - do not use (may indicate alternative interpretation
9770  * of REV field in future)
9771  */
9772 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0
9773 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
9774  * development only)
9775  */
9776 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
9777 /* enum: TX PD firmware with approximately Siena-compatible behaviour
9778  * (Huntington development only)
9779  */
9780 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
9781 /* enum: Full featured TX PD production firmware */
9782 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
9783 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9784 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3
9785 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
9786  * (Huntington development only)
9787  */
9788 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
9789 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
9790 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
9791  * tests (Medford development only)
9792  */
9793 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
9794 /* enum: Rules engine TX PD production firmware */
9795 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
9796 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
9797 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x9
9798 /* enum: DPDK TX PD production firmware */
9799 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa
9800 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
9801 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
9802 /* Hardware capabilities of NIC */
9803 #define       MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12
9804 #define       MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4
9805 /* Licensed capabilities */
9806 #define       MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16
9807 #define       MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4
9808 
9809 /* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */
9810 #define    MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0
9811 
9812 /* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */
9813 #define    MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72
9814 /* First word of flags. */
9815 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0
9816 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4
9817 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3
9818 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1
9819 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4
9820 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1
9821 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5
9822 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1
9823 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
9824 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
9825 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7
9826 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
9827 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8
9828 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
9829 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9
9830 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1
9831 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
9832 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
9833 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
9834 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
9835 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
9836 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
9837 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13
9838 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
9839 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14
9840 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1
9841 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
9842 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
9843 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16
9844 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1
9845 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17
9846 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1
9847 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18
9848 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1
9849 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19
9850 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1
9851 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20
9852 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1
9853 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21
9854 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1
9855 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22
9856 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1
9857 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23
9858 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1
9859 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24
9860 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1
9861 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25
9862 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1
9863 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26
9864 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1
9865 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27
9866 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
9867 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28
9868 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1
9869 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
9870 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
9871 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30
9872 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1
9873 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31
9874 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1
9875 /* RxDPCPU firmware id. */
9876 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4
9877 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2
9878 /* enum: Standard RXDP firmware */
9879 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0
9880 /* enum: Low latency RXDP firmware */
9881 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1
9882 /* enum: Packed stream RXDP firmware */
9883 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2
9884 /* enum: Rules engine RXDP firmware */
9885 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5
9886 /* enum: DPDK RXDP firmware */
9887 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6
9888 /* enum: BIST RXDP firmware */
9889 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a
9890 /* enum: RXDP Test firmware image 1 */
9891 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
9892 /* enum: RXDP Test firmware image 2 */
9893 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
9894 /* enum: RXDP Test firmware image 3 */
9895 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
9896 /* enum: RXDP Test firmware image 4 */
9897 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
9898 /* enum: RXDP Test firmware image 5 */
9899 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105
9900 /* enum: RXDP Test firmware image 6 */
9901 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
9902 /* enum: RXDP Test firmware image 7 */
9903 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
9904 /* enum: RXDP Test firmware image 8 */
9905 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
9906 /* enum: RXDP Test firmware image 9 */
9907 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
9908 /* enum: RXDP Test firmware image 10 */
9909 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c
9910 /* TxDPCPU firmware id. */
9911 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6
9912 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2
9913 /* enum: Standard TXDP firmware */
9914 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0
9915 /* enum: Low latency TXDP firmware */
9916 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1
9917 /* enum: High packet rate TXDP firmware */
9918 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3
9919 /* enum: Rules engine TXDP firmware */
9920 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5
9921 /* enum: DPDK TXDP firmware */
9922 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6
9923 /* enum: BIST TXDP firmware */
9924 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d
9925 /* enum: TXDP Test firmware image 1 */
9926 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
9927 /* enum: TXDP Test firmware image 2 */
9928 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
9929 /* enum: TXDP CSR bus test firmware */
9930 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103
9931 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8
9932 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2
9933 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0
9934 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12
9935 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12
9936 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
9937 /* enum: reserved value - do not use (may indicate alternative interpretation
9938  * of REV field in future)
9939  */
9940 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0
9941 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
9942  * development only)
9943  */
9944 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
9945 /* enum: RX PD firmware with approximately Siena-compatible behaviour
9946  * (Huntington development only)
9947  */
9948 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
9949 /* enum: Full featured RX PD production firmware */
9950 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
9951 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9952 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3
9953 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
9954  * (Huntington development only)
9955  */
9956 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
9957 /* enum: Low latency RX PD production firmware */
9958 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
9959 /* enum: Packed stream RX PD production firmware */
9960 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
9961 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
9962  * tests (Medford development only)
9963  */
9964 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
9965 /* enum: Rules engine RX PD production firmware */
9966 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
9967 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
9968 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x9
9969 /* enum: DPDK RX PD production firmware */
9970 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa
9971 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
9972 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
9973 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
9974  * encapsulations (Medford development only)
9975  */
9976 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
9977 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10
9978 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2
9979 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0
9980 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12
9981 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12
9982 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
9983 /* enum: reserved value - do not use (may indicate alternative interpretation
9984  * of REV field in future)
9985  */
9986 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0
9987 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
9988  * development only)
9989  */
9990 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
9991 /* enum: TX PD firmware with approximately Siena-compatible behaviour
9992  * (Huntington development only)
9993  */
9994 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
9995 /* enum: Full featured TX PD production firmware */
9996 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
9997 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9998 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3
9999 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
10000  * (Huntington development only)
10001  */
10002 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10003 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
10004 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
10005  * tests (Medford development only)
10006  */
10007 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
10008 /* enum: Rules engine TX PD production firmware */
10009 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
10010 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
10011 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x9
10012 /* enum: DPDK TX PD production firmware */
10013 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa
10014 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10015 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10016 /* Hardware capabilities of NIC */
10017 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12
10018 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4
10019 /* Licensed capabilities */
10020 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16
10021 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4
10022 /* Second word of flags. Not present on older firmware (check the length). */
10023 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20
10024 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4
10025 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0
10026 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1
10027 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1
10028 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1
10029 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2
10030 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1
10031 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3
10032 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1
10033 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4
10034 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1
10035 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5
10036 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
10037 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
10038 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
10039 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7
10040 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1
10041 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8
10042 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
10043 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9
10044 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1
10045 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10
10046 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1
10047 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11
10048 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1
10049 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
10050 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
10051 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 13
10052 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1
10053 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 14
10054 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1
10055 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_LBN 15
10056 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_WIDTH 1
10057 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_LBN 16
10058 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_WIDTH 1
10059 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_LBN 17
10060 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 1
10061 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
10062 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
10063 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_LBN 19
10064 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_WIDTH 1
10065 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_LBN 20
10066 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 1
10067 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
10068 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
10069 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_LBN 22
10070 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_WIDTH 1
10071 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
10072 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
10073 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_LBN 24
10074 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_WIDTH 1
10075 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
10076  * on older firmware (check the length).
10077  */
10078 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
10079 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
10080 /* One byte per PF containing the number of the external port assigned to this
10081  * PF, indexed by PF number. Special values indicate that a PF is either not
10082  * present or not assigned.
10083  */
10084 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
10085 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
10086 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
10087 /* enum: The caller is not permitted to access information on this PF. */
10088 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff
10089 /* enum: PF does not exist. */
10090 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe
10091 /* enum: PF does exist but is not assigned to any external port. */
10092 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd
10093 /* enum: This value indicates that PF is assigned, but it cannot be expressed
10094  * in this field. It is intended for a possible future situation where a more
10095  * complex scheme of PFs to ports mapping is being used. The future driver
10096  * should look for a new field supporting the new scheme. The current/old
10097  * driver should treat this value as PF_NOT_ASSIGNED.
10098  */
10099 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
10100 /* One byte per PF containing the number of its VFs, indexed by PF number. A
10101  * special value indicates that a PF is not present.
10102  */
10103 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42
10104 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1
10105 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16
10106 /* enum: The caller is not permitted to access information on this PF. */
10107 /*               MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */
10108 /* enum: PF does not exist. */
10109 /*               MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */
10110 /* Number of VIs available for each external port */
10111 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58
10112 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2
10113 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4
10114 /* Size of RX descriptor cache expressed as binary logarithm The actual size
10115  * equals (2 ^ RX_DESC_CACHE_SIZE)
10116  */
10117 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66
10118 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1
10119 /* Size of TX descriptor cache expressed as binary logarithm The actual size
10120  * equals (2 ^ TX_DESC_CACHE_SIZE)
10121  */
10122 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67
10123 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1
10124 /* Total number of available PIO buffers */
10125 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68
10126 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2
10127 /* Size of a single PIO buffer */
10128 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70
10129 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2
10130 
10131 /* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */
10132 #define    MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 76
10133 /* First word of flags. */
10134 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0
10135 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4
10136 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3
10137 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1
10138 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4
10139 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1
10140 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5
10141 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1
10142 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
10143 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
10144 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7
10145 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
10146 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8
10147 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
10148 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9
10149 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1
10150 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
10151 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
10152 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
10153 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
10154 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
10155 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
10156 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13
10157 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
10158 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14
10159 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1
10160 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
10161 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
10162 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16
10163 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1
10164 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17
10165 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1
10166 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18
10167 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1
10168 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19
10169 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1
10170 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20
10171 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1
10172 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21
10173 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1
10174 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22
10175 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1
10176 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23
10177 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1
10178 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24
10179 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1
10180 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25
10181 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1
10182 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26
10183 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1
10184 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27
10185 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
10186 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28
10187 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1
10188 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
10189 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
10190 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30
10191 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1
10192 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31
10193 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1
10194 /* RxDPCPU firmware id. */
10195 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4
10196 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2
10197 /* enum: Standard RXDP firmware */
10198 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0
10199 /* enum: Low latency RXDP firmware */
10200 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1
10201 /* enum: Packed stream RXDP firmware */
10202 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2
10203 /* enum: Rules engine RXDP firmware */
10204 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5
10205 /* enum: DPDK RXDP firmware */
10206 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6
10207 /* enum: BIST RXDP firmware */
10208 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a
10209 /* enum: RXDP Test firmware image 1 */
10210 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
10211 /* enum: RXDP Test firmware image 2 */
10212 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
10213 /* enum: RXDP Test firmware image 3 */
10214 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
10215 /* enum: RXDP Test firmware image 4 */
10216 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
10217 /* enum: RXDP Test firmware image 5 */
10218 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105
10219 /* enum: RXDP Test firmware image 6 */
10220 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
10221 /* enum: RXDP Test firmware image 7 */
10222 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
10223 /* enum: RXDP Test firmware image 8 */
10224 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
10225 /* enum: RXDP Test firmware image 9 */
10226 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
10227 /* enum: RXDP Test firmware image 10 */
10228 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c
10229 /* TxDPCPU firmware id. */
10230 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6
10231 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2
10232 /* enum: Standard TXDP firmware */
10233 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0
10234 /* enum: Low latency TXDP firmware */
10235 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1
10236 /* enum: High packet rate TXDP firmware */
10237 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3
10238 /* enum: Rules engine TXDP firmware */
10239 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5
10240 /* enum: DPDK TXDP firmware */
10241 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6
10242 /* enum: BIST TXDP firmware */
10243 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d
10244 /* enum: TXDP Test firmware image 1 */
10245 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
10246 /* enum: TXDP Test firmware image 2 */
10247 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
10248 /* enum: TXDP CSR bus test firmware */
10249 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103
10250 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8
10251 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2
10252 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0
10253 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12
10254 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12
10255 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
10256 /* enum: reserved value - do not use (may indicate alternative interpretation
10257  * of REV field in future)
10258  */
10259 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0
10260 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
10261  * development only)
10262  */
10263 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
10264 /* enum: RX PD firmware with approximately Siena-compatible behaviour
10265  * (Huntington development only)
10266  */
10267 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
10268 /* enum: Full featured RX PD production firmware */
10269 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
10270 /* enum: (deprecated original name for the FULL_FEATURED variant) */
10271 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3
10272 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
10273  * (Huntington development only)
10274  */
10275 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10276 /* enum: Low latency RX PD production firmware */
10277 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
10278 /* enum: Packed stream RX PD production firmware */
10279 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
10280 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
10281  * tests (Medford development only)
10282  */
10283 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
10284 /* enum: Rules engine RX PD production firmware */
10285 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
10286 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
10287 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x9
10288 /* enum: DPDK RX PD production firmware */
10289 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa
10290 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10291 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10292 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
10293  * encapsulations (Medford development only)
10294  */
10295 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
10296 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10
10297 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2
10298 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0
10299 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12
10300 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12
10301 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
10302 /* enum: reserved value - do not use (may indicate alternative interpretation
10303  * of REV field in future)
10304  */
10305 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0
10306 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
10307  * development only)
10308  */
10309 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
10310 /* enum: TX PD firmware with approximately Siena-compatible behaviour
10311  * (Huntington development only)
10312  */
10313 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
10314 /* enum: Full featured TX PD production firmware */
10315 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
10316 /* enum: (deprecated original name for the FULL_FEATURED variant) */
10317 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3
10318 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
10319  * (Huntington development only)
10320  */
10321 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10322 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
10323 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
10324  * tests (Medford development only)
10325  */
10326 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
10327 /* enum: Rules engine TX PD production firmware */
10328 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
10329 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
10330 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x9
10331 /* enum: DPDK TX PD production firmware */
10332 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa
10333 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10334 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10335 /* Hardware capabilities of NIC */
10336 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12
10337 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4
10338 /* Licensed capabilities */
10339 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16
10340 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4
10341 /* Second word of flags. Not present on older firmware (check the length). */
10342 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20
10343 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4
10344 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0
10345 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1
10346 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1
10347 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1
10348 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2
10349 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1
10350 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3
10351 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1
10352 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4
10353 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1
10354 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5
10355 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
10356 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
10357 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
10358 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7
10359 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1
10360 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8
10361 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
10362 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9
10363 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1
10364 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10
10365 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1
10366 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11
10367 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1
10368 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
10369 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
10370 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 13
10371 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1
10372 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 14
10373 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1
10374 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_LBN 15
10375 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_WIDTH 1
10376 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_LBN 16
10377 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_WIDTH 1
10378 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_LBN 17
10379 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 1
10380 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
10381 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
10382 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_LBN 19
10383 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_WIDTH 1
10384 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_LBN 20
10385 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 1
10386 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
10387 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
10388 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_LBN 22
10389 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_WIDTH 1
10390 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
10391 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
10392 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_LBN 24
10393 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_WIDTH 1
10394 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
10395  * on older firmware (check the length).
10396  */
10397 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
10398 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
10399 /* One byte per PF containing the number of the external port assigned to this
10400  * PF, indexed by PF number. Special values indicate that a PF is either not
10401  * present or not assigned.
10402  */
10403 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
10404 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
10405 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
10406 /* enum: The caller is not permitted to access information on this PF. */
10407 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff
10408 /* enum: PF does not exist. */
10409 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe
10410 /* enum: PF does exist but is not assigned to any external port. */
10411 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd
10412 /* enum: This value indicates that PF is assigned, but it cannot be expressed
10413  * in this field. It is intended for a possible future situation where a more
10414  * complex scheme of PFs to ports mapping is being used. The future driver
10415  * should look for a new field supporting the new scheme. The current/old
10416  * driver should treat this value as PF_NOT_ASSIGNED.
10417  */
10418 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
10419 /* One byte per PF containing the number of its VFs, indexed by PF number. A
10420  * special value indicates that a PF is not present.
10421  */
10422 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 42
10423 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1
10424 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16
10425 /* enum: The caller is not permitted to access information on this PF. */
10426 /*               MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */
10427 /* enum: PF does not exist. */
10428 /*               MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */
10429 /* Number of VIs available for each external port */
10430 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58
10431 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2
10432 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4
10433 /* Size of RX descriptor cache expressed as binary logarithm The actual size
10434  * equals (2 ^ RX_DESC_CACHE_SIZE)
10435  */
10436 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 66
10437 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1
10438 /* Size of TX descriptor cache expressed as binary logarithm The actual size
10439  * equals (2 ^ TX_DESC_CACHE_SIZE)
10440  */
10441 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 67
10442 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1
10443 /* Total number of available PIO buffers */
10444 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 68
10445 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 2
10446 /* Size of a single PIO buffer */
10447 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 70
10448 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 2
10449 /* On chips later than Medford the amount of address space assigned to each VI
10450  * is configurable. This is a global setting that the driver must query to
10451  * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
10452  * with 8k VI windows.
10453  */
10454 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 72
10455 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1
10456 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
10457  * CTPIO is not mapped.
10458  */
10459 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0
10460 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
10461 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1
10462 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
10463 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2
10464 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
10465  * (SF-115995-SW) in the present configuration of firmware and port mode.
10466  */
10467 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
10468 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
10469 /* Number of buffers per adapter that can be used for VFIFO Stuffing
10470  * (SF-115995-SW) in the present configuration of firmware and port mode.
10471  */
10472 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
10473 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
10474 
10475 /* MC_CMD_GET_CAPABILITIES_V4_OUT msgresponse */
10476 #define    MC_CMD_GET_CAPABILITIES_V4_OUT_LEN 78
10477 /* First word of flags. */
10478 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0
10479 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4
10480 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_LBN 3
10481 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 1
10482 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4
10483 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 1
10484 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_LBN 5
10485 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 1
10486 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
10487 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
10488 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_LBN 7
10489 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
10490 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_LBN 8
10491 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
10492 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_LBN 9
10493 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 1
10494 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
10495 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
10496 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
10497 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
10498 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
10499 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
10500 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_LBN 13
10501 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
10502 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_LBN 14
10503 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 1
10504 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
10505 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
10506 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_LBN 16
10507 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 1
10508 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_LBN 17
10509 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 1
10510 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_LBN 18
10511 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 1
10512 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_LBN 19
10513 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 1
10514 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_LBN 20
10515 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 1
10516 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_LBN 21
10517 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 1
10518 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_LBN 22
10519 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 1
10520 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_LBN 23
10521 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 1
10522 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_LBN 24
10523 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 1
10524 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_LBN 25
10525 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 1
10526 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_LBN 26
10527 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 1
10528 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_LBN 27
10529 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
10530 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_LBN 28
10531 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 1
10532 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
10533 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
10534 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_LBN 30
10535 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 1
10536 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_LBN 31
10537 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 1
10538 /* RxDPCPU firmware id. */
10539 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4
10540 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_LEN 2
10541 /* enum: Standard RXDP firmware */
10542 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0
10543 /* enum: Low latency RXDP firmware */
10544 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1
10545 /* enum: Packed stream RXDP firmware */
10546 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2
10547 /* enum: Rules engine RXDP firmware */
10548 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5
10549 /* enum: DPDK RXDP firmware */
10550 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6
10551 /* enum: BIST RXDP firmware */
10552 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a
10553 /* enum: RXDP Test firmware image 1 */
10554 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
10555 /* enum: RXDP Test firmware image 2 */
10556 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
10557 /* enum: RXDP Test firmware image 3 */
10558 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
10559 /* enum: RXDP Test firmware image 4 */
10560 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
10561 /* enum: RXDP Test firmware image 5 */
10562 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105
10563 /* enum: RXDP Test firmware image 6 */
10564 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
10565 /* enum: RXDP Test firmware image 7 */
10566 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
10567 /* enum: RXDP Test firmware image 8 */
10568 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
10569 /* enum: RXDP Test firmware image 9 */
10570 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
10571 /* enum: RXDP Test firmware image 10 */
10572 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c
10573 /* TxDPCPU firmware id. */
10574 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_OFST 6
10575 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_LEN 2
10576 /* enum: Standard TXDP firmware */
10577 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0
10578 /* enum: Low latency TXDP firmware */
10579 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1
10580 /* enum: High packet rate TXDP firmware */
10581 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3
10582 /* enum: Rules engine TXDP firmware */
10583 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5
10584 /* enum: DPDK TXDP firmware */
10585 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6
10586 /* enum: BIST TXDP firmware */
10587 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d
10588 /* enum: TXDP Test firmware image 1 */
10589 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
10590 /* enum: TXDP Test firmware image 2 */
10591 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
10592 /* enum: TXDP CSR bus test firmware */
10593 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103
10594 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 8
10595 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 2
10596 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0
10597 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_WIDTH 12
10598 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_LBN 12
10599 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
10600 /* enum: reserved value - do not use (may indicate alternative interpretation
10601  * of REV field in future)
10602  */
10603 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0
10604 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
10605  * development only)
10606  */
10607 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
10608 /* enum: RX PD firmware with approximately Siena-compatible behaviour
10609  * (Huntington development only)
10610  */
10611 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
10612 /* enum: Full featured RX PD production firmware */
10613 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
10614 /* enum: (deprecated original name for the FULL_FEATURED variant) */
10615 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3
10616 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
10617  * (Huntington development only)
10618  */
10619 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10620 /* enum: Low latency RX PD production firmware */
10621 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
10622 /* enum: Packed stream RX PD production firmware */
10623 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
10624 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
10625  * tests (Medford development only)
10626  */
10627 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
10628 /* enum: Rules engine RX PD production firmware */
10629 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
10630 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
10631 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x9
10632 /* enum: DPDK RX PD production firmware */
10633 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa
10634 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10635 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10636 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
10637  * encapsulations (Medford development only)
10638  */
10639 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
10640 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 10
10641 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 2
10642 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0
10643 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_WIDTH 12
10644 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_LBN 12
10645 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
10646 /* enum: reserved value - do not use (may indicate alternative interpretation
10647  * of REV field in future)
10648  */
10649 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0
10650 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
10651  * development only)
10652  */
10653 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
10654 /* enum: TX PD firmware with approximately Siena-compatible behaviour
10655  * (Huntington development only)
10656  */
10657 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
10658 /* enum: Full featured TX PD production firmware */
10659 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
10660 /* enum: (deprecated original name for the FULL_FEATURED variant) */
10661 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3
10662 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
10663  * (Huntington development only)
10664  */
10665 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10666 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
10667 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
10668  * tests (Medford development only)
10669  */
10670 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
10671 /* enum: Rules engine TX PD production firmware */
10672 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
10673 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
10674 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x9
10675 /* enum: DPDK TX PD production firmware */
10676 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa
10677 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10678 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10679 /* Hardware capabilities of NIC */
10680 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_OFST 12
10681 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4
10682 /* Licensed capabilities */
10683 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_OFST 16
10684 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4
10685 /* Second word of flags. Not present on older firmware (check the length). */
10686 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST 20
10687 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4
10688 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0
10689 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 1
10690 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 1
10691 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 1
10692 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_LBN 2
10693 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 1
10694 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_LBN 3
10695 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 1
10696 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4
10697 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 1
10698 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_LBN 5
10699 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
10700 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
10701 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
10702 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_LBN 7
10703 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 1
10704 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_LBN 8
10705 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
10706 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_LBN 9
10707 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 1
10708 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_LBN 10
10709 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 1
10710 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_LBN 11
10711 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 1
10712 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
10713 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
10714 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_LBN 13
10715 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 1
10716 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_LBN 14
10717 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1
10718 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN 15
10719 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_WIDTH 1
10720 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_LBN 16
10721 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_WIDTH 1
10722 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_LBN 17
10723 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 1
10724 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
10725 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
10726 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_LBN 19
10727 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_WIDTH 1
10728 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_LBN 20
10729 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 1
10730 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
10731 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
10732 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_LBN 22
10733 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_WIDTH 1
10734 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
10735 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
10736 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_LBN 24
10737 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_WIDTH 1
10738 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
10739  * on older firmware (check the length).
10740  */
10741 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
10742 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
10743 /* One byte per PF containing the number of the external port assigned to this
10744  * PF, indexed by PF number. Special values indicate that a PF is either not
10745  * present or not assigned.
10746  */
10747 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
10748 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
10749 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
10750 /* enum: The caller is not permitted to access information on this PF. */
10751 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff
10752 /* enum: PF does not exist. */
10753 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe
10754 /* enum: PF does exist but is not assigned to any external port. */
10755 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd
10756 /* enum: This value indicates that PF is assigned, but it cannot be expressed
10757  * in this field. It is intended for a possible future situation where a more
10758  * complex scheme of PFs to ports mapping is being used. The future driver
10759  * should look for a new field supporting the new scheme. The current/old
10760  * driver should treat this value as PF_NOT_ASSIGNED.
10761  */
10762 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
10763 /* One byte per PF containing the number of its VFs, indexed by PF number. A
10764  * special value indicates that a PF is not present.
10765  */
10766 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_OFST 42
10767 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 1
10768 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_NUM 16
10769 /* enum: The caller is not permitted to access information on this PF. */
10770 /*               MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */
10771 /* enum: PF does not exist. */
10772 /*               MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */
10773 /* Number of VIs available for each external port */
10774 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 58
10775 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 2
10776 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4
10777 /* Size of RX descriptor cache expressed as binary logarithm The actual size
10778  * equals (2 ^ RX_DESC_CACHE_SIZE)
10779  */
10780 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_OFST 66
10781 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_LEN 1
10782 /* Size of TX descriptor cache expressed as binary logarithm The actual size
10783  * equals (2 ^ TX_DESC_CACHE_SIZE)
10784  */
10785 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_OFST 67
10786 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_LEN 1
10787 /* Total number of available PIO buffers */
10788 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_OFST 68
10789 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_LEN 2
10790 /* Size of a single PIO buffer */
10791 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_OFST 70
10792 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_LEN 2
10793 /* On chips later than Medford the amount of address space assigned to each VI
10794  * is configurable. This is a global setting that the driver must query to
10795  * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
10796  * with 8k VI windows.
10797  */
10798 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_OFST 72
10799 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_LEN 1
10800 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
10801  * CTPIO is not mapped.
10802  */
10803 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0
10804 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
10805 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1
10806 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
10807 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2
10808 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
10809  * (SF-115995-SW) in the present configuration of firmware and port mode.
10810  */
10811 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
10812 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
10813 /* Number of buffers per adapter that can be used for VFIFO Stuffing
10814  * (SF-115995-SW) in the present configuration of firmware and port mode.
10815  */
10816 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
10817 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
10818 /* Entry count in the MAC stats array, including the final GENERATION_END
10819  * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
10820  * hold at least this many 64-bit stats values, if they wish to receive all
10821  * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
10822  * stats array returned will be truncated.
10823  */
10824 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_OFST 76
10825 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_LEN 2
10826 
10827 
10828 /***********************************/
10829 /* MC_CMD_V2_EXTN
10830  * Encapsulation for a v2 extended command
10831  */
10832 #define MC_CMD_V2_EXTN 0x7f
10833 
10834 /* MC_CMD_V2_EXTN_IN msgrequest */
10835 #define    MC_CMD_V2_EXTN_IN_LEN 4
10836 /* the extended command number */
10837 #define       MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
10838 #define       MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15
10839 #define       MC_CMD_V2_EXTN_IN_UNUSED_LBN 15
10840 #define       MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1
10841 /* the actual length of the encapsulated command (which is not in the v1
10842  * header)
10843  */
10844 #define       MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16
10845 #define       MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10
10846 #define       MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26
10847 #define       MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2
10848 /* Type of command/response */
10849 #define       MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28
10850 #define       MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4
10851 /* enum: MCDI command directed to or response originating from the MC. */
10852 #define          MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0
10853 /* enum: MCDI command directed to a TSA controller. MCDI responses of this type
10854  * are not defined.
10855  */
10856 #define          MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1
10857 
10858 
10859 /***********************************/
10860 /* MC_CMD_TCM_BUCKET_ALLOC
10861  * Allocate a pacer bucket (for qau rp or a snapper test)
10862  */
10863 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2
10864 
10865 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10866 
10867 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */
10868 #define    MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0
10869 
10870 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */
10871 #define    MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4
10872 /* the bucket id */
10873 #define       MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0
10874 #define       MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4
10875 
10876 
10877 /***********************************/
10878 /* MC_CMD_TCM_BUCKET_FREE
10879  * Free a pacer bucket
10880  */
10881 #define MC_CMD_TCM_BUCKET_FREE 0xb3
10882 
10883 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10884 
10885 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */
10886 #define    MC_CMD_TCM_BUCKET_FREE_IN_LEN 4
10887 /* the bucket id */
10888 #define       MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0
10889 #define       MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 4
10890 
10891 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */
10892 #define    MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0
10893 
10894 
10895 /***********************************/
10896 /* MC_CMD_TCM_BUCKET_INIT
10897  * Initialise pacer bucket with a given rate
10898  */
10899 #define MC_CMD_TCM_BUCKET_INIT 0xb4
10900 
10901 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10902 
10903 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */
10904 #define    MC_CMD_TCM_BUCKET_INIT_IN_LEN 8
10905 /* the bucket id */
10906 #define       MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0
10907 #define       MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 4
10908 /* the rate in mbps */
10909 #define       MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4
10910 #define       MC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 4
10911 
10912 /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */
10913 #define    MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12
10914 /* the bucket id */
10915 #define       MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0
10916 #define       MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 4
10917 /* the rate in mbps */
10918 #define       MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4
10919 #define       MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 4
10920 /* the desired maximum fill level */
10921 #define       MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8
10922 #define       MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 4
10923 
10924 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */
10925 #define    MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0
10926 
10927 
10928 /***********************************/
10929 /* MC_CMD_TCM_TXQ_INIT
10930  * Initialise txq in pacer with given options or set options
10931  */
10932 #define MC_CMD_TCM_TXQ_INIT 0xb5
10933 
10934 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10935 
10936 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */
10937 #define    MC_CMD_TCM_TXQ_INIT_IN_LEN 28
10938 /* the txq id */
10939 #define       MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0
10940 #define       MC_CMD_TCM_TXQ_INIT_IN_QID_LEN 4
10941 /* the static priority associated with the txq */
10942 #define       MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4
10943 #define       MC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 4
10944 /* bitmask of the priority queues this txq is inserted into when inserted. */
10945 #define       MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8
10946 #define       MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4
10947 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0
10948 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1
10949 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1
10950 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1
10951 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2
10952 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1
10953 /* the reaction point (RP) bucket */
10954 #define       MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12
10955 #define       MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 4
10956 /* an already reserved bucket (typically set to bucket associated with outer
10957  * vswitch)
10958  */
10959 #define       MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16
10960 #define       MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 4
10961 /* an already reserved bucket (typically set to bucket associated with inner
10962  * vswitch)
10963  */
10964 #define       MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20
10965 #define       MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 4
10966 /* the min bucket (typically for ETS/minimum bandwidth) */
10967 #define       MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24
10968 #define       MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 4
10969 
10970 /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */
10971 #define    MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32
10972 /* the txq id */
10973 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0
10974 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 4
10975 /* the static priority associated with the txq */
10976 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4
10977 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 4
10978 /* bitmask of the priority queues this txq is inserted into when inserted. */
10979 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8
10980 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4
10981 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0
10982 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1
10983 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1
10984 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1
10985 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2
10986 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1
10987 /* the reaction point (RP) bucket */
10988 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12
10989 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 4
10990 /* an already reserved bucket (typically set to bucket associated with outer
10991  * vswitch)
10992  */
10993 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16
10994 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 4
10995 /* an already reserved bucket (typically set to bucket associated with inner
10996  * vswitch)
10997  */
10998 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20
10999 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 4
11000 /* the min bucket (typically for ETS/minimum bandwidth) */
11001 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24
11002 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 4
11003 /* the static priority associated with the txq */
11004 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28
11005 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 4
11006 
11007 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */
11008 #define    MC_CMD_TCM_TXQ_INIT_OUT_LEN 0
11009 
11010 
11011 /***********************************/
11012 /* MC_CMD_LINK_PIOBUF
11013  * Link a push I/O buffer to a TxQ
11014  */
11015 #define MC_CMD_LINK_PIOBUF 0x92
11016 
11017 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
11018 
11019 /* MC_CMD_LINK_PIOBUF_IN msgrequest */
11020 #define    MC_CMD_LINK_PIOBUF_IN_LEN 8
11021 /* Handle for allocated push I/O buffer. */
11022 #define       MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
11023 #define       MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
11024 /* Function Local Instance (VI) number. */
11025 #define       MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
11026 #define       MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
11027 
11028 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */
11029 #define    MC_CMD_LINK_PIOBUF_OUT_LEN 0
11030 
11031 
11032 /***********************************/
11033 /* MC_CMD_UNLINK_PIOBUF
11034  * Unlink a push I/O buffer from a TxQ
11035  */
11036 #define MC_CMD_UNLINK_PIOBUF 0x93
11037 
11038 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
11039 
11040 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */
11041 #define    MC_CMD_UNLINK_PIOBUF_IN_LEN 4
11042 /* Function Local Instance (VI) number. */
11043 #define       MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0
11044 #define       MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
11045 
11046 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */
11047 #define    MC_CMD_UNLINK_PIOBUF_OUT_LEN 0
11048 
11049 
11050 /***********************************/
11051 /* MC_CMD_VSWITCH_ALLOC
11052  * allocate and initialise a v-switch.
11053  */
11054 #define MC_CMD_VSWITCH_ALLOC 0x94
11055 
11056 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11057 
11058 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */
11059 #define    MC_CMD_VSWITCH_ALLOC_IN_LEN 16
11060 /* The port to connect to the v-switch's upstream port. */
11061 #define       MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11062 #define       MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
11063 /* The type of v-switch to create. */
11064 #define       MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4
11065 #define       MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4
11066 /* enum: VLAN */
11067 #define          MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1
11068 /* enum: VEB */
11069 #define          MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2
11070 /* enum: VEPA (obsolete) */
11071 #define          MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3
11072 /* enum: MUX */
11073 #define          MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4
11074 /* enum: Snapper specific; semantics TBD */
11075 #define          MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5
11076 /* Flags controlling v-port creation */
11077 #define       MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8
11078 #define       MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4
11079 #define        MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
11080 #define        MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
11081 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,
11082  * this must be one or greated, and the attached v-ports must have exactly this
11083  * number of tags. For other v-switch types, this must be zero of greater, and
11084  * is an upper limit on the number of VLAN tags for attached v-ports. An error
11085  * will be returned if existing configuration means we can't support attached
11086  * v-ports with this number of tags.
11087  */
11088 #define       MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
11089 #define       MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
11090 
11091 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */
11092 #define    MC_CMD_VSWITCH_ALLOC_OUT_LEN 0
11093 
11094 
11095 /***********************************/
11096 /* MC_CMD_VSWITCH_FREE
11097  * de-allocate a v-switch.
11098  */
11099 #define MC_CMD_VSWITCH_FREE 0x95
11100 
11101 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11102 
11103 /* MC_CMD_VSWITCH_FREE_IN msgrequest */
11104 #define    MC_CMD_VSWITCH_FREE_IN_LEN 4
11105 /* The port to which the v-switch is connected. */
11106 #define       MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0
11107 #define       MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4
11108 
11109 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */
11110 #define    MC_CMD_VSWITCH_FREE_OUT_LEN 0
11111 
11112 
11113 /***********************************/
11114 /* MC_CMD_VSWITCH_QUERY
11115  * read some config of v-switch. For now this command is an empty placeholder.
11116  * It may be used to check if a v-switch is connected to a given EVB port (if
11117  * not, then the command returns ENOENT).
11118  */
11119 #define MC_CMD_VSWITCH_QUERY 0x63
11120 
11121 #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11122 
11123 /* MC_CMD_VSWITCH_QUERY_IN msgrequest */
11124 #define    MC_CMD_VSWITCH_QUERY_IN_LEN 4
11125 /* The port to which the v-switch is connected. */
11126 #define       MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
11127 #define       MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
11128 
11129 /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */
11130 #define    MC_CMD_VSWITCH_QUERY_OUT_LEN 0
11131 
11132 
11133 /***********************************/
11134 /* MC_CMD_VPORT_ALLOC
11135  * allocate a v-port.
11136  */
11137 #define MC_CMD_VPORT_ALLOC 0x96
11138 
11139 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11140 
11141 /* MC_CMD_VPORT_ALLOC_IN msgrequest */
11142 #define    MC_CMD_VPORT_ALLOC_IN_LEN 20
11143 /* The port to which the v-switch is connected. */
11144 #define       MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11145 #define       MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
11146 /* The type of the new v-port. */
11147 #define       MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4
11148 #define       MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4
11149 /* enum: VLAN (obsolete) */
11150 #define          MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1
11151 /* enum: VEB (obsolete) */
11152 #define          MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2
11153 /* enum: VEPA (obsolete) */
11154 #define          MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3
11155 /* enum: A normal v-port receives packets which match a specified MAC and/or
11156  * VLAN.
11157  */
11158 #define          MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4
11159 /* enum: An expansion v-port packets traffic which don't match any other
11160  * v-port.
11161  */
11162 #define          MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5
11163 /* enum: An test v-port receives packets which match any filters installed by
11164  * its downstream components.
11165  */
11166 #define          MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6
11167 /* Flags controlling v-port creation */
11168 #define       MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8
11169 #define       MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4
11170 #define        MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
11171 #define        MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
11172 #define        MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1
11173 #define        MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1
11174 /* The number of VLAN tags to insert/remove. An error will be returned if
11175  * incompatible with the number of VLAN tags specified for the upstream
11176  * v-switch.
11177  */
11178 #define       MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
11179 #define       MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
11180 /* The actual VLAN tags to insert/remove */
11181 #define       MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16
11182 #define       MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4
11183 #define        MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0
11184 #define        MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16
11185 #define        MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16
11186 #define        MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16
11187 
11188 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */
11189 #define    MC_CMD_VPORT_ALLOC_OUT_LEN 4
11190 /* The handle of the new v-port */
11191 #define       MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0
11192 #define       MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4
11193 
11194 
11195 /***********************************/
11196 /* MC_CMD_VPORT_FREE
11197  * de-allocate a v-port.
11198  */
11199 #define MC_CMD_VPORT_FREE 0x97
11200 
11201 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11202 
11203 /* MC_CMD_VPORT_FREE_IN msgrequest */
11204 #define    MC_CMD_VPORT_FREE_IN_LEN 4
11205 /* The handle of the v-port */
11206 #define       MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0
11207 #define       MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4
11208 
11209 /* MC_CMD_VPORT_FREE_OUT msgresponse */
11210 #define    MC_CMD_VPORT_FREE_OUT_LEN 0
11211 
11212 
11213 /***********************************/
11214 /* MC_CMD_VADAPTOR_ALLOC
11215  * allocate a v-adaptor.
11216  */
11217 #define MC_CMD_VADAPTOR_ALLOC 0x98
11218 
11219 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11220 
11221 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */
11222 #define    MC_CMD_VADAPTOR_ALLOC_IN_LEN 30
11223 /* The port to connect to the v-adaptor's port. */
11224 #define       MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11225 #define       MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
11226 /* Flags controlling v-adaptor creation */
11227 #define       MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8
11228 #define       MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4
11229 #define        MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0
11230 #define        MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1
11231 #define        MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1
11232 #define        MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
11233 /* The number of VLAN tags to strip on receive */
11234 #define       MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12
11235 #define       MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4
11236 /* The number of VLAN tags to transparently insert/remove. */
11237 #define       MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16
11238 #define       MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
11239 /* The actual VLAN tags to insert/remove */
11240 #define       MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20
11241 #define       MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4
11242 #define        MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0
11243 #define        MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16
11244 #define        MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16
11245 #define        MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16
11246 /* The MAC address to assign to this v-adaptor */
11247 #define       MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24
11248 #define       MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6
11249 /* enum: Derive the MAC address from the upstream port */
11250 #define          MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0
11251 
11252 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */
11253 #define    MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0
11254 
11255 
11256 /***********************************/
11257 /* MC_CMD_VADAPTOR_FREE
11258  * de-allocate a v-adaptor.
11259  */
11260 #define MC_CMD_VADAPTOR_FREE 0x99
11261 
11262 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11263 
11264 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */
11265 #define    MC_CMD_VADAPTOR_FREE_IN_LEN 4
11266 /* The port to which the v-adaptor is connected. */
11267 #define       MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0
11268 #define       MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4
11269 
11270 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */
11271 #define    MC_CMD_VADAPTOR_FREE_OUT_LEN 0
11272 
11273 
11274 /***********************************/
11275 /* MC_CMD_VADAPTOR_SET_MAC
11276  * assign a new MAC address to a v-adaptor.
11277  */
11278 #define MC_CMD_VADAPTOR_SET_MAC 0x5d
11279 
11280 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11281 
11282 /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */
11283 #define    MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10
11284 /* The port to which the v-adaptor is connected. */
11285 #define       MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
11286 #define       MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
11287 /* The new MAC address to assign to this v-adaptor */
11288 #define       MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4
11289 #define       MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6
11290 
11291 /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */
11292 #define    MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0
11293 
11294 
11295 /***********************************/
11296 /* MC_CMD_VADAPTOR_GET_MAC
11297  * read the MAC address assigned to a v-adaptor.
11298  */
11299 #define MC_CMD_VADAPTOR_GET_MAC 0x5e
11300 
11301 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11302 
11303 /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */
11304 #define    MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4
11305 /* The port to which the v-adaptor is connected. */
11306 #define       MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
11307 #define       MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
11308 
11309 /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */
11310 #define    MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6
11311 /* The MAC address assigned to this v-adaptor */
11312 #define       MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0
11313 #define       MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6
11314 
11315 
11316 /***********************************/
11317 /* MC_CMD_VADAPTOR_QUERY
11318  * read some config of v-adaptor.
11319  */
11320 #define MC_CMD_VADAPTOR_QUERY 0x61
11321 
11322 #define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11323 
11324 /* MC_CMD_VADAPTOR_QUERY_IN msgrequest */
11325 #define    MC_CMD_VADAPTOR_QUERY_IN_LEN 4
11326 /* The port to which the v-adaptor is connected. */
11327 #define       MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
11328 #define       MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
11329 
11330 /* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */
11331 #define    MC_CMD_VADAPTOR_QUERY_OUT_LEN 12
11332 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */
11333 #define       MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0
11334 #define       MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4
11335 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */
11336 #define       MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4
11337 #define       MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4
11338 /* The number of VLAN tags that may still be added */
11339 #define       MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8
11340 #define       MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
11341 
11342 
11343 /***********************************/
11344 /* MC_CMD_EVB_PORT_ASSIGN
11345  * assign a port to a PCI function.
11346  */
11347 #define MC_CMD_EVB_PORT_ASSIGN 0x9a
11348 
11349 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11350 
11351 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */
11352 #define    MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8
11353 /* The port to assign. */
11354 #define       MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0
11355 #define       MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4
11356 /* The target function to modify. */
11357 #define       MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4
11358 #define       MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4
11359 #define        MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0
11360 #define        MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16
11361 #define        MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16
11362 #define        MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16
11363 
11364 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */
11365 #define    MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0
11366 
11367 
11368 /***********************************/
11369 /* MC_CMD_RDWR_A64_REGIONS
11370  * Assign the 64 bit region addresses.
11371  */
11372 #define MC_CMD_RDWR_A64_REGIONS 0x9b
11373 
11374 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11375 
11376 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */
11377 #define    MC_CMD_RDWR_A64_REGIONS_IN_LEN 17
11378 #define       MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0
11379 #define       MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 4
11380 #define       MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4
11381 #define       MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 4
11382 #define       MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8
11383 #define       MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 4
11384 #define       MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12
11385 #define       MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 4
11386 /* Write enable bits 0-3, set to write, clear to read. */
11387 #define       MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128
11388 #define       MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4
11389 #define       MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16
11390 #define       MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1
11391 
11392 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included
11393  * regardless of state of write bits in the request.
11394  */
11395 #define    MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16
11396 #define       MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0
11397 #define       MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 4
11398 #define       MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4
11399 #define       MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 4
11400 #define       MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8
11401 #define       MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 4
11402 #define       MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12
11403 #define       MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4
11404 
11405 
11406 /***********************************/
11407 /* MC_CMD_ONLOAD_STACK_ALLOC
11408  * Allocate an Onload stack ID.
11409  */
11410 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c
11411 
11412 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
11413 
11414 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */
11415 #define    MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4
11416 /* The handle of the owning upstream port */
11417 #define       MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11418 #define       MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
11419 
11420 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */
11421 #define    MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4
11422 /* The handle of the new Onload stack */
11423 #define       MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0
11424 #define       MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4
11425 
11426 
11427 /***********************************/
11428 /* MC_CMD_ONLOAD_STACK_FREE
11429  * Free an Onload stack ID.
11430  */
11431 #define MC_CMD_ONLOAD_STACK_FREE 0x9d
11432 
11433 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
11434 
11435 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */
11436 #define    MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4
11437 /* The handle of the Onload stack */
11438 #define       MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0
11439 #define       MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 4
11440 
11441 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */
11442 #define    MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0
11443 
11444 
11445 /***********************************/
11446 /* MC_CMD_RSS_CONTEXT_ALLOC
11447  * Allocate an RSS context.
11448  */
11449 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
11450 
11451 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11452 
11453 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */
11454 #define    MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12
11455 /* The handle of the owning upstream port */
11456 #define       MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11457 #define       MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
11458 /* The type of context to allocate */
11459 #define       MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4
11460 #define       MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4
11461 /* enum: Allocate a context for exclusive use. The key and indirection table
11462  * must be explicitly configured.
11463  */
11464 #define          MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0
11465 /* enum: Allocate a context for shared use; this will spread across a range of
11466  * queues, but the key and indirection table are pre-configured and may not be
11467  * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
11468  */
11469 #define          MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
11470 /* Number of queues spanned by this context, in the range 1-64; valid offsets
11471  * in the indirection table will be in the range 0 to NUM_QUEUES-1.
11472  */
11473 #define       MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8
11474 #define       MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4
11475 
11476 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */
11477 #define    MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4
11478 /* The handle of the new RSS context. This should be considered opaque to the
11479  * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
11480  * handle.
11481  */
11482 #define       MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0
11483 #define       MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4
11484 /* enum: guaranteed invalid RSS context handle value */
11485 #define          MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff
11486 
11487 
11488 /***********************************/
11489 /* MC_CMD_RSS_CONTEXT_FREE
11490  * Free an RSS context.
11491  */
11492 #define MC_CMD_RSS_CONTEXT_FREE 0x9f
11493 
11494 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11495 
11496 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */
11497 #define    MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4
11498 /* The handle of the RSS context */
11499 #define       MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0
11500 #define       MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4
11501 
11502 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */
11503 #define    MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0
11504 
11505 
11506 /***********************************/
11507 /* MC_CMD_RSS_CONTEXT_SET_KEY
11508  * Set the Toeplitz hash key for an RSS context.
11509  */
11510 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
11511 
11512 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11513 
11514 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */
11515 #define    MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44
11516 /* The handle of the RSS context */
11517 #define       MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0
11518 #define       MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4
11519 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
11520 #define       MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4
11521 #define       MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40
11522 
11523 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */
11524 #define    MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0
11525 
11526 
11527 /***********************************/
11528 /* MC_CMD_RSS_CONTEXT_GET_KEY
11529  * Get the Toeplitz hash key for an RSS context.
11530  */
11531 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
11532 
11533 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11534 
11535 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */
11536 #define    MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4
11537 /* The handle of the RSS context */
11538 #define       MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0
11539 #define       MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4
11540 
11541 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */
11542 #define    MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44
11543 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
11544 #define       MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4
11545 #define       MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40
11546 
11547 
11548 /***********************************/
11549 /* MC_CMD_RSS_CONTEXT_SET_TABLE
11550  * Set the indirection table for an RSS context.
11551  */
11552 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
11553 
11554 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11555 
11556 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */
11557 #define    MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132
11558 /* The handle of the RSS context */
11559 #define       MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
11560 #define       MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
11561 /* The 128-byte indirection table (1 byte per entry) */
11562 #define       MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4
11563 #define       MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128
11564 
11565 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */
11566 #define    MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0
11567 
11568 
11569 /***********************************/
11570 /* MC_CMD_RSS_CONTEXT_GET_TABLE
11571  * Get the indirection table for an RSS context.
11572  */
11573 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
11574 
11575 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11576 
11577 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */
11578 #define    MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4
11579 /* The handle of the RSS context */
11580 #define       MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
11581 #define       MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
11582 
11583 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */
11584 #define    MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132
11585 /* The 128-byte indirection table (1 byte per entry) */
11586 #define       MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4
11587 #define       MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128
11588 
11589 
11590 /***********************************/
11591 /* MC_CMD_RSS_CONTEXT_SET_FLAGS
11592  * Set various control flags for an RSS context.
11593  */
11594 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
11595 
11596 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11597 
11598 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */
11599 #define    MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8
11600 /* The handle of the RSS context */
11601 #define       MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
11602 #define       MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
11603 /* Hash control flags. The _EN bits are always supported, but new modes are
11604  * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES:
11605  * in this case, the MODE fields may be set to non-zero values, and will take
11606  * effect regardless of the settings of the _EN flags. See the RSS_MODE
11607  * structure for the meaning of the mode bits. Drivers must check the
11608  * capability before trying to set any _MODE fields, as older firmware will
11609  * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In
11610  * the case where all the _MODE flags are zero, the _EN flags take effect,
11611  * providing backward compatibility for existing drivers. (Setting all _MODE
11612  * *and* all _EN flags to zero is valid, to disable RSS spreading for that
11613  * particular packet type.)
11614  */
11615 #define       MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4
11616 #define       MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4
11617 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0
11618 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1
11619 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1
11620 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1
11621 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2
11622 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1
11623 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3
11624 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1
11625 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4
11626 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4
11627 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8
11628 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4
11629 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12
11630 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4
11631 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16
11632 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4
11633 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20
11634 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4
11635 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24
11636 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4
11637 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28
11638 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4
11639 
11640 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */
11641 #define    MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0
11642 
11643 
11644 /***********************************/
11645 /* MC_CMD_RSS_CONTEXT_GET_FLAGS
11646  * Get various control flags for an RSS context.
11647  */
11648 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
11649 
11650 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11651 
11652 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */
11653 #define    MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4
11654 /* The handle of the RSS context */
11655 #define       MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
11656 #define       MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
11657 
11658 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */
11659 #define    MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8
11660 /* Hash control flags. If all _MODE bits are zero (which will always be true
11661  * for older firmware which does not report the ADDITIONAL_RSS_MODES
11662  * capability), the _EN bits report the state. If any _MODE bits are non-zero
11663  * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES)
11664  * then the _EN bits should be disregarded, although the _MODE flags are
11665  * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS
11666  * context and in the case where the _EN flags were used in the SET. This
11667  * provides backward compatibility: old drivers will not be attempting to
11668  * derive any meaning from the _MODE bits (and can never set them to any value
11669  * not representable by the _EN bits); new drivers can always determine the
11670  * mode by looking only at the _MODE bits; the value returned by a GET can
11671  * always be used for a SET regardless of old/new driver vs. old/new firmware.
11672  */
11673 #define       MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4
11674 #define       MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4
11675 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0
11676 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1
11677 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1
11678 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1
11679 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2
11680 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1
11681 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3
11682 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1
11683 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4
11684 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4
11685 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8
11686 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4
11687 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12
11688 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4
11689 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16
11690 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4
11691 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20
11692 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4
11693 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24
11694 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4
11695 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28
11696 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4
11697 
11698 
11699 /***********************************/
11700 /* MC_CMD_DOT1P_MAPPING_ALLOC
11701  * Allocate a .1p mapping.
11702  */
11703 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4
11704 
11705 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11706 
11707 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */
11708 #define    MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8
11709 /* The handle of the owning upstream port */
11710 #define       MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11711 #define       MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
11712 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed
11713  * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and
11714  * referenced RSS contexts must span no more than this number.
11715  */
11716 #define       MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4
11717 #define       MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_LEN 4
11718 
11719 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */
11720 #define    MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4
11721 /* The handle of the new .1p mapping. This should be considered opaque to the
11722  * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
11723  * handle.
11724  */
11725 #define       MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0
11726 #define       MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_LEN 4
11727 /* enum: guaranteed invalid .1p mapping handle value */
11728 #define          MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff
11729 
11730 
11731 /***********************************/
11732 /* MC_CMD_DOT1P_MAPPING_FREE
11733  * Free a .1p mapping.
11734  */
11735 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5
11736 
11737 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11738 
11739 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */
11740 #define    MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4
11741 /* The handle of the .1p mapping */
11742 #define       MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0
11743 #define       MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_LEN 4
11744 
11745 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */
11746 #define    MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0
11747 
11748 
11749 /***********************************/
11750 /* MC_CMD_DOT1P_MAPPING_SET_TABLE
11751  * Set the mapping table for a .1p mapping.
11752  */
11753 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6
11754 
11755 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11756 
11757 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */
11758 #define    MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36
11759 /* The handle of the .1p mapping */
11760 #define       MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
11761 #define       MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4
11762 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
11763  * handle)
11764  */
11765 #define       MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4
11766 #define       MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32
11767 
11768 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */
11769 #define    MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0
11770 
11771 
11772 /***********************************/
11773 /* MC_CMD_DOT1P_MAPPING_GET_TABLE
11774  * Get the mapping table for a .1p mapping.
11775  */
11776 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7
11777 
11778 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11779 
11780 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */
11781 #define    MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4
11782 /* The handle of the .1p mapping */
11783 #define       MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
11784 #define       MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4
11785 
11786 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */
11787 #define    MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36
11788 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
11789  * handle)
11790  */
11791 #define       MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4
11792 #define       MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32
11793 
11794 
11795 /***********************************/
11796 /* MC_CMD_GET_VECTOR_CFG
11797  * Get Interrupt Vector config for this PF.
11798  */
11799 #define MC_CMD_GET_VECTOR_CFG 0xbf
11800 
11801 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11802 
11803 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */
11804 #define    MC_CMD_GET_VECTOR_CFG_IN_LEN 0
11805 
11806 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */
11807 #define    MC_CMD_GET_VECTOR_CFG_OUT_LEN 12
11808 /* Base absolute interrupt vector number. */
11809 #define       MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0
11810 #define       MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_LEN 4
11811 /* Number of interrupt vectors allocate to this PF. */
11812 #define       MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4
11813 #define       MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_LEN 4
11814 /* Number of interrupt vectors to allocate per VF. */
11815 #define       MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8
11816 #define       MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_LEN 4
11817 
11818 
11819 /***********************************/
11820 /* MC_CMD_SET_VECTOR_CFG
11821  * Set Interrupt Vector config for this PF.
11822  */
11823 #define MC_CMD_SET_VECTOR_CFG 0xc0
11824 
11825 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11826 
11827 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */
11828 #define    MC_CMD_SET_VECTOR_CFG_IN_LEN 12
11829 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to
11830  * let the system find a suitable base.
11831  */
11832 #define       MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0
11833 #define       MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_LEN 4
11834 /* Number of interrupt vectors allocate to this PF. */
11835 #define       MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4
11836 #define       MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_LEN 4
11837 /* Number of interrupt vectors to allocate per VF. */
11838 #define       MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8
11839 #define       MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_LEN 4
11840 
11841 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */
11842 #define    MC_CMD_SET_VECTOR_CFG_OUT_LEN 0
11843 
11844 
11845 /***********************************/
11846 /* MC_CMD_VPORT_ADD_MAC_ADDRESS
11847  * Add a MAC address to a v-port
11848  */
11849 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
11850 
11851 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11852 
11853 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */
11854 #define    MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10
11855 /* The handle of the v-port */
11856 #define       MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0
11857 #define       MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4
11858 /* MAC address to add */
11859 #define       MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4
11860 #define       MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6
11861 
11862 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */
11863 #define    MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0
11864 
11865 
11866 /***********************************/
11867 /* MC_CMD_VPORT_DEL_MAC_ADDRESS
11868  * Delete a MAC address from a v-port
11869  */
11870 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
11871 
11872 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11873 
11874 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */
11875 #define    MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10
11876 /* The handle of the v-port */
11877 #define       MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0
11878 #define       MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4
11879 /* MAC address to add */
11880 #define       MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4
11881 #define       MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6
11882 
11883 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */
11884 #define    MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0
11885 
11886 
11887 /***********************************/
11888 /* MC_CMD_VPORT_GET_MAC_ADDRESSES
11889  * Delete a MAC address from a v-port
11890  */
11891 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
11892 
11893 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11894 
11895 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */
11896 #define    MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4
11897 /* The handle of the v-port */
11898 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0
11899 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4
11900 
11901 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */
11902 #define    MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4
11903 #define    MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250
11904 #define    MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))
11905 /* The number of MAC addresses returned */
11906 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0
11907 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4
11908 /* Array of MAC addresses */
11909 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4
11910 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6
11911 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0
11912 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41
11913 
11914 
11915 /***********************************/
11916 /* MC_CMD_VPORT_RECONFIGURE
11917  * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port
11918  * has already been passed to another function (v-port's user), then that
11919  * function will be reset before applying the changes.
11920  */
11921 #define MC_CMD_VPORT_RECONFIGURE 0xeb
11922 
11923 #define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11924 
11925 /* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */
11926 #define    MC_CMD_VPORT_RECONFIGURE_IN_LEN 44
11927 /* The handle of the v-port */
11928 #define       MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0
11929 #define       MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4
11930 /* Flags requesting what should be changed. */
11931 #define       MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4
11932 #define       MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4
11933 #define        MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0
11934 #define        MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1
11935 #define        MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1
11936 #define        MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1
11937 /* The number of VLAN tags to insert/remove. An error will be returned if
11938  * incompatible with the number of VLAN tags specified for the upstream
11939  * v-switch.
11940  */
11941 #define       MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8
11942 #define       MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4
11943 /* The actual VLAN tags to insert/remove */
11944 #define       MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12
11945 #define       MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4
11946 #define        MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0
11947 #define        MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16
11948 #define        MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16
11949 #define        MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16
11950 /* The number of MAC addresses to add */
11951 #define       MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16
11952 #define       MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4
11953 /* MAC addresses to add */
11954 #define       MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20
11955 #define       MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6
11956 #define       MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4
11957 
11958 /* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */
11959 #define    MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4
11960 #define       MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0
11961 #define       MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4
11962 #define        MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0
11963 #define        MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1
11964 
11965 
11966 /***********************************/
11967 /* MC_CMD_EVB_PORT_QUERY
11968  * read some config of v-port.
11969  */
11970 #define MC_CMD_EVB_PORT_QUERY 0x62
11971 
11972 #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11973 
11974 /* MC_CMD_EVB_PORT_QUERY_IN msgrequest */
11975 #define    MC_CMD_EVB_PORT_QUERY_IN_LEN 4
11976 /* The handle of the v-port */
11977 #define       MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0
11978 #define       MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 4
11979 
11980 /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */
11981 #define    MC_CMD_EVB_PORT_QUERY_OUT_LEN 8
11982 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */
11983 #define       MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0
11984 #define       MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 4
11985 /* The number of VLAN tags that may be used on a v-adaptor connected to this
11986  * EVB port.
11987  */
11988 #define       MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4
11989 #define       MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
11990 
11991 
11992 /***********************************/
11993 /* MC_CMD_DUMP_BUFTBL_ENTRIES
11994  * Dump buffer table entries, mainly for command client debug use. Dumps
11995  * absolute entries, and does not use chunk handles. All entries must be in
11996  * range, and used for q page mapping, Although the latter restriction may be
11997  * lifted in future.
11998  */
11999 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab
12000 
12001 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_INSECURE
12002 
12003 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */
12004 #define    MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8
12005 /* Index of the first buffer table entry. */
12006 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0
12007 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4
12008 /* Number of buffer table entries to dump. */
12009 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4
12010 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4
12011 
12012 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */
12013 #define    MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12
12014 #define    MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252
12015 #define    MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num))
12016 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */
12017 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0
12018 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12
12019 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1
12020 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21
12021 
12022 
12023 /***********************************/
12024 /* MC_CMD_SET_RXDP_CONFIG
12025  * Set global RXDP configuration settings
12026  */
12027 #define MC_CMD_SET_RXDP_CONFIG 0xc1
12028 
12029 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12030 
12031 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */
12032 #define    MC_CMD_SET_RXDP_CONFIG_IN_LEN 4
12033 #define       MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0
12034 #define       MC_CMD_SET_RXDP_CONFIG_IN_DATA_LEN 4
12035 #define        MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0
12036 #define        MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1
12037 #define        MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1
12038 #define        MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2
12039 /* enum: pad to 64 bytes */
12040 #define          MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0
12041 /* enum: pad to 128 bytes (Medford only) */
12042 #define          MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1
12043 /* enum: pad to 256 bytes (Medford only) */
12044 #define          MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2
12045 
12046 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */
12047 #define    MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0
12048 
12049 
12050 /***********************************/
12051 /* MC_CMD_GET_RXDP_CONFIG
12052  * Get global RXDP configuration settings
12053  */
12054 #define MC_CMD_GET_RXDP_CONFIG 0xc2
12055 
12056 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12057 
12058 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */
12059 #define    MC_CMD_GET_RXDP_CONFIG_IN_LEN 0
12060 
12061 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */
12062 #define    MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4
12063 #define       MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0
12064 #define       MC_CMD_GET_RXDP_CONFIG_OUT_DATA_LEN 4
12065 #define        MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0
12066 #define        MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1
12067 #define        MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1
12068 #define        MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2
12069 /*             Enum values, see field(s): */
12070 /*                MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */
12071 
12072 
12073 /***********************************/
12074 /* MC_CMD_GET_CLOCK
12075  * Return the system and PDCPU clock frequencies.
12076  */
12077 #define MC_CMD_GET_CLOCK 0xac
12078 
12079 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12080 
12081 /* MC_CMD_GET_CLOCK_IN msgrequest */
12082 #define    MC_CMD_GET_CLOCK_IN_LEN 0
12083 
12084 /* MC_CMD_GET_CLOCK_OUT msgresponse */
12085 #define    MC_CMD_GET_CLOCK_OUT_LEN 8
12086 /* System frequency, MHz */
12087 #define       MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0
12088 #define       MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4
12089 /* DPCPU frequency, MHz */
12090 #define       MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4
12091 #define       MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4
12092 
12093 
12094 /***********************************/
12095 /* MC_CMD_SET_CLOCK
12096  * Control the system and DPCPU clock frequencies. Changes are lost reboot.
12097  */
12098 #define MC_CMD_SET_CLOCK 0xad
12099 
12100 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_INSECURE
12101 
12102 /* MC_CMD_SET_CLOCK_IN msgrequest */
12103 #define    MC_CMD_SET_CLOCK_IN_LEN 28
12104 /* Requested frequency in MHz for system clock domain */
12105 #define       MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0
12106 #define       MC_CMD_SET_CLOCK_IN_SYS_FREQ_LEN 4
12107 /* enum: Leave the system clock domain frequency unchanged */
12108 #define          MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0
12109 /* Requested frequency in MHz for inter-core clock domain */
12110 #define       MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4
12111 #define       MC_CMD_SET_CLOCK_IN_ICORE_FREQ_LEN 4
12112 /* enum: Leave the inter-core clock domain frequency unchanged */
12113 #define          MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0
12114 /* Requested frequency in MHz for DPCPU clock domain */
12115 #define       MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8
12116 #define       MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_LEN 4
12117 /* enum: Leave the DPCPU clock domain frequency unchanged */
12118 #define          MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0
12119 /* Requested frequency in MHz for PCS clock domain */
12120 #define       MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12
12121 #define       MC_CMD_SET_CLOCK_IN_PCS_FREQ_LEN 4
12122 /* enum: Leave the PCS clock domain frequency unchanged */
12123 #define          MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0
12124 /* Requested frequency in MHz for MC clock domain */
12125 #define       MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16
12126 #define       MC_CMD_SET_CLOCK_IN_MC_FREQ_LEN 4
12127 /* enum: Leave the MC clock domain frequency unchanged */
12128 #define          MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0
12129 /* Requested frequency in MHz for rmon clock domain */
12130 #define       MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20
12131 #define       MC_CMD_SET_CLOCK_IN_RMON_FREQ_LEN 4
12132 /* enum: Leave the rmon clock domain frequency unchanged */
12133 #define          MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0
12134 /* Requested frequency in MHz for vswitch clock domain */
12135 #define       MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24
12136 #define       MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_LEN 4
12137 /* enum: Leave the vswitch clock domain frequency unchanged */
12138 #define          MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0
12139 
12140 /* MC_CMD_SET_CLOCK_OUT msgresponse */
12141 #define    MC_CMD_SET_CLOCK_OUT_LEN 28
12142 /* Resulting system frequency in MHz */
12143 #define       MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0
12144 #define       MC_CMD_SET_CLOCK_OUT_SYS_FREQ_LEN 4
12145 /* enum: The system clock domain doesn't exist */
12146 #define          MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0
12147 /* Resulting inter-core frequency in MHz */
12148 #define       MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4
12149 #define       MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_LEN 4
12150 /* enum: The inter-core clock domain doesn't exist / isn't used */
12151 #define          MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0
12152 /* Resulting DPCPU frequency in MHz */
12153 #define       MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8
12154 #define       MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_LEN 4
12155 /* enum: The dpcpu clock domain doesn't exist */
12156 #define          MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0
12157 /* Resulting PCS frequency in MHz */
12158 #define       MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12
12159 #define       MC_CMD_SET_CLOCK_OUT_PCS_FREQ_LEN 4
12160 /* enum: The PCS clock domain doesn't exist / isn't controlled */
12161 #define          MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0
12162 /* Resulting MC frequency in MHz */
12163 #define       MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16
12164 #define       MC_CMD_SET_CLOCK_OUT_MC_FREQ_LEN 4
12165 /* enum: The MC clock domain doesn't exist / isn't controlled */
12166 #define          MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0
12167 /* Resulting rmon frequency in MHz */
12168 #define       MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20
12169 #define       MC_CMD_SET_CLOCK_OUT_RMON_FREQ_LEN 4
12170 /* enum: The rmon clock domain doesn't exist / isn't controlled */
12171 #define          MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0
12172 /* Resulting vswitch frequency in MHz */
12173 #define       MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24
12174 #define       MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_LEN 4
12175 /* enum: The vswitch clock domain doesn't exist / isn't controlled */
12176 #define          MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0
12177 
12178 
12179 /***********************************/
12180 /* MC_CMD_DPCPU_RPC
12181  * Send an arbitrary DPCPU message.
12182  */
12183 #define MC_CMD_DPCPU_RPC 0xae
12184 
12185 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_INSECURE
12186 
12187 /* MC_CMD_DPCPU_RPC_IN msgrequest */
12188 #define    MC_CMD_DPCPU_RPC_IN_LEN 36
12189 #define       MC_CMD_DPCPU_RPC_IN_CPU_OFST 0
12190 #define       MC_CMD_DPCPU_RPC_IN_CPU_LEN 4
12191 /* enum: RxDPCPU0 */
12192 #define          MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0
12193 /* enum: TxDPCPU0 */
12194 #define          MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1
12195 /* enum: TxDPCPU1 */
12196 #define          MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2
12197 /* enum: RxDPCPU1 (Medford only) */
12198 #define          MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3
12199 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of
12200  * DPCPU_RX0)
12201  */
12202 #define          MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80
12203 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of
12204  * DPCPU_TX0)
12205  */
12206 #define          MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81
12207 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be
12208  * initialised to zero
12209  */
12210 #define       MC_CMD_DPCPU_RPC_IN_DATA_OFST 4
12211 #define       MC_CMD_DPCPU_RPC_IN_DATA_LEN 32
12212 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8
12213 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8
12214 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */
12215 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */
12216 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */
12217 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */
12218 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */
12219 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */
12220 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */
12221 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */
12222 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */
12223 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16
12224 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16
12225 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16
12226 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16
12227 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48
12228 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16
12229 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16
12230 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240
12231 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16
12232 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16
12233 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */
12234 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */
12235 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */
12236 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */
12237 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */
12238 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48
12239 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16
12240 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64
12241 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16
12242 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80
12243 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16
12244 #define        MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16
12245 #define        MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16
12246 #define          MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */
12247 #define          MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */
12248 #define          MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */
12249 #define        MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64
12250 #define        MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16
12251 #define       MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12
12252 #define       MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24
12253 /* Register data to write. Only valid in write/write-read. */
12254 #define       MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16
12255 #define       MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_LEN 4
12256 /* Register address. */
12257 #define       MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20
12258 #define       MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_LEN 4
12259 
12260 /* MC_CMD_DPCPU_RPC_OUT msgresponse */
12261 #define    MC_CMD_DPCPU_RPC_OUT_LEN 36
12262 #define       MC_CMD_DPCPU_RPC_OUT_RC_OFST 0
12263 #define       MC_CMD_DPCPU_RPC_OUT_RC_LEN 4
12264 /* DATA */
12265 #define       MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4
12266 #define       MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32
12267 #define        MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32
12268 #define        MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16
12269 #define        MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48
12270 #define        MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16
12271 #define       MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12
12272 #define       MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24
12273 #define       MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12
12274 #define       MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_LEN 4
12275 #define       MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16
12276 #define       MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_LEN 4
12277 #define       MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20
12278 #define       MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_LEN 4
12279 #define       MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24
12280 #define       MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_LEN 4
12281 
12282 
12283 /***********************************/
12284 /* MC_CMD_TRIGGER_INTERRUPT
12285  * Trigger an interrupt by prodding the BIU.
12286  */
12287 #define MC_CMD_TRIGGER_INTERRUPT 0xe3
12288 
12289 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12290 
12291 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */
12292 #define    MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4
12293 /* Interrupt level relative to base for function. */
12294 #define       MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0
12295 #define       MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4
12296 
12297 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */
12298 #define    MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0
12299 
12300 
12301 /***********************************/
12302 /* MC_CMD_SHMBOOT_OP
12303  * Special operations to support (for now) shmboot.
12304  */
12305 #define MC_CMD_SHMBOOT_OP 0xe6
12306 
12307 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12308 
12309 /* MC_CMD_SHMBOOT_OP_IN msgrequest */
12310 #define    MC_CMD_SHMBOOT_OP_IN_LEN 4
12311 /* Identifies the operation to perform */
12312 #define       MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0
12313 #define       MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4
12314 /* enum: Copy slave_data section to the slave core. (Greenport only) */
12315 #define          MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0
12316 
12317 /* MC_CMD_SHMBOOT_OP_OUT msgresponse */
12318 #define    MC_CMD_SHMBOOT_OP_OUT_LEN 0
12319 
12320 
12321 /***********************************/
12322 /* MC_CMD_CAP_BLK_READ
12323  * Read multiple 64bit words from capture block memory
12324  */
12325 #define MC_CMD_CAP_BLK_READ 0xe7
12326 
12327 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_INSECURE
12328 
12329 /* MC_CMD_CAP_BLK_READ_IN msgrequest */
12330 #define    MC_CMD_CAP_BLK_READ_IN_LEN 12
12331 #define       MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0
12332 #define       MC_CMD_CAP_BLK_READ_IN_CAP_REG_LEN 4
12333 #define       MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4
12334 #define       MC_CMD_CAP_BLK_READ_IN_ADDR_LEN 4
12335 #define       MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8
12336 #define       MC_CMD_CAP_BLK_READ_IN_COUNT_LEN 4
12337 
12338 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */
12339 #define    MC_CMD_CAP_BLK_READ_OUT_LENMIN 8
12340 #define    MC_CMD_CAP_BLK_READ_OUT_LENMAX 248
12341 #define    MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num))
12342 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0
12343 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8
12344 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0
12345 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4
12346 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1
12347 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31
12348 
12349 
12350 /***********************************/
12351 /* MC_CMD_DUMP_DO
12352  * Take a dump of the DUT state
12353  */
12354 #define MC_CMD_DUMP_DO 0xe8
12355 
12356 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_INSECURE
12357 
12358 /* MC_CMD_DUMP_DO_IN msgrequest */
12359 #define    MC_CMD_DUMP_DO_IN_LEN 52
12360 #define       MC_CMD_DUMP_DO_IN_PADDING_OFST 0
12361 #define       MC_CMD_DUMP_DO_IN_PADDING_LEN 4
12362 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4
12363 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_LEN 4
12364 #define          MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */
12365 #define          MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */
12366 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
12367 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
12368 #define          MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */
12369 #define          MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */
12370 #define          MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */
12371 #define          MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */
12372 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
12373 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
12374 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
12375 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
12376 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12
12377 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
12378 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16
12379 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
12380 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
12381 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
12382 #define          MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */
12383 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
12384 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
12385 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
12386 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
12387 #define          MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */
12388 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
12389 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
12390 /* enum: The uart port this command was received over (if using a uart
12391  * transport)
12392  */
12393 #define          MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff
12394 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
12395 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
12396 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28
12397 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_LEN 4
12398 #define          MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */
12399 #define          MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */
12400 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
12401 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
12402 /*            Enum values, see field(s): */
12403 /*               MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
12404 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36
12405 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
12406 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40
12407 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
12408 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36
12409 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
12410 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40
12411 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
12412 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36
12413 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
12414 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40
12415 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
12416 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44
12417 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
12418 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36
12419 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
12420 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48
12421 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
12422 
12423 /* MC_CMD_DUMP_DO_OUT msgresponse */
12424 #define    MC_CMD_DUMP_DO_OUT_LEN 4
12425 #define       MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0
12426 #define       MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_LEN 4
12427 
12428 
12429 /***********************************/
12430 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED
12431  * Configure unsolicited dumps
12432  */
12433 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9
12434 
12435 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_INSECURE
12436 
12437 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */
12438 #define    MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52
12439 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0
12440 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_LEN 4
12441 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4
12442 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_LEN 4
12443 /*            Enum values, see field(s): */
12444 /*               MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */
12445 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
12446 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
12447 /*            Enum values, see field(s): */
12448 /*               MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
12449 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
12450 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
12451 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
12452 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
12453 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12
12454 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
12455 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16
12456 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
12457 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
12458 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
12459 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
12460 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
12461 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
12462 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
12463 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
12464 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
12465 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
12466 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
12467 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28
12468 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_LEN 4
12469 /*            Enum values, see field(s): */
12470 /*               MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */
12471 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
12472 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
12473 /*            Enum values, see field(s): */
12474 /*               MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
12475 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36
12476 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
12477 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40
12478 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
12479 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36
12480 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
12481 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40
12482 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
12483 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36
12484 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
12485 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40
12486 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
12487 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44
12488 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
12489 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36
12490 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
12491 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48
12492 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
12493 
12494 
12495 /***********************************/
12496 /* MC_CMD_SET_PSU
12497  * Adjusts power supply parameters. This is a warranty-voiding operation.
12498  * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if
12499  * the parameter is out of range.
12500  */
12501 #define MC_CMD_SET_PSU 0xea
12502 
12503 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE
12504 
12505 /* MC_CMD_SET_PSU_IN msgrequest */
12506 #define    MC_CMD_SET_PSU_IN_LEN 12
12507 #define       MC_CMD_SET_PSU_IN_PARAM_OFST 0
12508 #define       MC_CMD_SET_PSU_IN_PARAM_LEN 4
12509 #define          MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */
12510 #define       MC_CMD_SET_PSU_IN_RAIL_OFST 4
12511 #define       MC_CMD_SET_PSU_IN_RAIL_LEN 4
12512 #define          MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */
12513 #define          MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */
12514 /* desired value, eg voltage in mV */
12515 #define       MC_CMD_SET_PSU_IN_VALUE_OFST 8
12516 #define       MC_CMD_SET_PSU_IN_VALUE_LEN 4
12517 
12518 /* MC_CMD_SET_PSU_OUT msgresponse */
12519 #define    MC_CMD_SET_PSU_OUT_LEN 0
12520 
12521 
12522 /***********************************/
12523 /* MC_CMD_GET_FUNCTION_INFO
12524  * Get function information. PF and VF number.
12525  */
12526 #define MC_CMD_GET_FUNCTION_INFO 0xec
12527 
12528 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12529 
12530 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */
12531 #define    MC_CMD_GET_FUNCTION_INFO_IN_LEN 0
12532 
12533 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */
12534 #define    MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8
12535 #define       MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0
12536 #define       MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4
12537 #define       MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4
12538 #define       MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4
12539 
12540 
12541 /***********************************/
12542 /* MC_CMD_ENABLE_OFFLINE_BIST
12543  * Enters offline BIST mode. All queues are torn down, chip enters quiescent
12544  * mode, calling function gets exclusive MCDI ownership. The only way out is
12545  * reboot.
12546  */
12547 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed
12548 
12549 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12550 
12551 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */
12552 #define    MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0
12553 
12554 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */
12555 #define    MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0
12556 
12557 
12558 /***********************************/
12559 /* MC_CMD_UART_SEND_DATA
12560  * Send checksummed[sic] block of data over the uart. Response is a placeholder
12561  * should we wish to make this reliable; currently requests are fire-and-
12562  * forget.
12563  */
12564 #define MC_CMD_UART_SEND_DATA 0xee
12565 
12566 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12567 
12568 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */
12569 #define    MC_CMD_UART_SEND_DATA_OUT_LENMIN 16
12570 #define    MC_CMD_UART_SEND_DATA_OUT_LENMAX 252
12571 #define    MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num))
12572 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */
12573 #define       MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0
12574 #define       MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_LEN 4
12575 /* Offset at which to write the data */
12576 #define       MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4
12577 #define       MC_CMD_UART_SEND_DATA_OUT_OFFSET_LEN 4
12578 /* Length of data */
12579 #define       MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8
12580 #define       MC_CMD_UART_SEND_DATA_OUT_LENGTH_LEN 4
12581 /* Reserved for future use */
12582 #define       MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12
12583 #define       MC_CMD_UART_SEND_DATA_OUT_RESERVED_LEN 4
12584 #define       MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16
12585 #define       MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1
12586 #define       MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0
12587 #define       MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236
12588 
12589 /* MC_CMD_UART_SEND_DATA_IN msgresponse */
12590 #define    MC_CMD_UART_SEND_DATA_IN_LEN 0
12591 
12592 
12593 /***********************************/
12594 /* MC_CMD_UART_RECV_DATA
12595  * Request checksummed[sic] block of data over the uart. Only a placeholder,
12596  * subject to change and not currently implemented.
12597  */
12598 #define MC_CMD_UART_RECV_DATA 0xef
12599 
12600 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12601 
12602 /* MC_CMD_UART_RECV_DATA_OUT msgrequest */
12603 #define    MC_CMD_UART_RECV_DATA_OUT_LEN 16
12604 /* CRC32 over OFFSET, LENGTH, RESERVED */
12605 #define       MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0
12606 #define       MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_LEN 4
12607 /* Offset from which to read the data */
12608 #define       MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4
12609 #define       MC_CMD_UART_RECV_DATA_OUT_OFFSET_LEN 4
12610 /* Length of data */
12611 #define       MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8
12612 #define       MC_CMD_UART_RECV_DATA_OUT_LENGTH_LEN 4
12613 /* Reserved for future use */
12614 #define       MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12
12615 #define       MC_CMD_UART_RECV_DATA_OUT_RESERVED_LEN 4
12616 
12617 /* MC_CMD_UART_RECV_DATA_IN msgresponse */
12618 #define    MC_CMD_UART_RECV_DATA_IN_LENMIN 16
12619 #define    MC_CMD_UART_RECV_DATA_IN_LENMAX 252
12620 #define    MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num))
12621 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */
12622 #define       MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0
12623 #define       MC_CMD_UART_RECV_DATA_IN_CHECKSUM_LEN 4
12624 /* Offset at which to write the data */
12625 #define       MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4
12626 #define       MC_CMD_UART_RECV_DATA_IN_RESERVED1_LEN 4
12627 /* Length of data */
12628 #define       MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8
12629 #define       MC_CMD_UART_RECV_DATA_IN_RESERVED2_LEN 4
12630 /* Reserved for future use */
12631 #define       MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12
12632 #define       MC_CMD_UART_RECV_DATA_IN_RESERVED3_LEN 4
12633 #define       MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16
12634 #define       MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1
12635 #define       MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0
12636 #define       MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236
12637 
12638 
12639 /***********************************/
12640 /* MC_CMD_READ_FUSES
12641  * Read data programmed into the device One-Time-Programmable (OTP) Fuses
12642  */
12643 #define MC_CMD_READ_FUSES 0xf0
12644 
12645 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE
12646 
12647 /* MC_CMD_READ_FUSES_IN msgrequest */
12648 #define    MC_CMD_READ_FUSES_IN_LEN 8
12649 /* Offset in OTP to read */
12650 #define       MC_CMD_READ_FUSES_IN_OFFSET_OFST 0
12651 #define       MC_CMD_READ_FUSES_IN_OFFSET_LEN 4
12652 /* Length of data to read in bytes */
12653 #define       MC_CMD_READ_FUSES_IN_LENGTH_OFST 4
12654 #define       MC_CMD_READ_FUSES_IN_LENGTH_LEN 4
12655 
12656 /* MC_CMD_READ_FUSES_OUT msgresponse */
12657 #define    MC_CMD_READ_FUSES_OUT_LENMIN 4
12658 #define    MC_CMD_READ_FUSES_OUT_LENMAX 252
12659 #define    MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))
12660 /* Length of returned OTP data in bytes */
12661 #define       MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0
12662 #define       MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4
12663 /* Returned data */
12664 #define       MC_CMD_READ_FUSES_OUT_DATA_OFST 4
12665 #define       MC_CMD_READ_FUSES_OUT_DATA_LEN 1
12666 #define       MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0
12667 #define       MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248
12668 
12669 
12670 /***********************************/
12671 /* MC_CMD_KR_TUNE
12672  * Get or set KR Serdes RXEQ and TX Driver settings
12673  */
12674 #define MC_CMD_KR_TUNE 0xf1
12675 
12676 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12677 
12678 /* MC_CMD_KR_TUNE_IN msgrequest */
12679 #define    MC_CMD_KR_TUNE_IN_LENMIN 4
12680 #define    MC_CMD_KR_TUNE_IN_LENMAX 252
12681 #define    MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num))
12682 /* Requested operation */
12683 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0
12684 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1
12685 /* enum: Get current RXEQ settings */
12686 #define          MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0
12687 /* enum: Override RXEQ settings */
12688 #define          MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1
12689 /* enum: Get current TX Driver settings */
12690 #define          MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2
12691 /* enum: Override TX Driver settings */
12692 #define          MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3
12693 /* enum: Force KR Serdes reset / recalibration */
12694 #define          MC_CMD_KR_TUNE_IN_RECAL 0x4
12695 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid
12696  * signal.
12697  */
12698 #define          MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5
12699 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The
12700  * caller should call this command repeatedly after starting eye plot, until no
12701  * more data is returned.
12702  */
12703 #define          MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6
12704 /* enum: Read Figure Of Merit (eye quality, higher is better). */
12705 #define          MC_CMD_KR_TUNE_IN_READ_FOM 0x7
12706 /* enum: Start/stop link training frames */
12707 #define          MC_CMD_KR_TUNE_IN_LINK_TRAIN_RUN 0x8
12708 /* enum: Issue KR link training command (control training coefficients) */
12709 #define          MC_CMD_KR_TUNE_IN_LINK_TRAIN_CMD 0x9
12710 /* Align the arguments to 32 bits */
12711 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1
12712 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3
12713 /* Arguments specific to the operation */
12714 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4
12715 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4
12716 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0
12717 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62
12718 
12719 /* MC_CMD_KR_TUNE_OUT msgresponse */
12720 #define    MC_CMD_KR_TUNE_OUT_LEN 0
12721 
12722 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */
12723 #define    MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4
12724 /* Requested operation */
12725 #define       MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0
12726 #define       MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1
12727 /* Align the arguments to 32 bits */
12728 #define       MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
12729 #define       MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3
12730 
12731 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */
12732 #define    MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4
12733 #define    MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252
12734 #define    MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
12735 /* RXEQ Parameter */
12736 #define       MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
12737 #define       MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
12738 #define       MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
12739 #define       MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
12740 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
12741 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
12742 /* enum: Attenuation (0-15, Huntington) */
12743 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0
12744 /* enum: CTLE Boost (0-15, Huntington) */
12745 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1
12746 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max
12747  * positive, Medford - 0-31)
12748  */
12749 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2
12750 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max
12751  * positive, Medford - 0-31)
12752  */
12753 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3
12754 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max
12755  * positive, Medford - 0-16)
12756  */
12757 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4
12758 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max
12759  * positive, Medford - 0-16)
12760  */
12761 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5
12762 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max
12763  * positive, Medford - 0-16)
12764  */
12765 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6
12766 /* enum: Edge DFE DLEV (0-128 for Medford) */
12767 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7
12768 /* enum: Variable Gain Amplifier (0-15, Medford) */
12769 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8
12770 /* enum: CTLE EQ Capacitor (0-15, Medford) */
12771 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
12772 /* enum: CTLE EQ Resistor (0-7, Medford) */
12773 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
12774 /* enum: CTLE gain (0-31, Medford2) */
12775 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN 0xb
12776 /* enum: CTLE pole (0-31, Medford2) */
12777 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc
12778 /* enum: CTLE peaking (0-31, Medford2) */
12779 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd
12780 /* enum: DFE Tap1 - even path (Medford2 - 6 bit signed (-29 - +29)) */
12781 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe
12782 /* enum: DFE Tap1 - odd path (Medford2 - 6 bit signed (-29 - +29)) */
12783 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf
12784 /* enum: DFE Tap2 (Medford2 - 6 bit signed (-20 - +20)) */
12785 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10
12786 /* enum: DFE Tap3 (Medford2 - 6 bit signed (-20 - +20)) */
12787 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11
12788 /* enum: DFE Tap4 (Medford2 - 6 bit signed (-20 - +20)) */
12789 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12
12790 /* enum: DFE Tap5 (Medford2 - 6 bit signed (-24 - +24)) */
12791 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13
12792 /* enum: DFE Tap6 (Medford2 - 6 bit signed (-24 - +24)) */
12793 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14
12794 /* enum: DFE Tap7 (Medford2 - 6 bit signed (-24 - +24)) */
12795 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15
12796 /* enum: DFE Tap8 (Medford2 - 6 bit signed (-24 - +24)) */
12797 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16
12798 /* enum: DFE Tap9 (Medford2 - 6 bit signed (-24 - +24)) */
12799 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17
12800 /* enum: DFE Tap10 (Medford2 - 6 bit signed (-24 - +24)) */
12801 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18
12802 /* enum: DFE Tap11 (Medford2 - 6 bit signed (-24 - +24)) */
12803 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19
12804 /* enum: DFE Tap12 (Medford2 - 6 bit signed (-24 - +24)) */
12805 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a
12806 /* enum: I/Q clk offset (Medford2 - 4 bit signed (-5 - +5))) */
12807 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b
12808 /* enum: Negative h1 polarity data sampler offset calibration code, even path
12809  * (Medford2 - 6 bit signed (-29 - +29)))
12810  */
12811 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_EVEN 0x1c
12812 /* enum: Negative h1 polarity data sampler offset calibration code, odd path
12813  * (Medford2 - 6 bit signed (-29 - +29)))
12814  */
12815 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_ODD 0x1d
12816 /* enum: Positive h1 polarity data sampler offset calibration code, even path
12817  * (Medford2 - 6 bit signed (-29 - +29)))
12818  */
12819 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_EVEN 0x1e
12820 /* enum: Positive h1 polarity data sampler offset calibration code, odd path
12821  * (Medford2 - 6 bit signed (-29 - +29)))
12822  */
12823 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_ODD 0x1f
12824 /* enum: CDR calibration loop code (Medford2) */
12825 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_PVT 0x20
12826 /* enum: CDR integral loop code (Medford2) */
12827 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_INTEG 0x21
12828 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
12829 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3
12830 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
12831 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
12832 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
12833 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
12834 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
12835 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11
12836 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
12837 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12
12838 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4
12839 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16
12840 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
12841 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
12842 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
12843 
12844 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */
12845 #define    MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8
12846 #define    MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252
12847 #define    MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
12848 /* Requested operation */
12849 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0
12850 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1
12851 /* Align the arguments to 32 bits */
12852 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
12853 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3
12854 /* RXEQ Parameter */
12855 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4
12856 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4
12857 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
12858 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62
12859 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
12860 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8
12861 /*             Enum values, see field(s): */
12862 /*                MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */
12863 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8
12864 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3
12865 /*             Enum values, see field(s): */
12866 /*                MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */
12867 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11
12868 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
12869 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12
12870 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4
12871 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16
12872 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
12873 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24
12874 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8
12875 
12876 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */
12877 #define    MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0
12878 
12879 /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */
12880 #define    MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4
12881 /* Requested operation */
12882 #define       MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0
12883 #define       MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1
12884 /* Align the arguments to 32 bits */
12885 #define       MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
12886 #define       MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3
12887 
12888 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */
12889 #define    MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4
12890 #define    MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252
12891 #define    MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
12892 /* TXEQ Parameter */
12893 #define       MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
12894 #define       MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
12895 #define       MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
12896 #define       MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63
12897 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
12898 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
12899 /* enum: TX Amplitude (Huntington, Medford, Medford2) */
12900 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0
12901 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */
12902 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1
12903 /* enum: De-Emphasis Tap1 Fine */
12904 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2
12905 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */
12906 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3
12907 /* enum: De-Emphasis Tap2 Fine (Huntington) */
12908 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4
12909 /* enum: Pre-Emphasis Magnitude (Huntington) */
12910 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5
12911 /* enum: Pre-Emphasis Fine (Huntington) */
12912 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6
12913 /* enum: TX Slew Rate Coarse control (Huntington) */
12914 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7
12915 /* enum: TX Slew Rate Fine control (Huntington) */
12916 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8
12917 /* enum: TX Termination Impedance control (Huntington) */
12918 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9
12919 /* enum: TX Amplitude Fine control (Medford) */
12920 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa
12921 /* enum: Pre-shoot Tap (Medford, Medford2) */
12922 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb
12923 /* enum: De-emphasis Tap (Medford, Medford2) */
12924 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc
12925 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
12926 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3
12927 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */
12928 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */
12929 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */
12930 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */
12931 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
12932 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11
12933 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5
12934 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16
12935 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
12936 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24
12937 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8
12938 
12939 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */
12940 #define    MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8
12941 #define    MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252
12942 #define    MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num))
12943 /* Requested operation */
12944 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0
12945 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1
12946 /* Align the arguments to 32 bits */
12947 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
12948 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3
12949 /* TXEQ Parameter */
12950 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4
12951 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4
12952 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1
12953 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62
12954 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0
12955 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8
12956 /*             Enum values, see field(s): */
12957 /*                MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */
12958 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8
12959 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3
12960 /*             Enum values, see field(s): */
12961 /*                MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */
12962 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11
12963 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5
12964 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16
12965 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
12966 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24
12967 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8
12968 
12969 /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */
12970 #define    MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0
12971 
12972 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */
12973 #define    MC_CMD_KR_TUNE_RECAL_IN_LEN 4
12974 /* Requested operation */
12975 #define       MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0
12976 #define       MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1
12977 /* Align the arguments to 32 bits */
12978 #define       MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1
12979 #define       MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3
12980 
12981 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */
12982 #define    MC_CMD_KR_TUNE_RECAL_OUT_LEN 0
12983 
12984 /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */
12985 #define    MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8
12986 /* Requested operation */
12987 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
12988 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
12989 /* Align the arguments to 32 bits */
12990 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
12991 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3
12992 /* Port-relative lane to scan eye on */
12993 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
12994 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_LEN 4
12995 
12996 /* MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN msgrequest */
12997 #define    MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LEN 12
12998 /* Requested operation */
12999 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_OFST 0
13000 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_LEN 1
13001 /* Align the arguments to 32 bits */
13002 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_OFST 1
13003 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_LEN 3
13004 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4
13005 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4
13006 #define        MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_LBN 0
13007 #define        MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_WIDTH 8
13008 #define        MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_LBN 31
13009 #define        MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_WIDTH 1
13010 /* Scan duration / cycle count */
13011 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_OFST 8
13012 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4
13013 
13014 /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */
13015 #define    MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0
13016 
13017 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */
13018 #define    MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4
13019 /* Requested operation */
13020 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
13021 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
13022 /* Align the arguments to 32 bits */
13023 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
13024 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3
13025 
13026 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */
13027 #define    MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
13028 #define    MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
13029 #define    MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
13030 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
13031 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
13032 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
13033 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126
13034 
13035 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */
13036 #define    MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8
13037 /* Requested operation */
13038 #define       MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0
13039 #define       MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1
13040 /* Align the arguments to 32 bits */
13041 #define       MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1
13042 #define       MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3
13043 #define       MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4
13044 #define       MC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4
13045 #define        MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_LBN 0
13046 #define        MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_WIDTH 8
13047 #define        MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_LBN 31
13048 #define        MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_WIDTH 1
13049 
13050 /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */
13051 #define    MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4
13052 #define       MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0
13053 #define       MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4
13054 
13055 /* MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN msgrequest */
13056 #define    MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_LEN 8
13057 /* Requested operation */
13058 #define       MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_OFST 0
13059 #define       MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_LEN 1
13060 /* Align the arguments to 32 bits */
13061 #define       MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_OFST 1
13062 #define       MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_LEN 3
13063 #define       MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_OFST 4
13064 #define       MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_LEN 4
13065 #define          MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_STOP 0x0 /* enum */
13066 #define          MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_START 0x1 /* enum */
13067 
13068 /* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN msgrequest */
13069 #define    MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LEN 28
13070 /* Requested operation */
13071 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_OFST 0
13072 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_LEN 1
13073 /* Align the arguments to 32 bits */
13074 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_OFST 1
13075 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_LEN 3
13076 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_OFST 4
13077 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_LEN 4
13078 /* Set INITIALIZE state */
13079 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_OFST 8
13080 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_LEN 4
13081 /* Set PRESET state */
13082 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_OFST 12
13083 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_LEN 4
13084 /* C(-1) request */
13085 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_OFST 16
13086 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_LEN 4
13087 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_HOLD 0x0 /* enum */
13088 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_INCREMENT 0x1 /* enum */
13089 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_DECREMENT 0x2 /* enum */
13090 /* C(0) request */
13091 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_OFST 20
13092 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_LEN 4
13093 /*            Enum values, see field(s): */
13094 /*               MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
13095 /* C(+1) request */
13096 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_OFST 24
13097 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_LEN 4
13098 /*            Enum values, see field(s): */
13099 /*               MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
13100 
13101 /* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT msgresponse */
13102 #define    MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_LEN 24
13103 /* C(-1) status */
13104 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_OFST 0
13105 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_LEN 4
13106 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_NOT_UPDATED 0x0 /* enum */
13107 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_UPDATED 0x1 /* enum */
13108 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MINIMUM 0x2 /* enum */
13109 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MAXIMUM 0x3 /* enum */
13110 /* C(0) status */
13111 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_OFST 4
13112 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_LEN 4
13113 /*            Enum values, see field(s): */
13114 /*               MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
13115 /* C(+1) status */
13116 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_OFST 8
13117 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_LEN 4
13118 /*            Enum values, see field(s): */
13119 /*               MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
13120 /* C(-1) value */
13121 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_OFST 12
13122 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_LEN 4
13123 /* C(0) value */
13124 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_OFST 16
13125 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_LEN 4
13126 /* C(+1) status */
13127 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_OFST 20
13128 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_LEN 4
13129 
13130 
13131 /***********************************/
13132 /* MC_CMD_PCIE_TUNE
13133  * Get or set PCIE Serdes RXEQ and TX Driver settings
13134  */
13135 #define MC_CMD_PCIE_TUNE 0xf2
13136 
13137 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13138 
13139 /* MC_CMD_PCIE_TUNE_IN msgrequest */
13140 #define    MC_CMD_PCIE_TUNE_IN_LENMIN 4
13141 #define    MC_CMD_PCIE_TUNE_IN_LENMAX 252
13142 #define    MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num))
13143 /* Requested operation */
13144 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0
13145 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1
13146 /* enum: Get current RXEQ settings */
13147 #define          MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0
13148 /* enum: Override RXEQ settings */
13149 #define          MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1
13150 /* enum: Get current TX Driver settings */
13151 #define          MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2
13152 /* enum: Override TX Driver settings */
13153 #define          MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3
13154 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */
13155 #define          MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5
13156 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The
13157  * caller should call this command repeatedly after starting eye plot, until no
13158  * more data is returned.
13159  */
13160 #define          MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6
13161 /* enum: Enable the SERDES BIST and set it to generate a 200MHz square wave */
13162 #define          MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7
13163 /* Align the arguments to 32 bits */
13164 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1
13165 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3
13166 /* Arguments specific to the operation */
13167 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4
13168 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4
13169 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0
13170 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62
13171 
13172 /* MC_CMD_PCIE_TUNE_OUT msgresponse */
13173 #define    MC_CMD_PCIE_TUNE_OUT_LEN 0
13174 
13175 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */
13176 #define    MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4
13177 /* Requested operation */
13178 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
13179 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
13180 /* Align the arguments to 32 bits */
13181 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
13182 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3
13183 
13184 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */
13185 #define    MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4
13186 #define    MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252
13187 #define    MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
13188 /* RXEQ Parameter */
13189 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
13190 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
13191 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
13192 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
13193 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
13194 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
13195 /* enum: Attenuation (0-15) */
13196 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0
13197 /* enum: CTLE Boost (0-15) */
13198 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1
13199 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */
13200 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2
13201 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */
13202 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3
13203 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */
13204 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4
13205 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */
13206 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5
13207 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */
13208 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6
13209 /* enum: DFE DLev */
13210 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7
13211 /* enum: Figure of Merit */
13212 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8
13213 /* enum: CTLE EQ Capacitor (HF Gain) */
13214 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
13215 /* enum: CTLE EQ Resistor (DC Gain) */
13216 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
13217 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
13218 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5
13219 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
13220 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
13221 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
13222 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
13223 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */
13224 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */
13225 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */
13226 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */
13227 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */
13228 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */
13229 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */
13230 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */
13231 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */
13232 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */
13233 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */
13234 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */
13235 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */
13236 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13
13237 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
13238 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14
13239 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10
13240 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
13241 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
13242 
13243 /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */
13244 #define    MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8
13245 #define    MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252
13246 #define    MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
13247 /* Requested operation */
13248 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0
13249 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1
13250 /* Align the arguments to 32 bits */
13251 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1
13252 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3
13253 /* RXEQ Parameter */
13254 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4
13255 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4
13256 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
13257 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62
13258 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
13259 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8
13260 /*             Enum values, see field(s): */
13261 /*                MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */
13262 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8
13263 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5
13264 /*             Enum values, see field(s): */
13265 /*                MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */
13266 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13
13267 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
13268 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14
13269 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2
13270 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16
13271 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
13272 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24
13273 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8
13274 
13275 /* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */
13276 #define    MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0
13277 
13278 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */
13279 #define    MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4
13280 /* Requested operation */
13281 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
13282 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
13283 /* Align the arguments to 32 bits */
13284 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
13285 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3
13286 
13287 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */
13288 #define    MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4
13289 #define    MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252
13290 #define    MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
13291 /* RXEQ Parameter */
13292 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
13293 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
13294 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
13295 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63
13296 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
13297 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
13298 /* enum: TxMargin (PIPE) */
13299 #define          MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0
13300 /* enum: TxSwing (PIPE) */
13301 #define          MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1
13302 /* enum: De-emphasis coefficient C(-1) (PIPE) */
13303 #define          MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2
13304 /* enum: De-emphasis coefficient C(0) (PIPE) */
13305 #define          MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3
13306 /* enum: De-emphasis coefficient C(+1) (PIPE) */
13307 #define          MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4
13308 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
13309 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4
13310 /*             Enum values, see field(s): */
13311 /*                MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */
13312 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12
13313 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12
13314 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24
13315 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
13316 
13317 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */
13318 #define    MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8
13319 /* Requested operation */
13320 #define       MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
13321 #define       MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1
13322 /* Align the arguments to 32 bits */
13323 #define       MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1
13324 #define       MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3
13325 #define       MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
13326 #define       MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_LEN 4
13327 
13328 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */
13329 #define    MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0
13330 
13331 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */
13332 #define    MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4
13333 /* Requested operation */
13334 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
13335 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1
13336 /* Align the arguments to 32 bits */
13337 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1
13338 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3
13339 
13340 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */
13341 #define    MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
13342 #define    MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
13343 #define    MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
13344 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
13345 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
13346 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
13347 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126
13348 
13349 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN msgrequest */
13350 #define    MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0
13351 
13352 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT msgrequest */
13353 #define    MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0
13354 
13355 
13356 /***********************************/
13357 /* MC_CMD_LICENSING
13358  * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition
13359  * - not used for V3 licensing
13360  */
13361 #define MC_CMD_LICENSING 0xf3
13362 
13363 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13364 
13365 /* MC_CMD_LICENSING_IN msgrequest */
13366 #define    MC_CMD_LICENSING_IN_LEN 4
13367 /* identifies the type of operation requested */
13368 #define       MC_CMD_LICENSING_IN_OP_OFST 0
13369 #define       MC_CMD_LICENSING_IN_OP_LEN 4
13370 /* enum: re-read and apply licenses after a license key partition update; note
13371  * that this operation returns a zero-length response
13372  */
13373 #define          MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0
13374 /* enum: report counts of installed licenses */
13375 #define          MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1
13376 
13377 /* MC_CMD_LICENSING_OUT msgresponse */
13378 #define    MC_CMD_LICENSING_OUT_LEN 28
13379 /* count of application keys which are valid */
13380 #define       MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0
13381 #define       MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4
13382 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with
13383  * MC_CMD_FC_OP_LICENSE)
13384  */
13385 #define       MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4
13386 #define       MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4
13387 /* count of application keys which are invalid due to being blacklisted */
13388 #define       MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8
13389 #define       MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4
13390 /* count of application keys which are invalid due to being unverifiable */
13391 #define       MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12
13392 #define       MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4
13393 /* count of application keys which are invalid due to being for the wrong node
13394  */
13395 #define       MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16
13396 #define       MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4
13397 /* licensing state (for diagnostics; the exact meaning of the bits in this
13398  * field are private to the firmware)
13399  */
13400 #define       MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20
13401 #define       MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4
13402 /* licensing subsystem self-test report (for manftest) */
13403 #define       MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24
13404 #define       MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4
13405 /* enum: licensing subsystem self-test failed */
13406 #define          MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0
13407 /* enum: licensing subsystem self-test passed */
13408 #define          MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1
13409 
13410 
13411 /***********************************/
13412 /* MC_CMD_LICENSING_V3
13413  * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition
13414  * - V3 licensing (Medford)
13415  */
13416 #define MC_CMD_LICENSING_V3 0xd0
13417 
13418 #define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13419 
13420 /* MC_CMD_LICENSING_V3_IN msgrequest */
13421 #define    MC_CMD_LICENSING_V3_IN_LEN 4
13422 /* identifies the type of operation requested */
13423 #define       MC_CMD_LICENSING_V3_IN_OP_OFST 0
13424 #define       MC_CMD_LICENSING_V3_IN_OP_LEN 4
13425 /* enum: re-read and apply licenses after a license key partition update; note
13426  * that this operation returns a zero-length response
13427  */
13428 #define          MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0
13429 /* enum: report counts of installed licenses Returns EAGAIN if license
13430  * processing (updating) has been started but not yet completed.
13431  */
13432 #define          MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1
13433 
13434 /* MC_CMD_LICENSING_V3_OUT msgresponse */
13435 #define    MC_CMD_LICENSING_V3_OUT_LEN 88
13436 /* count of keys which are valid */
13437 #define       MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0
13438 #define       MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4
13439 /* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with
13440  * MC_CMD_FC_OP_LICENSE)
13441  */
13442 #define       MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4
13443 #define       MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4
13444 /* count of keys which are invalid due to being unverifiable */
13445 #define       MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8
13446 #define       MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4
13447 /* count of keys which are invalid due to being for the wrong node */
13448 #define       MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12
13449 #define       MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4
13450 /* licensing state (for diagnostics; the exact meaning of the bits in this
13451  * field are private to the firmware)
13452  */
13453 #define       MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16
13454 #define       MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4
13455 /* licensing subsystem self-test report (for manftest) */
13456 #define       MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20
13457 #define       MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4
13458 /* enum: licensing subsystem self-test failed */
13459 #define          MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0
13460 /* enum: licensing subsystem self-test passed */
13461 #define          MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1
13462 /* bitmask of licensed applications */
13463 #define       MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24
13464 #define       MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8
13465 #define       MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24
13466 #define       MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28
13467 /* reserved for future use */
13468 #define       MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32
13469 #define       MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24
13470 /* bitmask of licensed features */
13471 #define       MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56
13472 #define       MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8
13473 #define       MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56
13474 #define       MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60
13475 /* reserved for future use */
13476 #define       MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64
13477 #define       MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24
13478 
13479 
13480 /***********************************/
13481 /* MC_CMD_LICENSING_GET_ID_V3
13482  * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license
13483  * partition - V3 licensing (Medford)
13484  */
13485 #define MC_CMD_LICENSING_GET_ID_V3 0xd1
13486 
13487 #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13488 
13489 /* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */
13490 #define    MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0
13491 
13492 /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */
13493 #define    MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8
13494 #define    MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252
13495 #define    MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num))
13496 /* type of license (eg 3) */
13497 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0
13498 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4
13499 /* length of the license ID (in bytes) */
13500 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4
13501 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 4
13502 /* the unique license ID of the adapter */
13503 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8
13504 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1
13505 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0
13506 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244
13507 
13508 
13509 /***********************************/
13510 /* MC_CMD_MC2MC_PROXY
13511  * Execute an arbitrary MCDI command on the slave MC of a dual-core device.
13512  * This will fail on a single-core system.
13513  */
13514 #define MC_CMD_MC2MC_PROXY 0xf4
13515 
13516 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13517 
13518 /* MC_CMD_MC2MC_PROXY_IN msgrequest */
13519 #define    MC_CMD_MC2MC_PROXY_IN_LEN 0
13520 
13521 /* MC_CMD_MC2MC_PROXY_OUT msgresponse */
13522 #define    MC_CMD_MC2MC_PROXY_OUT_LEN 0
13523 
13524 
13525 /***********************************/
13526 /* MC_CMD_GET_LICENSED_APP_STATE
13527  * Query the state of an individual licensed application. (Note that the actual
13528  * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation
13529  * or a reboot of the MC.) Not used for V3 licensing
13530  */
13531 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5
13532 
13533 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13534 
13535 /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */
13536 #define    MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4
13537 /* application ID to query (LICENSED_APP_ID_xxx) */
13538 #define       MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0
13539 #define       MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4
13540 
13541 /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */
13542 #define    MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4
13543 /* state of this application */
13544 #define       MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0
13545 #define       MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4
13546 /* enum: no (or invalid) license is present for the application */
13547 #define          MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0
13548 /* enum: a valid license is present for the application */
13549 #define          MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1
13550 
13551 
13552 /***********************************/
13553 /* MC_CMD_GET_LICENSED_V3_APP_STATE
13554  * Query the state of an individual licensed application. (Note that the actual
13555  * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE
13556  * operation or a reboot of the MC.) Used for V3 licensing (Medford)
13557  */
13558 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2
13559 
13560 #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13561 
13562 /* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */
13563 #define    MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8
13564 /* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit
13565  * mask
13566  */
13567 #define       MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0
13568 #define       MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8
13569 #define       MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0
13570 #define       MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4
13571 
13572 /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */
13573 #define    MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4
13574 /* state of this application */
13575 #define       MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0
13576 #define       MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4
13577 /* enum: no (or invalid) license is present for the application */
13578 #define          MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0
13579 /* enum: a valid license is present for the application */
13580 #define          MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1
13581 
13582 
13583 /***********************************/
13584 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES
13585  * Query the state of one or more licensed features. (Note that the actual
13586  * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE
13587  * operation or a reboot of the MC.) Used for V3 licensing (Medford)
13588  */
13589 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3
13590 
13591 #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13592 
13593 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */
13594 #define    MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8
13595 /* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or
13596  * more bits set
13597  */
13598 #define       MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0
13599 #define       MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8
13600 #define       MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0
13601 #define       MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4
13602 
13603 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */
13604 #define    MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8
13605 /* states of these features - bit set for licensed, clear for not licensed */
13606 #define       MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0
13607 #define       MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8
13608 #define       MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0
13609 #define       MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4
13610 
13611 
13612 /***********************************/
13613 /* MC_CMD_LICENSED_APP_OP
13614  * Perform an action for an individual licensed application - not used for V3
13615  * licensing.
13616  */
13617 #define MC_CMD_LICENSED_APP_OP 0xf6
13618 
13619 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13620 
13621 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */
13622 #define    MC_CMD_LICENSED_APP_OP_IN_LENMIN 8
13623 #define    MC_CMD_LICENSED_APP_OP_IN_LENMAX 252
13624 #define    MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num))
13625 /* application ID */
13626 #define       MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0
13627 #define       MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4
13628 /* the type of operation requested */
13629 #define       MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4
13630 #define       MC_CMD_LICENSED_APP_OP_IN_OP_LEN 4
13631 /* enum: validate application */
13632 #define          MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0
13633 /* enum: mask application */
13634 #define          MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1
13635 /* arguments specific to this particular operation */
13636 #define       MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8
13637 #define       MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4
13638 #define       MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0
13639 #define       MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61
13640 
13641 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */
13642 #define    MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0
13643 #define    MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252
13644 #define    MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))
13645 /* result specific to this particular operation */
13646 #define       MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0
13647 #define       MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4
13648 #define       MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0
13649 #define       MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63
13650 
13651 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */
13652 #define    MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72
13653 /* application ID */
13654 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0
13655 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 4
13656 /* the type of operation requested */
13657 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4
13658 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 4
13659 /* validation challenge */
13660 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8
13661 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64
13662 
13663 /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */
13664 #define    MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68
13665 /* feature expiry (time_t) */
13666 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0
13667 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 4
13668 /* validation response */
13669 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4
13670 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64
13671 
13672 /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */
13673 #define    MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12
13674 /* application ID */
13675 #define       MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0
13676 #define       MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 4
13677 /* the type of operation requested */
13678 #define       MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4
13679 #define       MC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 4
13680 /* flag */
13681 #define       MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8
13682 #define       MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 4
13683 
13684 /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */
13685 #define    MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0
13686 
13687 
13688 /***********************************/
13689 /* MC_CMD_LICENSED_V3_VALIDATE_APP
13690  * Perform validation for an individual licensed application - V3 licensing
13691  * (Medford)
13692  */
13693 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4
13694 
13695 #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13696 
13697 /* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */
13698 #define    MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 56
13699 /* challenge for validation (384 bits) */
13700 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0
13701 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 48
13702 /* application ID expressed as a single bit mask */
13703 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48
13704 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8
13705 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48
13706 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52
13707 
13708 /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */
13709 #define    MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116
13710 /* validation response to challenge in the form of ECDSA signature consisting
13711  * of two 384-bit integers, r and s, in big-endian order. The signature signs a
13712  * SHA-384 digest of a message constructed from the concatenation of the input
13713  * message and the remaining fields of this output message, e.g. challenge[48
13714  * bytes] ... expiry_time[4 bytes] ...
13715  */
13716 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0
13717 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96
13718 /* application expiry time */
13719 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96
13720 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 4
13721 /* application expiry units */
13722 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100
13723 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4
13724 /* enum: expiry units are accounting units */
13725 #define          MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0
13726 /* enum: expiry units are calendar days */
13727 #define          MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1
13728 /* base MAC address of the NIC stored in NVRAM (note that this is a constant
13729  * value for a given NIC regardless which function is calling, effectively this
13730  * is PF0 base MAC address)
13731  */
13732 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_OFST 104
13733 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_LEN 6
13734 /* MAC address of v-adaptor associated with the client. If no such v-adapator
13735  * exists, then the field is filled with 0xFF.
13736  */
13737 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 110
13738 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 6
13739 
13740 
13741 /***********************************/
13742 /* MC_CMD_LICENSED_V3_MASK_FEATURES
13743  * Mask features - V3 licensing (Medford)
13744  */
13745 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5
13746 
13747 #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13748 
13749 /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */
13750 #define    MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12
13751 /* mask to be applied to features to be changed */
13752 #define       MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0
13753 #define       MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8
13754 #define       MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0
13755 #define       MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4
13756 /* whether to turn on or turn off the masked features */
13757 #define       MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8
13758 #define       MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4
13759 /* enum: turn the features off */
13760 #define          MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0
13761 /* enum: turn the features back on */
13762 #define          MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1
13763 
13764 /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */
13765 #define    MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0
13766 
13767 
13768 /***********************************/
13769 /* MC_CMD_LICENSING_V3_TEMPORARY
13770  * Perform operations to support installation of a single temporary license in
13771  * the adapter, in addition to those found in the licensing partition. See
13772  * SF-116124-SW for an overview of how this could be used. The license is
13773  * stored in MC persistent data and so will survive a MC reboot, but will be
13774  * erased when the adapter is power cycled
13775  */
13776 #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6
13777 
13778 #define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13779 
13780 /* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */
13781 #define    MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4
13782 /* operation code */
13783 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0
13784 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 4
13785 /* enum: install a new license, overwriting any existing temporary license.
13786  * This is an asynchronous operation owing to the time taken to validate an
13787  * ECDSA license
13788  */
13789 #define          MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0
13790 /* enum: clear the license immediately rather than waiting for the next power
13791  * cycle
13792  */
13793 #define          MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1
13794 /* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET
13795  * operation
13796  */
13797 #define          MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2
13798 
13799 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */
13800 #define    MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164
13801 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0
13802 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 4
13803 /* ECDSA license and signature */
13804 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4
13805 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160
13806 
13807 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */
13808 #define    MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4
13809 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0
13810 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 4
13811 
13812 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */
13813 #define    MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4
13814 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0
13815 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 4
13816 
13817 /* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */
13818 #define    MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12
13819 /* status code */
13820 #define       MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0
13821 #define       MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4
13822 /* enum: finished validating and installing license */
13823 #define          MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0
13824 /* enum: license validation and installation in progress */
13825 #define          MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1
13826 /* enum: licensing error. More specific error messages are not provided to
13827  * avoid exposing details of the licensing system to the client
13828  */
13829 #define          MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2
13830 /* bitmask of licensed features */
13831 #define       MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4
13832 #define       MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8
13833 #define       MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4
13834 #define       MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8
13835 
13836 
13837 /***********************************/
13838 /* MC_CMD_SET_PORT_SNIFF_CONFIG
13839  * Configure RX port sniffing for the physical port associated with the calling
13840  * function. Only a privileged function may change the port sniffing
13841  * configuration. A copy of all traffic delivered to the host (non-promiscuous
13842  * mode) or all traffic arriving at the port (promiscuous mode) may be
13843  * delivered to a specific queue, or a set of queues with RSS.
13844  */
13845 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7
13846 
13847 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13848 
13849 /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */
13850 #define    MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16
13851 /* configuration flags */
13852 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
13853 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4
13854 #define        MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
13855 #define        MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
13856 #define        MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1
13857 #define        MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1
13858 /* receive queue handle (for RSS mode, this is the base queue) */
13859 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
13860 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4
13861 /* receive mode */
13862 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8
13863 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4
13864 /* enum: receive to just the specified queue */
13865 #define          MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
13866 /* enum: receive to multiple queues using RSS context */
13867 #define          MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
13868 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note
13869  * that these handles should be considered opaque to the host, although a value
13870  * of 0xFFFFFFFF is guaranteed never to be a valid handle.
13871  */
13872 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12
13873 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4
13874 
13875 /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */
13876 #define    MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0
13877 
13878 
13879 /***********************************/
13880 /* MC_CMD_GET_PORT_SNIFF_CONFIG
13881  * Obtain the current RX port sniffing configuration for the physical port
13882  * associated with the calling function. Only a privileged function may read
13883  * the configuration.
13884  */
13885 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8
13886 
13887 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13888 
13889 /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */
13890 #define    MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0
13891 
13892 /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */
13893 #define    MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16
13894 /* configuration flags */
13895 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
13896 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4
13897 #define        MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
13898 #define        MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
13899 #define        MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1
13900 #define        MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1
13901 /* receiving queue handle (for RSS mode, this is the base queue) */
13902 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
13903 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4
13904 /* receive mode */
13905 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8
13906 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4
13907 /* enum: receiving to just the specified queue */
13908 #define          MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
13909 /* enum: receiving to multiple queues using RSS context */
13910 #define          MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
13911 /* RSS context (for RX_MODE_RSS) */
13912 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12
13913 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4
13914 
13915 
13916 /***********************************/
13917 /* MC_CMD_SET_PARSER_DISP_CONFIG
13918  * Change configuration related to the parser-dispatcher subsystem.
13919  */
13920 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9
13921 
13922 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13923 
13924 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */
13925 #define    MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12
13926 #define    MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252
13927 #define    MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))
13928 /* the type of configuration setting to change */
13929 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
13930 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
13931 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible
13932  * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.)
13933  */
13934 #define          MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0
13935 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the
13936  * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single
13937  * boolean.)
13938  */
13939 #define          MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1
13940 /* handle for the entity to update: queue handle, EVB port ID, etc. depending
13941  * on the type of configuration setting being changed
13942  */
13943 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
13944 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
13945 /* new value: the details depend on the type of configuration setting being
13946  * changed
13947  */
13948 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8
13949 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4
13950 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1
13951 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61
13952 
13953 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */
13954 #define    MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0
13955 
13956 
13957 /***********************************/
13958 /* MC_CMD_GET_PARSER_DISP_CONFIG
13959  * Read configuration related to the parser-dispatcher subsystem.
13960  */
13961 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa
13962 
13963 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13964 
13965 /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */
13966 #define    MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8
13967 /* the type of configuration setting to read */
13968 #define       MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
13969 #define       MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
13970 /*            Enum values, see field(s): */
13971 /*               MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */
13972 /* handle for the entity to query: queue handle, EVB port ID, etc. depending on
13973  * the type of configuration setting being read
13974  */
13975 #define       MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
13976 #define       MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
13977 
13978 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */
13979 #define    MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4
13980 #define    MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252
13981 #define    MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num))
13982 /* current value: the details depend on the type of configuration setting being
13983  * read
13984  */
13985 #define       MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0
13986 #define       MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4
13987 #define       MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1
13988 #define       MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63
13989 
13990 
13991 /***********************************/
13992 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG
13993  * Configure TX port sniffing for the physical port associated with the calling
13994  * function. Only a privileged function may change the port sniffing
13995  * configuration. A copy of all traffic transmitted through the port may be
13996  * delivered to a specific queue, or a set of queues with RSS. Note that these
13997  * packets are delivered with transmit timestamps in the packet prefix, not
13998  * receive timestamps, so it is likely that the queue(s) will need to be
13999  * dedicated as TX sniff receivers.
14000  */
14001 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb
14002 
14003 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14004 
14005 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */
14006 #define    MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16
14007 /* configuration flags */
14008 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
14009 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4
14010 #define        MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
14011 #define        MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
14012 /* receive queue handle (for RSS mode, this is the base queue) */
14013 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
14014 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4
14015 /* receive mode */
14016 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8
14017 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4
14018 /* enum: receive to just the specified queue */
14019 #define          MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
14020 /* enum: receive to multiple queues using RSS context */
14021 #define          MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
14022 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note
14023  * that these handles should be considered opaque to the host, although a value
14024  * of 0xFFFFFFFF is guaranteed never to be a valid handle.
14025  */
14026 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12
14027 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4
14028 
14029 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */
14030 #define    MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0
14031 
14032 
14033 /***********************************/
14034 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG
14035  * Obtain the current TX port sniffing configuration for the physical port
14036  * associated with the calling function. Only a privileged function may read
14037  * the configuration.
14038  */
14039 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc
14040 
14041 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14042 
14043 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */
14044 #define    MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0
14045 
14046 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */
14047 #define    MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16
14048 /* configuration flags */
14049 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
14050 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4
14051 #define        MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
14052 #define        MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
14053 /* receiving queue handle (for RSS mode, this is the base queue) */
14054 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
14055 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4
14056 /* receive mode */
14057 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8
14058 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4
14059 /* enum: receiving to just the specified queue */
14060 #define          MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
14061 /* enum: receiving to multiple queues using RSS context */
14062 #define          MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
14063 /* RSS context (for RX_MODE_RSS) */
14064 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12
14065 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4
14066 
14067 
14068 /***********************************/
14069 /* MC_CMD_RMON_STATS_RX_ERRORS
14070  * Per queue rx error stats.
14071  */
14072 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe
14073 
14074 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14075 
14076 /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */
14077 #define    MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8
14078 /* The rx queue to get stats for. */
14079 #define       MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0
14080 #define       MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_LEN 4
14081 #define       MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4
14082 #define       MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_LEN 4
14083 #define        MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0
14084 #define        MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1
14085 
14086 /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */
14087 #define    MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16
14088 #define       MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0
14089 #define       MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_LEN 4
14090 #define       MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4
14091 #define       MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_LEN 4
14092 #define       MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8
14093 #define       MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_LEN 4
14094 #define       MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12
14095 #define       MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_LEN 4
14096 
14097 
14098 /***********************************/
14099 /* MC_CMD_GET_PCIE_RESOURCE_INFO
14100  * Find out about available PCIE resources
14101  */
14102 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd
14103 
14104 #define MC_CMD_0xfd_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14105 
14106 /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */
14107 #define    MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0
14108 
14109 /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */
14110 #define    MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28
14111 /* The maximum number of PFs the device can expose */
14112 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0
14113 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_LEN 4
14114 /* The maximum number of VFs the device can expose in total */
14115 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4
14116 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_LEN 4
14117 /* The maximum number of MSI-X vectors the device can provide in total */
14118 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8
14119 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_LEN 4
14120 /* the number of MSI-X vectors the device will allocate by default to each PF
14121  */
14122 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12
14123 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_LEN 4
14124 /* the number of MSI-X vectors the device will allocate by default to each VF
14125  */
14126 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16
14127 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_LEN 4
14128 /* the maximum number of MSI-X vectors the device can allocate to any one PF */
14129 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20
14130 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_LEN 4
14131 /* the maximum number of MSI-X vectors the device can allocate to any one VF */
14132 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24
14133 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_LEN 4
14134 
14135 
14136 /***********************************/
14137 /* MC_CMD_GET_PORT_MODES
14138  * Find out about available port modes
14139  */
14140 #define MC_CMD_GET_PORT_MODES 0xff
14141 
14142 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14143 
14144 /* MC_CMD_GET_PORT_MODES_IN msgrequest */
14145 #define    MC_CMD_GET_PORT_MODES_IN_LEN 0
14146 
14147 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */
14148 #define    MC_CMD_GET_PORT_MODES_OUT_LEN 12
14149 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */
14150 #define       MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0
14151 #define       MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4
14152 /* Default (canonical) board mode */
14153 #define       MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4
14154 #define       MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 4
14155 /* Current board mode */
14156 #define       MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8
14157 #define       MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4
14158 
14159 
14160 /***********************************/
14161 /* MC_CMD_READ_ATB
14162  * Sample voltages on the ATB
14163  */
14164 #define MC_CMD_READ_ATB 0x100
14165 
14166 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14167 
14168 /* MC_CMD_READ_ATB_IN msgrequest */
14169 #define    MC_CMD_READ_ATB_IN_LEN 16
14170 #define       MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0
14171 #define       MC_CMD_READ_ATB_IN_SIGNAL_BUS_LEN 4
14172 #define          MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */
14173 #define          MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */
14174 #define          MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */
14175 #define       MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4
14176 #define       MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_LEN 4
14177 #define       MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8
14178 #define       MC_CMD_READ_ATB_IN_SIGNAL_SEL_LEN 4
14179 #define       MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12
14180 #define       MC_CMD_READ_ATB_IN_SETTLING_TIME_US_LEN 4
14181 
14182 /* MC_CMD_READ_ATB_OUT msgresponse */
14183 #define    MC_CMD_READ_ATB_OUT_LEN 4
14184 #define       MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0
14185 #define       MC_CMD_READ_ATB_OUT_SAMPLE_MV_LEN 4
14186 
14187 
14188 /***********************************/
14189 /* MC_CMD_GET_WORKAROUNDS
14190  * Read the list of all implemented and all currently enabled workarounds. The
14191  * enums here must correspond with those in MC_CMD_WORKAROUND.
14192  */
14193 #define MC_CMD_GET_WORKAROUNDS 0x59
14194 
14195 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14196 
14197 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */
14198 #define    MC_CMD_GET_WORKAROUNDS_OUT_LEN 8
14199 /* Each workaround is represented by a single bit according to the enums below.
14200  */
14201 #define       MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0
14202 #define       MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4
14203 #define       MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4
14204 #define       MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4
14205 /* enum: Bug 17230 work around. */
14206 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2
14207 /* enum: Bug 35388 work around (unsafe EVQ writes). */
14208 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4
14209 /* enum: Bug35017 workaround (A64 tables must be identity map) */
14210 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8
14211 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
14212 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10
14213 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
14214  * - before adding code that queries this workaround, remember that there's
14215  * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
14216  * and will hence (incorrectly) report that the bug doesn't exist.
14217  */
14218 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20
14219 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */
14220 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40
14221 /* enum: Bug 61265 work around (broken EVQ TMR writes). */
14222 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80
14223 
14224 
14225 /***********************************/
14226 /* MC_CMD_PRIVILEGE_MASK
14227  * Read/set privileges of an arbitrary PCIe function
14228  */
14229 #define MC_CMD_PRIVILEGE_MASK 0x5a
14230 
14231 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14232 
14233 /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */
14234 #define    MC_CMD_PRIVILEGE_MASK_IN_LEN 8
14235 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF
14236  * 1,3 = 0x00030001
14237  */
14238 #define       MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0
14239 #define       MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4
14240 #define        MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0
14241 #define        MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16
14242 #define        MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16
14243 #define        MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16
14244 #define          MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */
14245 /* New privilege mask to be set. The mask will only be changed if the MSB is
14246  * set to 1.
14247  */
14248 #define       MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4
14249 #define       MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4
14250 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */
14251 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */
14252 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */
14253 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */
14254 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */
14255 /* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */
14256 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20
14257 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */
14258 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */
14259 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */
14260 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */
14261 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */
14262 /* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC
14263  * adress.
14264  */
14265 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800
14266 /* enum: Privilege that allows a Function to change the MAC address configured
14267  * in its associated vAdapter/vPort.
14268  */
14269 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000
14270 /* enum: Privilege that allows a Function to install filters that specify VLANs
14271  * that are not in the permit list for the associated vPort. This privilege is
14272  * primarily to support ESX where vPorts are created that restrict traffic to
14273  * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT.
14274  */
14275 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000
14276 /* enum: Privilege for insecure commands. Commands that belong to this group
14277  * are not permitted on secure adapters regardless of the privilege mask.
14278  */
14279 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000
14280 /* enum: Set this bit to indicate that a new privilege mask is to be set,
14281  * otherwise the command will only read the existing mask.
14282  */
14283 #define          MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000
14284 
14285 /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */
14286 #define    MC_CMD_PRIVILEGE_MASK_OUT_LEN 4
14287 /* For an admin function, always all the privileges are reported. */
14288 #define       MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0
14289 #define       MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4
14290 
14291 
14292 /***********************************/
14293 /* MC_CMD_LINK_STATE_MODE
14294  * Read/set link state mode of a VF
14295  */
14296 #define MC_CMD_LINK_STATE_MODE 0x5c
14297 
14298 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14299 
14300 /* MC_CMD_LINK_STATE_MODE_IN msgrequest */
14301 #define    MC_CMD_LINK_STATE_MODE_IN_LEN 8
14302 /* The target function to have its link state mode read or set, must be a VF
14303  * e.g. VF 1,3 = 0x00030001
14304  */
14305 #define       MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0
14306 #define       MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4
14307 #define        MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0
14308 #define        MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16
14309 #define        MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16
14310 #define        MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16
14311 /* New link state mode to be set */
14312 #define       MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4
14313 #define       MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4
14314 #define          MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */
14315 #define          MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */
14316 #define          MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */
14317 /* enum: Use this value to just read the existing setting without modifying it.
14318  */
14319 #define          MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff
14320 
14321 /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */
14322 #define    MC_CMD_LINK_STATE_MODE_OUT_LEN 4
14323 #define       MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0
14324 #define       MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4
14325 
14326 
14327 /***********************************/
14328 /* MC_CMD_GET_SNAPSHOT_LENGTH
14329  * Obtain the current range of allowable values for the SNAPSHOT_LENGTH
14330  * parameter to MC_CMD_INIT_RXQ.
14331  */
14332 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101
14333 
14334 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14335 
14336 /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */
14337 #define    MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0
14338 
14339 /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */
14340 #define    MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8
14341 /* Minimum acceptable snapshot length. */
14342 #define       MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0
14343 #define       MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_LEN 4
14344 /* Maximum acceptable snapshot length. */
14345 #define       MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4
14346 #define       MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_LEN 4
14347 
14348 
14349 /***********************************/
14350 /* MC_CMD_FUSE_DIAGS
14351  * Additional fuse diagnostics
14352  */
14353 #define MC_CMD_FUSE_DIAGS 0x102
14354 
14355 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14356 
14357 /* MC_CMD_FUSE_DIAGS_IN msgrequest */
14358 #define    MC_CMD_FUSE_DIAGS_IN_LEN 0
14359 
14360 /* MC_CMD_FUSE_DIAGS_OUT msgresponse */
14361 #define    MC_CMD_FUSE_DIAGS_OUT_LEN 48
14362 /* Total number of mismatched bits between pairs in area 0 */
14363 #define       MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0
14364 #define       MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 4
14365 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */
14366 #define       MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4
14367 #define       MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 4
14368 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */
14369 #define       MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8
14370 #define       MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 4
14371 /* Checksum of data after logical OR of pairs in area 0 */
14372 #define       MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12
14373 #define       MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 4
14374 /* Total number of mismatched bits between pairs in area 1 */
14375 #define       MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16
14376 #define       MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 4
14377 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */
14378 #define       MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20
14379 #define       MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 4
14380 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */
14381 #define       MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24
14382 #define       MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 4
14383 /* Checksum of data after logical OR of pairs in area 1 */
14384 #define       MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28
14385 #define       MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 4
14386 /* Total number of mismatched bits between pairs in area 2 */
14387 #define       MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32
14388 #define       MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 4
14389 /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */
14390 #define       MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36
14391 #define       MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 4
14392 /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */
14393 #define       MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40
14394 #define       MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 4
14395 /* Checksum of data after logical OR of pairs in area 2 */
14396 #define       MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44
14397 #define       MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4
14398 
14399 
14400 /***********************************/
14401 /* MC_CMD_PRIVILEGE_MODIFY
14402  * Modify the privileges of a set of PCIe functions. Note that this operation
14403  * only effects non-admin functions unless the admin privilege itself is
14404  * included in one of the masks provided.
14405  */
14406 #define MC_CMD_PRIVILEGE_MODIFY 0x60
14407 
14408 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14409 
14410 /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */
14411 #define    MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16
14412 /* The groups of functions to have their privilege masks modified. */
14413 #define       MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0
14414 #define       MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4
14415 #define          MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */
14416 #define          MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */
14417 #define          MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */
14418 #define          MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */
14419 #define          MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */
14420 #define          MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */
14421 /* For VFS_OF_PF specify the PF, for ONE specify the target function */
14422 #define       MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4
14423 #define       MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4
14424 #define        MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0
14425 #define        MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16
14426 #define        MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16
14427 #define        MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16
14428 /* Privileges to be added to the target functions. For privilege definitions
14429  * refer to the command MC_CMD_PRIVILEGE_MASK
14430  */
14431 #define       MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8
14432 #define       MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 4
14433 /* Privileges to be removed from the target functions. For privilege
14434  * definitions refer to the command MC_CMD_PRIVILEGE_MASK
14435  */
14436 #define       MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12
14437 #define       MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 4
14438 
14439 /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */
14440 #define    MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0
14441 
14442 
14443 /***********************************/
14444 /* MC_CMD_XPM_READ_BYTES
14445  * Read XPM memory
14446  */
14447 #define MC_CMD_XPM_READ_BYTES 0x103
14448 
14449 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14450 
14451 /* MC_CMD_XPM_READ_BYTES_IN msgrequest */
14452 #define    MC_CMD_XPM_READ_BYTES_IN_LEN 8
14453 /* Start address (byte) */
14454 #define       MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0
14455 #define       MC_CMD_XPM_READ_BYTES_IN_ADDR_LEN 4
14456 /* Count (bytes) */
14457 #define       MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4
14458 #define       MC_CMD_XPM_READ_BYTES_IN_COUNT_LEN 4
14459 
14460 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */
14461 #define    MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0
14462 #define    MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252
14463 #define    MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num))
14464 /* Data */
14465 #define       MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0
14466 #define       MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1
14467 #define       MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0
14468 #define       MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252
14469 
14470 
14471 /***********************************/
14472 /* MC_CMD_XPM_WRITE_BYTES
14473  * Write XPM memory
14474  */
14475 #define MC_CMD_XPM_WRITE_BYTES 0x104
14476 
14477 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14478 
14479 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */
14480 #define    MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8
14481 #define    MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252
14482 #define    MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num))
14483 /* Start address (byte) */
14484 #define       MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0
14485 #define       MC_CMD_XPM_WRITE_BYTES_IN_ADDR_LEN 4
14486 /* Count (bytes) */
14487 #define       MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4
14488 #define       MC_CMD_XPM_WRITE_BYTES_IN_COUNT_LEN 4
14489 /* Data */
14490 #define       MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8
14491 #define       MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1
14492 #define       MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0
14493 #define       MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244
14494 
14495 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */
14496 #define    MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0
14497 
14498 
14499 /***********************************/
14500 /* MC_CMD_XPM_READ_SECTOR
14501  * Read XPM sector
14502  */
14503 #define MC_CMD_XPM_READ_SECTOR 0x105
14504 
14505 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14506 
14507 /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */
14508 #define    MC_CMD_XPM_READ_SECTOR_IN_LEN 8
14509 /* Sector index */
14510 #define       MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0
14511 #define       MC_CMD_XPM_READ_SECTOR_IN_INDEX_LEN 4
14512 /* Sector size */
14513 #define       MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4
14514 #define       MC_CMD_XPM_READ_SECTOR_IN_SIZE_LEN 4
14515 
14516 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */
14517 #define    MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4
14518 #define    MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36
14519 #define    MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num))
14520 /* Sector type */
14521 #define       MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0
14522 #define       MC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4
14523 #define          MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */
14524 #define          MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */
14525 #define          MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */
14526 #define          MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA 0x3 /* enum */
14527 #define          MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */
14528 /* Sector data */
14529 #define       MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4
14530 #define       MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1
14531 #define       MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0
14532 #define       MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32
14533 
14534 
14535 /***********************************/
14536 /* MC_CMD_XPM_WRITE_SECTOR
14537  * Write XPM sector
14538  */
14539 #define MC_CMD_XPM_WRITE_SECTOR 0x106
14540 
14541 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14542 
14543 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */
14544 #define    MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12
14545 #define    MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44
14546 #define    MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num))
14547 /* If writing fails due to an uncorrectable error, try up to RETRIES following
14548  * sectors (or until no more space available). If 0, only one write attempt is
14549  * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair
14550  * mechanism.
14551  */
14552 #define       MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0
14553 #define       MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1
14554 #define       MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1
14555 #define       MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3
14556 /* Sector type */
14557 #define       MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4
14558 #define       MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_LEN 4
14559 /*            Enum values, see field(s): */
14560 /*               MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */
14561 /* Sector size */
14562 #define       MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8
14563 #define       MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_LEN 4
14564 /* Sector data */
14565 #define       MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12
14566 #define       MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1
14567 #define       MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0
14568 #define       MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32
14569 
14570 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */
14571 #define    MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4
14572 /* New sector index */
14573 #define       MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0
14574 #define       MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_LEN 4
14575 
14576 
14577 /***********************************/
14578 /* MC_CMD_XPM_INVALIDATE_SECTOR
14579  * Invalidate XPM sector
14580  */
14581 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107
14582 
14583 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14584 
14585 /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */
14586 #define    MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4
14587 /* Sector index */
14588 #define       MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0
14589 #define       MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_LEN 4
14590 
14591 /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */
14592 #define    MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0
14593 
14594 
14595 /***********************************/
14596 /* MC_CMD_XPM_BLANK_CHECK
14597  * Blank-check XPM memory and report bad locations
14598  */
14599 #define MC_CMD_XPM_BLANK_CHECK 0x108
14600 
14601 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14602 
14603 /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */
14604 #define    MC_CMD_XPM_BLANK_CHECK_IN_LEN 8
14605 /* Start address (byte) */
14606 #define       MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0
14607 #define       MC_CMD_XPM_BLANK_CHECK_IN_ADDR_LEN 4
14608 /* Count (bytes) */
14609 #define       MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4
14610 #define       MC_CMD_XPM_BLANK_CHECK_IN_COUNT_LEN 4
14611 
14612 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */
14613 #define    MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4
14614 #define    MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252
14615 #define    MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num))
14616 /* Total number of bad (non-blank) locations */
14617 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0
14618 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_LEN 4
14619 /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit
14620  * into MCDI response)
14621  */
14622 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4
14623 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2
14624 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0
14625 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124
14626 
14627 
14628 /***********************************/
14629 /* MC_CMD_XPM_REPAIR
14630  * Blank-check and repair XPM memory
14631  */
14632 #define MC_CMD_XPM_REPAIR 0x109
14633 
14634 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14635 
14636 /* MC_CMD_XPM_REPAIR_IN msgrequest */
14637 #define    MC_CMD_XPM_REPAIR_IN_LEN 8
14638 /* Start address (byte) */
14639 #define       MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0
14640 #define       MC_CMD_XPM_REPAIR_IN_ADDR_LEN 4
14641 /* Count (bytes) */
14642 #define       MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4
14643 #define       MC_CMD_XPM_REPAIR_IN_COUNT_LEN 4
14644 
14645 /* MC_CMD_XPM_REPAIR_OUT msgresponse */
14646 #define    MC_CMD_XPM_REPAIR_OUT_LEN 0
14647 
14648 
14649 /***********************************/
14650 /* MC_CMD_XPM_DECODER_TEST
14651  * Test XPM memory address decoders for gross manufacturing defects. Can only
14652  * be performed on an unprogrammed part.
14653  */
14654 #define MC_CMD_XPM_DECODER_TEST 0x10a
14655 
14656 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14657 
14658 /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */
14659 #define    MC_CMD_XPM_DECODER_TEST_IN_LEN 0
14660 
14661 /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */
14662 #define    MC_CMD_XPM_DECODER_TEST_OUT_LEN 0
14663 
14664 
14665 /***********************************/
14666 /* MC_CMD_XPM_WRITE_TEST
14667  * XPM memory write test. Test XPM write logic for gross manufacturing defects
14668  * by writing to a dedicated test row. There are 16 locations in the test row
14669  * and the test can only be performed on locations that have not been
14670  * previously used (i.e. can be run at most 16 times). The test will pick the
14671  * first available location to use, or fail with ENOSPC if none left.
14672  */
14673 #define MC_CMD_XPM_WRITE_TEST 0x10b
14674 
14675 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14676 
14677 /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */
14678 #define    MC_CMD_XPM_WRITE_TEST_IN_LEN 0
14679 
14680 /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */
14681 #define    MC_CMD_XPM_WRITE_TEST_OUT_LEN 0
14682 
14683 
14684 /***********************************/
14685 /* MC_CMD_EXEC_SIGNED
14686  * Check the CMAC of the contents of IMEM and DMEM against the value supplied
14687  * and if correct begin execution from the start of IMEM. The caller supplies a
14688  * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC
14689  * computation runs from the start of IMEM, and from the start of DMEM + 16k,
14690  * to match flash booting. The command will respond with EINVAL if the CMAC
14691  * does match, otherwise it will respond with success before it jumps to IMEM.
14692  */
14693 #define MC_CMD_EXEC_SIGNED 0x10c
14694 
14695 #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14696 
14697 /* MC_CMD_EXEC_SIGNED_IN msgrequest */
14698 #define    MC_CMD_EXEC_SIGNED_IN_LEN 28
14699 /* the length of code to include in the CMAC */
14700 #define       MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0
14701 #define       MC_CMD_EXEC_SIGNED_IN_CODELEN_LEN 4
14702 /* the length of date to include in the CMAC */
14703 #define       MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4
14704 #define       MC_CMD_EXEC_SIGNED_IN_DATALEN_LEN 4
14705 /* the XPM sector containing the key to use */
14706 #define       MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8
14707 #define       MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_LEN 4
14708 /* the expected CMAC value */
14709 #define       MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12
14710 #define       MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16
14711 
14712 /* MC_CMD_EXEC_SIGNED_OUT msgresponse */
14713 #define    MC_CMD_EXEC_SIGNED_OUT_LEN 0
14714 
14715 
14716 /***********************************/
14717 /* MC_CMD_PREPARE_SIGNED
14718  * Prepare to upload a signed image. This will scrub the specified length of
14719  * the data region, which must be at least as large as the DATALEN supplied to
14720  * MC_CMD_EXEC_SIGNED.
14721  */
14722 #define MC_CMD_PREPARE_SIGNED 0x10d
14723 
14724 #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14725 
14726 /* MC_CMD_PREPARE_SIGNED_IN msgrequest */
14727 #define    MC_CMD_PREPARE_SIGNED_IN_LEN 4
14728 /* the length of data area to clear */
14729 #define       MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0
14730 #define       MC_CMD_PREPARE_SIGNED_IN_DATALEN_LEN 4
14731 
14732 /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */
14733 #define    MC_CMD_PREPARE_SIGNED_OUT_LEN 0
14734 
14735 
14736 /* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */
14737 #define    TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4
14738 /* UDP port (the standard ports are named below but any port may be used) */
14739 #define       TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0
14740 #define       TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2
14741 /* enum: the IANA allocated UDP port for VXLAN */
14742 #define          TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5
14743 /* enum: the IANA allocated UDP port for Geneve */
14744 #define          TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1
14745 #define       TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0
14746 #define       TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16
14747 /* tunnel encapsulation protocol (only those named below are supported) */
14748 #define       TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2
14749 #define       TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2
14750 /* enum: This port will be used for VXLAN on both IPv4 and IPv6 */
14751 #define          TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0
14752 /* enum: This port will be used for Geneve on both IPv4 and IPv6 */
14753 #define          TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1
14754 #define       TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16
14755 #define       TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16
14756 
14757 
14758 /***********************************/
14759 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS
14760  * Configure UDP ports for tunnel encapsulation hardware acceleration. The
14761  * parser-dispatcher will attempt to parse traffic on these ports as tunnel
14762  * encapsulation PDUs and filter them using the tunnel encapsulation filter
14763  * chain rather than the standard filter chain. Note that this command can
14764  * cause all functions to see a reset. (Available on Medford only.)
14765  */
14766 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
14767 
14768 #define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14769 
14770 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */
14771 #define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4
14772 #define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68
14773 #define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))
14774 /* Flags */
14775 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0
14776 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2
14777 #define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0
14778 #define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1
14779 /* The number of entries in the ENTRIES array */
14780 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2
14781 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2
14782 /* Entries defining the UDP port to protocol mapping, each laid out as a
14783  * TUNNEL_ENCAP_UDP_PORT_ENTRY
14784  */
14785 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4
14786 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4
14787 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0
14788 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16
14789 
14790 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */
14791 #define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2
14792 /* Flags */
14793 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0
14794 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2
14795 #define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0
14796 #define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1
14797 
14798 
14799 /***********************************/
14800 /* MC_CMD_RX_BALANCING
14801  * Configure a port upconverter to distribute the packets on both RX engines.
14802  * Packets are distributed based on a table with the destination vFIFO. The
14803  * index of the table is a hash of source and destination of IPV4 and VLAN
14804  * priority.
14805  */
14806 #define MC_CMD_RX_BALANCING 0x118
14807 
14808 #define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14809 
14810 /* MC_CMD_RX_BALANCING_IN msgrequest */
14811 #define    MC_CMD_RX_BALANCING_IN_LEN 16
14812 /* The RX port whose upconverter table will be modified */
14813 #define       MC_CMD_RX_BALANCING_IN_PORT_OFST 0
14814 #define       MC_CMD_RX_BALANCING_IN_PORT_LEN 4
14815 /* The VLAN priority associated to the table index and vFIFO */
14816 #define       MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4
14817 #define       MC_CMD_RX_BALANCING_IN_PRIORITY_LEN 4
14818 /* The resulting bit of SRC^DST for indexing the table */
14819 #define       MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8
14820 #define       MC_CMD_RX_BALANCING_IN_SRC_DST_LEN 4
14821 /* The RX engine to which the vFIFO in the table entry will point to */
14822 #define       MC_CMD_RX_BALANCING_IN_ENG_OFST 12
14823 #define       MC_CMD_RX_BALANCING_IN_ENG_LEN 4
14824 
14825 /* MC_CMD_RX_BALANCING_OUT msgresponse */
14826 #define    MC_CMD_RX_BALANCING_OUT_LEN 0
14827 
14828 
14829 /***********************************/
14830 /* MC_CMD_NVRAM_PRIVATE_APPEND
14831  * Append a single TLV to the MC_USAGE_TLV partition. Returns MC_CMD_ERR_EEXIST
14832  * if the tag is already present.
14833  */
14834 #define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c
14835 
14836 #define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14837 
14838 /* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */
14839 #define    MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9
14840 #define    MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252
14841 #define    MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num))
14842 /* The tag to be appended */
14843 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0
14844 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_LEN 4
14845 /* The length of the data */
14846 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4
14847 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_LEN 4
14848 /* The data to be contained in the TLV structure */
14849 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_OFST 8
14850 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1
14851 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1
14852 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM 244
14853 
14854 /* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */
14855 #define    MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0
14856 
14857 
14858 /***********************************/
14859 /* MC_CMD_XPM_VERIFY_CONTENTS
14860  * Verify that the contents of the XPM memory is correct (Medford only). This
14861  * is used during manufacture to check that the XPM memory has been programmed
14862  * correctly at ATE.
14863  */
14864 #define MC_CMD_XPM_VERIFY_CONTENTS 0x11b
14865 
14866 #define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14867 
14868 /* MC_CMD_XPM_VERIFY_CONTENTS_IN msgrequest */
14869 #define    MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4
14870 /* Data type to be checked */
14871 #define       MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0
14872 #define       MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_LEN 4
14873 
14874 /* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */
14875 #define    MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12
14876 #define    MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252
14877 #define    MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num))
14878 /* Number of sectors found (test builds only) */
14879 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0
14880 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_LEN 4
14881 /* Number of bytes found (test builds only) */
14882 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4
14883 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_LEN 4
14884 /* Length of signature */
14885 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_OFST 8
14886 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_LEN 4
14887 /* Signature */
14888 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_OFST 12
14889 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1
14890 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0
14891 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240
14892 
14893 
14894 /***********************************/
14895 /* MC_CMD_SET_EVQ_TMR
14896  * Update the timer load, timer reload and timer mode values for a given EVQ.
14897  * The requested timer values (in TMR_LOAD_REQ_NS and TMR_RELOAD_REQ_NS) will
14898  * be rounded up to the granularity supported by the hardware, then truncated
14899  * to the range supported by the hardware. The resulting value after the
14900  * rounding and truncation will be returned to the caller (in TMR_LOAD_ACT_NS
14901  * and TMR_RELOAD_ACT_NS).
14902  */
14903 #define MC_CMD_SET_EVQ_TMR 0x120
14904 
14905 #define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14906 
14907 /* MC_CMD_SET_EVQ_TMR_IN msgrequest */
14908 #define    MC_CMD_SET_EVQ_TMR_IN_LEN 16
14909 /* Function-relative queue instance */
14910 #define       MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0
14911 #define       MC_CMD_SET_EVQ_TMR_IN_INSTANCE_LEN 4
14912 /* Requested value for timer load (in nanoseconds) */
14913 #define       MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4
14914 #define       MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_LEN 4
14915 /* Requested value for timer reload (in nanoseconds) */
14916 #define       MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8
14917 #define       MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_LEN 4
14918 /* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */
14919 #define       MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12
14920 #define       MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_LEN 4
14921 #define          MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */
14922 #define          MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */
14923 #define          MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */
14924 #define          MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */
14925 
14926 /* MC_CMD_SET_EVQ_TMR_OUT msgresponse */
14927 #define    MC_CMD_SET_EVQ_TMR_OUT_LEN 8
14928 /* Actual value for timer load (in nanoseconds) */
14929 #define       MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0
14930 #define       MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_LEN 4
14931 /* Actual value for timer reload (in nanoseconds) */
14932 #define       MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4
14933 #define       MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_LEN 4
14934 
14935 
14936 /***********************************/
14937 /* MC_CMD_GET_EVQ_TMR_PROPERTIES
14938  * Query properties about the event queue timers.
14939  */
14940 #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122
14941 
14942 #define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14943 
14944 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_IN msgrequest */
14945 #define    MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0
14946 
14947 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT msgresponse */
14948 #define    MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36
14949 /* Reserved for future use. */
14950 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0
14951 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_LEN 4
14952 /* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in
14953  * nanoseconds) for each increment of the timer load/reload count. The
14954  * requested duration of a timer is this value multiplied by the timer
14955  * load/reload count.
14956  */
14957 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4
14958 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_LEN 4
14959 /* For timers updated via writes to EVQ_TMR_REG, this is the maximum value
14960  * allowed for timer load/reload counts.
14961  */
14962 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8
14963 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_LEN 4
14964 /* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a
14965  * multiple of this step size will be rounded in an implementation defined
14966  * manner.
14967  */
14968 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12
14969 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_LEN 4
14970 /* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only
14971  * meaningful if MC_CMD_SET_EVQ_TMR is implemented.
14972  */
14973 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16
14974 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_LEN 4
14975 /* Timer durations requested via MCDI that are not a multiple of this step size
14976  * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented.
14977  */
14978 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20
14979 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_LEN 4
14980 /* For timers updated using the bug35388 workaround, this is the time interval
14981  * (in nanoseconds) for each increment of the timer load/reload count. The
14982  * requested duration of a timer is this value multiplied by the timer
14983  * load/reload count. This field is only meaningful if the bug35388 workaround
14984  * is enabled.
14985  */
14986 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24
14987 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_LEN 4
14988 /* For timers updated using the bug35388 workaround, this is the maximum value
14989  * allowed for timer load/reload counts. This field is only meaningful if the
14990  * bug35388 workaround is enabled.
14991  */
14992 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28
14993 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_LEN 4
14994 /* For timers updated using the bug35388 workaround, timer load/reload counts
14995  * not a multiple of this step size will be rounded in an implementation
14996  * defined manner. This field is only meaningful if the bug35388 workaround is
14997  * enabled.
14998  */
14999 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32
15000 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4
15001 
15002 
15003 /***********************************/
15004 /* MC_CMD_ALLOCATE_TX_VFIFO_CP
15005  * When we use the TX_vFIFO_ULL mode, we can allocate common pools using the
15006  * non used switch buffers.
15007  */
15008 #define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d
15009 
15010 #define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15011 
15012 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */
15013 #define    MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20
15014 /* Desired instance. Must be set to a specific instance, which is a function
15015  * local queue index.
15016  */
15017 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0
15018 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4
15019 /* Will the common pool be used as TX_vFIFO_ULL (1) */
15020 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4
15021 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_LEN 4
15022 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */
15023 /* enum: Using this interface without TX_vFIFO_ULL is not supported for now */
15024 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0
15025 /* Number of buffers to reserve for the common pool */
15026 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8
15027 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_LEN 4
15028 /* TX datapath to which the Common Pool is connected to. */
15029 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12
15030 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_LEN 4
15031 /* enum: Extracts information from function */
15032 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1
15033 /* Network port or RX Engine to which the common pool connects. */
15034 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16
15035 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_LEN 4
15036 /* enum: Extracts information from function */
15037 /*               MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */
15038 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */
15039 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */
15040 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */
15041 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */
15042 /* enum: To enable Switch loopback with Rx engine 0 */
15043 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4
15044 /* enum: To enable Switch loopback with Rx engine 1 */
15045 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5
15046 
15047 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT msgresponse */
15048 #define    MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4
15049 /* ID of the common pool allocated */
15050 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0
15051 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_LEN 4
15052 
15053 
15054 /***********************************/
15055 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO
15056  * When we use the TX_vFIFO_ULL mode, we can allocate vFIFOs using the
15057  * previously allocated common pools.
15058  */
15059 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e
15060 
15061 #define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15062 
15063 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */
15064 #define    MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20
15065 /* Common pool previously allocated to which the new vFIFO will be associated
15066  */
15067 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0
15068 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_LEN 4
15069 /* Port or RX engine to associate the vFIFO egress */
15070 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4
15071 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_LEN 4
15072 /* enum: Extracts information from common pool */
15073 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1
15074 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */
15075 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */
15076 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */
15077 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */
15078 /* enum: To enable Switch loopback with Rx engine 0 */
15079 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4
15080 /* enum: To enable Switch loopback with Rx engine 1 */
15081 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5
15082 /* Minimum number of buffers that the pool must have */
15083 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8
15084 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_LEN 4
15085 /* enum: Do not check the space available */
15086 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0
15087 /* Will the vFIFO be used as TX_vFIFO_ULL */
15088 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12
15089 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_LEN 4
15090 /* Network priority of the vFIFO,if applicable */
15091 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16
15092 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_LEN 4
15093 /* enum: Search for the lowest unused priority */
15094 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1
15095 
15096 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT msgresponse */
15097 #define    MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8
15098 /* Short vFIFO ID */
15099 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0
15100 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_LEN 4
15101 /* Network priority of the vFIFO */
15102 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4
15103 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_LEN 4
15104 
15105 
15106 /***********************************/
15107 /* MC_CMD_TEARDOWN_TX_VFIFO_VF
15108  * This interface clears the configuration of the given vFIFO and leaves it
15109  * ready to be re-used.
15110  */
15111 #define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f
15112 
15113 #define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15114 
15115 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */
15116 #define    MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4
15117 /* Short vFIFO ID */
15118 #define       MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0
15119 #define       MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_LEN 4
15120 
15121 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */
15122 #define    MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0
15123 
15124 
15125 /***********************************/
15126 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP
15127  * This interface clears the configuration of the given common pool and leaves
15128  * it ready to be re-used.
15129  */
15130 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121
15131 
15132 #define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15133 
15134 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */
15135 #define    MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4
15136 /* Common pool ID given when pool allocated */
15137 #define       MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0
15138 #define       MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_LEN 4
15139 
15140 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */
15141 #define    MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0
15142 
15143 
15144 /***********************************/
15145 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS
15146  * This interface allows the host to find out how many common pool buffers are
15147  * not yet assigned.
15148  */
15149 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124
15150 
15151 #define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15152 
15153 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN msgrequest */
15154 #define    MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0
15155 
15156 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT msgresponse */
15157 #define    MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_LEN 8
15158 /* Available buffers for the ENG to NET vFIFOs. */
15159 #define       MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0
15160 #define       MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_LEN 4
15161 /* Available buffers for the ENG to ENG and NET to ENG vFIFOs. */
15162 #define       MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4
15163 #define       MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_LEN 4
15164 
15165 
15166 #endif /* MCDI_PCOL_H */
15167