1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2009-2013 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 11 #ifndef MCDI_PCOL_H 12 #define MCDI_PCOL_H 13 14 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 15 /* Power-on reset state */ 16 #define MC_FW_STATE_POR (1) 17 /* If this is set in MC_RESET_STATE_REG then it should be 18 * possible to jump into IMEM without loading code from flash. */ 19 #define MC_FW_WARM_BOOT_OK (2) 20 /* The MC main image has started to boot. */ 21 #define MC_FW_STATE_BOOTING (4) 22 /* The Scheduler has started. */ 23 #define MC_FW_STATE_SCHED (8) 24 /* If this is set in MC_RESET_STATE_REG then it should be 25 * possible to jump into IMEM without loading code from flash. 26 * Unlike a warm boot, assume DMEM has been reloaded, so that 27 * the MC persistent data must be reinitialised. */ 28 #define MC_FW_TEPID_BOOT_OK (16) 29 /* We have entered the main firmware via recovery mode. This 30 * means that MC persistent data must be reinitialised, but that 31 * we shouldn't touch PCIe config. */ 32 #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32) 33 /* BIST state has been initialized */ 34 #define MC_FW_BIST_INIT_OK (128) 35 36 /* Siena MC shared memmory offsets */ 37 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 38 #define MC_SMEM_P0_DOORBELL_OFST 0x000 39 #define MC_SMEM_P1_DOORBELL_OFST 0x004 40 /* The rest of these are firmware-defined */ 41 #define MC_SMEM_P0_PDU_OFST 0x008 42 #define MC_SMEM_P1_PDU_OFST 0x108 43 #define MC_SMEM_PDU_LEN 0x100 44 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 45 #define MC_SMEM_P0_STATUS_OFST 0x7f8 46 #define MC_SMEM_P1_STATUS_OFST 0x7fc 47 48 /* Values to be written to the per-port status dword in shared 49 * memory on reboot and assert */ 50 #define MC_STATUS_DWORD_REBOOT (0xb007b007) 51 #define MC_STATUS_DWORD_ASSERT (0xdeaddead) 52 53 /* Check whether an mcfw version (in host order) belongs to a bootloader */ 54 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) 55 56 /* The current version of the MCDI protocol. 57 * 58 * Note that the ROM burnt into the card only talks V0, so at the very 59 * least every driver must support version 0 and MCDI_PCOL_VERSION 60 */ 61 #define MCDI_PCOL_VERSION 2 62 63 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 64 65 /* MCDI version 1 66 * 67 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit 68 * structure, filled in by the client. 69 * 70 * 0 7 8 16 20 22 23 24 31 71 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 72 * | | | 73 * | | \--- Response 74 * | \------- Error 75 * \------------------------------ Resync (always set) 76 * 77 * The client writes it's request into MC shared memory, and rings the 78 * doorbell. Each request is completed by either by the MC writting 79 * back into shared memory, or by writting out an event. 80 * 81 * All MCDI commands support completion by shared memory response. Each 82 * request may also contain additional data (accounted for by HEADER.LEN), 83 * and some response's may also contain additional data (again, accounted 84 * for by HEADER.LEN). 85 * 86 * Some MCDI commands support completion by event, in which any associated 87 * response data is included in the event. 88 * 89 * The protocol requires one response to be delivered for every request, a 90 * request should not be sent unless the response for the previous request 91 * has been received (either by polling shared memory, or by receiving 92 * an event). 93 */ 94 95 /** Request/Response structure */ 96 #define MCDI_HEADER_OFST 0 97 #define MCDI_HEADER_CODE_LBN 0 98 #define MCDI_HEADER_CODE_WIDTH 7 99 #define MCDI_HEADER_RESYNC_LBN 7 100 #define MCDI_HEADER_RESYNC_WIDTH 1 101 #define MCDI_HEADER_DATALEN_LBN 8 102 #define MCDI_HEADER_DATALEN_WIDTH 8 103 #define MCDI_HEADER_SEQ_LBN 16 104 #define MCDI_HEADER_SEQ_WIDTH 4 105 #define MCDI_HEADER_RSVD_LBN 20 106 #define MCDI_HEADER_RSVD_WIDTH 1 107 #define MCDI_HEADER_NOT_EPOCH_LBN 21 108 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 109 #define MCDI_HEADER_ERROR_LBN 22 110 #define MCDI_HEADER_ERROR_WIDTH 1 111 #define MCDI_HEADER_RESPONSE_LBN 23 112 #define MCDI_HEADER_RESPONSE_WIDTH 1 113 #define MCDI_HEADER_XFLAGS_LBN 24 114 #define MCDI_HEADER_XFLAGS_WIDTH 8 115 /* Request response using event */ 116 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 117 118 /* Maximum number of payload bytes */ 119 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc 120 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 121 122 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 123 124 125 /* The MC can generate events for two reasons: 126 * - To complete a shared memory request if XFLAGS_EVREQ was set 127 * - As a notification (link state, i2c event), controlled 128 * via MC_CMD_LOG_CTRL 129 * 130 * Both events share a common structure: 131 * 132 * 0 32 33 36 44 52 60 133 * | Data | Cont | Level | Src | Code | Rsvd | 134 * | 135 * \ There is another event pending in this notification 136 * 137 * If Code==CMDDONE, then the fields are further interpreted as: 138 * 139 * - LEVEL==INFO Command succeeded 140 * - LEVEL==ERR Command failed 141 * 142 * 0 8 16 24 32 143 * | Seq | Datalen | Errno | Rsvd | 144 * 145 * These fields are taken directly out of the standard MCDI header, i.e., 146 * LEVEL==ERR, Datalen == 0 => Reboot 147 * 148 * Events can be squirted out of the UART (using LOG_CTRL) without a 149 * MCDI header. An event can be distinguished from a MCDI response by 150 * examining the first byte which is 0xc0. This corresponds to the 151 * non-existent MCDI command MC_CMD_DEBUG_LOG. 152 * 153 * 0 7 8 154 * | command | Resync | = 0xc0 155 * 156 * Since the event is written in big-endian byte order, this works 157 * providing bits 56-63 of the event are 0xc0. 158 * 159 * 56 60 63 160 * | Rsvd | Code | = 0xc0 161 * 162 * Which means for convenience the event code is 0xc for all MC 163 * generated events. 164 */ 165 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 166 167 168 /* Operation not permitted. */ 169 #define MC_CMD_ERR_EPERM 1 170 /* Non-existent command target */ 171 #define MC_CMD_ERR_ENOENT 2 172 /* assert() has killed the MC */ 173 #define MC_CMD_ERR_EINTR 4 174 /* I/O failure */ 175 #define MC_CMD_ERR_EIO 5 176 /* Already exists */ 177 #define MC_CMD_ERR_EEXIST 6 178 /* Try again */ 179 #define MC_CMD_ERR_EAGAIN 11 180 /* Out of memory */ 181 #define MC_CMD_ERR_ENOMEM 12 182 /* Caller does not hold required locks */ 183 #define MC_CMD_ERR_EACCES 13 184 /* Resource is currently unavailable (e.g. lock contention) */ 185 #define MC_CMD_ERR_EBUSY 16 186 /* No such device */ 187 #define MC_CMD_ERR_ENODEV 19 188 /* Invalid argument to target */ 189 #define MC_CMD_ERR_EINVAL 22 190 /* Broken pipe */ 191 #define MC_CMD_ERR_EPIPE 32 192 /* Read-only */ 193 #define MC_CMD_ERR_EROFS 30 194 /* Out of range */ 195 #define MC_CMD_ERR_ERANGE 34 196 /* Non-recursive resource is already acquired */ 197 #define MC_CMD_ERR_EDEADLK 35 198 /* Operation not implemented */ 199 #define MC_CMD_ERR_ENOSYS 38 200 /* Operation timed out */ 201 #define MC_CMD_ERR_ETIME 62 202 /* Link has been severed */ 203 #define MC_CMD_ERR_ENOLINK 67 204 /* Protocol error */ 205 #define MC_CMD_ERR_EPROTO 71 206 /* Operation not supported */ 207 #define MC_CMD_ERR_ENOTSUP 95 208 /* Address not available */ 209 #define MC_CMD_ERR_EADDRNOTAVAIL 99 210 /* Not connected */ 211 #define MC_CMD_ERR_ENOTCONN 107 212 /* Operation already in progress */ 213 #define MC_CMD_ERR_EALREADY 114 214 215 /* Resource allocation failed. */ 216 #define MC_CMD_ERR_ALLOC_FAIL 0x1000 217 /* V-adaptor not found. */ 218 #define MC_CMD_ERR_NO_VADAPTOR 0x1001 219 /* EVB port not found. */ 220 #define MC_CMD_ERR_NO_EVB_PORT 0x1002 221 /* V-switch not found. */ 222 #define MC_CMD_ERR_NO_VSWITCH 0x1003 223 /* Too many VLAN tags. */ 224 #define MC_CMD_ERR_VLAN_LIMIT 0x1004 225 /* Bad PCI function number. */ 226 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 227 /* Invalid VLAN mode. */ 228 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 229 /* Invalid v-switch type. */ 230 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 231 /* Invalid v-port type. */ 232 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 233 /* MAC address exists. */ 234 #define MC_CMD_ERR_MAC_EXIST 0x1009 235 /* Slave core not present */ 236 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a 237 /* The datapath is disabled. */ 238 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b 239 /* The requesting client is not a function */ 240 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c 241 /* The requested operation might require the 242 command to be passed between MCs, and the 243 transport doesn't support that. Should 244 only ever been seen over the UART. */ 245 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d 246 /* VLAN tag(s) exists */ 247 #define MC_CMD_ERR_VLAN_EXIST 0x100e 248 /* No MAC address assigned to an EVB port */ 249 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f 250 /* Notifies the driver that the request has been relayed 251 * to an admin function for authorization. The driver should 252 * wait for a PROXY_RESPONSE event and then resend its request. 253 * This error code is followed by a 32-bit handle that 254 * helps matching it with the respective PROXY_RESPONSE event. */ 255 #define MC_CMD_ERR_PROXY_PENDING 0x1010 256 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4 257 /* The request cannot be passed for authorization because 258 * another request from the same function is currently being 259 * authorized. The drvier should try again later. */ 260 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011 261 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function 262 * that has enabled proxying or BLOCK_INDEX points to a function that 263 * doesn't await an authorization. */ 264 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012 265 /* This code is currently only used internally in FW. Its meaning is that 266 * an operation failed due to lack of SR-IOV privilege. 267 * Normally it is translated to EPERM by send_cmd_err(), 268 * but it may also be used to trigger some special mechanism 269 * for handling such case, e.g. to relay the failed request 270 * to a designated admin function for authorization. */ 271 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013 272 /* Workaround 26807 could not be turned on/off because some functions 273 * have already installed filters. See the comment at 274 * MC_CMD_WORKAROUND_BUG26807. */ 275 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 276 /* The clock whose frequency you've attempted to set set 277 * doesn't exist on this NIC */ 278 #define MC_CMD_ERR_NO_CLOCK 0x1015 279 280 #define MC_CMD_ERR_CODE_OFST 0 281 282 /* We define 8 "escape" commands to allow 283 for command number space extension */ 284 285 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 286 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 287 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 288 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 289 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 290 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 291 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 292 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 293 294 /* Vectors in the boot ROM */ 295 /* Point to the copycode entry point. */ 296 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) 297 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) 298 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4) 299 /* Points to the recovery mode entry point. */ 300 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) 301 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) 302 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4) 303 304 /* The command set exported by the boot ROM (MCDI v0) */ 305 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 306 (1 << MC_CMD_READ32) | \ 307 (1 << MC_CMD_WRITE32) | \ 308 (1 << MC_CMD_COPYCODE) | \ 309 (1 << MC_CMD_GET_VERSION), \ 310 0, 0, 0 } 311 312 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 313 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 314 315 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 316 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 317 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 318 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 319 320 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 321 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 322 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 323 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 324 325 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 326 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 327 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 328 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 329 330 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default 331 * stack ID (which must be in the range 1-255) along with an EVB port ID. 332 */ 333 #define EVB_STACK_ID(n) (((n) & 0xff) << 16) 334 335 336 /* Version 2 adds an optional argument to error returns: the errno value 337 * may be followed by the (0-based) number of the first argument that 338 * could not be processed. 339 */ 340 #define MC_CMD_ERR_ARG_OFST 4 341 342 /* No space */ 343 #define MC_CMD_ERR_ENOSPC 28 344 345 /* MCDI_EVENT structuredef */ 346 #define MCDI_EVENT_LEN 8 347 #define MCDI_EVENT_CONT_LBN 32 348 #define MCDI_EVENT_CONT_WIDTH 1 349 #define MCDI_EVENT_LEVEL_LBN 33 350 #define MCDI_EVENT_LEVEL_WIDTH 3 351 /* enum: Info. */ 352 #define MCDI_EVENT_LEVEL_INFO 0x0 353 /* enum: Warning. */ 354 #define MCDI_EVENT_LEVEL_WARN 0x1 355 /* enum: Error. */ 356 #define MCDI_EVENT_LEVEL_ERR 0x2 357 /* enum: Fatal. */ 358 #define MCDI_EVENT_LEVEL_FATAL 0x3 359 #define MCDI_EVENT_DATA_OFST 0 360 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 361 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 362 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 363 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 364 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 365 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 366 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 367 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 368 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 369 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 370 /* enum: 100Mbs */ 371 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 372 /* enum: 1Gbs */ 373 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 374 /* enum: 10Gbs */ 375 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 376 /* enum: 40Gbs */ 377 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 378 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 379 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 380 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 381 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 382 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 383 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 384 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 385 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 386 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 387 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 388 #define MCDI_EVENT_FWALERT_DATA_LBN 8 389 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 390 #define MCDI_EVENT_FWALERT_REASON_LBN 0 391 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 392 /* enum: SRAM Access. */ 393 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 394 #define MCDI_EVENT_FLR_VF_LBN 0 395 #define MCDI_EVENT_FLR_VF_WIDTH 8 396 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 397 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 398 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 399 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 400 /* enum: Descriptor loader reported failure */ 401 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 402 /* enum: Descriptor ring empty and no EOP seen for packet */ 403 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 404 /* enum: Overlength packet */ 405 #define MCDI_EVENT_TX_ERR_2BIG 0x3 406 /* enum: Malformed option descriptor */ 407 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 408 /* enum: Option descriptor part way through a packet */ 409 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 410 /* enum: DMA or PIO data access error */ 411 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 412 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 413 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 414 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 415 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 416 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 417 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 418 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 419 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 420 /* enum: PLL lost lock */ 421 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 422 /* enum: Filter overflow (PDMA) */ 423 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 424 /* enum: FIFO overflow (FPGA) */ 425 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 426 /* enum: Merge queue overflow */ 427 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 428 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 429 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 430 /* enum: AOE failed to load - no valid image? */ 431 #define MCDI_EVENT_AOE_NO_LOAD 0x1 432 /* enum: AOE FC reported an exception */ 433 #define MCDI_EVENT_AOE_FC_ASSERT 0x2 434 /* enum: AOE FC watchdogged */ 435 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 436 /* enum: AOE FC failed to start */ 437 #define MCDI_EVENT_AOE_FC_NO_START 0x4 438 /* enum: Generic AOE fault - likely to have been reported via other means too 439 * but intended for use by aoex driver. 440 */ 441 #define MCDI_EVENT_AOE_FAULT 0x5 442 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ 443 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 444 /* enum: AOE loaded successfully */ 445 #define MCDI_EVENT_AOE_LOAD 0x7 446 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ 447 #define MCDI_EVENT_AOE_DMA 0x8 448 /* enum: AOE byteblaster connected/disconnected (Connection status in 449 * AOE_ERR_DATA) 450 */ 451 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 452 /* enum: DDR ECC status update */ 453 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa 454 /* enum: PTP status update */ 455 #define MCDI_EVENT_AOE_PTP_STATUS 0xb 456 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 457 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 458 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 459 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 460 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 461 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 462 #define MCDI_EVENT_RX_ERR_INFO_LBN 16 463 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 464 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 465 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 466 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 467 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 468 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 469 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 470 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0 471 #define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8 472 /* enum: MUM failed to load - no valid image? */ 473 #define MCDI_EVENT_MUM_NO_LOAD 0x1 474 /* enum: MUM f/w reported an exception */ 475 #define MCDI_EVENT_MUM_ASSERT 0x2 476 /* enum: MUM not kicking watchdog */ 477 #define MCDI_EVENT_MUM_WATCHDOG 0x3 478 #define MCDI_EVENT_MUM_ERR_DATA_LBN 8 479 #define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8 480 #define MCDI_EVENT_DATA_LBN 0 481 #define MCDI_EVENT_DATA_WIDTH 32 482 #define MCDI_EVENT_SRC_LBN 36 483 #define MCDI_EVENT_SRC_WIDTH 8 484 #define MCDI_EVENT_EV_CODE_LBN 60 485 #define MCDI_EVENT_EV_CODE_WIDTH 4 486 #define MCDI_EVENT_CODE_LBN 44 487 #define MCDI_EVENT_CODE_WIDTH 8 488 /* enum: Event generated by host software */ 489 #define MCDI_EVENT_SW_EVENT 0x0 490 /* enum: Bad assert. */ 491 #define MCDI_EVENT_CODE_BADSSERT 0x1 492 /* enum: PM Notice. */ 493 #define MCDI_EVENT_CODE_PMNOTICE 0x2 494 /* enum: Command done. */ 495 #define MCDI_EVENT_CODE_CMDDONE 0x3 496 /* enum: Link change. */ 497 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 498 /* enum: Sensor Event. */ 499 #define MCDI_EVENT_CODE_SENSOREVT 0x5 500 /* enum: Schedule error. */ 501 #define MCDI_EVENT_CODE_SCHEDERR 0x6 502 /* enum: Reboot. */ 503 #define MCDI_EVENT_CODE_REBOOT 0x7 504 /* enum: Mac stats DMA. */ 505 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 506 /* enum: Firmware alert. */ 507 #define MCDI_EVENT_CODE_FWALERT 0x9 508 /* enum: Function level reset. */ 509 #define MCDI_EVENT_CODE_FLR 0xa 510 /* enum: Transmit error */ 511 #define MCDI_EVENT_CODE_TX_ERR 0xb 512 /* enum: Tx flush has completed */ 513 #define MCDI_EVENT_CODE_TX_FLUSH 0xc 514 /* enum: PTP packet received timestamp */ 515 #define MCDI_EVENT_CODE_PTP_RX 0xd 516 /* enum: PTP NIC failure */ 517 #define MCDI_EVENT_CODE_PTP_FAULT 0xe 518 /* enum: PTP PPS event */ 519 #define MCDI_EVENT_CODE_PTP_PPS 0xf 520 /* enum: Rx flush has completed */ 521 #define MCDI_EVENT_CODE_RX_FLUSH 0x10 522 /* enum: Receive error */ 523 #define MCDI_EVENT_CODE_RX_ERR 0x11 524 /* enum: AOE fault */ 525 #define MCDI_EVENT_CODE_AOE 0x12 526 /* enum: Network port calibration failed (VCAL). */ 527 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 528 /* enum: HW PPS event */ 529 #define MCDI_EVENT_CODE_HW_PPS 0x14 530 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and 531 * a different format) 532 */ 533 #define MCDI_EVENT_CODE_MC_REBOOT 0x15 534 /* enum: the MC has detected a parity error */ 535 #define MCDI_EVENT_CODE_PAR_ERR 0x16 536 /* enum: the MC has detected a correctable error */ 537 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 538 /* enum: the MC has detected an uncorrectable error */ 539 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 540 /* enum: The MC has entered offline BIST mode */ 541 #define MCDI_EVENT_CODE_MC_BIST 0x19 542 /* enum: PTP tick event providing current NIC time */ 543 #define MCDI_EVENT_CODE_PTP_TIME 0x1a 544 /* enum: MUM fault */ 545 #define MCDI_EVENT_CODE_MUM 0x1b 546 /* enum: notify the designated PF of a new authorization request */ 547 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c 548 /* enum: notify a function that awaits an authorization that its request has 549 * been processed and it may now resend the command 550 */ 551 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d 552 /* enum: Artificial event generated by host and posted via MC for test 553 * purposes. 554 */ 555 #define MCDI_EVENT_CODE_TESTGEN 0xfa 556 #define MCDI_EVENT_CMDDONE_DATA_OFST 0 557 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 558 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 559 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 560 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 561 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 562 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 563 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 564 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 565 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 566 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 567 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 568 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 569 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 570 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 571 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of 572 * timestamp 573 */ 574 #define MCDI_EVENT_PTP_SECONDS_OFST 0 575 #define MCDI_EVENT_PTP_SECONDS_LBN 0 576 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 577 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of 578 * timestamp 579 */ 580 #define MCDI_EVENT_PTP_MAJOR_OFST 0 581 #define MCDI_EVENT_PTP_MAJOR_LBN 0 582 #define MCDI_EVENT_PTP_MAJOR_WIDTH 32 583 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field 584 * of timestamp 585 */ 586 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 587 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 588 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 589 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of 590 * timestamp 591 */ 592 #define MCDI_EVENT_PTP_MINOR_OFST 0 593 #define MCDI_EVENT_PTP_MINOR_LBN 0 594 #define MCDI_EVENT_PTP_MINOR_WIDTH 32 595 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet 596 */ 597 #define MCDI_EVENT_PTP_UUID_OFST 0 598 #define MCDI_EVENT_PTP_UUID_LBN 0 599 #define MCDI_EVENT_PTP_UUID_WIDTH 32 600 #define MCDI_EVENT_RX_ERR_DATA_OFST 0 601 #define MCDI_EVENT_RX_ERR_DATA_LBN 0 602 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 603 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 604 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 605 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 606 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 607 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 608 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 609 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 610 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 611 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 612 /* For CODE_PTP_TIME events, the major value of the PTP clock */ 613 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 614 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 615 #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 616 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ 617 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 618 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 619 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 620 * whether the NIC clock has ever been set 621 */ 622 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36 623 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1 624 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 625 * whether the NIC and System clocks are in sync 626 */ 627 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37 628 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1 629 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of 630 * the minor value of the PTP clock 631 */ 632 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38 633 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6 634 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0 635 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0 636 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32 637 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0 638 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0 639 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32 640 /* Zero means that the request has been completed or authorized, and the driver 641 * should resend it. A non-zero value means that the authorization has been 642 * denied, and gives the reason. Typically it will be EPERM. 643 */ 644 #define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36 645 #define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8 646 647 /* FCDI_EVENT structuredef */ 648 #define FCDI_EVENT_LEN 8 649 #define FCDI_EVENT_CONT_LBN 32 650 #define FCDI_EVENT_CONT_WIDTH 1 651 #define FCDI_EVENT_LEVEL_LBN 33 652 #define FCDI_EVENT_LEVEL_WIDTH 3 653 /* enum: Info. */ 654 #define FCDI_EVENT_LEVEL_INFO 0x0 655 /* enum: Warning. */ 656 #define FCDI_EVENT_LEVEL_WARN 0x1 657 /* enum: Error. */ 658 #define FCDI_EVENT_LEVEL_ERR 0x2 659 /* enum: Fatal. */ 660 #define FCDI_EVENT_LEVEL_FATAL 0x3 661 #define FCDI_EVENT_DATA_OFST 0 662 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 663 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 664 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ 665 #define FCDI_EVENT_LINK_UP 0x1 /* enum */ 666 #define FCDI_EVENT_DATA_LBN 0 667 #define FCDI_EVENT_DATA_WIDTH 32 668 #define FCDI_EVENT_SRC_LBN 36 669 #define FCDI_EVENT_SRC_WIDTH 8 670 #define FCDI_EVENT_EV_CODE_LBN 60 671 #define FCDI_EVENT_EV_CODE_WIDTH 4 672 #define FCDI_EVENT_CODE_LBN 44 673 #define FCDI_EVENT_CODE_WIDTH 8 674 /* enum: The FC was rebooted. */ 675 #define FCDI_EVENT_CODE_REBOOT 0x1 676 /* enum: Bad assert. */ 677 #define FCDI_EVENT_CODE_ASSERT 0x2 678 /* enum: DDR3 test result. */ 679 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 680 /* enum: Link status. */ 681 #define FCDI_EVENT_CODE_LINK_STATE 0x4 682 /* enum: A timed read is ready to be serviced. */ 683 #define FCDI_EVENT_CODE_TIMED_READ 0x5 684 /* enum: One or more PPS IN events */ 685 #define FCDI_EVENT_CODE_PPS_IN 0x6 686 /* enum: Tick event from PTP clock */ 687 #define FCDI_EVENT_CODE_PTP_TICK 0x7 688 /* enum: ECC error counters */ 689 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 690 /* enum: Current status of PTP */ 691 #define FCDI_EVENT_CODE_PTP_STATUS 0x9 692 /* enum: Port id config to map MC-FC port idx */ 693 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa 694 /* enum: Boot result or error code */ 695 #define FCDI_EVENT_CODE_BOOT_RESULT 0xb 696 #define FCDI_EVENT_REBOOT_SRC_LBN 36 697 #define FCDI_EVENT_REBOOT_SRC_WIDTH 8 698 #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */ 699 #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */ 700 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 701 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 702 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 703 #define FCDI_EVENT_ASSERT_TYPE_LBN 36 704 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 705 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 706 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 707 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 708 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 709 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 710 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 711 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 712 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 713 #define FCDI_EVENT_PTP_STATE_OFST 0 714 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ 715 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ 716 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ 717 #define FCDI_EVENT_PTP_STATE_LBN 0 718 #define FCDI_EVENT_PTP_STATE_WIDTH 32 719 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 720 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 721 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 722 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 723 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 724 /* Index of MC port being referred to */ 725 #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 726 #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 727 /* FC Port index that matches the MC port index in SRC */ 728 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 729 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 730 #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 731 #define FCDI_EVENT_BOOT_RESULT_OFST 0 732 /* Enum values, see field(s): */ 733 /* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */ 734 #define FCDI_EVENT_BOOT_RESULT_LBN 0 735 #define FCDI_EVENT_BOOT_RESULT_WIDTH 32 736 737 /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events 738 * to the MC. Note that this structure | is overlayed over a normal FCDI event 739 * such that bits 32-63 containing | event code, level, source etc remain the 740 * same. In this case the data | field of the header is defined to be the 741 * number of timestamps 742 */ 743 #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 744 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 745 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) 746 /* Number of timestamps following */ 747 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 748 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 749 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 750 /* Seconds field of a timestamp record */ 751 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 752 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 753 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 754 /* Nanoseconds field of a timestamp record */ 755 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 756 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 757 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 758 /* Timestamp records comprising the event */ 759 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 760 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 761 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 762 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 763 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 764 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 765 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 766 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 767 768 /* MUM_EVENT structuredef */ 769 #define MUM_EVENT_LEN 8 770 #define MUM_EVENT_CONT_LBN 32 771 #define MUM_EVENT_CONT_WIDTH 1 772 #define MUM_EVENT_LEVEL_LBN 33 773 #define MUM_EVENT_LEVEL_WIDTH 3 774 /* enum: Info. */ 775 #define MUM_EVENT_LEVEL_INFO 0x0 776 /* enum: Warning. */ 777 #define MUM_EVENT_LEVEL_WARN 0x1 778 /* enum: Error. */ 779 #define MUM_EVENT_LEVEL_ERR 0x2 780 /* enum: Fatal. */ 781 #define MUM_EVENT_LEVEL_FATAL 0x3 782 #define MUM_EVENT_DATA_OFST 0 783 #define MUM_EVENT_SENSOR_ID_LBN 0 784 #define MUM_EVENT_SENSOR_ID_WIDTH 8 785 /* Enum values, see field(s): */ 786 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 787 #define MUM_EVENT_SENSOR_STATE_LBN 8 788 #define MUM_EVENT_SENSOR_STATE_WIDTH 8 789 #define MUM_EVENT_PORT_PHY_READY_LBN 0 790 #define MUM_EVENT_PORT_PHY_READY_WIDTH 1 791 #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1 792 #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1 793 #define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2 794 #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1 795 #define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3 796 #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1 797 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4 798 #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1 799 #define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5 800 #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1 801 #define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6 802 #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1 803 #define MUM_EVENT_DATA_LBN 0 804 #define MUM_EVENT_DATA_WIDTH 32 805 #define MUM_EVENT_SRC_LBN 36 806 #define MUM_EVENT_SRC_WIDTH 8 807 #define MUM_EVENT_EV_CODE_LBN 60 808 #define MUM_EVENT_EV_CODE_WIDTH 4 809 #define MUM_EVENT_CODE_LBN 44 810 #define MUM_EVENT_CODE_WIDTH 8 811 /* enum: The MUM was rebooted. */ 812 #define MUM_EVENT_CODE_REBOOT 0x1 813 /* enum: Bad assert. */ 814 #define MUM_EVENT_CODE_ASSERT 0x2 815 /* enum: Sensor failure. */ 816 #define MUM_EVENT_CODE_SENSOR 0x3 817 /* enum: Link fault has been asserted, or has cleared. */ 818 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4 819 #define MUM_EVENT_SENSOR_DATA_OFST 0 820 #define MUM_EVENT_SENSOR_DATA_LBN 0 821 #define MUM_EVENT_SENSOR_DATA_WIDTH 32 822 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0 823 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0 824 #define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32 825 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0 826 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0 827 #define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32 828 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0 829 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0 830 #define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32 831 #define MUM_EVENT_PORT_PHY_TECH_OFST 0 832 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */ 833 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */ 834 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */ 835 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */ 836 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */ 837 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */ 838 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */ 839 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */ 840 #define MUM_EVENT_PORT_PHY_TECH_LBN 0 841 #define MUM_EVENT_PORT_PHY_TECH_WIDTH 32 842 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36 843 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4 844 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */ 845 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */ 846 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */ 847 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */ 848 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */ 849 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 850 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 851 852 853 /***********************************/ 854 /* MC_CMD_READ32 855 * Read multiple 32byte words from MC memory. 856 */ 857 #define MC_CMD_READ32 0x1 858 859 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 860 861 /* MC_CMD_READ32_IN msgrequest */ 862 #define MC_CMD_READ32_IN_LEN 8 863 #define MC_CMD_READ32_IN_ADDR_OFST 0 864 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 865 866 /* MC_CMD_READ32_OUT msgresponse */ 867 #define MC_CMD_READ32_OUT_LENMIN 4 868 #define MC_CMD_READ32_OUT_LENMAX 252 869 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 870 #define MC_CMD_READ32_OUT_BUFFER_OFST 0 871 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 872 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 873 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 874 875 876 /***********************************/ 877 /* MC_CMD_WRITE32 878 * Write multiple 32byte words to MC memory. 879 */ 880 #define MC_CMD_WRITE32 0x2 881 882 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 883 884 /* MC_CMD_WRITE32_IN msgrequest */ 885 #define MC_CMD_WRITE32_IN_LENMIN 8 886 #define MC_CMD_WRITE32_IN_LENMAX 252 887 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 888 #define MC_CMD_WRITE32_IN_ADDR_OFST 0 889 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 890 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 891 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 892 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 893 894 /* MC_CMD_WRITE32_OUT msgresponse */ 895 #define MC_CMD_WRITE32_OUT_LEN 0 896 897 898 /***********************************/ 899 /* MC_CMD_COPYCODE 900 * Copy MC code between two locations and jump. 901 */ 902 #define MC_CMD_COPYCODE 0x3 903 904 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN 905 906 /* MC_CMD_COPYCODE_IN msgrequest */ 907 #define MC_CMD_COPYCODE_IN_LEN 16 908 /* Source address 909 * 910 * The main image should be entered via a copy of a single word from and to a 911 * magic address, which controls various aspects of the boot. The magic address 912 * is a bitfield, with each bit as documented below. 913 */ 914 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 915 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ 916 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 917 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and 918 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below) 919 */ 920 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 921 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, 922 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see 923 * below) 924 */ 925 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc 926 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 927 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 928 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 929 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 930 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 931 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 932 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 933 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 934 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 935 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 936 /* Destination address */ 937 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 938 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 939 /* Address of where to jump after copy. */ 940 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 941 /* enum: Control should return to the caller rather than jumping */ 942 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 943 944 /* MC_CMD_COPYCODE_OUT msgresponse */ 945 #define MC_CMD_COPYCODE_OUT_LEN 0 946 947 948 /***********************************/ 949 /* MC_CMD_SET_FUNC 950 * Select function for function-specific commands. 951 */ 952 #define MC_CMD_SET_FUNC 0x4 953 954 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 955 956 /* MC_CMD_SET_FUNC_IN msgrequest */ 957 #define MC_CMD_SET_FUNC_IN_LEN 4 958 /* Set function */ 959 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 960 961 /* MC_CMD_SET_FUNC_OUT msgresponse */ 962 #define MC_CMD_SET_FUNC_OUT_LEN 0 963 964 965 /***********************************/ 966 /* MC_CMD_GET_BOOT_STATUS 967 * Get the instruction address from which the MC booted. 968 */ 969 #define MC_CMD_GET_BOOT_STATUS 0x5 970 971 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 972 973 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 974 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 975 976 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 977 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 978 /* ?? */ 979 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 980 /* enum: indicates that the MC wasn't flash booted */ 981 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef 982 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 983 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 984 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 985 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 986 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 987 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 988 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 989 990 991 /***********************************/ 992 /* MC_CMD_GET_ASSERTS 993 * Get (and optionally clear) the current assertion status. Only 994 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other 995 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS 996 */ 997 #define MC_CMD_GET_ASSERTS 0x6 998 999 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1000 1001 /* MC_CMD_GET_ASSERTS_IN msgrequest */ 1002 #define MC_CMD_GET_ASSERTS_IN_LEN 4 1003 /* Set to clear assertion */ 1004 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 1005 1006 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ 1007 #define MC_CMD_GET_ASSERTS_OUT_LEN 140 1008 /* Assertion status flag. */ 1009 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 1010 /* enum: No assertions have failed. */ 1011 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 1012 /* enum: A system-level assertion has failed. */ 1013 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 1014 /* enum: A thread-level assertion has failed. */ 1015 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 1016 /* enum: The system was reset by the watchdog. */ 1017 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 1018 /* enum: An illegal address trap stopped the system (huntington and later) */ 1019 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 1020 /* Failing PC value */ 1021 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 1022 /* Saved GP regs */ 1023 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 1024 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 1025 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 1026 /* enum: A magic value hinting that the value in this register at the time of 1027 * the failure has likely been lost. 1028 */ 1029 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 1030 /* Failing thread address */ 1031 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 1032 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 1033 1034 1035 /***********************************/ 1036 /* MC_CMD_LOG_CTRL 1037 * Configure the output stream for log events such as link state changes, 1038 * sensor notifications and MCDI completions 1039 */ 1040 #define MC_CMD_LOG_CTRL 0x7 1041 1042 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1043 1044 /* MC_CMD_LOG_CTRL_IN msgrequest */ 1045 #define MC_CMD_LOG_CTRL_IN_LEN 8 1046 /* Log destination */ 1047 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 1048 /* enum: UART. */ 1049 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 1050 /* enum: Event queue. */ 1051 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 1052 /* Legacy argument. Must be zero. */ 1053 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 1054 1055 /* MC_CMD_LOG_CTRL_OUT msgresponse */ 1056 #define MC_CMD_LOG_CTRL_OUT_LEN 0 1057 1058 1059 /***********************************/ 1060 /* MC_CMD_GET_VERSION 1061 * Get version information about the MC firmware. 1062 */ 1063 #define MC_CMD_GET_VERSION 0x8 1064 1065 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1066 1067 /* MC_CMD_GET_VERSION_IN msgrequest */ 1068 #define MC_CMD_GET_VERSION_IN_LEN 0 1069 1070 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ 1071 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 1072 /* placeholder, set to 0 */ 1073 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 1074 1075 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ 1076 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 1077 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 1078 /* enum: Reserved version number to indicate "any" version. */ 1079 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff 1080 /* enum: Bootrom version value for Siena. */ 1081 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 1082 /* enum: Bootrom version value for Huntington. */ 1083 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 1084 1085 /* MC_CMD_GET_VERSION_OUT msgresponse */ 1086 #define MC_CMD_GET_VERSION_OUT_LEN 32 1087 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1088 /* Enum values, see field(s): */ 1089 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1090 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 1091 /* 128bit mask of functions supported by the current firmware */ 1092 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 1093 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 1094 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 1095 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 1096 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 1097 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 1098 1099 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ 1100 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 1101 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1102 /* Enum values, see field(s): */ 1103 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1104 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 1105 /* 128bit mask of functions supported by the current firmware */ 1106 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 1107 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 1108 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 1109 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 1110 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 1111 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 1112 /* extra info */ 1113 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 1114 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 1115 1116 1117 /***********************************/ 1118 /* MC_CMD_PTP 1119 * Perform PTP operation 1120 */ 1121 #define MC_CMD_PTP 0xb 1122 1123 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1124 1125 /* MC_CMD_PTP_IN msgrequest */ 1126 #define MC_CMD_PTP_IN_LEN 1 1127 /* PTP operation code */ 1128 #define MC_CMD_PTP_IN_OP_OFST 0 1129 #define MC_CMD_PTP_IN_OP_LEN 1 1130 /* enum: Enable PTP packet timestamping operation. */ 1131 #define MC_CMD_PTP_OP_ENABLE 0x1 1132 /* enum: Disable PTP packet timestamping operation. */ 1133 #define MC_CMD_PTP_OP_DISABLE 0x2 1134 /* enum: Send a PTP packet. */ 1135 #define MC_CMD_PTP_OP_TRANSMIT 0x3 1136 /* enum: Read the current NIC time. */ 1137 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 1138 /* enum: Get the current PTP status. */ 1139 #define MC_CMD_PTP_OP_STATUS 0x5 1140 /* enum: Adjust the PTP NIC's time. */ 1141 #define MC_CMD_PTP_OP_ADJUST 0x6 1142 /* enum: Synchronize host and NIC time. */ 1143 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 1144 /* enum: Basic manufacturing tests. */ 1145 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 1146 /* enum: Packet based manufacturing tests. */ 1147 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 1148 /* enum: Reset some of the PTP related statistics */ 1149 #define MC_CMD_PTP_OP_RESET_STATS 0xa 1150 /* enum: Debug operations to MC. */ 1151 #define MC_CMD_PTP_OP_DEBUG 0xb 1152 /* enum: Read an FPGA register */ 1153 #define MC_CMD_PTP_OP_FPGAREAD 0xc 1154 /* enum: Write an FPGA register */ 1155 #define MC_CMD_PTP_OP_FPGAWRITE 0xd 1156 /* enum: Apply an offset to the NIC clock */ 1157 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe 1158 /* enum: Change Apply an offset to the NIC clock */ 1159 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf 1160 /* enum: Set the MC packet filter VLAN tags for received PTP packets */ 1161 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 1162 /* enum: Set the MC packet filter UUID for received PTP packets */ 1163 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 1164 /* enum: Set the MC packet filter Domain for received PTP packets */ 1165 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 1166 /* enum: Set the clock source */ 1167 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 1168 /* enum: Reset value of Timer Reg. */ 1169 #define MC_CMD_PTP_OP_RST_CLK 0x14 1170 /* enum: Enable the forwarding of PPS events to the host */ 1171 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 1172 /* enum: Get the time format used by this NIC for PTP operations */ 1173 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 1174 /* enum: Get the clock attributes. NOTE- extended version of 1175 * MC_CMD_PTP_OP_GET_TIME_FORMAT 1176 */ 1177 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 1178 /* enum: Get corrections that should be applied to the various different 1179 * timestamps 1180 */ 1181 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 1182 /* enum: Subscribe to receive periodic time events indicating the current NIC 1183 * time 1184 */ 1185 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 1186 /* enum: Unsubscribe to stop receiving time events */ 1187 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 1188 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS 1189 * input on the same NIC. 1190 */ 1191 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a 1192 /* enum: Set the PTP sync status. Status is used by firmware to report to event 1193 * subscribers. 1194 */ 1195 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b 1196 /* enum: Above this for future use. */ 1197 #define MC_CMD_PTP_OP_MAX 0x1c 1198 1199 /* MC_CMD_PTP_IN_ENABLE msgrequest */ 1200 #define MC_CMD_PTP_IN_ENABLE_LEN 16 1201 #define MC_CMD_PTP_IN_CMD_OFST 0 1202 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 1203 /* Event queue for PTP events */ 1204 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 1205 /* PTP timestamping mode */ 1206 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 1207 /* enum: PTP, version 1 */ 1208 #define MC_CMD_PTP_MODE_V1 0x0 1209 /* enum: PTP, version 1, with VLAN headers - deprecated */ 1210 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 1211 /* enum: PTP, version 2 */ 1212 #define MC_CMD_PTP_MODE_V2 0x2 1213 /* enum: PTP, version 2, with VLAN headers - deprecated */ 1214 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 1215 /* enum: PTP, version 2, with improved UUID filtering */ 1216 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 1217 /* enum: FCoE (seconds and microseconds) */ 1218 #define MC_CMD_PTP_MODE_FCOE 0x5 1219 1220 /* MC_CMD_PTP_IN_DISABLE msgrequest */ 1221 #define MC_CMD_PTP_IN_DISABLE_LEN 8 1222 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1223 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1224 1225 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 1226 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 1227 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 1228 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 1229 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1230 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1231 /* Transmit packet length */ 1232 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 1233 /* Transmit packet data */ 1234 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 1235 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 1236 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 1237 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 1238 1239 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 1240 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 1241 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1242 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1243 1244 /* MC_CMD_PTP_IN_STATUS msgrequest */ 1245 #define MC_CMD_PTP_IN_STATUS_LEN 8 1246 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1247 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1248 1249 /* MC_CMD_PTP_IN_ADJUST msgrequest */ 1250 #define MC_CMD_PTP_IN_ADJUST_LEN 24 1251 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1252 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1253 /* Frequency adjustment 40 bit fixed point ns */ 1254 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 1255 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 1256 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 1257 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 1258 /* enum: Number of fractional bits in frequency adjustment */ 1259 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 1260 /* Time adjustment in seconds */ 1261 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 1262 /* Time adjustment major value */ 1263 #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 1264 /* Time adjustment in nanoseconds */ 1265 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 1266 /* Time adjustment minor value */ 1267 #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 1268 1269 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 1270 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 1271 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1272 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1273 /* Number of time readings to capture */ 1274 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 1275 /* Host address in which to write "synchronization started" indication (64 1276 * bits) 1277 */ 1278 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 1279 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 1280 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 1281 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 1282 1283 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 1284 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 1285 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1286 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1287 1288 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 1289 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 1290 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1291 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1292 /* Enable or disable packet testing */ 1293 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 1294 1295 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ 1296 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 1297 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1298 /* Reset PTP statistics */ 1299 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1300 1301 /* MC_CMD_PTP_IN_DEBUG msgrequest */ 1302 #define MC_CMD_PTP_IN_DEBUG_LEN 12 1303 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1304 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1305 /* Debug operations */ 1306 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 1307 1308 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ 1309 #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 1310 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1311 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1312 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 1313 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 1314 1315 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ 1316 #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 1317 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 1318 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) 1319 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1320 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1321 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 1322 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 1323 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 1324 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 1325 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 1326 1327 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ 1328 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 1329 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1330 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1331 /* Time adjustment in seconds */ 1332 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 1333 /* Time adjustment major value */ 1334 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 1335 /* Time adjustment in nanoseconds */ 1336 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 1337 /* Time adjustment minor value */ 1338 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 1339 1340 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ 1341 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 1342 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1343 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1344 /* Frequency adjustment 40 bit fixed point ns */ 1345 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 1346 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 1347 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 1348 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 1349 /* enum: Number of fractional bits in frequency adjustment */ 1350 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ 1351 1352 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ 1353 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 1354 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1355 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1356 /* Number of VLAN tags, 0 if not VLAN */ 1357 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 1358 /* Set of VLAN tags to filter against */ 1359 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 1360 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 1361 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 1362 1363 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ 1364 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 1365 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1366 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1367 /* 1 to enable UUID filtering, 0 to disable */ 1368 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 1369 /* UUID to filter against */ 1370 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 1371 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 1372 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 1373 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 1374 1375 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ 1376 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 1377 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1378 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1379 /* 1 to enable Domain filtering, 0 to disable */ 1380 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 1381 /* Domain number to filter against */ 1382 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 1383 1384 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ 1385 #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 1386 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1387 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1388 /* Set the clock source. */ 1389 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 1390 /* enum: Internal. */ 1391 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 1392 /* enum: External. */ 1393 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 1394 1395 /* MC_CMD_PTP_IN_RST_CLK msgrequest */ 1396 #define MC_CMD_PTP_IN_RST_CLK_LEN 8 1397 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1398 /* Reset value of Timer Reg. */ 1399 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1400 1401 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ 1402 #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 1403 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1404 /* Enable or disable */ 1405 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 1406 /* enum: Enable */ 1407 #define MC_CMD_PTP_ENABLE_PPS 0x0 1408 /* enum: Disable */ 1409 #define MC_CMD_PTP_DISABLE_PPS 0x1 1410 /* Queue id to send events back */ 1411 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 1412 1413 /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ 1414 #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 1415 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1416 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1417 1418 /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ 1419 #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 1420 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1421 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1422 1423 /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ 1424 #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 1425 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1426 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1427 1428 /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ 1429 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 1430 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1431 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1432 /* Original field containing queue ID. Now extended to include flags. */ 1433 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 1434 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0 1435 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16 1436 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31 1437 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1 1438 1439 /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ 1440 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 1441 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1442 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1443 /* Unsubscribe options */ 1444 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 1445 /* enum: Unsubscribe a single queue */ 1446 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 1447 /* enum: Unsubscribe all queues */ 1448 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 1449 /* Event queue ID */ 1450 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 1451 1452 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ 1453 #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 1454 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1455 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1456 /* 1 to enable PPS test mode, 0 to disable and return result. */ 1457 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 1458 1459 /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */ 1460 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24 1461 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1462 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1463 /* NIC - Host System Clock Synchronization status */ 1464 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8 1465 /* enum: Host System clock and NIC clock are not in sync */ 1466 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0 1467 /* enum: Host System clock and NIC clock are synchronized */ 1468 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1 1469 /* If synchronized, number of seconds until clocks should be considered to be 1470 * no longer in sync. 1471 */ 1472 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12 1473 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16 1474 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 1475 1476 /* MC_CMD_PTP_OUT msgresponse */ 1477 #define MC_CMD_PTP_OUT_LEN 0 1478 1479 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 1480 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 1481 /* Value of seconds timestamp */ 1482 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 1483 /* Timestamp major value */ 1484 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 1485 /* Value of nanoseconds timestamp */ 1486 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 1487 /* Timestamp minor value */ 1488 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 1489 1490 /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ 1491 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 1492 1493 /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ 1494 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 1495 1496 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 1497 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 1498 /* Value of seconds timestamp */ 1499 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 1500 /* Timestamp major value */ 1501 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 1502 /* Value of nanoseconds timestamp */ 1503 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 1504 /* Timestamp minor value */ 1505 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 1506 1507 /* MC_CMD_PTP_OUT_STATUS msgresponse */ 1508 #define MC_CMD_PTP_OUT_STATUS_LEN 64 1509 /* Frequency of NIC's hardware clock */ 1510 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 1511 /* Number of packets transmitted and timestamped */ 1512 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 1513 /* Number of packets received and timestamped */ 1514 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 1515 /* Number of packets timestamped by the FPGA */ 1516 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 1517 /* Number of packets filter matched */ 1518 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 1519 /* Number of packets not filter matched */ 1520 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 1521 /* Number of PPS overflows (noise on input?) */ 1522 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 1523 /* Number of PPS bad periods */ 1524 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 1525 /* Minimum period of PPS pulse in nanoseconds */ 1526 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 1527 /* Maximum period of PPS pulse in nanoseconds */ 1528 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 1529 /* Last period of PPS pulse in nanoseconds */ 1530 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 1531 /* Mean period of PPS pulse in nanoseconds */ 1532 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 1533 /* Minimum offset of PPS pulse in nanoseconds (signed) */ 1534 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 1535 /* Maximum offset of PPS pulse in nanoseconds (signed) */ 1536 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 1537 /* Last offset of PPS pulse in nanoseconds (signed) */ 1538 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 1539 /* Mean offset of PPS pulse in nanoseconds (signed) */ 1540 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 1541 1542 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 1543 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 1544 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 1545 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 1546 /* A set of host and NIC times */ 1547 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 1548 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 1549 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 1550 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 1551 /* Host time immediately before NIC's hardware clock read */ 1552 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 1553 /* Value of seconds timestamp */ 1554 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 1555 /* Timestamp major value */ 1556 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 1557 /* Value of nanoseconds timestamp */ 1558 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 1559 /* Timestamp minor value */ 1560 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 1561 /* Host time immediately after NIC's hardware clock read */ 1562 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 1563 /* Number of nanoseconds waited after reading NIC's hardware clock */ 1564 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 1565 1566 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 1567 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 1568 /* Results of testing */ 1569 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 1570 /* enum: Successful test */ 1571 #define MC_CMD_PTP_MANF_SUCCESS 0x0 1572 /* enum: FPGA load failed */ 1573 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 1574 /* enum: FPGA version invalid */ 1575 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 1576 /* enum: FPGA registers incorrect */ 1577 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 1578 /* enum: Oscillator possibly not working? */ 1579 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 1580 /* enum: Timestamps not increasing */ 1581 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 1582 /* enum: Mismatched packet count */ 1583 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 1584 /* enum: Mismatched packet count (Siena filter and FPGA) */ 1585 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 1586 /* enum: Not enough packets to perform timestamp check */ 1587 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 1588 /* enum: Timestamp trigger GPIO not working */ 1589 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 1590 /* enum: Insufficient PPS events to perform checks */ 1591 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa 1592 /* enum: PPS time event period not sufficiently close to 1s. */ 1593 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb 1594 /* enum: PPS time event nS reading not sufficiently close to zero. */ 1595 #define MC_CMD_PTP_MANF_PPS_NS 0xc 1596 /* enum: PTP peripheral registers incorrect */ 1597 #define MC_CMD_PTP_MANF_REGISTERS 0xd 1598 /* enum: Failed to read time from PTP peripheral */ 1599 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe 1600 /* Presence of external oscillator */ 1601 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 1602 1603 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 1604 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 1605 /* Results of testing */ 1606 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 1607 /* Number of packets received by FPGA */ 1608 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 1609 /* Number of packets received by Siena filters */ 1610 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 1611 1612 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ 1613 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 1614 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 1615 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) 1616 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 1617 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 1618 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 1619 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 1620 1621 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ 1622 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 1623 /* Time format required/used by for this NIC. Applies to all PTP MCDI 1624 * operations that pass times between the host and firmware. If this operation 1625 * is not supported (older firmware) a format of seconds and nanoseconds should 1626 * be assumed. 1627 */ 1628 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 1629 /* enum: Times are in seconds and nanoseconds */ 1630 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 1631 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 1632 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 1633 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 1634 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 1635 1636 /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ 1637 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24 1638 /* Time format required/used by for this NIC. Applies to all PTP MCDI 1639 * operations that pass times between the host and firmware. If this operation 1640 * is not supported (older firmware) a format of seconds and nanoseconds should 1641 * be assumed. 1642 */ 1643 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 1644 /* enum: Times are in seconds and nanoseconds */ 1645 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 1646 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 1647 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 1648 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 1649 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 1650 /* Minimum acceptable value for a corrected synchronization timeset. When 1651 * comparing host and NIC clock times, the MC returns a set of samples that 1652 * contain the host start and end time, the MC time when the host start was 1653 * detected and the time the MC waited between reading the time and detecting 1654 * the host end. The corrected sync window is the difference between the host 1655 * end and start times minus the time that the MC waited for host end. 1656 */ 1657 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 1658 /* Various PTP capabilities */ 1659 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8 1660 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0 1661 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1 1662 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12 1663 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16 1664 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20 1665 1666 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ 1667 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 1668 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 1669 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 1670 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 1671 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 1672 /* Uncorrected error on PPS output in NIC clock format */ 1673 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 1674 /* Uncorrected error on PPS input in NIC clock format */ 1675 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 1676 1677 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */ 1678 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24 1679 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 1680 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0 1681 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 1682 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4 1683 /* Uncorrected error on PPS output in NIC clock format */ 1684 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8 1685 /* Uncorrected error on PPS input in NIC clock format */ 1686 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12 1687 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */ 1688 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16 1689 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */ 1690 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20 1691 1692 /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ 1693 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 1694 /* Results of testing */ 1695 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 1696 /* Enum values, see field(s): */ 1697 /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ 1698 1699 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ 1700 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 1701 1702 1703 /***********************************/ 1704 /* MC_CMD_CSR_READ32 1705 * Read 32bit words from the indirect memory map. 1706 */ 1707 #define MC_CMD_CSR_READ32 0xc 1708 1709 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1710 1711 /* MC_CMD_CSR_READ32_IN msgrequest */ 1712 #define MC_CMD_CSR_READ32_IN_LEN 12 1713 /* Address */ 1714 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 1715 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 1716 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 1717 1718 /* MC_CMD_CSR_READ32_OUT msgresponse */ 1719 #define MC_CMD_CSR_READ32_OUT_LENMIN 4 1720 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 1721 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 1722 /* The last dword is the status, not a value read */ 1723 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 1724 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 1725 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 1726 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 1727 1728 1729 /***********************************/ 1730 /* MC_CMD_CSR_WRITE32 1731 * Write 32bit dwords to the indirect memory map. 1732 */ 1733 #define MC_CMD_CSR_WRITE32 0xd 1734 1735 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1736 1737 /* MC_CMD_CSR_WRITE32_IN msgrequest */ 1738 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 1739 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 1740 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 1741 /* Address */ 1742 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 1743 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 1744 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 1745 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 1746 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 1747 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 1748 1749 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 1750 #define MC_CMD_CSR_WRITE32_OUT_LEN 4 1751 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 1752 1753 1754 /***********************************/ 1755 /* MC_CMD_HP 1756 * These commands are used for HP related features. They are grouped under one 1757 * MCDI command to avoid creating too many MCDI commands. 1758 */ 1759 #define MC_CMD_HP 0x54 1760 1761 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1762 1763 /* MC_CMD_HP_IN msgrequest */ 1764 #define MC_CMD_HP_IN_LEN 16 1765 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at 1766 * the specified address with the specified interval.When address is NULL, 1767 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current 1768 * state / 2: (debug) Show temperature reported by one of the supported 1769 * sensors. 1770 */ 1771 #define MC_CMD_HP_IN_SUBCMD_OFST 0 1772 /* enum: OCSD (Option Card Sensor Data) sub-command. */ 1773 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 1774 /* enum: Last known valid HP sub-command. */ 1775 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 1776 /* The address to the array of sensor fields. (Or NULL to use a sub-command.) 1777 */ 1778 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 1779 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 1780 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 1781 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 1782 /* The requested update interval, in seconds. (Or the sub-command if ADDR is 1783 * NULL.) 1784 */ 1785 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 1786 1787 /* MC_CMD_HP_OUT msgresponse */ 1788 #define MC_CMD_HP_OUT_LEN 4 1789 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 1790 /* enum: OCSD stopped for this card. */ 1791 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 1792 /* enum: OCSD was successfully started with the address provided. */ 1793 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 1794 /* enum: OCSD was already started for this card. */ 1795 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 1796 1797 1798 /***********************************/ 1799 /* MC_CMD_STACKINFO 1800 * Get stack information. 1801 */ 1802 #define MC_CMD_STACKINFO 0xf 1803 1804 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1805 1806 /* MC_CMD_STACKINFO_IN msgrequest */ 1807 #define MC_CMD_STACKINFO_IN_LEN 0 1808 1809 /* MC_CMD_STACKINFO_OUT msgresponse */ 1810 #define MC_CMD_STACKINFO_OUT_LENMIN 12 1811 #define MC_CMD_STACKINFO_OUT_LENMAX 252 1812 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 1813 /* (thread ptr, stack size, free space) for each thread in system */ 1814 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 1815 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 1816 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 1817 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 1818 1819 1820 /***********************************/ 1821 /* MC_CMD_MDIO_READ 1822 * MDIO register read. 1823 */ 1824 #define MC_CMD_MDIO_READ 0x10 1825 1826 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1827 1828 /* MC_CMD_MDIO_READ_IN msgrequest */ 1829 #define MC_CMD_MDIO_READ_IN_LEN 16 1830 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 1831 * external devices. 1832 */ 1833 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 1834 /* enum: Internal. */ 1835 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 1836 /* enum: External. */ 1837 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 1838 /* Port address */ 1839 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 1840 /* Device Address or clause 22. */ 1841 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 1842 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 1843 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 1844 */ 1845 #define MC_CMD_MDIO_CLAUSE22 0x20 1846 /* Address */ 1847 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 1848 1849 /* MC_CMD_MDIO_READ_OUT msgresponse */ 1850 #define MC_CMD_MDIO_READ_OUT_LEN 8 1851 /* Value */ 1852 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 1853 /* Status the MDIO commands return the raw status bits from the MDIO block. A 1854 * "good" transaction should have the DONE bit set and all other bits clear. 1855 */ 1856 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 1857 /* enum: Good. */ 1858 #define MC_CMD_MDIO_STATUS_GOOD 0x8 1859 1860 1861 /***********************************/ 1862 /* MC_CMD_MDIO_WRITE 1863 * MDIO register write. 1864 */ 1865 #define MC_CMD_MDIO_WRITE 0x11 1866 1867 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1868 1869 /* MC_CMD_MDIO_WRITE_IN msgrequest */ 1870 #define MC_CMD_MDIO_WRITE_IN_LEN 20 1871 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 1872 * external devices. 1873 */ 1874 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 1875 /* enum: Internal. */ 1876 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 1877 /* enum: External. */ 1878 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 1879 /* Port address */ 1880 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 1881 /* Device Address or clause 22. */ 1882 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 1883 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 1884 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 1885 */ 1886 /* MC_CMD_MDIO_CLAUSE22 0x20 */ 1887 /* Address */ 1888 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 1889 /* Value */ 1890 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 1891 1892 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 1893 #define MC_CMD_MDIO_WRITE_OUT_LEN 4 1894 /* Status; the MDIO commands return the raw status bits from the MDIO block. A 1895 * "good" transaction should have the DONE bit set and all other bits clear. 1896 */ 1897 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 1898 /* enum: Good. */ 1899 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 1900 1901 1902 /***********************************/ 1903 /* MC_CMD_DBI_WRITE 1904 * Write DBI register(s). 1905 */ 1906 #define MC_CMD_DBI_WRITE 0x12 1907 1908 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1909 1910 /* MC_CMD_DBI_WRITE_IN msgrequest */ 1911 #define MC_CMD_DBI_WRITE_IN_LENMIN 12 1912 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 1913 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 1914 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset 1915 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. 1916 */ 1917 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 1918 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 1919 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 1920 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 1921 1922 /* MC_CMD_DBI_WRITE_OUT msgresponse */ 1923 #define MC_CMD_DBI_WRITE_OUT_LEN 0 1924 1925 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 1926 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 1927 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 1928 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 1929 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 1930 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 1931 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 1932 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 1933 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 1934 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 1935 #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 1936 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 1937 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 1938 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 1939 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 1940 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 1941 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 1942 1943 1944 /***********************************/ 1945 /* MC_CMD_PORT_READ32 1946 * Read a 32-bit register from the indirect port register map. The port to 1947 * access is implied by the Shared memory channel used. 1948 */ 1949 #define MC_CMD_PORT_READ32 0x14 1950 1951 /* MC_CMD_PORT_READ32_IN msgrequest */ 1952 #define MC_CMD_PORT_READ32_IN_LEN 4 1953 /* Address */ 1954 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 1955 1956 /* MC_CMD_PORT_READ32_OUT msgresponse */ 1957 #define MC_CMD_PORT_READ32_OUT_LEN 8 1958 /* Value */ 1959 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 1960 /* Status */ 1961 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 1962 1963 1964 /***********************************/ 1965 /* MC_CMD_PORT_WRITE32 1966 * Write a 32-bit register to the indirect port register map. The port to 1967 * access is implied by the Shared memory channel used. 1968 */ 1969 #define MC_CMD_PORT_WRITE32 0x15 1970 1971 /* MC_CMD_PORT_WRITE32_IN msgrequest */ 1972 #define MC_CMD_PORT_WRITE32_IN_LEN 8 1973 /* Address */ 1974 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 1975 /* Value */ 1976 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 1977 1978 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 1979 #define MC_CMD_PORT_WRITE32_OUT_LEN 4 1980 /* Status */ 1981 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 1982 1983 1984 /***********************************/ 1985 /* MC_CMD_PORT_READ128 1986 * Read a 128-bit register from the indirect port register map. The port to 1987 * access is implied by the Shared memory channel used. 1988 */ 1989 #define MC_CMD_PORT_READ128 0x16 1990 1991 /* MC_CMD_PORT_READ128_IN msgrequest */ 1992 #define MC_CMD_PORT_READ128_IN_LEN 4 1993 /* Address */ 1994 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 1995 1996 /* MC_CMD_PORT_READ128_OUT msgresponse */ 1997 #define MC_CMD_PORT_READ128_OUT_LEN 20 1998 /* Value */ 1999 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 2000 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 2001 /* Status */ 2002 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 2003 2004 2005 /***********************************/ 2006 /* MC_CMD_PORT_WRITE128 2007 * Write a 128-bit register to the indirect port register map. The port to 2008 * access is implied by the Shared memory channel used. 2009 */ 2010 #define MC_CMD_PORT_WRITE128 0x17 2011 2012 /* MC_CMD_PORT_WRITE128_IN msgrequest */ 2013 #define MC_CMD_PORT_WRITE128_IN_LEN 20 2014 /* Address */ 2015 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 2016 /* Value */ 2017 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 2018 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 2019 2020 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 2021 #define MC_CMD_PORT_WRITE128_OUT_LEN 4 2022 /* Status */ 2023 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 2024 2025 /* MC_CMD_CAPABILITIES structuredef */ 2026 #define MC_CMD_CAPABILITIES_LEN 4 2027 /* Small buf table. */ 2028 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 2029 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 2030 /* Turbo mode (for Maranello). */ 2031 #define MC_CMD_CAPABILITIES_TURBO_LBN 1 2032 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 2033 /* Turbo mode active (for Maranello). */ 2034 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 2035 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 2036 /* PTP offload. */ 2037 #define MC_CMD_CAPABILITIES_PTP_LBN 3 2038 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 2039 /* AOE mode. */ 2040 #define MC_CMD_CAPABILITIES_AOE_LBN 4 2041 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 2042 /* AOE mode active. */ 2043 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 2044 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 2045 /* AOE mode active. */ 2046 #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 2047 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 2048 #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 2049 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 2050 2051 2052 /***********************************/ 2053 /* MC_CMD_GET_BOARD_CFG 2054 * Returns the MC firmware configuration structure. 2055 */ 2056 #define MC_CMD_GET_BOARD_CFG 0x18 2057 2058 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2059 2060 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 2061 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 2062 2063 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 2064 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 2065 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 2066 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 2067 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 2068 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 2069 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 2070 /* See MC_CMD_CAPABILITIES */ 2071 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 2072 /* See MC_CMD_CAPABILITIES */ 2073 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 2074 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 2075 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 2076 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 2077 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 2078 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 2079 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 2080 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 2081 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 2082 /* This field contains a 16-bit value for each of the types of NVRAM area. The 2083 * values are defined in the firmware/mc/platform/.c file for a specific board 2084 * type, but otherwise have no meaning to the MC; they are used by the driver 2085 * to manage selection of appropriate firmware updates. 2086 */ 2087 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 2088 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 2089 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 2090 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 2091 2092 2093 /***********************************/ 2094 /* MC_CMD_DBI_READX 2095 * Read DBI register(s) -- extended functionality 2096 */ 2097 #define MC_CMD_DBI_READX 0x19 2098 2099 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2100 2101 /* MC_CMD_DBI_READX_IN msgrequest */ 2102 #define MC_CMD_DBI_READX_IN_LENMIN 8 2103 #define MC_CMD_DBI_READX_IN_LENMAX 248 2104 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 2105 /* Each Read op consists of an address (offset 0), VF/CS2) */ 2106 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 2107 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 2108 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 2109 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 2110 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 2111 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 2112 2113 /* MC_CMD_DBI_READX_OUT msgresponse */ 2114 #define MC_CMD_DBI_READX_OUT_LENMIN 4 2115 #define MC_CMD_DBI_READX_OUT_LENMAX 252 2116 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 2117 /* Value */ 2118 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 2119 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 2120 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 2121 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 2122 2123 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ 2124 #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 2125 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 2126 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 2127 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 2128 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 2129 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 2130 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 2131 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 2132 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 2133 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 2134 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 2135 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 2136 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 2137 2138 2139 /***********************************/ 2140 /* MC_CMD_SET_RAND_SEED 2141 * Set the 16byte seed for the MC pseudo-random generator. 2142 */ 2143 #define MC_CMD_SET_RAND_SEED 0x1a 2144 2145 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2146 2147 /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 2148 #define MC_CMD_SET_RAND_SEED_IN_LEN 16 2149 /* Seed value. */ 2150 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 2151 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 2152 2153 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 2154 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 2155 2156 2157 /***********************************/ 2158 /* MC_CMD_LTSSM_HIST 2159 * Retrieve the history of the LTSSM, if the build supports it. 2160 */ 2161 #define MC_CMD_LTSSM_HIST 0x1b 2162 2163 /* MC_CMD_LTSSM_HIST_IN msgrequest */ 2164 #define MC_CMD_LTSSM_HIST_IN_LEN 0 2165 2166 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 2167 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 2168 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 2169 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 2170 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ 2171 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 2172 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 2173 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 2174 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 2175 2176 2177 /***********************************/ 2178 /* MC_CMD_DRV_ATTACH 2179 * Inform MCPU that this port is managed on the host (i.e. driver active). For 2180 * Huntington, also request the preferred datapath firmware to use if possible 2181 * (it may not be possible for this request to be fulfilled; the driver must 2182 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which 2183 * features are actually available). The FIRMWARE_ID field is ignored by older 2184 * platforms. 2185 */ 2186 #define MC_CMD_DRV_ATTACH 0x1c 2187 2188 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2189 2190 /* MC_CMD_DRV_ATTACH_IN msgrequest */ 2191 #define MC_CMD_DRV_ATTACH_IN_LEN 12 2192 /* new state to set if UPDATE=1 */ 2193 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 2194 #define MC_CMD_DRV_ATTACH_LBN 0 2195 #define MC_CMD_DRV_ATTACH_WIDTH 1 2196 #define MC_CMD_DRV_PREBOOT_LBN 1 2197 #define MC_CMD_DRV_PREBOOT_WIDTH 1 2198 /* 1 to set new state, or 0 to just report the existing state */ 2199 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 2200 /* preferred datapath firmware (for Huntington; ignored for Siena) */ 2201 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 2202 /* enum: Prefer to use full featured firmware */ 2203 #define MC_CMD_FW_FULL_FEATURED 0x0 2204 /* enum: Prefer to use firmware with fewer features but lower latency */ 2205 #define MC_CMD_FW_LOW_LATENCY 0x1 2206 /* enum: Prefer to use firmware for SolarCapture packed stream mode */ 2207 #define MC_CMD_FW_PACKED_STREAM 0x2 2208 /* enum: Prefer to use firmware with fewer features and simpler TX event 2209 * batching but higher TX packet rate 2210 */ 2211 #define MC_CMD_FW_HIGH_TX_RATE 0x3 2212 /* enum: Reserved value */ 2213 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 2214 /* enum: Only this option is allowed for non-admin functions */ 2215 #define MC_CMD_FW_DONT_CARE 0xffffffff 2216 2217 /* MC_CMD_DRV_ATTACH_OUT msgresponse */ 2218 #define MC_CMD_DRV_ATTACH_OUT_LEN 4 2219 /* previous or existing state, see the bitmask at NEW_STATE */ 2220 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 2221 2222 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ 2223 #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 2224 /* previous or existing state, see the bitmask at NEW_STATE */ 2225 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 2226 /* Flags associated with this function */ 2227 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 2228 /* enum: Labels the lowest-numbered function visible to the OS */ 2229 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 2230 /* enum: The function can control the link state of the physical port it is 2231 * bound to. 2232 */ 2233 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 2234 /* enum: The function can perform privileged operations */ 2235 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 2236 /* enum: The function does not have an active port associated with it. The port 2237 * refers to the Sorrento external FPGA port. 2238 */ 2239 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3 2240 2241 2242 /***********************************/ 2243 /* MC_CMD_SHMUART 2244 * Route UART output to circular buffer in shared memory instead. 2245 */ 2246 #define MC_CMD_SHMUART 0x1f 2247 2248 /* MC_CMD_SHMUART_IN msgrequest */ 2249 #define MC_CMD_SHMUART_IN_LEN 4 2250 /* ??? */ 2251 #define MC_CMD_SHMUART_IN_FLAG_OFST 0 2252 2253 /* MC_CMD_SHMUART_OUT msgresponse */ 2254 #define MC_CMD_SHMUART_OUT_LEN 0 2255 2256 2257 /***********************************/ 2258 /* MC_CMD_PORT_RESET 2259 * Generic per-port reset. There is no equivalent for per-board reset. Locks 2260 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - 2261 * use MC_CMD_ENTITY_RESET instead. 2262 */ 2263 #define MC_CMD_PORT_RESET 0x20 2264 2265 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2266 2267 /* MC_CMD_PORT_RESET_IN msgrequest */ 2268 #define MC_CMD_PORT_RESET_IN_LEN 0 2269 2270 /* MC_CMD_PORT_RESET_OUT msgresponse */ 2271 #define MC_CMD_PORT_RESET_OUT_LEN 0 2272 2273 2274 /***********************************/ 2275 /* MC_CMD_ENTITY_RESET 2276 * Generic per-resource reset. There is no equivalent for per-board reset. 2277 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an 2278 * extended version of the deprecated MC_CMD_PORT_RESET with added fields. 2279 */ 2280 #define MC_CMD_ENTITY_RESET 0x20 2281 /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */ 2282 2283 /* MC_CMD_ENTITY_RESET_IN msgrequest */ 2284 #define MC_CMD_ENTITY_RESET_IN_LEN 4 2285 /* Optional flags field. Omitting this will perform a "legacy" reset action 2286 * (TBD). 2287 */ 2288 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 2289 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 2290 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 2291 2292 /* MC_CMD_ENTITY_RESET_OUT msgresponse */ 2293 #define MC_CMD_ENTITY_RESET_OUT_LEN 0 2294 2295 2296 /***********************************/ 2297 /* MC_CMD_PCIE_CREDITS 2298 * Read instantaneous and minimum flow control thresholds. 2299 */ 2300 #define MC_CMD_PCIE_CREDITS 0x21 2301 2302 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 2303 #define MC_CMD_PCIE_CREDITS_IN_LEN 8 2304 /* poll period. 0 is disabled */ 2305 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 2306 /* wipe statistics */ 2307 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 2308 2309 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 2310 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 2311 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 2312 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 2313 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 2314 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 2315 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 2316 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 2317 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 2318 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 2319 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 2320 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 2321 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 2322 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 2323 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 2324 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 2325 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 2326 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 2327 2328 2329 /***********************************/ 2330 /* MC_CMD_RXD_MONITOR 2331 * Get histogram of RX queue fill level. 2332 */ 2333 #define MC_CMD_RXD_MONITOR 0x22 2334 2335 /* MC_CMD_RXD_MONITOR_IN msgrequest */ 2336 #define MC_CMD_RXD_MONITOR_IN_LEN 12 2337 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 2338 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 2339 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 2340 2341 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 2342 #define MC_CMD_RXD_MONITOR_OUT_LEN 80 2343 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 2344 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 2345 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 2346 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 2347 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 2348 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 2349 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 2350 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 2351 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 2352 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 2353 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 2354 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 2355 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 2356 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 2357 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 2358 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 2359 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 2360 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 2361 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 2362 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 2363 2364 2365 /***********************************/ 2366 /* MC_CMD_PUTS 2367 * Copy the given ASCII string out onto UART and/or out of the network port. 2368 */ 2369 #define MC_CMD_PUTS 0x23 2370 2371 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2372 2373 /* MC_CMD_PUTS_IN msgrequest */ 2374 #define MC_CMD_PUTS_IN_LENMIN 13 2375 #define MC_CMD_PUTS_IN_LENMAX 252 2376 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 2377 #define MC_CMD_PUTS_IN_DEST_OFST 0 2378 #define MC_CMD_PUTS_IN_UART_LBN 0 2379 #define MC_CMD_PUTS_IN_UART_WIDTH 1 2380 #define MC_CMD_PUTS_IN_PORT_LBN 1 2381 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 2382 #define MC_CMD_PUTS_IN_DHOST_OFST 4 2383 #define MC_CMD_PUTS_IN_DHOST_LEN 6 2384 #define MC_CMD_PUTS_IN_STRING_OFST 12 2385 #define MC_CMD_PUTS_IN_STRING_LEN 1 2386 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 2387 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 2388 2389 /* MC_CMD_PUTS_OUT msgresponse */ 2390 #define MC_CMD_PUTS_OUT_LEN 0 2391 2392 2393 /***********************************/ 2394 /* MC_CMD_GET_PHY_CFG 2395 * Report PHY configuration. This guarantees to succeed even if the PHY is in a 2396 * 'zombie' state. Locks required: None 2397 */ 2398 #define MC_CMD_GET_PHY_CFG 0x24 2399 2400 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2401 2402 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 2403 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 2404 2405 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 2406 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 2407 /* flags */ 2408 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 2409 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 2410 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 2411 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 2412 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 2413 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 2414 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 2415 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 2416 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 2417 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 2418 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 2419 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 2420 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 2421 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 2422 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 2423 /* ?? */ 2424 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 2425 /* Bitmask of supported capabilities */ 2426 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 2427 #define MC_CMD_PHY_CAP_10HDX_LBN 1 2428 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 2429 #define MC_CMD_PHY_CAP_10FDX_LBN 2 2430 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 2431 #define MC_CMD_PHY_CAP_100HDX_LBN 3 2432 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 2433 #define MC_CMD_PHY_CAP_100FDX_LBN 4 2434 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 2435 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 2436 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 2437 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 2438 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 2439 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 2440 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 2441 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 2442 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 2443 #define MC_CMD_PHY_CAP_ASYM_LBN 9 2444 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 2445 #define MC_CMD_PHY_CAP_AN_LBN 10 2446 #define MC_CMD_PHY_CAP_AN_WIDTH 1 2447 #define MC_CMD_PHY_CAP_40000FDX_LBN 11 2448 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 2449 #define MC_CMD_PHY_CAP_DDM_LBN 12 2450 #define MC_CMD_PHY_CAP_DDM_WIDTH 1 2451 /* ?? */ 2452 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 2453 /* ?? */ 2454 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 2455 /* ?? */ 2456 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 2457 /* ?? */ 2458 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 2459 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 2460 /* ?? */ 2461 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 2462 /* enum: Xaui. */ 2463 #define MC_CMD_MEDIA_XAUI 0x1 2464 /* enum: CX4. */ 2465 #define MC_CMD_MEDIA_CX4 0x2 2466 /* enum: KX4. */ 2467 #define MC_CMD_MEDIA_KX4 0x3 2468 /* enum: XFP Far. */ 2469 #define MC_CMD_MEDIA_XFP 0x4 2470 /* enum: SFP+. */ 2471 #define MC_CMD_MEDIA_SFP_PLUS 0x5 2472 /* enum: 10GBaseT. */ 2473 #define MC_CMD_MEDIA_BASE_T 0x6 2474 /* enum: QSFP+. */ 2475 #define MC_CMD_MEDIA_QSFP_PLUS 0x7 2476 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 2477 /* enum: Native clause 22 */ 2478 #define MC_CMD_MMD_CLAUSE22 0x0 2479 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 2480 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 2481 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 2482 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 2483 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 2484 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 2485 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 2486 /* enum: Clause22 proxied over clause45 by PHY. */ 2487 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d 2488 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 2489 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 2490 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 2491 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 2492 2493 2494 /***********************************/ 2495 /* MC_CMD_START_BIST 2496 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST 2497 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) 2498 */ 2499 #define MC_CMD_START_BIST 0x25 2500 2501 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2502 2503 /* MC_CMD_START_BIST_IN msgrequest */ 2504 #define MC_CMD_START_BIST_IN_LEN 4 2505 /* Type of test. */ 2506 #define MC_CMD_START_BIST_IN_TYPE_OFST 0 2507 /* enum: Run the PHY's short cable BIST. */ 2508 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 2509 /* enum: Run the PHY's long cable BIST. */ 2510 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 2511 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ 2512 #define MC_CMD_BPX_SERDES_BIST 0x3 2513 /* enum: Run the MC loopback tests. */ 2514 #define MC_CMD_MC_LOOPBACK_BIST 0x4 2515 /* enum: Run the PHY's standard BIST. */ 2516 #define MC_CMD_PHY_BIST 0x5 2517 /* enum: Run MC RAM test. */ 2518 #define MC_CMD_MC_MEM_BIST 0x6 2519 /* enum: Run Port RAM test. */ 2520 #define MC_CMD_PORT_MEM_BIST 0x7 2521 /* enum: Run register test. */ 2522 #define MC_CMD_REG_BIST 0x8 2523 2524 /* MC_CMD_START_BIST_OUT msgresponse */ 2525 #define MC_CMD_START_BIST_OUT_LEN 0 2526 2527 2528 /***********************************/ 2529 /* MC_CMD_POLL_BIST 2530 * Poll for BIST completion. Returns a single status code, and optionally some 2531 * PHY specific bist output. The driver should only consume the BIST output 2532 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't 2533 * successfully parse the BIST output, it should still respect the pass/Fail in 2534 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, 2535 * EACCES (if PHY_LOCK is not held). 2536 */ 2537 #define MC_CMD_POLL_BIST 0x26 2538 2539 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2540 2541 /* MC_CMD_POLL_BIST_IN msgrequest */ 2542 #define MC_CMD_POLL_BIST_IN_LEN 0 2543 2544 /* MC_CMD_POLL_BIST_OUT msgresponse */ 2545 #define MC_CMD_POLL_BIST_OUT_LEN 8 2546 /* result */ 2547 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 2548 /* enum: Running. */ 2549 #define MC_CMD_POLL_BIST_RUNNING 0x1 2550 /* enum: Passed. */ 2551 #define MC_CMD_POLL_BIST_PASSED 0x2 2552 /* enum: Failed. */ 2553 #define MC_CMD_POLL_BIST_FAILED 0x3 2554 /* enum: Timed-out. */ 2555 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 2556 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 2557 2558 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 2559 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 2560 /* result */ 2561 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 2562 /* Enum values, see field(s): */ 2563 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 2564 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 2565 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 2566 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 2567 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 2568 /* Status of each channel A */ 2569 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 2570 /* enum: Ok. */ 2571 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 2572 /* enum: Open. */ 2573 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 2574 /* enum: Intra-pair short. */ 2575 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 2576 /* enum: Inter-pair short. */ 2577 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 2578 /* enum: Busy. */ 2579 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 2580 /* Status of each channel B */ 2581 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 2582 /* Enum values, see field(s): */ 2583 /* CABLE_STATUS_A */ 2584 /* Status of each channel C */ 2585 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 2586 /* Enum values, see field(s): */ 2587 /* CABLE_STATUS_A */ 2588 /* Status of each channel D */ 2589 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 2590 /* Enum values, see field(s): */ 2591 /* CABLE_STATUS_A */ 2592 2593 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 2594 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 2595 /* result */ 2596 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 2597 /* Enum values, see field(s): */ 2598 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 2599 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 2600 /* enum: Complete. */ 2601 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 2602 /* enum: Bus switch off I2C write. */ 2603 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 2604 /* enum: Bus switch off I2C no access IO exp. */ 2605 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 2606 /* enum: Bus switch off I2C no access module. */ 2607 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 2608 /* enum: IO exp I2C configure. */ 2609 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 2610 /* enum: Bus switch I2C no cross talk. */ 2611 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 2612 /* enum: Module presence. */ 2613 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 2614 /* enum: Module ID I2C access. */ 2615 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 2616 /* enum: Module ID sane value. */ 2617 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 2618 2619 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ 2620 #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 2621 /* result */ 2622 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 2623 /* Enum values, see field(s): */ 2624 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 2625 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 2626 /* enum: Test has completed. */ 2627 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 2628 /* enum: RAM test - walk ones. */ 2629 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 2630 /* enum: RAM test - walk zeros. */ 2631 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 2632 /* enum: RAM test - walking inversions zeros/ones. */ 2633 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 2634 /* enum: RAM test - walking inversions checkerboard. */ 2635 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 2636 /* enum: Register test - set / clear individual bits. */ 2637 #define MC_CMD_POLL_BIST_MEM_REG 0x5 2638 /* enum: ECC error detected. */ 2639 #define MC_CMD_POLL_BIST_MEM_ECC 0x6 2640 /* Failure address, only valid if result is POLL_BIST_FAILED */ 2641 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 2642 /* Bus or address space to which the failure address corresponds */ 2643 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 2644 /* enum: MC MIPS bus. */ 2645 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 2646 /* enum: CSR IREG bus. */ 2647 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 2648 /* enum: RX DPCPU bus. */ 2649 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 2650 /* enum: TX0 DPCPU bus. */ 2651 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 2652 /* enum: TX1 DPCPU bus. */ 2653 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 2654 /* enum: RX DICPU bus. */ 2655 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 2656 /* enum: TX DICPU bus. */ 2657 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 2658 /* Pattern written to RAM / register */ 2659 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 2660 /* Actual value read from RAM / register */ 2661 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 2662 /* ECC error mask */ 2663 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 2664 /* ECC parity error mask */ 2665 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 2666 /* ECC fatal error mask */ 2667 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 2668 2669 2670 /***********************************/ 2671 /* MC_CMD_FLUSH_RX_QUEUES 2672 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ 2673 * flushes should be initiated via this MCDI operation, rather than via 2674 * directly writing FLUSH_CMD. 2675 * 2676 * The flush is completed (either done/fail) asynchronously (after this command 2677 * returns). The driver must still wait for flush done/failure events as usual. 2678 */ 2679 #define MC_CMD_FLUSH_RX_QUEUES 0x27 2680 2681 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 2682 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 2683 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 2684 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 2685 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 2686 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 2687 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 2688 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 2689 2690 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 2691 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 2692 2693 2694 /***********************************/ 2695 /* MC_CMD_GET_LOOPBACK_MODES 2696 * Returns a bitmask of loopback modes available at each speed. 2697 */ 2698 #define MC_CMD_GET_LOOPBACK_MODES 0x28 2699 2700 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2701 2702 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 2703 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 2704 2705 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 2706 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 2707 /* Supported loopbacks. */ 2708 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 2709 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 2710 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 2711 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 2712 /* enum: None. */ 2713 #define MC_CMD_LOOPBACK_NONE 0x0 2714 /* enum: Data. */ 2715 #define MC_CMD_LOOPBACK_DATA 0x1 2716 /* enum: GMAC. */ 2717 #define MC_CMD_LOOPBACK_GMAC 0x2 2718 /* enum: XGMII. */ 2719 #define MC_CMD_LOOPBACK_XGMII 0x3 2720 /* enum: XGXS. */ 2721 #define MC_CMD_LOOPBACK_XGXS 0x4 2722 /* enum: XAUI. */ 2723 #define MC_CMD_LOOPBACK_XAUI 0x5 2724 /* enum: GMII. */ 2725 #define MC_CMD_LOOPBACK_GMII 0x6 2726 /* enum: SGMII. */ 2727 #define MC_CMD_LOOPBACK_SGMII 0x7 2728 /* enum: XGBR. */ 2729 #define MC_CMD_LOOPBACK_XGBR 0x8 2730 /* enum: XFI. */ 2731 #define MC_CMD_LOOPBACK_XFI 0x9 2732 /* enum: XAUI Far. */ 2733 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa 2734 /* enum: GMII Far. */ 2735 #define MC_CMD_LOOPBACK_GMII_FAR 0xb 2736 /* enum: SGMII Far. */ 2737 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc 2738 /* enum: XFI Far. */ 2739 #define MC_CMD_LOOPBACK_XFI_FAR 0xd 2740 /* enum: GPhy. */ 2741 #define MC_CMD_LOOPBACK_GPHY 0xe 2742 /* enum: PhyXS. */ 2743 #define MC_CMD_LOOPBACK_PHYXS 0xf 2744 /* enum: PCS. */ 2745 #define MC_CMD_LOOPBACK_PCS 0x10 2746 /* enum: PMA-PMD. */ 2747 #define MC_CMD_LOOPBACK_PMAPMD 0x11 2748 /* enum: Cross-Port. */ 2749 #define MC_CMD_LOOPBACK_XPORT 0x12 2750 /* enum: XGMII-Wireside. */ 2751 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 2752 /* enum: XAUI Wireside. */ 2753 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 2754 /* enum: XAUI Wireside Far. */ 2755 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 2756 /* enum: XAUI Wireside near. */ 2757 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 2758 /* enum: GMII Wireside. */ 2759 #define MC_CMD_LOOPBACK_GMII_WS 0x17 2760 /* enum: XFI Wireside. */ 2761 #define MC_CMD_LOOPBACK_XFI_WS 0x18 2762 /* enum: XFI Wireside Far. */ 2763 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 2764 /* enum: PhyXS Wireside. */ 2765 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a 2766 /* enum: PMA lanes MAC-Serdes. */ 2767 #define MC_CMD_LOOPBACK_PMA_INT 0x1b 2768 /* enum: KR Serdes Parallel (Encoder). */ 2769 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c 2770 /* enum: KR Serdes Serial. */ 2771 #define MC_CMD_LOOPBACK_SD_FAR 0x1d 2772 /* enum: PMA lanes MAC-Serdes Wireside. */ 2773 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e 2774 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 2775 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f 2776 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 2777 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 2778 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 2779 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 2780 /* enum: KR Serdes Serial Wireside. */ 2781 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 2782 /* enum: Near side of AOE Siena side port */ 2783 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 2784 /* enum: Medford Wireside datapath loopback */ 2785 #define MC_CMD_LOOPBACK_DATA_WS 0x24 2786 /* enum: Force link up without setting up any physical loopback (snapper use 2787 * only) 2788 */ 2789 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 2790 /* Supported loopbacks. */ 2791 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 2792 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 2793 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 2794 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 2795 /* Enum values, see field(s): */ 2796 /* 100M */ 2797 /* Supported loopbacks. */ 2798 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 2799 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 2800 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 2801 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 2802 /* Enum values, see field(s): */ 2803 /* 100M */ 2804 /* Supported loopbacks. */ 2805 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 2806 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 2807 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 2808 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 2809 /* Enum values, see field(s): */ 2810 /* 100M */ 2811 /* Supported loopbacks. */ 2812 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 2813 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 2814 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 2815 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 2816 /* Enum values, see field(s): */ 2817 /* 100M */ 2818 2819 2820 /***********************************/ 2821 /* MC_CMD_GET_LINK 2822 * Read the unified MAC/PHY link state. Locks required: None Return code: 0, 2823 * ETIME. 2824 */ 2825 #define MC_CMD_GET_LINK 0x29 2826 2827 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2828 2829 /* MC_CMD_GET_LINK_IN msgrequest */ 2830 #define MC_CMD_GET_LINK_IN_LEN 0 2831 2832 /* MC_CMD_GET_LINK_OUT msgresponse */ 2833 #define MC_CMD_GET_LINK_OUT_LEN 28 2834 /* near-side advertised capabilities */ 2835 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 2836 /* link-partner advertised capabilities */ 2837 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 2838 /* Autonegotiated speed in mbit/s. The link may still be down even if this 2839 * reads non-zero. 2840 */ 2841 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 2842 /* Current loopback setting. */ 2843 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 2844 /* Enum values, see field(s): */ 2845 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 2846 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 2847 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 2848 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 2849 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 2850 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 2851 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 2852 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 2853 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 2854 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 2855 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 2856 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 2857 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 2858 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 2859 /* This returns the negotiated flow control value. */ 2860 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 2861 /* Enum values, see field(s): */ 2862 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 2863 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 2864 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 2865 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 2866 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 2867 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 2868 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 2869 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 2870 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 2871 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 2872 2873 2874 /***********************************/ 2875 /* MC_CMD_SET_LINK 2876 * Write the unified MAC/PHY link configuration. Locks required: None. Return 2877 * code: 0, EINVAL, ETIME 2878 */ 2879 #define MC_CMD_SET_LINK 0x2a 2880 2881 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK 2882 2883 /* MC_CMD_SET_LINK_IN msgrequest */ 2884 #define MC_CMD_SET_LINK_IN_LEN 16 2885 /* ??? */ 2886 #define MC_CMD_SET_LINK_IN_CAP_OFST 0 2887 /* Flags */ 2888 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 2889 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 2890 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 2891 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 2892 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 2893 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 2894 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 2895 /* Loopback mode. */ 2896 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 2897 /* Enum values, see field(s): */ 2898 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 2899 /* A loopback speed of "0" is supported, and means (choose any available 2900 * speed). 2901 */ 2902 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 2903 2904 /* MC_CMD_SET_LINK_OUT msgresponse */ 2905 #define MC_CMD_SET_LINK_OUT_LEN 0 2906 2907 2908 /***********************************/ 2909 /* MC_CMD_SET_ID_LED 2910 * Set identification LED state. Locks required: None. Return code: 0, EINVAL 2911 */ 2912 #define MC_CMD_SET_ID_LED 0x2b 2913 2914 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK 2915 2916 /* MC_CMD_SET_ID_LED_IN msgrequest */ 2917 #define MC_CMD_SET_ID_LED_IN_LEN 4 2918 /* Set LED state. */ 2919 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 2920 #define MC_CMD_LED_OFF 0x0 /* enum */ 2921 #define MC_CMD_LED_ON 0x1 /* enum */ 2922 #define MC_CMD_LED_DEFAULT 0x2 /* enum */ 2923 2924 /* MC_CMD_SET_ID_LED_OUT msgresponse */ 2925 #define MC_CMD_SET_ID_LED_OUT_LEN 0 2926 2927 2928 /***********************************/ 2929 /* MC_CMD_SET_MAC 2930 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL 2931 */ 2932 #define MC_CMD_SET_MAC 0x2c 2933 2934 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2935 2936 /* MC_CMD_SET_MAC_IN msgrequest */ 2937 #define MC_CMD_SET_MAC_IN_LEN 28 2938 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 2939 * EtherII, VLAN, bug16011 padding). 2940 */ 2941 #define MC_CMD_SET_MAC_IN_MTU_OFST 0 2942 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 2943 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 2944 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 2945 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 2946 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 2947 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 2948 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 2949 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 2950 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 2951 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 2952 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 2953 /* enum: Flow control is off. */ 2954 #define MC_CMD_FCNTL_OFF 0x0 2955 /* enum: Respond to flow control. */ 2956 #define MC_CMD_FCNTL_RESPOND 0x1 2957 /* enum: Respond to and Issue flow control. */ 2958 #define MC_CMD_FCNTL_BIDIR 0x2 2959 /* enum: Auto neg flow control. */ 2960 #define MC_CMD_FCNTL_AUTO 0x3 2961 /* enum: Priority flow control (eftest builds only). */ 2962 #define MC_CMD_FCNTL_QBB 0x4 2963 /* enum: Issue flow control. */ 2964 #define MC_CMD_FCNTL_GENERATE 0x5 2965 #define MC_CMD_SET_MAC_IN_FLAGS_OFST 24 2966 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0 2967 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1 2968 2969 /* MC_CMD_SET_MAC_EXT_IN msgrequest */ 2970 #define MC_CMD_SET_MAC_EXT_IN_LEN 32 2971 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 2972 * EtherII, VLAN, bug16011 padding). 2973 */ 2974 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0 2975 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4 2976 #define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8 2977 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8 2978 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8 2979 #define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12 2980 #define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16 2981 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0 2982 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1 2983 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1 2984 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1 2985 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20 2986 /* enum: Flow control is off. */ 2987 /* MC_CMD_FCNTL_OFF 0x0 */ 2988 /* enum: Respond to flow control. */ 2989 /* MC_CMD_FCNTL_RESPOND 0x1 */ 2990 /* enum: Respond to and Issue flow control. */ 2991 /* MC_CMD_FCNTL_BIDIR 0x2 */ 2992 /* enum: Auto neg flow control. */ 2993 /* MC_CMD_FCNTL_AUTO 0x3 */ 2994 /* enum: Priority flow control (eftest builds only). */ 2995 /* MC_CMD_FCNTL_QBB 0x4 */ 2996 /* enum: Issue flow control. */ 2997 /* MC_CMD_FCNTL_GENERATE 0x5 */ 2998 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24 2999 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0 3000 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1 3001 /* Select which parameters to configure. A parameter will only be modified if 3002 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in 3003 * capabilities then this field is ignored (and all flags are assumed to be 3004 * set). 3005 */ 3006 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28 3007 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0 3008 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1 3009 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1 3010 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1 3011 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2 3012 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1 3013 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3 3014 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1 3015 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4 3016 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1 3017 3018 /* MC_CMD_SET_MAC_OUT msgresponse */ 3019 #define MC_CMD_SET_MAC_OUT_LEN 0 3020 3021 /* MC_CMD_SET_MAC_V2_OUT msgresponse */ 3022 #define MC_CMD_SET_MAC_V2_OUT_LEN 4 3023 /* MTU as configured after processing the request. See comment at 3024 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL 3025 * to 0. 3026 */ 3027 #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0 3028 3029 3030 /***********************************/ 3031 /* MC_CMD_PHY_STATS 3032 * Get generic PHY statistics. This call returns the statistics for a generic 3033 * PHY in a sparse array (indexed by the enumerate). Each value is represented 3034 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the 3035 * statistics may be read from the message response. If DMA_ADDR != 0, then the 3036 * statistics are dmad to that (page-aligned location). Locks required: None. 3037 * Returns: 0, ETIME 3038 */ 3039 #define MC_CMD_PHY_STATS 0x2d 3040 3041 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK 3042 3043 /* MC_CMD_PHY_STATS_IN msgrequest */ 3044 #define MC_CMD_PHY_STATS_IN_LEN 8 3045 /* ??? */ 3046 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 3047 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 3048 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 3049 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 3050 3051 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 3052 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 3053 3054 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 3055 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 3056 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 3057 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 3058 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 3059 /* enum: OUI. */ 3060 #define MC_CMD_OUI 0x0 3061 /* enum: PMA-PMD Link Up. */ 3062 #define MC_CMD_PMA_PMD_LINK_UP 0x1 3063 /* enum: PMA-PMD RX Fault. */ 3064 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 3065 /* enum: PMA-PMD TX Fault. */ 3066 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 3067 /* enum: PMA-PMD Signal */ 3068 #define MC_CMD_PMA_PMD_SIGNAL 0x4 3069 /* enum: PMA-PMD SNR A. */ 3070 #define MC_CMD_PMA_PMD_SNR_A 0x5 3071 /* enum: PMA-PMD SNR B. */ 3072 #define MC_CMD_PMA_PMD_SNR_B 0x6 3073 /* enum: PMA-PMD SNR C. */ 3074 #define MC_CMD_PMA_PMD_SNR_C 0x7 3075 /* enum: PMA-PMD SNR D. */ 3076 #define MC_CMD_PMA_PMD_SNR_D 0x8 3077 /* enum: PCS Link Up. */ 3078 #define MC_CMD_PCS_LINK_UP 0x9 3079 /* enum: PCS RX Fault. */ 3080 #define MC_CMD_PCS_RX_FAULT 0xa 3081 /* enum: PCS TX Fault. */ 3082 #define MC_CMD_PCS_TX_FAULT 0xb 3083 /* enum: PCS BER. */ 3084 #define MC_CMD_PCS_BER 0xc 3085 /* enum: PCS Block Errors. */ 3086 #define MC_CMD_PCS_BLOCK_ERRORS 0xd 3087 /* enum: PhyXS Link Up. */ 3088 #define MC_CMD_PHYXS_LINK_UP 0xe 3089 /* enum: PhyXS RX Fault. */ 3090 #define MC_CMD_PHYXS_RX_FAULT 0xf 3091 /* enum: PhyXS TX Fault. */ 3092 #define MC_CMD_PHYXS_TX_FAULT 0x10 3093 /* enum: PhyXS Align. */ 3094 #define MC_CMD_PHYXS_ALIGN 0x11 3095 /* enum: PhyXS Sync. */ 3096 #define MC_CMD_PHYXS_SYNC 0x12 3097 /* enum: AN link-up. */ 3098 #define MC_CMD_AN_LINK_UP 0x13 3099 /* enum: AN Complete. */ 3100 #define MC_CMD_AN_COMPLETE 0x14 3101 /* enum: AN 10GBaseT Status. */ 3102 #define MC_CMD_AN_10GBT_STATUS 0x15 3103 /* enum: Clause 22 Link-Up. */ 3104 #define MC_CMD_CL22_LINK_UP 0x16 3105 /* enum: (Last entry) */ 3106 #define MC_CMD_PHY_NSTATS 0x17 3107 3108 3109 /***********************************/ 3110 /* MC_CMD_MAC_STATS 3111 * Get generic MAC statistics. This call returns unified statistics maintained 3112 * by the MC as it switches between the GMAC and XMAC. The MC will write out 3113 * all supported stats. The driver should zero initialise the buffer to 3114 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is 3115 * performed, and the statistics may be read from the message response. If 3116 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). 3117 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no 3118 * effect. Returns: 0, ETIME 3119 */ 3120 #define MC_CMD_MAC_STATS 0x2e 3121 3122 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3123 3124 /* MC_CMD_MAC_STATS_IN msgrequest */ 3125 #define MC_CMD_MAC_STATS_IN_LEN 20 3126 /* ??? */ 3127 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 3128 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 3129 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 3130 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 3131 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 3132 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 3133 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 3134 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 3135 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 3136 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 3137 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 3138 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 3139 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 3140 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 3141 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 3142 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 3143 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 3144 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 3145 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 3146 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 3147 /* port id so vadapter stats can be provided */ 3148 #define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16 3149 3150 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 3151 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 3152 3153 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 3154 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 3155 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 3156 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 3157 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 3158 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 3159 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 3160 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 3161 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */ 3162 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 3163 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 3164 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 3165 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 3166 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 3167 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 3168 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 3169 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 3170 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 3171 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 3172 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 3173 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 3174 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 3175 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 3176 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 3177 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 3178 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 3179 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 3180 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 3181 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 3182 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 3183 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 3184 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 3185 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 3186 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 3187 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 3188 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 3189 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 3190 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 3191 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 3192 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 3193 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 3194 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 3195 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 3196 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 3197 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 3198 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 3199 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 3200 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 3201 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 3202 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 3203 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 3204 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 3205 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 3206 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 3207 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 3208 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 3209 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 3210 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 3211 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 3212 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 3213 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 3214 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 3215 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 3216 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 3217 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 3218 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 3219 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 3220 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 3221 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3222 * capability only. 3223 */ 3224 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c 3225 /* enum: PM discard_bb_overflow counter. Valid for EF10 with 3226 * PM_AND_RXDP_COUNTERS capability only. 3227 */ 3228 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d 3229 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3230 * capability only. 3231 */ 3232 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e 3233 /* enum: PM discard_vfifo_full counter. Valid for EF10 with 3234 * PM_AND_RXDP_COUNTERS capability only. 3235 */ 3236 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f 3237 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3238 * capability only. 3239 */ 3240 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40 3241 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3242 * capability only. 3243 */ 3244 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41 3245 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3246 * capability only. 3247 */ 3248 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 3249 /* enum: RXDP counter: Number of packets dropped due to the queue being 3250 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 3251 */ 3252 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 3253 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 3254 * with PM_AND_RXDP_COUNTERS capability only. 3255 */ 3256 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 3257 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with 3258 * PM_AND_RXDP_COUNTERS capability only. 3259 */ 3260 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 3261 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed. 3262 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 3263 */ 3264 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47 3265 /* enum: RXDP counter: Number of times the DPCPU waited for an existing 3266 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 3267 */ 3268 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48 3269 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */ 3270 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */ 3271 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */ 3272 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */ 3273 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */ 3274 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */ 3275 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */ 3276 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */ 3277 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */ 3278 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */ 3279 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */ 3280 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */ 3281 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */ 3282 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */ 3283 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */ 3284 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */ 3285 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */ 3286 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */ 3287 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */ 3288 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */ 3289 /* enum: Start of GMAC stats buffer space, for Siena only. */ 3290 #define MC_CMD_GMAC_DMABUF_START 0x40 3291 /* enum: End of GMAC stats buffer space, for Siena only. */ 3292 #define MC_CMD_GMAC_DMABUF_END 0x5f 3293 #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ 3294 #define MC_CMD_MAC_NSTATS 0x61 /* enum */ 3295 3296 3297 /***********************************/ 3298 /* MC_CMD_SRIOV 3299 * to be documented 3300 */ 3301 #define MC_CMD_SRIOV 0x30 3302 3303 /* MC_CMD_SRIOV_IN msgrequest */ 3304 #define MC_CMD_SRIOV_IN_LEN 12 3305 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 3306 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 3307 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 3308 3309 /* MC_CMD_SRIOV_OUT msgresponse */ 3310 #define MC_CMD_SRIOV_OUT_LEN 8 3311 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 3312 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 3313 3314 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 3315 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 3316 /* this is only used for the first record */ 3317 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 3318 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 3319 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 3320 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 3321 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 3322 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 3323 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 3324 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 3325 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 3326 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 3327 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 3328 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 3329 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 3330 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 3331 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 3332 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 3333 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 3334 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 3335 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 3336 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 3337 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 3338 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 3339 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 3340 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 3341 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 3342 3343 3344 /***********************************/ 3345 /* MC_CMD_MEMCPY 3346 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data 3347 * embedded directly in the command. 3348 * 3349 * A common pattern is for a client to use generation counts to signal a dma 3350 * update of a datastructure. To facilitate this, this MCDI operation can 3351 * contain multiple requests which are executed in strict order. Requests take 3352 * the form of duplicating the entire MCDI request continuously (including the 3353 * requests record, which is ignored in all but the first structure) 3354 * 3355 * The source data can either come from a DMA from the host, or it can be 3356 * embedded within the request directly, thereby eliminating a DMA read. To 3357 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and 3358 * ADDR_LO=offset, and inserts the data at %offset from the start of the 3359 * payload. It's the callers responsibility to ensure that the embedded data 3360 * doesn't overlap the records. 3361 * 3362 * Returns: 0, EINVAL (invalid RID) 3363 */ 3364 #define MC_CMD_MEMCPY 0x31 3365 3366 /* MC_CMD_MEMCPY_IN msgrequest */ 3367 #define MC_CMD_MEMCPY_IN_LENMIN 32 3368 #define MC_CMD_MEMCPY_IN_LENMAX 224 3369 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 3370 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ 3371 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 3372 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 3373 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 3374 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 3375 3376 /* MC_CMD_MEMCPY_OUT msgresponse */ 3377 #define MC_CMD_MEMCPY_OUT_LEN 0 3378 3379 3380 /***********************************/ 3381 /* MC_CMD_WOL_FILTER_SET 3382 * Set a WoL filter. 3383 */ 3384 #define MC_CMD_WOL_FILTER_SET 0x32 3385 3386 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK 3387 3388 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 3389 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 3390 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 3391 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 3392 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 3393 /* A type value of 1 is unused. */ 3394 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 3395 /* enum: Magic */ 3396 #define MC_CMD_WOL_TYPE_MAGIC 0x0 3397 /* enum: MS Windows Magic */ 3398 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 3399 /* enum: IPv4 Syn */ 3400 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 3401 /* enum: IPv6 Syn */ 3402 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 3403 /* enum: Bitmap */ 3404 #define MC_CMD_WOL_TYPE_BITMAP 0x5 3405 /* enum: Link */ 3406 #define MC_CMD_WOL_TYPE_LINK 0x6 3407 /* enum: (Above this for future use) */ 3408 #define MC_CMD_WOL_TYPE_MAX 0x7 3409 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 3410 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 3411 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 3412 3413 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 3414 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 3415 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 3416 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 3417 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 3418 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 3419 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 3420 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 3421 3422 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 3423 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 3424 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 3425 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 3426 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 3427 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 3428 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 3429 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 3430 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 3431 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 3432 3433 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 3434 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 3435 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 3436 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 3437 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 3438 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 3439 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 3440 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 3441 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 3442 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 3443 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 3444 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 3445 3446 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 3447 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 3448 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 3449 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 3450 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 3451 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 3452 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 3453 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 3454 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 3455 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 3456 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 3457 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 3458 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 3459 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 3460 3461 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 3462 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 3463 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 3464 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 3465 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 3466 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 3467 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 3468 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 3469 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 3470 3471 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 3472 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 3473 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 3474 3475 3476 /***********************************/ 3477 /* MC_CMD_WOL_FILTER_REMOVE 3478 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS 3479 */ 3480 #define MC_CMD_WOL_FILTER_REMOVE 0x33 3481 3482 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK 3483 3484 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 3485 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 3486 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 3487 3488 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 3489 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 3490 3491 3492 /***********************************/ 3493 /* MC_CMD_WOL_FILTER_RESET 3494 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, 3495 * ENOSYS 3496 */ 3497 #define MC_CMD_WOL_FILTER_RESET 0x34 3498 3499 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK 3500 3501 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 3502 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 3503 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 3504 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 3505 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 3506 3507 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 3508 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 3509 3510 3511 /***********************************/ 3512 /* MC_CMD_SET_MCAST_HASH 3513 * Set the MCAST hash value without otherwise reconfiguring the MAC 3514 */ 3515 #define MC_CMD_SET_MCAST_HASH 0x35 3516 3517 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 3518 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 3519 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 3520 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 3521 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 3522 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 3523 3524 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 3525 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 3526 3527 3528 /***********************************/ 3529 /* MC_CMD_NVRAM_TYPES 3530 * Return bitfield indicating available types of virtual NVRAM partitions. 3531 * Locks required: none. Returns: 0 3532 */ 3533 #define MC_CMD_NVRAM_TYPES 0x36 3534 3535 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3536 3537 /* MC_CMD_NVRAM_TYPES_IN msgrequest */ 3538 #define MC_CMD_NVRAM_TYPES_IN_LEN 0 3539 3540 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 3541 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 3542 /* Bit mask of supported types. */ 3543 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 3544 /* enum: Disabled callisto. */ 3545 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 3546 /* enum: MC firmware. */ 3547 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 3548 /* enum: MC backup firmware. */ 3549 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 3550 /* enum: Static configuration Port0. */ 3551 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 3552 /* enum: Static configuration Port1. */ 3553 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 3554 /* enum: Dynamic configuration Port0. */ 3555 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 3556 /* enum: Dynamic configuration Port1. */ 3557 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 3558 /* enum: Expansion Rom. */ 3559 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 3560 /* enum: Expansion Rom Configuration Port0. */ 3561 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 3562 /* enum: Expansion Rom Configuration Port1. */ 3563 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 3564 /* enum: Phy Configuration Port0. */ 3565 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa 3566 /* enum: Phy Configuration Port1. */ 3567 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb 3568 /* enum: Log. */ 3569 #define MC_CMD_NVRAM_TYPE_LOG 0xc 3570 /* enum: FPGA image. */ 3571 #define MC_CMD_NVRAM_TYPE_FPGA 0xd 3572 /* enum: FPGA backup image */ 3573 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe 3574 /* enum: FC firmware. */ 3575 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf 3576 /* enum: FC backup firmware. */ 3577 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 3578 /* enum: CPLD image. */ 3579 #define MC_CMD_NVRAM_TYPE_CPLD 0x11 3580 /* enum: Licensing information. */ 3581 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 3582 /* enum: FC Log. */ 3583 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 3584 /* enum: Additional flash on FPGA. */ 3585 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 3586 3587 3588 /***********************************/ 3589 /* MC_CMD_NVRAM_INFO 3590 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, 3591 * EINVAL (bad type). 3592 */ 3593 #define MC_CMD_NVRAM_INFO 0x37 3594 3595 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3596 3597 /* MC_CMD_NVRAM_INFO_IN msgrequest */ 3598 #define MC_CMD_NVRAM_INFO_IN_LEN 4 3599 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 3600 /* Enum values, see field(s): */ 3601 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3602 3603 /* MC_CMD_NVRAM_INFO_OUT msgresponse */ 3604 #define MC_CMD_NVRAM_INFO_OUT_LEN 24 3605 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 3606 /* Enum values, see field(s): */ 3607 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3608 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 3609 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 3610 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 3611 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 3612 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 3613 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 3614 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 3615 #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 3616 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 3617 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 3618 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 3619 3620 /* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */ 3621 #define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28 3622 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0 3623 /* Enum values, see field(s): */ 3624 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3625 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4 3626 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8 3627 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12 3628 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0 3629 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1 3630 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1 3631 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1 3632 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7 3633 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1 3634 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16 3635 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20 3636 /* Writes must be multiples of this size. Added to support the MUM on Sorrento. 3637 */ 3638 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24 3639 3640 3641 /***********************************/ 3642 /* MC_CMD_NVRAM_UPDATE_START 3643 * Start a group of update operations on a virtual NVRAM partition. Locks 3644 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if 3645 * PHY_LOCK required and not held). 3646 */ 3647 #define MC_CMD_NVRAM_UPDATE_START 0x38 3648 3649 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3650 3651 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */ 3652 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 3653 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 3654 /* Enum values, see field(s): */ 3655 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3656 3657 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 3658 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 3659 3660 3661 /***********************************/ 3662 /* MC_CMD_NVRAM_READ 3663 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if 3664 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 3665 * PHY_LOCK required and not held) 3666 */ 3667 #define MC_CMD_NVRAM_READ 0x39 3668 3669 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3670 3671 /* MC_CMD_NVRAM_READ_IN msgrequest */ 3672 #define MC_CMD_NVRAM_READ_IN_LEN 12 3673 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 3674 /* Enum values, see field(s): */ 3675 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3676 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 3677 /* amount to read in bytes */ 3678 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 3679 3680 /* MC_CMD_NVRAM_READ_IN_V2 msgrequest */ 3681 #define MC_CMD_NVRAM_READ_IN_V2_LEN 16 3682 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0 3683 /* Enum values, see field(s): */ 3684 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3685 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4 3686 /* amount to read in bytes */ 3687 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8 3688 /* Optional control info. If a partition is stored with an A/B versioning 3689 * scheme (i.e. in more than one physical partition in NVRAM) the host can set 3690 * this to control which underlying physical partition is used to read data 3691 * from. This allows it to perform a read-modify-write-verify with the write 3692 * lock continuously held by calling NVRAM_UPDATE_START, reading the old 3693 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then 3694 * verifying by reading with MODE=TARGET_BACKUP. 3695 */ 3696 #define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12 3697 /* enum: Same as omitting MODE: caller sees data in current partition unless it 3698 * holds the write lock in which case it sees data in the partition it is 3699 * updating. 3700 */ 3701 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0 3702 /* enum: Read from the current partition of an A/B pair, even if holding the 3703 * write lock. 3704 */ 3705 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1 3706 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B 3707 * pair 3708 */ 3709 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2 3710 3711 /* MC_CMD_NVRAM_READ_OUT msgresponse */ 3712 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 3713 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 3714 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 3715 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 3716 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 3717 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 3718 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 3719 3720 3721 /***********************************/ 3722 /* MC_CMD_NVRAM_WRITE 3723 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if 3724 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 3725 * PHY_LOCK required and not held) 3726 */ 3727 #define MC_CMD_NVRAM_WRITE 0x3a 3728 3729 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3730 3731 /* MC_CMD_NVRAM_WRITE_IN msgrequest */ 3732 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 3733 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 3734 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 3735 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 3736 /* Enum values, see field(s): */ 3737 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3738 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 3739 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 3740 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 3741 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 3742 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 3743 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 3744 3745 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 3746 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 3747 3748 3749 /***********************************/ 3750 /* MC_CMD_NVRAM_ERASE 3751 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if 3752 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 3753 * PHY_LOCK required and not held) 3754 */ 3755 #define MC_CMD_NVRAM_ERASE 0x3b 3756 3757 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3758 3759 /* MC_CMD_NVRAM_ERASE_IN msgrequest */ 3760 #define MC_CMD_NVRAM_ERASE_IN_LEN 12 3761 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 3762 /* Enum values, see field(s): */ 3763 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3764 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 3765 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 3766 3767 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 3768 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 3769 3770 3771 /***********************************/ 3772 /* MC_CMD_NVRAM_UPDATE_FINISH 3773 * Finish a group of update operations on a virtual NVRAM partition. Locks 3774 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad 3775 * type/offset/length), EACCES (if PHY_LOCK required and not held) 3776 */ 3777 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 3778 3779 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3780 3781 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */ 3782 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 3783 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 3784 /* Enum values, see field(s): */ 3785 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3786 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 3787 3788 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */ 3789 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 3790 3791 3792 /***********************************/ 3793 /* MC_CMD_REBOOT 3794 * Reboot the MC. 3795 * 3796 * The AFTER_ASSERTION flag is intended to be used when the driver notices an 3797 * assertion failure (at which point it is expected to perform a complete tear 3798 * down and reinitialise), to allow both ports to reset the MC once in an 3799 * atomic fashion. 3800 * 3801 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, 3802 * which means that they will automatically reboot out of the assertion 3803 * handler, so this is in practise an optional operation. It is still 3804 * recommended that drivers execute this to support custom firmwares with 3805 * REBOOT_ON_ASSERT=0. 3806 * 3807 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, 3808 * DATALEN=0 3809 */ 3810 #define MC_CMD_REBOOT 0x3d 3811 3812 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3813 3814 /* MC_CMD_REBOOT_IN msgrequest */ 3815 #define MC_CMD_REBOOT_IN_LEN 4 3816 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 3817 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 3818 3819 /* MC_CMD_REBOOT_OUT msgresponse */ 3820 #define MC_CMD_REBOOT_OUT_LEN 0 3821 3822 3823 /***********************************/ 3824 /* MC_CMD_SCHEDINFO 3825 * Request scheduler info. Locks required: NONE. Returns: An array of 3826 * (timeslice,maximum overrun), one for each thread, in ascending order of 3827 * thread address. 3828 */ 3829 #define MC_CMD_SCHEDINFO 0x3e 3830 3831 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3832 3833 /* MC_CMD_SCHEDINFO_IN msgrequest */ 3834 #define MC_CMD_SCHEDINFO_IN_LEN 0 3835 3836 /* MC_CMD_SCHEDINFO_OUT msgresponse */ 3837 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 3838 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 3839 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 3840 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 3841 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 3842 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 3843 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 3844 3845 3846 /***********************************/ 3847 /* MC_CMD_REBOOT_MODE 3848 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot 3849 * mode to the specified value. Returns the old mode. 3850 */ 3851 #define MC_CMD_REBOOT_MODE 0x3f 3852 3853 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3854 3855 /* MC_CMD_REBOOT_MODE_IN msgrequest */ 3856 #define MC_CMD_REBOOT_MODE_IN_LEN 4 3857 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 3858 /* enum: Normal. */ 3859 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 3860 /* enum: Power-on Reset. */ 3861 #define MC_CMD_REBOOT_MODE_POR 0x2 3862 /* enum: Snapper. */ 3863 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 3864 /* enum: snapper fake POR */ 3865 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 3866 #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 3867 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 3868 3869 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 3870 #define MC_CMD_REBOOT_MODE_OUT_LEN 4 3871 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 3872 3873 3874 /***********************************/ 3875 /* MC_CMD_SENSOR_INFO 3876 * Returns information about every available sensor. 3877 * 3878 * Each sensor has a single (16bit) value, and a corresponding state. The 3879 * mapping between value and state is nominally determined by the MC, but may 3880 * be implemented using up to 2 ranges per sensor. 3881 * 3882 * This call returns a mask (32bit) of the sensors that are supported by this 3883 * platform, then an array of sensor information structures, in order of sensor 3884 * type (but without gaps for unimplemented sensors). Each structure defines 3885 * the ranges for the corresponding sensor. An unused range is indicated by 3886 * equal limit values. If one range is used, a value outside that range results 3887 * in STATE_FATAL. If two ranges are used, a value outside the second range 3888 * results in STATE_FATAL while a value outside the first and inside the second 3889 * range results in STATE_WARNING. 3890 * 3891 * Sensor masks and sensor information arrays are organised into pages. For 3892 * backward compatibility, older host software can only use sensors in page 0. 3893 * Bit 32 in the sensor mask was previously unused, and is no reserved for use 3894 * as the next page flag. 3895 * 3896 * If the request does not contain a PAGE value then firmware will only return 3897 * page 0 of sensor information, with bit 31 in the sensor mask cleared. 3898 * 3899 * If the request contains a PAGE value then firmware responds with the sensor 3900 * mask and sensor information array for that page of sensors. In this case bit 3901 * 31 in the mask is set if another page exists. 3902 * 3903 * Locks required: None Returns: 0 3904 */ 3905 #define MC_CMD_SENSOR_INFO 0x41 3906 3907 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3908 3909 /* MC_CMD_SENSOR_INFO_IN msgrequest */ 3910 #define MC_CMD_SENSOR_INFO_IN_LEN 0 3911 3912 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ 3913 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 3914 /* Which page of sensors to report. 3915 * 3916 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). 3917 * 3918 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. 3919 */ 3920 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 3921 3922 /* MC_CMD_SENSOR_INFO_OUT msgresponse */ 3923 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 3924 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 3925 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 3926 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 3927 /* enum: Controller temperature: degC */ 3928 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 3929 /* enum: Phy common temperature: degC */ 3930 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 3931 /* enum: Controller cooling: bool */ 3932 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 3933 /* enum: Phy 0 temperature: degC */ 3934 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 3935 /* enum: Phy 0 cooling: bool */ 3936 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 3937 /* enum: Phy 1 temperature: degC */ 3938 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 3939 /* enum: Phy 1 cooling: bool */ 3940 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 3941 /* enum: 1.0v power: mV */ 3942 #define MC_CMD_SENSOR_IN_1V0 0x7 3943 /* enum: 1.2v power: mV */ 3944 #define MC_CMD_SENSOR_IN_1V2 0x8 3945 /* enum: 1.8v power: mV */ 3946 #define MC_CMD_SENSOR_IN_1V8 0x9 3947 /* enum: 2.5v power: mV */ 3948 #define MC_CMD_SENSOR_IN_2V5 0xa 3949 /* enum: 3.3v power: mV */ 3950 #define MC_CMD_SENSOR_IN_3V3 0xb 3951 /* enum: 12v power: mV */ 3952 #define MC_CMD_SENSOR_IN_12V0 0xc 3953 /* enum: 1.2v analogue power: mV */ 3954 #define MC_CMD_SENSOR_IN_1V2A 0xd 3955 /* enum: reference voltage: mV */ 3956 #define MC_CMD_SENSOR_IN_VREF 0xe 3957 /* enum: AOE FPGA power: mV */ 3958 #define MC_CMD_SENSOR_OUT_VAOE 0xf 3959 /* enum: AOE FPGA temperature: degC */ 3960 #define MC_CMD_SENSOR_AOE_TEMP 0x10 3961 /* enum: AOE FPGA PSU temperature: degC */ 3962 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 3963 /* enum: AOE PSU temperature: degC */ 3964 #define MC_CMD_SENSOR_PSU_TEMP 0x12 3965 /* enum: Fan 0 speed: RPM */ 3966 #define MC_CMD_SENSOR_FAN_0 0x13 3967 /* enum: Fan 1 speed: RPM */ 3968 #define MC_CMD_SENSOR_FAN_1 0x14 3969 /* enum: Fan 2 speed: RPM */ 3970 #define MC_CMD_SENSOR_FAN_2 0x15 3971 /* enum: Fan 3 speed: RPM */ 3972 #define MC_CMD_SENSOR_FAN_3 0x16 3973 /* enum: Fan 4 speed: RPM */ 3974 #define MC_CMD_SENSOR_FAN_4 0x17 3975 /* enum: AOE FPGA input power: mV */ 3976 #define MC_CMD_SENSOR_IN_VAOE 0x18 3977 /* enum: AOE FPGA current: mA */ 3978 #define MC_CMD_SENSOR_OUT_IAOE 0x19 3979 /* enum: AOE FPGA input current: mA */ 3980 #define MC_CMD_SENSOR_IN_IAOE 0x1a 3981 /* enum: NIC power consumption: W */ 3982 #define MC_CMD_SENSOR_NIC_POWER 0x1b 3983 /* enum: 0.9v power voltage: mV */ 3984 #define MC_CMD_SENSOR_IN_0V9 0x1c 3985 /* enum: 0.9v power current: mA */ 3986 #define MC_CMD_SENSOR_IN_I0V9 0x1d 3987 /* enum: 1.2v power current: mA */ 3988 #define MC_CMD_SENSOR_IN_I1V2 0x1e 3989 /* enum: Not a sensor: reserved for the next page flag */ 3990 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f 3991 /* enum: 0.9v power voltage (at ADC): mV */ 3992 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 3993 /* enum: Controller temperature 2: degC */ 3994 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 3995 /* enum: Voltage regulator internal temperature: degC */ 3996 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 3997 /* enum: 0.9V voltage regulator temperature: degC */ 3998 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 3999 /* enum: 1.2V voltage regulator temperature: degC */ 4000 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 4001 /* enum: controller internal temperature sensor voltage (internal ADC): mV */ 4002 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 4003 /* enum: controller internal temperature (internal ADC): degC */ 4004 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 4005 /* enum: controller internal temperature sensor voltage (external ADC): mV */ 4006 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 4007 /* enum: controller internal temperature (external ADC): degC */ 4008 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 4009 /* enum: ambient temperature: degC */ 4010 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 4011 /* enum: air flow: bool */ 4012 #define MC_CMD_SENSOR_AIRFLOW 0x2a 4013 /* enum: voltage between VSS08D and VSS08D at CSR: mV */ 4014 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b 4015 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ 4016 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c 4017 /* enum: Hotpoint temperature: degC */ 4018 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d 4019 /* enum: Port 0 PHY power switch over-current: bool */ 4020 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e 4021 /* enum: Port 1 PHY power switch over-current: bool */ 4022 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f 4023 /* enum: Mop-up microcontroller reference voltage (millivolts) */ 4024 #define MC_CMD_SENSOR_MUM_VCC 0x30 4025 /* enum: 0.9v power phase A voltage: mV */ 4026 #define MC_CMD_SENSOR_IN_0V9_A 0x31 4027 /* enum: 0.9v power phase A current: mA */ 4028 #define MC_CMD_SENSOR_IN_I0V9_A 0x32 4029 /* enum: 0.9V voltage regulator phase A temperature: degC */ 4030 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33 4031 /* enum: 0.9v power phase B voltage: mV */ 4032 #define MC_CMD_SENSOR_IN_0V9_B 0x34 4033 /* enum: 0.9v power phase B current: mA */ 4034 #define MC_CMD_SENSOR_IN_I0V9_B 0x35 4035 /* enum: 0.9V voltage regulator phase B temperature: degC */ 4036 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36 4037 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */ 4038 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37 4039 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */ 4040 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38 4041 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */ 4042 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 4043 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */ 4044 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a 4045 /* enum: CCOM RTS temperature: degC */ 4046 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b 4047 /* enum: Not a sensor: reserved for the next page flag */ 4048 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f 4049 /* enum: controller internal temperature sensor voltage on master core 4050 * (internal ADC): mV 4051 */ 4052 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40 4053 /* enum: controller internal temperature on master core (internal ADC): degC */ 4054 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41 4055 /* enum: controller internal temperature sensor voltage on master core 4056 * (external ADC): mV 4057 */ 4058 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42 4059 /* enum: controller internal temperature on master core (external ADC): degC */ 4060 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43 4061 /* enum: controller internal temperature on slave core sensor voltage (internal 4062 * ADC): mV 4063 */ 4064 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44 4065 /* enum: controller internal temperature on slave core (internal ADC): degC */ 4066 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45 4067 /* enum: controller internal temperature on slave core sensor voltage (external 4068 * ADC): mV 4069 */ 4070 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46 4071 /* enum: controller internal temperature on slave core (external ADC): degC */ 4072 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47 4073 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */ 4074 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49 4075 /* enum: Temperature of SODIMM 0 (if installed): degC */ 4076 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a 4077 /* enum: Temperature of SODIMM 1 (if installed): degC */ 4078 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b 4079 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */ 4080 #define MC_CMD_SENSOR_PHY0_VCC 0x4c 4081 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ 4082 #define MC_CMD_SENSOR_PHY1_VCC 0x4d 4083 /* enum: Controller die temperature (TDIODE): degC */ 4084 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e 4085 /* enum: Board temperature (front): degC */ 4086 #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f 4087 /* enum: Board temperature (back): degC */ 4088 #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50 4089 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 4090 #define MC_CMD_SENSOR_ENTRY_OFST 4 4091 #define MC_CMD_SENSOR_ENTRY_LEN 8 4092 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 4093 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 4094 #define MC_CMD_SENSOR_ENTRY_MINNUM 0 4095 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 4096 4097 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ 4098 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 4099 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 4100 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) 4101 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 4102 /* Enum values, see field(s): */ 4103 /* MC_CMD_SENSOR_INFO_OUT */ 4104 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 4105 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 4106 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 4107 /* MC_CMD_SENSOR_ENTRY_OFST 4 */ 4108 /* MC_CMD_SENSOR_ENTRY_LEN 8 */ 4109 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ 4110 /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ 4111 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ 4112 /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ 4113 4114 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 4115 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 4116 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 4117 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 4118 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 4119 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 4120 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 4121 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 4122 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 4123 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 4124 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 4125 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 4126 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 4127 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 4128 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 4129 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 4130 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 4131 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 4132 4133 4134 /***********************************/ 4135 /* MC_CMD_READ_SENSORS 4136 * Returns the current reading from each sensor. DMAs an array of sensor 4137 * readings, in order of sensor type (but without gaps for unimplemented 4138 * sensors), into host memory. Each array element is a 4139 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. 4140 * 4141 * If the request does not contain the LENGTH field then only sensors 0 to 30 4142 * are reported, to avoid DMA buffer overflow in older host software. If the 4143 * sensor reading require more space than the LENGTH allows, then return 4144 * EINVAL. 4145 * 4146 * The MC will send a SENSOREVT event every time any sensor changes state. The 4147 * driver is responsible for ensuring that it doesn't miss any events. The 4148 * board will function normally if all sensors are in STATE_OK or 4149 * STATE_WARNING. Otherwise the board should not be expected to function. 4150 */ 4151 #define MC_CMD_READ_SENSORS 0x42 4152 4153 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4154 4155 /* MC_CMD_READ_SENSORS_IN msgrequest */ 4156 #define MC_CMD_READ_SENSORS_IN_LEN 8 4157 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 4158 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 4159 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 4160 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 4161 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 4162 4163 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ 4164 #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 4165 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 4166 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 4167 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 4168 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 4169 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 4170 /* Size in bytes of host buffer. */ 4171 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 4172 4173 /* MC_CMD_READ_SENSORS_OUT msgresponse */ 4174 #define MC_CMD_READ_SENSORS_OUT_LEN 0 4175 4176 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ 4177 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 4178 4179 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 4180 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 4181 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 4182 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 4183 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 4184 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 4185 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 4186 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 4187 /* enum: Ok. */ 4188 #define MC_CMD_SENSOR_STATE_OK 0x0 4189 /* enum: Breached warning threshold. */ 4190 #define MC_CMD_SENSOR_STATE_WARNING 0x1 4191 /* enum: Breached fatal threshold. */ 4192 #define MC_CMD_SENSOR_STATE_FATAL 0x2 4193 /* enum: Fault with sensor. */ 4194 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 4195 /* enum: Sensor is working but does not currently have a reading. */ 4196 #define MC_CMD_SENSOR_STATE_NO_READING 0x4 4197 /* enum: Sensor initialisation failed. */ 4198 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5 4199 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 4200 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 4201 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 4202 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 4203 /* Enum values, see field(s): */ 4204 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 4205 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 4206 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 4207 4208 4209 /***********************************/ 4210 /* MC_CMD_GET_PHY_STATE 4211 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot 4212 * (e.g. due to missing or corrupted firmware). Locks required: None. Return 4213 * code: 0 4214 */ 4215 #define MC_CMD_GET_PHY_STATE 0x43 4216 4217 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4218 4219 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 4220 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 4221 4222 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 4223 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 4224 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 4225 /* enum: Ok. */ 4226 #define MC_CMD_PHY_STATE_OK 0x1 4227 /* enum: Faulty. */ 4228 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 4229 4230 4231 /***********************************/ 4232 /* MC_CMD_SETUP_8021QBB 4233 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 4234 * disable 802.Qbb for a given priority. 4235 */ 4236 #define MC_CMD_SETUP_8021QBB 0x44 4237 4238 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 4239 #define MC_CMD_SETUP_8021QBB_IN_LEN 32 4240 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 4241 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 4242 4243 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 4244 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 4245 4246 4247 /***********************************/ 4248 /* MC_CMD_WOL_FILTER_GET 4249 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS 4250 */ 4251 #define MC_CMD_WOL_FILTER_GET 0x45 4252 4253 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK 4254 4255 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 4256 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 4257 4258 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 4259 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 4260 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 4261 4262 4263 /***********************************/ 4264 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 4265 * Add a protocol offload to NIC for lights-out state. Locks required: None. 4266 * Returns: 0, ENOSYS 4267 */ 4268 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 4269 4270 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK 4271 4272 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 4273 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 4274 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 4275 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 4276 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 4277 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 4278 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 4279 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 4280 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 4281 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 4282 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 4283 4284 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 4285 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 4286 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 4287 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 4288 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 4289 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 4290 4291 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 4292 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 4293 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 4294 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 4295 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 4296 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 4297 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 4298 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 4299 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 4300 4301 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 4302 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 4303 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 4304 4305 4306 /***********************************/ 4307 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 4308 * Remove a protocol offload from NIC for lights-out state. Locks required: 4309 * None. Returns: 0, ENOSYS 4310 */ 4311 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 4312 4313 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK 4314 4315 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 4316 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 4317 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 4318 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 4319 4320 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 4321 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 4322 4323 4324 /***********************************/ 4325 /* MC_CMD_MAC_RESET_RESTORE 4326 * Restore MAC after block reset. Locks required: None. Returns: 0. 4327 */ 4328 #define MC_CMD_MAC_RESET_RESTORE 0x48 4329 4330 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 4331 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 4332 4333 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 4334 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 4335 4336 4337 /***********************************/ 4338 /* MC_CMD_TESTASSERT 4339 * Deliberately trigger an assert-detonation in the firmware for testing 4340 * purposes (i.e. to allow tests that the driver copes gracefully). Locks 4341 * required: None Returns: 0 4342 */ 4343 #define MC_CMD_TESTASSERT 0x49 4344 4345 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4346 4347 /* MC_CMD_TESTASSERT_IN msgrequest */ 4348 #define MC_CMD_TESTASSERT_IN_LEN 0 4349 4350 /* MC_CMD_TESTASSERT_OUT msgresponse */ 4351 #define MC_CMD_TESTASSERT_OUT_LEN 0 4352 4353 4354 /***********************************/ 4355 /* MC_CMD_WORKAROUND 4356 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't 4357 * understand the given workaround number - which should not be treated as a 4358 * hard error by client code. This op does not imply any semantics about each 4359 * workaround, that's between the driver and the mcfw on a per-workaround 4360 * basis. Locks required: None. Returns: 0, EINVAL . 4361 */ 4362 #define MC_CMD_WORKAROUND 0x4a 4363 4364 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4365 4366 /* MC_CMD_WORKAROUND_IN msgrequest */ 4367 #define MC_CMD_WORKAROUND_IN_LEN 8 4368 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */ 4369 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 4370 /* enum: Bug 17230 work around. */ 4371 #define MC_CMD_WORKAROUND_BUG17230 0x1 4372 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 4373 #define MC_CMD_WORKAROUND_BUG35388 0x2 4374 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 4375 #define MC_CMD_WORKAROUND_BUG35017 0x3 4376 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 4377 #define MC_CMD_WORKAROUND_BUG41750 0x4 4378 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 4379 * - before adding code that queries this workaround, remember that there's 4380 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 4381 * and will hence (incorrectly) report that the bug doesn't exist. 4382 */ 4383 #define MC_CMD_WORKAROUND_BUG42008 0x5 4384 /* enum: Bug 26807 features present in firmware (multicast filter chaining) 4385 * This feature cannot be turned on/off while there are any filters already 4386 * present. The behaviour in such case depends on the acting client's privilege 4387 * level. If the client has the admin privilege, then all functions that have 4388 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise 4389 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT. 4390 */ 4391 #define MC_CMD_WORKAROUND_BUG26807 0x6 4392 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable 4393 * the workaround 4394 */ 4395 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 4396 4397 /* MC_CMD_WORKAROUND_OUT msgresponse */ 4398 #define MC_CMD_WORKAROUND_OUT_LEN 0 4399 4400 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used 4401 * when (TYPE == MC_CMD_WORKAROUND_BUG26807) 4402 */ 4403 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4 4404 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0 4405 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 4406 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1 4407 4408 4409 /***********************************/ 4410 /* MC_CMD_GET_PHY_MEDIA_INFO 4411 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for 4412 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG 4413 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the 4414 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 4415 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. 4416 * Anything else: currently undefined. Locks required: None. Return code: 0. 4417 */ 4418 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 4419 4420 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4421 4422 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 4423 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 4424 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 4425 4426 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 4427 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 4428 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 4429 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 4430 /* in bytes */ 4431 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 4432 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 4433 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 4434 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 4435 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 4436 4437 4438 /***********************************/ 4439 /* MC_CMD_NVRAM_TEST 4440 * Test a particular NVRAM partition for valid contents (where "valid" depends 4441 * on the type of partition). 4442 */ 4443 #define MC_CMD_NVRAM_TEST 0x4c 4444 4445 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4446 4447 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 4448 #define MC_CMD_NVRAM_TEST_IN_LEN 4 4449 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 4450 /* Enum values, see field(s): */ 4451 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4452 4453 /* MC_CMD_NVRAM_TEST_OUT msgresponse */ 4454 #define MC_CMD_NVRAM_TEST_OUT_LEN 4 4455 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 4456 /* enum: Passed. */ 4457 #define MC_CMD_NVRAM_TEST_PASS 0x0 4458 /* enum: Failed. */ 4459 #define MC_CMD_NVRAM_TEST_FAIL 0x1 4460 /* enum: Not supported. */ 4461 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 4462 4463 4464 /***********************************/ 4465 /* MC_CMD_MRSFP_TWEAK 4466 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. 4467 * I2C I/O expander bits are always read; if equaliser parameters are supplied, 4468 * they are configured first. Locks required: None. Return code: 0, EINVAL. 4469 */ 4470 #define MC_CMD_MRSFP_TWEAK 0x4d 4471 4472 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 4473 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 4474 /* 0-6 low->high de-emph. */ 4475 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 4476 /* 0-8 low->high ref.V */ 4477 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 4478 /* 0-8 0-8 low->high boost */ 4479 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 4480 /* 0-8 low->high ref.V */ 4481 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 4482 4483 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 4484 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 4485 4486 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 4487 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 4488 /* input bits */ 4489 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 4490 /* output bits */ 4491 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 4492 /* direction */ 4493 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 4494 /* enum: Out. */ 4495 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 4496 /* enum: In. */ 4497 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 4498 4499 4500 /***********************************/ 4501 /* MC_CMD_SENSOR_SET_LIMS 4502 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: 4503 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out 4504 * of range. 4505 */ 4506 #define MC_CMD_SENSOR_SET_LIMS 0x4e 4507 4508 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4509 4510 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 4511 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 4512 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 4513 /* Enum values, see field(s): */ 4514 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 4515 /* interpretation is is sensor-specific. */ 4516 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 4517 /* interpretation is is sensor-specific. */ 4518 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 4519 /* interpretation is is sensor-specific. */ 4520 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 4521 /* interpretation is is sensor-specific. */ 4522 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 4523 4524 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 4525 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 4526 4527 4528 /***********************************/ 4529 /* MC_CMD_GET_RESOURCE_LIMITS 4530 */ 4531 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 4532 4533 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 4534 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 4535 4536 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 4537 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 4538 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 4539 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 4540 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 4541 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 4542 4543 4544 /***********************************/ 4545 /* MC_CMD_NVRAM_PARTITIONS 4546 * Reads the list of available virtual NVRAM partition types. Locks required: 4547 * none. Returns: 0, EINVAL (bad type). 4548 */ 4549 #define MC_CMD_NVRAM_PARTITIONS 0x51 4550 4551 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4552 4553 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ 4554 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 4555 4556 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ 4557 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 4558 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 4559 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) 4560 /* total number of partitions */ 4561 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 4562 /* type ID code for each of NUM_PARTITIONS partitions */ 4563 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 4564 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 4565 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 4566 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 4567 4568 4569 /***********************************/ 4570 /* MC_CMD_NVRAM_METADATA 4571 * Reads soft metadata for a virtual NVRAM partition type. Locks required: 4572 * none. Returns: 0, EINVAL (bad type). 4573 */ 4574 #define MC_CMD_NVRAM_METADATA 0x52 4575 4576 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4577 4578 /* MC_CMD_NVRAM_METADATA_IN msgrequest */ 4579 #define MC_CMD_NVRAM_METADATA_IN_LEN 4 4580 /* Partition type ID code */ 4581 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 4582 4583 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */ 4584 #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 4585 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 4586 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) 4587 /* Partition type ID code */ 4588 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 4589 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 4590 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 4591 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 4592 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 4593 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 4594 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 4595 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 4596 /* Subtype ID code for content of this partition */ 4597 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 4598 /* 1st component of W.X.Y.Z version number for content of this partition */ 4599 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 4600 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 4601 /* 2nd component of W.X.Y.Z version number for content of this partition */ 4602 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 4603 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 4604 /* 3rd component of W.X.Y.Z version number for content of this partition */ 4605 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 4606 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 4607 /* 4th component of W.X.Y.Z version number for content of this partition */ 4608 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 4609 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 4610 /* Zero-terminated string describing the content of this partition */ 4611 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 4612 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 4613 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 4614 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 4615 4616 4617 /***********************************/ 4618 /* MC_CMD_GET_MAC_ADDRESSES 4619 * Returns the base MAC, count and stride for the requesting function 4620 */ 4621 #define MC_CMD_GET_MAC_ADDRESSES 0x55 4622 4623 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4624 4625 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ 4626 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 4627 4628 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ 4629 #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 4630 /* Base MAC address */ 4631 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 4632 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 4633 /* Padding */ 4634 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 4635 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 4636 /* Number of allocated MAC addresses */ 4637 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 4638 /* Spacing of allocated MAC addresses */ 4639 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 4640 4641 4642 /***********************************/ 4643 /* MC_CMD_CLP 4644 * Perform a CLP related operation 4645 */ 4646 #define MC_CMD_CLP 0x56 4647 4648 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4649 4650 /* MC_CMD_CLP_IN msgrequest */ 4651 #define MC_CMD_CLP_IN_LEN 4 4652 /* Sub operation */ 4653 #define MC_CMD_CLP_IN_OP_OFST 0 4654 /* enum: Return to factory default settings */ 4655 #define MC_CMD_CLP_OP_DEFAULT 0x1 4656 /* enum: Set MAC address */ 4657 #define MC_CMD_CLP_OP_SET_MAC 0x2 4658 /* enum: Get MAC address */ 4659 #define MC_CMD_CLP_OP_GET_MAC 0x3 4660 /* enum: Set UEFI/GPXE boot mode */ 4661 #define MC_CMD_CLP_OP_SET_BOOT 0x4 4662 /* enum: Get UEFI/GPXE boot mode */ 4663 #define MC_CMD_CLP_OP_GET_BOOT 0x5 4664 4665 /* MC_CMD_CLP_OUT msgresponse */ 4666 #define MC_CMD_CLP_OUT_LEN 0 4667 4668 /* MC_CMD_CLP_IN_DEFAULT msgrequest */ 4669 #define MC_CMD_CLP_IN_DEFAULT_LEN 4 4670 /* MC_CMD_CLP_IN_OP_OFST 0 */ 4671 4672 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */ 4673 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0 4674 4675 /* MC_CMD_CLP_IN_SET_MAC msgrequest */ 4676 #define MC_CMD_CLP_IN_SET_MAC_LEN 12 4677 /* MC_CMD_CLP_IN_OP_OFST 0 */ 4678 /* MAC address assigned to port */ 4679 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 4680 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 4681 /* Padding */ 4682 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 4683 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 4684 4685 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */ 4686 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0 4687 4688 /* MC_CMD_CLP_IN_GET_MAC msgrequest */ 4689 #define MC_CMD_CLP_IN_GET_MAC_LEN 4 4690 /* MC_CMD_CLP_IN_OP_OFST 0 */ 4691 4692 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */ 4693 #define MC_CMD_CLP_OUT_GET_MAC_LEN 8 4694 /* MAC address assigned to port */ 4695 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 4696 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 4697 /* Padding */ 4698 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 4699 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 4700 4701 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */ 4702 #define MC_CMD_CLP_IN_SET_BOOT_LEN 5 4703 /* MC_CMD_CLP_IN_OP_OFST 0 */ 4704 /* Boot flag */ 4705 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 4706 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 4707 4708 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ 4709 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 4710 4711 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */ 4712 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4 4713 /* MC_CMD_CLP_IN_OP_OFST 0 */ 4714 4715 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ 4716 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 4717 /* Boot flag */ 4718 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 4719 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 4720 /* Padding */ 4721 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 4722 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 4723 4724 4725 /***********************************/ 4726 /* MC_CMD_MUM 4727 * Perform a MUM operation 4728 */ 4729 #define MC_CMD_MUM 0x57 4730 4731 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4732 4733 /* MC_CMD_MUM_IN msgrequest */ 4734 #define MC_CMD_MUM_IN_LEN 4 4735 #define MC_CMD_MUM_IN_OP_HDR_OFST 0 4736 #define MC_CMD_MUM_IN_OP_LBN 0 4737 #define MC_CMD_MUM_IN_OP_WIDTH 8 4738 /* enum: NULL MCDI command to MUM */ 4739 #define MC_CMD_MUM_OP_NULL 0x1 4740 /* enum: Get MUM version */ 4741 #define MC_CMD_MUM_OP_GET_VERSION 0x2 4742 /* enum: Issue raw I2C command to MUM */ 4743 #define MC_CMD_MUM_OP_RAW_CMD 0x3 4744 /* enum: Read from registers on devices connected to MUM. */ 4745 #define MC_CMD_MUM_OP_READ 0x4 4746 /* enum: Write to registers on devices connected to MUM. */ 4747 #define MC_CMD_MUM_OP_WRITE 0x5 4748 /* enum: Control UART logging. */ 4749 #define MC_CMD_MUM_OP_LOG 0x6 4750 /* enum: Operations on MUM GPIO lines */ 4751 #define MC_CMD_MUM_OP_GPIO 0x7 4752 /* enum: Get sensor readings from MUM */ 4753 #define MC_CMD_MUM_OP_READ_SENSORS 0x8 4754 /* enum: Initiate clock programming on the MUM */ 4755 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9 4756 /* enum: Initiate FPGA load from flash on the MUM */ 4757 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa 4758 /* enum: Request sensor reading from MUM ADC resulting from earlier request via 4759 * MUM ATB 4760 */ 4761 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb 4762 /* enum: Send commands relating to the QSFP ports via the MUM for PHY 4763 * operations 4764 */ 4765 #define MC_CMD_MUM_OP_QSFP 0xc 4766 /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage 4767 * level) from MUM 4768 */ 4769 #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd 4770 4771 /* MC_CMD_MUM_IN_NULL msgrequest */ 4772 #define MC_CMD_MUM_IN_NULL_LEN 4 4773 /* MUM cmd header */ 4774 #define MC_CMD_MUM_IN_CMD_OFST 0 4775 4776 /* MC_CMD_MUM_IN_GET_VERSION msgrequest */ 4777 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4 4778 /* MUM cmd header */ 4779 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4780 4781 /* MC_CMD_MUM_IN_READ msgrequest */ 4782 #define MC_CMD_MUM_IN_READ_LEN 16 4783 /* MUM cmd header */ 4784 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4785 /* ID of (device connected to MUM) to read from registers of */ 4786 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4 4787 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 4788 #define MC_CMD_MUM_DEV_HITTITE 0x1 4789 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */ 4790 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2 4791 /* 32-bit address to read from */ 4792 #define MC_CMD_MUM_IN_READ_ADDR_OFST 8 4793 /* Number of words to read. */ 4794 #define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12 4795 4796 /* MC_CMD_MUM_IN_WRITE msgrequest */ 4797 #define MC_CMD_MUM_IN_WRITE_LENMIN 16 4798 #define MC_CMD_MUM_IN_WRITE_LENMAX 252 4799 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) 4800 /* MUM cmd header */ 4801 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4802 /* ID of (device connected to MUM) to write to registers of */ 4803 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4 4804 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 4805 /* MC_CMD_MUM_DEV_HITTITE 0x1 */ 4806 /* 32-bit address to write to */ 4807 #define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8 4808 /* Words to write */ 4809 #define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12 4810 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4 4811 #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1 4812 #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60 4813 4814 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */ 4815 #define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17 4816 #define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252 4817 #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) 4818 /* MUM cmd header */ 4819 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4820 /* MUM I2C cmd code */ 4821 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4 4822 /* Number of bytes to write */ 4823 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8 4824 /* Number of bytes to read */ 4825 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12 4826 /* Bytes to write */ 4827 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16 4828 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1 4829 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1 4830 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236 4831 4832 /* MC_CMD_MUM_IN_LOG msgrequest */ 4833 #define MC_CMD_MUM_IN_LOG_LEN 8 4834 /* MUM cmd header */ 4835 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4836 #define MC_CMD_MUM_IN_LOG_OP_OFST 4 4837 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */ 4838 4839 /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */ 4840 #define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12 4841 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4842 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */ 4843 /* Enable/disable debug output to UART */ 4844 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8 4845 4846 /* MC_CMD_MUM_IN_GPIO msgrequest */ 4847 #define MC_CMD_MUM_IN_GPIO_LEN 8 4848 /* MUM cmd header */ 4849 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4850 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4 4851 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0 4852 #define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8 4853 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */ 4854 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */ 4855 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */ 4856 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */ 4857 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */ 4858 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */ 4859 4860 /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */ 4861 #define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8 4862 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4863 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4 4864 4865 /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ 4866 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 4867 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4868 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 4869 /* The first 32-bit word to be written to the GPIO OUT register. */ 4870 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 4871 /* The second 32-bit word to be written to the GPIO OUT register. */ 4872 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 4873 4874 /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */ 4875 #define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8 4876 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4877 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4 4878 4879 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ 4880 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 4881 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4882 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 4883 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ 4884 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 4885 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ 4886 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 4887 4888 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */ 4889 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8 4890 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4891 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4 4892 4893 /* MC_CMD_MUM_IN_GPIO_OP msgrequest */ 4894 #define MC_CMD_MUM_IN_GPIO_OP_LEN 8 4895 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4896 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4 4897 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8 4898 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8 4899 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */ 4900 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */ 4901 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */ 4902 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */ 4903 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16 4904 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8 4905 4906 /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */ 4907 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8 4908 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4909 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4 4910 4911 /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */ 4912 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8 4913 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4914 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4 4915 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24 4916 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8 4917 4918 /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */ 4919 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8 4920 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4921 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4 4922 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24 4923 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8 4924 4925 /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */ 4926 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8 4927 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4928 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4 4929 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24 4930 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8 4931 4932 /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */ 4933 #define MC_CMD_MUM_IN_READ_SENSORS_LEN 8 4934 /* MUM cmd header */ 4935 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4936 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4 4937 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0 4938 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8 4939 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8 4940 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8 4941 4942 /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */ 4943 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12 4944 /* MUM cmd header */ 4945 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4946 /* Bit-mask of clocks to be programmed */ 4947 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4 4948 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */ 4949 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */ 4950 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */ 4951 /* Control flags for clock programming */ 4952 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 4953 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 4954 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 4955 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1 4956 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1 4957 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2 4958 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1 4959 4960 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ 4961 #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 4962 /* MUM cmd header */ 4963 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4964 /* Enable/Disable FPGA config from flash */ 4965 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4 4966 4967 /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */ 4968 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4 4969 /* MUM cmd header */ 4970 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4971 4972 /* MC_CMD_MUM_IN_QSFP msgrequest */ 4973 #define MC_CMD_MUM_IN_QSFP_LEN 12 4974 /* MUM cmd header */ 4975 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4976 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4 4977 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0 4978 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4 4979 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */ 4980 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */ 4981 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */ 4982 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */ 4983 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */ 4984 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */ 4985 #define MC_CMD_MUM_IN_QSFP_IDX_OFST 8 4986 4987 /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */ 4988 #define MC_CMD_MUM_IN_QSFP_INIT_LEN 16 4989 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4990 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4 4991 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8 4992 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12 4993 4994 /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */ 4995 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24 4996 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4997 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4 4998 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8 4999 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12 5000 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16 5001 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20 5002 5003 /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */ 5004 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12 5005 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5006 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4 5007 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8 5008 5009 /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */ 5010 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16 5011 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5012 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4 5013 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8 5014 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12 5015 5016 /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */ 5017 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12 5018 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5019 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4 5020 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8 5021 5022 /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */ 5023 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12 5024 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5025 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 5026 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 5027 5028 /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */ 5029 #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4 5030 /* MUM cmd header */ 5031 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5032 5033 /* MC_CMD_MUM_OUT msgresponse */ 5034 #define MC_CMD_MUM_OUT_LEN 0 5035 5036 /* MC_CMD_MUM_OUT_NULL msgresponse */ 5037 #define MC_CMD_MUM_OUT_NULL_LEN 0 5038 5039 /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */ 5040 #define MC_CMD_MUM_OUT_GET_VERSION_LEN 12 5041 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0 5042 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4 5043 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8 5044 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4 5045 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8 5046 5047 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */ 5048 #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1 5049 #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252 5050 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) 5051 /* returned data */ 5052 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0 5053 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1 5054 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1 5055 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252 5056 5057 /* MC_CMD_MUM_OUT_READ msgresponse */ 5058 #define MC_CMD_MUM_OUT_READ_LENMIN 4 5059 #define MC_CMD_MUM_OUT_READ_LENMAX 252 5060 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) 5061 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0 5062 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4 5063 #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1 5064 #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63 5065 5066 /* MC_CMD_MUM_OUT_WRITE msgresponse */ 5067 #define MC_CMD_MUM_OUT_WRITE_LEN 0 5068 5069 /* MC_CMD_MUM_OUT_LOG msgresponse */ 5070 #define MC_CMD_MUM_OUT_LOG_LEN 0 5071 5072 /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */ 5073 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0 5074 5075 /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ 5076 #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 5077 /* The first 32-bit word read from the GPIO IN register. */ 5078 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 5079 /* The second 32-bit word read from the GPIO IN register. */ 5080 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 5081 5082 /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */ 5083 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0 5084 5085 /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ 5086 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 5087 /* The first 32-bit word read from the GPIO OUT register. */ 5088 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 5089 /* The second 32-bit word read from the GPIO OUT register. */ 5090 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 5091 5092 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */ 5093 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0 5094 5095 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */ 5096 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8 5097 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0 5098 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4 5099 5100 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */ 5101 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4 5102 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0 5103 5104 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */ 5105 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0 5106 5107 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */ 5108 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0 5109 5110 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */ 5111 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0 5112 5113 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */ 5114 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4 5115 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252 5116 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) 5117 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0 5118 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4 5119 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1 5120 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63 5121 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0 5122 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16 5123 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16 5124 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8 5125 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24 5126 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8 5127 5128 /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */ 5129 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4 5130 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0 5131 5132 /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */ 5133 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0 5134 5135 /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */ 5136 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4 5137 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0 5138 5139 /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */ 5140 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0 5141 5142 /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */ 5143 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8 5144 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0 5145 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4 5146 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0 5147 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1 5148 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1 5149 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1 5150 5151 /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */ 5152 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4 5153 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0 5154 5155 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */ 5156 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5 5157 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252 5158 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) 5159 /* in bytes */ 5160 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0 5161 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4 5162 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1 5163 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1 5164 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248 5165 5166 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */ 5167 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8 5168 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0 5169 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4 5170 5171 /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */ 5172 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 5173 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 5174 5175 /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */ 5176 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24 5177 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248 5178 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num)) 5179 /* Discrete (soldered) DDR resistor strap info */ 5180 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0 5181 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0 5182 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16 5183 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16 5184 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16 5185 /* Number of SODIMM info records */ 5186 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4 5187 /* Array of SODIMM info records */ 5188 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8 5189 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8 5190 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8 5191 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12 5192 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2 5193 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30 5194 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0 5195 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8 5196 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */ 5197 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0 5198 /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */ 5199 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1 5200 /* enum: Total number of SODIMM banks */ 5201 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2 5202 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8 5203 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8 5204 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16 5205 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4 5206 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20 5207 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4 5208 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */ 5209 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */ 5210 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */ 5211 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */ 5212 /* enum: Values 5-15 are reserved for future usage */ 5213 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4 5214 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24 5215 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8 5216 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32 5217 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16 5218 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48 5219 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4 5220 /* enum: No module present */ 5221 #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0 5222 /* enum: Module present supported and powered on */ 5223 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1 5224 /* enum: Module present but bad type */ 5225 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2 5226 /* enum: Module present but incompatible voltage */ 5227 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3 5228 /* enum: Module present but unknown SPD */ 5229 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4 5230 /* enum: Module present but slot cannot support it */ 5231 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5 5232 /* enum: Modules may or may not be present, but cannot establish contact by I2C 5233 */ 5234 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6 5235 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52 5236 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12 5237 5238 /* MC_CMD_RESOURCE_SPECIFIER enum */ 5239 /* enum: Any */ 5240 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff 5241 /* enum: None */ 5242 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe 5243 5244 /* EVB_PORT_ID structuredef */ 5245 #define EVB_PORT_ID_LEN 4 5246 #define EVB_PORT_ID_PORT_ID_OFST 0 5247 /* enum: An invalid port handle. */ 5248 #define EVB_PORT_ID_NULL 0x0 5249 /* enum: The port assigned to this function.. */ 5250 #define EVB_PORT_ID_ASSIGNED 0x1000000 5251 /* enum: External network port 0 */ 5252 #define EVB_PORT_ID_MAC0 0x2000000 5253 /* enum: External network port 1 */ 5254 #define EVB_PORT_ID_MAC1 0x2000001 5255 /* enum: External network port 2 */ 5256 #define EVB_PORT_ID_MAC2 0x2000002 5257 /* enum: External network port 3 */ 5258 #define EVB_PORT_ID_MAC3 0x2000003 5259 #define EVB_PORT_ID_PORT_ID_LBN 0 5260 #define EVB_PORT_ID_PORT_ID_WIDTH 32 5261 5262 /* EVB_VLAN_TAG structuredef */ 5263 #define EVB_VLAN_TAG_LEN 2 5264 /* The VLAN tag value */ 5265 #define EVB_VLAN_TAG_VLAN_ID_LBN 0 5266 #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 5267 #define EVB_VLAN_TAG_MODE_LBN 12 5268 #define EVB_VLAN_TAG_MODE_WIDTH 4 5269 /* enum: Insert the VLAN. */ 5270 #define EVB_VLAN_TAG_INSERT 0x0 5271 /* enum: Replace the VLAN if already present. */ 5272 #define EVB_VLAN_TAG_REPLACE 0x1 5273 5274 /* BUFTBL_ENTRY structuredef */ 5275 #define BUFTBL_ENTRY_LEN 12 5276 /* the owner ID */ 5277 #define BUFTBL_ENTRY_OID_OFST 0 5278 #define BUFTBL_ENTRY_OID_LEN 2 5279 #define BUFTBL_ENTRY_OID_LBN 0 5280 #define BUFTBL_ENTRY_OID_WIDTH 16 5281 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ 5282 #define BUFTBL_ENTRY_PGSZ_OFST 2 5283 #define BUFTBL_ENTRY_PGSZ_LEN 2 5284 #define BUFTBL_ENTRY_PGSZ_LBN 16 5285 #define BUFTBL_ENTRY_PGSZ_WIDTH 16 5286 /* the raw 64-bit address field from the SMC, not adjusted for page size */ 5287 #define BUFTBL_ENTRY_RAWADDR_OFST 4 5288 #define BUFTBL_ENTRY_RAWADDR_LEN 8 5289 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 5290 #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 5291 #define BUFTBL_ENTRY_RAWADDR_LBN 32 5292 #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 5293 5294 /* NVRAM_PARTITION_TYPE structuredef */ 5295 #define NVRAM_PARTITION_TYPE_LEN 2 5296 #define NVRAM_PARTITION_TYPE_ID_OFST 0 5297 #define NVRAM_PARTITION_TYPE_ID_LEN 2 5298 /* enum: Primary MC firmware partition */ 5299 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 5300 /* enum: Secondary MC firmware partition */ 5301 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 5302 /* enum: Expansion ROM partition */ 5303 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 5304 /* enum: Static configuration TLV partition */ 5305 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 5306 /* enum: Dynamic configuration TLV partition */ 5307 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 5308 /* enum: Expansion ROM configuration data for port 0 */ 5309 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 5310 /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */ 5311 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600 5312 /* enum: Expansion ROM configuration data for port 1 */ 5313 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 5314 /* enum: Expansion ROM configuration data for port 2 */ 5315 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 5316 /* enum: Expansion ROM configuration data for port 3 */ 5317 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 5318 /* enum: Non-volatile log output partition */ 5319 #define NVRAM_PARTITION_TYPE_LOG 0x700 5320 /* enum: Non-volatile log output of second core on dual-core device */ 5321 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701 5322 /* enum: Device state dump output partition */ 5323 #define NVRAM_PARTITION_TYPE_DUMP 0x800 5324 /* enum: Application license key storage partition */ 5325 #define NVRAM_PARTITION_TYPE_LICENSE 0x900 5326 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ 5327 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 5328 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ 5329 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff 5330 /* enum: Primary FPGA partition */ 5331 #define NVRAM_PARTITION_TYPE_FPGA 0xb00 5332 /* enum: Secondary FPGA partition */ 5333 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01 5334 /* enum: FC firmware partition */ 5335 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02 5336 /* enum: FC License partition */ 5337 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03 5338 /* enum: Non-volatile log output partition for FC */ 5339 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04 5340 /* enum: MUM firmware partition */ 5341 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00 5342 /* enum: MUM Non-volatile log output partition. */ 5343 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01 5344 /* enum: MUM Application table partition. */ 5345 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02 5346 /* enum: MUM boot rom partition. */ 5347 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03 5348 /* enum: MUM production signatures & calibration rom partition. */ 5349 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04 5350 /* enum: MUM user signatures & calibration rom partition. */ 5351 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05 5352 /* enum: MUM fuses and lockbits partition. */ 5353 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06 5354 /* enum: UEFI expansion ROM if separate from PXE */ 5355 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00 5356 /* enum: Spare partition 0 */ 5357 #define NVRAM_PARTITION_TYPE_SPARE_0 0x1000 5358 /* enum: Spare partition 1 */ 5359 #define NVRAM_PARTITION_TYPE_SPARE_1 0x1100 5360 /* enum: Spare partition 2 */ 5361 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200 5362 /* enum: Spare partition 3 */ 5363 #define NVRAM_PARTITION_TYPE_SPARE_3 0x1300 5364 /* enum: Spare partition 4 */ 5365 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400 5366 /* enum: Spare partition 5 */ 5367 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500 5368 /* enum: Start of reserved value range (firmware may use for any purpose) */ 5369 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 5370 /* enum: End of reserved value range (firmware may use for any purpose) */ 5371 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd 5372 /* enum: Recovery partition map (provided if real map is missing or corrupt) */ 5373 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe 5374 /* enum: Partition map (real map as stored in flash) */ 5375 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff 5376 #define NVRAM_PARTITION_TYPE_ID_LBN 0 5377 #define NVRAM_PARTITION_TYPE_ID_WIDTH 16 5378 5379 /* LICENSED_APP_ID structuredef */ 5380 #define LICENSED_APP_ID_LEN 4 5381 #define LICENSED_APP_ID_ID_OFST 0 5382 /* enum: OpenOnload */ 5383 #define LICENSED_APP_ID_ONLOAD 0x1 5384 /* enum: PTP timestamping */ 5385 #define LICENSED_APP_ID_PTP 0x2 5386 /* enum: SolarCapture Pro */ 5387 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 5388 /* enum: SolarSecure filter engine */ 5389 #define LICENSED_APP_ID_SOLARSECURE 0x8 5390 /* enum: Performance monitor */ 5391 #define LICENSED_APP_ID_PERF_MONITOR 0x10 5392 /* enum: SolarCapture Live */ 5393 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20 5394 /* enum: Capture SolarSystem */ 5395 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40 5396 /* enum: Network Access Control */ 5397 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80 5398 #define LICENSED_APP_ID_ID_LBN 0 5399 #define LICENSED_APP_ID_ID_WIDTH 32 5400 5401 /* LICENSED_FEATURES structuredef */ 5402 #define LICENSED_FEATURES_LEN 8 5403 /* Bitmask of licensed firmware features */ 5404 #define LICENSED_FEATURES_MASK_OFST 0 5405 #define LICENSED_FEATURES_MASK_LEN 8 5406 #define LICENSED_FEATURES_MASK_LO_OFST 0 5407 #define LICENSED_FEATURES_MASK_HI_OFST 4 5408 #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0 5409 #define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1 5410 #define LICENSED_FEATURES_PIO_LBN 1 5411 #define LICENSED_FEATURES_PIO_WIDTH 1 5412 #define LICENSED_FEATURES_EVQ_TIMER_LBN 2 5413 #define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1 5414 #define LICENSED_FEATURES_CLOCK_LBN 3 5415 #define LICENSED_FEATURES_CLOCK_WIDTH 1 5416 #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4 5417 #define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1 5418 #define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5 5419 #define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1 5420 #define LICENSED_FEATURES_RX_SNIFF_LBN 6 5421 #define LICENSED_FEATURES_RX_SNIFF_WIDTH 1 5422 #define LICENSED_FEATURES_TX_SNIFF_LBN 7 5423 #define LICENSED_FEATURES_TX_SNIFF_WIDTH 1 5424 #define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8 5425 #define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1 5426 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9 5427 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 5428 #define LICENSED_FEATURES_MASK_LBN 0 5429 #define LICENSED_FEATURES_MASK_WIDTH 64 5430 5431 /* LICENSED_V3_APPS structuredef */ 5432 #define LICENSED_V3_APPS_LEN 8 5433 /* Bitmask of licensed applications */ 5434 #define LICENSED_V3_APPS_MASK_OFST 0 5435 #define LICENSED_V3_APPS_MASK_LEN 8 5436 #define LICENSED_V3_APPS_MASK_LO_OFST 0 5437 #define LICENSED_V3_APPS_MASK_HI_OFST 4 5438 #define LICENSED_V3_APPS_ONLOAD_LBN 0 5439 #define LICENSED_V3_APPS_ONLOAD_WIDTH 1 5440 #define LICENSED_V3_APPS_PTP_LBN 1 5441 #define LICENSED_V3_APPS_PTP_WIDTH 1 5442 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2 5443 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1 5444 #define LICENSED_V3_APPS_SOLARSECURE_LBN 3 5445 #define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1 5446 #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4 5447 #define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1 5448 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5 5449 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1 5450 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6 5451 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1 5452 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7 5453 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1 5454 #define LICENSED_V3_APPS_MASK_LBN 0 5455 #define LICENSED_V3_APPS_MASK_WIDTH 64 5456 5457 /* LICENSED_V3_FEATURES structuredef */ 5458 #define LICENSED_V3_FEATURES_LEN 8 5459 /* Bitmask of licensed firmware features */ 5460 #define LICENSED_V3_FEATURES_MASK_OFST 0 5461 #define LICENSED_V3_FEATURES_MASK_LEN 8 5462 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0 5463 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4 5464 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0 5465 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1 5466 #define LICENSED_V3_FEATURES_PIO_LBN 1 5467 #define LICENSED_V3_FEATURES_PIO_WIDTH 1 5468 #define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2 5469 #define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1 5470 #define LICENSED_V3_FEATURES_CLOCK_LBN 3 5471 #define LICENSED_V3_FEATURES_CLOCK_WIDTH 1 5472 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4 5473 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1 5474 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5 5475 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1 5476 #define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6 5477 #define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1 5478 #define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7 5479 #define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1 5480 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8 5481 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1 5482 #define LICENSED_V3_FEATURES_MASK_LBN 0 5483 #define LICENSED_V3_FEATURES_MASK_WIDTH 64 5484 5485 /* TX_TIMESTAMP_EVENT structuredef */ 5486 #define TX_TIMESTAMP_EVENT_LEN 6 5487 /* lower 16 bits of timestamp data */ 5488 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0 5489 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2 5490 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0 5491 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16 5492 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp 5493 */ 5494 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3 5495 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1 5496 /* enum: This is a TX completion event, not a timestamp */ 5497 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0 5498 /* enum: This is the low part of a TX timestamp event */ 5499 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51 5500 /* enum: This is the high part of a TX timestamp event */ 5501 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52 5502 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24 5503 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8 5504 /* upper 16 bits of timestamp data */ 5505 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4 5506 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2 5507 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32 5508 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16 5509 5510 /* RSS_MODE structuredef */ 5511 #define RSS_MODE_LEN 1 5512 /* The RSS mode for a particular packet type is a value from 0 - 15 which can 5513 * be considered as 4 bits selecting which fields are included in the hash. (A 5514 * value 0 effectively disables RSS spreading for the packet type.) The YAML 5515 * generation tools require this structure to be a whole number of bytes wide, 5516 * but only 4 bits are relevant. 5517 */ 5518 #define RSS_MODE_HASH_SELECTOR_OFST 0 5519 #define RSS_MODE_HASH_SELECTOR_LEN 1 5520 #define RSS_MODE_HASH_SRC_ADDR_LBN 0 5521 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1 5522 #define RSS_MODE_HASH_DST_ADDR_LBN 1 5523 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1 5524 #define RSS_MODE_HASH_SRC_PORT_LBN 2 5525 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1 5526 #define RSS_MODE_HASH_DST_PORT_LBN 3 5527 #define RSS_MODE_HASH_DST_PORT_WIDTH 1 5528 #define RSS_MODE_HASH_SELECTOR_LBN 0 5529 #define RSS_MODE_HASH_SELECTOR_WIDTH 8 5530 5531 5532 /***********************************/ 5533 /* MC_CMD_READ_REGS 5534 * Get a dump of the MCPU registers 5535 */ 5536 #define MC_CMD_READ_REGS 0x50 5537 5538 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5539 5540 /* MC_CMD_READ_REGS_IN msgrequest */ 5541 #define MC_CMD_READ_REGS_IN_LEN 0 5542 5543 /* MC_CMD_READ_REGS_OUT msgresponse */ 5544 #define MC_CMD_READ_REGS_OUT_LEN 308 5545 /* Whether the corresponding register entry contains a valid value */ 5546 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 5547 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 5548 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, 5549 * fir, fp) 5550 */ 5551 #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 5552 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 5553 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 5554 5555 5556 /***********************************/ 5557 /* MC_CMD_INIT_EVQ 5558 * Set up an event queue according to the supplied parameters. The IN arguments 5559 * end with an address for each 4k of host memory required to back the EVQ. 5560 */ 5561 #define MC_CMD_INIT_EVQ 0x80 5562 5563 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5564 5565 /* MC_CMD_INIT_EVQ_IN msgrequest */ 5566 #define MC_CMD_INIT_EVQ_IN_LENMIN 44 5567 #define MC_CMD_INIT_EVQ_IN_LENMAX 548 5568 #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) 5569 /* Size, in entries */ 5570 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 5571 /* Desired instance. Must be set to a specific instance, which is a function 5572 * local queue index. 5573 */ 5574 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 5575 /* The initial timer value. The load value is ignored if the timer mode is DIS. 5576 */ 5577 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 5578 /* The reload value is ignored in one-shot modes */ 5579 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 5580 /* tbd */ 5581 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 5582 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 5583 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 5584 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 5585 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 5586 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 5587 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 5588 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 5589 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 5590 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 5591 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 5592 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 5593 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 5594 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6 5595 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1 5596 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 5597 /* enum: Disabled */ 5598 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 5599 /* enum: Immediate */ 5600 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 5601 /* enum: Triggered */ 5602 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 5603 /* enum: Hold-off */ 5604 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 5605 /* Target EVQ for wakeups if in wakeup mode. */ 5606 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 5607 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 5608 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 5609 * purposes. 5610 */ 5611 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 5612 /* Event Counter Mode. */ 5613 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 5614 /* enum: Disabled */ 5615 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 5616 /* enum: Disabled */ 5617 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 5618 /* enum: Disabled */ 5619 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 5620 /* enum: Disabled */ 5621 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 5622 /* Event queue packet count threshold. */ 5623 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 5624 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 5625 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 5626 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 5627 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 5628 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 5629 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 5630 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 5631 5632 /* MC_CMD_INIT_EVQ_OUT msgresponse */ 5633 #define MC_CMD_INIT_EVQ_OUT_LEN 4 5634 /* Only valid if INTRFLAG was true */ 5635 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 5636 5637 /* QUEUE_CRC_MODE structuredef */ 5638 #define QUEUE_CRC_MODE_LEN 1 5639 #define QUEUE_CRC_MODE_MODE_LBN 0 5640 #define QUEUE_CRC_MODE_MODE_WIDTH 4 5641 /* enum: No CRC. */ 5642 #define QUEUE_CRC_MODE_NONE 0x0 5643 /* enum: CRC Fiber channel over ethernet. */ 5644 #define QUEUE_CRC_MODE_FCOE 0x1 5645 /* enum: CRC (digest) iSCSI header only. */ 5646 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 5647 /* enum: CRC (digest) iSCSI header and payload. */ 5648 #define QUEUE_CRC_MODE_ISCSI 0x3 5649 /* enum: CRC Fiber channel over IP over ethernet. */ 5650 #define QUEUE_CRC_MODE_FCOIPOE 0x4 5651 /* enum: CRC MPA. */ 5652 #define QUEUE_CRC_MODE_MPA 0x5 5653 #define QUEUE_CRC_MODE_SPARE_LBN 4 5654 #define QUEUE_CRC_MODE_SPARE_WIDTH 4 5655 5656 5657 /***********************************/ 5658 /* MC_CMD_INIT_RXQ 5659 * set up a receive queue according to the supplied parameters. The IN 5660 * arguments end with an address for each 4k of host memory required to back 5661 * the RXQ. 5662 */ 5663 #define MC_CMD_INIT_RXQ 0x81 5664 5665 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5666 5667 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version 5668 * in new code. 5669 */ 5670 #define MC_CMD_INIT_RXQ_IN_LENMIN 36 5671 #define MC_CMD_INIT_RXQ_IN_LENMAX 252 5672 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) 5673 /* Size, in entries */ 5674 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 5675 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 5676 */ 5677 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 5678 /* The value to put in the event data. Check hardware spec. for valid range. */ 5679 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 5680 /* Desired instance. Must be set to a specific instance, which is a function 5681 * local queue index. 5682 */ 5683 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 5684 /* There will be more flags here. */ 5685 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 5686 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 5687 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 5688 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 5689 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 5690 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 5691 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 5692 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 5693 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 5694 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 5695 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 5696 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 5697 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 5698 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 5699 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 5700 #define MC_CMD_INIT_RXQ_IN_FLAG_FORCE_EV_MERGING_LBN 10 5701 #define MC_CMD_INIT_RXQ_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 5702 /* Owner ID to use if in buffer mode (zero if physical) */ 5703 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 5704 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 5705 #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 5706 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 5707 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 5708 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 5709 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 5710 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 5711 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 5712 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 5713 5714 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode 5715 * flags 5716 */ 5717 #define MC_CMD_INIT_RXQ_EXT_IN_LEN 544 5718 /* Size, in entries */ 5719 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0 5720 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 5721 */ 5722 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4 5723 /* The value to put in the event data. Check hardware spec. for valid range. */ 5724 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8 5725 /* Desired instance. Must be set to a specific instance, which is a function 5726 * local queue index. 5727 */ 5728 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12 5729 /* There will be more flags here. */ 5730 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16 5731 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 5732 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 5733 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1 5734 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1 5735 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2 5736 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 5737 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3 5738 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4 5739 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7 5740 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1 5741 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8 5742 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1 5743 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9 5744 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1 5745 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10 5746 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4 5747 /* enum: One packet per descriptor (for normal networking) */ 5748 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0 5749 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 5750 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1 5751 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14 5752 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 5753 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 5754 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 5755 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */ 5756 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */ 5757 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */ 5758 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */ 5759 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ 5760 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 5761 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 5762 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19 5763 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 5764 /* Owner ID to use if in buffer mode (zero if physical) */ 5765 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 5766 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 5767 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24 5768 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 5769 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28 5770 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8 5771 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28 5772 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32 5773 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64 5774 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 5775 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540 5776 5777 /* MC_CMD_INIT_RXQ_OUT msgresponse */ 5778 #define MC_CMD_INIT_RXQ_OUT_LEN 0 5779 5780 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */ 5781 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0 5782 5783 5784 /***********************************/ 5785 /* MC_CMD_INIT_TXQ 5786 */ 5787 #define MC_CMD_INIT_TXQ 0x82 5788 5789 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5790 5791 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version 5792 * in new code. 5793 */ 5794 #define MC_CMD_INIT_TXQ_IN_LENMIN 36 5795 #define MC_CMD_INIT_TXQ_IN_LENMAX 252 5796 #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) 5797 /* Size, in entries */ 5798 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 5799 /* The EVQ to send events to. This is an index originally specified to 5800 * INIT_EVQ. 5801 */ 5802 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 5803 /* The value to put in the event data. Check hardware spec. for valid range. */ 5804 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 5805 /* Desired instance. Must be set to a specific instance, which is a function 5806 * local queue index. 5807 */ 5808 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 5809 /* There will be more flags here. */ 5810 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 5811 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 5812 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 5813 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 5814 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 5815 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 5816 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 5817 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 5818 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 5819 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 5820 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 5821 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 5822 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 5823 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 5824 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 5825 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 5826 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 5827 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 5828 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 5829 /* Owner ID to use if in buffer mode (zero if physical) */ 5830 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 5831 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 5832 #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 5833 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 5834 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 5835 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 5836 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 5837 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 5838 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 5839 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 5840 5841 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode 5842 * flags 5843 */ 5844 #define MC_CMD_INIT_TXQ_EXT_IN_LEN 544 5845 /* Size, in entries */ 5846 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0 5847 /* The EVQ to send events to. This is an index originally specified to 5848 * INIT_EVQ. 5849 */ 5850 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4 5851 /* The value to put in the event data. Check hardware spec. for valid range. */ 5852 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8 5853 /* Desired instance. Must be set to a specific instance, which is a function 5854 * local queue index. 5855 */ 5856 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12 5857 /* There will be more flags here. */ 5858 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16 5859 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 5860 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 5861 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1 5862 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1 5863 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2 5864 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 5865 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3 5866 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 5867 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4 5868 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4 5869 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8 5870 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 5871 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9 5872 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1 5873 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 5874 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 5875 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 5876 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 5877 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12 5878 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1 5879 /* Owner ID to use if in buffer mode (zero if physical) */ 5880 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 5881 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 5882 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24 5883 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 5884 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28 5885 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8 5886 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28 5887 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32 5888 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1 5889 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64 5890 /* Flags related to Qbb flow control mode. */ 5891 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540 5892 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0 5893 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1 5894 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1 5895 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3 5896 5897 /* MC_CMD_INIT_TXQ_OUT msgresponse */ 5898 #define MC_CMD_INIT_TXQ_OUT_LEN 0 5899 5900 5901 /***********************************/ 5902 /* MC_CMD_FINI_EVQ 5903 * Teardown an EVQ. 5904 * 5905 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first 5906 * or the operation will fail with EBUSY 5907 */ 5908 #define MC_CMD_FINI_EVQ 0x83 5909 5910 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5911 5912 /* MC_CMD_FINI_EVQ_IN msgrequest */ 5913 #define MC_CMD_FINI_EVQ_IN_LEN 4 5914 /* Instance of EVQ to destroy. Should be the same instance as that previously 5915 * passed to INIT_EVQ 5916 */ 5917 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 5918 5919 /* MC_CMD_FINI_EVQ_OUT msgresponse */ 5920 #define MC_CMD_FINI_EVQ_OUT_LEN 0 5921 5922 5923 /***********************************/ 5924 /* MC_CMD_FINI_RXQ 5925 * Teardown a RXQ. 5926 */ 5927 #define MC_CMD_FINI_RXQ 0x84 5928 5929 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5930 5931 /* MC_CMD_FINI_RXQ_IN msgrequest */ 5932 #define MC_CMD_FINI_RXQ_IN_LEN 4 5933 /* Instance of RXQ to destroy */ 5934 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 5935 5936 /* MC_CMD_FINI_RXQ_OUT msgresponse */ 5937 #define MC_CMD_FINI_RXQ_OUT_LEN 0 5938 5939 5940 /***********************************/ 5941 /* MC_CMD_FINI_TXQ 5942 * Teardown a TXQ. 5943 */ 5944 #define MC_CMD_FINI_TXQ 0x85 5945 5946 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5947 5948 /* MC_CMD_FINI_TXQ_IN msgrequest */ 5949 #define MC_CMD_FINI_TXQ_IN_LEN 4 5950 /* Instance of TXQ to destroy */ 5951 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 5952 5953 /* MC_CMD_FINI_TXQ_OUT msgresponse */ 5954 #define MC_CMD_FINI_TXQ_OUT_LEN 0 5955 5956 5957 /***********************************/ 5958 /* MC_CMD_DRIVER_EVENT 5959 * Generate an event on an EVQ belonging to the function issuing the command. 5960 */ 5961 #define MC_CMD_DRIVER_EVENT 0x86 5962 5963 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5964 5965 /* MC_CMD_DRIVER_EVENT_IN msgrequest */ 5966 #define MC_CMD_DRIVER_EVENT_IN_LEN 12 5967 /* Handle of target EVQ */ 5968 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 5969 /* Bits 0 - 63 of event */ 5970 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 5971 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 5972 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 5973 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 5974 5975 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ 5976 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 5977 5978 5979 /***********************************/ 5980 /* MC_CMD_PROXY_CMD 5981 * Execute an arbitrary MCDI command on behalf of a different function, subject 5982 * to security restrictions. The command to be proxied follows immediately 5983 * afterward in the host buffer (or on the UART). This command supercedes 5984 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. 5985 */ 5986 #define MC_CMD_PROXY_CMD 0x5b 5987 5988 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5989 5990 /* MC_CMD_PROXY_CMD_IN msgrequest */ 5991 #define MC_CMD_PROXY_CMD_IN_LEN 4 5992 /* The handle of the target function. */ 5993 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 5994 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 5995 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 5996 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 5997 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 5998 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ 5999 6000 /* MC_CMD_PROXY_CMD_OUT msgresponse */ 6001 #define MC_CMD_PROXY_CMD_OUT_LEN 0 6002 6003 /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to 6004 * manage proxied requests 6005 */ 6006 #define MC_PROXY_STATUS_BUFFER_LEN 16 6007 /* Handle allocated by the firmware for this proxy transaction */ 6008 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0 6009 /* enum: An invalid handle. */ 6010 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0 6011 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0 6012 #define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32 6013 /* The requesting physical function number */ 6014 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4 6015 #define MC_PROXY_STATUS_BUFFER_PF_LEN 2 6016 #define MC_PROXY_STATUS_BUFFER_PF_LBN 32 6017 #define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16 6018 /* The requesting virtual function number. Set to VF_NULL if the target is a 6019 * PF. 6020 */ 6021 #define MC_PROXY_STATUS_BUFFER_VF_OFST 6 6022 #define MC_PROXY_STATUS_BUFFER_VF_LEN 2 6023 #define MC_PROXY_STATUS_BUFFER_VF_LBN 48 6024 #define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16 6025 /* The target function RID. */ 6026 #define MC_PROXY_STATUS_BUFFER_RID_OFST 8 6027 #define MC_PROXY_STATUS_BUFFER_RID_LEN 2 6028 #define MC_PROXY_STATUS_BUFFER_RID_LBN 64 6029 #define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16 6030 /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */ 6031 #define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10 6032 #define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2 6033 #define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80 6034 #define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16 6035 /* If a request is authorized rather than carried out by the host, this is the 6036 * elevated privilege mask granted to the requesting function. 6037 */ 6038 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12 6039 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 6040 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 6041 6042 6043 /***********************************/ 6044 /* MC_CMD_PROXY_CONFIGURE 6045 * Enable/disable authorization of MCDI requests from unprivileged functions by 6046 * a designated admin function 6047 */ 6048 #define MC_CMD_PROXY_CONFIGURE 0x58 6049 6050 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6051 6052 /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */ 6053 #define MC_CMD_PROXY_CONFIGURE_IN_LEN 108 6054 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0 6055 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0 6056 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1 6057 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 6058 * of blocks, each of the size REQUEST_BLOCK_SIZE. 6059 */ 6060 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4 6061 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8 6062 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4 6063 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8 6064 /* Must be a power of 2 */ 6065 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12 6066 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 6067 * of blocks, each of the size REPLY_BLOCK_SIZE. 6068 */ 6069 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16 6070 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8 6071 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16 6072 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20 6073 /* Must be a power of 2 */ 6074 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24 6075 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 6076 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 6077 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 6078 */ 6079 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28 6080 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8 6081 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28 6082 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32 6083 /* Must be a power of 2, or zero if this buffer is not provided */ 6084 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36 6085 /* Applies to all three buffers */ 6086 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40 6087 /* A bit mask defining which MCDI operations may be proxied */ 6088 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 6089 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 6090 6091 /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */ 6092 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112 6093 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0 6094 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0 6095 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1 6096 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 6097 * of blocks, each of the size REQUEST_BLOCK_SIZE. 6098 */ 6099 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4 6100 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8 6101 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4 6102 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8 6103 /* Must be a power of 2 */ 6104 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12 6105 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 6106 * of blocks, each of the size REPLY_BLOCK_SIZE. 6107 */ 6108 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16 6109 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8 6110 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16 6111 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20 6112 /* Must be a power of 2 */ 6113 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24 6114 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 6115 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 6116 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 6117 */ 6118 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28 6119 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8 6120 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28 6121 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32 6122 /* Must be a power of 2, or zero if this buffer is not provided */ 6123 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36 6124 /* Applies to all three buffers */ 6125 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40 6126 /* A bit mask defining which MCDI operations may be proxied */ 6127 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44 6128 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64 6129 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108 6130 6131 /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ 6132 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 6133 6134 6135 /***********************************/ 6136 /* MC_CMD_PROXY_COMPLETE 6137 * Tells FW that a requested proxy operation has either been completed (by 6138 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the 6139 * function that enabled proxying/authorization (by using 6140 * MC_CMD_PROXY_CONFIGURE). 6141 */ 6142 #define MC_CMD_PROXY_COMPLETE 0x5f 6143 6144 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6145 6146 /* MC_CMD_PROXY_COMPLETE_IN msgrequest */ 6147 #define MC_CMD_PROXY_COMPLETE_IN_LEN 12 6148 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0 6149 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4 6150 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply 6151 * is stored in the REPLY_BUFF. 6152 */ 6153 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0 6154 /* enum: The operation has been authorized. The originating function may now 6155 * try again. 6156 */ 6157 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1 6158 /* enum: The operation has been declined. */ 6159 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2 6160 /* enum: The authorization failed because the relevant application did not 6161 * respond in time. 6162 */ 6163 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3 6164 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8 6165 6166 /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ 6167 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 6168 6169 6170 /***********************************/ 6171 /* MC_CMD_ALLOC_BUFTBL_CHUNK 6172 * Allocate a set of buffer table entries using the specified owner ID. This 6173 * operation allocates the required buffer table entries (and fails if it 6174 * cannot do so). The buffer table entries will initially be zeroed. 6175 */ 6176 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 6177 6178 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 6179 6180 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 6181 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 6182 /* Owner ID to use */ 6183 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 6184 /* Size of buffer table pages to use, in bytes (note that only a few values are 6185 * legal on any specific hardware). 6186 */ 6187 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 6188 6189 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 6190 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 6191 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 6192 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 6193 /* Buffer table IDs for use in DMA descriptors. */ 6194 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 6195 6196 6197 /***********************************/ 6198 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES 6199 * Reprogram a set of buffer table entries in the specified chunk. 6200 */ 6201 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 6202 6203 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 6204 6205 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 6206 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 6207 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 6208 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 6209 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 6210 /* ID */ 6211 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 6212 /* Num entries */ 6213 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 6214 /* Buffer table entry address */ 6215 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 6216 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 6217 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 6218 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 6219 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 6220 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 6221 6222 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 6223 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 6224 6225 6226 /***********************************/ 6227 /* MC_CMD_FREE_BUFTBL_CHUNK 6228 */ 6229 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 6230 6231 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 6232 6233 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 6234 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 6235 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 6236 6237 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 6238 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 6239 6240 /* PORT_CONFIG_ENTRY structuredef */ 6241 #define PORT_CONFIG_ENTRY_LEN 16 6242 /* External port number (label) */ 6243 #define PORT_CONFIG_ENTRY_EXT_NUMBER_OFST 0 6244 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LEN 1 6245 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LBN 0 6246 #define PORT_CONFIG_ENTRY_EXT_NUMBER_WIDTH 8 6247 /* Port core location */ 6248 #define PORT_CONFIG_ENTRY_CORE_OFST 1 6249 #define PORT_CONFIG_ENTRY_CORE_LEN 1 6250 #define PORT_CONFIG_ENTRY_STANDALONE 0x0 /* enum */ 6251 #define PORT_CONFIG_ENTRY_MASTER 0x1 /* enum */ 6252 #define PORT_CONFIG_ENTRY_SLAVE 0x2 /* enum */ 6253 #define PORT_CONFIG_ENTRY_CORE_LBN 8 6254 #define PORT_CONFIG_ENTRY_CORE_WIDTH 8 6255 /* Internal number (HW resource) relative to the core */ 6256 #define PORT_CONFIG_ENTRY_INT_NUMBER_OFST 2 6257 #define PORT_CONFIG_ENTRY_INT_NUMBER_LEN 1 6258 #define PORT_CONFIG_ENTRY_INT_NUMBER_LBN 16 6259 #define PORT_CONFIG_ENTRY_INT_NUMBER_WIDTH 8 6260 /* Reserved */ 6261 #define PORT_CONFIG_ENTRY_RSVD_OFST 3 6262 #define PORT_CONFIG_ENTRY_RSVD_LEN 1 6263 #define PORT_CONFIG_ENTRY_RSVD_LBN 24 6264 #define PORT_CONFIG_ENTRY_RSVD_WIDTH 8 6265 /* Bitmask of KR lanes used by the port */ 6266 #define PORT_CONFIG_ENTRY_LANES_OFST 4 6267 #define PORT_CONFIG_ENTRY_LANES_LBN 32 6268 #define PORT_CONFIG_ENTRY_LANES_WIDTH 32 6269 /* Port capabilities (MC_CMD_PHY_CAP_*) */ 6270 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_OFST 8 6271 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_LBN 64 6272 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_WIDTH 32 6273 /* Reserved (align to 16 bytes) */ 6274 #define PORT_CONFIG_ENTRY_RSVD2_OFST 12 6275 #define PORT_CONFIG_ENTRY_RSVD2_LBN 96 6276 #define PORT_CONFIG_ENTRY_RSVD2_WIDTH 32 6277 6278 6279 /***********************************/ 6280 /* MC_CMD_FILTER_OP 6281 * Multiplexed MCDI call for filter operations 6282 */ 6283 #define MC_CMD_FILTER_OP 0x8a 6284 6285 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6286 6287 /* MC_CMD_FILTER_OP_IN msgrequest */ 6288 #define MC_CMD_FILTER_OP_IN_LEN 108 6289 /* identifies the type of operation requested */ 6290 #define MC_CMD_FILTER_OP_IN_OP_OFST 0 6291 /* enum: single-recipient filter insert */ 6292 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 6293 /* enum: single-recipient filter remove */ 6294 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 6295 /* enum: multi-recipient filter subscribe */ 6296 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 6297 /* enum: multi-recipient filter unsubscribe */ 6298 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 6299 /* enum: replace one recipient with another (warning - the filter handle may 6300 * change) 6301 */ 6302 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 6303 /* filter handle (for remove / unsubscribe operations) */ 6304 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 6305 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 6306 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 6307 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 6308 /* The port ID associated with the v-adaptor which should contain this filter. 6309 */ 6310 #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 6311 /* fields to include in match criteria */ 6312 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 6313 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 6314 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 6315 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 6316 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 6317 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 6318 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 6319 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 6320 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 6321 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 6322 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 6323 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 6324 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 6325 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 6326 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 6327 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 6328 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 6329 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 6330 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 6331 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 6332 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 6333 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 6334 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 6335 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 6336 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 6337 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 6338 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 6339 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 6340 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 6341 /* receive destination */ 6342 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 6343 /* enum: drop packets */ 6344 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 6345 /* enum: receive to host */ 6346 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 6347 /* enum: receive to MC */ 6348 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 6349 /* enum: loop back to TXDP 0 */ 6350 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 6351 /* enum: loop back to TXDP 1 */ 6352 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 6353 /* receive queue handle (for multiple queue modes, this is the base queue) */ 6354 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 6355 /* receive mode */ 6356 #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 6357 /* enum: receive to just the specified queue */ 6358 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 6359 /* enum: receive to multiple queues using RSS context */ 6360 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 6361 /* enum: receive to multiple queues using .1p mapping */ 6362 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 6363 /* enum: install a filter entry that will never match; for test purposes only 6364 */ 6365 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 6366 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 6367 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 6368 * MC_CMD_DOT1P_MAPPING_ALLOC. 6369 */ 6370 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 6371 /* transmit domain (reserved; set to 0) */ 6372 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 6373 /* transmit destination (either set the MAC and/or PM bits for explicit 6374 * control, or set this field to TX_DEST_DEFAULT for sensible default 6375 * behaviour) 6376 */ 6377 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 6378 /* enum: request default behaviour (based on filter type) */ 6379 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff 6380 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 6381 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 6382 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 6383 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 6384 /* source MAC address to match (as bytes in network order) */ 6385 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 6386 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 6387 /* source port to match (as bytes in network order) */ 6388 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 6389 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 6390 /* destination MAC address to match (as bytes in network order) */ 6391 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 6392 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 6393 /* destination port to match (as bytes in network order) */ 6394 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 6395 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 6396 /* Ethernet type to match (as bytes in network order) */ 6397 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 6398 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 6399 /* Inner VLAN tag to match (as bytes in network order) */ 6400 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 6401 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 6402 /* Outer VLAN tag to match (as bytes in network order) */ 6403 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 6404 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 6405 /* IP protocol to match (in low byte; set high byte to 0) */ 6406 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 6407 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 6408 /* Firmware defined register 0 to match (reserved; set to 0) */ 6409 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 6410 /* Firmware defined register 1 to match (reserved; set to 0) */ 6411 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 6412 /* source IP address to match (as bytes in network order; set last 12 bytes to 6413 * 0 for IPv4 address) 6414 */ 6415 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 6416 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 6417 /* destination IP address to match (as bytes in network order; set last 12 6418 * bytes to 0 for IPv4 address) 6419 */ 6420 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 6421 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 6422 6423 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to 6424 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is 6425 * supported on Medford only). 6426 */ 6427 #define MC_CMD_FILTER_OP_EXT_IN_LEN 172 6428 /* identifies the type of operation requested */ 6429 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0 6430 /* Enum values, see field(s): */ 6431 /* MC_CMD_FILTER_OP_IN/OP */ 6432 /* filter handle (for remove / unsubscribe operations) */ 6433 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4 6434 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8 6435 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4 6436 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8 6437 /* The port ID associated with the v-adaptor which should contain this filter. 6438 */ 6439 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12 6440 /* fields to include in match criteria */ 6441 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16 6442 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0 6443 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1 6444 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1 6445 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1 6446 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2 6447 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1 6448 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3 6449 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1 6450 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4 6451 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1 6452 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5 6453 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1 6454 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6 6455 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1 6456 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7 6457 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1 6458 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8 6459 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1 6460 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9 6461 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1 6462 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10 6463 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1 6464 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11 6465 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1 6466 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12 6467 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1 6468 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13 6469 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1 6470 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14 6471 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 6472 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15 6473 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 6474 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16 6475 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1 6476 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17 6477 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1 6478 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 6479 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 6480 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19 6481 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 6482 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 6483 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 6484 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21 6485 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 6486 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22 6487 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1 6488 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23 6489 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1 6490 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 6491 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 6492 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 6493 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 6494 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 6495 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 6496 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 6497 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 6498 /* receive destination */ 6499 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20 6500 /* enum: drop packets */ 6501 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0 6502 /* enum: receive to host */ 6503 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1 6504 /* enum: receive to MC */ 6505 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2 6506 /* enum: loop back to TXDP 0 */ 6507 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3 6508 /* enum: loop back to TXDP 1 */ 6509 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4 6510 /* receive queue handle (for multiple queue modes, this is the base queue) */ 6511 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24 6512 /* receive mode */ 6513 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28 6514 /* enum: receive to just the specified queue */ 6515 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0 6516 /* enum: receive to multiple queues using RSS context */ 6517 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1 6518 /* enum: receive to multiple queues using .1p mapping */ 6519 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2 6520 /* enum: install a filter entry that will never match; for test purposes only 6521 */ 6522 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 6523 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 6524 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 6525 * MC_CMD_DOT1P_MAPPING_ALLOC. 6526 */ 6527 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32 6528 /* transmit domain (reserved; set to 0) */ 6529 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36 6530 /* transmit destination (either set the MAC and/or PM bits for explicit 6531 * control, or set this field to TX_DEST_DEFAULT for sensible default 6532 * behaviour) 6533 */ 6534 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40 6535 /* enum: request default behaviour (based on filter type) */ 6536 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff 6537 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0 6538 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1 6539 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1 6540 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1 6541 /* source MAC address to match (as bytes in network order) */ 6542 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44 6543 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6 6544 /* source port to match (as bytes in network order) */ 6545 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50 6546 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2 6547 /* destination MAC address to match (as bytes in network order) */ 6548 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52 6549 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6 6550 /* destination port to match (as bytes in network order) */ 6551 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58 6552 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2 6553 /* Ethernet type to match (as bytes in network order) */ 6554 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60 6555 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2 6556 /* Inner VLAN tag to match (as bytes in network order) */ 6557 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62 6558 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2 6559 /* Outer VLAN tag to match (as bytes in network order) */ 6560 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64 6561 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2 6562 /* IP protocol to match (in low byte; set high byte to 0) */ 6563 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66 6564 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2 6565 /* Firmware defined register 0 to match (reserved; set to 0) */ 6566 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68 6567 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP 6568 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for 6569 * VXLAN/NVGRE, or 1 for Geneve) 6570 */ 6571 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72 6572 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0 6573 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24 6574 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24 6575 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8 6576 /* enum: Match VXLAN traffic with this VNI */ 6577 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0 6578 /* enum: Match Geneve traffic with this VNI */ 6579 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1 6580 /* enum: Reserved for experimental development use */ 6581 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe 6582 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0 6583 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24 6584 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24 6585 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8 6586 /* enum: Match NVGRE traffic with this VSID */ 6587 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0 6588 /* source IP address to match (as bytes in network order; set last 12 bytes to 6589 * 0 for IPv4 address) 6590 */ 6591 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76 6592 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16 6593 /* destination IP address to match (as bytes in network order; set last 12 6594 * bytes to 0 for IPv4 address) 6595 */ 6596 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92 6597 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16 6598 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network 6599 * order) 6600 */ 6601 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108 6602 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6 6603 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ 6604 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114 6605 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2 6606 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in 6607 * network order) 6608 */ 6609 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116 6610 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6 6611 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network 6612 * order) 6613 */ 6614 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122 6615 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2 6616 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) 6617 */ 6618 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124 6619 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2 6620 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) 6621 */ 6622 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126 6623 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2 6624 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) 6625 */ 6626 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128 6627 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2 6628 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to 6629 * 0) 6630 */ 6631 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130 6632 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2 6633 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set 6634 * to 0) 6635 */ 6636 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132 6637 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set 6638 * to 0) 6639 */ 6640 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136 6641 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network 6642 * order; set last 12 bytes to 0 for IPv4 address) 6643 */ 6644 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140 6645 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16 6646 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network 6647 * order; set last 12 bytes to 0 for IPv4 address) 6648 */ 6649 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156 6650 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16 6651 6652 /* MC_CMD_FILTER_OP_OUT msgresponse */ 6653 #define MC_CMD_FILTER_OP_OUT_LEN 12 6654 /* identifies the type of operation requested */ 6655 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 6656 /* Enum values, see field(s): */ 6657 /* MC_CMD_FILTER_OP_IN/OP */ 6658 /* Returned filter handle (for insert / subscribe operations). Note that these 6659 * handles should be considered opaque to the host, although a value of 6660 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 6661 */ 6662 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 6663 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 6664 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 6665 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 6666 /* enum: guaranteed invalid filter handle (low 32 bits) */ 6667 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff 6668 /* enum: guaranteed invalid filter handle (high 32 bits) */ 6669 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff 6670 6671 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */ 6672 #define MC_CMD_FILTER_OP_EXT_OUT_LEN 12 6673 /* identifies the type of operation requested */ 6674 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0 6675 /* Enum values, see field(s): */ 6676 /* MC_CMD_FILTER_OP_EXT_IN/OP */ 6677 /* Returned filter handle (for insert / subscribe operations). Note that these 6678 * handles should be considered opaque to the host, although a value of 6679 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 6680 */ 6681 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4 6682 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8 6683 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4 6684 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8 6685 /* Enum values, see field(s): */ 6686 /* MC_CMD_FILTER_OP_OUT/HANDLE */ 6687 6688 6689 /***********************************/ 6690 /* MC_CMD_GET_PARSER_DISP_INFO 6691 * Get information related to the parser-dispatcher subsystem 6692 */ 6693 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 6694 6695 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6696 6697 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ 6698 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 6699 /* identifies the type of operation requested */ 6700 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 6701 /* enum: read the list of supported RX filter matches */ 6702 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 6703 /* enum: read flags indicating restrictions on filter insertion for the calling 6704 * client 6705 */ 6706 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2 6707 /* enum: read properties relating to security rules (Medford-only; for use by 6708 * SolarSecure apps, not directly by drivers. See SF-114946-SW.) 6709 */ 6710 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3 6711 /* enum: read the list of supported RX filter matches for VXLAN/NVGRE 6712 * encapsulated frames, which follow a different match sequence to normal 6713 * frames (Medford only) 6714 */ 6715 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4 6716 6717 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ 6718 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 6719 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 6720 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) 6721 /* identifies the type of operation requested */ 6722 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 6723 /* Enum values, see field(s): */ 6724 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 6725 /* number of supported match types */ 6726 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 6727 /* array of supported match types (valid MATCH_FIELDS values for 6728 * MC_CMD_FILTER_OP) sorted in decreasing priority order 6729 */ 6730 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 6731 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 6732 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 6733 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 6734 6735 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */ 6736 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8 6737 /* identifies the type of operation requested */ 6738 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0 6739 /* Enum values, see field(s): */ 6740 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 6741 /* bitfield of filter insertion restrictions */ 6742 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4 6743 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0 6744 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1 6745 6746 6747 /***********************************/ 6748 /* MC_CMD_PARSER_DISP_RW 6749 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging. 6750 * Please note that this interface is only of use to debug tools which have 6751 * knowledge of firmware and hardware data structures; nothing here is intended 6752 * for use by normal driver code. 6753 */ 6754 #define MC_CMD_PARSER_DISP_RW 0xe5 6755 6756 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6757 6758 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ 6759 #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 6760 /* identifies the target of the operation */ 6761 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 6762 /* enum: RX dispatcher CPU */ 6763 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 6764 /* enum: TX dispatcher CPU */ 6765 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 6766 /* enum: Lookup engine (with original metadata format) */ 6767 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 6768 /* enum: Lookup engine (with requested metadata format) */ 6769 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 6770 /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */ 6771 #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0 6772 /* enum: RX1 dispatcher CPU (only valid for Medford) */ 6773 #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4 6774 /* enum: Miscellaneous other state (only valid for Medford) */ 6775 #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5 6776 /* identifies the type of operation requested */ 6777 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 6778 /* enum: read a word of DICPU DMEM or a LUE entry */ 6779 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 6780 /* enum: write a word of DICPU DMEM or a LUE entry */ 6781 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 6782 /* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */ 6783 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 6784 /* data memory address (DICPU targets) or LUE index (LUE targets) */ 6785 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 6786 /* selector (for MISC_STATE target) */ 6787 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8 6788 /* enum: Port to datapath mapping */ 6789 #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1 6790 /* value to write (for DMEM writes) */ 6791 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 6792 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 6793 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 6794 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 6795 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 6796 /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */ 6797 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12 6798 /* value to write (for LUE writes) */ 6799 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 6800 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 6801 6802 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ 6803 #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 6804 /* value read (for DMEM reads) */ 6805 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 6806 /* value read (for LUE reads) */ 6807 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 6808 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 6809 /* up to 8 32-bit words of additional soft state from the LUE manager (the 6810 * exact content is firmware-dependent and intended only for debug use) 6811 */ 6812 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 6813 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 6814 /* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */ 6815 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0 6816 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4 6817 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4 6818 #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */ 6819 #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */ 6820 6821 6822 /***********************************/ 6823 /* MC_CMD_GET_PF_COUNT 6824 * Get number of PFs on the device. 6825 */ 6826 #define MC_CMD_GET_PF_COUNT 0xb6 6827 6828 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6829 6830 /* MC_CMD_GET_PF_COUNT_IN msgrequest */ 6831 #define MC_CMD_GET_PF_COUNT_IN_LEN 0 6832 6833 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 6834 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 6835 /* Identifies the number of PFs on the device. */ 6836 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 6837 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 6838 6839 6840 /***********************************/ 6841 /* MC_CMD_SET_PF_COUNT 6842 * Set number of PFs on the device. 6843 */ 6844 #define MC_CMD_SET_PF_COUNT 0xb7 6845 6846 /* MC_CMD_SET_PF_COUNT_IN msgrequest */ 6847 #define MC_CMD_SET_PF_COUNT_IN_LEN 4 6848 /* New number of PFs on the device. */ 6849 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 6850 6851 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 6852 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 6853 6854 6855 /***********************************/ 6856 /* MC_CMD_GET_PORT_ASSIGNMENT 6857 * Get port assignment for current PCI function. 6858 */ 6859 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 6860 6861 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6862 6863 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ 6864 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 6865 6866 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ 6867 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 6868 /* Identifies the port assignment for this function. */ 6869 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 6870 6871 6872 /***********************************/ 6873 /* MC_CMD_SET_PORT_ASSIGNMENT 6874 * Set port assignment for current PCI function. 6875 */ 6876 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 6877 6878 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6879 6880 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 6881 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 6882 /* Identifies the port assignment for this function. */ 6883 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 6884 6885 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 6886 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 6887 6888 6889 /***********************************/ 6890 /* MC_CMD_ALLOC_VIS 6891 * Allocate VIs for current PCI function. 6892 */ 6893 #define MC_CMD_ALLOC_VIS 0x8b 6894 6895 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6896 6897 /* MC_CMD_ALLOC_VIS_IN msgrequest */ 6898 #define MC_CMD_ALLOC_VIS_IN_LEN 8 6899 /* The minimum number of VIs that is acceptable */ 6900 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 6901 /* The maximum number of VIs that would be useful */ 6902 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 6903 6904 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request. 6905 * Use extended version in new code. 6906 */ 6907 #define MC_CMD_ALLOC_VIS_OUT_LEN 8 6908 /* The number of VIs allocated on this function */ 6909 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 6910 /* The base absolute VI number allocated to this function. Required to 6911 * correctly interpret wakeup events. 6912 */ 6913 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 6914 6915 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */ 6916 #define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12 6917 /* The number of VIs allocated on this function */ 6918 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0 6919 /* The base absolute VI number allocated to this function. Required to 6920 * correctly interpret wakeup events. 6921 */ 6922 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4 6923 /* Function's port vi_shift value (always 0 on Huntington) */ 6924 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 6925 6926 6927 /***********************************/ 6928 /* MC_CMD_FREE_VIS 6929 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, 6930 * but not freed. 6931 */ 6932 #define MC_CMD_FREE_VIS 0x8c 6933 6934 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6935 6936 /* MC_CMD_FREE_VIS_IN msgrequest */ 6937 #define MC_CMD_FREE_VIS_IN_LEN 0 6938 6939 /* MC_CMD_FREE_VIS_OUT msgresponse */ 6940 #define MC_CMD_FREE_VIS_OUT_LEN 0 6941 6942 6943 /***********************************/ 6944 /* MC_CMD_GET_SRIOV_CFG 6945 * Get SRIOV config for this PF. 6946 */ 6947 #define MC_CMD_GET_SRIOV_CFG 0xba 6948 6949 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6950 6951 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ 6952 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 6953 6954 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ 6955 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 6956 /* Number of VFs currently enabled. */ 6957 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 6958 /* Max number of VFs before sriov stride and offset may need to be changed. */ 6959 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 6960 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 6961 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 6962 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 6963 /* RID offset of first VF from PF. */ 6964 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 6965 /* RID offset of each subsequent VF from the previous. */ 6966 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 6967 6968 6969 /***********************************/ 6970 /* MC_CMD_SET_SRIOV_CFG 6971 * Set SRIOV config for this PF. 6972 */ 6973 #define MC_CMD_SET_SRIOV_CFG 0xbb 6974 6975 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6976 6977 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 6978 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 6979 /* Number of VFs currently enabled. */ 6980 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 6981 /* Max number of VFs before sriov stride and offset may need to be changed. */ 6982 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 6983 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 6984 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 6985 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 6986 /* RID offset of first VF from PF, or 0 for no change, or 6987 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. 6988 */ 6989 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 6990 /* RID offset of each subsequent VF from the previous, 0 for no change, or 6991 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. 6992 */ 6993 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 6994 6995 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 6996 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 6997 6998 6999 /***********************************/ 7000 /* MC_CMD_GET_VI_ALLOC_INFO 7001 * Get information about number of VI's and base VI number allocated to this 7002 * function. 7003 */ 7004 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d 7005 7006 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7007 7008 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ 7009 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 7010 7011 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ 7012 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 7013 /* The number of VIs allocated on this function */ 7014 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 7015 /* The base absolute VI number allocated to this function. Required to 7016 * correctly interpret wakeup events. 7017 */ 7018 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 7019 /* Function's port vi_shift value (always 0 on Huntington) */ 7020 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 7021 7022 7023 /***********************************/ 7024 /* MC_CMD_DUMP_VI_STATE 7025 * For CmdClient use. Dump pertinent information on a specific absolute VI. 7026 */ 7027 #define MC_CMD_DUMP_VI_STATE 0x8e 7028 7029 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7030 7031 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ 7032 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 7033 /* The VI number to query. */ 7034 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 7035 7036 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ 7037 #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 7038 /* The PF part of the function owning this VI. */ 7039 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 7040 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 7041 /* The VF part of the function owning this VI. */ 7042 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 7043 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 7044 /* Base of VIs allocated to this function. */ 7045 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 7046 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 7047 /* Count of VIs allocated to the owner function. */ 7048 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 7049 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 7050 /* Base interrupt vector allocated to this function. */ 7051 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 7052 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 7053 /* Number of interrupt vectors allocated to this function. */ 7054 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 7055 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 7056 /* Raw evq ptr table data. */ 7057 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 7058 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 7059 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 7060 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 7061 /* Raw evq timer table data. */ 7062 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 7063 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 7064 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 7065 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 7066 /* Combined metadata field. */ 7067 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 7068 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 7069 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 7070 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 7071 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 7072 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 7073 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 7074 /* TXDPCPU raw table data for queue. */ 7075 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 7076 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 7077 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 7078 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 7079 /* TXDPCPU raw table data for queue. */ 7080 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 7081 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 7082 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 7083 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 7084 /* TXDPCPU raw table data for queue. */ 7085 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 7086 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 7087 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 7088 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 7089 /* Combined metadata field. */ 7090 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 7091 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 7092 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 7093 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 7094 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 7095 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 7096 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 7097 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 7098 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 7099 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 7100 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 7101 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 7102 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 7103 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 7104 /* RXDPCPU raw table data for queue. */ 7105 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 7106 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 7107 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 7108 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 7109 /* RXDPCPU raw table data for queue. */ 7110 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 7111 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 7112 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 7113 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 7114 /* Reserved, currently 0. */ 7115 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 7116 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 7117 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 7118 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 7119 /* Combined metadata field. */ 7120 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 7121 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 7122 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 7123 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 7124 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 7125 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 7126 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 7127 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 7128 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 7129 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 7130 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 7131 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 7132 7133 7134 /***********************************/ 7135 /* MC_CMD_ALLOC_PIOBUF 7136 * Allocate a push I/O buffer for later use with a tx queue. 7137 */ 7138 #define MC_CMD_ALLOC_PIOBUF 0x8f 7139 7140 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 7141 7142 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ 7143 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 7144 7145 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ 7146 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 7147 /* Handle for allocated push I/O buffer. */ 7148 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 7149 7150 7151 /***********************************/ 7152 /* MC_CMD_FREE_PIOBUF 7153 * Free a push I/O buffer. 7154 */ 7155 #define MC_CMD_FREE_PIOBUF 0x90 7156 7157 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 7158 7159 /* MC_CMD_FREE_PIOBUF_IN msgrequest */ 7160 #define MC_CMD_FREE_PIOBUF_IN_LEN 4 7161 /* Handle for allocated push I/O buffer. */ 7162 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 7163 7164 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ 7165 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 7166 7167 7168 /***********************************/ 7169 /* MC_CMD_GET_VI_TLP_PROCESSING 7170 * Get TLP steering and ordering information for a VI. 7171 */ 7172 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 7173 7174 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7175 7176 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ 7177 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 7178 /* VI number to get information for. */ 7179 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 7180 7181 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ 7182 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 7183 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 7184 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 7185 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 7186 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 7187 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 7188 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 7189 /* Use Relaxed ordering model for TLPs on this VI. */ 7190 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 7191 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 7192 /* Use ID based ordering for TLPs on this VI. */ 7193 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 7194 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 7195 /* Set no snoop bit for TLPs on this VI. */ 7196 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 7197 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 7198 /* Enable TPH for TLPs on this VI. */ 7199 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 7200 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 7201 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 7202 7203 7204 /***********************************/ 7205 /* MC_CMD_SET_VI_TLP_PROCESSING 7206 * Set TLP steering and ordering information for a VI. 7207 */ 7208 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 7209 7210 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7211 7212 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ 7213 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 7214 /* VI number to set information for. */ 7215 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 7216 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 7217 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 7218 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 7219 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 7220 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 7221 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 7222 /* Use Relaxed ordering model for TLPs on this VI. */ 7223 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 7224 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 7225 /* Use ID based ordering for TLPs on this VI. */ 7226 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 7227 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 7228 /* Set the no snoop bit for TLPs on this VI. */ 7229 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 7230 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 7231 /* Enable TPH for TLPs on this VI. */ 7232 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 7233 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 7234 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 7235 7236 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ 7237 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 7238 7239 7240 /***********************************/ 7241 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS 7242 * Get global PCIe steering and transaction processing configuration. 7243 */ 7244 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc 7245 7246 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7247 7248 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 7249 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 7250 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 7251 /* enum: MISC. */ 7252 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 7253 /* enum: IDO. */ 7254 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 7255 /* enum: RO. */ 7256 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 7257 /* enum: TPH Type. */ 7258 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 7259 7260 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 7261 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 7262 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 7263 /* Enum values, see field(s): */ 7264 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 7265 /* Amalgamated TLP info word. */ 7266 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 7267 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 7268 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 7269 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 7270 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 7271 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 7272 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 7273 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 7274 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 7275 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 7276 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 7277 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 7278 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 7279 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 7280 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 7281 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 7282 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 7283 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 7284 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 7285 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 7286 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 7287 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 7288 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 7289 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 7290 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 7291 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 7292 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 7293 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 7294 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 7295 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 7296 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 7297 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 7298 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 7299 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 7300 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 7301 7302 7303 /***********************************/ 7304 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS 7305 * Set global PCIe steering and transaction processing configuration. 7306 */ 7307 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd 7308 7309 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7310 7311 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 7312 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 7313 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 7314 /* Enum values, see field(s): */ 7315 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 7316 /* Amalgamated TLP info word. */ 7317 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 7318 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 7319 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 7320 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 7321 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 7322 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 7323 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 7324 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 7325 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 7326 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 7327 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 7328 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 7329 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 7330 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 7331 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 7332 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 7333 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 7334 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 7335 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 7336 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 7337 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 7338 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 7339 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 7340 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 7341 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 7342 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 7343 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 7344 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 7345 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 7346 7347 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 7348 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 7349 7350 7351 /***********************************/ 7352 /* MC_CMD_SATELLITE_DOWNLOAD 7353 * Download a new set of images to the satellite CPUs from the host. 7354 */ 7355 #define MC_CMD_SATELLITE_DOWNLOAD 0x91 7356 7357 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7358 7359 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs 7360 * are subtle, and so downloads must proceed in a number of phases. 7361 * 7362 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. 7363 * 7364 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download 7365 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should 7366 * be a checksum (a simple 32-bit sum) of the transferred data. An individual 7367 * download may be aborted using CHUNK_ID_ABORT. 7368 * 7369 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), 7370 * similar to PHASE_IMEMS. 7371 * 7372 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. 7373 * 7374 * After any error (a requested abort is not considered to be an error) the 7375 * sequence must be restarted from PHASE_RESET. 7376 */ 7377 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 7378 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 7379 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) 7380 /* Download phase. (Note: the IDLE phase is used internally and is never valid 7381 * in a command from the host.) 7382 */ 7383 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 7384 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ 7385 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ 7386 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ 7387 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ 7388 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ 7389 /* Target for download. (These match the blob numbers defined in 7390 * mc_flash_layout.h.) 7391 */ 7392 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 7393 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7394 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 7395 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7396 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 7397 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7398 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 7399 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7400 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 7401 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7402 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 7403 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7404 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 7405 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7406 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 7407 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7408 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 7409 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7410 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 7411 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7412 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 7413 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7414 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa 7415 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7416 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb 7417 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 7418 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc 7419 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 7420 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd 7421 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 7422 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe 7423 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 7424 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf 7425 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ 7426 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff 7427 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ 7428 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 7429 /* enum: Last chunk, containing checksum rather than data */ 7430 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff 7431 /* enum: Abort download of this item */ 7432 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe 7433 /* Length of this chunk in bytes */ 7434 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 7435 /* Data for this chunk */ 7436 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 7437 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 7438 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 7439 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 7440 7441 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ 7442 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 7443 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 7444 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 7445 /* Extra status information */ 7446 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 7447 /* enum: Code download OK, completed. */ 7448 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 7449 /* enum: Code download aborted as requested. */ 7450 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 7451 /* enum: Code download OK so far, send next chunk. */ 7452 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 7453 /* enum: Download phases out of sequence */ 7454 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 7455 /* enum: Bad target for this phase */ 7456 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 7457 /* enum: Chunk ID out of sequence */ 7458 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 7459 /* enum: Chunk length zero or too large */ 7460 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 7461 /* enum: Checksum was incorrect */ 7462 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 7463 7464 7465 /***********************************/ 7466 /* MC_CMD_GET_CAPABILITIES 7467 * Get device capabilities. 7468 * 7469 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to 7470 * reference inherent device capabilities as opposed to current NVRAM config. 7471 */ 7472 #define MC_CMD_GET_CAPABILITIES 0xbe 7473 7474 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7475 7476 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */ 7477 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0 7478 7479 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ 7480 #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 7481 /* First word of flags. */ 7482 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 7483 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3 7484 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1 7485 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4 7486 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1 7487 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5 7488 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1 7489 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 7490 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 7491 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7 7492 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 7493 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8 7494 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 7495 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9 7496 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1 7497 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 7498 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 7499 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 7500 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 7501 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 7502 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 7503 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13 7504 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 7505 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14 7506 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1 7507 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 7508 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 7509 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16 7510 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1 7511 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17 7512 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1 7513 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18 7514 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1 7515 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 7516 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 7517 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 7518 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 7519 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 7520 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 7521 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 7522 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 7523 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 7524 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 7525 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 7526 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 7527 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 7528 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 7529 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 7530 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 7531 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 7532 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 7533 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28 7534 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1 7535 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 7536 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 7537 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30 7538 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1 7539 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31 7540 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1 7541 /* RxDPCPU firmware id. */ 7542 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 7543 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 7544 /* enum: Standard RXDP firmware */ 7545 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 7546 /* enum: Low latency RXDP firmware */ 7547 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 7548 /* enum: Packed stream RXDP firmware */ 7549 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2 7550 /* enum: BIST RXDP firmware */ 7551 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a 7552 /* enum: RXDP Test firmware image 1 */ 7553 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 7554 /* enum: RXDP Test firmware image 2 */ 7555 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 7556 /* enum: RXDP Test firmware image 3 */ 7557 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 7558 /* enum: RXDP Test firmware image 4 */ 7559 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 7560 /* enum: RXDP Test firmware image 5 */ 7561 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 7562 /* enum: RXDP Test firmware image 6 */ 7563 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 7564 /* enum: RXDP Test firmware image 7 */ 7565 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 7566 /* enum: RXDP Test firmware image 8 */ 7567 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 7568 /* enum: RXDP Test firmware image 9 */ 7569 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 7570 /* TxDPCPU firmware id. */ 7571 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 7572 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 7573 /* enum: Standard TXDP firmware */ 7574 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 7575 /* enum: Low latency TXDP firmware */ 7576 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 7577 /* enum: High packet rate TXDP firmware */ 7578 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3 7579 /* enum: BIST TXDP firmware */ 7580 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d 7581 /* enum: TXDP Test firmware image 1 */ 7582 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 7583 /* enum: TXDP Test firmware image 2 */ 7584 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 7585 /* enum: TXDP CSR bus test firmware */ 7586 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103 7587 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 7588 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 7589 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 7590 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 7591 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 7592 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 7593 /* enum: reserved value - do not use (may indicate alternative interpretation 7594 * of REV field in future) 7595 */ 7596 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0 7597 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 7598 * development only) 7599 */ 7600 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 7601 /* enum: RX PD firmware with approximately Siena-compatible behaviour 7602 * (Huntington development only) 7603 */ 7604 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 7605 /* enum: Virtual switching (full feature) RX PD production firmware */ 7606 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 7607 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 7608 * (Huntington development only) 7609 */ 7610 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 7611 /* enum: Low latency RX PD production firmware */ 7612 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 7613 /* enum: Packed stream RX PD production firmware */ 7614 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 7615 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 7616 * tests (Medford development only) 7617 */ 7618 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 7619 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 7620 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 7621 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 7622 * encapsulations (Medford development only) 7623 */ 7624 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 7625 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 7626 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 7627 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 7628 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 7629 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 7630 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 7631 /* enum: reserved value - do not use (may indicate alternative interpretation 7632 * of REV field in future) 7633 */ 7634 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0 7635 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 7636 * development only) 7637 */ 7638 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 7639 /* enum: TX PD firmware with approximately Siena-compatible behaviour 7640 * (Huntington development only) 7641 */ 7642 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 7643 /* enum: Virtual switching (full feature) TX PD production firmware */ 7644 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 7645 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 7646 * (Huntington development only) 7647 */ 7648 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 7649 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 7650 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 7651 * tests (Medford development only) 7652 */ 7653 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 7654 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 7655 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 7656 /* Hardware capabilities of NIC */ 7657 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 7658 /* Licensed capabilities */ 7659 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 7660 7661 /* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */ 7662 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0 7663 7664 /* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */ 7665 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72 7666 /* First word of flags. */ 7667 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0 7668 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3 7669 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1 7670 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4 7671 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1 7672 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5 7673 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1 7674 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 7675 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 7676 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7 7677 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 7678 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8 7679 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 7680 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9 7681 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1 7682 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 7683 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 7684 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 7685 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 7686 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 7687 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 7688 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13 7689 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 7690 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14 7691 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1 7692 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 7693 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 7694 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16 7695 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1 7696 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17 7697 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1 7698 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18 7699 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1 7700 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19 7701 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1 7702 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20 7703 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1 7704 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21 7705 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1 7706 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22 7707 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1 7708 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23 7709 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1 7710 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24 7711 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1 7712 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25 7713 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1 7714 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26 7715 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1 7716 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27 7717 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 7718 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28 7719 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1 7720 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 7721 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 7722 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30 7723 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1 7724 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31 7725 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1 7726 /* RxDPCPU firmware id. */ 7727 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4 7728 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2 7729 /* enum: Standard RXDP firmware */ 7730 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0 7731 /* enum: Low latency RXDP firmware */ 7732 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1 7733 /* enum: Packed stream RXDP firmware */ 7734 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2 7735 /* enum: BIST RXDP firmware */ 7736 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a 7737 /* enum: RXDP Test firmware image 1 */ 7738 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 7739 /* enum: RXDP Test firmware image 2 */ 7740 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 7741 /* enum: RXDP Test firmware image 3 */ 7742 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 7743 /* enum: RXDP Test firmware image 4 */ 7744 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 7745 /* enum: RXDP Test firmware image 5 */ 7746 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105 7747 /* enum: RXDP Test firmware image 6 */ 7748 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 7749 /* enum: RXDP Test firmware image 7 */ 7750 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 7751 /* enum: RXDP Test firmware image 8 */ 7752 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 7753 /* enum: RXDP Test firmware image 9 */ 7754 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 7755 /* TxDPCPU firmware id. */ 7756 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6 7757 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2 7758 /* enum: Standard TXDP firmware */ 7759 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0 7760 /* enum: Low latency TXDP firmware */ 7761 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1 7762 /* enum: High packet rate TXDP firmware */ 7763 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3 7764 /* enum: BIST TXDP firmware */ 7765 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d 7766 /* enum: TXDP Test firmware image 1 */ 7767 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 7768 /* enum: TXDP Test firmware image 2 */ 7769 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 7770 /* enum: TXDP CSR bus test firmware */ 7771 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103 7772 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8 7773 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2 7774 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0 7775 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12 7776 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12 7777 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 7778 /* enum: reserved value - do not use (may indicate alternative interpretation 7779 * of REV field in future) 7780 */ 7781 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0 7782 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 7783 * development only) 7784 */ 7785 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 7786 /* enum: RX PD firmware with approximately Siena-compatible behaviour 7787 * (Huntington development only) 7788 */ 7789 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 7790 /* enum: Virtual switching (full feature) RX PD production firmware */ 7791 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3 7792 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 7793 * (Huntington development only) 7794 */ 7795 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 7796 /* enum: Low latency RX PD production firmware */ 7797 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 7798 /* enum: Packed stream RX PD production firmware */ 7799 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 7800 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 7801 * tests (Medford development only) 7802 */ 7803 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 7804 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 7805 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 7806 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 7807 * encapsulations (Medford development only) 7808 */ 7809 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 7810 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10 7811 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2 7812 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0 7813 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12 7814 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12 7815 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 7816 /* enum: reserved value - do not use (may indicate alternative interpretation 7817 * of REV field in future) 7818 */ 7819 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0 7820 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 7821 * development only) 7822 */ 7823 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 7824 /* enum: TX PD firmware with approximately Siena-compatible behaviour 7825 * (Huntington development only) 7826 */ 7827 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 7828 /* enum: Virtual switching (full feature) TX PD production firmware */ 7829 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3 7830 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 7831 * (Huntington development only) 7832 */ 7833 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 7834 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 7835 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 7836 * tests (Medford development only) 7837 */ 7838 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 7839 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 7840 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 7841 /* Hardware capabilities of NIC */ 7842 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12 7843 /* Licensed capabilities */ 7844 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16 7845 /* Second word of flags. Not present on older firmware (check the length). */ 7846 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20 7847 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0 7848 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1 7849 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1 7850 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1 7851 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2 7852 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1 7853 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3 7854 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1 7855 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4 7856 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1 7857 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 7858 * on older firmware (check the length). 7859 */ 7860 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 7861 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 7862 /* One byte per PF containing the number of the external port assigned to this 7863 * PF, indexed by PF number. Special values indicate that a PF is either not 7864 * present or not assigned. 7865 */ 7866 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 7867 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 7868 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 7869 /* enum: The caller is not permitted to access information on this PF. */ 7870 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff 7871 /* enum: PF does not exist. */ 7872 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe 7873 /* enum: PF does exist but is not assigned to any external port. */ 7874 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd 7875 /* enum: This value indicates that PF is assigned, but it cannot be expressed 7876 * in this field. It is intended for a possible future situation where a more 7877 * complex scheme of PFs to ports mapping is being used. The future driver 7878 * should look for a new field supporting the new scheme. The current/old 7879 * driver should treat this value as PF_NOT_ASSIGNED. 7880 */ 7881 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 7882 /* One byte per PF containing the number of its VFs, indexed by PF number. A 7883 * special value indicates that a PF is not present. 7884 */ 7885 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42 7886 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1 7887 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16 7888 /* enum: The caller is not permitted to access information on this PF. */ 7889 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */ 7890 /* enum: PF does not exist. */ 7891 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */ 7892 /* Number of VIs available for each external port */ 7893 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58 7894 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2 7895 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4 7896 /* Size of RX descriptor cache expressed as binary logarithm The actual size 7897 * equals (2 ^ RX_DESC_CACHE_SIZE) 7898 */ 7899 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66 7900 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1 7901 /* Size of TX descriptor cache expressed as binary logarithm The actual size 7902 * equals (2 ^ TX_DESC_CACHE_SIZE) 7903 */ 7904 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67 7905 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1 7906 /* Total number of available PIO buffers */ 7907 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68 7908 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2 7909 /* Size of a single PIO buffer */ 7910 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70 7911 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2 7912 7913 7914 /***********************************/ 7915 /* MC_CMD_V2_EXTN 7916 * Encapsulation for a v2 extended command 7917 */ 7918 #define MC_CMD_V2_EXTN 0x7f 7919 7920 /* MC_CMD_V2_EXTN_IN msgrequest */ 7921 #define MC_CMD_V2_EXTN_IN_LEN 4 7922 /* the extended command number */ 7923 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 7924 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 7925 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 7926 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 7927 /* the actual length of the encapsulated command (which is not in the v1 7928 * header) 7929 */ 7930 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 7931 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 7932 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 7933 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6 7934 7935 7936 /***********************************/ 7937 /* MC_CMD_TCM_BUCKET_ALLOC 7938 * Allocate a pacer bucket (for qau rp or a snapper test) 7939 */ 7940 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 7941 7942 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7943 7944 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 7945 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 7946 7947 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 7948 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 7949 /* the bucket id */ 7950 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 7951 7952 7953 /***********************************/ 7954 /* MC_CMD_TCM_BUCKET_FREE 7955 * Free a pacer bucket 7956 */ 7957 #define MC_CMD_TCM_BUCKET_FREE 0xb3 7958 7959 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7960 7961 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 7962 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 7963 /* the bucket id */ 7964 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 7965 7966 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 7967 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 7968 7969 7970 /***********************************/ 7971 /* MC_CMD_TCM_BUCKET_INIT 7972 * Initialise pacer bucket with a given rate 7973 */ 7974 #define MC_CMD_TCM_BUCKET_INIT 0xb4 7975 7976 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7977 7978 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ 7979 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 7980 /* the bucket id */ 7981 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 7982 /* the rate in mbps */ 7983 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 7984 7985 /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */ 7986 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12 7987 /* the bucket id */ 7988 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0 7989 /* the rate in mbps */ 7990 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4 7991 /* the desired maximum fill level */ 7992 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8 7993 7994 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ 7995 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 7996 7997 7998 /***********************************/ 7999 /* MC_CMD_TCM_TXQ_INIT 8000 * Initialise txq in pacer with given options or set options 8001 */ 8002 #define MC_CMD_TCM_TXQ_INIT 0xb5 8003 8004 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8005 8006 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 8007 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 8008 /* the txq id */ 8009 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 8010 /* the static priority associated with the txq */ 8011 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 8012 /* bitmask of the priority queues this txq is inserted into when inserted. */ 8013 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 8014 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0 8015 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 8016 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1 8017 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1 8018 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2 8019 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1 8020 /* the reaction point (RP) bucket */ 8021 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 8022 /* an already reserved bucket (typically set to bucket associated with outer 8023 * vswitch) 8024 */ 8025 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 8026 /* an already reserved bucket (typically set to bucket associated with inner 8027 * vswitch) 8028 */ 8029 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 8030 /* the min bucket (typically for ETS/minimum bandwidth) */ 8031 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 8032 8033 /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */ 8034 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32 8035 /* the txq id */ 8036 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0 8037 /* the static priority associated with the txq */ 8038 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4 8039 /* bitmask of the priority queues this txq is inserted into when inserted. */ 8040 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8 8041 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0 8042 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 8043 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1 8044 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1 8045 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2 8046 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1 8047 /* the reaction point (RP) bucket */ 8048 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12 8049 /* an already reserved bucket (typically set to bucket associated with outer 8050 * vswitch) 8051 */ 8052 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16 8053 /* an already reserved bucket (typically set to bucket associated with inner 8054 * vswitch) 8055 */ 8056 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20 8057 /* the min bucket (typically for ETS/minimum bandwidth) */ 8058 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24 8059 /* the static priority associated with the txq */ 8060 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28 8061 8062 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 8063 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 8064 8065 8066 /***********************************/ 8067 /* MC_CMD_LINK_PIOBUF 8068 * Link a push I/O buffer to a TxQ 8069 */ 8070 #define MC_CMD_LINK_PIOBUF 0x92 8071 8072 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8073 8074 /* MC_CMD_LINK_PIOBUF_IN msgrequest */ 8075 #define MC_CMD_LINK_PIOBUF_IN_LEN 8 8076 /* Handle for allocated push I/O buffer. */ 8077 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 8078 /* Function Local Instance (VI) number. */ 8079 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 8080 8081 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ 8082 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 8083 8084 8085 /***********************************/ 8086 /* MC_CMD_UNLINK_PIOBUF 8087 * Unlink a push I/O buffer from a TxQ 8088 */ 8089 #define MC_CMD_UNLINK_PIOBUF 0x93 8090 8091 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8092 8093 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ 8094 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 8095 /* Function Local Instance (VI) number. */ 8096 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 8097 8098 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ 8099 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 8100 8101 8102 /***********************************/ 8103 /* MC_CMD_VSWITCH_ALLOC 8104 * allocate and initialise a v-switch. 8105 */ 8106 #define MC_CMD_VSWITCH_ALLOC 0x94 8107 8108 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8109 8110 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ 8111 #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 8112 /* The port to connect to the v-switch's upstream port. */ 8113 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 8114 /* The type of v-switch to create. */ 8115 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 8116 /* enum: VLAN */ 8117 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 8118 /* enum: VEB */ 8119 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 8120 /* enum: VEPA (obsolete) */ 8121 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 8122 /* enum: MUX */ 8123 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4 8124 /* enum: Snapper specific; semantics TBD */ 8125 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5 8126 /* Flags controlling v-port creation */ 8127 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 8128 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 8129 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 8130 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators, 8131 * this must be one or greated, and the attached v-ports must have exactly this 8132 * number of tags. For other v-switch types, this must be zero of greater, and 8133 * is an upper limit on the number of VLAN tags for attached v-ports. An error 8134 * will be returned if existing configuration means we can't support attached 8135 * v-ports with this number of tags. 8136 */ 8137 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 8138 8139 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ 8140 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 8141 8142 8143 /***********************************/ 8144 /* MC_CMD_VSWITCH_FREE 8145 * de-allocate a v-switch. 8146 */ 8147 #define MC_CMD_VSWITCH_FREE 0x95 8148 8149 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8150 8151 /* MC_CMD_VSWITCH_FREE_IN msgrequest */ 8152 #define MC_CMD_VSWITCH_FREE_IN_LEN 4 8153 /* The port to which the v-switch is connected. */ 8154 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 8155 8156 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ 8157 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 8158 8159 8160 /***********************************/ 8161 /* MC_CMD_VSWITCH_QUERY 8162 * read some config of v-switch. For now this command is an empty placeholder. 8163 * It may be used to check if a v-switch is connected to a given EVB port (if 8164 * not, then the command returns ENOENT). 8165 */ 8166 #define MC_CMD_VSWITCH_QUERY 0x63 8167 8168 #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8169 8170 /* MC_CMD_VSWITCH_QUERY_IN msgrequest */ 8171 #define MC_CMD_VSWITCH_QUERY_IN_LEN 4 8172 /* The port to which the v-switch is connected. */ 8173 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 8174 8175 /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */ 8176 #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0 8177 8178 8179 /***********************************/ 8180 /* MC_CMD_VPORT_ALLOC 8181 * allocate a v-port. 8182 */ 8183 #define MC_CMD_VPORT_ALLOC 0x96 8184 8185 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8186 8187 /* MC_CMD_VPORT_ALLOC_IN msgrequest */ 8188 #define MC_CMD_VPORT_ALLOC_IN_LEN 20 8189 /* The port to which the v-switch is connected. */ 8190 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 8191 /* The type of the new v-port. */ 8192 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 8193 /* enum: VLAN (obsolete) */ 8194 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 8195 /* enum: VEB (obsolete) */ 8196 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 8197 /* enum: VEPA (obsolete) */ 8198 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 8199 /* enum: A normal v-port receives packets which match a specified MAC and/or 8200 * VLAN. 8201 */ 8202 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 8203 /* enum: An expansion v-port packets traffic which don't match any other 8204 * v-port. 8205 */ 8206 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 8207 /* enum: An test v-port receives packets which match any filters installed by 8208 * its downstream components. 8209 */ 8210 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 8211 /* Flags controlling v-port creation */ 8212 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 8213 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 8214 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 8215 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1 8216 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1 8217 /* The number of VLAN tags to insert/remove. An error will be returned if 8218 * incompatible with the number of VLAN tags specified for the upstream 8219 * v-switch. 8220 */ 8221 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 8222 /* The actual VLAN tags to insert/remove */ 8223 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 8224 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 8225 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 8226 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 8227 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 8228 8229 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */ 8230 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4 8231 /* The handle of the new v-port */ 8232 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 8233 8234 8235 /***********************************/ 8236 /* MC_CMD_VPORT_FREE 8237 * de-allocate a v-port. 8238 */ 8239 #define MC_CMD_VPORT_FREE 0x97 8240 8241 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8242 8243 /* MC_CMD_VPORT_FREE_IN msgrequest */ 8244 #define MC_CMD_VPORT_FREE_IN_LEN 4 8245 /* The handle of the v-port */ 8246 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 8247 8248 /* MC_CMD_VPORT_FREE_OUT msgresponse */ 8249 #define MC_CMD_VPORT_FREE_OUT_LEN 0 8250 8251 8252 /***********************************/ 8253 /* MC_CMD_VADAPTOR_ALLOC 8254 * allocate a v-adaptor. 8255 */ 8256 #define MC_CMD_VADAPTOR_ALLOC 0x98 8257 8258 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8259 8260 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ 8261 #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30 8262 /* The port to connect to the v-adaptor's port. */ 8263 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 8264 /* Flags controlling v-adaptor creation */ 8265 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 8266 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 8267 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 8268 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1 8269 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 8270 /* The number of VLAN tags to strip on receive */ 8271 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 8272 /* The number of VLAN tags to transparently insert/remove. */ 8273 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16 8274 /* The actual VLAN tags to insert/remove */ 8275 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20 8276 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0 8277 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16 8278 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16 8279 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16 8280 /* The MAC address to assign to this v-adaptor */ 8281 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24 8282 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6 8283 /* enum: Derive the MAC address from the upstream port */ 8284 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0 8285 8286 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ 8287 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 8288 8289 8290 /***********************************/ 8291 /* MC_CMD_VADAPTOR_FREE 8292 * de-allocate a v-adaptor. 8293 */ 8294 #define MC_CMD_VADAPTOR_FREE 0x99 8295 8296 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8297 8298 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */ 8299 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4 8300 /* The port to which the v-adaptor is connected. */ 8301 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 8302 8303 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ 8304 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 8305 8306 8307 /***********************************/ 8308 /* MC_CMD_VADAPTOR_SET_MAC 8309 * assign a new MAC address to a v-adaptor. 8310 */ 8311 #define MC_CMD_VADAPTOR_SET_MAC 0x5d 8312 8313 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8314 8315 /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */ 8316 #define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10 8317 /* The port to which the v-adaptor is connected. */ 8318 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 8319 /* The new MAC address to assign to this v-adaptor */ 8320 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4 8321 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6 8322 8323 /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ 8324 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 8325 8326 8327 /***********************************/ 8328 /* MC_CMD_VADAPTOR_GET_MAC 8329 * read the MAC address assigned to a v-adaptor. 8330 */ 8331 #define MC_CMD_VADAPTOR_GET_MAC 0x5e 8332 8333 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8334 8335 /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ 8336 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 8337 /* The port to which the v-adaptor is connected. */ 8338 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 8339 8340 /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ 8341 #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 8342 /* The MAC address assigned to this v-adaptor */ 8343 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 8344 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 8345 8346 8347 /***********************************/ 8348 /* MC_CMD_VADAPTOR_QUERY 8349 * read some config of v-adaptor. 8350 */ 8351 #define MC_CMD_VADAPTOR_QUERY 0x61 8352 8353 #define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8354 8355 /* MC_CMD_VADAPTOR_QUERY_IN msgrequest */ 8356 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4 8357 /* The port to which the v-adaptor is connected. */ 8358 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 8359 8360 /* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */ 8361 #define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12 8362 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 8363 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0 8364 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */ 8365 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4 8366 /* The number of VLAN tags that may still be added */ 8367 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8 8368 8369 8370 /***********************************/ 8371 /* MC_CMD_EVB_PORT_ASSIGN 8372 * assign a port to a PCI function. 8373 */ 8374 #define MC_CMD_EVB_PORT_ASSIGN 0x9a 8375 8376 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8377 8378 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ 8379 #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 8380 /* The port to assign. */ 8381 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 8382 /* The target function to modify. */ 8383 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 8384 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 8385 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 8386 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 8387 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 8388 8389 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ 8390 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 8391 8392 8393 /***********************************/ 8394 /* MC_CMD_RDWR_A64_REGIONS 8395 * Assign the 64 bit region addresses. 8396 */ 8397 #define MC_CMD_RDWR_A64_REGIONS 0x9b 8398 8399 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8400 8401 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ 8402 #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 8403 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 8404 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 8405 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 8406 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 8407 /* Write enable bits 0-3, set to write, clear to read. */ 8408 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 8409 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 8410 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 8411 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 8412 8413 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included 8414 * regardless of state of write bits in the request. 8415 */ 8416 #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 8417 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 8418 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 8419 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 8420 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 8421 8422 8423 /***********************************/ 8424 /* MC_CMD_ONLOAD_STACK_ALLOC 8425 * Allocate an Onload stack ID. 8426 */ 8427 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c 8428 8429 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8430 8431 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ 8432 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 8433 /* The handle of the owning upstream port */ 8434 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 8435 8436 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ 8437 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 8438 /* The handle of the new Onload stack */ 8439 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 8440 8441 8442 /***********************************/ 8443 /* MC_CMD_ONLOAD_STACK_FREE 8444 * Free an Onload stack ID. 8445 */ 8446 #define MC_CMD_ONLOAD_STACK_FREE 0x9d 8447 8448 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8449 8450 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ 8451 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 8452 /* The handle of the Onload stack */ 8453 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 8454 8455 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ 8456 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 8457 8458 8459 /***********************************/ 8460 /* MC_CMD_RSS_CONTEXT_ALLOC 8461 * Allocate an RSS context. 8462 */ 8463 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e 8464 8465 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8466 8467 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ 8468 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 8469 /* The handle of the owning upstream port */ 8470 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 8471 /* The type of context to allocate */ 8472 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 8473 /* enum: Allocate a context for exclusive use. The key and indirection table 8474 * must be explicitly configured. 8475 */ 8476 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 8477 /* enum: Allocate a context for shared use; this will spread across a range of 8478 * queues, but the key and indirection table are pre-configured and may not be 8479 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. 8480 */ 8481 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 8482 /* Number of queues spanned by this context, in the range 1-64; valid offsets 8483 * in the indirection table will be in the range 0 to NUM_QUEUES-1. 8484 */ 8485 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 8486 8487 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ 8488 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 8489 /* The handle of the new RSS context. This should be considered opaque to the 8490 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 8491 * handle. 8492 */ 8493 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 8494 /* enum: guaranteed invalid RSS context handle value */ 8495 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff 8496 8497 8498 /***********************************/ 8499 /* MC_CMD_RSS_CONTEXT_FREE 8500 * Free an RSS context. 8501 */ 8502 #define MC_CMD_RSS_CONTEXT_FREE 0x9f 8503 8504 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8505 8506 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ 8507 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 8508 /* The handle of the RSS context */ 8509 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 8510 8511 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ 8512 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 8513 8514 8515 /***********************************/ 8516 /* MC_CMD_RSS_CONTEXT_SET_KEY 8517 * Set the Toeplitz hash key for an RSS context. 8518 */ 8519 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 8520 8521 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8522 8523 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ 8524 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 8525 /* The handle of the RSS context */ 8526 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 8527 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 8528 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 8529 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 8530 8531 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ 8532 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 8533 8534 8535 /***********************************/ 8536 /* MC_CMD_RSS_CONTEXT_GET_KEY 8537 * Get the Toeplitz hash key for an RSS context. 8538 */ 8539 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 8540 8541 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8542 8543 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ 8544 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 8545 /* The handle of the RSS context */ 8546 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 8547 8548 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ 8549 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 8550 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 8551 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 8552 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 8553 8554 8555 /***********************************/ 8556 /* MC_CMD_RSS_CONTEXT_SET_TABLE 8557 * Set the indirection table for an RSS context. 8558 */ 8559 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 8560 8561 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8562 8563 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ 8564 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 8565 /* The handle of the RSS context */ 8566 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 8567 /* The 128-byte indirection table (1 byte per entry) */ 8568 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 8569 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 8570 8571 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ 8572 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 8573 8574 8575 /***********************************/ 8576 /* MC_CMD_RSS_CONTEXT_GET_TABLE 8577 * Get the indirection table for an RSS context. 8578 */ 8579 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 8580 8581 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8582 8583 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ 8584 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 8585 /* The handle of the RSS context */ 8586 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 8587 8588 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ 8589 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 8590 /* The 128-byte indirection table (1 byte per entry) */ 8591 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 8592 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 8593 8594 8595 /***********************************/ 8596 /* MC_CMD_RSS_CONTEXT_SET_FLAGS 8597 * Set various control flags for an RSS context. 8598 */ 8599 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 8600 8601 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8602 8603 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ 8604 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 8605 /* The handle of the RSS context */ 8606 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 8607 /* Hash control flags. The _EN bits are always supported, but new modes are 8608 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES: 8609 * in this case, the MODE fields may be set to non-zero values, and will take 8610 * effect regardless of the settings of the _EN flags. See the RSS_MODE 8611 * structure for the meaning of the mode bits. Drivers must check the 8612 * capability before trying to set any _MODE fields, as older firmware will 8613 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In 8614 * the case where all the _MODE flags are zero, the _EN flags take effect, 8615 * providing backward compatibility for existing drivers. (Setting all _MODE 8616 * *and* all _EN flags to zero is valid, to disable RSS spreading for that 8617 * particular packet type.) 8618 */ 8619 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 8620 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 8621 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 8622 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 8623 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 8624 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 8625 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 8626 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 8627 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 8628 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4 8629 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4 8630 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8 8631 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4 8632 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12 8633 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4 8634 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16 8635 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4 8636 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20 8637 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4 8638 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24 8639 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4 8640 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28 8641 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4 8642 8643 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ 8644 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 8645 8646 8647 /***********************************/ 8648 /* MC_CMD_RSS_CONTEXT_GET_FLAGS 8649 * Get various control flags for an RSS context. 8650 */ 8651 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 8652 8653 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8654 8655 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ 8656 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 8657 /* The handle of the RSS context */ 8658 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 8659 8660 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ 8661 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 8662 /* Hash control flags. If all _MODE bits are zero (which will always be true 8663 * for older firmware which does not report the ADDITIONAL_RSS_MODES 8664 * capability), the _EN bits report the state. If any _MODE bits are non-zero 8665 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES) 8666 * then the _EN bits should be disregarded, although the _MODE flags are 8667 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS 8668 * context and in the case where the _EN flags were used in the SET. This 8669 * provides backward compatibility: old drivers will not be attempting to 8670 * derive any meaning from the _MODE bits (and can never set them to any value 8671 * not representable by the _EN bits); new drivers can always determine the 8672 * mode by looking only at the _MODE bits; the value returned by a GET can 8673 * always be used for a SET regardless of old/new driver vs. old/new firmware. 8674 */ 8675 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 8676 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 8677 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 8678 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 8679 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 8680 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 8681 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 8682 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 8683 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 8684 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4 8685 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4 8686 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8 8687 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4 8688 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12 8689 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4 8690 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16 8691 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4 8692 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20 8693 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4 8694 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24 8695 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4 8696 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 8697 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 8698 8699 8700 /***********************************/ 8701 /* MC_CMD_DOT1P_MAPPING_ALLOC 8702 * Allocate a .1p mapping. 8703 */ 8704 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 8705 8706 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8707 8708 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ 8709 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 8710 /* The handle of the owning upstream port */ 8711 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 8712 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed 8713 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and 8714 * referenced RSS contexts must span no more than this number. 8715 */ 8716 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 8717 8718 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ 8719 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 8720 /* The handle of the new .1p mapping. This should be considered opaque to the 8721 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 8722 * handle. 8723 */ 8724 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 8725 /* enum: guaranteed invalid .1p mapping handle value */ 8726 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff 8727 8728 8729 /***********************************/ 8730 /* MC_CMD_DOT1P_MAPPING_FREE 8731 * Free a .1p mapping. 8732 */ 8733 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 8734 8735 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8736 8737 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ 8738 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 8739 /* The handle of the .1p mapping */ 8740 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 8741 8742 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ 8743 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 8744 8745 8746 /***********************************/ 8747 /* MC_CMD_DOT1P_MAPPING_SET_TABLE 8748 * Set the mapping table for a .1p mapping. 8749 */ 8750 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 8751 8752 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8753 8754 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ 8755 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 8756 /* The handle of the .1p mapping */ 8757 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 8758 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 8759 * handle) 8760 */ 8761 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 8762 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 8763 8764 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ 8765 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 8766 8767 8768 /***********************************/ 8769 /* MC_CMD_DOT1P_MAPPING_GET_TABLE 8770 * Get the mapping table for a .1p mapping. 8771 */ 8772 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 8773 8774 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8775 8776 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ 8777 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 8778 /* The handle of the .1p mapping */ 8779 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 8780 8781 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ 8782 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 8783 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 8784 * handle) 8785 */ 8786 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 8787 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 8788 8789 8790 /***********************************/ 8791 /* MC_CMD_GET_VECTOR_CFG 8792 * Get Interrupt Vector config for this PF. 8793 */ 8794 #define MC_CMD_GET_VECTOR_CFG 0xbf 8795 8796 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8797 8798 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 8799 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 8800 8801 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 8802 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 8803 /* Base absolute interrupt vector number. */ 8804 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 8805 /* Number of interrupt vectors allocate to this PF. */ 8806 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 8807 /* Number of interrupt vectors to allocate per VF. */ 8808 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 8809 8810 8811 /***********************************/ 8812 /* MC_CMD_SET_VECTOR_CFG 8813 * Set Interrupt Vector config for this PF. 8814 */ 8815 #define MC_CMD_SET_VECTOR_CFG 0xc0 8816 8817 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8818 8819 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 8820 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 8821 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to 8822 * let the system find a suitable base. 8823 */ 8824 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 8825 /* Number of interrupt vectors allocate to this PF. */ 8826 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 8827 /* Number of interrupt vectors to allocate per VF. */ 8828 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 8829 8830 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 8831 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 8832 8833 8834 /***********************************/ 8835 /* MC_CMD_VPORT_ADD_MAC_ADDRESS 8836 * Add a MAC address to a v-port 8837 */ 8838 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 8839 8840 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8841 8842 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ 8843 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 8844 /* The handle of the v-port */ 8845 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 8846 /* MAC address to add */ 8847 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 8848 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 8849 8850 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ 8851 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 8852 8853 8854 /***********************************/ 8855 /* MC_CMD_VPORT_DEL_MAC_ADDRESS 8856 * Delete a MAC address from a v-port 8857 */ 8858 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 8859 8860 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8861 8862 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ 8863 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 8864 /* The handle of the v-port */ 8865 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 8866 /* MAC address to add */ 8867 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 8868 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 8869 8870 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ 8871 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 8872 8873 8874 /***********************************/ 8875 /* MC_CMD_VPORT_GET_MAC_ADDRESSES 8876 * Delete a MAC address from a v-port 8877 */ 8878 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa 8879 8880 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8881 8882 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ 8883 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 8884 /* The handle of the v-port */ 8885 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 8886 8887 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ 8888 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 8889 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 8890 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) 8891 /* The number of MAC addresses returned */ 8892 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 8893 /* Array of MAC addresses */ 8894 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 8895 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 8896 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 8897 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 8898 8899 8900 /***********************************/ 8901 /* MC_CMD_VPORT_RECONFIGURE 8902 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port 8903 * has already been passed to another function (v-port's user), then that 8904 * function will be reset before applying the changes. 8905 */ 8906 #define MC_CMD_VPORT_RECONFIGURE 0xeb 8907 8908 #define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8909 8910 /* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */ 8911 #define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44 8912 /* The handle of the v-port */ 8913 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0 8914 /* Flags requesting what should be changed. */ 8915 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4 8916 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0 8917 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1 8918 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1 8919 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1 8920 /* The number of VLAN tags to insert/remove. An error will be returned if 8921 * incompatible with the number of VLAN tags specified for the upstream 8922 * v-switch. 8923 */ 8924 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8 8925 /* The actual VLAN tags to insert/remove */ 8926 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12 8927 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0 8928 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16 8929 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16 8930 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16 8931 /* The number of MAC addresses to add */ 8932 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16 8933 /* MAC addresses to add */ 8934 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20 8935 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6 8936 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4 8937 8938 /* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */ 8939 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4 8940 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0 8941 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0 8942 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1 8943 8944 8945 /***********************************/ 8946 /* MC_CMD_EVB_PORT_QUERY 8947 * read some config of v-port. 8948 */ 8949 #define MC_CMD_EVB_PORT_QUERY 0x62 8950 8951 #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8952 8953 /* MC_CMD_EVB_PORT_QUERY_IN msgrequest */ 8954 #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4 8955 /* The handle of the v-port */ 8956 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0 8957 8958 /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */ 8959 #define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8 8960 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 8961 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0 8962 /* The number of VLAN tags that may be used on a v-adaptor connected to this 8963 * EVB port. 8964 */ 8965 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4 8966 8967 8968 /***********************************/ 8969 /* MC_CMD_DUMP_BUFTBL_ENTRIES 8970 * Dump buffer table entries, mainly for command client debug use. Dumps 8971 * absolute entries, and does not use chunk handles. All entries must be in 8972 * range, and used for q page mapping, Although the latter restriction may be 8973 * lifted in future. 8974 */ 8975 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab 8976 8977 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8978 8979 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ 8980 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 8981 /* Index of the first buffer table entry. */ 8982 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 8983 /* Number of buffer table entries to dump. */ 8984 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 8985 8986 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ 8987 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 8988 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 8989 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) 8990 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ 8991 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 8992 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 8993 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 8994 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 8995 8996 8997 /***********************************/ 8998 /* MC_CMD_SET_RXDP_CONFIG 8999 * Set global RXDP configuration settings 9000 */ 9001 #define MC_CMD_SET_RXDP_CONFIG 0xc1 9002 9003 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9004 9005 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ 9006 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 9007 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 9008 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 9009 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 9010 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1 9011 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2 9012 /* enum: pad to 64 bytes */ 9013 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0 9014 /* enum: pad to 128 bytes (Medford only) */ 9015 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1 9016 /* enum: pad to 256 bytes (Medford only) */ 9017 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2 9018 9019 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ 9020 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 9021 9022 9023 /***********************************/ 9024 /* MC_CMD_GET_RXDP_CONFIG 9025 * Get global RXDP configuration settings 9026 */ 9027 #define MC_CMD_GET_RXDP_CONFIG 0xc2 9028 9029 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9030 9031 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ 9032 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 9033 9034 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ 9035 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 9036 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 9037 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 9038 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 9039 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1 9040 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2 9041 /* Enum values, see field(s): */ 9042 /* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */ 9043 9044 9045 /***********************************/ 9046 /* MC_CMD_GET_CLOCK 9047 * Return the system and PDCPU clock frequencies. 9048 */ 9049 #define MC_CMD_GET_CLOCK 0xac 9050 9051 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9052 9053 /* MC_CMD_GET_CLOCK_IN msgrequest */ 9054 #define MC_CMD_GET_CLOCK_IN_LEN 0 9055 9056 /* MC_CMD_GET_CLOCK_OUT msgresponse */ 9057 #define MC_CMD_GET_CLOCK_OUT_LEN 8 9058 /* System frequency, MHz */ 9059 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 9060 /* DPCPU frequency, MHz */ 9061 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 9062 9063 9064 /***********************************/ 9065 /* MC_CMD_SET_CLOCK 9066 * Control the system and DPCPU clock frequencies. Changes are lost reboot. 9067 */ 9068 #define MC_CMD_SET_CLOCK 0xad 9069 9070 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9071 9072 /* MC_CMD_SET_CLOCK_IN msgrequest */ 9073 #define MC_CMD_SET_CLOCK_IN_LEN 28 9074 /* Requested frequency in MHz for system clock domain */ 9075 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 9076 /* enum: Leave the system clock domain frequency unchanged */ 9077 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0 9078 /* Requested frequency in MHz for inter-core clock domain */ 9079 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 9080 /* enum: Leave the inter-core clock domain frequency unchanged */ 9081 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0 9082 /* Requested frequency in MHz for DPCPU clock domain */ 9083 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 9084 /* enum: Leave the DPCPU clock domain frequency unchanged */ 9085 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0 9086 /* Requested frequency in MHz for PCS clock domain */ 9087 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12 9088 /* enum: Leave the PCS clock domain frequency unchanged */ 9089 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0 9090 /* Requested frequency in MHz for MC clock domain */ 9091 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16 9092 /* enum: Leave the MC clock domain frequency unchanged */ 9093 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0 9094 /* Requested frequency in MHz for rmon clock domain */ 9095 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20 9096 /* enum: Leave the rmon clock domain frequency unchanged */ 9097 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0 9098 /* Requested frequency in MHz for vswitch clock domain */ 9099 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24 9100 /* enum: Leave the vswitch clock domain frequency unchanged */ 9101 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0 9102 9103 /* MC_CMD_SET_CLOCK_OUT msgresponse */ 9104 #define MC_CMD_SET_CLOCK_OUT_LEN 28 9105 /* Resulting system frequency in MHz */ 9106 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 9107 /* enum: The system clock domain doesn't exist */ 9108 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0 9109 /* Resulting inter-core frequency in MHz */ 9110 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 9111 /* enum: The inter-core clock domain doesn't exist / isn't used */ 9112 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0 9113 /* Resulting DPCPU frequency in MHz */ 9114 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 9115 /* enum: The dpcpu clock domain doesn't exist */ 9116 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0 9117 /* Resulting PCS frequency in MHz */ 9118 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12 9119 /* enum: The PCS clock domain doesn't exist / isn't controlled */ 9120 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0 9121 /* Resulting MC frequency in MHz */ 9122 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16 9123 /* enum: The MC clock domain doesn't exist / isn't controlled */ 9124 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0 9125 /* Resulting rmon frequency in MHz */ 9126 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20 9127 /* enum: The rmon clock domain doesn't exist / isn't controlled */ 9128 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0 9129 /* Resulting vswitch frequency in MHz */ 9130 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24 9131 /* enum: The vswitch clock domain doesn't exist / isn't controlled */ 9132 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 9133 9134 9135 /***********************************/ 9136 /* MC_CMD_DPCPU_RPC 9137 * Send an arbitrary DPCPU message. 9138 */ 9139 #define MC_CMD_DPCPU_RPC 0xae 9140 9141 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9142 9143 /* MC_CMD_DPCPU_RPC_IN msgrequest */ 9144 #define MC_CMD_DPCPU_RPC_IN_LEN 36 9145 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 9146 /* enum: RxDPCPU0 */ 9147 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0 9148 /* enum: TxDPCPU0 */ 9149 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 9150 /* enum: TxDPCPU1 */ 9151 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 9152 /* enum: RxDPCPU1 (Medford only) */ 9153 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3 9154 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of 9155 * DPCPU_RX0) 9156 */ 9157 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80 9158 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of 9159 * DPCPU_TX0) 9160 */ 9161 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81 9162 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be 9163 * initialised to zero 9164 */ 9165 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 9166 #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 9167 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 9168 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 9169 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ 9170 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ 9171 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ 9172 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ 9173 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ 9174 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ 9175 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ 9176 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ 9177 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ 9178 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 9179 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 9180 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 9181 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 9182 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 9183 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 9184 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 9185 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 9186 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 9187 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 9188 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ 9189 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ 9190 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ 9191 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ 9192 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ 9193 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 9194 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 9195 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 9196 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 9197 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 9198 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 9199 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 9200 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 9201 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ 9202 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ 9203 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ 9204 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 9205 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 9206 #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 9207 #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 9208 /* Register data to write. Only valid in write/write-read. */ 9209 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 9210 /* Register address. */ 9211 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 9212 9213 /* MC_CMD_DPCPU_RPC_OUT msgresponse */ 9214 #define MC_CMD_DPCPU_RPC_OUT_LEN 36 9215 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 9216 /* DATA */ 9217 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 9218 #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 9219 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 9220 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 9221 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 9222 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 9223 #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 9224 #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 9225 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 9226 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 9227 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 9228 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 9229 9230 9231 /***********************************/ 9232 /* MC_CMD_TRIGGER_INTERRUPT 9233 * Trigger an interrupt by prodding the BIU. 9234 */ 9235 #define MC_CMD_TRIGGER_INTERRUPT 0xe3 9236 9237 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9238 9239 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ 9240 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 9241 /* Interrupt level relative to base for function. */ 9242 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 9243 9244 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ 9245 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 9246 9247 9248 /***********************************/ 9249 /* MC_CMD_SHMBOOT_OP 9250 * Special operations to support (for now) shmboot. 9251 */ 9252 #define MC_CMD_SHMBOOT_OP 0xe6 9253 9254 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9255 9256 /* MC_CMD_SHMBOOT_OP_IN msgrequest */ 9257 #define MC_CMD_SHMBOOT_OP_IN_LEN 4 9258 /* Identifies the operation to perform */ 9259 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0 9260 /* enum: Copy slave_data section to the slave core. (Greenport only) */ 9261 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0 9262 9263 /* MC_CMD_SHMBOOT_OP_OUT msgresponse */ 9264 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0 9265 9266 9267 /***********************************/ 9268 /* MC_CMD_CAP_BLK_READ 9269 * Read multiple 64bit words from capture block memory 9270 */ 9271 #define MC_CMD_CAP_BLK_READ 0xe7 9272 9273 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9274 9275 /* MC_CMD_CAP_BLK_READ_IN msgrequest */ 9276 #define MC_CMD_CAP_BLK_READ_IN_LEN 12 9277 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 9278 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 9279 #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 9280 9281 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */ 9282 #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 9283 #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 9284 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) 9285 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 9286 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 9287 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 9288 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 9289 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 9290 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 9291 9292 9293 /***********************************/ 9294 /* MC_CMD_DUMP_DO 9295 * Take a dump of the DUT state 9296 */ 9297 #define MC_CMD_DUMP_DO 0xe8 9298 9299 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9300 9301 /* MC_CMD_DUMP_DO_IN msgrequest */ 9302 #define MC_CMD_DUMP_DO_IN_LEN 52 9303 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 9304 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 9305 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ 9306 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ 9307 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 9308 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ 9309 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ 9310 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ 9311 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ 9312 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 9313 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 9314 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 9315 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 9316 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 9317 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ 9318 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 9319 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 9320 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ 9321 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 9322 /* enum: The uart port this command was received over (if using a uart 9323 * transport) 9324 */ 9325 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff 9326 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 9327 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 9328 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ 9329 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ 9330 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 9331 /* Enum values, see field(s): */ 9332 /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 9333 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 9334 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 9335 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 9336 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 9337 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 9338 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 9339 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 9340 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 9341 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 9342 9343 /* MC_CMD_DUMP_DO_OUT msgresponse */ 9344 #define MC_CMD_DUMP_DO_OUT_LEN 4 9345 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 9346 9347 9348 /***********************************/ 9349 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED 9350 * Configure unsolicited dumps 9351 */ 9352 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 9353 9354 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9355 9356 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ 9357 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 9358 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 9359 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 9360 /* Enum values, see field(s): */ 9361 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ 9362 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 9363 /* Enum values, see field(s): */ 9364 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 9365 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 9366 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 9367 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 9368 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 9369 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 9370 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 9371 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 9372 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 9373 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 9374 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 9375 /* Enum values, see field(s): */ 9376 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ 9377 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 9378 /* Enum values, see field(s): */ 9379 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 9380 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 9381 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 9382 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 9383 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 9384 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 9385 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 9386 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 9387 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 9388 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 9389 9390 9391 /***********************************/ 9392 /* MC_CMD_SET_PSU 9393 * Adjusts power supply parameters. This is a warranty-voiding operation. 9394 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if 9395 * the parameter is out of range. 9396 */ 9397 #define MC_CMD_SET_PSU 0xea 9398 9399 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9400 9401 /* MC_CMD_SET_PSU_IN msgrequest */ 9402 #define MC_CMD_SET_PSU_IN_LEN 12 9403 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 9404 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ 9405 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 9406 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ 9407 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ 9408 /* desired value, eg voltage in mV */ 9409 #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 9410 9411 /* MC_CMD_SET_PSU_OUT msgresponse */ 9412 #define MC_CMD_SET_PSU_OUT_LEN 0 9413 9414 9415 /***********************************/ 9416 /* MC_CMD_GET_FUNCTION_INFO 9417 * Get function information. PF and VF number. 9418 */ 9419 #define MC_CMD_GET_FUNCTION_INFO 0xec 9420 9421 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9422 9423 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ 9424 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 9425 9426 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ 9427 #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 9428 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 9429 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 9430 9431 9432 /***********************************/ 9433 /* MC_CMD_ENABLE_OFFLINE_BIST 9434 * Enters offline BIST mode. All queues are torn down, chip enters quiescent 9435 * mode, calling function gets exclusive MCDI ownership. The only way out is 9436 * reboot. 9437 */ 9438 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed 9439 9440 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9441 9442 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ 9443 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 9444 9445 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ 9446 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 9447 9448 9449 /***********************************/ 9450 /* MC_CMD_UART_SEND_DATA 9451 * Send checksummed[sic] block of data over the uart. Response is a placeholder 9452 * should we wish to make this reliable; currently requests are fire-and- 9453 * forget. 9454 */ 9455 #define MC_CMD_UART_SEND_DATA 0xee 9456 9457 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9458 9459 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */ 9460 #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 9461 #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 9462 #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) 9463 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ 9464 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 9465 /* Offset at which to write the data */ 9466 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 9467 /* Length of data */ 9468 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 9469 /* Reserved for future use */ 9470 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 9471 #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 9472 #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 9473 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 9474 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 9475 9476 /* MC_CMD_UART_SEND_DATA_IN msgresponse */ 9477 #define MC_CMD_UART_SEND_DATA_IN_LEN 0 9478 9479 9480 /***********************************/ 9481 /* MC_CMD_UART_RECV_DATA 9482 * Request checksummed[sic] block of data over the uart. Only a placeholder, 9483 * subject to change and not currently implemented. 9484 */ 9485 #define MC_CMD_UART_RECV_DATA 0xef 9486 9487 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9488 9489 /* MC_CMD_UART_RECV_DATA_OUT msgrequest */ 9490 #define MC_CMD_UART_RECV_DATA_OUT_LEN 16 9491 /* CRC32 over OFFSET, LENGTH, RESERVED */ 9492 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 9493 /* Offset from which to read the data */ 9494 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 9495 /* Length of data */ 9496 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 9497 /* Reserved for future use */ 9498 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 9499 9500 /* MC_CMD_UART_RECV_DATA_IN msgresponse */ 9501 #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 9502 #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 9503 #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) 9504 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ 9505 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 9506 /* Offset at which to write the data */ 9507 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 9508 /* Length of data */ 9509 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 9510 /* Reserved for future use */ 9511 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 9512 #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 9513 #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 9514 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 9515 #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 9516 9517 9518 /***********************************/ 9519 /* MC_CMD_READ_FUSES 9520 * Read data programmed into the device One-Time-Programmable (OTP) Fuses 9521 */ 9522 #define MC_CMD_READ_FUSES 0xf0 9523 9524 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9525 9526 /* MC_CMD_READ_FUSES_IN msgrequest */ 9527 #define MC_CMD_READ_FUSES_IN_LEN 8 9528 /* Offset in OTP to read */ 9529 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 9530 /* Length of data to read in bytes */ 9531 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 9532 9533 /* MC_CMD_READ_FUSES_OUT msgresponse */ 9534 #define MC_CMD_READ_FUSES_OUT_LENMIN 4 9535 #define MC_CMD_READ_FUSES_OUT_LENMAX 252 9536 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) 9537 /* Length of returned OTP data in bytes */ 9538 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 9539 /* Returned data */ 9540 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 9541 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 9542 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 9543 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 9544 9545 9546 /***********************************/ 9547 /* MC_CMD_KR_TUNE 9548 * Get or set KR Serdes RXEQ and TX Driver settings 9549 */ 9550 #define MC_CMD_KR_TUNE 0xf1 9551 9552 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9553 9554 /* MC_CMD_KR_TUNE_IN msgrequest */ 9555 #define MC_CMD_KR_TUNE_IN_LENMIN 4 9556 #define MC_CMD_KR_TUNE_IN_LENMAX 252 9557 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) 9558 /* Requested operation */ 9559 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 9560 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 9561 /* enum: Get current RXEQ settings */ 9562 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 9563 /* enum: Override RXEQ settings */ 9564 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 9565 /* enum: Get current TX Driver settings */ 9566 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 9567 /* enum: Override TX Driver settings */ 9568 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 9569 /* enum: Force KR Serdes reset / recalibration */ 9570 #define MC_CMD_KR_TUNE_IN_RECAL 0x4 9571 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid 9572 * signal. 9573 */ 9574 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 9575 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The 9576 * caller should call this command repeatedly after starting eye plot, until no 9577 * more data is returned. 9578 */ 9579 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 9580 /* enum: Read Figure Of Merit (eye quality, higher is better). */ 9581 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7 9582 /* Align the arguments to 32 bits */ 9583 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 9584 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 9585 /* Arguments specific to the operation */ 9586 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 9587 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 9588 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 9589 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 9590 9591 /* MC_CMD_KR_TUNE_OUT msgresponse */ 9592 #define MC_CMD_KR_TUNE_OUT_LEN 0 9593 9594 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ 9595 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 9596 /* Requested operation */ 9597 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 9598 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 9599 /* Align the arguments to 32 bits */ 9600 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 9601 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 9602 9603 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ 9604 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 9605 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 9606 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 9607 /* RXEQ Parameter */ 9608 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 9609 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 9610 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 9611 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 9612 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 9613 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 9614 /* enum: Attenuation (0-15, Huntington) */ 9615 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 9616 /* enum: CTLE Boost (0-15, Huntington) */ 9617 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 9618 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max 9619 * positive, Medford - 0-31) 9620 */ 9621 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 9622 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max 9623 * positive, Medford - 0-31) 9624 */ 9625 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 9626 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max 9627 * positive, Medford - 0-16) 9628 */ 9629 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 9630 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max 9631 * positive, Medford - 0-16) 9632 */ 9633 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 9634 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max 9635 * positive, Medford - 0-16) 9636 */ 9637 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 9638 /* enum: Edge DFE DLEV (0-128 for Medford) */ 9639 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 9640 /* enum: Variable Gain Amplifier (0-15, Medford) */ 9641 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8 9642 /* enum: CTLE EQ Capacitor (0-15, Medford) */ 9643 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 9644 /* enum: CTLE EQ Resistor (0-7, Medford) */ 9645 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 9646 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 9647 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 9648 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 9649 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 9650 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 9651 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 9652 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 9653 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 9654 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 9655 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 9656 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 9657 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 9658 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 9659 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 9660 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 9661 9662 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ 9663 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 9664 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 9665 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 9666 /* Requested operation */ 9667 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 9668 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 9669 /* Align the arguments to 32 bits */ 9670 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 9671 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 9672 /* RXEQ Parameter */ 9673 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 9674 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 9675 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 9676 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 9677 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 9678 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 9679 /* Enum values, see field(s): */ 9680 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ 9681 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 9682 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 9683 /* Enum values, see field(s): */ 9684 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 9685 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 9686 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 9687 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 9688 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 9689 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 9690 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 9691 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 9692 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 9693 9694 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ 9695 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 9696 9697 /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ 9698 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 9699 /* Requested operation */ 9700 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 9701 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 9702 /* Align the arguments to 32 bits */ 9703 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 9704 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 9705 9706 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ 9707 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 9708 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 9709 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 9710 /* TXEQ Parameter */ 9711 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 9712 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 9713 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 9714 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 9715 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 9716 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 9717 /* enum: TX Amplitude (Huntington, Medford) */ 9718 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 9719 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */ 9720 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 9721 /* enum: De-Emphasis Tap1 Fine */ 9722 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 9723 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */ 9724 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 9725 /* enum: De-Emphasis Tap2 Fine (Huntington) */ 9726 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 9727 /* enum: Pre-Emphasis Magnitude (Huntington) */ 9728 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 9729 /* enum: Pre-Emphasis Fine (Huntington) */ 9730 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 9731 /* enum: TX Slew Rate Coarse control (Huntington) */ 9732 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 9733 /* enum: TX Slew Rate Fine control (Huntington) */ 9734 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 9735 /* enum: TX Termination Impedance control (Huntington) */ 9736 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 9737 /* enum: TX Amplitude Fine control (Medford) */ 9738 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa 9739 /* enum: Pre-shoot Tap (Medford) */ 9740 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb 9741 /* enum: De-emphasis Tap (Medford) */ 9742 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc 9743 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 9744 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 9745 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ 9746 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ 9747 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ 9748 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ 9749 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 9750 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 9751 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 9752 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 9753 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 9754 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 9755 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 9756 9757 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ 9758 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 9759 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 9760 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) 9761 /* Requested operation */ 9762 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 9763 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 9764 /* Align the arguments to 32 bits */ 9765 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 9766 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 9767 /* TXEQ Parameter */ 9768 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 9769 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 9770 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 9771 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 9772 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 9773 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 9774 /* Enum values, see field(s): */ 9775 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ 9776 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 9777 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 9778 /* Enum values, see field(s): */ 9779 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ 9780 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 9781 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 9782 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 9783 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 9784 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 9785 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 9786 9787 /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ 9788 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 9789 9790 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ 9791 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 9792 /* Requested operation */ 9793 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 9794 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 9795 /* Align the arguments to 32 bits */ 9796 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 9797 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 9798 9799 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ 9800 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 9801 9802 /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ 9803 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 9804 /* Requested operation */ 9805 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 9806 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 9807 /* Align the arguments to 32 bits */ 9808 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 9809 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 9810 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 9811 9812 /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ 9813 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 9814 9815 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ 9816 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 9817 /* Requested operation */ 9818 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 9819 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 9820 /* Align the arguments to 32 bits */ 9821 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 9822 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 9823 9824 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 9825 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 9826 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 9827 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 9828 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 9829 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 9830 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 9831 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 9832 9833 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */ 9834 #define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8 9835 /* Requested operation */ 9836 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0 9837 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1 9838 /* Align the arguments to 32 bits */ 9839 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1 9840 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3 9841 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4 9842 9843 /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */ 9844 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4 9845 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0 9846 9847 9848 /***********************************/ 9849 /* MC_CMD_PCIE_TUNE 9850 * Get or set PCIE Serdes RXEQ and TX Driver settings 9851 */ 9852 #define MC_CMD_PCIE_TUNE 0xf2 9853 9854 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9855 9856 /* MC_CMD_PCIE_TUNE_IN msgrequest */ 9857 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 9858 #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 9859 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) 9860 /* Requested operation */ 9861 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 9862 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 9863 /* enum: Get current RXEQ settings */ 9864 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 9865 /* enum: Override RXEQ settings */ 9866 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 9867 /* enum: Get current TX Driver settings */ 9868 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 9869 /* enum: Override TX Driver settings */ 9870 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 9871 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ 9872 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 9873 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The 9874 * caller should call this command repeatedly after starting eye plot, until no 9875 * more data is returned. 9876 */ 9877 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 9878 /* Align the arguments to 32 bits */ 9879 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 9880 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 9881 /* Arguments specific to the operation */ 9882 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 9883 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 9884 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 9885 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 9886 9887 /* MC_CMD_PCIE_TUNE_OUT msgresponse */ 9888 #define MC_CMD_PCIE_TUNE_OUT_LEN 0 9889 9890 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ 9891 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 9892 /* Requested operation */ 9893 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 9894 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 9895 /* Align the arguments to 32 bits */ 9896 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 9897 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 9898 9899 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ 9900 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 9901 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 9902 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 9903 /* RXEQ Parameter */ 9904 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 9905 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 9906 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 9907 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 9908 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 9909 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 9910 /* enum: Attenuation (0-15) */ 9911 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 9912 /* enum: CTLE Boost (0-15) */ 9913 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 9914 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 9915 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 9916 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 9917 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 9918 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 9919 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 9920 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 9921 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 9922 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 9923 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 9924 /* enum: DFE DLev */ 9925 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7 9926 /* enum: Figure of Merit */ 9927 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8 9928 /* enum: CTLE EQ Capacitor (HF Gain) */ 9929 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 9930 /* enum: CTLE EQ Resistor (DC Gain) */ 9931 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 9932 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 9933 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5 9934 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 9935 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 9936 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 9937 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 9938 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ 9939 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ 9940 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ 9941 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ 9942 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */ 9943 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */ 9944 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */ 9945 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */ 9946 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */ 9947 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */ 9948 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */ 9949 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */ 9950 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */ 9951 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13 9952 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 9953 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14 9954 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10 9955 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 9956 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 9957 9958 /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */ 9959 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8 9960 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252 9961 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 9962 /* Requested operation */ 9963 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0 9964 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1 9965 /* Align the arguments to 32 bits */ 9966 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1 9967 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3 9968 /* RXEQ Parameter */ 9969 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4 9970 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4 9971 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 9972 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 9973 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 9974 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 9975 /* Enum values, see field(s): */ 9976 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */ 9977 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 9978 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5 9979 /* Enum values, see field(s): */ 9980 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 9981 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13 9982 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 9983 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14 9984 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2 9985 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 9986 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 9987 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 9988 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 9989 9990 /* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */ 9991 #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0 9992 9993 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ 9994 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 9995 /* Requested operation */ 9996 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 9997 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 9998 /* Align the arguments to 32 bits */ 9999 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 10000 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 10001 10002 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ 10003 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 10004 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 10005 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 10006 /* RXEQ Parameter */ 10007 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 10008 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 10009 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 10010 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 10011 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 10012 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 10013 /* enum: TxMargin (PIPE) */ 10014 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 10015 /* enum: TxSwing (PIPE) */ 10016 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 10017 /* enum: De-emphasis coefficient C(-1) (PIPE) */ 10018 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 10019 /* enum: De-emphasis coefficient C(0) (PIPE) */ 10020 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 10021 /* enum: De-emphasis coefficient C(+1) (PIPE) */ 10022 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 10023 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 10024 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 10025 /* Enum values, see field(s): */ 10026 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 10027 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 10028 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 10029 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 10030 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 10031 10032 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ 10033 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 10034 /* Requested operation */ 10035 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 10036 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 10037 /* Align the arguments to 32 bits */ 10038 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 10039 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 10040 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 10041 10042 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ 10043 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 10044 10045 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ 10046 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 10047 /* Requested operation */ 10048 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 10049 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 10050 /* Align the arguments to 32 bits */ 10051 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 10052 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 10053 10054 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 10055 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 10056 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 10057 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 10058 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 10059 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 10060 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 10061 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 10062 10063 10064 /***********************************/ 10065 /* MC_CMD_LICENSING 10066 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 10067 * - not used for V3 licensing 10068 */ 10069 #define MC_CMD_LICENSING 0xf3 10070 10071 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10072 10073 /* MC_CMD_LICENSING_IN msgrequest */ 10074 #define MC_CMD_LICENSING_IN_LEN 4 10075 /* identifies the type of operation requested */ 10076 #define MC_CMD_LICENSING_IN_OP_OFST 0 10077 /* enum: re-read and apply licenses after a license key partition update; note 10078 * that this operation returns a zero-length response 10079 */ 10080 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 10081 /* enum: report counts of installed licenses */ 10082 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 10083 10084 /* MC_CMD_LICENSING_OUT msgresponse */ 10085 #define MC_CMD_LICENSING_OUT_LEN 28 10086 /* count of application keys which are valid */ 10087 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 10088 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with 10089 * MC_CMD_FC_OP_LICENSE) 10090 */ 10091 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 10092 /* count of application keys which are invalid due to being blacklisted */ 10093 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 10094 /* count of application keys which are invalid due to being unverifiable */ 10095 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 10096 /* count of application keys which are invalid due to being for the wrong node 10097 */ 10098 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 10099 /* licensing state (for diagnostics; the exact meaning of the bits in this 10100 * field are private to the firmware) 10101 */ 10102 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 10103 /* licensing subsystem self-test report (for manftest) */ 10104 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 10105 /* enum: licensing subsystem self-test failed */ 10106 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 10107 /* enum: licensing subsystem self-test passed */ 10108 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 10109 10110 10111 /***********************************/ 10112 /* MC_CMD_LICENSING_V3 10113 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 10114 * - V3 licensing (Medford) 10115 */ 10116 #define MC_CMD_LICENSING_V3 0xd0 10117 10118 #define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10119 10120 /* MC_CMD_LICENSING_V3_IN msgrequest */ 10121 #define MC_CMD_LICENSING_V3_IN_LEN 4 10122 /* identifies the type of operation requested */ 10123 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0 10124 /* enum: re-read and apply licenses after a license key partition update; note 10125 * that this operation returns a zero-length response 10126 */ 10127 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0 10128 /* enum: report counts of installed licenses */ 10129 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1 10130 10131 /* MC_CMD_LICENSING_V3_OUT msgresponse */ 10132 #define MC_CMD_LICENSING_V3_OUT_LEN 88 10133 /* count of keys which are valid */ 10134 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0 10135 /* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with 10136 * MC_CMD_FC_OP_LICENSE) 10137 */ 10138 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4 10139 /* count of keys which are invalid due to being unverifiable */ 10140 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8 10141 /* count of keys which are invalid due to being for the wrong node */ 10142 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12 10143 /* licensing state (for diagnostics; the exact meaning of the bits in this 10144 * field are private to the firmware) 10145 */ 10146 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16 10147 /* licensing subsystem self-test report (for manftest) */ 10148 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20 10149 /* enum: licensing subsystem self-test failed */ 10150 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0 10151 /* enum: licensing subsystem self-test passed */ 10152 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1 10153 /* bitmask of licensed applications */ 10154 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24 10155 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8 10156 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24 10157 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28 10158 /* reserved for future use */ 10159 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32 10160 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24 10161 /* bitmask of licensed features */ 10162 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56 10163 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8 10164 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56 10165 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60 10166 /* reserved for future use */ 10167 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64 10168 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24 10169 10170 10171 /***********************************/ 10172 /* MC_CMD_LICENSING_GET_ID_V3 10173 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license 10174 * partition - V3 licensing (Medford) 10175 */ 10176 #define MC_CMD_LICENSING_GET_ID_V3 0xd1 10177 10178 #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10179 10180 /* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */ 10181 #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0 10182 10183 /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */ 10184 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8 10185 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252 10186 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num)) 10187 /* type of license (eg 3) */ 10188 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0 10189 /* length of the license ID (in bytes) */ 10190 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4 10191 /* the unique license ID of the adapter */ 10192 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8 10193 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1 10194 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0 10195 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244 10196 10197 10198 /***********************************/ 10199 /* MC_CMD_MC2MC_PROXY 10200 * Execute an arbitrary MCDI command on the slave MC of a dual-core device. 10201 * This will fail on a single-core system. 10202 */ 10203 #define MC_CMD_MC2MC_PROXY 0xf4 10204 10205 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10206 10207 /* MC_CMD_MC2MC_PROXY_IN msgrequest */ 10208 #define MC_CMD_MC2MC_PROXY_IN_LEN 0 10209 10210 /* MC_CMD_MC2MC_PROXY_OUT msgresponse */ 10211 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0 10212 10213 10214 /***********************************/ 10215 /* MC_CMD_GET_LICENSED_APP_STATE 10216 * Query the state of an individual licensed application. (Note that the actual 10217 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation 10218 * or a reboot of the MC.) Not used for V3 licensing 10219 */ 10220 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5 10221 10222 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10223 10224 /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ 10225 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 10226 /* application ID to query (LICENSED_APP_ID_xxx) */ 10227 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 10228 10229 /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ 10230 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 10231 /* state of this application */ 10232 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 10233 /* enum: no (or invalid) license is present for the application */ 10234 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 10235 /* enum: a valid license is present for the application */ 10236 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 10237 10238 10239 /***********************************/ 10240 /* MC_CMD_GET_LICENSED_V3_APP_STATE 10241 * Query the state of an individual licensed application. (Note that the actual 10242 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 10243 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 10244 */ 10245 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2 10246 10247 #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10248 10249 /* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */ 10250 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8 10251 /* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit 10252 * mask 10253 */ 10254 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0 10255 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8 10256 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0 10257 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4 10258 10259 /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */ 10260 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4 10261 /* state of this application */ 10262 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0 10263 /* enum: no (or invalid) license is present for the application */ 10264 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0 10265 /* enum: a valid license is present for the application */ 10266 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1 10267 10268 10269 /***********************************/ 10270 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES 10271 * Query the state of an one or more licensed features. (Note that the actual 10272 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 10273 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 10274 */ 10275 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3 10276 10277 #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10278 10279 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */ 10280 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8 10281 /* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or 10282 * more bits set 10283 */ 10284 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0 10285 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8 10286 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0 10287 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4 10288 10289 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */ 10290 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8 10291 /* states of these features - bit set for licensed, clear for not licensed */ 10292 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0 10293 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8 10294 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0 10295 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4 10296 10297 10298 /***********************************/ 10299 /* MC_CMD_LICENSED_APP_OP 10300 * Perform an action for an individual licensed application - not used for V3 10301 * licensing. 10302 */ 10303 #define MC_CMD_LICENSED_APP_OP 0xf6 10304 10305 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10306 10307 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */ 10308 #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 10309 #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 10310 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) 10311 /* application ID */ 10312 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 10313 /* the type of operation requested */ 10314 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 10315 /* enum: validate application */ 10316 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 10317 /* enum: mask application */ 10318 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1 10319 /* arguments specific to this particular operation */ 10320 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 10321 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 10322 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 10323 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 10324 10325 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ 10326 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 10327 #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 10328 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) 10329 /* result specific to this particular operation */ 10330 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 10331 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 10332 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 10333 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 10334 10335 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ 10336 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 10337 /* application ID */ 10338 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 10339 /* the type of operation requested */ 10340 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 10341 /* validation challenge */ 10342 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 10343 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 10344 10345 /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ 10346 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 10347 /* feature expiry (time_t) */ 10348 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 10349 /* validation response */ 10350 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 10351 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 10352 10353 /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */ 10354 #define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12 10355 /* application ID */ 10356 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0 10357 /* the type of operation requested */ 10358 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4 10359 /* flag */ 10360 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8 10361 10362 /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ 10363 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 10364 10365 10366 /***********************************/ 10367 /* MC_CMD_LICENSED_V3_VALIDATE_APP 10368 * Perform validation for an individual licensed application - V3 licensing 10369 * (Medford) 10370 */ 10371 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4 10372 10373 #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10374 10375 /* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */ 10376 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 72 10377 /* application ID expressed as a single bit mask */ 10378 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 0 10379 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8 10380 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 0 10381 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 4 10382 /* challenge for validation */ 10383 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 8 10384 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 64 10385 10386 /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */ 10387 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 72 10388 /* application expiry time */ 10389 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 0 10390 /* application expiry units */ 10391 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 4 10392 /* enum: expiry units are accounting units */ 10393 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0 10394 /* enum: expiry units are calendar days */ 10395 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1 10396 /* validation response to challenge */ 10397 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 8 10398 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 64 10399 10400 10401 /***********************************/ 10402 /* MC_CMD_LICENSED_V3_MASK_FEATURES 10403 * Mask features - V3 licensing (Medford) 10404 */ 10405 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5 10406 10407 #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10408 10409 /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */ 10410 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12 10411 /* mask to be applied to features to be changed */ 10412 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0 10413 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8 10414 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0 10415 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4 10416 /* whether to turn on or turn off the masked features */ 10417 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8 10418 /* enum: turn the features off */ 10419 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0 10420 /* enum: turn the features back on */ 10421 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1 10422 10423 /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */ 10424 #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0 10425 10426 10427 /***********************************/ 10428 /* MC_CMD_SET_PORT_SNIFF_CONFIG 10429 * Configure RX port sniffing for the physical port associated with the calling 10430 * function. Only a privileged function may change the port sniffing 10431 * configuration. A copy of all traffic delivered to the host (non-promiscuous 10432 * mode) or all traffic arriving at the port (promiscuous mode) may be 10433 * delivered to a specific queue, or a set of queues with RSS. 10434 */ 10435 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 10436 10437 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10438 10439 /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ 10440 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 10441 /* configuration flags */ 10442 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 10443 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 10444 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 10445 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 10446 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 10447 /* receive queue handle (for RSS mode, this is the base queue) */ 10448 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 10449 /* receive mode */ 10450 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 10451 /* enum: receive to just the specified queue */ 10452 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 10453 /* enum: receive to multiple queues using RSS context */ 10454 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 10455 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 10456 * that these handles should be considered opaque to the host, although a value 10457 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 10458 */ 10459 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 10460 10461 /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ 10462 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 10463 10464 10465 /***********************************/ 10466 /* MC_CMD_GET_PORT_SNIFF_CONFIG 10467 * Obtain the current RX port sniffing configuration for the physical port 10468 * associated with the calling function. Only a privileged function may read 10469 * the configuration. 10470 */ 10471 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 10472 10473 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10474 10475 /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ 10476 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 10477 10478 /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ 10479 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 10480 /* configuration flags */ 10481 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 10482 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 10483 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 10484 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 10485 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 10486 /* receiving queue handle (for RSS mode, this is the base queue) */ 10487 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 10488 /* receive mode */ 10489 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 10490 /* enum: receiving to just the specified queue */ 10491 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 10492 /* enum: receiving to multiple queues using RSS context */ 10493 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 10494 /* RSS context (for RX_MODE_RSS) */ 10495 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 10496 10497 10498 /***********************************/ 10499 /* MC_CMD_SET_PARSER_DISP_CONFIG 10500 * Change configuration related to the parser-dispatcher subsystem. 10501 */ 10502 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9 10503 10504 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10505 10506 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */ 10507 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12 10508 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252 10509 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num)) 10510 /* the type of configuration setting to change */ 10511 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 10512 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible 10513 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.) 10514 */ 10515 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0 10516 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the 10517 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single 10518 * boolean.) 10519 */ 10520 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1 10521 /* handle for the entity to update: queue handle, EVB port ID, etc. depending 10522 * on the type of configuration setting being changed 10523 */ 10524 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 10525 /* new value: the details depend on the type of configuration setting being 10526 * changed 10527 */ 10528 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8 10529 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4 10530 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1 10531 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61 10532 10533 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ 10534 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 10535 10536 10537 /***********************************/ 10538 /* MC_CMD_GET_PARSER_DISP_CONFIG 10539 * Read configuration related to the parser-dispatcher subsystem. 10540 */ 10541 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa 10542 10543 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10544 10545 /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */ 10546 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8 10547 /* the type of configuration setting to read */ 10548 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 10549 /* Enum values, see field(s): */ 10550 /* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */ 10551 /* handle for the entity to query: queue handle, EVB port ID, etc. depending on 10552 * the type of configuration setting being read 10553 */ 10554 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 10555 10556 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */ 10557 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4 10558 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252 10559 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) 10560 /* current value: the details depend on the type of configuration setting being 10561 * read 10562 */ 10563 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0 10564 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4 10565 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 10566 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 10567 10568 10569 /***********************************/ 10570 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG 10571 * Configure TX port sniffing for the physical port associated with the calling 10572 * function. Only a privileged function may change the port sniffing 10573 * configuration. A copy of all traffic transmitted through the port may be 10574 * delivered to a specific queue, or a set of queues with RSS. Note that these 10575 * packets are delivered with transmit timestamps in the packet prefix, not 10576 * receive timestamps, so it is likely that the queue(s) will need to be 10577 * dedicated as TX sniff receivers. 10578 */ 10579 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb 10580 10581 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10582 10583 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 10584 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16 10585 /* configuration flags */ 10586 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 10587 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 10588 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 10589 /* receive queue handle (for RSS mode, this is the base queue) */ 10590 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 10591 /* receive mode */ 10592 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 10593 /* enum: receive to just the specified queue */ 10594 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 10595 /* enum: receive to multiple queues using RSS context */ 10596 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 10597 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 10598 * that these handles should be considered opaque to the host, although a value 10599 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 10600 */ 10601 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 10602 10603 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 10604 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 10605 10606 10607 /***********************************/ 10608 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG 10609 * Obtain the current TX port sniffing configuration for the physical port 10610 * associated with the calling function. Only a privileged function may read 10611 * the configuration. 10612 */ 10613 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc 10614 10615 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10616 10617 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 10618 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0 10619 10620 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 10621 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16 10622 /* configuration flags */ 10623 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 10624 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 10625 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 10626 /* receiving queue handle (for RSS mode, this is the base queue) */ 10627 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 10628 /* receive mode */ 10629 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 10630 /* enum: receiving to just the specified queue */ 10631 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 10632 /* enum: receiving to multiple queues using RSS context */ 10633 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 10634 /* RSS context (for RX_MODE_RSS) */ 10635 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 10636 10637 10638 /***********************************/ 10639 /* MC_CMD_RMON_STATS_RX_ERRORS 10640 * Per queue rx error stats. 10641 */ 10642 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe 10643 10644 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10645 10646 /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */ 10647 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8 10648 /* The rx queue to get stats for. */ 10649 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0 10650 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4 10651 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0 10652 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1 10653 10654 /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */ 10655 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16 10656 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0 10657 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4 10658 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8 10659 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 10660 10661 10662 /***********************************/ 10663 /* MC_CMD_GET_PCIE_RESOURCE_INFO 10664 * Find out about available PCIE resources 10665 */ 10666 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd 10667 10668 /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */ 10669 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0 10670 10671 /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */ 10672 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28 10673 /* The maximum number of PFs the device can expose */ 10674 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0 10675 /* The maximum number of VFs the device can expose in total */ 10676 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4 10677 /* The maximum number of MSI-X vectors the device can provide in total */ 10678 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8 10679 /* the number of MSI-X vectors the device will allocate by default to each PF 10680 */ 10681 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12 10682 /* the number of MSI-X vectors the device will allocate by default to each VF 10683 */ 10684 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16 10685 /* the maximum number of MSI-X vectors the device can allocate to any one PF */ 10686 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20 10687 /* the maximum number of MSI-X vectors the device can allocate to any one VF */ 10688 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 10689 10690 10691 /***********************************/ 10692 /* MC_CMD_GET_PORT_MODES 10693 * Find out about available port modes 10694 */ 10695 #define MC_CMD_GET_PORT_MODES 0xff 10696 10697 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10698 10699 /* MC_CMD_GET_PORT_MODES_IN msgrequest */ 10700 #define MC_CMD_GET_PORT_MODES_IN_LEN 0 10701 10702 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */ 10703 #define MC_CMD_GET_PORT_MODES_OUT_LEN 12 10704 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */ 10705 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0 10706 /* Default (canonical) board mode */ 10707 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4 10708 /* Current board mode */ 10709 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 10710 10711 10712 /***********************************/ 10713 /* MC_CMD_READ_ATB 10714 * Sample voltages on the ATB 10715 */ 10716 #define MC_CMD_READ_ATB 0x100 10717 10718 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10719 10720 /* MC_CMD_READ_ATB_IN msgrequest */ 10721 #define MC_CMD_READ_ATB_IN_LEN 16 10722 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0 10723 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */ 10724 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */ 10725 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */ 10726 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4 10727 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8 10728 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12 10729 10730 /* MC_CMD_READ_ATB_OUT msgresponse */ 10731 #define MC_CMD_READ_ATB_OUT_LEN 4 10732 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 10733 10734 10735 /***********************************/ 10736 /* MC_CMD_GET_WORKAROUNDS 10737 * Read the list of all implemented and all currently enabled workarounds. The 10738 * enums here must correspond with those in MC_CMD_WORKAROUND. 10739 */ 10740 #define MC_CMD_GET_WORKAROUNDS 0x59 10741 10742 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10743 10744 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */ 10745 #define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8 10746 /* Each workaround is represented by a single bit according to the enums below. 10747 */ 10748 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0 10749 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4 10750 /* enum: Bug 17230 work around. */ 10751 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2 10752 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 10753 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4 10754 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 10755 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8 10756 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 10757 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10 10758 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 10759 * - before adding code that queries this workaround, remember that there's 10760 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 10761 * and will hence (incorrectly) report that the bug doesn't exist. 10762 */ 10763 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20 10764 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */ 10765 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40 10766 10767 10768 /***********************************/ 10769 /* MC_CMD_PRIVILEGE_MASK 10770 * Read/set privileges of an arbitrary PCIe function 10771 */ 10772 #define MC_CMD_PRIVILEGE_MASK 0x5a 10773 10774 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10775 10776 /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */ 10777 #define MC_CMD_PRIVILEGE_MASK_IN_LEN 8 10778 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF 10779 * 1,3 = 0x00030001 10780 */ 10781 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0 10782 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0 10783 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16 10784 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16 10785 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16 10786 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */ 10787 /* New privilege mask to be set. The mask will only be changed if the MSB is 10788 * set to 1. 10789 */ 10790 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4 10791 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */ 10792 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */ 10793 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */ 10794 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */ 10795 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */ 10796 /* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */ 10797 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 10798 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */ 10799 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */ 10800 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */ 10801 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */ 10802 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */ 10803 /* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC 10804 * adress. 10805 */ 10806 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800 10807 /* enum: Privilege that allows a Function to change the MAC address configured 10808 * in its associated vAdapter/vPort. 10809 */ 10810 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000 10811 /* enum: Privilege that allows a Function to install filters that specify VLANs 10812 * that are not in the permit list for the associated vPort. This privilege is 10813 * primarily to support ESX where vPorts are created that restrict traffic to 10814 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT. 10815 */ 10816 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000 10817 /* enum: Set this bit to indicate that a new privilege mask is to be set, 10818 * otherwise the command will only read the existing mask. 10819 */ 10820 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000 10821 10822 /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */ 10823 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4 10824 /* For an admin function, always all the privileges are reported. */ 10825 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0 10826 10827 10828 /***********************************/ 10829 /* MC_CMD_LINK_STATE_MODE 10830 * Read/set link state mode of a VF 10831 */ 10832 #define MC_CMD_LINK_STATE_MODE 0x5c 10833 10834 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10835 10836 /* MC_CMD_LINK_STATE_MODE_IN msgrequest */ 10837 #define MC_CMD_LINK_STATE_MODE_IN_LEN 8 10838 /* The target function to have its link state mode read or set, must be a VF 10839 * e.g. VF 1,3 = 0x00030001 10840 */ 10841 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0 10842 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0 10843 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16 10844 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16 10845 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16 10846 /* New link state mode to be set */ 10847 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4 10848 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */ 10849 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */ 10850 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */ 10851 /* enum: Use this value to just read the existing setting without modifying it. 10852 */ 10853 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff 10854 10855 /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */ 10856 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4 10857 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 10858 10859 10860 /***********************************/ 10861 /* MC_CMD_GET_SNAPSHOT_LENGTH 10862 * Obtain the curent range of allowable values for the SNAPSHOT_LENGTH 10863 * parameter to MC_CMD_INIT_RXQ. 10864 */ 10865 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101 10866 10867 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10868 10869 /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */ 10870 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0 10871 10872 /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */ 10873 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8 10874 /* Minimum acceptable snapshot length. */ 10875 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0 10876 /* Maximum acceptable snapshot length. */ 10877 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 10878 10879 10880 /***********************************/ 10881 /* MC_CMD_FUSE_DIAGS 10882 * Additional fuse diagnostics 10883 */ 10884 #define MC_CMD_FUSE_DIAGS 0x102 10885 10886 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10887 10888 /* MC_CMD_FUSE_DIAGS_IN msgrequest */ 10889 #define MC_CMD_FUSE_DIAGS_IN_LEN 0 10890 10891 /* MC_CMD_FUSE_DIAGS_OUT msgresponse */ 10892 #define MC_CMD_FUSE_DIAGS_OUT_LEN 48 10893 /* Total number of mismatched bits between pairs in area 0 */ 10894 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0 10895 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */ 10896 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4 10897 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */ 10898 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8 10899 /* Checksum of data after logical OR of pairs in area 0 */ 10900 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12 10901 /* Total number of mismatched bits between pairs in area 1 */ 10902 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16 10903 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */ 10904 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20 10905 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */ 10906 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24 10907 /* Checksum of data after logical OR of pairs in area 1 */ 10908 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28 10909 /* Total number of mismatched bits between pairs in area 2 */ 10910 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32 10911 /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */ 10912 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36 10913 /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */ 10914 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40 10915 /* Checksum of data after logical OR of pairs in area 2 */ 10916 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 10917 10918 10919 /***********************************/ 10920 /* MC_CMD_PRIVILEGE_MODIFY 10921 * Modify the privileges of a set of PCIe functions. Note that this operation 10922 * only effects non-admin functions unless the admin privilege itself is 10923 * included in one of the masks provided. 10924 */ 10925 #define MC_CMD_PRIVILEGE_MODIFY 0x60 10926 10927 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10928 10929 /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */ 10930 #define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16 10931 /* The groups of functions to have their privilege masks modified. */ 10932 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0 10933 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */ 10934 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */ 10935 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */ 10936 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */ 10937 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */ 10938 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */ 10939 /* For VFS_OF_PF specify the PF, for ONE specify the target function */ 10940 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4 10941 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0 10942 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16 10943 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16 10944 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16 10945 /* Privileges to be added to the target functions. For privilege definitions 10946 * refer to the command MC_CMD_PRIVILEGE_MASK 10947 */ 10948 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8 10949 /* Privileges to be removed from the target functions. For privilege 10950 * definitions refer to the command MC_CMD_PRIVILEGE_MASK 10951 */ 10952 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12 10953 10954 /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ 10955 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 10956 10957 10958 /***********************************/ 10959 /* MC_CMD_XPM_READ_BYTES 10960 * Read XPM memory 10961 */ 10962 #define MC_CMD_XPM_READ_BYTES 0x103 10963 10964 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10965 10966 /* MC_CMD_XPM_READ_BYTES_IN msgrequest */ 10967 #define MC_CMD_XPM_READ_BYTES_IN_LEN 8 10968 /* Start address (byte) */ 10969 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0 10970 /* Count (bytes) */ 10971 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4 10972 10973 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */ 10974 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0 10975 #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252 10976 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) 10977 /* Data */ 10978 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0 10979 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1 10980 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 10981 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 10982 10983 10984 /***********************************/ 10985 /* MC_CMD_XPM_WRITE_BYTES 10986 * Write XPM memory 10987 */ 10988 #define MC_CMD_XPM_WRITE_BYTES 0x104 10989 10990 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10991 10992 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */ 10993 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8 10994 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252 10995 #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) 10996 /* Start address (byte) */ 10997 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0 10998 /* Count (bytes) */ 10999 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4 11000 /* Data */ 11001 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8 11002 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1 11003 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0 11004 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244 11005 11006 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ 11007 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 11008 11009 11010 /***********************************/ 11011 /* MC_CMD_XPM_READ_SECTOR 11012 * Read XPM sector 11013 */ 11014 #define MC_CMD_XPM_READ_SECTOR 0x105 11015 11016 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11017 11018 /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */ 11019 #define MC_CMD_XPM_READ_SECTOR_IN_LEN 8 11020 /* Sector index */ 11021 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0 11022 /* Sector size */ 11023 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4 11024 11025 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */ 11026 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4 11027 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36 11028 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) 11029 /* Sector type */ 11030 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0 11031 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */ 11032 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */ 11033 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */ 11034 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */ 11035 /* Sector data */ 11036 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4 11037 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1 11038 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 11039 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 11040 11041 11042 /***********************************/ 11043 /* MC_CMD_XPM_WRITE_SECTOR 11044 * Write XPM sector 11045 */ 11046 #define MC_CMD_XPM_WRITE_SECTOR 0x106 11047 11048 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11049 11050 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */ 11051 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12 11052 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44 11053 #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) 11054 /* If writing fails due to an uncorrectable error, try up to RETRIES following 11055 * sectors (or until no more space available). If 0, only one write attempt is 11056 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair 11057 * mechanism. 11058 */ 11059 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0 11060 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1 11061 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1 11062 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3 11063 /* Sector type */ 11064 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 11065 /* Enum values, see field(s): */ 11066 /* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ 11067 /* Sector size */ 11068 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 11069 /* Sector data */ 11070 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12 11071 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1 11072 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0 11073 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32 11074 11075 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */ 11076 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4 11077 /* New sector index */ 11078 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 11079 11080 11081 /***********************************/ 11082 /* MC_CMD_XPM_INVALIDATE_SECTOR 11083 * Invalidate XPM sector 11084 */ 11085 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107 11086 11087 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11088 11089 /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */ 11090 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4 11091 /* Sector index */ 11092 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0 11093 11094 /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ 11095 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 11096 11097 11098 /***********************************/ 11099 /* MC_CMD_XPM_BLANK_CHECK 11100 * Blank-check XPM memory and report bad locations 11101 */ 11102 #define MC_CMD_XPM_BLANK_CHECK 0x108 11103 11104 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11105 11106 /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */ 11107 #define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8 11108 /* Start address (byte) */ 11109 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0 11110 /* Count (bytes) */ 11111 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4 11112 11113 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */ 11114 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4 11115 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252 11116 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) 11117 /* Total number of bad (non-blank) locations */ 11118 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0 11119 /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit 11120 * into MCDI response) 11121 */ 11122 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4 11123 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2 11124 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 11125 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 11126 11127 11128 /***********************************/ 11129 /* MC_CMD_XPM_REPAIR 11130 * Blank-check and repair XPM memory 11131 */ 11132 #define MC_CMD_XPM_REPAIR 0x109 11133 11134 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11135 11136 /* MC_CMD_XPM_REPAIR_IN msgrequest */ 11137 #define MC_CMD_XPM_REPAIR_IN_LEN 8 11138 /* Start address (byte) */ 11139 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0 11140 /* Count (bytes) */ 11141 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4 11142 11143 /* MC_CMD_XPM_REPAIR_OUT msgresponse */ 11144 #define MC_CMD_XPM_REPAIR_OUT_LEN 0 11145 11146 11147 /***********************************/ 11148 /* MC_CMD_XPM_DECODER_TEST 11149 * Test XPM memory address decoders for gross manufacturing defects. Can only 11150 * be performed on an unprogrammed part. 11151 */ 11152 #define MC_CMD_XPM_DECODER_TEST 0x10a 11153 11154 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11155 11156 /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */ 11157 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0 11158 11159 /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ 11160 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 11161 11162 11163 /***********************************/ 11164 /* MC_CMD_XPM_WRITE_TEST 11165 * XPM memory write test. Test XPM write logic for gross manufacturing defects 11166 * by writing to a dedicated test row. There are 16 locations in the test row 11167 * and the test can only be performed on locations that have not been 11168 * previously used (i.e. can be run at most 16 times). The test will pick the 11169 * first available location to use, or fail with ENOSPC if none left. 11170 */ 11171 #define MC_CMD_XPM_WRITE_TEST 0x10b 11172 11173 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11174 11175 /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */ 11176 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0 11177 11178 /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ 11179 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 11180 11181 11182 /***********************************/ 11183 /* MC_CMD_EXEC_SIGNED 11184 * Check the CMAC of the contents of IMEM and DMEM against the value supplied 11185 * and if correct begin execution from the start of IMEM. The caller supplies a 11186 * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC 11187 * computation runs from the start of IMEM, and from the start of DMEM + 16k, 11188 * to match flash booting. The command will respond with EINVAL if the CMAC 11189 * does match, otherwise it will respond with success before it jumps to IMEM. 11190 */ 11191 #define MC_CMD_EXEC_SIGNED 0x10c 11192 11193 #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11194 11195 /* MC_CMD_EXEC_SIGNED_IN msgrequest */ 11196 #define MC_CMD_EXEC_SIGNED_IN_LEN 28 11197 /* the length of code to include in the CMAC */ 11198 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0 11199 /* the length of date to include in the CMAC */ 11200 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4 11201 /* the XPM sector containing the key to use */ 11202 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8 11203 /* the expected CMAC value */ 11204 #define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12 11205 #define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16 11206 11207 /* MC_CMD_EXEC_SIGNED_OUT msgresponse */ 11208 #define MC_CMD_EXEC_SIGNED_OUT_LEN 0 11209 11210 11211 /***********************************/ 11212 /* MC_CMD_PREPARE_SIGNED 11213 * Prepare to upload a signed image. This will scrub the specified length of 11214 * the data region, which must be at least as large as the DATALEN supplied to 11215 * MC_CMD_EXEC_SIGNED. 11216 */ 11217 #define MC_CMD_PREPARE_SIGNED 0x10d 11218 11219 #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11220 11221 /* MC_CMD_PREPARE_SIGNED_IN msgrequest */ 11222 #define MC_CMD_PREPARE_SIGNED_IN_LEN 4 11223 /* the length of data area to clear */ 11224 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0 11225 11226 /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */ 11227 #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0 11228 11229 11230 /***********************************/ 11231 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 11232 * Configure UDP ports for tunnel encapsulation hardware acceleration. The 11233 * parser-dispatcher will attempt to parse traffic on these ports as tunnel 11234 * encapsulation PDUs and filter them using the tunnel encapsulation filter 11235 * chain rather than the standard filter chain. Note that this command can 11236 * cause all functions to see a reset. (Available on Medford only.) 11237 */ 11238 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117 11239 11240 #define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11241 11242 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */ 11243 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4 11244 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68 11245 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num)) 11246 /* Flags */ 11247 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0 11248 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2 11249 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0 11250 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1 11251 /* The number of entries in the ENTRIES array */ 11252 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2 11253 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2 11254 /* Entries defining the UDP port to protocol mapping, each laid out as a 11255 * TUNNEL_ENCAP_UDP_PORT_ENTRY 11256 */ 11257 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4 11258 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4 11259 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0 11260 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16 11261 11262 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */ 11263 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2 11264 /* Flags */ 11265 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0 11266 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2 11267 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0 11268 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1 11269 11270 11271 /***********************************/ 11272 /* MC_CMD_RX_BALANCING 11273 * Configure a port upconverter to distribute the packets on both RX engines. 11274 * Packets are distributed based on a table with the destination vFIFO. The 11275 * index of the table is a hash of source and destination of IPV4 and VLAN 11276 * priority. 11277 */ 11278 #define MC_CMD_RX_BALANCING 0x118 11279 11280 #define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11281 11282 /* MC_CMD_RX_BALANCING_IN msgrequest */ 11283 #define MC_CMD_RX_BALANCING_IN_LEN 4 11284 /* The RX port whose upconverter table will be modified */ 11285 #define MC_CMD_RX_BALANCING_IN_PORT_OFST 0 11286 #define MC_CMD_RX_BALANCING_IN_PORT_LEN 1 11287 /* The VLAN priority associated to the table index and vFIFO */ 11288 #define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 1 11289 #define MC_CMD_RX_BALANCING_IN_PRIORITY_LEN 1 11290 /* The resulting bit of SRC^DST for indexing the table */ 11291 #define MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 2 11292 #define MC_CMD_RX_BALANCING_IN_SRC_DST_LEN 1 11293 /* The RX engine to which the vFIFO in the table entry will point to */ 11294 #define MC_CMD_RX_BALANCING_IN_ENG_OFST 3 11295 #define MC_CMD_RX_BALANCING_IN_ENG_LEN 1 11296 11297 /* MC_CMD_RX_BALANCING_OUT msgresponse */ 11298 #define MC_CMD_RX_BALANCING_OUT_LEN 0 11299 11300 11301 #endif /* MCDI_PCOL_H */ 11302