1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2009-2013 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 11 #ifndef MCDI_PCOL_H 12 #define MCDI_PCOL_H 13 14 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 15 /* Power-on reset state */ 16 #define MC_FW_STATE_POR (1) 17 /* If this is set in MC_RESET_STATE_REG then it should be 18 * possible to jump into IMEM without loading code from flash. */ 19 #define MC_FW_WARM_BOOT_OK (2) 20 /* The MC main image has started to boot. */ 21 #define MC_FW_STATE_BOOTING (4) 22 /* The Scheduler has started. */ 23 #define MC_FW_STATE_SCHED (8) 24 /* If this is set in MC_RESET_STATE_REG then it should be 25 * possible to jump into IMEM without loading code from flash. 26 * Unlike a warm boot, assume DMEM has been reloaded, so that 27 * the MC persistent data must be reinitialised. */ 28 #define MC_FW_TEPID_BOOT_OK (16) 29 /* BIST state has been initialized */ 30 #define MC_FW_BIST_INIT_OK (128) 31 32 /* Siena MC shared memmory offsets */ 33 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 34 #define MC_SMEM_P0_DOORBELL_OFST 0x000 35 #define MC_SMEM_P1_DOORBELL_OFST 0x004 36 /* The rest of these are firmware-defined */ 37 #define MC_SMEM_P0_PDU_OFST 0x008 38 #define MC_SMEM_P1_PDU_OFST 0x108 39 #define MC_SMEM_PDU_LEN 0x100 40 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 41 #define MC_SMEM_P0_STATUS_OFST 0x7f8 42 #define MC_SMEM_P1_STATUS_OFST 0x7fc 43 44 /* Values to be written to the per-port status dword in shared 45 * memory on reboot and assert */ 46 #define MC_STATUS_DWORD_REBOOT (0xb007b007) 47 #define MC_STATUS_DWORD_ASSERT (0xdeaddead) 48 49 /* Check whether an mcfw version (in host order) belongs to a bootloader */ 50 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) 51 52 /* The current version of the MCDI protocol. 53 * 54 * Note that the ROM burnt into the card only talks V0, so at the very 55 * least every driver must support version 0 and MCDI_PCOL_VERSION 56 */ 57 #define MCDI_PCOL_VERSION 2 58 59 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 60 61 /* MCDI version 1 62 * 63 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit 64 * structure, filled in by the client. 65 * 66 * 0 7 8 16 20 22 23 24 31 67 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 68 * | | | 69 * | | \--- Response 70 * | \------- Error 71 * \------------------------------ Resync (always set) 72 * 73 * The client writes it's request into MC shared memory, and rings the 74 * doorbell. Each request is completed by either by the MC writting 75 * back into shared memory, or by writting out an event. 76 * 77 * All MCDI commands support completion by shared memory response. Each 78 * request may also contain additional data (accounted for by HEADER.LEN), 79 * and some response's may also contain additional data (again, accounted 80 * for by HEADER.LEN). 81 * 82 * Some MCDI commands support completion by event, in which any associated 83 * response data is included in the event. 84 * 85 * The protocol requires one response to be delivered for every request, a 86 * request should not be sent unless the response for the previous request 87 * has been received (either by polling shared memory, or by receiving 88 * an event). 89 */ 90 91 /** Request/Response structure */ 92 #define MCDI_HEADER_OFST 0 93 #define MCDI_HEADER_CODE_LBN 0 94 #define MCDI_HEADER_CODE_WIDTH 7 95 #define MCDI_HEADER_RESYNC_LBN 7 96 #define MCDI_HEADER_RESYNC_WIDTH 1 97 #define MCDI_HEADER_DATALEN_LBN 8 98 #define MCDI_HEADER_DATALEN_WIDTH 8 99 #define MCDI_HEADER_SEQ_LBN 16 100 #define MCDI_HEADER_SEQ_WIDTH 4 101 #define MCDI_HEADER_RSVD_LBN 20 102 #define MCDI_HEADER_RSVD_WIDTH 1 103 #define MCDI_HEADER_NOT_EPOCH_LBN 21 104 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 105 #define MCDI_HEADER_ERROR_LBN 22 106 #define MCDI_HEADER_ERROR_WIDTH 1 107 #define MCDI_HEADER_RESPONSE_LBN 23 108 #define MCDI_HEADER_RESPONSE_WIDTH 1 109 #define MCDI_HEADER_XFLAGS_LBN 24 110 #define MCDI_HEADER_XFLAGS_WIDTH 8 111 /* Request response using event */ 112 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 113 114 /* Maximum number of payload bytes */ 115 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc 116 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 117 118 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 119 120 121 /* The MC can generate events for two reasons: 122 * - To complete a shared memory request if XFLAGS_EVREQ was set 123 * - As a notification (link state, i2c event), controlled 124 * via MC_CMD_LOG_CTRL 125 * 126 * Both events share a common structure: 127 * 128 * 0 32 33 36 44 52 60 129 * | Data | Cont | Level | Src | Code | Rsvd | 130 * | 131 * \ There is another event pending in this notification 132 * 133 * If Code==CMDDONE, then the fields are further interpreted as: 134 * 135 * - LEVEL==INFO Command succeeded 136 * - LEVEL==ERR Command failed 137 * 138 * 0 8 16 24 32 139 * | Seq | Datalen | Errno | Rsvd | 140 * 141 * These fields are taken directly out of the standard MCDI header, i.e., 142 * LEVEL==ERR, Datalen == 0 => Reboot 143 * 144 * Events can be squirted out of the UART (using LOG_CTRL) without a 145 * MCDI header. An event can be distinguished from a MCDI response by 146 * examining the first byte which is 0xc0. This corresponds to the 147 * non-existent MCDI command MC_CMD_DEBUG_LOG. 148 * 149 * 0 7 8 150 * | command | Resync | = 0xc0 151 * 152 * Since the event is written in big-endian byte order, this works 153 * providing bits 56-63 of the event are 0xc0. 154 * 155 * 56 60 63 156 * | Rsvd | Code | = 0xc0 157 * 158 * Which means for convenience the event code is 0xc for all MC 159 * generated events. 160 */ 161 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 162 163 164 /* Operation not permitted. */ 165 #define MC_CMD_ERR_EPERM 1 166 /* Non-existent command target */ 167 #define MC_CMD_ERR_ENOENT 2 168 /* assert() has killed the MC */ 169 #define MC_CMD_ERR_EINTR 4 170 /* I/O failure */ 171 #define MC_CMD_ERR_EIO 5 172 /* Try again */ 173 #define MC_CMD_ERR_EAGAIN 11 174 /* Out of memory */ 175 #define MC_CMD_ERR_ENOMEM 12 176 /* Caller does not hold required locks */ 177 #define MC_CMD_ERR_EACCES 13 178 /* Resource is currently unavailable (e.g. lock contention) */ 179 #define MC_CMD_ERR_EBUSY 16 180 /* No such device */ 181 #define MC_CMD_ERR_ENODEV 19 182 /* Invalid argument to target */ 183 #define MC_CMD_ERR_EINVAL 22 184 /* Out of range */ 185 #define MC_CMD_ERR_ERANGE 34 186 /* Non-recursive resource is already acquired */ 187 #define MC_CMD_ERR_EDEADLK 35 188 /* Operation not implemented */ 189 #define MC_CMD_ERR_ENOSYS 38 190 /* Operation timed out */ 191 #define MC_CMD_ERR_ETIME 62 192 /* Link has been severed */ 193 #define MC_CMD_ERR_ENOLINK 67 194 /* Protocol error */ 195 #define MC_CMD_ERR_EPROTO 71 196 /* Operation not supported */ 197 #define MC_CMD_ERR_ENOTSUP 95 198 /* Address not available */ 199 #define MC_CMD_ERR_EADDRNOTAVAIL 99 200 /* Not connected */ 201 #define MC_CMD_ERR_ENOTCONN 107 202 /* Operation already in progress */ 203 #define MC_CMD_ERR_EALREADY 114 204 205 /* Resource allocation failed. */ 206 #define MC_CMD_ERR_ALLOC_FAIL 0x1000 207 /* V-adaptor not found. */ 208 #define MC_CMD_ERR_NO_VADAPTOR 0x1001 209 /* EVB port not found. */ 210 #define MC_CMD_ERR_NO_EVB_PORT 0x1002 211 /* V-switch not found. */ 212 #define MC_CMD_ERR_NO_VSWITCH 0x1003 213 /* Too many VLAN tags. */ 214 #define MC_CMD_ERR_VLAN_LIMIT 0x1004 215 /* Bad PCI function number. */ 216 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 217 /* Invalid VLAN mode. */ 218 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 219 /* Invalid v-switch type. */ 220 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 221 /* Invalid v-port type. */ 222 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 223 /* MAC address exists. */ 224 #define MC_CMD_ERR_MAC_EXIST 0x1009 225 /* Slave core not present */ 226 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a 227 228 #define MC_CMD_ERR_CODE_OFST 0 229 230 /* We define 8 "escape" commands to allow 231 for command number space extension */ 232 233 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 234 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 235 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 236 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 237 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 238 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 239 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 240 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 241 242 /* Vectors in the boot ROM */ 243 /* Point to the copycode entry point. */ 244 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) 245 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) 246 /* Points to the recovery mode entry point. */ 247 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) 248 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) 249 250 /* The command set exported by the boot ROM (MCDI v0) */ 251 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 252 (1 << MC_CMD_READ32) | \ 253 (1 << MC_CMD_WRITE32) | \ 254 (1 << MC_CMD_COPYCODE) | \ 255 (1 << MC_CMD_GET_VERSION), \ 256 0, 0, 0 } 257 258 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 259 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 260 261 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 262 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 263 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 264 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 265 266 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 267 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 268 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 269 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 270 271 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 272 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 273 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 274 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 275 276 277 /* Version 2 adds an optional argument to error returns: the errno value 278 * may be followed by the (0-based) number of the first argument that 279 * could not be processed. 280 */ 281 #define MC_CMD_ERR_ARG_OFST 4 282 283 /* No space */ 284 #define MC_CMD_ERR_ENOSPC 28 285 286 /* MCDI_EVENT structuredef */ 287 #define MCDI_EVENT_LEN 8 288 #define MCDI_EVENT_CONT_LBN 32 289 #define MCDI_EVENT_CONT_WIDTH 1 290 #define MCDI_EVENT_LEVEL_LBN 33 291 #define MCDI_EVENT_LEVEL_WIDTH 3 292 /* enum: Info. */ 293 #define MCDI_EVENT_LEVEL_INFO 0x0 294 /* enum: Warning. */ 295 #define MCDI_EVENT_LEVEL_WARN 0x1 296 /* enum: Error. */ 297 #define MCDI_EVENT_LEVEL_ERR 0x2 298 /* enum: Fatal. */ 299 #define MCDI_EVENT_LEVEL_FATAL 0x3 300 #define MCDI_EVENT_DATA_OFST 0 301 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 302 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 303 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 304 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 305 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 306 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 307 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 308 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 309 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 310 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 311 /* enum: 100Mbs */ 312 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 313 /* enum: 1Gbs */ 314 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 315 /* enum: 10Gbs */ 316 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 317 /* enum: 40Gbs */ 318 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 319 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 320 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 321 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 322 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 323 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 324 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 325 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 326 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 327 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 328 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 329 #define MCDI_EVENT_FWALERT_DATA_LBN 8 330 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 331 #define MCDI_EVENT_FWALERT_REASON_LBN 0 332 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 333 /* enum: SRAM Access. */ 334 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 335 #define MCDI_EVENT_FLR_VF_LBN 0 336 #define MCDI_EVENT_FLR_VF_WIDTH 8 337 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 338 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 339 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 340 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 341 /* enum: Descriptor loader reported failure */ 342 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 343 /* enum: Descriptor ring empty and no EOP seen for packet */ 344 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 345 /* enum: Overlength packet */ 346 #define MCDI_EVENT_TX_ERR_2BIG 0x3 347 /* enum: Malformed option descriptor */ 348 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 349 /* enum: Option descriptor part way through a packet */ 350 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 351 /* enum: DMA or PIO data access error */ 352 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 353 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 354 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 355 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 356 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 357 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 358 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 359 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 360 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 361 /* enum: PLL lost lock */ 362 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 363 /* enum: Filter overflow (PDMA) */ 364 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 365 /* enum: FIFO overflow (FPGA) */ 366 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 367 /* enum: Merge queue overflow */ 368 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 369 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 370 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 371 /* enum: AOE failed to load - no valid image? */ 372 #define MCDI_EVENT_AOE_NO_LOAD 0x1 373 /* enum: AOE FC reported an exception */ 374 #define MCDI_EVENT_AOE_FC_ASSERT 0x2 375 /* enum: AOE FC watchdogged */ 376 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 377 /* enum: AOE FC failed to start */ 378 #define MCDI_EVENT_AOE_FC_NO_START 0x4 379 /* enum: Generic AOE fault - likely to have been reported via other means too 380 * but intended for use by aoex driver. 381 */ 382 #define MCDI_EVENT_AOE_FAULT 0x5 383 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ 384 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 385 /* enum: AOE loaded successfully */ 386 #define MCDI_EVENT_AOE_LOAD 0x7 387 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ 388 #define MCDI_EVENT_AOE_DMA 0x8 389 /* enum: AOE byteblaster connected/disconnected (Connection status in 390 * AOE_ERR_DATA) 391 */ 392 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 393 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 394 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 395 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 396 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 397 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 398 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 399 #define MCDI_EVENT_RX_ERR_INFO_LBN 16 400 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 401 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 402 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 403 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 404 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 405 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 406 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 407 #define MCDI_EVENT_DATA_LBN 0 408 #define MCDI_EVENT_DATA_WIDTH 32 409 #define MCDI_EVENT_SRC_LBN 36 410 #define MCDI_EVENT_SRC_WIDTH 8 411 #define MCDI_EVENT_EV_CODE_LBN 60 412 #define MCDI_EVENT_EV_CODE_WIDTH 4 413 #define MCDI_EVENT_CODE_LBN 44 414 #define MCDI_EVENT_CODE_WIDTH 8 415 /* enum: Bad assert. */ 416 #define MCDI_EVENT_CODE_BADSSERT 0x1 417 /* enum: PM Notice. */ 418 #define MCDI_EVENT_CODE_PMNOTICE 0x2 419 /* enum: Command done. */ 420 #define MCDI_EVENT_CODE_CMDDONE 0x3 421 /* enum: Link change. */ 422 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 423 /* enum: Sensor Event. */ 424 #define MCDI_EVENT_CODE_SENSOREVT 0x5 425 /* enum: Schedule error. */ 426 #define MCDI_EVENT_CODE_SCHEDERR 0x6 427 /* enum: Reboot. */ 428 #define MCDI_EVENT_CODE_REBOOT 0x7 429 /* enum: Mac stats DMA. */ 430 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 431 /* enum: Firmware alert. */ 432 #define MCDI_EVENT_CODE_FWALERT 0x9 433 /* enum: Function level reset. */ 434 #define MCDI_EVENT_CODE_FLR 0xa 435 /* enum: Transmit error */ 436 #define MCDI_EVENT_CODE_TX_ERR 0xb 437 /* enum: Tx flush has completed */ 438 #define MCDI_EVENT_CODE_TX_FLUSH 0xc 439 /* enum: PTP packet received timestamp */ 440 #define MCDI_EVENT_CODE_PTP_RX 0xd 441 /* enum: PTP NIC failure */ 442 #define MCDI_EVENT_CODE_PTP_FAULT 0xe 443 /* enum: PTP PPS event */ 444 #define MCDI_EVENT_CODE_PTP_PPS 0xf 445 /* enum: Rx flush has completed */ 446 #define MCDI_EVENT_CODE_RX_FLUSH 0x10 447 /* enum: Receive error */ 448 #define MCDI_EVENT_CODE_RX_ERR 0x11 449 /* enum: AOE fault */ 450 #define MCDI_EVENT_CODE_AOE 0x12 451 /* enum: Network port calibration failed (VCAL). */ 452 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 453 /* enum: HW PPS event */ 454 #define MCDI_EVENT_CODE_HW_PPS 0x14 455 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and 456 * a different format) 457 */ 458 #define MCDI_EVENT_CODE_MC_REBOOT 0x15 459 /* enum: the MC has detected a parity error */ 460 #define MCDI_EVENT_CODE_PAR_ERR 0x16 461 /* enum: the MC has detected a correctable error */ 462 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 463 /* enum: the MC has detected an uncorrectable error */ 464 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 465 /* enum: Artificial event generated by host and posted via MC for test 466 * purposes. 467 */ 468 #define MCDI_EVENT_CODE_TESTGEN 0xfa 469 #define MCDI_EVENT_CMDDONE_DATA_OFST 0 470 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 471 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 472 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 473 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 474 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 475 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 476 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 477 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 478 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 479 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 480 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 481 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 482 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 483 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 484 /* Seconds field of timestamp */ 485 #define MCDI_EVENT_PTP_SECONDS_OFST 0 486 #define MCDI_EVENT_PTP_SECONDS_LBN 0 487 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 488 /* Nanoseconds field of timestamp */ 489 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 490 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 491 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 492 /* Lowest four bytes of sourceUUID from PTP packet */ 493 #define MCDI_EVENT_PTP_UUID_OFST 0 494 #define MCDI_EVENT_PTP_UUID_LBN 0 495 #define MCDI_EVENT_PTP_UUID_WIDTH 32 496 #define MCDI_EVENT_RX_ERR_DATA_OFST 0 497 #define MCDI_EVENT_RX_ERR_DATA_LBN 0 498 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 499 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 500 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 501 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 502 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 503 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 504 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 505 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 506 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 507 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 508 509 /* FCDI_EVENT structuredef */ 510 #define FCDI_EVENT_LEN 8 511 #define FCDI_EVENT_CONT_LBN 32 512 #define FCDI_EVENT_CONT_WIDTH 1 513 #define FCDI_EVENT_LEVEL_LBN 33 514 #define FCDI_EVENT_LEVEL_WIDTH 3 515 /* enum: Info. */ 516 #define FCDI_EVENT_LEVEL_INFO 0x0 517 /* enum: Warning. */ 518 #define FCDI_EVENT_LEVEL_WARN 0x1 519 /* enum: Error. */ 520 #define FCDI_EVENT_LEVEL_ERR 0x2 521 /* enum: Fatal. */ 522 #define FCDI_EVENT_LEVEL_FATAL 0x3 523 #define FCDI_EVENT_DATA_OFST 0 524 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 525 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 526 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ 527 #define FCDI_EVENT_LINK_UP 0x1 /* enum */ 528 #define FCDI_EVENT_DATA_LBN 0 529 #define FCDI_EVENT_DATA_WIDTH 32 530 #define FCDI_EVENT_SRC_LBN 36 531 #define FCDI_EVENT_SRC_WIDTH 8 532 #define FCDI_EVENT_EV_CODE_LBN 60 533 #define FCDI_EVENT_EV_CODE_WIDTH 4 534 #define FCDI_EVENT_CODE_LBN 44 535 #define FCDI_EVENT_CODE_WIDTH 8 536 /* enum: The FC was rebooted. */ 537 #define FCDI_EVENT_CODE_REBOOT 0x1 538 /* enum: Bad assert. */ 539 #define FCDI_EVENT_CODE_ASSERT 0x2 540 /* enum: DDR3 test result. */ 541 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 542 /* enum: Link status. */ 543 #define FCDI_EVENT_CODE_LINK_STATE 0x4 544 /* enum: A timed read is ready to be serviced. */ 545 #define FCDI_EVENT_CODE_TIMED_READ 0x5 546 /* enum: One or more PPS IN events */ 547 #define FCDI_EVENT_CODE_PPS_IN 0x6 548 /* enum: One or more PPS OUT events */ 549 #define FCDI_EVENT_CODE_PPS_OUT 0x7 550 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 551 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 552 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 553 #define FCDI_EVENT_ASSERT_TYPE_LBN 36 554 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 555 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 556 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 557 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 558 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 559 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 560 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 561 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 562 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 563 #define FCDI_EVENT_PPS_COUNT_OFST 0 564 #define FCDI_EVENT_PPS_COUNT_LBN 0 565 #define FCDI_EVENT_PPS_COUNT_WIDTH 32 566 567 /* FCDI_EXTENDED_EVENT structuredef */ 568 #define FCDI_EXTENDED_EVENT_LENMIN 16 569 #define FCDI_EXTENDED_EVENT_LENMAX 248 570 #define FCDI_EXTENDED_EVENT_LEN(num) (8+8*(num)) 571 /* Number of timestamps following */ 572 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 573 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 574 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 575 /* Seconds field of a timestamp record */ 576 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 577 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 578 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 579 /* Nanoseconds field of a timestamp record */ 580 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 581 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 582 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 583 /* Timestamp records comprising the event */ 584 #define FCDI_EXTENDED_EVENT_PPS_TIME_OFST 8 585 #define FCDI_EXTENDED_EVENT_PPS_TIME_LEN 8 586 #define FCDI_EXTENDED_EVENT_PPS_TIME_LO_OFST 8 587 #define FCDI_EXTENDED_EVENT_PPS_TIME_HI_OFST 12 588 #define FCDI_EXTENDED_EVENT_PPS_TIME_MINNUM 1 589 #define FCDI_EXTENDED_EVENT_PPS_TIME_MAXNUM 30 590 #define FCDI_EXTENDED_EVENT_PPS_TIME_LBN 64 591 #define FCDI_EXTENDED_EVENT_PPS_TIME_WIDTH 64 592 593 594 /***********************************/ 595 /* MC_CMD_READ32 596 * Read multiple 32byte words from MC memory. 597 */ 598 #define MC_CMD_READ32 0x1 599 600 /* MC_CMD_READ32_IN msgrequest */ 601 #define MC_CMD_READ32_IN_LEN 8 602 #define MC_CMD_READ32_IN_ADDR_OFST 0 603 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 604 605 /* MC_CMD_READ32_OUT msgresponse */ 606 #define MC_CMD_READ32_OUT_LENMIN 4 607 #define MC_CMD_READ32_OUT_LENMAX 252 608 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 609 #define MC_CMD_READ32_OUT_BUFFER_OFST 0 610 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 611 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 612 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 613 614 615 /***********************************/ 616 /* MC_CMD_WRITE32 617 * Write multiple 32byte words to MC memory. 618 */ 619 #define MC_CMD_WRITE32 0x2 620 621 /* MC_CMD_WRITE32_IN msgrequest */ 622 #define MC_CMD_WRITE32_IN_LENMIN 8 623 #define MC_CMD_WRITE32_IN_LENMAX 252 624 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 625 #define MC_CMD_WRITE32_IN_ADDR_OFST 0 626 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 627 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 628 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 629 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 630 631 /* MC_CMD_WRITE32_OUT msgresponse */ 632 #define MC_CMD_WRITE32_OUT_LEN 0 633 634 635 /***********************************/ 636 /* MC_CMD_COPYCODE 637 * Copy MC code between two locations and jump. 638 */ 639 #define MC_CMD_COPYCODE 0x3 640 641 /* MC_CMD_COPYCODE_IN msgrequest */ 642 #define MC_CMD_COPYCODE_IN_LEN 16 643 /* Source address */ 644 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 645 /* enum: Entering the main image via a copy of a single word from and to this 646 * address indicates that it should not attempt to start the datapath CPUs. 647 * This is useful for certain soft rebooting scenarios. (Huntington only) 648 */ 649 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 650 /* enum: Entering the main image via a copy of a single word from and to this 651 * address indicates that it should not attempt to parse any configuration from 652 * flash. (In addition, the datapath CPUs will not be started, as for 653 * MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR above.) This is useful for 654 * certain soft rebooting scenarios. (Huntington only) 655 */ 656 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc 657 /* Destination address */ 658 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 659 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 660 /* Address of where to jump after copy. */ 661 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 662 /* enum: Control should return to the caller rather than jumping */ 663 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 664 665 /* MC_CMD_COPYCODE_OUT msgresponse */ 666 #define MC_CMD_COPYCODE_OUT_LEN 0 667 668 669 /***********************************/ 670 /* MC_CMD_SET_FUNC 671 * Select function for function-specific commands. 672 */ 673 #define MC_CMD_SET_FUNC 0x4 674 675 /* MC_CMD_SET_FUNC_IN msgrequest */ 676 #define MC_CMD_SET_FUNC_IN_LEN 4 677 /* Set function */ 678 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 679 680 /* MC_CMD_SET_FUNC_OUT msgresponse */ 681 #define MC_CMD_SET_FUNC_OUT_LEN 0 682 683 684 /***********************************/ 685 /* MC_CMD_GET_BOOT_STATUS 686 * Get the instruction address from which the MC booted. 687 */ 688 #define MC_CMD_GET_BOOT_STATUS 0x5 689 690 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 691 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 692 693 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 694 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 695 /* ?? */ 696 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 697 /* enum: indicates that the MC wasn't flash booted */ 698 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef 699 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 700 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 701 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 702 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 703 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 704 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 705 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 706 707 708 /***********************************/ 709 /* MC_CMD_GET_ASSERTS 710 * Get (and optionally clear) the current assertion status. Only 711 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other 712 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS 713 */ 714 #define MC_CMD_GET_ASSERTS 0x6 715 716 /* MC_CMD_GET_ASSERTS_IN msgrequest */ 717 #define MC_CMD_GET_ASSERTS_IN_LEN 4 718 /* Set to clear assertion */ 719 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 720 721 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ 722 #define MC_CMD_GET_ASSERTS_OUT_LEN 140 723 /* Assertion status flag. */ 724 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 725 /* enum: No assertions have failed. */ 726 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 727 /* enum: A system-level assertion has failed. */ 728 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 729 /* enum: A thread-level assertion has failed. */ 730 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 731 /* enum: The system was reset by the watchdog. */ 732 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 733 /* enum: An illegal address trap stopped the system (huntington and later) */ 734 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 735 /* Failing PC value */ 736 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 737 /* Saved GP regs */ 738 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 739 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 740 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 741 /* Failing thread address */ 742 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 743 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 744 745 746 /***********************************/ 747 /* MC_CMD_LOG_CTRL 748 * Configure the output stream for various events and messages. 749 */ 750 #define MC_CMD_LOG_CTRL 0x7 751 752 /* MC_CMD_LOG_CTRL_IN msgrequest */ 753 #define MC_CMD_LOG_CTRL_IN_LEN 8 754 /* Log destination */ 755 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 756 /* enum: UART. */ 757 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 758 /* enum: Event queue. */ 759 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 760 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 761 762 /* MC_CMD_LOG_CTRL_OUT msgresponse */ 763 #define MC_CMD_LOG_CTRL_OUT_LEN 0 764 765 766 /***********************************/ 767 /* MC_CMD_GET_VERSION 768 * Get version information about the MC firmware. 769 */ 770 #define MC_CMD_GET_VERSION 0x8 771 772 /* MC_CMD_GET_VERSION_IN msgrequest */ 773 #define MC_CMD_GET_VERSION_IN_LEN 0 774 775 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ 776 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 777 /* placeholder, set to 0 */ 778 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 779 780 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ 781 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 782 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 783 /* enum: Reserved version number to indicate "any" version. */ 784 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff 785 /* enum: Bootrom version value for Siena. */ 786 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 787 /* enum: Bootrom version value for Huntington. */ 788 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 789 790 /* MC_CMD_GET_VERSION_OUT msgresponse */ 791 #define MC_CMD_GET_VERSION_OUT_LEN 32 792 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 793 /* Enum values, see field(s): */ 794 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 795 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 796 /* 128bit mask of functions supported by the current firmware */ 797 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 798 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 799 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 800 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 801 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 802 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 803 804 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ 805 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 806 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 807 /* Enum values, see field(s): */ 808 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 809 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 810 /* 128bit mask of functions supported by the current firmware */ 811 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 812 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 813 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 814 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 815 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 816 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 817 /* extra info */ 818 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 819 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 820 821 822 /***********************************/ 823 /* MC_CMD_PTP 824 * Perform PTP operation 825 */ 826 #define MC_CMD_PTP 0xb 827 828 /* MC_CMD_PTP_IN msgrequest */ 829 #define MC_CMD_PTP_IN_LEN 1 830 /* PTP operation code */ 831 #define MC_CMD_PTP_IN_OP_OFST 0 832 #define MC_CMD_PTP_IN_OP_LEN 1 833 /* enum: Enable PTP packet timestamping operation. */ 834 #define MC_CMD_PTP_OP_ENABLE 0x1 835 /* enum: Disable PTP packet timestamping operation. */ 836 #define MC_CMD_PTP_OP_DISABLE 0x2 837 /* enum: Send a PTP packet. */ 838 #define MC_CMD_PTP_OP_TRANSMIT 0x3 839 /* enum: Read the current NIC time. */ 840 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 841 /* enum: Get the current PTP status. */ 842 #define MC_CMD_PTP_OP_STATUS 0x5 843 /* enum: Adjust the PTP NIC's time. */ 844 #define MC_CMD_PTP_OP_ADJUST 0x6 845 /* enum: Synchronize host and NIC time. */ 846 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 847 /* enum: Basic manufacturing tests. */ 848 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 849 /* enum: Packet based manufacturing tests. */ 850 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 851 /* enum: Reset some of the PTP related statistics */ 852 #define MC_CMD_PTP_OP_RESET_STATS 0xa 853 /* enum: Debug operations to MC. */ 854 #define MC_CMD_PTP_OP_DEBUG 0xb 855 /* enum: Read an FPGA register */ 856 #define MC_CMD_PTP_OP_FPGAREAD 0xc 857 /* enum: Write an FPGA register */ 858 #define MC_CMD_PTP_OP_FPGAWRITE 0xd 859 /* enum: Apply an offset to the NIC clock */ 860 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe 861 /* enum: Change Apply an offset to the NIC clock */ 862 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf 863 /* enum: Set the MC packet filter VLAN tags for received PTP packets */ 864 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 865 /* enum: Set the MC packet filter UUID for received PTP packets */ 866 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 867 /* enum: Set the MC packet filter Domain for received PTP packets */ 868 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 869 /* enum: Set the clock source */ 870 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 871 /* enum: Reset value of Timer Reg. */ 872 #define MC_CMD_PTP_OP_RST_CLK 0x14 873 /* enum: Enable the forwarding of PPS events to the host */ 874 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 875 /* enum: Above this for future use. */ 876 #define MC_CMD_PTP_OP_MAX 0x16 877 878 /* MC_CMD_PTP_IN_ENABLE msgrequest */ 879 #define MC_CMD_PTP_IN_ENABLE_LEN 16 880 #define MC_CMD_PTP_IN_CMD_OFST 0 881 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 882 /* Event queue for PTP events */ 883 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 884 /* PTP timestamping mode */ 885 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 886 /* enum: PTP, version 1 */ 887 #define MC_CMD_PTP_MODE_V1 0x0 888 /* enum: PTP, version 1, with VLAN headers - deprecated */ 889 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 890 /* enum: PTP, version 2 */ 891 #define MC_CMD_PTP_MODE_V2 0x2 892 /* enum: PTP, version 2, with VLAN headers - deprecated */ 893 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 894 /* enum: PTP, version 2, with improved UUID filtering */ 895 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 896 /* enum: FCoE (seconds and microseconds) */ 897 #define MC_CMD_PTP_MODE_FCOE 0x5 898 899 /* MC_CMD_PTP_IN_DISABLE msgrequest */ 900 #define MC_CMD_PTP_IN_DISABLE_LEN 8 901 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 902 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 903 904 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 905 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 906 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 907 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 908 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 909 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 910 /* Transmit packet length */ 911 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 912 /* Transmit packet data */ 913 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 914 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 915 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 916 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 917 918 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 919 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 920 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 921 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 922 923 /* MC_CMD_PTP_IN_STATUS msgrequest */ 924 #define MC_CMD_PTP_IN_STATUS_LEN 8 925 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 926 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 927 928 /* MC_CMD_PTP_IN_ADJUST msgrequest */ 929 #define MC_CMD_PTP_IN_ADJUST_LEN 24 930 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 931 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 932 /* Frequency adjustment 40 bit fixed point ns */ 933 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 934 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 935 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 936 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 937 /* enum: Number of fractional bits in frequency adjustment */ 938 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 939 /* Time adjustment in seconds */ 940 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 941 /* Time adjustment in nanoseconds */ 942 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 943 944 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 945 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 946 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 947 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 948 /* Number of time readings to capture */ 949 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 950 /* Host address in which to write "synchronization started" indication (64 951 * bits) 952 */ 953 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 954 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 955 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 956 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 957 958 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 959 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 960 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 961 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 962 963 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 964 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 965 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 966 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 967 /* Enable or disable packet testing */ 968 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 969 970 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ 971 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 972 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 973 /* Reset PTP statistics */ 974 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 975 976 /* MC_CMD_PTP_IN_DEBUG msgrequest */ 977 #define MC_CMD_PTP_IN_DEBUG_LEN 12 978 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 979 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 980 /* Debug operations */ 981 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 982 983 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ 984 #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 985 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 986 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 987 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 988 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 989 990 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ 991 #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 992 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 993 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) 994 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 995 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 996 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 997 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 998 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 999 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 1000 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 1001 1002 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ 1003 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 1004 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1005 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1006 /* Time adjustment in seconds */ 1007 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 1008 /* Time adjustment in nanoseconds */ 1009 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 1010 1011 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ 1012 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 1013 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1014 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1015 /* Frequency adjustment 40 bit fixed point ns */ 1016 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 1017 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 1018 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 1019 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 1020 /* enum: Number of fractional bits in frequency adjustment */ 1021 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ 1022 1023 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ 1024 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 1025 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1026 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1027 /* Number of VLAN tags, 0 if not VLAN */ 1028 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 1029 /* Set of VLAN tags to filter against */ 1030 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 1031 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 1032 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 1033 1034 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ 1035 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 1036 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1037 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1038 /* 1 to enable UUID filtering, 0 to disable */ 1039 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 1040 /* UUID to filter against */ 1041 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 1042 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 1043 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 1044 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 1045 1046 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ 1047 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 1048 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1049 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1050 /* 1 to enable Domain filtering, 0 to disable */ 1051 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 1052 /* Domain number to filter against */ 1053 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 1054 1055 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ 1056 #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 1057 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1058 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1059 /* Set the clock source. */ 1060 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 1061 /* enum: Internal. */ 1062 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 1063 /* enum: External. */ 1064 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 1065 1066 /* MC_CMD_PTP_IN_RST_CLK msgrequest */ 1067 #define MC_CMD_PTP_IN_RST_CLK_LEN 8 1068 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1069 /* Reset value of Timer Reg. */ 1070 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1071 1072 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ 1073 #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 1074 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1075 /* Enable or disable */ 1076 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 1077 /* enum: Enable */ 1078 #define MC_CMD_PTP_ENABLE_PPS 0x0 1079 /* enum: Disable */ 1080 #define MC_CMD_PTP_DISABLE_PPS 0x1 1081 /* Queueid to send events back */ 1082 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 1083 1084 /* MC_CMD_PTP_OUT msgresponse */ 1085 #define MC_CMD_PTP_OUT_LEN 0 1086 1087 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 1088 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 1089 /* Value of seconds timestamp */ 1090 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 1091 /* Value of nanoseconds timestamp */ 1092 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 1093 1094 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 1095 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 1096 /* Value of seconds timestamp */ 1097 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 1098 /* Value of nanoseconds timestamp */ 1099 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 1100 1101 /* MC_CMD_PTP_OUT_STATUS msgresponse */ 1102 #define MC_CMD_PTP_OUT_STATUS_LEN 64 1103 /* Frequency of NIC's hardware clock */ 1104 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 1105 /* Number of packets transmitted and timestamped */ 1106 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 1107 /* Number of packets received and timestamped */ 1108 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 1109 /* Number of packets timestamped by the FPGA */ 1110 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 1111 /* Number of packets filter matched */ 1112 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 1113 /* Number of packets not filter matched */ 1114 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 1115 /* Number of PPS overflows (noise on input?) */ 1116 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 1117 /* Number of PPS bad periods */ 1118 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 1119 /* Minimum period of PPS pulse */ 1120 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 1121 /* Maximum period of PPS pulse */ 1122 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 1123 /* Last period of PPS pulse */ 1124 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 1125 /* Mean period of PPS pulse */ 1126 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 1127 /* Minimum offset of PPS pulse (signed) */ 1128 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 1129 /* Maximum offset of PPS pulse (signed) */ 1130 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 1131 /* Last offset of PPS pulse (signed) */ 1132 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 1133 /* Mean offset of PPS pulse (signed) */ 1134 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 1135 1136 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 1137 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 1138 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 1139 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 1140 /* A set of host and NIC times */ 1141 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 1142 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 1143 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 1144 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 1145 /* Host time immediately before NIC's hardware clock read */ 1146 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 1147 /* Value of seconds timestamp */ 1148 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 1149 /* Value of nanoseconds timestamp */ 1150 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 1151 /* Host time immediately after NIC's hardware clock read */ 1152 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 1153 /* Number of nanoseconds waited after reading NIC's hardware clock */ 1154 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 1155 1156 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 1157 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 1158 /* Results of testing */ 1159 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 1160 /* enum: Successful test */ 1161 #define MC_CMD_PTP_MANF_SUCCESS 0x0 1162 /* enum: FPGA load failed */ 1163 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 1164 /* enum: FPGA version invalid */ 1165 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 1166 /* enum: FPGA registers incorrect */ 1167 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 1168 /* enum: Oscillator possibly not working? */ 1169 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 1170 /* enum: Timestamps not increasing */ 1171 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 1172 /* enum: Mismatched packet count */ 1173 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 1174 /* enum: Mismatched packet count (Siena filter and FPGA) */ 1175 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 1176 /* enum: Not enough packets to perform timestamp check */ 1177 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 1178 /* enum: Timestamp trigger GPIO not working */ 1179 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 1180 /* Presence of external oscillator */ 1181 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 1182 1183 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 1184 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 1185 /* Results of testing */ 1186 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 1187 /* Number of packets received by FPGA */ 1188 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 1189 /* Number of packets received by Siena filters */ 1190 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 1191 1192 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ 1193 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 1194 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 1195 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) 1196 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 1197 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 1198 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 1199 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 1200 1201 1202 /***********************************/ 1203 /* MC_CMD_CSR_READ32 1204 * Read 32bit words from the indirect memory map. 1205 */ 1206 #define MC_CMD_CSR_READ32 0xc 1207 1208 /* MC_CMD_CSR_READ32_IN msgrequest */ 1209 #define MC_CMD_CSR_READ32_IN_LEN 12 1210 /* Address */ 1211 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 1212 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 1213 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 1214 1215 /* MC_CMD_CSR_READ32_OUT msgresponse */ 1216 #define MC_CMD_CSR_READ32_OUT_LENMIN 4 1217 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 1218 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 1219 /* The last dword is the status, not a value read */ 1220 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 1221 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 1222 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 1223 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 1224 1225 1226 /***********************************/ 1227 /* MC_CMD_CSR_WRITE32 1228 * Write 32bit dwords to the indirect memory map. 1229 */ 1230 #define MC_CMD_CSR_WRITE32 0xd 1231 1232 /* MC_CMD_CSR_WRITE32_IN msgrequest */ 1233 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 1234 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 1235 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 1236 /* Address */ 1237 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 1238 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 1239 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 1240 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 1241 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 1242 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 1243 1244 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 1245 #define MC_CMD_CSR_WRITE32_OUT_LEN 4 1246 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 1247 1248 1249 /***********************************/ 1250 /* MC_CMD_HP 1251 * These commands are used for HP related features. They are grouped under one 1252 * MCDI command to avoid creating too many MCDI commands. 1253 */ 1254 #define MC_CMD_HP 0x54 1255 1256 /* MC_CMD_HP_IN msgrequest */ 1257 #define MC_CMD_HP_IN_LEN 16 1258 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at 1259 * the specified address with the specified interval.When address is NULL, 1260 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current 1261 * state / 2: (debug) Show temperature reported by one of the supported 1262 * sensors. 1263 */ 1264 #define MC_CMD_HP_IN_SUBCMD_OFST 0 1265 /* enum: OCSD (Option Card Sensor Data) sub-command. */ 1266 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 1267 /* enum: Last known valid HP sub-command. */ 1268 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 1269 /* The address to the array of sensor fields. (Or NULL to use a sub-command.) 1270 */ 1271 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 1272 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 1273 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 1274 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 1275 /* The requested update interval, in seconds. (Or the sub-command if ADDR is 1276 * NULL.) 1277 */ 1278 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 1279 1280 /* MC_CMD_HP_OUT msgresponse */ 1281 #define MC_CMD_HP_OUT_LEN 4 1282 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 1283 /* enum: OCSD stopped for this card. */ 1284 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 1285 /* enum: OCSD was successfully started with the address provided. */ 1286 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 1287 /* enum: OCSD was already started for this card. */ 1288 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 1289 1290 1291 /***********************************/ 1292 /* MC_CMD_STACKINFO 1293 * Get stack information. 1294 */ 1295 #define MC_CMD_STACKINFO 0xf 1296 1297 /* MC_CMD_STACKINFO_IN msgrequest */ 1298 #define MC_CMD_STACKINFO_IN_LEN 0 1299 1300 /* MC_CMD_STACKINFO_OUT msgresponse */ 1301 #define MC_CMD_STACKINFO_OUT_LENMIN 12 1302 #define MC_CMD_STACKINFO_OUT_LENMAX 252 1303 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 1304 /* (thread ptr, stack size, free space) for each thread in system */ 1305 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 1306 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 1307 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 1308 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 1309 1310 1311 /***********************************/ 1312 /* MC_CMD_MDIO_READ 1313 * MDIO register read. 1314 */ 1315 #define MC_CMD_MDIO_READ 0x10 1316 1317 /* MC_CMD_MDIO_READ_IN msgrequest */ 1318 #define MC_CMD_MDIO_READ_IN_LEN 16 1319 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 1320 * external devices. 1321 */ 1322 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 1323 /* enum: Internal. */ 1324 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 1325 /* enum: External. */ 1326 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 1327 /* Port address */ 1328 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 1329 /* Device Address or clause 22. */ 1330 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 1331 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 1332 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 1333 */ 1334 #define MC_CMD_MDIO_CLAUSE22 0x20 1335 /* Address */ 1336 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 1337 1338 /* MC_CMD_MDIO_READ_OUT msgresponse */ 1339 #define MC_CMD_MDIO_READ_OUT_LEN 8 1340 /* Value */ 1341 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 1342 /* Status the MDIO commands return the raw status bits from the MDIO block. A 1343 * "good" transaction should have the DONE bit set and all other bits clear. 1344 */ 1345 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 1346 /* enum: Good. */ 1347 #define MC_CMD_MDIO_STATUS_GOOD 0x8 1348 1349 1350 /***********************************/ 1351 /* MC_CMD_MDIO_WRITE 1352 * MDIO register write. 1353 */ 1354 #define MC_CMD_MDIO_WRITE 0x11 1355 1356 /* MC_CMD_MDIO_WRITE_IN msgrequest */ 1357 #define MC_CMD_MDIO_WRITE_IN_LEN 20 1358 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 1359 * external devices. 1360 */ 1361 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 1362 /* enum: Internal. */ 1363 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 1364 /* enum: External. */ 1365 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 1366 /* Port address */ 1367 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 1368 /* Device Address or clause 22. */ 1369 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 1370 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 1371 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 1372 */ 1373 /* MC_CMD_MDIO_CLAUSE22 0x20 */ 1374 /* Address */ 1375 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 1376 /* Value */ 1377 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 1378 1379 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 1380 #define MC_CMD_MDIO_WRITE_OUT_LEN 4 1381 /* Status; the MDIO commands return the raw status bits from the MDIO block. A 1382 * "good" transaction should have the DONE bit set and all other bits clear. 1383 */ 1384 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 1385 /* enum: Good. */ 1386 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 1387 1388 1389 /***********************************/ 1390 /* MC_CMD_DBI_WRITE 1391 * Write DBI register(s). 1392 */ 1393 #define MC_CMD_DBI_WRITE 0x12 1394 1395 /* MC_CMD_DBI_WRITE_IN msgrequest */ 1396 #define MC_CMD_DBI_WRITE_IN_LENMIN 12 1397 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 1398 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 1399 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset 1400 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. 1401 */ 1402 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 1403 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 1404 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 1405 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 1406 1407 /* MC_CMD_DBI_WRITE_OUT msgresponse */ 1408 #define MC_CMD_DBI_WRITE_OUT_LEN 0 1409 1410 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 1411 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 1412 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 1413 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 1414 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 1415 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 1416 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 1417 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 1418 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 1419 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 1420 #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 1421 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 1422 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 1423 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 1424 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 1425 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 1426 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 1427 1428 1429 /***********************************/ 1430 /* MC_CMD_PORT_READ32 1431 * Read a 32-bit register from the indirect port register map. The port to 1432 * access is implied by the Shared memory channel used. 1433 */ 1434 #define MC_CMD_PORT_READ32 0x14 1435 1436 /* MC_CMD_PORT_READ32_IN msgrequest */ 1437 #define MC_CMD_PORT_READ32_IN_LEN 4 1438 /* Address */ 1439 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 1440 1441 /* MC_CMD_PORT_READ32_OUT msgresponse */ 1442 #define MC_CMD_PORT_READ32_OUT_LEN 8 1443 /* Value */ 1444 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 1445 /* Status */ 1446 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 1447 1448 1449 /***********************************/ 1450 /* MC_CMD_PORT_WRITE32 1451 * Write a 32-bit register to the indirect port register map. The port to 1452 * access is implied by the Shared memory channel used. 1453 */ 1454 #define MC_CMD_PORT_WRITE32 0x15 1455 1456 /* MC_CMD_PORT_WRITE32_IN msgrequest */ 1457 #define MC_CMD_PORT_WRITE32_IN_LEN 8 1458 /* Address */ 1459 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 1460 /* Value */ 1461 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 1462 1463 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 1464 #define MC_CMD_PORT_WRITE32_OUT_LEN 4 1465 /* Status */ 1466 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 1467 1468 1469 /***********************************/ 1470 /* MC_CMD_PORT_READ128 1471 * Read a 128-bit register from the indirect port register map. The port to 1472 * access is implied by the Shared memory channel used. 1473 */ 1474 #define MC_CMD_PORT_READ128 0x16 1475 1476 /* MC_CMD_PORT_READ128_IN msgrequest */ 1477 #define MC_CMD_PORT_READ128_IN_LEN 4 1478 /* Address */ 1479 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 1480 1481 /* MC_CMD_PORT_READ128_OUT msgresponse */ 1482 #define MC_CMD_PORT_READ128_OUT_LEN 20 1483 /* Value */ 1484 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 1485 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 1486 /* Status */ 1487 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 1488 1489 1490 /***********************************/ 1491 /* MC_CMD_PORT_WRITE128 1492 * Write a 128-bit register to the indirect port register map. The port to 1493 * access is implied by the Shared memory channel used. 1494 */ 1495 #define MC_CMD_PORT_WRITE128 0x17 1496 1497 /* MC_CMD_PORT_WRITE128_IN msgrequest */ 1498 #define MC_CMD_PORT_WRITE128_IN_LEN 20 1499 /* Address */ 1500 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 1501 /* Value */ 1502 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 1503 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 1504 1505 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 1506 #define MC_CMD_PORT_WRITE128_OUT_LEN 4 1507 /* Status */ 1508 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 1509 1510 /* MC_CMD_CAPABILITIES structuredef */ 1511 #define MC_CMD_CAPABILITIES_LEN 4 1512 /* Small buf table. */ 1513 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 1514 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 1515 /* Turbo mode (for Maranello). */ 1516 #define MC_CMD_CAPABILITIES_TURBO_LBN 1 1517 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 1518 /* Turbo mode active (for Maranello). */ 1519 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 1520 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 1521 /* PTP offload. */ 1522 #define MC_CMD_CAPABILITIES_PTP_LBN 3 1523 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 1524 /* AOE mode. */ 1525 #define MC_CMD_CAPABILITIES_AOE_LBN 4 1526 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 1527 /* AOE mode active. */ 1528 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 1529 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 1530 /* AOE mode active. */ 1531 #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 1532 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 1533 #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 1534 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 1535 1536 1537 /***********************************/ 1538 /* MC_CMD_GET_BOARD_CFG 1539 * Returns the MC firmware configuration structure. 1540 */ 1541 #define MC_CMD_GET_BOARD_CFG 0x18 1542 1543 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 1544 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 1545 1546 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 1547 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 1548 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 1549 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 1550 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 1551 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 1552 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 1553 /* See MC_CMD_CAPABILITIES */ 1554 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 1555 /* See MC_CMD_CAPABILITIES */ 1556 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 1557 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 1558 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 1559 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 1560 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 1561 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 1562 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 1563 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 1564 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 1565 /* This field contains a 16-bit value for each of the types of NVRAM area. The 1566 * values are defined in the firmware/mc/platform/.c file for a specific board 1567 * type, but otherwise have no meaning to the MC; they are used by the driver 1568 * to manage selection of appropriate firmware updates. 1569 */ 1570 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 1571 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 1572 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 1573 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 1574 1575 1576 /***********************************/ 1577 /* MC_CMD_DBI_READX 1578 * Read DBI register(s) -- extended functionality 1579 */ 1580 #define MC_CMD_DBI_READX 0x19 1581 1582 /* MC_CMD_DBI_READX_IN msgrequest */ 1583 #define MC_CMD_DBI_READX_IN_LENMIN 8 1584 #define MC_CMD_DBI_READX_IN_LENMAX 248 1585 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 1586 /* Each Read op consists of an address (offset 0), VF/CS2) */ 1587 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 1588 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 1589 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 1590 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 1591 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 1592 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 1593 1594 /* MC_CMD_DBI_READX_OUT msgresponse */ 1595 #define MC_CMD_DBI_READX_OUT_LENMIN 4 1596 #define MC_CMD_DBI_READX_OUT_LENMAX 252 1597 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 1598 /* Value */ 1599 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 1600 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 1601 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 1602 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 1603 1604 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ 1605 #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 1606 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 1607 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 1608 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 1609 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 1610 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 1611 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 1612 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 1613 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 1614 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 1615 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 1616 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 1617 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 1618 1619 1620 /***********************************/ 1621 /* MC_CMD_SET_RAND_SEED 1622 * Set the 16byte seed for the MC pseudo-random generator. 1623 */ 1624 #define MC_CMD_SET_RAND_SEED 0x1a 1625 1626 /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 1627 #define MC_CMD_SET_RAND_SEED_IN_LEN 16 1628 /* Seed value. */ 1629 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 1630 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 1631 1632 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 1633 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 1634 1635 1636 /***********************************/ 1637 /* MC_CMD_LTSSM_HIST 1638 * Retrieve the history of the LTSSM, if the build supports it. 1639 */ 1640 #define MC_CMD_LTSSM_HIST 0x1b 1641 1642 /* MC_CMD_LTSSM_HIST_IN msgrequest */ 1643 #define MC_CMD_LTSSM_HIST_IN_LEN 0 1644 1645 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 1646 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 1647 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 1648 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 1649 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ 1650 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 1651 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 1652 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 1653 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 1654 1655 1656 /***********************************/ 1657 /* MC_CMD_DRV_ATTACH 1658 * Inform MCPU that this port is managed on the host (i.e. driver active). For 1659 * Huntington, also request the preferred datapath firmware to use if possible 1660 * (it may not be possible for this request to be fulfilled; the driver must 1661 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which 1662 * features are actually available). The FIRMWARE_ID field is ignored by older 1663 * platforms. 1664 */ 1665 #define MC_CMD_DRV_ATTACH 0x1c 1666 1667 /* MC_CMD_DRV_ATTACH_IN msgrequest */ 1668 #define MC_CMD_DRV_ATTACH_IN_LEN 12 1669 /* new state (0=detached, 1=attached) to set if UPDATE=1 */ 1670 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 1671 /* 1 to set new state, or 0 to just report the existing state */ 1672 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 1673 /* preferred datapath firmware (for Huntington; ignored for Siena) */ 1674 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 1675 /* enum: Prefer to use full featured firmware */ 1676 #define MC_CMD_FW_FULL_FEATURED 0x0 1677 /* enum: Prefer to use firmware with fewer features but lower latency */ 1678 #define MC_CMD_FW_LOW_LATENCY 0x1 1679 1680 /* MC_CMD_DRV_ATTACH_OUT msgresponse */ 1681 #define MC_CMD_DRV_ATTACH_OUT_LEN 4 1682 /* previous or existing state (0=detached, 1=attached) */ 1683 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 1684 1685 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ 1686 #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 1687 /* previous or existing state (0=detached, 1=attached) */ 1688 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 1689 /* Flags associated with this function */ 1690 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 1691 /* enum: Labels the lowest-numbered function visible to the OS */ 1692 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 1693 /* enum: The function can control the link state of the physical port it is 1694 * bound to. 1695 */ 1696 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 1697 /* enum: The function can perform privileged operations */ 1698 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 1699 1700 1701 /***********************************/ 1702 /* MC_CMD_SHMUART 1703 * Route UART output to circular buffer in shared memory instead. 1704 */ 1705 #define MC_CMD_SHMUART 0x1f 1706 1707 /* MC_CMD_SHMUART_IN msgrequest */ 1708 #define MC_CMD_SHMUART_IN_LEN 4 1709 /* ??? */ 1710 #define MC_CMD_SHMUART_IN_FLAG_OFST 0 1711 1712 /* MC_CMD_SHMUART_OUT msgresponse */ 1713 #define MC_CMD_SHMUART_OUT_LEN 0 1714 1715 1716 /***********************************/ 1717 /* MC_CMD_PORT_RESET 1718 * Generic per-port reset. There is no equivalent for per-board reset. Locks 1719 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - 1720 * use MC_CMD_ENTITY_RESET instead. 1721 */ 1722 #define MC_CMD_PORT_RESET 0x20 1723 1724 /* MC_CMD_PORT_RESET_IN msgrequest */ 1725 #define MC_CMD_PORT_RESET_IN_LEN 0 1726 1727 /* MC_CMD_PORT_RESET_OUT msgresponse */ 1728 #define MC_CMD_PORT_RESET_OUT_LEN 0 1729 1730 1731 /***********************************/ 1732 /* MC_CMD_ENTITY_RESET 1733 * Generic per-resource reset. There is no equivalent for per-board reset. 1734 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an 1735 * extended version of the deprecated MC_CMD_PORT_RESET with added fields. 1736 */ 1737 #define MC_CMD_ENTITY_RESET 0x20 1738 1739 /* MC_CMD_ENTITY_RESET_IN msgrequest */ 1740 #define MC_CMD_ENTITY_RESET_IN_LEN 4 1741 /* Optional flags field. Omitting this will perform a "legacy" reset action 1742 * (TBD). 1743 */ 1744 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 1745 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 1746 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 1747 1748 /* MC_CMD_ENTITY_RESET_OUT msgresponse */ 1749 #define MC_CMD_ENTITY_RESET_OUT_LEN 0 1750 1751 1752 /***********************************/ 1753 /* MC_CMD_PCIE_CREDITS 1754 * Read instantaneous and minimum flow control thresholds. 1755 */ 1756 #define MC_CMD_PCIE_CREDITS 0x21 1757 1758 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 1759 #define MC_CMD_PCIE_CREDITS_IN_LEN 8 1760 /* poll period. 0 is disabled */ 1761 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 1762 /* wipe statistics */ 1763 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 1764 1765 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 1766 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 1767 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 1768 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 1769 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 1770 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 1771 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 1772 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 1773 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 1774 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 1775 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 1776 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 1777 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 1778 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 1779 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 1780 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 1781 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 1782 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 1783 1784 1785 /***********************************/ 1786 /* MC_CMD_RXD_MONITOR 1787 * Get histogram of RX queue fill level. 1788 */ 1789 #define MC_CMD_RXD_MONITOR 0x22 1790 1791 /* MC_CMD_RXD_MONITOR_IN msgrequest */ 1792 #define MC_CMD_RXD_MONITOR_IN_LEN 12 1793 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 1794 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 1795 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 1796 1797 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 1798 #define MC_CMD_RXD_MONITOR_OUT_LEN 80 1799 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 1800 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 1801 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 1802 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 1803 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 1804 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 1805 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 1806 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 1807 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 1808 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 1809 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 1810 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 1811 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 1812 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 1813 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 1814 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 1815 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 1816 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 1817 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 1818 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 1819 1820 1821 /***********************************/ 1822 /* MC_CMD_PUTS 1823 * Copy the given ASCII string out onto UART and/or out of the network port. 1824 */ 1825 #define MC_CMD_PUTS 0x23 1826 1827 /* MC_CMD_PUTS_IN msgrequest */ 1828 #define MC_CMD_PUTS_IN_LENMIN 13 1829 #define MC_CMD_PUTS_IN_LENMAX 252 1830 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 1831 #define MC_CMD_PUTS_IN_DEST_OFST 0 1832 #define MC_CMD_PUTS_IN_UART_LBN 0 1833 #define MC_CMD_PUTS_IN_UART_WIDTH 1 1834 #define MC_CMD_PUTS_IN_PORT_LBN 1 1835 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 1836 #define MC_CMD_PUTS_IN_DHOST_OFST 4 1837 #define MC_CMD_PUTS_IN_DHOST_LEN 6 1838 #define MC_CMD_PUTS_IN_STRING_OFST 12 1839 #define MC_CMD_PUTS_IN_STRING_LEN 1 1840 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 1841 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 1842 1843 /* MC_CMD_PUTS_OUT msgresponse */ 1844 #define MC_CMD_PUTS_OUT_LEN 0 1845 1846 1847 /***********************************/ 1848 /* MC_CMD_GET_PHY_CFG 1849 * Report PHY configuration. This guarantees to succeed even if the PHY is in a 1850 * 'zombie' state. Locks required: None 1851 */ 1852 #define MC_CMD_GET_PHY_CFG 0x24 1853 1854 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 1855 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 1856 1857 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 1858 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 1859 /* flags */ 1860 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 1861 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 1862 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 1863 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 1864 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 1865 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 1866 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 1867 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 1868 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 1869 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 1870 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 1871 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 1872 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 1873 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 1874 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 1875 /* ?? */ 1876 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 1877 /* Bitmask of supported capabilities */ 1878 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 1879 #define MC_CMD_PHY_CAP_10HDX_LBN 1 1880 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 1881 #define MC_CMD_PHY_CAP_10FDX_LBN 2 1882 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 1883 #define MC_CMD_PHY_CAP_100HDX_LBN 3 1884 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 1885 #define MC_CMD_PHY_CAP_100FDX_LBN 4 1886 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 1887 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 1888 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 1889 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 1890 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 1891 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 1892 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 1893 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 1894 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 1895 #define MC_CMD_PHY_CAP_ASYM_LBN 9 1896 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 1897 #define MC_CMD_PHY_CAP_AN_LBN 10 1898 #define MC_CMD_PHY_CAP_AN_WIDTH 1 1899 #define MC_CMD_PHY_CAP_40000FDX_LBN 11 1900 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 1901 #define MC_CMD_PHY_CAP_DDM_LBN 12 1902 #define MC_CMD_PHY_CAP_DDM_WIDTH 1 1903 /* ?? */ 1904 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 1905 /* ?? */ 1906 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 1907 /* ?? */ 1908 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 1909 /* ?? */ 1910 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 1911 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 1912 /* ?? */ 1913 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 1914 /* enum: Xaui. */ 1915 #define MC_CMD_MEDIA_XAUI 0x1 1916 /* enum: CX4. */ 1917 #define MC_CMD_MEDIA_CX4 0x2 1918 /* enum: KX4. */ 1919 #define MC_CMD_MEDIA_KX4 0x3 1920 /* enum: XFP Far. */ 1921 #define MC_CMD_MEDIA_XFP 0x4 1922 /* enum: SFP+. */ 1923 #define MC_CMD_MEDIA_SFP_PLUS 0x5 1924 /* enum: 10GBaseT. */ 1925 #define MC_CMD_MEDIA_BASE_T 0x6 1926 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 1927 /* enum: Native clause 22 */ 1928 #define MC_CMD_MMD_CLAUSE22 0x0 1929 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 1930 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 1931 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 1932 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 1933 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 1934 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 1935 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 1936 /* enum: Clause22 proxied over clause45 by PHY. */ 1937 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d 1938 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 1939 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 1940 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 1941 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 1942 1943 1944 /***********************************/ 1945 /* MC_CMD_START_BIST 1946 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST 1947 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) 1948 */ 1949 #define MC_CMD_START_BIST 0x25 1950 1951 /* MC_CMD_START_BIST_IN msgrequest */ 1952 #define MC_CMD_START_BIST_IN_LEN 4 1953 /* Type of test. */ 1954 #define MC_CMD_START_BIST_IN_TYPE_OFST 0 1955 /* enum: Run the PHY's short cable BIST. */ 1956 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 1957 /* enum: Run the PHY's long cable BIST. */ 1958 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 1959 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ 1960 #define MC_CMD_BPX_SERDES_BIST 0x3 1961 /* enum: Run the MC loopback tests. */ 1962 #define MC_CMD_MC_LOOPBACK_BIST 0x4 1963 /* enum: Run the PHY's standard BIST. */ 1964 #define MC_CMD_PHY_BIST 0x5 1965 /* enum: Run MC RAM test. */ 1966 #define MC_CMD_MC_MEM_BIST 0x6 1967 /* enum: Run Port RAM test. */ 1968 #define MC_CMD_PORT_MEM_BIST 0x7 1969 /* enum: Run register test. */ 1970 #define MC_CMD_REG_BIST 0x8 1971 1972 /* MC_CMD_START_BIST_OUT msgresponse */ 1973 #define MC_CMD_START_BIST_OUT_LEN 0 1974 1975 1976 /***********************************/ 1977 /* MC_CMD_POLL_BIST 1978 * Poll for BIST completion. Returns a single status code, and optionally some 1979 * PHY specific bist output. The driver should only consume the BIST output 1980 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't 1981 * successfully parse the BIST output, it should still respect the pass/Fail in 1982 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, 1983 * EACCES (if PHY_LOCK is not held). 1984 */ 1985 #define MC_CMD_POLL_BIST 0x26 1986 1987 /* MC_CMD_POLL_BIST_IN msgrequest */ 1988 #define MC_CMD_POLL_BIST_IN_LEN 0 1989 1990 /* MC_CMD_POLL_BIST_OUT msgresponse */ 1991 #define MC_CMD_POLL_BIST_OUT_LEN 8 1992 /* result */ 1993 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 1994 /* enum: Running. */ 1995 #define MC_CMD_POLL_BIST_RUNNING 0x1 1996 /* enum: Passed. */ 1997 #define MC_CMD_POLL_BIST_PASSED 0x2 1998 /* enum: Failed. */ 1999 #define MC_CMD_POLL_BIST_FAILED 0x3 2000 /* enum: Timed-out. */ 2001 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 2002 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 2003 2004 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 2005 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 2006 /* result */ 2007 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 2008 /* Enum values, see field(s): */ 2009 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 2010 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 2011 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 2012 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 2013 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 2014 /* Status of each channel A */ 2015 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 2016 /* enum: Ok. */ 2017 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 2018 /* enum: Open. */ 2019 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 2020 /* enum: Intra-pair short. */ 2021 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 2022 /* enum: Inter-pair short. */ 2023 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 2024 /* enum: Busy. */ 2025 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 2026 /* Status of each channel B */ 2027 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 2028 /* Enum values, see field(s): */ 2029 /* CABLE_STATUS_A */ 2030 /* Status of each channel C */ 2031 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 2032 /* Enum values, see field(s): */ 2033 /* CABLE_STATUS_A */ 2034 /* Status of each channel D */ 2035 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 2036 /* Enum values, see field(s): */ 2037 /* CABLE_STATUS_A */ 2038 2039 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 2040 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 2041 /* result */ 2042 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 2043 /* Enum values, see field(s): */ 2044 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 2045 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 2046 /* enum: Complete. */ 2047 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 2048 /* enum: Bus switch off I2C write. */ 2049 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 2050 /* enum: Bus switch off I2C no access IO exp. */ 2051 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 2052 /* enum: Bus switch off I2C no access module. */ 2053 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 2054 /* enum: IO exp I2C configure. */ 2055 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 2056 /* enum: Bus switch I2C no cross talk. */ 2057 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 2058 /* enum: Module presence. */ 2059 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 2060 /* enum: Module ID I2C access. */ 2061 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 2062 /* enum: Module ID sane value. */ 2063 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 2064 2065 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ 2066 #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 2067 /* result */ 2068 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 2069 /* Enum values, see field(s): */ 2070 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 2071 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 2072 /* enum: Test has completed. */ 2073 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 2074 /* enum: RAM test - walk ones. */ 2075 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 2076 /* enum: RAM test - walk zeros. */ 2077 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 2078 /* enum: RAM test - walking inversions zeros/ones. */ 2079 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 2080 /* enum: RAM test - walking inversions checkerboard. */ 2081 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 2082 /* enum: Register test - set / clear individual bits. */ 2083 #define MC_CMD_POLL_BIST_MEM_REG 0x5 2084 /* enum: ECC error detected. */ 2085 #define MC_CMD_POLL_BIST_MEM_ECC 0x6 2086 /* Failure address, only valid if result is POLL_BIST_FAILED */ 2087 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 2088 /* Bus or address space to which the failure address corresponds */ 2089 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 2090 /* enum: MC MIPS bus. */ 2091 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 2092 /* enum: CSR IREG bus. */ 2093 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 2094 /* enum: RX DPCPU bus. */ 2095 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 2096 /* enum: TX0 DPCPU bus. */ 2097 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 2098 /* enum: TX1 DPCPU bus. */ 2099 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 2100 /* enum: RX DICPU bus. */ 2101 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 2102 /* enum: TX DICPU bus. */ 2103 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 2104 /* Pattern written to RAM / register */ 2105 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 2106 /* Actual value read from RAM / register */ 2107 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 2108 /* ECC error mask */ 2109 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 2110 /* ECC parity error mask */ 2111 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 2112 /* ECC fatal error mask */ 2113 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 2114 2115 2116 /***********************************/ 2117 /* MC_CMD_FLUSH_RX_QUEUES 2118 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ 2119 * flushes should be initiated via this MCDI operation, rather than via 2120 * directly writing FLUSH_CMD. 2121 * 2122 * The flush is completed (either done/fail) asynchronously (after this command 2123 * returns). The driver must still wait for flush done/failure events as usual. 2124 */ 2125 #define MC_CMD_FLUSH_RX_QUEUES 0x27 2126 2127 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 2128 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 2129 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 2130 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 2131 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 2132 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 2133 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 2134 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 2135 2136 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 2137 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 2138 2139 2140 /***********************************/ 2141 /* MC_CMD_GET_LOOPBACK_MODES 2142 * Returns a bitmask of loopback modes available at each speed. 2143 */ 2144 #define MC_CMD_GET_LOOPBACK_MODES 0x28 2145 2146 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 2147 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 2148 2149 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 2150 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 2151 /* Supported loopbacks. */ 2152 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 2153 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 2154 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 2155 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 2156 /* enum: None. */ 2157 #define MC_CMD_LOOPBACK_NONE 0x0 2158 /* enum: Data. */ 2159 #define MC_CMD_LOOPBACK_DATA 0x1 2160 /* enum: GMAC. */ 2161 #define MC_CMD_LOOPBACK_GMAC 0x2 2162 /* enum: XGMII. */ 2163 #define MC_CMD_LOOPBACK_XGMII 0x3 2164 /* enum: XGXS. */ 2165 #define MC_CMD_LOOPBACK_XGXS 0x4 2166 /* enum: XAUI. */ 2167 #define MC_CMD_LOOPBACK_XAUI 0x5 2168 /* enum: GMII. */ 2169 #define MC_CMD_LOOPBACK_GMII 0x6 2170 /* enum: SGMII. */ 2171 #define MC_CMD_LOOPBACK_SGMII 0x7 2172 /* enum: XGBR. */ 2173 #define MC_CMD_LOOPBACK_XGBR 0x8 2174 /* enum: XFI. */ 2175 #define MC_CMD_LOOPBACK_XFI 0x9 2176 /* enum: XAUI Far. */ 2177 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa 2178 /* enum: GMII Far. */ 2179 #define MC_CMD_LOOPBACK_GMII_FAR 0xb 2180 /* enum: SGMII Far. */ 2181 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc 2182 /* enum: XFI Far. */ 2183 #define MC_CMD_LOOPBACK_XFI_FAR 0xd 2184 /* enum: GPhy. */ 2185 #define MC_CMD_LOOPBACK_GPHY 0xe 2186 /* enum: PhyXS. */ 2187 #define MC_CMD_LOOPBACK_PHYXS 0xf 2188 /* enum: PCS. */ 2189 #define MC_CMD_LOOPBACK_PCS 0x10 2190 /* enum: PMA-PMD. */ 2191 #define MC_CMD_LOOPBACK_PMAPMD 0x11 2192 /* enum: Cross-Port. */ 2193 #define MC_CMD_LOOPBACK_XPORT 0x12 2194 /* enum: XGMII-Wireside. */ 2195 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 2196 /* enum: XAUI Wireside. */ 2197 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 2198 /* enum: XAUI Wireside Far. */ 2199 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 2200 /* enum: XAUI Wireside near. */ 2201 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 2202 /* enum: GMII Wireside. */ 2203 #define MC_CMD_LOOPBACK_GMII_WS 0x17 2204 /* enum: XFI Wireside. */ 2205 #define MC_CMD_LOOPBACK_XFI_WS 0x18 2206 /* enum: XFI Wireside Far. */ 2207 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 2208 /* enum: PhyXS Wireside. */ 2209 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a 2210 /* enum: PMA lanes MAC-Serdes. */ 2211 #define MC_CMD_LOOPBACK_PMA_INT 0x1b 2212 /* enum: KR Serdes Parallel (Encoder). */ 2213 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c 2214 /* enum: KR Serdes Serial. */ 2215 #define MC_CMD_LOOPBACK_SD_FAR 0x1d 2216 /* enum: PMA lanes MAC-Serdes Wireside. */ 2217 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e 2218 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 2219 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f 2220 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 2221 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 2222 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 2223 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 2224 /* enum: KR Serdes Serial Wireside. */ 2225 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 2226 /* Supported loopbacks. */ 2227 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 2228 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 2229 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 2230 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 2231 /* Enum values, see field(s): */ 2232 /* 100M */ 2233 /* Supported loopbacks. */ 2234 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 2235 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 2236 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 2237 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 2238 /* Enum values, see field(s): */ 2239 /* 100M */ 2240 /* Supported loopbacks. */ 2241 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 2242 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 2243 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 2244 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 2245 /* Enum values, see field(s): */ 2246 /* 100M */ 2247 /* Supported loopbacks. */ 2248 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 2249 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 2250 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 2251 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 2252 /* Enum values, see field(s): */ 2253 /* 100M */ 2254 2255 2256 /***********************************/ 2257 /* MC_CMD_GET_LINK 2258 * Read the unified MAC/PHY link state. Locks required: None Return code: 0, 2259 * ETIME. 2260 */ 2261 #define MC_CMD_GET_LINK 0x29 2262 2263 /* MC_CMD_GET_LINK_IN msgrequest */ 2264 #define MC_CMD_GET_LINK_IN_LEN 0 2265 2266 /* MC_CMD_GET_LINK_OUT msgresponse */ 2267 #define MC_CMD_GET_LINK_OUT_LEN 28 2268 /* near-side advertised capabilities */ 2269 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 2270 /* link-partner advertised capabilities */ 2271 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 2272 /* Autonegotiated speed in mbit/s. The link may still be down even if this 2273 * reads non-zero. 2274 */ 2275 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 2276 /* Current loopback setting. */ 2277 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 2278 /* Enum values, see field(s): */ 2279 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 2280 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 2281 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 2282 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 2283 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 2284 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 2285 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 2286 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 2287 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 2288 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 2289 /* This returns the negotiated flow control value. */ 2290 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 2291 /* enum: Flow control is off. */ 2292 #define MC_CMD_FCNTL_OFF 0x0 2293 /* enum: Respond to flow control. */ 2294 #define MC_CMD_FCNTL_RESPOND 0x1 2295 /* enum: Respond to and Issue flow control. */ 2296 #define MC_CMD_FCNTL_BIDIR 0x2 2297 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 2298 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 2299 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 2300 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 2301 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 2302 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 2303 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 2304 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 2305 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 2306 2307 2308 /***********************************/ 2309 /* MC_CMD_SET_LINK 2310 * Write the unified MAC/PHY link configuration. Locks required: None. Return 2311 * code: 0, EINVAL, ETIME 2312 */ 2313 #define MC_CMD_SET_LINK 0x2a 2314 2315 /* MC_CMD_SET_LINK_IN msgrequest */ 2316 #define MC_CMD_SET_LINK_IN_LEN 16 2317 /* ??? */ 2318 #define MC_CMD_SET_LINK_IN_CAP_OFST 0 2319 /* Flags */ 2320 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 2321 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 2322 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 2323 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 2324 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 2325 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 2326 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 2327 /* Loopback mode. */ 2328 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 2329 /* Enum values, see field(s): */ 2330 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 2331 /* A loopback speed of "0" is supported, and means (choose any available 2332 * speed). 2333 */ 2334 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 2335 2336 /* MC_CMD_SET_LINK_OUT msgresponse */ 2337 #define MC_CMD_SET_LINK_OUT_LEN 0 2338 2339 2340 /***********************************/ 2341 /* MC_CMD_SET_ID_LED 2342 * Set identification LED state. Locks required: None. Return code: 0, EINVAL 2343 */ 2344 #define MC_CMD_SET_ID_LED 0x2b 2345 2346 /* MC_CMD_SET_ID_LED_IN msgrequest */ 2347 #define MC_CMD_SET_ID_LED_IN_LEN 4 2348 /* Set LED state. */ 2349 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 2350 #define MC_CMD_LED_OFF 0x0 /* enum */ 2351 #define MC_CMD_LED_ON 0x1 /* enum */ 2352 #define MC_CMD_LED_DEFAULT 0x2 /* enum */ 2353 2354 /* MC_CMD_SET_ID_LED_OUT msgresponse */ 2355 #define MC_CMD_SET_ID_LED_OUT_LEN 0 2356 2357 2358 /***********************************/ 2359 /* MC_CMD_SET_MAC 2360 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL 2361 */ 2362 #define MC_CMD_SET_MAC 0x2c 2363 2364 /* MC_CMD_SET_MAC_IN msgrequest */ 2365 #define MC_CMD_SET_MAC_IN_LEN 24 2366 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 2367 * EtherII, VLAN, bug16011 padding). 2368 */ 2369 #define MC_CMD_SET_MAC_IN_MTU_OFST 0 2370 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 2371 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 2372 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 2373 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 2374 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 2375 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 2376 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 2377 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 2378 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 2379 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 2380 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 2381 /* enum: Flow control is off. */ 2382 /* MC_CMD_FCNTL_OFF 0x0 */ 2383 /* enum: Respond to flow control. */ 2384 /* MC_CMD_FCNTL_RESPOND 0x1 */ 2385 /* enum: Respond to and Issue flow control. */ 2386 /* MC_CMD_FCNTL_BIDIR 0x2 */ 2387 /* enum: Auto neg flow control. */ 2388 #define MC_CMD_FCNTL_AUTO 0x3 2389 2390 /* MC_CMD_SET_MAC_OUT msgresponse */ 2391 #define MC_CMD_SET_MAC_OUT_LEN 0 2392 2393 2394 /***********************************/ 2395 /* MC_CMD_PHY_STATS 2396 * Get generic PHY statistics. This call returns the statistics for a generic 2397 * PHY in a sparse array (indexed by the enumerate). Each value is represented 2398 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the 2399 * statistics may be read from the message response. If DMA_ADDR != 0, then the 2400 * statistics are dmad to that (page-aligned location). Locks required: None. 2401 * Returns: 0, ETIME 2402 */ 2403 #define MC_CMD_PHY_STATS 0x2d 2404 2405 /* MC_CMD_PHY_STATS_IN msgrequest */ 2406 #define MC_CMD_PHY_STATS_IN_LEN 8 2407 /* ??? */ 2408 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 2409 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 2410 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 2411 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 2412 2413 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 2414 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 2415 2416 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 2417 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 2418 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 2419 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 2420 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 2421 /* enum: OUI. */ 2422 #define MC_CMD_OUI 0x0 2423 /* enum: PMA-PMD Link Up. */ 2424 #define MC_CMD_PMA_PMD_LINK_UP 0x1 2425 /* enum: PMA-PMD RX Fault. */ 2426 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 2427 /* enum: PMA-PMD TX Fault. */ 2428 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 2429 /* enum: PMA-PMD Signal */ 2430 #define MC_CMD_PMA_PMD_SIGNAL 0x4 2431 /* enum: PMA-PMD SNR A. */ 2432 #define MC_CMD_PMA_PMD_SNR_A 0x5 2433 /* enum: PMA-PMD SNR B. */ 2434 #define MC_CMD_PMA_PMD_SNR_B 0x6 2435 /* enum: PMA-PMD SNR C. */ 2436 #define MC_CMD_PMA_PMD_SNR_C 0x7 2437 /* enum: PMA-PMD SNR D. */ 2438 #define MC_CMD_PMA_PMD_SNR_D 0x8 2439 /* enum: PCS Link Up. */ 2440 #define MC_CMD_PCS_LINK_UP 0x9 2441 /* enum: PCS RX Fault. */ 2442 #define MC_CMD_PCS_RX_FAULT 0xa 2443 /* enum: PCS TX Fault. */ 2444 #define MC_CMD_PCS_TX_FAULT 0xb 2445 /* enum: PCS BER. */ 2446 #define MC_CMD_PCS_BER 0xc 2447 /* enum: PCS Block Errors. */ 2448 #define MC_CMD_PCS_BLOCK_ERRORS 0xd 2449 /* enum: PhyXS Link Up. */ 2450 #define MC_CMD_PHYXS_LINK_UP 0xe 2451 /* enum: PhyXS RX Fault. */ 2452 #define MC_CMD_PHYXS_RX_FAULT 0xf 2453 /* enum: PhyXS TX Fault. */ 2454 #define MC_CMD_PHYXS_TX_FAULT 0x10 2455 /* enum: PhyXS Align. */ 2456 #define MC_CMD_PHYXS_ALIGN 0x11 2457 /* enum: PhyXS Sync. */ 2458 #define MC_CMD_PHYXS_SYNC 0x12 2459 /* enum: AN link-up. */ 2460 #define MC_CMD_AN_LINK_UP 0x13 2461 /* enum: AN Complete. */ 2462 #define MC_CMD_AN_COMPLETE 0x14 2463 /* enum: AN 10GBaseT Status. */ 2464 #define MC_CMD_AN_10GBT_STATUS 0x15 2465 /* enum: Clause 22 Link-Up. */ 2466 #define MC_CMD_CL22_LINK_UP 0x16 2467 /* enum: (Last entry) */ 2468 #define MC_CMD_PHY_NSTATS 0x17 2469 2470 2471 /***********************************/ 2472 /* MC_CMD_MAC_STATS 2473 * Get generic MAC statistics. This call returns unified statistics maintained 2474 * by the MC as it switches between the GMAC and XMAC. The MC will write out 2475 * all supported stats. The driver should zero initialise the buffer to 2476 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is 2477 * performed, and the statistics may be read from the message response. If 2478 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). 2479 * Locks required: None. Returns: 0, ETIME 2480 */ 2481 #define MC_CMD_MAC_STATS 0x2e 2482 2483 /* MC_CMD_MAC_STATS_IN msgrequest */ 2484 #define MC_CMD_MAC_STATS_IN_LEN 16 2485 /* ??? */ 2486 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 2487 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 2488 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 2489 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 2490 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 2491 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 2492 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 2493 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 2494 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 2495 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 2496 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 2497 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 2498 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 2499 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 2500 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 2501 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 2502 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 2503 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 2504 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 2505 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 2506 2507 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 2508 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 2509 2510 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 2511 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 2512 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 2513 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 2514 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 2515 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 2516 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 2517 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 2518 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 2519 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 2520 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 2521 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 2522 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 2523 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 2524 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 2525 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 2526 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 2527 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 2528 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 2529 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 2530 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 2531 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 2532 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 2533 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 2534 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 2535 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 2536 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 2537 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 2538 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 2539 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 2540 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 2541 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 2542 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 2543 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 2544 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 2545 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 2546 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 2547 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 2548 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 2549 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 2550 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 2551 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 2552 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 2553 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 2554 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 2555 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 2556 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 2557 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 2558 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 2559 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 2560 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 2561 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 2562 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 2563 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 2564 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 2565 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 2566 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 2567 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 2568 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 2569 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 2570 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 2571 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 2572 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 2573 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 2574 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 2575 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 2576 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 2577 #define MC_CMD_GMAC_DMABUF_START 0x40 /* enum */ 2578 #define MC_CMD_GMAC_DMABUF_END 0x5f /* enum */ 2579 #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ 2580 #define MC_CMD_MAC_NSTATS 0x61 /* enum */ 2581 2582 2583 /***********************************/ 2584 /* MC_CMD_SRIOV 2585 * to be documented 2586 */ 2587 #define MC_CMD_SRIOV 0x30 2588 2589 /* MC_CMD_SRIOV_IN msgrequest */ 2590 #define MC_CMD_SRIOV_IN_LEN 12 2591 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 2592 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 2593 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 2594 2595 /* MC_CMD_SRIOV_OUT msgresponse */ 2596 #define MC_CMD_SRIOV_OUT_LEN 8 2597 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 2598 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 2599 2600 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 2601 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 2602 /* this is only used for the first record */ 2603 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 2604 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 2605 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 2606 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 2607 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 2608 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 2609 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 2610 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 2611 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 2612 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 2613 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 2614 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 2615 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 2616 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 2617 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 2618 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 2619 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 2620 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 2621 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 2622 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 2623 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 2624 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 2625 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 2626 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 2627 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 2628 2629 2630 /***********************************/ 2631 /* MC_CMD_MEMCPY 2632 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data 2633 * embedded directly in the command. 2634 * 2635 * A common pattern is for a client to use generation counts to signal a dma 2636 * update of a datastructure. To facilitate this, this MCDI operation can 2637 * contain multiple requests which are executed in strict order. Requests take 2638 * the form of duplicating the entire MCDI request continuously (including the 2639 * requests record, which is ignored in all but the first structure) 2640 * 2641 * The source data can either come from a DMA from the host, or it can be 2642 * embedded within the request directly, thereby eliminating a DMA read. To 2643 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and 2644 * ADDR_LO=offset, and inserts the data at %offset from the start of the 2645 * payload. It's the callers responsibility to ensure that the embedded data 2646 * doesn't overlap the records. 2647 * 2648 * Returns: 0, EINVAL (invalid RID) 2649 */ 2650 #define MC_CMD_MEMCPY 0x31 2651 2652 /* MC_CMD_MEMCPY_IN msgrequest */ 2653 #define MC_CMD_MEMCPY_IN_LENMIN 32 2654 #define MC_CMD_MEMCPY_IN_LENMAX 224 2655 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 2656 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ 2657 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 2658 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 2659 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 2660 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 2661 2662 /* MC_CMD_MEMCPY_OUT msgresponse */ 2663 #define MC_CMD_MEMCPY_OUT_LEN 0 2664 2665 2666 /***********************************/ 2667 /* MC_CMD_WOL_FILTER_SET 2668 * Set a WoL filter. 2669 */ 2670 #define MC_CMD_WOL_FILTER_SET 0x32 2671 2672 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 2673 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 2674 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 2675 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 2676 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 2677 /* A type value of 1 is unused. */ 2678 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 2679 /* enum: Magic */ 2680 #define MC_CMD_WOL_TYPE_MAGIC 0x0 2681 /* enum: MS Windows Magic */ 2682 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 2683 /* enum: IPv4 Syn */ 2684 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 2685 /* enum: IPv6 Syn */ 2686 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 2687 /* enum: Bitmap */ 2688 #define MC_CMD_WOL_TYPE_BITMAP 0x5 2689 /* enum: Link */ 2690 #define MC_CMD_WOL_TYPE_LINK 0x6 2691 /* enum: (Above this for future use) */ 2692 #define MC_CMD_WOL_TYPE_MAX 0x7 2693 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 2694 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 2695 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 2696 2697 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 2698 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 2699 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 2700 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 2701 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 2702 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 2703 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 2704 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 2705 2706 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 2707 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 2708 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 2709 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 2710 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 2711 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 2712 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 2713 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 2714 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 2715 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 2716 2717 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 2718 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 2719 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 2720 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 2721 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 2722 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 2723 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 2724 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 2725 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 2726 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 2727 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 2728 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 2729 2730 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 2731 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 2732 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 2733 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 2734 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 2735 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 2736 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 2737 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 2738 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 2739 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 2740 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 2741 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 2742 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 2743 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 2744 2745 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 2746 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 2747 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 2748 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 2749 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 2750 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 2751 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 2752 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 2753 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 2754 2755 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 2756 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 2757 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 2758 2759 2760 /***********************************/ 2761 /* MC_CMD_WOL_FILTER_REMOVE 2762 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS 2763 */ 2764 #define MC_CMD_WOL_FILTER_REMOVE 0x33 2765 2766 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 2767 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 2768 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 2769 2770 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 2771 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 2772 2773 2774 /***********************************/ 2775 /* MC_CMD_WOL_FILTER_RESET 2776 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, 2777 * ENOSYS 2778 */ 2779 #define MC_CMD_WOL_FILTER_RESET 0x34 2780 2781 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 2782 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 2783 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 2784 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 2785 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 2786 2787 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 2788 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 2789 2790 2791 /***********************************/ 2792 /* MC_CMD_SET_MCAST_HASH 2793 * Set the MCAST hash value without otherwise reconfiguring the MAC 2794 */ 2795 #define MC_CMD_SET_MCAST_HASH 0x35 2796 2797 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 2798 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 2799 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 2800 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 2801 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 2802 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 2803 2804 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 2805 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 2806 2807 2808 /***********************************/ 2809 /* MC_CMD_NVRAM_TYPES 2810 * Return bitfield indicating available types of virtual NVRAM partitions. 2811 * Locks required: none. Returns: 0 2812 */ 2813 #define MC_CMD_NVRAM_TYPES 0x36 2814 2815 /* MC_CMD_NVRAM_TYPES_IN msgrequest */ 2816 #define MC_CMD_NVRAM_TYPES_IN_LEN 0 2817 2818 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 2819 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 2820 /* Bit mask of supported types. */ 2821 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 2822 /* enum: Disabled callisto. */ 2823 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 2824 /* enum: MC firmware. */ 2825 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 2826 /* enum: MC backup firmware. */ 2827 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 2828 /* enum: Static configuration Port0. */ 2829 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 2830 /* enum: Static configuration Port1. */ 2831 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 2832 /* enum: Dynamic configuration Port0. */ 2833 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 2834 /* enum: Dynamic configuration Port1. */ 2835 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 2836 /* enum: Expansion Rom. */ 2837 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 2838 /* enum: Expansion Rom Configuration Port0. */ 2839 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 2840 /* enum: Expansion Rom Configuration Port1. */ 2841 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 2842 /* enum: Phy Configuration Port0. */ 2843 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa 2844 /* enum: Phy Configuration Port1. */ 2845 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb 2846 /* enum: Log. */ 2847 #define MC_CMD_NVRAM_TYPE_LOG 0xc 2848 /* enum: FPGA image. */ 2849 #define MC_CMD_NVRAM_TYPE_FPGA 0xd 2850 /* enum: FPGA backup image */ 2851 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe 2852 /* enum: FC firmware. */ 2853 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf 2854 /* enum: FC backup firmware. */ 2855 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 2856 /* enum: CPLD image. */ 2857 #define MC_CMD_NVRAM_TYPE_CPLD 0x11 2858 /* enum: Licensing information. */ 2859 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 2860 /* enum: FC Log. */ 2861 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 2862 2863 2864 /***********************************/ 2865 /* MC_CMD_NVRAM_INFO 2866 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, 2867 * EINVAL (bad type). 2868 */ 2869 #define MC_CMD_NVRAM_INFO 0x37 2870 2871 /* MC_CMD_NVRAM_INFO_IN msgrequest */ 2872 #define MC_CMD_NVRAM_INFO_IN_LEN 4 2873 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 2874 /* Enum values, see field(s): */ 2875 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 2876 2877 /* MC_CMD_NVRAM_INFO_OUT msgresponse */ 2878 #define MC_CMD_NVRAM_INFO_OUT_LEN 24 2879 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 2880 /* Enum values, see field(s): */ 2881 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 2882 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 2883 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 2884 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 2885 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 2886 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 2887 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 2888 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 2889 #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 2890 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 2891 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 2892 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 2893 2894 2895 /***********************************/ 2896 /* MC_CMD_NVRAM_UPDATE_START 2897 * Start a group of update operations on a virtual NVRAM partition. Locks 2898 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if 2899 * PHY_LOCK required and not held). 2900 */ 2901 #define MC_CMD_NVRAM_UPDATE_START 0x38 2902 2903 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */ 2904 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 2905 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 2906 /* Enum values, see field(s): */ 2907 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 2908 2909 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 2910 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 2911 2912 2913 /***********************************/ 2914 /* MC_CMD_NVRAM_READ 2915 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if 2916 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 2917 * PHY_LOCK required and not held) 2918 */ 2919 #define MC_CMD_NVRAM_READ 0x39 2920 2921 /* MC_CMD_NVRAM_READ_IN msgrequest */ 2922 #define MC_CMD_NVRAM_READ_IN_LEN 12 2923 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 2924 /* Enum values, see field(s): */ 2925 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 2926 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 2927 /* amount to read in bytes */ 2928 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 2929 2930 /* MC_CMD_NVRAM_READ_OUT msgresponse */ 2931 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 2932 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 2933 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 2934 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 2935 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 2936 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 2937 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 2938 2939 2940 /***********************************/ 2941 /* MC_CMD_NVRAM_WRITE 2942 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if 2943 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 2944 * PHY_LOCK required and not held) 2945 */ 2946 #define MC_CMD_NVRAM_WRITE 0x3a 2947 2948 /* MC_CMD_NVRAM_WRITE_IN msgrequest */ 2949 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 2950 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 2951 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 2952 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 2953 /* Enum values, see field(s): */ 2954 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 2955 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 2956 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 2957 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 2958 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 2959 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 2960 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 2961 2962 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 2963 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 2964 2965 2966 /***********************************/ 2967 /* MC_CMD_NVRAM_ERASE 2968 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if 2969 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 2970 * PHY_LOCK required and not held) 2971 */ 2972 #define MC_CMD_NVRAM_ERASE 0x3b 2973 2974 /* MC_CMD_NVRAM_ERASE_IN msgrequest */ 2975 #define MC_CMD_NVRAM_ERASE_IN_LEN 12 2976 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 2977 /* Enum values, see field(s): */ 2978 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 2979 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 2980 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 2981 2982 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 2983 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 2984 2985 2986 /***********************************/ 2987 /* MC_CMD_NVRAM_UPDATE_FINISH 2988 * Finish a group of update operations on a virtual NVRAM partition. Locks 2989 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad 2990 * type/offset/length), EACCES (if PHY_LOCK required and not held) 2991 */ 2992 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 2993 2994 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */ 2995 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 2996 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 2997 /* Enum values, see field(s): */ 2998 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 2999 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 3000 3001 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */ 3002 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 3003 3004 3005 /***********************************/ 3006 /* MC_CMD_REBOOT 3007 * Reboot the MC. 3008 * 3009 * The AFTER_ASSERTION flag is intended to be used when the driver notices an 3010 * assertion failure (at which point it is expected to perform a complete tear 3011 * down and reinitialise), to allow both ports to reset the MC once in an 3012 * atomic fashion. 3013 * 3014 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, 3015 * which means that they will automatically reboot out of the assertion 3016 * handler, so this is in practise an optional operation. It is still 3017 * recommended that drivers execute this to support custom firmwares with 3018 * REBOOT_ON_ASSERT=0. 3019 * 3020 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, 3021 * DATALEN=0 3022 */ 3023 #define MC_CMD_REBOOT 0x3d 3024 3025 /* MC_CMD_REBOOT_IN msgrequest */ 3026 #define MC_CMD_REBOOT_IN_LEN 4 3027 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 3028 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 3029 3030 /* MC_CMD_REBOOT_OUT msgresponse */ 3031 #define MC_CMD_REBOOT_OUT_LEN 0 3032 3033 3034 /***********************************/ 3035 /* MC_CMD_SCHEDINFO 3036 * Request scheduler info. Locks required: NONE. Returns: An array of 3037 * (timeslice,maximum overrun), one for each thread, in ascending order of 3038 * thread address. 3039 */ 3040 #define MC_CMD_SCHEDINFO 0x3e 3041 3042 /* MC_CMD_SCHEDINFO_IN msgrequest */ 3043 #define MC_CMD_SCHEDINFO_IN_LEN 0 3044 3045 /* MC_CMD_SCHEDINFO_OUT msgresponse */ 3046 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 3047 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 3048 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 3049 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 3050 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 3051 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 3052 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 3053 3054 3055 /***********************************/ 3056 /* MC_CMD_REBOOT_MODE 3057 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot 3058 * mode to the specified value. Returns the old mode. 3059 */ 3060 #define MC_CMD_REBOOT_MODE 0x3f 3061 3062 /* MC_CMD_REBOOT_MODE_IN msgrequest */ 3063 #define MC_CMD_REBOOT_MODE_IN_LEN 4 3064 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 3065 /* enum: Normal. */ 3066 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 3067 /* enum: Power-on Reset. */ 3068 #define MC_CMD_REBOOT_MODE_POR 0x2 3069 /* enum: Snapper. */ 3070 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 3071 /* enum: snapper fake POR */ 3072 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 3073 #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 3074 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 3075 3076 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 3077 #define MC_CMD_REBOOT_MODE_OUT_LEN 4 3078 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 3079 3080 3081 /***********************************/ 3082 /* MC_CMD_SENSOR_INFO 3083 * Returns information about every available sensor. 3084 * 3085 * Each sensor has a single (16bit) value, and a corresponding state. The 3086 * mapping between value and state is nominally determined by the MC, but may 3087 * be implemented using up to 2 ranges per sensor. 3088 * 3089 * This call returns a mask (32bit) of the sensors that are supported by this 3090 * platform, then an array of sensor information structures, in order of sensor 3091 * type (but without gaps for unimplemented sensors). Each structure defines 3092 * the ranges for the corresponding sensor. An unused range is indicated by 3093 * equal limit values. If one range is used, a value outside that range results 3094 * in STATE_FATAL. If two ranges are used, a value outside the second range 3095 * results in STATE_FATAL while a value outside the first and inside the second 3096 * range results in STATE_WARNING. 3097 * 3098 * Sensor masks and sensor information arrays are organised into pages. For 3099 * backward compatibility, older host software can only use sensors in page 0. 3100 * Bit 32 in the sensor mask was previously unused, and is no reserved for use 3101 * as the next page flag. 3102 * 3103 * If the request does not contain a PAGE value then firmware will only return 3104 * page 0 of sensor information, with bit 31 in the sensor mask cleared. 3105 * 3106 * If the request contains a PAGE value then firmware responds with the sensor 3107 * mask and sensor information array for that page of sensors. In this case bit 3108 * 31 in the mask is set if another page exists. 3109 * 3110 * Locks required: None Returns: 0 3111 */ 3112 #define MC_CMD_SENSOR_INFO 0x41 3113 3114 /* MC_CMD_SENSOR_INFO_IN msgrequest */ 3115 #define MC_CMD_SENSOR_INFO_IN_LEN 0 3116 3117 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ 3118 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 3119 /* Which page of sensors to report. 3120 * 3121 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). 3122 * 3123 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. 3124 */ 3125 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 3126 3127 /* MC_CMD_SENSOR_INFO_OUT msgresponse */ 3128 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 12 3129 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 3130 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 3131 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 3132 /* enum: Controller temperature: degC */ 3133 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 3134 /* enum: Phy common temperature: degC */ 3135 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 3136 /* enum: Controller cooling: bool */ 3137 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 3138 /* enum: Phy 0 temperature: degC */ 3139 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 3140 /* enum: Phy 0 cooling: bool */ 3141 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 3142 /* enum: Phy 1 temperature: degC */ 3143 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 3144 /* enum: Phy 1 cooling: bool */ 3145 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 3146 /* enum: 1.0v power: mV */ 3147 #define MC_CMD_SENSOR_IN_1V0 0x7 3148 /* enum: 1.2v power: mV */ 3149 #define MC_CMD_SENSOR_IN_1V2 0x8 3150 /* enum: 1.8v power: mV */ 3151 #define MC_CMD_SENSOR_IN_1V8 0x9 3152 /* enum: 2.5v power: mV */ 3153 #define MC_CMD_SENSOR_IN_2V5 0xa 3154 /* enum: 3.3v power: mV */ 3155 #define MC_CMD_SENSOR_IN_3V3 0xb 3156 /* enum: 12v power: mV */ 3157 #define MC_CMD_SENSOR_IN_12V0 0xc 3158 /* enum: 1.2v analogue power: mV */ 3159 #define MC_CMD_SENSOR_IN_1V2A 0xd 3160 /* enum: reference voltage: mV */ 3161 #define MC_CMD_SENSOR_IN_VREF 0xe 3162 /* enum: AOE FPGA power: mV */ 3163 #define MC_CMD_SENSOR_OUT_VAOE 0xf 3164 /* enum: AOE FPGA temperature: degC */ 3165 #define MC_CMD_SENSOR_AOE_TEMP 0x10 3166 /* enum: AOE FPGA PSU temperature: degC */ 3167 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 3168 /* enum: AOE PSU temperature: degC */ 3169 #define MC_CMD_SENSOR_PSU_TEMP 0x12 3170 /* enum: Fan 0 speed: RPM */ 3171 #define MC_CMD_SENSOR_FAN_0 0x13 3172 /* enum: Fan 1 speed: RPM */ 3173 #define MC_CMD_SENSOR_FAN_1 0x14 3174 /* enum: Fan 2 speed: RPM */ 3175 #define MC_CMD_SENSOR_FAN_2 0x15 3176 /* enum: Fan 3 speed: RPM */ 3177 #define MC_CMD_SENSOR_FAN_3 0x16 3178 /* enum: Fan 4 speed: RPM */ 3179 #define MC_CMD_SENSOR_FAN_4 0x17 3180 /* enum: AOE FPGA input power: mV */ 3181 #define MC_CMD_SENSOR_IN_VAOE 0x18 3182 /* enum: AOE FPGA current: mA */ 3183 #define MC_CMD_SENSOR_OUT_IAOE 0x19 3184 /* enum: AOE FPGA input current: mA */ 3185 #define MC_CMD_SENSOR_IN_IAOE 0x1a 3186 /* enum: NIC power consumption: W */ 3187 #define MC_CMD_SENSOR_NIC_POWER 0x1b 3188 /* enum: 0.9v power voltage: mV */ 3189 #define MC_CMD_SENSOR_IN_0V9 0x1c 3190 /* enum: 0.9v power current: mA */ 3191 #define MC_CMD_SENSOR_IN_I0V9 0x1d 3192 /* enum: 1.2v power current: mA */ 3193 #define MC_CMD_SENSOR_IN_I1V2 0x1e 3194 /* enum: Not a sensor: reserved for the next page flag */ 3195 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f 3196 /* enum: 0.9v power voltage (at ADC): mV */ 3197 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 3198 /* enum: Controller temperature 2: degC */ 3199 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 3200 /* enum: Voltage regulator internal temperature: degC */ 3201 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 3202 /* enum: 0.9V voltage regulator temperature: degC */ 3203 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 3204 /* enum: 1.2V voltage regulator temperature: degC */ 3205 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 3206 /* enum: controller internal temperature sensor voltage (internal ADC): mV */ 3207 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 3208 /* enum: controller internal temperature (internal ADC): degC */ 3209 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 3210 /* enum: controller internal temperature sensor voltage (external ADC): mV */ 3211 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 3212 /* enum: controller internal temperature (external ADC): degC */ 3213 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 3214 /* enum: ambient temperature: degC */ 3215 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 3216 /* enum: air flow: bool */ 3217 #define MC_CMD_SENSOR_AIRFLOW 0x2a 3218 /* enum: voltage between VSS08D and VSS08D at CSR: mV */ 3219 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b 3220 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ 3221 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c 3222 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 3223 #define MC_CMD_SENSOR_ENTRY_OFST 4 3224 #define MC_CMD_SENSOR_ENTRY_LEN 8 3225 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 3226 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 3227 #define MC_CMD_SENSOR_ENTRY_MINNUM 1 3228 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 3229 3230 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ 3231 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 12 3232 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 3233 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) 3234 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 3235 /* Enum values, see field(s): */ 3236 /* MC_CMD_SENSOR_INFO_OUT */ 3237 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 3238 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 3239 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 3240 /* MC_CMD_SENSOR_ENTRY_OFST 4 */ 3241 /* MC_CMD_SENSOR_ENTRY_LEN 8 */ 3242 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ 3243 /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ 3244 /* MC_CMD_SENSOR_ENTRY_MINNUM 1 */ 3245 /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ 3246 3247 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 3248 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 3249 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 3250 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 3251 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 3252 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 3253 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 3254 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 3255 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 3256 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 3257 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 3258 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 3259 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 3260 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 3261 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 3262 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 3263 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 3264 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 3265 3266 3267 /***********************************/ 3268 /* MC_CMD_READ_SENSORS 3269 * Returns the current reading from each sensor. DMAs an array of sensor 3270 * readings, in order of sensor type (but without gaps for unimplemented 3271 * sensors), into host memory. Each array element is a 3272 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. 3273 * 3274 * If the request does not contain the LENGTH field then only sensors 0 to 30 3275 * are reported, to avoid DMA buffer overflow in older host software. If the 3276 * sensor reading require more space than the LENGTH allows, then return 3277 * EINVAL. 3278 * 3279 * The MC will send a SENSOREVT event every time any sensor changes state. The 3280 * driver is responsible for ensuring that it doesn't miss any events. The 3281 * board will function normally if all sensors are in STATE_OK or 3282 * STATE_WARNING. Otherwise the board should not be expected to function. 3283 */ 3284 #define MC_CMD_READ_SENSORS 0x42 3285 3286 /* MC_CMD_READ_SENSORS_IN msgrequest */ 3287 #define MC_CMD_READ_SENSORS_IN_LEN 8 3288 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 3289 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 3290 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 3291 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 3292 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 3293 3294 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ 3295 #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 3296 /* DMA address of host buffer for sensor readings */ 3297 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 3298 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 3299 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 3300 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 3301 /* Size in bytes of host buffer. */ 3302 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 3303 3304 /* MC_CMD_READ_SENSORS_OUT msgresponse */ 3305 #define MC_CMD_READ_SENSORS_OUT_LEN 0 3306 3307 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ 3308 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 3309 3310 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 3311 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 3312 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 3313 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 3314 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 3315 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 3316 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 3317 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 3318 /* enum: Ok. */ 3319 #define MC_CMD_SENSOR_STATE_OK 0x0 3320 /* enum: Breached warning threshold. */ 3321 #define MC_CMD_SENSOR_STATE_WARNING 0x1 3322 /* enum: Breached fatal threshold. */ 3323 #define MC_CMD_SENSOR_STATE_FATAL 0x2 3324 /* enum: Fault with sensor. */ 3325 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 3326 /* enum: Sensor is working but does not currently have a reading. */ 3327 #define MC_CMD_SENSOR_STATE_NO_READING 0x4 3328 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 3329 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 3330 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 3331 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 3332 /* Enum values, see field(s): */ 3333 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 3334 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 3335 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 3336 3337 3338 /***********************************/ 3339 /* MC_CMD_GET_PHY_STATE 3340 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot 3341 * (e.g. due to missing or corrupted firmware). Locks required: None. Return 3342 * code: 0 3343 */ 3344 #define MC_CMD_GET_PHY_STATE 0x43 3345 3346 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 3347 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 3348 3349 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 3350 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 3351 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 3352 /* enum: Ok. */ 3353 #define MC_CMD_PHY_STATE_OK 0x1 3354 /* enum: Faulty. */ 3355 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 3356 3357 3358 /***********************************/ 3359 /* MC_CMD_SETUP_8021QBB 3360 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 3361 * disable 802.Qbb for a given priority. 3362 */ 3363 #define MC_CMD_SETUP_8021QBB 0x44 3364 3365 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 3366 #define MC_CMD_SETUP_8021QBB_IN_LEN 32 3367 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 3368 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 3369 3370 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 3371 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 3372 3373 3374 /***********************************/ 3375 /* MC_CMD_WOL_FILTER_GET 3376 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS 3377 */ 3378 #define MC_CMD_WOL_FILTER_GET 0x45 3379 3380 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 3381 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 3382 3383 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 3384 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 3385 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 3386 3387 3388 /***********************************/ 3389 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 3390 * Add a protocol offload to NIC for lights-out state. Locks required: None. 3391 * Returns: 0, ENOSYS 3392 */ 3393 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 3394 3395 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 3396 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 3397 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 3398 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 3399 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 3400 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 3401 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 3402 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 3403 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 3404 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 3405 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 3406 3407 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 3408 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 3409 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 3410 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 3411 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 3412 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 3413 3414 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 3415 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 3416 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 3417 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 3418 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 3419 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 3420 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 3421 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 3422 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 3423 3424 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 3425 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 3426 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 3427 3428 3429 /***********************************/ 3430 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 3431 * Remove a protocol offload from NIC for lights-out state. Locks required: 3432 * None. Returns: 0, ENOSYS 3433 */ 3434 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 3435 3436 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 3437 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 3438 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 3439 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 3440 3441 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 3442 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 3443 3444 3445 /***********************************/ 3446 /* MC_CMD_MAC_RESET_RESTORE 3447 * Restore MAC after block reset. Locks required: None. Returns: 0. 3448 */ 3449 #define MC_CMD_MAC_RESET_RESTORE 0x48 3450 3451 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 3452 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 3453 3454 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 3455 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 3456 3457 3458 /***********************************/ 3459 /* MC_CMD_TESTASSERT 3460 * Deliberately trigger an assert-detonation in the firmware for testing 3461 * purposes (i.e. to allow tests that the driver copes gracefully). Locks 3462 * required: None Returns: 0 3463 */ 3464 #define MC_CMD_TESTASSERT 0x49 3465 3466 /* MC_CMD_TESTASSERT_IN msgrequest */ 3467 #define MC_CMD_TESTASSERT_IN_LEN 0 3468 3469 /* MC_CMD_TESTASSERT_OUT msgresponse */ 3470 #define MC_CMD_TESTASSERT_OUT_LEN 0 3471 3472 3473 /***********************************/ 3474 /* MC_CMD_WORKAROUND 3475 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't 3476 * understand the given workaround number - which should not be treated as a 3477 * hard error by client code. This op does not imply any semantics about each 3478 * workaround, that's between the driver and the mcfw on a per-workaround 3479 * basis. Locks required: None. Returns: 0, EINVAL . 3480 */ 3481 #define MC_CMD_WORKAROUND 0x4a 3482 3483 /* MC_CMD_WORKAROUND_IN msgrequest */ 3484 #define MC_CMD_WORKAROUND_IN_LEN 8 3485 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 3486 /* enum: Bug 17230 work around. */ 3487 #define MC_CMD_WORKAROUND_BUG17230 0x1 3488 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 3489 #define MC_CMD_WORKAROUND_BUG35388 0x2 3490 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 3491 #define MC_CMD_WORKAROUND_BUG35017 0x3 3492 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 3493 3494 /* MC_CMD_WORKAROUND_OUT msgresponse */ 3495 #define MC_CMD_WORKAROUND_OUT_LEN 0 3496 3497 3498 /***********************************/ 3499 /* MC_CMD_GET_PHY_MEDIA_INFO 3500 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for 3501 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG 3502 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the 3503 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 3504 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. 3505 * Anything else: currently undefined. Locks required: None. Return code: 0. 3506 */ 3507 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 3508 3509 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 3510 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 3511 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 3512 3513 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 3514 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 3515 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 3516 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 3517 /* in bytes */ 3518 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 3519 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 3520 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 3521 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 3522 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 3523 3524 3525 /***********************************/ 3526 /* MC_CMD_NVRAM_TEST 3527 * Test a particular NVRAM partition for valid contents (where "valid" depends 3528 * on the type of partition). 3529 */ 3530 #define MC_CMD_NVRAM_TEST 0x4c 3531 3532 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 3533 #define MC_CMD_NVRAM_TEST_IN_LEN 4 3534 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 3535 /* Enum values, see field(s): */ 3536 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3537 3538 /* MC_CMD_NVRAM_TEST_OUT msgresponse */ 3539 #define MC_CMD_NVRAM_TEST_OUT_LEN 4 3540 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 3541 /* enum: Passed. */ 3542 #define MC_CMD_NVRAM_TEST_PASS 0x0 3543 /* enum: Failed. */ 3544 #define MC_CMD_NVRAM_TEST_FAIL 0x1 3545 /* enum: Not supported. */ 3546 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 3547 3548 3549 /***********************************/ 3550 /* MC_CMD_MRSFP_TWEAK 3551 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. 3552 * I2C I/O expander bits are always read; if equaliser parameters are supplied, 3553 * they are configured first. Locks required: None. Return code: 0, EINVAL. 3554 */ 3555 #define MC_CMD_MRSFP_TWEAK 0x4d 3556 3557 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 3558 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 3559 /* 0-6 low->high de-emph. */ 3560 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 3561 /* 0-8 low->high ref.V */ 3562 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 3563 /* 0-8 0-8 low->high boost */ 3564 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 3565 /* 0-8 low->high ref.V */ 3566 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 3567 3568 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 3569 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 3570 3571 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 3572 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 3573 /* input bits */ 3574 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 3575 /* output bits */ 3576 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 3577 /* direction */ 3578 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 3579 /* enum: Out. */ 3580 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 3581 /* enum: In. */ 3582 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 3583 3584 3585 /***********************************/ 3586 /* MC_CMD_SENSOR_SET_LIMS 3587 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: 3588 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out 3589 * of range. 3590 */ 3591 #define MC_CMD_SENSOR_SET_LIMS 0x4e 3592 3593 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 3594 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 3595 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 3596 /* Enum values, see field(s): */ 3597 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 3598 /* interpretation is is sensor-specific. */ 3599 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 3600 /* interpretation is is sensor-specific. */ 3601 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 3602 /* interpretation is is sensor-specific. */ 3603 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 3604 /* interpretation is is sensor-specific. */ 3605 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 3606 3607 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 3608 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 3609 3610 3611 /***********************************/ 3612 /* MC_CMD_GET_RESOURCE_LIMITS 3613 */ 3614 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 3615 3616 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 3617 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 3618 3619 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 3620 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 3621 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 3622 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 3623 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 3624 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 3625 3626 3627 /***********************************/ 3628 /* MC_CMD_NVRAM_PARTITIONS 3629 * Reads the list of available virtual NVRAM partition types. Locks required: 3630 * none. Returns: 0, EINVAL (bad type). 3631 */ 3632 #define MC_CMD_NVRAM_PARTITIONS 0x51 3633 3634 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ 3635 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 3636 3637 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ 3638 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 3639 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 3640 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) 3641 /* total number of partitions */ 3642 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 3643 /* type ID code for each of NUM_PARTITIONS partitions */ 3644 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 3645 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 3646 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 3647 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 3648 3649 3650 /***********************************/ 3651 /* MC_CMD_NVRAM_METADATA 3652 * Reads soft metadata for a virtual NVRAM partition type. Locks required: 3653 * none. Returns: 0, EINVAL (bad type). 3654 */ 3655 #define MC_CMD_NVRAM_METADATA 0x52 3656 3657 /* MC_CMD_NVRAM_METADATA_IN msgrequest */ 3658 #define MC_CMD_NVRAM_METADATA_IN_LEN 4 3659 /* Partition type ID code */ 3660 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 3661 3662 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */ 3663 #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 3664 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 3665 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) 3666 /* Partition type ID code */ 3667 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 3668 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 3669 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 3670 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 3671 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 3672 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 3673 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 3674 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 3675 /* Subtype ID code for content of this partition */ 3676 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 3677 /* 1st component of W.X.Y.Z version number for content of this partition */ 3678 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 3679 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 3680 /* 2nd component of W.X.Y.Z version number for content of this partition */ 3681 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 3682 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 3683 /* 3rd component of W.X.Y.Z version number for content of this partition */ 3684 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 3685 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 3686 /* 4th component of W.X.Y.Z version number for content of this partition */ 3687 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 3688 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 3689 /* Zero-terminated string describing the content of this partition */ 3690 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 3691 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 3692 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 3693 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 3694 3695 3696 /***********************************/ 3697 /* MC_CMD_GET_MAC_ADDRESSES 3698 * Returns the base MAC, count and stride for the requestiong function 3699 */ 3700 #define MC_CMD_GET_MAC_ADDRESSES 0x55 3701 3702 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ 3703 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 3704 3705 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ 3706 #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 3707 /* Base MAC address */ 3708 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 3709 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 3710 /* Padding */ 3711 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 3712 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 3713 /* Number of allocated MAC addresses */ 3714 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 3715 /* Spacing of allocated MAC addresses */ 3716 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 3717 3718 /* MC_CMD_RESOURCE_SPECIFIER enum */ 3719 /* enum: Any */ 3720 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff 3721 /* enum: None */ 3722 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe 3723 3724 /* EVB_PORT_ID structuredef */ 3725 #define EVB_PORT_ID_LEN 4 3726 #define EVB_PORT_ID_PORT_ID_OFST 0 3727 /* enum: An invalid port handle. */ 3728 #define EVB_PORT_ID_NULL 0x0 3729 /* enum: The port assigned to this function.. */ 3730 #define EVB_PORT_ID_ASSIGNED 0x1000000 3731 /* enum: External network port 0 */ 3732 #define EVB_PORT_ID_MAC0 0x2000000 3733 /* enum: External network port 1 */ 3734 #define EVB_PORT_ID_MAC1 0x2000001 3735 /* enum: External network port 2 */ 3736 #define EVB_PORT_ID_MAC2 0x2000002 3737 /* enum: External network port 3 */ 3738 #define EVB_PORT_ID_MAC3 0x2000003 3739 #define EVB_PORT_ID_PORT_ID_LBN 0 3740 #define EVB_PORT_ID_PORT_ID_WIDTH 32 3741 3742 /* EVB_VLAN_TAG structuredef */ 3743 #define EVB_VLAN_TAG_LEN 2 3744 /* The VLAN tag value */ 3745 #define EVB_VLAN_TAG_VLAN_ID_LBN 0 3746 #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 3747 #define EVB_VLAN_TAG_MODE_LBN 12 3748 #define EVB_VLAN_TAG_MODE_WIDTH 4 3749 /* enum: Insert the VLAN. */ 3750 #define EVB_VLAN_TAG_INSERT 0x0 3751 /* enum: Replace the VLAN if already present. */ 3752 #define EVB_VLAN_TAG_REPLACE 0x1 3753 3754 /* BUFTBL_ENTRY structuredef */ 3755 #define BUFTBL_ENTRY_LEN 12 3756 /* the owner ID */ 3757 #define BUFTBL_ENTRY_OID_OFST 0 3758 #define BUFTBL_ENTRY_OID_LEN 2 3759 #define BUFTBL_ENTRY_OID_LBN 0 3760 #define BUFTBL_ENTRY_OID_WIDTH 16 3761 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ 3762 #define BUFTBL_ENTRY_PGSZ_OFST 2 3763 #define BUFTBL_ENTRY_PGSZ_LEN 2 3764 #define BUFTBL_ENTRY_PGSZ_LBN 16 3765 #define BUFTBL_ENTRY_PGSZ_WIDTH 16 3766 /* the raw 64-bit address field from the SMC, not adjusted for page size */ 3767 #define BUFTBL_ENTRY_RAWADDR_OFST 4 3768 #define BUFTBL_ENTRY_RAWADDR_LEN 8 3769 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 3770 #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 3771 #define BUFTBL_ENTRY_RAWADDR_LBN 32 3772 #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 3773 3774 /* NVRAM_PARTITION_TYPE structuredef */ 3775 #define NVRAM_PARTITION_TYPE_LEN 2 3776 #define NVRAM_PARTITION_TYPE_ID_OFST 0 3777 #define NVRAM_PARTITION_TYPE_ID_LEN 2 3778 /* enum: Primary MC firmware partition */ 3779 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 3780 /* enum: Secondary MC firmware partition */ 3781 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 3782 /* enum: Expansion ROM partition */ 3783 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 3784 /* enum: Static configuration TLV partition */ 3785 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 3786 /* enum: Dynamic configuration TLV partition */ 3787 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 3788 /* enum: Expansion ROM configuration data for port 0 */ 3789 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 3790 /* enum: Expansion ROM configuration data for port 1 */ 3791 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 3792 /* enum: Expansion ROM configuration data for port 2 */ 3793 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 3794 /* enum: Expansion ROM configuration data for port 3 */ 3795 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 3796 /* enum: Non-volatile log output partition */ 3797 #define NVRAM_PARTITION_TYPE_LOG 0x700 3798 /* enum: Device state dump output partition */ 3799 #define NVRAM_PARTITION_TYPE_DUMP 0x800 3800 /* enum: Application license key storage partition */ 3801 #define NVRAM_PARTITION_TYPE_LICENSE 0x900 3802 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ 3803 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 3804 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ 3805 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff 3806 /* enum: Start of reserved value range (firmware may use for any purpose) */ 3807 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 3808 /* enum: End of reserved value range (firmware may use for any purpose) */ 3809 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd 3810 /* enum: Recovery partition map (provided if real map is missing or corrupt) */ 3811 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe 3812 /* enum: Partition map (real map as stored in flash) */ 3813 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff 3814 #define NVRAM_PARTITION_TYPE_ID_LBN 0 3815 #define NVRAM_PARTITION_TYPE_ID_WIDTH 16 3816 3817 3818 /***********************************/ 3819 /* MC_CMD_READ_REGS 3820 * Get a dump of the MCPU registers 3821 */ 3822 #define MC_CMD_READ_REGS 0x50 3823 3824 /* MC_CMD_READ_REGS_IN msgrequest */ 3825 #define MC_CMD_READ_REGS_IN_LEN 0 3826 3827 /* MC_CMD_READ_REGS_OUT msgresponse */ 3828 #define MC_CMD_READ_REGS_OUT_LEN 308 3829 /* Whether the corresponding register entry contains a valid value */ 3830 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 3831 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 3832 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, 3833 * fir, fp) 3834 */ 3835 #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 3836 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 3837 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 3838 3839 3840 /***********************************/ 3841 /* MC_CMD_INIT_EVQ 3842 * Set up an event queue according to the supplied parameters. The IN arguments 3843 * end with an address for each 4k of host memory required to back the EVQ. 3844 */ 3845 #define MC_CMD_INIT_EVQ 0x80 3846 3847 /* MC_CMD_INIT_EVQ_IN msgrequest */ 3848 #define MC_CMD_INIT_EVQ_IN_LENMIN 44 3849 #define MC_CMD_INIT_EVQ_IN_LENMAX 548 3850 #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) 3851 /* Size, in entries */ 3852 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 3853 /* Desired instance. Must be set to a specific instance, which is a function 3854 * local queue index. 3855 */ 3856 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 3857 /* The initial timer value. The load value is ignored if the timer mode is DIS. 3858 */ 3859 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 3860 /* The reload value is ignored in one-shot modes */ 3861 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 3862 /* tbd */ 3863 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 3864 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 3865 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 3866 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 3867 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 3868 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 3869 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 3870 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 3871 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 3872 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 3873 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 3874 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 3875 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 3876 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 3877 /* enum: Disabled */ 3878 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 3879 /* enum: Immediate */ 3880 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 3881 /* enum: Triggered */ 3882 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 3883 /* enum: Hold-off */ 3884 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 3885 /* Target EVQ for wakeups if in wakeup mode. */ 3886 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 3887 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 3888 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 3889 * purposes. 3890 */ 3891 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 3892 /* Event Counter Mode. */ 3893 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 3894 /* enum: Disabled */ 3895 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 3896 /* enum: Disabled */ 3897 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 3898 /* enum: Disabled */ 3899 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 3900 /* enum: Disabled */ 3901 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 3902 /* Event queue packet count threshold. */ 3903 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 3904 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 3905 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 3906 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 3907 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 3908 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 3909 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 3910 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 3911 3912 /* MC_CMD_INIT_EVQ_OUT msgresponse */ 3913 #define MC_CMD_INIT_EVQ_OUT_LEN 4 3914 /* Only valid if INTRFLAG was true */ 3915 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 3916 3917 /* QUEUE_CRC_MODE structuredef */ 3918 #define QUEUE_CRC_MODE_LEN 1 3919 #define QUEUE_CRC_MODE_MODE_LBN 0 3920 #define QUEUE_CRC_MODE_MODE_WIDTH 4 3921 /* enum: No CRC. */ 3922 #define QUEUE_CRC_MODE_NONE 0x0 3923 /* enum: CRC Fiber channel over ethernet. */ 3924 #define QUEUE_CRC_MODE_FCOE 0x1 3925 /* enum: CRC (digest) iSCSI header only. */ 3926 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 3927 /* enum: CRC (digest) iSCSI header and payload. */ 3928 #define QUEUE_CRC_MODE_ISCSI 0x3 3929 /* enum: CRC Fiber channel over IP over ethernet. */ 3930 #define QUEUE_CRC_MODE_FCOIPOE 0x4 3931 /* enum: CRC MPA. */ 3932 #define QUEUE_CRC_MODE_MPA 0x5 3933 #define QUEUE_CRC_MODE_SPARE_LBN 4 3934 #define QUEUE_CRC_MODE_SPARE_WIDTH 4 3935 3936 3937 /***********************************/ 3938 /* MC_CMD_INIT_RXQ 3939 * set up a receive queue according to the supplied parameters. The IN 3940 * arguments end with an address for each 4k of host memory required to back 3941 * the RXQ. 3942 */ 3943 #define MC_CMD_INIT_RXQ 0x81 3944 3945 /* MC_CMD_INIT_RXQ_IN msgrequest */ 3946 #define MC_CMD_INIT_RXQ_IN_LENMIN 36 3947 #define MC_CMD_INIT_RXQ_IN_LENMAX 252 3948 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) 3949 /* Size, in entries */ 3950 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 3951 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 3952 */ 3953 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 3954 /* The value to put in the event data. Check hardware spec. for valid range. */ 3955 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 3956 /* Desired instance. Must be set to a specific instance, which is a function 3957 * local queue index. 3958 */ 3959 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 3960 /* There will be more flags here. */ 3961 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 3962 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 3963 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 3964 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 3965 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 3966 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 3967 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 3968 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 3969 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 3970 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 3971 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 3972 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 3973 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 3974 /* Owner ID to use if in buffer mode (zero if physical) */ 3975 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 3976 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 3977 #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 3978 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 3979 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 3980 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 3981 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 3982 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 3983 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 3984 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 3985 3986 /* MC_CMD_INIT_RXQ_OUT msgresponse */ 3987 #define MC_CMD_INIT_RXQ_OUT_LEN 0 3988 3989 3990 /***********************************/ 3991 /* MC_CMD_INIT_TXQ 3992 */ 3993 #define MC_CMD_INIT_TXQ 0x82 3994 3995 /* MC_CMD_INIT_TXQ_IN msgrequest */ 3996 #define MC_CMD_INIT_TXQ_IN_LENMIN 36 3997 #define MC_CMD_INIT_TXQ_IN_LENMAX 252 3998 #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) 3999 /* Size, in entries */ 4000 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 4001 /* The EVQ to send events to. This is an index originally specified to 4002 * INIT_EVQ. 4003 */ 4004 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 4005 /* The value to put in the event data. Check hardware spec. for valid range. */ 4006 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 4007 /* Desired instance. Must be set to a specific instance, which is a function 4008 * local queue index. 4009 */ 4010 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 4011 /* There will be more flags here. */ 4012 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 4013 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 4014 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 4015 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 4016 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 4017 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 4018 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 4019 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 4020 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 4021 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 4022 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 4023 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 4024 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 4025 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 4026 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 4027 /* Owner ID to use if in buffer mode (zero if physical) */ 4028 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 4029 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 4030 #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 4031 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 4032 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 4033 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 4034 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 4035 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 4036 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 4037 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 4038 4039 /* MC_CMD_INIT_TXQ_OUT msgresponse */ 4040 #define MC_CMD_INIT_TXQ_OUT_LEN 0 4041 4042 4043 /***********************************/ 4044 /* MC_CMD_FINI_EVQ 4045 * Teardown an EVQ. 4046 * 4047 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first 4048 * or the operation will fail with EBUSY 4049 */ 4050 #define MC_CMD_FINI_EVQ 0x83 4051 4052 /* MC_CMD_FINI_EVQ_IN msgrequest */ 4053 #define MC_CMD_FINI_EVQ_IN_LEN 4 4054 /* Instance of EVQ to destroy. Should be the same instance as that previously 4055 * passed to INIT_EVQ 4056 */ 4057 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 4058 4059 /* MC_CMD_FINI_EVQ_OUT msgresponse */ 4060 #define MC_CMD_FINI_EVQ_OUT_LEN 0 4061 4062 4063 /***********************************/ 4064 /* MC_CMD_FINI_RXQ 4065 * Teardown a RXQ. 4066 */ 4067 #define MC_CMD_FINI_RXQ 0x84 4068 4069 /* MC_CMD_FINI_RXQ_IN msgrequest */ 4070 #define MC_CMD_FINI_RXQ_IN_LEN 4 4071 /* Instance of RXQ to destroy */ 4072 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 4073 4074 /* MC_CMD_FINI_RXQ_OUT msgresponse */ 4075 #define MC_CMD_FINI_RXQ_OUT_LEN 0 4076 4077 4078 /***********************************/ 4079 /* MC_CMD_FINI_TXQ 4080 * Teardown a TXQ. 4081 */ 4082 #define MC_CMD_FINI_TXQ 0x85 4083 4084 /* MC_CMD_FINI_TXQ_IN msgrequest */ 4085 #define MC_CMD_FINI_TXQ_IN_LEN 4 4086 /* Instance of TXQ to destroy */ 4087 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 4088 4089 /* MC_CMD_FINI_TXQ_OUT msgresponse */ 4090 #define MC_CMD_FINI_TXQ_OUT_LEN 0 4091 4092 4093 /***********************************/ 4094 /* MC_CMD_DRIVER_EVENT 4095 * Generate an event on an EVQ belonging to the function issuing the command. 4096 */ 4097 #define MC_CMD_DRIVER_EVENT 0x86 4098 4099 /* MC_CMD_DRIVER_EVENT_IN msgrequest */ 4100 #define MC_CMD_DRIVER_EVENT_IN_LEN 12 4101 /* Handle of target EVQ */ 4102 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 4103 /* Bits 0 - 63 of event */ 4104 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 4105 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 4106 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 4107 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 4108 4109 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ 4110 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 4111 4112 4113 /***********************************/ 4114 /* MC_CMD_PROXY_CMD 4115 * Execute an arbitrary MCDI command on behalf of a different function, subject 4116 * to security restrictions. The command to be proxied follows immediately 4117 * afterward in the host buffer (or on the UART). This command supercedes 4118 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. 4119 */ 4120 #define MC_CMD_PROXY_CMD 0x5b 4121 4122 /* MC_CMD_PROXY_CMD_IN msgrequest */ 4123 #define MC_CMD_PROXY_CMD_IN_LEN 4 4124 /* The handle of the target function. */ 4125 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 4126 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 4127 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 4128 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 4129 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 4130 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ 4131 4132 4133 /***********************************/ 4134 /* MC_CMD_ALLOC_BUFTBL_CHUNK 4135 * Allocate a set of buffer table entries using the specified owner ID. This 4136 * operation allocates the required buffer table entries (and fails if it 4137 * cannot do so). The buffer table entries will initially be zeroed. 4138 */ 4139 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 4140 4141 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 4142 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 4143 /* Owner ID to use */ 4144 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 4145 /* Size of buffer table pages to use, in bytes (note that only a few values are 4146 * legal on any specific hardware). 4147 */ 4148 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 4149 4150 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 4151 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 4152 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 4153 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 4154 /* Buffer table IDs for use in DMA descriptors. */ 4155 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 4156 4157 4158 /***********************************/ 4159 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES 4160 * Reprogram a set of buffer table entries in the specified chunk. 4161 */ 4162 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 4163 4164 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 4165 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 4166 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 252 4167 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 4168 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 4169 /* ID */ 4170 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 4171 /* Num entries */ 4172 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 4173 /* Buffer table entry address */ 4174 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 4175 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 4176 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 4177 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 4178 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 4179 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 30 4180 4181 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 4182 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 4183 4184 4185 /***********************************/ 4186 /* MC_CMD_FREE_BUFTBL_CHUNK 4187 */ 4188 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 4189 4190 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 4191 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 4192 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 4193 4194 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 4195 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 4196 4197 4198 /***********************************/ 4199 /* MC_CMD_FILTER_OP 4200 * Multiplexed MCDI call for filter operations 4201 */ 4202 #define MC_CMD_FILTER_OP 0x8a 4203 4204 /* MC_CMD_FILTER_OP_IN msgrequest */ 4205 #define MC_CMD_FILTER_OP_IN_LEN 108 4206 /* identifies the type of operation requested */ 4207 #define MC_CMD_FILTER_OP_IN_OP_OFST 0 4208 /* enum: single-recipient filter insert */ 4209 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 4210 /* enum: single-recipient filter remove */ 4211 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 4212 /* enum: multi-recipient filter subscribe */ 4213 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 4214 /* enum: multi-recipient filter unsubscribe */ 4215 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 4216 /* enum: replace one recipient with another (warning - the filter handle may 4217 * change) 4218 */ 4219 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 4220 /* filter handle (for remove / unsubscribe operations) */ 4221 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 4222 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 4223 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 4224 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 4225 /* The port ID associated with the v-adaptor which should contain this filter. 4226 */ 4227 #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 4228 /* fields to include in match criteria */ 4229 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 4230 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 4231 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 4232 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 4233 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 4234 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 4235 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 4236 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 4237 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 4238 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 4239 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 4240 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 4241 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 4242 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 4243 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 4244 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 4245 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 4246 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 4247 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 4248 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 4249 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 4250 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 4251 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 4252 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 4253 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 4254 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 4255 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 4256 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 4257 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 4258 /* receive destination */ 4259 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 4260 /* enum: drop packets */ 4261 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 4262 /* enum: receive to host */ 4263 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 4264 /* enum: receive to MC */ 4265 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 4266 /* enum: loop back to port 0 TX MAC */ 4267 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 4268 /* enum: loop back to port 1 TX MAC */ 4269 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 4270 /* receive queue handle (for multiple queue modes, this is the base queue) */ 4271 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 4272 /* receive mode */ 4273 #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 4274 /* enum: receive to just the specified queue */ 4275 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 4276 /* enum: receive to multiple queues using RSS context */ 4277 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 4278 /* enum: receive to multiple queues using .1p mapping */ 4279 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 4280 /* enum: install a filter entry that will never match; for test purposes only 4281 */ 4282 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 4283 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 4284 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 4285 * MC_CMD_DOT1P_MAPPING_ALLOC. Note that these handles should be considered 4286 * opaque to the host, although a value of 0xFFFFFFFF is guaranteed never to be 4287 * a valid handle. 4288 */ 4289 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 4290 /* transmit domain (reserved; set to 0) */ 4291 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 4292 /* transmit destination (either set the MAC and/or PM bits for explicit 4293 * control, or set this field to TX_DEST_DEFAULT for sensible default 4294 * behaviour) 4295 */ 4296 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 4297 /* enum: request default behaviour (based on filter type) */ 4298 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff 4299 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 4300 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 4301 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 4302 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 4303 /* source MAC address to match (as bytes in network order) */ 4304 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 4305 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 4306 /* source port to match (as bytes in network order) */ 4307 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 4308 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 4309 /* destination MAC address to match (as bytes in network order) */ 4310 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 4311 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 4312 /* destination port to match (as bytes in network order) */ 4313 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 4314 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 4315 /* Ethernet type to match (as bytes in network order) */ 4316 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 4317 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 4318 /* Inner VLAN tag to match (as bytes in network order) */ 4319 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 4320 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 4321 /* Outer VLAN tag to match (as bytes in network order) */ 4322 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 4323 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 4324 /* IP protocol to match (in low byte; set high byte to 0) */ 4325 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 4326 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 4327 /* Firmware defined register 0 to match (reserved; set to 0) */ 4328 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 4329 /* Firmware defined register 1 to match (reserved; set to 0) */ 4330 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 4331 /* source IP address to match (as bytes in network order; set last 12 bytes to 4332 * 0 for IPv4 address) 4333 */ 4334 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 4335 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 4336 /* destination IP address to match (as bytes in network order; set last 12 4337 * bytes to 0 for IPv4 address) 4338 */ 4339 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 4340 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 4341 4342 /* MC_CMD_FILTER_OP_OUT msgresponse */ 4343 #define MC_CMD_FILTER_OP_OUT_LEN 12 4344 /* identifies the type of operation requested */ 4345 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 4346 /* Enum values, see field(s): */ 4347 /* MC_CMD_FILTER_OP_IN/OP */ 4348 /* Returned filter handle (for insert / subscribe operations). Note that these 4349 * handles should be considered opaque to the host, although a value of 4350 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 4351 */ 4352 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 4353 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 4354 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 4355 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 4356 4357 4358 /***********************************/ 4359 /* MC_CMD_GET_PARSER_DISP_INFO 4360 * Get information related to the parser-dispatcher subsystem 4361 */ 4362 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 4363 4364 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ 4365 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 4366 /* identifies the type of operation requested */ 4367 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 4368 /* enum: read the list of supported RX filter matches */ 4369 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 4370 4371 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ 4372 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 4373 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 4374 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) 4375 /* identifies the type of operation requested */ 4376 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 4377 /* Enum values, see field(s): */ 4378 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 4379 /* number of supported match types */ 4380 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 4381 /* array of supported match types (valid MATCH_FIELDS values for 4382 * MC_CMD_FILTER_OP) sorted in decreasing priority order 4383 */ 4384 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 4385 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 4386 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 4387 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 4388 4389 4390 /***********************************/ 4391 /* MC_CMD_PARSER_DISP_RW 4392 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging 4393 */ 4394 #define MC_CMD_PARSER_DISP_RW 0xe5 4395 4396 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ 4397 #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 4398 /* identifies the target of the operation */ 4399 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 4400 /* enum: RX dispatcher CPU */ 4401 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 4402 /* enum: TX dispatcher CPU */ 4403 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 4404 /* enum: Lookup engine */ 4405 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 4406 /* identifies the type of operation requested */ 4407 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 4408 /* enum: read a word of DICPU DMEM or a LUE entry */ 4409 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 4410 /* enum: write a word of DICPU DMEM or a LUE entry */ 4411 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 4412 /* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */ 4413 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 4414 /* data memory address or LUE index */ 4415 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 4416 /* value to write (for DMEM writes) */ 4417 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 4418 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 4419 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 4420 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 4421 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 4422 /* value to write (for LUE writes) */ 4423 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 4424 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 4425 4426 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ 4427 #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 4428 /* value read (for DMEM reads) */ 4429 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 4430 /* value read (for LUE reads) */ 4431 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 4432 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 4433 /* up to 8 32-bit words of additional soft state from the LUE manager (the 4434 * exact content is firmware-dependent and intended only for debug use) 4435 */ 4436 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 4437 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 4438 4439 4440 /***********************************/ 4441 /* MC_CMD_GET_PF_COUNT 4442 * Get number of PFs on the device. 4443 */ 4444 #define MC_CMD_GET_PF_COUNT 0xb6 4445 4446 /* MC_CMD_GET_PF_COUNT_IN msgrequest */ 4447 #define MC_CMD_GET_PF_COUNT_IN_LEN 0 4448 4449 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 4450 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 4451 /* Identifies the number of PFs on the device. */ 4452 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 4453 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 4454 4455 4456 /***********************************/ 4457 /* MC_CMD_SET_PF_COUNT 4458 * Set number of PFs on the device. 4459 */ 4460 #define MC_CMD_SET_PF_COUNT 0xb7 4461 4462 /* MC_CMD_SET_PF_COUNT_IN msgrequest */ 4463 #define MC_CMD_SET_PF_COUNT_IN_LEN 4 4464 /* New number of PFs on the device. */ 4465 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 4466 4467 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 4468 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 4469 4470 4471 /***********************************/ 4472 /* MC_CMD_GET_PORT_ASSIGNMENT 4473 * Get port assignment for current PCI function. 4474 */ 4475 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 4476 4477 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ 4478 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 4479 4480 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ 4481 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 4482 /* Identifies the port assignment for this function. */ 4483 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 4484 4485 4486 /***********************************/ 4487 /* MC_CMD_SET_PORT_ASSIGNMENT 4488 * Set port assignment for current PCI function. 4489 */ 4490 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 4491 4492 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 4493 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 4494 /* Identifies the port assignment for this function. */ 4495 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 4496 4497 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 4498 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 4499 4500 4501 /***********************************/ 4502 /* MC_CMD_ALLOC_VIS 4503 * Allocate VIs for current PCI function. 4504 */ 4505 #define MC_CMD_ALLOC_VIS 0x8b 4506 4507 /* MC_CMD_ALLOC_VIS_IN msgrequest */ 4508 #define MC_CMD_ALLOC_VIS_IN_LEN 8 4509 /* The minimum number of VIs that is acceptable */ 4510 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 4511 /* The maximum number of VIs that would be useful */ 4512 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 4513 4514 /* MC_CMD_ALLOC_VIS_OUT msgresponse */ 4515 #define MC_CMD_ALLOC_VIS_OUT_LEN 8 4516 /* The number of VIs allocated on this function */ 4517 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 4518 /* The base absolute VI number allocated to this function. Required to 4519 * correctly interpret wakeup events. 4520 */ 4521 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 4522 4523 4524 /***********************************/ 4525 /* MC_CMD_FREE_VIS 4526 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, 4527 * but not freed. 4528 */ 4529 #define MC_CMD_FREE_VIS 0x8c 4530 4531 /* MC_CMD_FREE_VIS_IN msgrequest */ 4532 #define MC_CMD_FREE_VIS_IN_LEN 0 4533 4534 /* MC_CMD_FREE_VIS_OUT msgresponse */ 4535 #define MC_CMD_FREE_VIS_OUT_LEN 0 4536 4537 4538 /***********************************/ 4539 /* MC_CMD_GET_SRIOV_CFG 4540 * Get SRIOV config for this PF. 4541 */ 4542 #define MC_CMD_GET_SRIOV_CFG 0xba 4543 4544 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ 4545 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 4546 4547 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ 4548 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 4549 /* Number of VFs currently enabled. */ 4550 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 4551 /* Max number of VFs before sriov stride and offset may need to be changed. */ 4552 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 4553 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 4554 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 4555 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 4556 /* RID offset of first VF from PF. */ 4557 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 4558 /* RID offset of each subsequent VF from the previous. */ 4559 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 4560 4561 4562 /***********************************/ 4563 /* MC_CMD_SET_SRIOV_CFG 4564 * Set SRIOV config for this PF. 4565 */ 4566 #define MC_CMD_SET_SRIOV_CFG 0xbb 4567 4568 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 4569 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 4570 /* Number of VFs currently enabled. */ 4571 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 4572 /* Max number of VFs before sriov stride and offset may need to be changed. */ 4573 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 4574 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 4575 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 4576 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 4577 /* RID offset of first VF from PF, or 0 for no change, or 4578 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. 4579 */ 4580 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 4581 /* RID offset of each subsequent VF from the previous, 0 for no change, or 4582 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. 4583 */ 4584 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 4585 4586 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 4587 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 4588 4589 4590 /***********************************/ 4591 /* MC_CMD_GET_VI_ALLOC_INFO 4592 * Get information about number of VI's and base VI number allocated to this 4593 * function. 4594 */ 4595 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d 4596 4597 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ 4598 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 4599 4600 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ 4601 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 8 4602 /* The number of VIs allocated on this function */ 4603 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 4604 /* The base absolute VI number allocated to this function. Required to 4605 * correctly interpret wakeup events. 4606 */ 4607 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 4608 4609 4610 /***********************************/ 4611 /* MC_CMD_DUMP_VI_STATE 4612 * For CmdClient use. Dump pertinent information on a specific absolute VI. 4613 */ 4614 #define MC_CMD_DUMP_VI_STATE 0x8e 4615 4616 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ 4617 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 4618 /* The VI number to query. */ 4619 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 4620 4621 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ 4622 #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 4623 /* The PF part of the function owning this VI. */ 4624 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 4625 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 4626 /* The VF part of the function owning this VI. */ 4627 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 4628 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 4629 /* Base of VIs allocated to this function. */ 4630 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 4631 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 4632 /* Count of VIs allocated to the owner function. */ 4633 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 4634 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 4635 /* Base interrupt vector allocated to this function. */ 4636 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 4637 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 4638 /* Number of interrupt vectors allocated to this function. */ 4639 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 4640 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 4641 /* Raw evq ptr table data. */ 4642 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 4643 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 4644 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 4645 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 4646 /* Raw evq timer table data. */ 4647 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 4648 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 4649 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 4650 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 4651 /* Combined metadata field. */ 4652 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 4653 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 4654 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 4655 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 4656 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 4657 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 4658 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 4659 /* TXDPCPU raw table data for queue. */ 4660 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 4661 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 4662 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 4663 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 4664 /* TXDPCPU raw table data for queue. */ 4665 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 4666 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 4667 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 4668 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 4669 /* TXDPCPU raw table data for queue. */ 4670 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 4671 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 4672 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 4673 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 4674 /* Combined metadata field. */ 4675 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 4676 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 4677 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 4678 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 4679 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 4680 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 4681 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 4682 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 4683 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 4684 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 4685 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 4686 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 4687 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 4688 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 4689 /* RXDPCPU raw table data for queue. */ 4690 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 4691 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 4692 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 4693 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 4694 /* RXDPCPU raw table data for queue. */ 4695 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 4696 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 4697 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 4698 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 4699 /* Reserved, currently 0. */ 4700 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 4701 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 4702 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 4703 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 4704 /* Combined metadata field. */ 4705 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 4706 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 4707 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 4708 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 4709 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 4710 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 4711 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 4712 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 4713 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 4714 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 4715 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 4716 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 4717 4718 4719 /***********************************/ 4720 /* MC_CMD_ALLOC_PIOBUF 4721 * Allocate a push I/O buffer for later use with a tx queue. 4722 */ 4723 #define MC_CMD_ALLOC_PIOBUF 0x8f 4724 4725 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ 4726 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 4727 4728 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ 4729 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 4730 /* Handle for allocated push I/O buffer. */ 4731 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 4732 4733 4734 /***********************************/ 4735 /* MC_CMD_FREE_PIOBUF 4736 * Free a push I/O buffer. 4737 */ 4738 #define MC_CMD_FREE_PIOBUF 0x90 4739 4740 /* MC_CMD_FREE_PIOBUF_IN msgrequest */ 4741 #define MC_CMD_FREE_PIOBUF_IN_LEN 4 4742 /* Handle for allocated push I/O buffer. */ 4743 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 4744 4745 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ 4746 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 4747 4748 4749 /***********************************/ 4750 /* MC_CMD_GET_VI_TLP_PROCESSING 4751 * Get TLP steering and ordering information for a VI. 4752 */ 4753 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 4754 4755 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ 4756 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 4757 /* VI number to get information for. */ 4758 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 4759 4760 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ 4761 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 4762 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 4763 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 4764 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 4765 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 4766 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 4767 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 4768 /* Use Relaxed ordering model for TLPs on this VI. */ 4769 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 4770 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 4771 /* Use ID based ordering for TLPs on this VI. */ 4772 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 4773 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 4774 /* Set no snoop bit for TLPs on this VI. */ 4775 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 4776 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 4777 /* Enable TPH for TLPs on this VI. */ 4778 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 4779 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 4780 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 4781 4782 4783 /***********************************/ 4784 /* MC_CMD_SET_VI_TLP_PROCESSING 4785 * Set TLP steering and ordering information for a VI. 4786 */ 4787 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 4788 4789 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ 4790 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 4791 /* VI number to set information for. */ 4792 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 4793 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 4794 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 4795 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 4796 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 4797 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 4798 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 4799 /* Use Relaxed ordering model for TLPs on this VI. */ 4800 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 4801 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 4802 /* Use ID based ordering for TLPs on this VI. */ 4803 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 4804 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 4805 /* Set the no snoop bit for TLPs on this VI. */ 4806 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 4807 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 4808 /* Enable TPH for TLPs on this VI. */ 4809 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 4810 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 4811 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 4812 4813 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ 4814 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 4815 4816 4817 /***********************************/ 4818 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS 4819 * Get global PCIe steering and transaction processing configuration. 4820 */ 4821 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc 4822 4823 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 4824 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 4825 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 4826 /* enum: MISC. */ 4827 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 4828 /* enum: IDO. */ 4829 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 4830 /* enum: RO. */ 4831 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 4832 /* enum: TPH Type. */ 4833 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 4834 4835 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 4836 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 4837 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 4838 /* Enum values, see field(s): */ 4839 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 4840 /* Amalgamated TLP info word. */ 4841 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 4842 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 4843 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 4844 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 4845 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 4846 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 4847 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 4848 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 4849 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 4850 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 4851 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 4852 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 4853 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 4854 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 4855 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 4856 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 4857 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 4858 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 4859 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 4860 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 4861 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 4862 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 4863 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 4864 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 4865 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 4866 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 4867 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 4868 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 4869 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 4870 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 4871 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 4872 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 4873 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 4874 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 4875 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 4876 4877 4878 /***********************************/ 4879 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS 4880 * Set global PCIe steering and transaction processing configuration. 4881 */ 4882 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd 4883 4884 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 4885 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 4886 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 4887 /* Enum values, see field(s): */ 4888 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 4889 /* Amalgamated TLP info word. */ 4890 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 4891 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 4892 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 4893 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 4894 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 4895 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 4896 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 4897 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 4898 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 4899 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 4900 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 4901 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 4902 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 4903 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 4904 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 4905 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 4906 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 4907 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 4908 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 4909 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 4910 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 4911 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 4912 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 4913 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 4914 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 4915 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 4916 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 4917 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 4918 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 4919 4920 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 4921 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 4922 4923 4924 /***********************************/ 4925 /* MC_CMD_SATELLITE_DOWNLOAD 4926 * Download a new set of images to the satellite CPUs from the host. 4927 */ 4928 #define MC_CMD_SATELLITE_DOWNLOAD 0x91 4929 4930 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs 4931 * are subtle, and so downloads must proceed in a number of phases. 4932 * 4933 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. 4934 * 4935 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download 4936 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should 4937 * be a checksum (a simple 32-bit sum) of the transferred data. An individual 4938 * download may be aborted using CHUNK_ID_ABORT. 4939 * 4940 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), 4941 * similar to PHASE_IMEMS. 4942 * 4943 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. 4944 * 4945 * After any error (a requested abort is not considered to be an error) the 4946 * sequence must be restarted from PHASE_RESET. 4947 */ 4948 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 4949 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 4950 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) 4951 /* Download phase. (Note: the IDLE phase is used internally and is never valid 4952 * in a command from the host.) 4953 */ 4954 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 4955 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ 4956 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ 4957 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ 4958 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ 4959 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ 4960 /* Target for download. (These match the blob numbers defined in 4961 * mc_flash_layout.h.) 4962 */ 4963 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 4964 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 4965 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 4966 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 4967 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 4968 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 4969 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 4970 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 4971 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 4972 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 4973 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 4974 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 4975 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 4976 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 4977 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 4978 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 4979 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 4980 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 4981 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 4982 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 4983 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 4984 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 4985 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa 4986 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 4987 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb 4988 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 4989 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc 4990 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 4991 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd 4992 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 4993 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe 4994 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 4995 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf 4996 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ 4997 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff 4998 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ 4999 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 5000 /* enum: Last chunk, containing checksum rather than data */ 5001 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff 5002 /* enum: Abort download of this item */ 5003 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe 5004 /* Length of this chunk in bytes */ 5005 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 5006 /* Data for this chunk */ 5007 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 5008 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 5009 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 5010 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 5011 5012 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ 5013 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 5014 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 5015 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 5016 /* Extra status information */ 5017 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 5018 /* enum: Code download OK, completed. */ 5019 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 5020 /* enum: Code download aborted as requested. */ 5021 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 5022 /* enum: Code download OK so far, send next chunk. */ 5023 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 5024 /* enum: Download phases out of sequence */ 5025 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 5026 /* enum: Bad target for this phase */ 5027 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 5028 /* enum: Chunk ID out of sequence */ 5029 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 5030 /* enum: Chunk length zero or too large */ 5031 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 5032 /* enum: Checksum was incorrect */ 5033 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 5034 5035 5036 /***********************************/ 5037 /* MC_CMD_GET_CAPABILITIES 5038 * Get device capabilities. 5039 * 5040 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to 5041 * reference inherent device capabilities as opposed to current NVRAM config. 5042 */ 5043 #define MC_CMD_GET_CAPABILITIES 0xbe 5044 5045 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */ 5046 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0 5047 5048 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ 5049 #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 5050 /* First word of flags. */ 5051 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 5052 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 5053 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 5054 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 5055 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 5056 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 5057 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 5058 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 5059 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 5060 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 5061 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 5062 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 5063 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 5064 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 5065 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 5066 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 5067 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 5068 /* RxDPCPU firmware id. */ 5069 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 5070 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 5071 /* enum: Standard RXDP firmware */ 5072 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 5073 /* enum: Low latency RXDP firmware */ 5074 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 5075 /* enum: RXDP Test firmware image 1 */ 5076 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 5077 /* enum: RXDP Test firmware image 2 */ 5078 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 5079 /* enum: RXDP Test firmware image 3 */ 5080 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 5081 /* enum: RXDP Test firmware image 4 */ 5082 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 5083 /* enum: RXDP Test firmware image 5 */ 5084 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 5085 /* enum: RXDP Test firmware image 6 */ 5086 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 5087 /* enum: RXDP Test firmware image 7 */ 5088 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 5089 /* enum: RXDP Test firmware image 8 */ 5090 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 5091 /* TxDPCPU firmware id. */ 5092 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 5093 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 5094 /* enum: Standard TXDP firmware */ 5095 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 5096 /* enum: Low latency TXDP firmware */ 5097 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 5098 /* enum: TXDP Test firmware image 1 */ 5099 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 5100 /* enum: TXDP Test firmware image 2 */ 5101 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 5102 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 5103 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 5104 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 5105 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 5106 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 5107 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 5108 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 /* enum */ 5109 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 /* enum */ 5110 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 /* enum */ 5111 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 /* enum */ 5112 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 5113 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 5114 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 5115 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 5116 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 5117 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 5118 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 5119 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 /* enum */ 5120 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 /* enum */ 5121 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 /* enum */ 5122 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 /* enum */ 5123 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 5124 /* Hardware capabilities of NIC */ 5125 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 5126 /* Licensed capabilities */ 5127 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 5128 5129 5130 /***********************************/ 5131 /* MC_CMD_V2_EXTN 5132 * Encapsulation for a v2 extended command 5133 */ 5134 #define MC_CMD_V2_EXTN 0x7f 5135 5136 /* MC_CMD_V2_EXTN_IN msgrequest */ 5137 #define MC_CMD_V2_EXTN_IN_LEN 4 5138 /* the extended command number */ 5139 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 5140 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 5141 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 5142 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 5143 /* the actual length of the encapsulated command (which is not in the v1 5144 * header) 5145 */ 5146 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 5147 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 5148 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 5149 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6 5150 5151 5152 /***********************************/ 5153 /* MC_CMD_TCM_BUCKET_ALLOC 5154 * Allocate a pacer bucket (for qau rp or a snapper test) 5155 */ 5156 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 5157 5158 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 5159 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 5160 5161 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 5162 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 5163 /* the bucket id */ 5164 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 5165 5166 5167 /***********************************/ 5168 /* MC_CMD_TCM_BUCKET_FREE 5169 * Free a pacer bucket 5170 */ 5171 #define MC_CMD_TCM_BUCKET_FREE 0xb3 5172 5173 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 5174 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 5175 /* the bucket id */ 5176 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 5177 5178 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 5179 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 5180 5181 5182 /***********************************/ 5183 /* MC_CMD_TCM_BUCKET_INIT 5184 * Initialise pacer bucket with a given rate 5185 */ 5186 #define MC_CMD_TCM_BUCKET_INIT 0xb4 5187 5188 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ 5189 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 5190 /* the bucket id */ 5191 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 5192 /* the rate in mbps */ 5193 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 5194 5195 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ 5196 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 5197 5198 5199 /***********************************/ 5200 /* MC_CMD_TCM_TXQ_INIT 5201 * Initialise txq in pacer with given options or set options 5202 */ 5203 #define MC_CMD_TCM_TXQ_INIT 0xb5 5204 5205 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 5206 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 5207 /* the txq id */ 5208 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 5209 /* the static priority associated with the txq */ 5210 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 5211 /* bitmask of the priority queues this txq is inserted into */ 5212 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 5213 /* the reaction point (RP) bucket */ 5214 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 5215 /* an already reserved bucket (typically set to bucket associated with outer 5216 * vswitch) 5217 */ 5218 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 5219 /* an already reserved bucket (typically set to bucket associated with inner 5220 * vswitch) 5221 */ 5222 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 5223 /* the min bucket (typically for ETS/minimum bandwidth) */ 5224 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 5225 5226 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 5227 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 5228 5229 5230 /***********************************/ 5231 /* MC_CMD_LINK_PIOBUF 5232 * Link a push I/O buffer to a TxQ 5233 */ 5234 #define MC_CMD_LINK_PIOBUF 0x92 5235 5236 /* MC_CMD_LINK_PIOBUF_IN msgrequest */ 5237 #define MC_CMD_LINK_PIOBUF_IN_LEN 8 5238 /* Handle for allocated push I/O buffer. */ 5239 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 5240 /* Function Local Instance (VI) number. */ 5241 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 5242 5243 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ 5244 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 5245 5246 5247 /***********************************/ 5248 /* MC_CMD_UNLINK_PIOBUF 5249 * Unlink a push I/O buffer from a TxQ 5250 */ 5251 #define MC_CMD_UNLINK_PIOBUF 0x93 5252 5253 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ 5254 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 5255 /* Function Local Instance (VI) number. */ 5256 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 5257 5258 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ 5259 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 5260 5261 5262 /***********************************/ 5263 /* MC_CMD_VSWITCH_ALLOC 5264 * allocate and initialise a v-switch. 5265 */ 5266 #define MC_CMD_VSWITCH_ALLOC 0x94 5267 5268 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ 5269 #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 5270 /* The port to connect to the v-switch's upstream port. */ 5271 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 5272 /* The type of v-switch to create. */ 5273 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 5274 /* enum: VLAN */ 5275 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 5276 /* enum: VEB */ 5277 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 5278 /* enum: VEPA */ 5279 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 5280 /* Flags controlling v-port creation */ 5281 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 5282 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 5283 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 5284 /* The number of VLAN tags to support. */ 5285 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 5286 5287 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ 5288 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 5289 5290 5291 /***********************************/ 5292 /* MC_CMD_VSWITCH_FREE 5293 * de-allocate a v-switch. 5294 */ 5295 #define MC_CMD_VSWITCH_FREE 0x95 5296 5297 /* MC_CMD_VSWITCH_FREE_IN msgrequest */ 5298 #define MC_CMD_VSWITCH_FREE_IN_LEN 4 5299 /* The port to which the v-switch is connected. */ 5300 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 5301 5302 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ 5303 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 5304 5305 5306 /***********************************/ 5307 /* MC_CMD_VPORT_ALLOC 5308 * allocate a v-port. 5309 */ 5310 #define MC_CMD_VPORT_ALLOC 0x96 5311 5312 /* MC_CMD_VPORT_ALLOC_IN msgrequest */ 5313 #define MC_CMD_VPORT_ALLOC_IN_LEN 20 5314 /* The port to which the v-switch is connected. */ 5315 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 5316 /* The type of the new v-port. */ 5317 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 5318 /* enum: VLAN (obsolete) */ 5319 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 5320 /* enum: VEB (obsolete) */ 5321 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 5322 /* enum: VEPA (obsolete) */ 5323 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 5324 /* enum: A normal v-port receives packets which match a specified MAC and/or 5325 * VLAN. 5326 */ 5327 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 5328 /* enum: An expansion v-port packets traffic which don't match any other 5329 * v-port. 5330 */ 5331 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 5332 /* enum: An test v-port receives packets which match any filters installed by 5333 * its downstream components. 5334 */ 5335 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 5336 /* Flags controlling v-port creation */ 5337 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 5338 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 5339 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 5340 /* The number of VLAN tags to insert/remove. */ 5341 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 5342 /* The actual VLAN tags to insert/remove */ 5343 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 5344 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 5345 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 5346 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 5347 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 5348 5349 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */ 5350 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4 5351 /* The handle of the new v-port */ 5352 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 5353 5354 5355 /***********************************/ 5356 /* MC_CMD_VPORT_FREE 5357 * de-allocate a v-port. 5358 */ 5359 #define MC_CMD_VPORT_FREE 0x97 5360 5361 /* MC_CMD_VPORT_FREE_IN msgrequest */ 5362 #define MC_CMD_VPORT_FREE_IN_LEN 4 5363 /* The handle of the v-port */ 5364 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 5365 5366 /* MC_CMD_VPORT_FREE_OUT msgresponse */ 5367 #define MC_CMD_VPORT_FREE_OUT_LEN 0 5368 5369 5370 /***********************************/ 5371 /* MC_CMD_VADAPTOR_ALLOC 5372 * allocate a v-adaptor. 5373 */ 5374 #define MC_CMD_VADAPTOR_ALLOC 0x98 5375 5376 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ 5377 #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 16 5378 /* The port to connect to the v-adaptor's port. */ 5379 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 5380 /* Flags controlling v-adaptor creation */ 5381 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 5382 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 5383 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 5384 /* The number of VLAN tags to strip on receive */ 5385 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 5386 5387 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ 5388 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 5389 5390 5391 /***********************************/ 5392 /* MC_CMD_VADAPTOR_FREE 5393 * de-allocate a v-adaptor. 5394 */ 5395 #define MC_CMD_VADAPTOR_FREE 0x99 5396 5397 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */ 5398 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4 5399 /* The port to which the v-adaptor is connected. */ 5400 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 5401 5402 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ 5403 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 5404 5405 5406 /***********************************/ 5407 /* MC_CMD_EVB_PORT_ASSIGN 5408 * assign a port to a PCI function. 5409 */ 5410 #define MC_CMD_EVB_PORT_ASSIGN 0x9a 5411 5412 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ 5413 #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 5414 /* The port to assign. */ 5415 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 5416 /* The target function to modify. */ 5417 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 5418 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 5419 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 5420 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 5421 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 5422 5423 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ 5424 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 5425 5426 5427 /***********************************/ 5428 /* MC_CMD_RDWR_A64_REGIONS 5429 * Assign the 64 bit region addresses. 5430 */ 5431 #define MC_CMD_RDWR_A64_REGIONS 0x9b 5432 5433 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ 5434 #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 5435 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 5436 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 5437 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 5438 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 5439 /* Write enable bits 0-3, set to write, clear to read. */ 5440 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 5441 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 5442 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 5443 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 5444 5445 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included 5446 * regardless of state of write bits in the request. 5447 */ 5448 #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 5449 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 5450 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 5451 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 5452 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 5453 5454 5455 /***********************************/ 5456 /* MC_CMD_ONLOAD_STACK_ALLOC 5457 * Allocate an Onload stack ID. 5458 */ 5459 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c 5460 5461 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ 5462 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 5463 /* The handle of the owning upstream port */ 5464 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 5465 5466 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ 5467 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 5468 /* The handle of the new Onload stack */ 5469 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 5470 5471 5472 /***********************************/ 5473 /* MC_CMD_ONLOAD_STACK_FREE 5474 * Free an Onload stack ID. 5475 */ 5476 #define MC_CMD_ONLOAD_STACK_FREE 0x9d 5477 5478 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ 5479 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 5480 /* The handle of the Onload stack */ 5481 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 5482 5483 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ 5484 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 5485 5486 5487 /***********************************/ 5488 /* MC_CMD_RSS_CONTEXT_ALLOC 5489 * Allocate an RSS context. 5490 */ 5491 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e 5492 5493 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ 5494 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 5495 /* The handle of the owning upstream port */ 5496 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 5497 /* The type of context to allocate */ 5498 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 5499 /* enum: Allocate a context for exclusive use. The key and indirection table 5500 * must be explicitly configured. 5501 */ 5502 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 5503 /* enum: Allocate a context for shared use; this will spread across a range of 5504 * queues, but the key and indirection table are pre-configured and may not be 5505 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. 5506 */ 5507 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 5508 /* Number of queues spanned by this context, in the range 1-64; valid offsets 5509 * in the indirection table will be in the range 0 to NUM_QUEUES-1. 5510 */ 5511 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 5512 5513 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ 5514 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 5515 /* The handle of the new RSS context */ 5516 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 5517 5518 5519 /***********************************/ 5520 /* MC_CMD_RSS_CONTEXT_FREE 5521 * Free an RSS context. 5522 */ 5523 #define MC_CMD_RSS_CONTEXT_FREE 0x9f 5524 5525 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ 5526 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 5527 /* The handle of the RSS context */ 5528 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 5529 5530 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ 5531 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 5532 5533 5534 /***********************************/ 5535 /* MC_CMD_RSS_CONTEXT_SET_KEY 5536 * Set the Toeplitz hash key for an RSS context. 5537 */ 5538 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 5539 5540 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ 5541 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 5542 /* The handle of the RSS context */ 5543 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 5544 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 5545 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 5546 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 5547 5548 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ 5549 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 5550 5551 5552 /***********************************/ 5553 /* MC_CMD_RSS_CONTEXT_GET_KEY 5554 * Get the Toeplitz hash key for an RSS context. 5555 */ 5556 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 5557 5558 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ 5559 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 5560 /* The handle of the RSS context */ 5561 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 5562 5563 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ 5564 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 5565 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 5566 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 5567 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 5568 5569 5570 /***********************************/ 5571 /* MC_CMD_RSS_CONTEXT_SET_TABLE 5572 * Set the indirection table for an RSS context. 5573 */ 5574 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 5575 5576 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ 5577 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 5578 /* The handle of the RSS context */ 5579 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 5580 /* The 128-byte indirection table (1 byte per entry) */ 5581 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 5582 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 5583 5584 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ 5585 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 5586 5587 5588 /***********************************/ 5589 /* MC_CMD_RSS_CONTEXT_GET_TABLE 5590 * Get the indirection table for an RSS context. 5591 */ 5592 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 5593 5594 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ 5595 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 5596 /* The handle of the RSS context */ 5597 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 5598 5599 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ 5600 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 5601 /* The 128-byte indirection table (1 byte per entry) */ 5602 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 5603 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 5604 5605 5606 /***********************************/ 5607 /* MC_CMD_RSS_CONTEXT_SET_FLAGS 5608 * Set various control flags for an RSS context. 5609 */ 5610 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 5611 5612 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ 5613 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 5614 /* The handle of the RSS context */ 5615 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 5616 /* Hash control flags */ 5617 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 5618 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 5619 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 5620 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 5621 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 5622 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 5623 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 5624 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 5625 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 5626 5627 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ 5628 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 5629 5630 5631 /***********************************/ 5632 /* MC_CMD_RSS_CONTEXT_GET_FLAGS 5633 * Get various control flags for an RSS context. 5634 */ 5635 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 5636 5637 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ 5638 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 5639 /* The handle of the RSS context */ 5640 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 5641 5642 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ 5643 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 5644 /* Hash control flags */ 5645 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 5646 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 5647 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 5648 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 5649 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 5650 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 5651 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 5652 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 5653 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 5654 5655 5656 /***********************************/ 5657 /* MC_CMD_DOT1P_MAPPING_ALLOC 5658 * Allocate a .1p mapping. 5659 */ 5660 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 5661 5662 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ 5663 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 5664 /* The handle of the owning upstream port */ 5665 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 5666 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed 5667 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and 5668 * referenced RSS contexts must span no more than this number. 5669 */ 5670 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 5671 5672 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ 5673 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 5674 /* The handle of the new .1p mapping */ 5675 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 5676 5677 5678 /***********************************/ 5679 /* MC_CMD_DOT1P_MAPPING_FREE 5680 * Free a .1p mapping. 5681 */ 5682 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 5683 5684 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ 5685 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 5686 /* The handle of the .1p mapping */ 5687 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 5688 5689 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ 5690 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 5691 5692 5693 /***********************************/ 5694 /* MC_CMD_DOT1P_MAPPING_SET_TABLE 5695 * Set the mapping table for a .1p mapping. 5696 */ 5697 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 5698 5699 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ 5700 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 5701 /* The handle of the .1p mapping */ 5702 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 5703 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 5704 * handle) 5705 */ 5706 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 5707 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 5708 5709 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ 5710 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 5711 5712 5713 /***********************************/ 5714 /* MC_CMD_DOT1P_MAPPING_GET_TABLE 5715 * Get the mapping table for a .1p mapping. 5716 */ 5717 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 5718 5719 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ 5720 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 5721 /* The handle of the .1p mapping */ 5722 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 5723 5724 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ 5725 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 5726 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 5727 * handle) 5728 */ 5729 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 5730 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 5731 5732 5733 /***********************************/ 5734 /* MC_CMD_GET_VECTOR_CFG 5735 * Get Interrupt Vector config for this PF. 5736 */ 5737 #define MC_CMD_GET_VECTOR_CFG 0xbf 5738 5739 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 5740 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 5741 5742 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 5743 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 5744 /* Base absolute interrupt vector number. */ 5745 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 5746 /* Number of interrupt vectors allocate to this PF. */ 5747 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 5748 /* Number of interrupt vectors to allocate per VF. */ 5749 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 5750 5751 5752 /***********************************/ 5753 /* MC_CMD_SET_VECTOR_CFG 5754 * Set Interrupt Vector config for this PF. 5755 */ 5756 #define MC_CMD_SET_VECTOR_CFG 0xc0 5757 5758 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 5759 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 5760 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to 5761 * let the system find a suitable base. 5762 */ 5763 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 5764 /* Number of interrupt vectors allocate to this PF. */ 5765 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 5766 /* Number of interrupt vectors to allocate per VF. */ 5767 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 5768 5769 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 5770 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 5771 5772 5773 /***********************************/ 5774 /* MC_CMD_RMON_RX_CLASS_STATS 5775 * Retrieve rmon rx class statistics 5776 */ 5777 #define MC_CMD_RMON_RX_CLASS_STATS 0xc3 5778 5779 /* MC_CMD_RMON_RX_CLASS_STATS_IN msgrequest */ 5780 #define MC_CMD_RMON_RX_CLASS_STATS_IN_LEN 4 5781 /* flags */ 5782 #define MC_CMD_RMON_RX_CLASS_STATS_IN_FLAGS_OFST 0 5783 #define MC_CMD_RMON_RX_CLASS_STATS_IN_CLASS_LBN 0 5784 #define MC_CMD_RMON_RX_CLASS_STATS_IN_CLASS_WIDTH 8 5785 #define MC_CMD_RMON_RX_CLASS_STATS_IN_RST_LBN 8 5786 #define MC_CMD_RMON_RX_CLASS_STATS_IN_RST_WIDTH 1 5787 5788 /* MC_CMD_RMON_RX_CLASS_STATS_OUT msgresponse */ 5789 #define MC_CMD_RMON_RX_CLASS_STATS_OUT_LENMIN 4 5790 #define MC_CMD_RMON_RX_CLASS_STATS_OUT_LENMAX 252 5791 #define MC_CMD_RMON_RX_CLASS_STATS_OUT_LEN(num) (0+4*(num)) 5792 /* Array of stats */ 5793 #define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_OFST 0 5794 #define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_LEN 4 5795 #define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_MINNUM 1 5796 #define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_MAXNUM 63 5797 5798 5799 /***********************************/ 5800 /* MC_CMD_RMON_TX_CLASS_STATS 5801 * Retrieve rmon tx class statistics 5802 */ 5803 #define MC_CMD_RMON_TX_CLASS_STATS 0xc4 5804 5805 /* MC_CMD_RMON_TX_CLASS_STATS_IN msgrequest */ 5806 #define MC_CMD_RMON_TX_CLASS_STATS_IN_LEN 4 5807 /* flags */ 5808 #define MC_CMD_RMON_TX_CLASS_STATS_IN_FLAGS_OFST 0 5809 #define MC_CMD_RMON_TX_CLASS_STATS_IN_CLASS_LBN 0 5810 #define MC_CMD_RMON_TX_CLASS_STATS_IN_CLASS_WIDTH 8 5811 #define MC_CMD_RMON_TX_CLASS_STATS_IN_RST_LBN 8 5812 #define MC_CMD_RMON_TX_CLASS_STATS_IN_RST_WIDTH 1 5813 5814 /* MC_CMD_RMON_TX_CLASS_STATS_OUT msgresponse */ 5815 #define MC_CMD_RMON_TX_CLASS_STATS_OUT_LENMIN 4 5816 #define MC_CMD_RMON_TX_CLASS_STATS_OUT_LENMAX 252 5817 #define MC_CMD_RMON_TX_CLASS_STATS_OUT_LEN(num) (0+4*(num)) 5818 /* Array of stats */ 5819 #define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_OFST 0 5820 #define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_LEN 4 5821 #define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_MINNUM 1 5822 #define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_MAXNUM 63 5823 5824 5825 /***********************************/ 5826 /* MC_CMD_RMON_RX_SUPER_CLASS_STATS 5827 * Retrieve rmon rx super_class statistics 5828 */ 5829 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS 0xc5 5830 5831 /* MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN msgrequest */ 5832 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_LEN 4 5833 /* flags */ 5834 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_FLAGS_OFST 0 5835 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_SUPER_CLASS_LBN 0 5836 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_SUPER_CLASS_WIDTH 4 5837 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_RST_LBN 4 5838 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_RST_WIDTH 1 5839 5840 /* MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT msgresponse */ 5841 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LENMIN 4 5842 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LENMAX 252 5843 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LEN(num) (0+4*(num)) 5844 /* Array of stats */ 5845 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_OFST 0 5846 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_LEN 4 5847 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_MINNUM 1 5848 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_MAXNUM 63 5849 5850 5851 /***********************************/ 5852 /* MC_CMD_RMON_TX_SUPER_CLASS_STATS 5853 * Retrieve rmon tx super_class statistics 5854 */ 5855 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS 0xc6 5856 5857 /* MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN msgrequest */ 5858 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_LEN 4 5859 /* flags */ 5860 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_FLAGS_OFST 0 5861 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_SUPER_CLASS_LBN 0 5862 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_SUPER_CLASS_WIDTH 4 5863 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_RST_LBN 4 5864 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_RST_WIDTH 1 5865 5866 /* MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT msgresponse */ 5867 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LENMIN 4 5868 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LENMAX 252 5869 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LEN(num) (0+4*(num)) 5870 /* Array of stats */ 5871 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_OFST 0 5872 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_LEN 4 5873 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_MINNUM 1 5874 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_MAXNUM 63 5875 5876 5877 /***********************************/ 5878 /* MC_CMD_RMON_RX_ADD_QID_TO_CLASS 5879 * Add qid to class for statistics collection 5880 */ 5881 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS 0xc7 5882 5883 /* MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN msgrequest */ 5884 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_LEN 12 5885 /* class */ 5886 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_CLASS_OFST 0 5887 /* qid */ 5888 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_QID_OFST 4 5889 /* flags */ 5890 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8 5891 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0 5892 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4 5893 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4 5894 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4 5895 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_MTU_LBN 8 5896 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14 5897 5898 /* MC_CMD_RMON_RX_ADD_QID_TO_CLASS_OUT msgresponse */ 5899 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_OUT_LEN 0 5900 5901 5902 /***********************************/ 5903 /* MC_CMD_RMON_TX_ADD_QID_TO_CLASS 5904 * Add qid to class for statistics collection 5905 */ 5906 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS 0xc8 5907 5908 /* MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN msgrequest */ 5909 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_LEN 12 5910 /* class */ 5911 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_CLASS_OFST 0 5912 /* qid */ 5913 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_QID_OFST 4 5914 /* flags */ 5915 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8 5916 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0 5917 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4 5918 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4 5919 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4 5920 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_MTU_LBN 8 5921 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14 5922 5923 /* MC_CMD_RMON_TX_ADD_QID_TO_CLASS_OUT msgresponse */ 5924 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_OUT_LEN 0 5925 5926 5927 /***********************************/ 5928 /* MC_CMD_RMON_MC_ADD_QID_TO_CLASS 5929 * Add qid to class for statistics collection 5930 */ 5931 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS 0xc9 5932 5933 /* MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN msgrequest */ 5934 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_LEN 12 5935 /* class */ 5936 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_CLASS_OFST 0 5937 /* qid */ 5938 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_QID_OFST 4 5939 /* flags */ 5940 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8 5941 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0 5942 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4 5943 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4 5944 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4 5945 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_MTU_LBN 8 5946 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14 5947 5948 /* MC_CMD_RMON_MC_ADD_QID_TO_CLASS_OUT msgresponse */ 5949 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_OUT_LEN 0 5950 5951 5952 /***********************************/ 5953 /* MC_CMD_RMON_ALLOC_CLASS 5954 * Allocate an rmon class 5955 */ 5956 #define MC_CMD_RMON_ALLOC_CLASS 0xca 5957 5958 /* MC_CMD_RMON_ALLOC_CLASS_IN msgrequest */ 5959 #define MC_CMD_RMON_ALLOC_CLASS_IN_LEN 0 5960 5961 /* MC_CMD_RMON_ALLOC_CLASS_OUT msgresponse */ 5962 #define MC_CMD_RMON_ALLOC_CLASS_OUT_LEN 4 5963 /* class */ 5964 #define MC_CMD_RMON_ALLOC_CLASS_OUT_CLASS_OFST 0 5965 5966 5967 /***********************************/ 5968 /* MC_CMD_RMON_DEALLOC_CLASS 5969 * Deallocate an rmon class 5970 */ 5971 #define MC_CMD_RMON_DEALLOC_CLASS 0xcb 5972 5973 /* MC_CMD_RMON_DEALLOC_CLASS_IN msgrequest */ 5974 #define MC_CMD_RMON_DEALLOC_CLASS_IN_LEN 4 5975 /* class */ 5976 #define MC_CMD_RMON_DEALLOC_CLASS_IN_CLASS_OFST 0 5977 5978 /* MC_CMD_RMON_DEALLOC_CLASS_OUT msgresponse */ 5979 #define MC_CMD_RMON_DEALLOC_CLASS_OUT_LEN 0 5980 5981 5982 /***********************************/ 5983 /* MC_CMD_RMON_ALLOC_SUPER_CLASS 5984 * Allocate an rmon super_class 5985 */ 5986 #define MC_CMD_RMON_ALLOC_SUPER_CLASS 0xcc 5987 5988 /* MC_CMD_RMON_ALLOC_SUPER_CLASS_IN msgrequest */ 5989 #define MC_CMD_RMON_ALLOC_SUPER_CLASS_IN_LEN 0 5990 5991 /* MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT msgresponse */ 5992 #define MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT_LEN 4 5993 /* super_class */ 5994 #define MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT_SUPER_CLASS_OFST 0 5995 5996 5997 /***********************************/ 5998 /* MC_CMD_RMON_DEALLOC_SUPER_CLASS 5999 * Deallocate an rmon tx super_class 6000 */ 6001 #define MC_CMD_RMON_DEALLOC_SUPER_CLASS 0xcd 6002 6003 /* MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN msgrequest */ 6004 #define MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN_LEN 4 6005 /* super_class */ 6006 #define MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN_SUPER_CLASS_OFST 0 6007 6008 /* MC_CMD_RMON_DEALLOC_SUPER_CLASS_OUT msgresponse */ 6009 #define MC_CMD_RMON_DEALLOC_SUPER_CLASS_OUT_LEN 0 6010 6011 6012 /***********************************/ 6013 /* MC_CMD_RMON_RX_UP_CONV_STATS 6014 * Retrieve up converter statistics 6015 */ 6016 #define MC_CMD_RMON_RX_UP_CONV_STATS 0xce 6017 6018 /* MC_CMD_RMON_RX_UP_CONV_STATS_IN msgrequest */ 6019 #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_LEN 4 6020 /* flags */ 6021 #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_FLAGS_OFST 0 6022 #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_PORT_LBN 0 6023 #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_PORT_WIDTH 2 6024 #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_RST_LBN 2 6025 #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_RST_WIDTH 1 6026 6027 /* MC_CMD_RMON_RX_UP_CONV_STATS_OUT msgresponse */ 6028 #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LENMIN 4 6029 #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LENMAX 252 6030 #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LEN(num) (0+4*(num)) 6031 /* Array of stats */ 6032 #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_OFST 0 6033 #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_LEN 4 6034 #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_MINNUM 1 6035 #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_MAXNUM 63 6036 6037 6038 /***********************************/ 6039 /* MC_CMD_RMON_RX_IPI_STATS 6040 * Retrieve rx ipi stats 6041 */ 6042 #define MC_CMD_RMON_RX_IPI_STATS 0xcf 6043 6044 /* MC_CMD_RMON_RX_IPI_STATS_IN msgrequest */ 6045 #define MC_CMD_RMON_RX_IPI_STATS_IN_LEN 4 6046 /* flags */ 6047 #define MC_CMD_RMON_RX_IPI_STATS_IN_FLAGS_OFST 0 6048 #define MC_CMD_RMON_RX_IPI_STATS_IN_VFIFO_LBN 0 6049 #define MC_CMD_RMON_RX_IPI_STATS_IN_VFIFO_WIDTH 5 6050 #define MC_CMD_RMON_RX_IPI_STATS_IN_RST_LBN 5 6051 #define MC_CMD_RMON_RX_IPI_STATS_IN_RST_WIDTH 1 6052 6053 /* MC_CMD_RMON_RX_IPI_STATS_OUT msgresponse */ 6054 #define MC_CMD_RMON_RX_IPI_STATS_OUT_LENMIN 4 6055 #define MC_CMD_RMON_RX_IPI_STATS_OUT_LENMAX 252 6056 #define MC_CMD_RMON_RX_IPI_STATS_OUT_LEN(num) (0+4*(num)) 6057 /* Array of stats */ 6058 #define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_OFST 0 6059 #define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_LEN 4 6060 #define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_MINNUM 1 6061 #define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_MAXNUM 63 6062 6063 6064 /***********************************/ 6065 /* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS 6066 * Retrieve rx ipsec cntxt_ptr indexed stats 6067 */ 6068 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS 0xd0 6069 6070 /* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN msgrequest */ 6071 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_LEN 4 6072 /* flags */ 6073 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_FLAGS_OFST 0 6074 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_LBN 0 6075 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_WIDTH 9 6076 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_RST_LBN 9 6077 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_RST_WIDTH 1 6078 6079 /* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT msgresponse */ 6080 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LENMIN 4 6081 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LENMAX 252 6082 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LEN(num) (0+4*(num)) 6083 /* Array of stats */ 6084 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_OFST 0 6085 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_LEN 4 6086 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MINNUM 1 6087 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MAXNUM 63 6088 6089 6090 /***********************************/ 6091 /* MC_CMD_RMON_RX_IPSEC_PORT_STATS 6092 * Retrieve rx ipsec port indexed stats 6093 */ 6094 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS 0xd1 6095 6096 /* MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN msgrequest */ 6097 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_LEN 4 6098 /* flags */ 6099 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_FLAGS_OFST 0 6100 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_PORT_LBN 0 6101 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_PORT_WIDTH 2 6102 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_RST_LBN 2 6103 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_RST_WIDTH 1 6104 6105 /* MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT msgresponse */ 6106 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LENMIN 4 6107 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LENMAX 252 6108 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LEN(num) (0+4*(num)) 6109 /* Array of stats */ 6110 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_OFST 0 6111 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_LEN 4 6112 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_MINNUM 1 6113 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_MAXNUM 63 6114 6115 6116 /***********************************/ 6117 /* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS 6118 * Retrieve tx ipsec overflow 6119 */ 6120 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS 0xd2 6121 6122 /* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN msgrequest */ 6123 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_LEN 4 6124 /* flags */ 6125 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_FLAGS_OFST 0 6126 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_PORT_LBN 0 6127 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_PORT_WIDTH 2 6128 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_RST_LBN 2 6129 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_RST_WIDTH 1 6130 6131 /* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT msgresponse */ 6132 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LENMIN 4 6133 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LENMAX 252 6134 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LEN(num) (0+4*(num)) 6135 /* Array of stats */ 6136 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_OFST 0 6137 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_LEN 4 6138 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_MINNUM 1 6139 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_MAXNUM 63 6140 6141 6142 /***********************************/ 6143 /* MC_CMD_VPORT_ADD_MAC_ADDRESS 6144 * Add a MAC address to a v-port 6145 */ 6146 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 6147 6148 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ 6149 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 6150 /* The handle of the v-port */ 6151 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 6152 /* MAC address to add */ 6153 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 6154 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 6155 6156 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ 6157 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 6158 6159 6160 /***********************************/ 6161 /* MC_CMD_VPORT_DEL_MAC_ADDRESS 6162 * Delete a MAC address from a v-port 6163 */ 6164 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 6165 6166 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ 6167 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 6168 /* The handle of the v-port */ 6169 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 6170 /* MAC address to add */ 6171 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 6172 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 6173 6174 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ 6175 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 6176 6177 6178 /***********************************/ 6179 /* MC_CMD_VPORT_GET_MAC_ADDRESSES 6180 * Delete a MAC address from a v-port 6181 */ 6182 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa 6183 6184 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ 6185 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 6186 /* The handle of the v-port */ 6187 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 6188 6189 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ 6190 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 6191 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 6192 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) 6193 /* The number of MAC addresses returned */ 6194 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 6195 /* Array of MAC addresses */ 6196 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 6197 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 6198 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 6199 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 6200 6201 6202 /***********************************/ 6203 /* MC_CMD_DUMP_BUFTBL_ENTRIES 6204 * Dump buffer table entries, mainly for command client debug use. Dumps 6205 * absolute entries, and does not use chunk handles. All entries must be in 6206 * range, and used for q page mapping, Although the latter restriction may be 6207 * lifted in future. 6208 */ 6209 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab 6210 6211 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ 6212 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 6213 /* Index of the first buffer table entry. */ 6214 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 6215 /* Number of buffer table entries to dump. */ 6216 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 6217 6218 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ 6219 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 6220 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 6221 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) 6222 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ 6223 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 6224 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 6225 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 6226 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 6227 6228 6229 /***********************************/ 6230 /* MC_CMD_SET_RXDP_CONFIG 6231 * Set global RXDP configuration settings 6232 */ 6233 #define MC_CMD_SET_RXDP_CONFIG 0xc1 6234 6235 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ 6236 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 6237 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 6238 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 6239 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 6240 6241 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ 6242 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 6243 6244 6245 /***********************************/ 6246 /* MC_CMD_GET_RXDP_CONFIG 6247 * Get global RXDP configuration settings 6248 */ 6249 #define MC_CMD_GET_RXDP_CONFIG 0xc2 6250 6251 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ 6252 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 6253 6254 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ 6255 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 6256 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 6257 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 6258 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 6259 6260 6261 /***********************************/ 6262 /* MC_CMD_RMON_RX_CLASS_DROPS_STATS 6263 * Retrieve rx class drop stats 6264 */ 6265 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS 0xd3 6266 6267 /* MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN msgrequest */ 6268 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_LEN 4 6269 /* flags */ 6270 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_FLAGS_OFST 0 6271 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_CLASS_LBN 0 6272 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_CLASS_WIDTH 8 6273 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_RST_LBN 8 6274 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_RST_WIDTH 1 6275 6276 /* MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT msgresponse */ 6277 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LENMIN 4 6278 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LENMAX 252 6279 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LEN(num) (0+4*(num)) 6280 /* Array of stats */ 6281 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_OFST 0 6282 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_LEN 4 6283 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_MINNUM 1 6284 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_MAXNUM 63 6285 6286 6287 /***********************************/ 6288 /* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS 6289 * Retrieve rx super class drop stats 6290 */ 6291 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS 0xd4 6292 6293 /* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN msgrequest */ 6294 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_LEN 4 6295 /* flags */ 6296 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_FLAGS_OFST 0 6297 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_SUPER_CLASS_LBN 0 6298 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_SUPER_CLASS_WIDTH 4 6299 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_RST_LBN 4 6300 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_RST_WIDTH 1 6301 6302 /* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT msgresponse */ 6303 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LENMIN 4 6304 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LENMAX 252 6305 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LEN(num) (0+4*(num)) 6306 /* Array of stats */ 6307 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_OFST 0 6308 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_LEN 4 6309 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_MINNUM 1 6310 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_MAXNUM 63 6311 6312 6313 /***********************************/ 6314 /* MC_CMD_RMON_RX_ERRORS_STATS 6315 * Retrieve rxdp errors 6316 */ 6317 #define MC_CMD_RMON_RX_ERRORS_STATS 0xd5 6318 6319 /* MC_CMD_RMON_RX_ERRORS_STATS_IN msgrequest */ 6320 #define MC_CMD_RMON_RX_ERRORS_STATS_IN_LEN 4 6321 /* flags */ 6322 #define MC_CMD_RMON_RX_ERRORS_STATS_IN_FLAGS_OFST 0 6323 #define MC_CMD_RMON_RX_ERRORS_STATS_IN_QID_LBN 0 6324 #define MC_CMD_RMON_RX_ERRORS_STATS_IN_QID_WIDTH 11 6325 #define MC_CMD_RMON_RX_ERRORS_STATS_IN_RST_LBN 11 6326 #define MC_CMD_RMON_RX_ERRORS_STATS_IN_RST_WIDTH 1 6327 6328 /* MC_CMD_RMON_RX_ERRORS_STATS_OUT msgresponse */ 6329 #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LENMIN 4 6330 #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LENMAX 252 6331 #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LEN(num) (0+4*(num)) 6332 /* Array of stats */ 6333 #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_OFST 0 6334 #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_LEN 4 6335 #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_MINNUM 1 6336 #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_MAXNUM 63 6337 6338 6339 /***********************************/ 6340 /* MC_CMD_RMON_RX_OVERFLOW_STATS 6341 * Retrieve rxdp overflow 6342 */ 6343 #define MC_CMD_RMON_RX_OVERFLOW_STATS 0xd6 6344 6345 /* MC_CMD_RMON_RX_OVERFLOW_STATS_IN msgrequest */ 6346 #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_LEN 4 6347 /* flags */ 6348 #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_FLAGS_OFST 0 6349 #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_CLASS_LBN 0 6350 #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_CLASS_WIDTH 8 6351 #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_RST_LBN 8 6352 #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_RST_WIDTH 1 6353 6354 /* MC_CMD_RMON_RX_OVERFLOW_STATS_OUT msgresponse */ 6355 #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LENMIN 4 6356 #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LENMAX 252 6357 #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LEN(num) (0+4*(num)) 6358 /* Array of stats */ 6359 #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_OFST 0 6360 #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_LEN 4 6361 #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_MINNUM 1 6362 #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_MAXNUM 63 6363 6364 6365 /***********************************/ 6366 /* MC_CMD_RMON_TX_IPI_STATS 6367 * Retrieve tx ipi stats 6368 */ 6369 #define MC_CMD_RMON_TX_IPI_STATS 0xd7 6370 6371 /* MC_CMD_RMON_TX_IPI_STATS_IN msgrequest */ 6372 #define MC_CMD_RMON_TX_IPI_STATS_IN_LEN 4 6373 /* flags */ 6374 #define MC_CMD_RMON_TX_IPI_STATS_IN_FLAGS_OFST 0 6375 #define MC_CMD_RMON_TX_IPI_STATS_IN_VFIFO_LBN 0 6376 #define MC_CMD_RMON_TX_IPI_STATS_IN_VFIFO_WIDTH 5 6377 #define MC_CMD_RMON_TX_IPI_STATS_IN_RST_LBN 5 6378 #define MC_CMD_RMON_TX_IPI_STATS_IN_RST_WIDTH 1 6379 6380 /* MC_CMD_RMON_TX_IPI_STATS_OUT msgresponse */ 6381 #define MC_CMD_RMON_TX_IPI_STATS_OUT_LENMIN 4 6382 #define MC_CMD_RMON_TX_IPI_STATS_OUT_LENMAX 252 6383 #define MC_CMD_RMON_TX_IPI_STATS_OUT_LEN(num) (0+4*(num)) 6384 /* Array of stats */ 6385 #define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_OFST 0 6386 #define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_LEN 4 6387 #define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_MINNUM 1 6388 #define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_MAXNUM 63 6389 6390 6391 /***********************************/ 6392 /* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS 6393 * Retrieve tx ipsec counters by cntxt_ptr 6394 */ 6395 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS 0xd8 6396 6397 /* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN msgrequest */ 6398 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_LEN 4 6399 /* flags */ 6400 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_FLAGS_OFST 0 6401 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_LBN 0 6402 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_WIDTH 9 6403 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_RST_LBN 9 6404 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_RST_WIDTH 1 6405 6406 /* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT msgresponse */ 6407 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LENMIN 4 6408 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LENMAX 252 6409 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LEN(num) (0+4*(num)) 6410 /* Array of stats */ 6411 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_OFST 0 6412 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_LEN 4 6413 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MINNUM 1 6414 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MAXNUM 63 6415 6416 6417 /***********************************/ 6418 /* MC_CMD_RMON_TX_IPSEC_PORT_STATS 6419 * Retrieve tx ipsec counters by port 6420 */ 6421 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS 0xd9 6422 6423 /* MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN msgrequest */ 6424 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_LEN 4 6425 /* flags */ 6426 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_FLAGS_OFST 0 6427 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_PORT_LBN 0 6428 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_PORT_WIDTH 2 6429 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_RST_LBN 2 6430 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_RST_WIDTH 1 6431 6432 /* MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT msgresponse */ 6433 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LENMIN 4 6434 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LENMAX 252 6435 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LEN(num) (0+4*(num)) 6436 /* Array of stats */ 6437 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_OFST 0 6438 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_LEN 4 6439 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_MINNUM 1 6440 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_MAXNUM 63 6441 6442 6443 /***********************************/ 6444 /* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS 6445 * Retrieve tx ipsec overflow 6446 */ 6447 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS 0xda 6448 6449 /* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN msgrequest */ 6450 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_LEN 4 6451 /* flags */ 6452 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_FLAGS_OFST 0 6453 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_PORT_LBN 0 6454 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_PORT_WIDTH 2 6455 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_RST_LBN 2 6456 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_RST_WIDTH 1 6457 6458 /* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT msgresponse */ 6459 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LENMIN 4 6460 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LENMAX 252 6461 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LEN(num) (0+4*(num)) 6462 /* Array of stats */ 6463 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_OFST 0 6464 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_LEN 4 6465 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_MINNUM 1 6466 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_MAXNUM 63 6467 6468 6469 /***********************************/ 6470 /* MC_CMD_RMON_TX_NOWHERE_STATS 6471 * Retrieve tx nowhere stats 6472 */ 6473 #define MC_CMD_RMON_TX_NOWHERE_STATS 0xdb 6474 6475 /* MC_CMD_RMON_TX_NOWHERE_STATS_IN msgrequest */ 6476 #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_LEN 4 6477 /* flags */ 6478 #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_FLAGS_OFST 0 6479 #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_CLASS_LBN 0 6480 #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_CLASS_WIDTH 8 6481 #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_RST_LBN 8 6482 #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_RST_WIDTH 1 6483 6484 /* MC_CMD_RMON_TX_NOWHERE_STATS_OUT msgresponse */ 6485 #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LENMIN 4 6486 #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LENMAX 252 6487 #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LEN(num) (0+4*(num)) 6488 /* Array of stats */ 6489 #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_OFST 0 6490 #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_LEN 4 6491 #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_MINNUM 1 6492 #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_MAXNUM 63 6493 6494 6495 /***********************************/ 6496 /* MC_CMD_RMON_TX_NOWHERE_QBB_STATS 6497 * Retrieve tx nowhere qbb stats 6498 */ 6499 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS 0xdc 6500 6501 /* MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN msgrequest */ 6502 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_LEN 4 6503 /* flags */ 6504 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_FLAGS_OFST 0 6505 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_PRIORITY_LBN 0 6506 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_PRIORITY_WIDTH 3 6507 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_RST_LBN 3 6508 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_RST_WIDTH 1 6509 6510 /* MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT msgresponse */ 6511 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LENMIN 4 6512 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LENMAX 252 6513 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LEN(num) (0+4*(num)) 6514 /* Array of stats */ 6515 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_OFST 0 6516 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_LEN 4 6517 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_MINNUM 1 6518 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_MAXNUM 63 6519 6520 6521 /***********************************/ 6522 /* MC_CMD_RMON_TX_ERRORS_STATS 6523 * Retrieve rxdp errors 6524 */ 6525 #define MC_CMD_RMON_TX_ERRORS_STATS 0xdd 6526 6527 /* MC_CMD_RMON_TX_ERRORS_STATS_IN msgrequest */ 6528 #define MC_CMD_RMON_TX_ERRORS_STATS_IN_LEN 4 6529 /* flags */ 6530 #define MC_CMD_RMON_TX_ERRORS_STATS_IN_FLAGS_OFST 0 6531 #define MC_CMD_RMON_TX_ERRORS_STATS_IN_QID_LBN 0 6532 #define MC_CMD_RMON_TX_ERRORS_STATS_IN_QID_WIDTH 11 6533 #define MC_CMD_RMON_TX_ERRORS_STATS_IN_RST_LBN 11 6534 #define MC_CMD_RMON_TX_ERRORS_STATS_IN_RST_WIDTH 1 6535 6536 /* MC_CMD_RMON_TX_ERRORS_STATS_OUT msgresponse */ 6537 #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LENMIN 4 6538 #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LENMAX 252 6539 #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LEN(num) (0+4*(num)) 6540 /* Array of stats */ 6541 #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_OFST 0 6542 #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_LEN 4 6543 #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_MINNUM 1 6544 #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_MAXNUM 63 6545 6546 6547 /***********************************/ 6548 /* MC_CMD_RMON_TX_OVERFLOW_STATS 6549 * Retrieve rxdp overflow 6550 */ 6551 #define MC_CMD_RMON_TX_OVERFLOW_STATS 0xde 6552 6553 /* MC_CMD_RMON_TX_OVERFLOW_STATS_IN msgrequest */ 6554 #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_LEN 4 6555 /* flags */ 6556 #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_FLAGS_OFST 0 6557 #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_CLASS_LBN 0 6558 #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_CLASS_WIDTH 8 6559 #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_RST_LBN 8 6560 #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_RST_WIDTH 1 6561 6562 /* MC_CMD_RMON_TX_OVERFLOW_STATS_OUT msgresponse */ 6563 #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LENMIN 4 6564 #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LENMAX 252 6565 #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LEN(num) (0+4*(num)) 6566 /* Array of stats */ 6567 #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_OFST 0 6568 #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_LEN 4 6569 #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_MINNUM 1 6570 #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_MAXNUM 63 6571 6572 6573 /***********************************/ 6574 /* MC_CMD_RMON_COLLECT_CLASS_STATS 6575 * Explicitly collect class stats at the specified evb port 6576 */ 6577 #define MC_CMD_RMON_COLLECT_CLASS_STATS 0xdf 6578 6579 /* MC_CMD_RMON_COLLECT_CLASS_STATS_IN msgrequest */ 6580 #define MC_CMD_RMON_COLLECT_CLASS_STATS_IN_LEN 4 6581 /* The port id associated with the vport/pport at which to collect class stats 6582 */ 6583 #define MC_CMD_RMON_COLLECT_CLASS_STATS_IN_PORT_ID_OFST 0 6584 6585 /* MC_CMD_RMON_COLLECT_CLASS_STATS_OUT msgresponse */ 6586 #define MC_CMD_RMON_COLLECT_CLASS_STATS_OUT_LEN 4 6587 /* class */ 6588 #define MC_CMD_RMON_COLLECT_CLASS_STATS_OUT_CLASS_OFST 0 6589 6590 6591 /***********************************/ 6592 /* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS 6593 * Explicitly collect class stats at the specified evb port 6594 */ 6595 #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS 0xe0 6596 6597 /* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN msgrequest */ 6598 #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN_LEN 4 6599 /* The port id associated with the vport/pport at which to collect class stats 6600 */ 6601 #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN_PORT_ID_OFST 0 6602 6603 /* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT msgresponse */ 6604 #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT_LEN 4 6605 /* super_class */ 6606 #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT_SUPER_CLASS_OFST 0 6607 6608 6609 /***********************************/ 6610 /* MC_CMD_GET_CLOCK 6611 * Return the system and PDCPU clock frequencies. 6612 */ 6613 #define MC_CMD_GET_CLOCK 0xac 6614 6615 /* MC_CMD_GET_CLOCK_IN msgrequest */ 6616 #define MC_CMD_GET_CLOCK_IN_LEN 0 6617 6618 /* MC_CMD_GET_CLOCK_OUT msgresponse */ 6619 #define MC_CMD_GET_CLOCK_OUT_LEN 8 6620 /* System frequency, MHz */ 6621 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 6622 /* DPCPU frequency, MHz */ 6623 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 6624 6625 6626 /***********************************/ 6627 /* MC_CMD_SET_CLOCK 6628 * Control the system and DPCPU clock frequencies. Changes are lost reboot. 6629 */ 6630 #define MC_CMD_SET_CLOCK 0xad 6631 6632 /* MC_CMD_SET_CLOCK_IN msgrequest */ 6633 #define MC_CMD_SET_CLOCK_IN_LEN 12 6634 /* Requested system frequency in MHz; 0 leaves unchanged. */ 6635 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 6636 /* Requested inter-core frequency in MHz; 0 leaves unchanged. */ 6637 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 6638 /* Request DPCPU frequency in MHz; 0 leaves unchanged. */ 6639 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 6640 6641 /* MC_CMD_SET_CLOCK_OUT msgresponse */ 6642 #define MC_CMD_SET_CLOCK_OUT_LEN 12 6643 /* Resulting system frequency in MHz */ 6644 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 6645 /* Resulting inter-core frequency in MHz */ 6646 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 6647 /* Resulting DPCPU frequency in MHz */ 6648 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 6649 6650 6651 /***********************************/ 6652 /* MC_CMD_DPCPU_RPC 6653 * Send an arbitrary DPCPU message. 6654 */ 6655 #define MC_CMD_DPCPU_RPC 0xae 6656 6657 /* MC_CMD_DPCPU_RPC_IN msgrequest */ 6658 #define MC_CMD_DPCPU_RPC_IN_LEN 36 6659 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 6660 /* enum: RxDPCPU */ 6661 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x0 6662 /* enum: TxDPCPU0 */ 6663 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 6664 /* enum: TxDPCPU1 */ 6665 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 6666 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be 6667 * initialised to zero 6668 */ 6669 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 6670 #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 6671 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 6672 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 6673 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ 6674 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ 6675 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ 6676 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ 6677 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ 6678 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ 6679 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ 6680 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ 6681 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ 6682 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 6683 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 6684 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 6685 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 6686 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 6687 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 6688 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 6689 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 6690 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 6691 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 6692 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ 6693 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ 6694 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ 6695 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ 6696 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ 6697 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 6698 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 6699 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 6700 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 6701 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 6702 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 6703 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 6704 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 6705 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ 6706 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ 6707 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ 6708 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 6709 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 6710 #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 6711 #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 6712 /* Register data to write. Only valid in write/write-read. */ 6713 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 6714 /* Register address. */ 6715 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 6716 6717 /* MC_CMD_DPCPU_RPC_OUT msgresponse */ 6718 #define MC_CMD_DPCPU_RPC_OUT_LEN 36 6719 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 6720 /* DATA */ 6721 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 6722 #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 6723 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 6724 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 6725 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 6726 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 6727 #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 6728 #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 6729 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 6730 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 6731 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 6732 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 6733 6734 6735 /***********************************/ 6736 /* MC_CMD_TRIGGER_INTERRUPT 6737 * Trigger an interrupt by prodding the BIU. 6738 */ 6739 #define MC_CMD_TRIGGER_INTERRUPT 0xe3 6740 6741 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ 6742 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 6743 /* Interrupt level relative to base for function. */ 6744 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 6745 6746 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ 6747 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 6748 6749 6750 /***********************************/ 6751 /* MC_CMD_DUMP_DO 6752 * Take a dump of the DUT state 6753 */ 6754 #define MC_CMD_DUMP_DO 0xe8 6755 6756 /* MC_CMD_DUMP_DO_IN msgrequest */ 6757 #define MC_CMD_DUMP_DO_IN_LEN 52 6758 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 6759 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 6760 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ 6761 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ 6762 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 6763 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ 6764 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ 6765 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ 6766 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ 6767 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 6768 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 6769 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 6770 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 6771 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 6772 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ 6773 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 6774 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 6775 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ 6776 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 6777 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 6778 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 6779 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ 6780 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ 6781 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 6782 /* Enum values, see field(s): */ 6783 /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 6784 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 6785 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 6786 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 6787 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 6788 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 6789 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 6790 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 6791 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 6792 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 6793 6794 /* MC_CMD_DUMP_DO_OUT msgresponse */ 6795 #define MC_CMD_DUMP_DO_OUT_LEN 4 6796 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 6797 6798 6799 /***********************************/ 6800 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED 6801 * Configure unsolicited dumps 6802 */ 6803 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 6804 6805 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ 6806 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 6807 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 6808 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 6809 /* Enum values, see field(s): */ 6810 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ 6811 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 6812 /* Enum values, see field(s): */ 6813 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 6814 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 6815 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 6816 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 6817 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 6818 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 6819 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 6820 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 6821 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 6822 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 6823 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 6824 /* Enum values, see field(s): */ 6825 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ 6826 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 6827 /* Enum values, see field(s): */ 6828 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 6829 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 6830 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 6831 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 6832 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 6833 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 6834 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 6835 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 6836 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 6837 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 6838 6839 6840 /***********************************/ 6841 /* MC_CMD_SET_PSU 6842 * Adjusts power supply parameters. This is a warranty-voiding operation. 6843 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if 6844 * the parameter is out of range. 6845 */ 6846 #define MC_CMD_SET_PSU 0xea 6847 6848 /* MC_CMD_SET_PSU_IN msgrequest */ 6849 #define MC_CMD_SET_PSU_IN_LEN 12 6850 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 6851 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ 6852 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 6853 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ 6854 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ 6855 /* desired value, eg voltage in mV */ 6856 #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 6857 6858 /* MC_CMD_SET_PSU_OUT msgresponse */ 6859 #define MC_CMD_SET_PSU_OUT_LEN 0 6860 6861 6862 /***********************************/ 6863 /* MC_CMD_GET_FUNCTION_INFO 6864 * Get function information. PF and VF number. 6865 */ 6866 #define MC_CMD_GET_FUNCTION_INFO 0xec 6867 6868 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ 6869 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 6870 6871 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ 6872 #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 6873 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 6874 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 6875 6876 6877 /***********************************/ 6878 /* MC_CMD_ENABLE_OFFLINE_BIST 6879 * Enters offline BIST mode. All queues are torn down, chip enters quiescent 6880 * mode, calling function gets exclusive MCDI ownership. The only way out is 6881 * reboot. 6882 */ 6883 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed 6884 6885 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ 6886 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 6887 6888 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ 6889 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 6890 6891 6892 /***********************************/ 6893 /* MC_CMD_START_KR_EYE_PLOT 6894 * Start KR Serdes Eye diagram plot on a given lane. Lane must have valid 6895 * signal. 6896 */ 6897 #define MC_CMD_START_KR_EYE_PLOT 0xee 6898 6899 /* MC_CMD_START_KR_EYE_PLOT_IN msgrequest */ 6900 #define MC_CMD_START_KR_EYE_PLOT_IN_LEN 4 6901 #define MC_CMD_START_KR_EYE_PLOT_IN_LANE_OFST 0 6902 6903 /* MC_CMD_START_KR_EYE_PLOT_OUT msgresponse */ 6904 #define MC_CMD_START_KR_EYE_PLOT_OUT_LEN 0 6905 6906 6907 /***********************************/ 6908 /* MC_CMD_POLL_KR_EYE_PLOT 6909 * Poll KR Serdes Eye diagram plot. Returns one row of BER data. The caller 6910 * should call this command repeatedly after starting eye plot, until no more 6911 * data is returned. 6912 */ 6913 #define MC_CMD_POLL_KR_EYE_PLOT 0xef 6914 6915 /* MC_CMD_POLL_KR_EYE_PLOT_IN msgrequest */ 6916 #define MC_CMD_POLL_KR_EYE_PLOT_IN_LEN 0 6917 6918 /* MC_CMD_POLL_KR_EYE_PLOT_OUT msgresponse */ 6919 #define MC_CMD_POLL_KR_EYE_PLOT_OUT_LENMIN 0 6920 #define MC_CMD_POLL_KR_EYE_PLOT_OUT_LENMAX 252 6921 #define MC_CMD_POLL_KR_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 6922 #define MC_CMD_POLL_KR_EYE_PLOT_OUT_SAMPLES_OFST 0 6923 #define MC_CMD_POLL_KR_EYE_PLOT_OUT_SAMPLES_LEN 2 6924 #define MC_CMD_POLL_KR_EYE_PLOT_OUT_SAMPLES_MINNUM 0 6925 #define MC_CMD_POLL_KR_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 6926 6927 6928 /***********************************/ 6929 /* MC_CMD_READ_FUSES 6930 * Read data programmed into the device One-Time-Programmable (OTP) Fuses 6931 */ 6932 #define MC_CMD_READ_FUSES 0xf0 6933 6934 /* MC_CMD_READ_FUSES_IN msgrequest */ 6935 #define MC_CMD_READ_FUSES_IN_LEN 8 6936 /* Offset in OTP to read */ 6937 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 6938 /* Length of data to read in bytes */ 6939 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 6940 6941 /* MC_CMD_READ_FUSES_OUT msgresponse */ 6942 #define MC_CMD_READ_FUSES_OUT_LENMIN 4 6943 #define MC_CMD_READ_FUSES_OUT_LENMAX 252 6944 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) 6945 /* Length of returned OTP data in bytes */ 6946 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 6947 /* Returned data */ 6948 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 6949 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 6950 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 6951 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 6952 6953 6954 /***********************************/ 6955 /* MC_CMD_KR_TUNE 6956 * Get or set KR Serdes RXEQ and TX Driver settings 6957 */ 6958 #define MC_CMD_KR_TUNE 0xf1 6959 6960 /* MC_CMD_KR_TUNE_IN msgrequest */ 6961 #define MC_CMD_KR_TUNE_IN_LENMIN 4 6962 #define MC_CMD_KR_TUNE_IN_LENMAX 252 6963 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) 6964 /* Requested operation */ 6965 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 6966 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 6967 /* enum: Get current RXEQ settings */ 6968 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 6969 /* enum: Override RXEQ settings */ 6970 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 6971 /* enum: Get current TX Driver settings */ 6972 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 6973 /* enum: Override TX Driver settings */ 6974 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 6975 /* enum: Force KR Serdes reset / recalibration */ 6976 #define MC_CMD_KR_TUNE_IN_RECAL 0x4 6977 /* Align the arguments to 32 bits */ 6978 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 6979 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 6980 /* Arguments specific to the operation */ 6981 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 6982 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 6983 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 6984 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 6985 6986 /* MC_CMD_KR_TUNE_OUT msgresponse */ 6987 #define MC_CMD_KR_TUNE_OUT_LEN 0 6988 6989 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ 6990 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 6991 /* Requested operation */ 6992 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 6993 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 6994 /* Align the arguments to 32 bits */ 6995 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 6996 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 6997 6998 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ 6999 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 7000 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 7001 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 7002 /* RXEQ Parameter */ 7003 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 7004 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 7005 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 7006 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 7007 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 7008 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 7009 /* enum: Attenuation (0-15) */ 7010 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 7011 /* enum: CTLE Boost (0-15) */ 7012 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 7013 /* enum: Edge DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 7014 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 7015 /* enum: Edge DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 7016 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 7017 /* enum: Edge DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 7018 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 7019 /* enum: Edge DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 7020 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 7021 /* enum: Edge DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 7022 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 7023 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 7024 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 7025 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 7026 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 7027 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 7028 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 7029 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 7030 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 7031 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 7032 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 7033 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 7034 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 7035 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 7036 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 7037 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 7038 7039 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ 7040 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 7041 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 7042 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 7043 /* Requested operation */ 7044 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 7045 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 7046 /* Align the arguments to 32 bits */ 7047 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 7048 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 7049 /* RXEQ Parameter */ 7050 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 7051 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 7052 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 7053 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 7054 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 7055 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 7056 /* Enum values, see field(s): */ 7057 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ 7058 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 7059 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 7060 /* Enum values, see field(s): */ 7061 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 7062 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 7063 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 7064 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 7065 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 7066 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 7067 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 7068 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 7069 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 7070 7071 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ 7072 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 7073 7074 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ 7075 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 7076 /* Requested operation */ 7077 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 7078 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 7079 /* Align the arguments to 32 bits */ 7080 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 7081 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 7082 7083 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ 7084 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 7085 7086 7087 /***********************************/ 7088 /* MC_CMD_PCIE_TUNE 7089 * Get or set PCIE Serdes RXEQ and TX Driver settings 7090 */ 7091 #define MC_CMD_PCIE_TUNE 0xf2 7092 7093 /* MC_CMD_PCIE_TUNE_IN msgrequest */ 7094 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 7095 #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 7096 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) 7097 /* Requested operation */ 7098 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 7099 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 7100 /* enum: Get current RXEQ settings */ 7101 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 7102 /* enum: Override RXEQ settings */ 7103 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 7104 /* enum: Get current TX Driver settings */ 7105 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 7106 /* enum: Override TX Driver settings */ 7107 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 7108 /* Align the arguments to 32 bits */ 7109 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 7110 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 7111 /* Arguments specific to the operation */ 7112 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 7113 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 7114 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 7115 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 7116 7117 /* MC_CMD_PCIE_TUNE_OUT msgresponse */ 7118 #define MC_CMD_PCIE_TUNE_OUT_LEN 0 7119 7120 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ 7121 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 7122 /* Requested operation */ 7123 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 7124 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 7125 /* Align the arguments to 32 bits */ 7126 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 7127 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 7128 7129 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ 7130 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 7131 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 7132 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 7133 /* RXEQ Parameter */ 7134 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 7135 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 7136 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 7137 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 7138 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 7139 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 7140 /* enum: Attenuation (0-15) */ 7141 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 7142 /* enum: CTLE Boost (0-15) */ 7143 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 7144 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 7145 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 7146 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 7147 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 7148 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 7149 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 7150 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 7151 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 7152 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 7153 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 7154 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 7155 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 4 7156 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 7157 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 7158 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 7159 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 7160 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ 7161 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ 7162 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ 7163 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ 7164 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x8 /* enum */ 7165 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 7166 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 12 7167 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 7168 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 7169 7170 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ 7171 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 7172 /* Requested operation */ 7173 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 7174 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 7175 /* Align the arguments to 32 bits */ 7176 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 7177 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 7178 7179 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ 7180 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 7181 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 7182 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 7183 /* RXEQ Parameter */ 7184 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 7185 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 7186 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 7187 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 7188 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 7189 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 7190 /* enum: TxMargin (PIPE) */ 7191 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 7192 /* enum: TxSwing (PIPE) */ 7193 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 7194 /* enum: De-emphasis coefficient C(-1) (PIPE) */ 7195 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 7196 /* enum: De-emphasis coefficient C(0) (PIPE) */ 7197 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 7198 /* enum: De-emphasis coefficient C(+1) (PIPE) */ 7199 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 7200 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 7201 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 7202 /* Enum values, see field(s): */ 7203 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 7204 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 7205 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 7206 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 7207 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 7208 7209 7210 /***********************************/ 7211 /* MC_CMD_LICENSING 7212 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 7213 */ 7214 #define MC_CMD_LICENSING 0xf3 7215 7216 /* MC_CMD_LICENSING_IN msgrequest */ 7217 #define MC_CMD_LICENSING_IN_LEN 4 7218 /* identifies the type of operation requested */ 7219 #define MC_CMD_LICENSING_IN_OP_OFST 0 7220 /* enum: re-read and apply licenses after a license key partition update; note 7221 * that this operation returns a zero-length response 7222 */ 7223 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 7224 /* enum: report counts of installed licenses */ 7225 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 7226 7227 /* MC_CMD_LICENSING_OUT msgresponse */ 7228 #define MC_CMD_LICENSING_OUT_LEN 28 7229 /* count of application keys which are valid */ 7230 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 7231 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with 7232 * MC_CMD_FC_OP_LICENSE) 7233 */ 7234 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 7235 /* count of application keys which are invalid due to being blacklisted */ 7236 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 7237 /* count of application keys which are invalid due to being unverifiable */ 7238 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 7239 /* count of application keys which are invalid due to being for the wrong node 7240 */ 7241 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 7242 /* licensing state (for diagnostics; the exact meaning of the bits in this 7243 * field are private to the firmware) 7244 */ 7245 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 7246 /* licensing subsystem self-test report (for manftest) */ 7247 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 7248 /* enum: licensing subsystem self-test failed */ 7249 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 7250 /* enum: licensing subsystem self-test passed */ 7251 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 7252 7253 7254 /***********************************/ 7255 /* MC_CMD_MC2MC_PROXY 7256 * Execute an arbitrary MCDI command on the slave MC of a dual-core device. 7257 * This will fail on a single-core system. 7258 */ 7259 #define MC_CMD_MC2MC_PROXY 0xf4 7260 7261 7262 #endif /* MCDI_PCOL_H */ 7263