1 /**************************************************************************** 2 * Driver for Solarflare Solarstorm network controllers and boards 3 * Copyright 2009-2011 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 11 #ifndef MCDI_PCOL_H 12 #define MCDI_PCOL_H 13 14 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 15 /* Power-on reset state */ 16 #define MC_FW_STATE_POR (1) 17 /* If this is set in MC_RESET_STATE_REG then it should be 18 * possible to jump into IMEM without loading code from flash. */ 19 #define MC_FW_WARM_BOOT_OK (2) 20 /* The MC main image has started to boot. */ 21 #define MC_FW_STATE_BOOTING (4) 22 /* The Scheduler has started. */ 23 #define MC_FW_STATE_SCHED (8) 24 25 /* Siena MC shared memmory offsets */ 26 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 27 #define MC_SMEM_P0_DOORBELL_OFST 0x000 28 #define MC_SMEM_P1_DOORBELL_OFST 0x004 29 /* The rest of these are firmware-defined */ 30 #define MC_SMEM_P0_PDU_OFST 0x008 31 #define MC_SMEM_P1_PDU_OFST 0x108 32 #define MC_SMEM_PDU_LEN 0x100 33 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 34 #define MC_SMEM_P0_STATUS_OFST 0x7f8 35 #define MC_SMEM_P1_STATUS_OFST 0x7fc 36 37 /* Values to be written to the per-port status dword in shared 38 * memory on reboot and assert */ 39 #define MC_STATUS_DWORD_REBOOT (0xb007b007) 40 #define MC_STATUS_DWORD_ASSERT (0xdeaddead) 41 42 /* The current version of the MCDI protocol. 43 * 44 * Note that the ROM burnt into the card only talks V0, so at the very 45 * least every driver must support version 0 and MCDI_PCOL_VERSION 46 */ 47 #define MCDI_PCOL_VERSION 1 48 49 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 50 51 /* MCDI version 1 52 * 53 * Each MCDI request starts with an MCDI_HEADER, which is a 32byte 54 * structure, filled in by the client. 55 * 56 * 0 7 8 16 20 22 23 24 31 57 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 58 * | | | 59 * | | \--- Response 60 * | \------- Error 61 * \------------------------------ Resync (always set) 62 * 63 * The client writes it's request into MC shared memory, and rings the 64 * doorbell. Each request is completed by either by the MC writting 65 * back into shared memory, or by writting out an event. 66 * 67 * All MCDI commands support completion by shared memory response. Each 68 * request may also contain additional data (accounted for by HEADER.LEN), 69 * and some response's may also contain additional data (again, accounted 70 * for by HEADER.LEN). 71 * 72 * Some MCDI commands support completion by event, in which any associated 73 * response data is included in the event. 74 * 75 * The protocol requires one response to be delivered for every request, a 76 * request should not be sent unless the response for the previous request 77 * has been received (either by polling shared memory, or by receiving 78 * an event). 79 */ 80 81 /** Request/Response structure */ 82 #define MCDI_HEADER_OFST 0 83 #define MCDI_HEADER_CODE_LBN 0 84 #define MCDI_HEADER_CODE_WIDTH 7 85 #define MCDI_HEADER_RESYNC_LBN 7 86 #define MCDI_HEADER_RESYNC_WIDTH 1 87 #define MCDI_HEADER_DATALEN_LBN 8 88 #define MCDI_HEADER_DATALEN_WIDTH 8 89 #define MCDI_HEADER_SEQ_LBN 16 90 #define MCDI_HEADER_RSVD_LBN 20 91 #define MCDI_HEADER_RSVD_WIDTH 2 92 #define MCDI_HEADER_SEQ_WIDTH 4 93 #define MCDI_HEADER_ERROR_LBN 22 94 #define MCDI_HEADER_ERROR_WIDTH 1 95 #define MCDI_HEADER_RESPONSE_LBN 23 96 #define MCDI_HEADER_RESPONSE_WIDTH 1 97 #define MCDI_HEADER_XFLAGS_LBN 24 98 #define MCDI_HEADER_XFLAGS_WIDTH 8 99 /* Request response using event */ 100 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 101 102 /* Maximum number of payload bytes */ 103 #define MCDI_CTL_SDU_LEN_MAX 0xfc 104 105 /* The MC can generate events for two reasons: 106 * - To complete a shared memory request if XFLAGS_EVREQ was set 107 * - As a notification (link state, i2c event), controlled 108 * via MC_CMD_LOG_CTRL 109 * 110 * Both events share a common structure: 111 * 112 * 0 32 33 36 44 52 60 113 * | Data | Cont | Level | Src | Code | Rsvd | 114 * | 115 * \ There is another event pending in this notification 116 * 117 * If Code==CMDDONE, then the fields are further interpreted as: 118 * 119 * - LEVEL==INFO Command succeeded 120 * - LEVEL==ERR Command failed 121 * 122 * 0 8 16 24 32 123 * | Seq | Datalen | Errno | Rsvd | 124 * 125 * These fields are taken directly out of the standard MCDI header, i.e., 126 * LEVEL==ERR, Datalen == 0 => Reboot 127 * 128 * Events can be squirted out of the UART (using LOG_CTRL) without a 129 * MCDI header. An event can be distinguished from a MCDI response by 130 * examining the first byte which is 0xc0. This corresponds to the 131 * non-existent MCDI command MC_CMD_DEBUG_LOG. 132 * 133 * 0 7 8 134 * | command | Resync | = 0xc0 135 * 136 * Since the event is written in big-endian byte order, this works 137 * providing bits 56-63 of the event are 0xc0. 138 * 139 * 56 60 63 140 * | Rsvd | Code | = 0xc0 141 * 142 * Which means for convenience the event code is 0xc for all MC 143 * generated events. 144 */ 145 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 146 147 148 /* Non-existent command target */ 149 #define MC_CMD_ERR_ENOENT 2 150 /* assert() has killed the MC */ 151 #define MC_CMD_ERR_EINTR 4 152 /* Caller does not hold required locks */ 153 #define MC_CMD_ERR_EACCES 13 154 /* Resource is currently unavailable (e.g. lock contention) */ 155 #define MC_CMD_ERR_EBUSY 16 156 /* Invalid argument to target */ 157 #define MC_CMD_ERR_EINVAL 22 158 /* Non-recursive resource is already acquired */ 159 #define MC_CMD_ERR_EDEADLK 35 160 /* Operation not implemented */ 161 #define MC_CMD_ERR_ENOSYS 38 162 /* Operation timed out */ 163 #define MC_CMD_ERR_ETIME 62 164 165 #define MC_CMD_ERR_CODE_OFST 0 166 167 /* We define 8 "escape" commands to allow 168 for command number space extension */ 169 170 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 171 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 172 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 173 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 174 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 175 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 176 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 177 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 178 179 /* Vectors in the boot ROM */ 180 /* Point to the copycode entry point. */ 181 #define MC_BOOTROM_COPYCODE_VEC (0x7f4) 182 /* Points to the recovery mode entry point. */ 183 #define MC_BOOTROM_NOFLASH_VEC (0x7f8) 184 185 /* The command set exported by the boot ROM (MCDI v0) */ 186 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 187 (1 << MC_CMD_READ32) | \ 188 (1 << MC_CMD_WRITE32) | \ 189 (1 << MC_CMD_COPYCODE) | \ 190 (1 << MC_CMD_GET_VERSION), \ 191 0, 0, 0 } 192 193 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 194 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 195 196 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 197 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 198 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 199 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 200 201 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 202 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 203 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 204 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 205 206 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 207 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 208 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 209 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 210 211 212 /* MCDI_EVENT structuredef */ 213 #define MCDI_EVENT_LEN 8 214 #define MCDI_EVENT_CONT_LBN 32 215 #define MCDI_EVENT_CONT_WIDTH 1 216 #define MCDI_EVENT_LEVEL_LBN 33 217 #define MCDI_EVENT_LEVEL_WIDTH 3 218 #define MCDI_EVENT_LEVEL_INFO 0x0 /* enum */ 219 #define MCDI_EVENT_LEVEL_WARN 0x1 /* enum */ 220 #define MCDI_EVENT_LEVEL_ERR 0x2 /* enum */ 221 #define MCDI_EVENT_LEVEL_FATAL 0x3 /* enum */ 222 #define MCDI_EVENT_DATA_OFST 0 223 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 224 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 225 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 226 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 227 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 228 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 229 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 230 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 231 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 232 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 233 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 /* enum */ 234 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 /* enum */ 235 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 /* enum */ 236 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 237 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 238 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 239 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 240 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 241 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 242 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 243 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 244 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 245 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 246 #define MCDI_EVENT_FWALERT_DATA_LBN 8 247 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 248 #define MCDI_EVENT_FWALERT_REASON_LBN 0 249 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 250 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 /* enum */ 251 #define MCDI_EVENT_FLR_VF_LBN 0 252 #define MCDI_EVENT_FLR_VF_WIDTH 8 253 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 254 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 255 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 256 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 257 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 /* enum */ 258 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 /* enum */ 259 #define MCDI_EVENT_TX_ERR_2BIG 0x3 /* enum */ 260 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 261 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 262 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 263 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 264 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 265 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 266 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 /* enum */ 267 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 /* enum */ 268 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 /* enum */ 269 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 /* enum */ 270 #define MCDI_EVENT_DATA_LBN 0 271 #define MCDI_EVENT_DATA_WIDTH 32 272 #define MCDI_EVENT_SRC_LBN 36 273 #define MCDI_EVENT_SRC_WIDTH 8 274 #define MCDI_EVENT_EV_CODE_LBN 60 275 #define MCDI_EVENT_EV_CODE_WIDTH 4 276 #define MCDI_EVENT_CODE_LBN 44 277 #define MCDI_EVENT_CODE_WIDTH 8 278 #define MCDI_EVENT_CODE_BADSSERT 0x1 /* enum */ 279 #define MCDI_EVENT_CODE_PMNOTICE 0x2 /* enum */ 280 #define MCDI_EVENT_CODE_CMDDONE 0x3 /* enum */ 281 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 /* enum */ 282 #define MCDI_EVENT_CODE_SENSOREVT 0x5 /* enum */ 283 #define MCDI_EVENT_CODE_SCHEDERR 0x6 /* enum */ 284 #define MCDI_EVENT_CODE_REBOOT 0x7 /* enum */ 285 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 /* enum */ 286 #define MCDI_EVENT_CODE_FWALERT 0x9 /* enum */ 287 #define MCDI_EVENT_CODE_FLR 0xa /* enum */ 288 #define MCDI_EVENT_CODE_TX_ERR 0xb /* enum */ 289 #define MCDI_EVENT_CODE_TX_FLUSH 0xc /* enum */ 290 #define MCDI_EVENT_CODE_PTP_RX 0xd /* enum */ 291 #define MCDI_EVENT_CODE_PTP_FAULT 0xe /* enum */ 292 #define MCDI_EVENT_CMDDONE_DATA_OFST 0 293 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 294 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 295 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 296 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 297 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 298 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 299 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 300 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 301 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 302 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 303 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 304 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 305 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 306 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 307 #define MCDI_EVENT_PTP_SECONDS_OFST 0 308 #define MCDI_EVENT_PTP_SECONDS_LBN 0 309 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 310 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 311 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 312 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 313 #define MCDI_EVENT_PTP_UUID_OFST 0 314 #define MCDI_EVENT_PTP_UUID_LBN 0 315 #define MCDI_EVENT_PTP_UUID_WIDTH 32 316 317 318 /***********************************/ 319 /* MC_CMD_READ32 320 * Read multiple 32byte words from MC memory. 321 */ 322 #define MC_CMD_READ32 0x1 323 324 /* MC_CMD_READ32_IN msgrequest */ 325 #define MC_CMD_READ32_IN_LEN 8 326 #define MC_CMD_READ32_IN_ADDR_OFST 0 327 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 328 329 /* MC_CMD_READ32_OUT msgresponse */ 330 #define MC_CMD_READ32_OUT_LENMIN 4 331 #define MC_CMD_READ32_OUT_LENMAX 252 332 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 333 #define MC_CMD_READ32_OUT_BUFFER_OFST 0 334 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 335 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 336 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 337 338 339 /***********************************/ 340 /* MC_CMD_WRITE32 341 * Write multiple 32byte words to MC memory. 342 */ 343 #define MC_CMD_WRITE32 0x2 344 345 /* MC_CMD_WRITE32_IN msgrequest */ 346 #define MC_CMD_WRITE32_IN_LENMIN 8 347 #define MC_CMD_WRITE32_IN_LENMAX 252 348 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 349 #define MC_CMD_WRITE32_IN_ADDR_OFST 0 350 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 351 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 352 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 353 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 354 355 /* MC_CMD_WRITE32_OUT msgresponse */ 356 #define MC_CMD_WRITE32_OUT_LEN 0 357 358 359 /***********************************/ 360 /* MC_CMD_COPYCODE 361 * Copy MC code between two locations and jump. 362 */ 363 #define MC_CMD_COPYCODE 0x3 364 365 /* MC_CMD_COPYCODE_IN msgrequest */ 366 #define MC_CMD_COPYCODE_IN_LEN 16 367 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 368 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 369 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 370 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 371 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 /* enum */ 372 373 /* MC_CMD_COPYCODE_OUT msgresponse */ 374 #define MC_CMD_COPYCODE_OUT_LEN 0 375 376 377 /***********************************/ 378 /* MC_CMD_SET_FUNC 379 */ 380 #define MC_CMD_SET_FUNC 0x4 381 382 /* MC_CMD_SET_FUNC_IN msgrequest */ 383 #define MC_CMD_SET_FUNC_IN_LEN 4 384 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 385 386 /* MC_CMD_SET_FUNC_OUT msgresponse */ 387 #define MC_CMD_SET_FUNC_OUT_LEN 0 388 389 390 /***********************************/ 391 /* MC_CMD_GET_BOOT_STATUS 392 */ 393 #define MC_CMD_GET_BOOT_STATUS 0x5 394 395 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 396 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 397 398 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 399 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 400 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 401 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 402 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 403 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 404 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 405 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 406 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 407 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 408 409 410 /***********************************/ 411 /* MC_CMD_GET_ASSERTS 412 * Get and clear any assertion status. 413 */ 414 #define MC_CMD_GET_ASSERTS 0x6 415 416 /* MC_CMD_GET_ASSERTS_IN msgrequest */ 417 #define MC_CMD_GET_ASSERTS_IN_LEN 4 418 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 419 420 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ 421 #define MC_CMD_GET_ASSERTS_OUT_LEN 140 422 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 423 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 /* enum */ 424 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 /* enum */ 425 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 /* enum */ 426 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 /* enum */ 427 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 428 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 429 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 430 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 431 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 432 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 433 434 435 /***********************************/ 436 /* MC_CMD_LOG_CTRL 437 * Configure the output stream for various events and messages. 438 */ 439 #define MC_CMD_LOG_CTRL 0x7 440 441 /* MC_CMD_LOG_CTRL_IN msgrequest */ 442 #define MC_CMD_LOG_CTRL_IN_LEN 8 443 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 444 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 /* enum */ 445 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 /* enum */ 446 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 447 448 /* MC_CMD_LOG_CTRL_OUT msgresponse */ 449 #define MC_CMD_LOG_CTRL_OUT_LEN 0 450 451 452 /***********************************/ 453 /* MC_CMD_GET_VERSION 454 * Get version information about the MC firmware. 455 */ 456 #define MC_CMD_GET_VERSION 0x8 457 458 /* MC_CMD_GET_VERSION_IN msgrequest */ 459 #define MC_CMD_GET_VERSION_IN_LEN 0 460 461 /* MC_CMD_GET_VERSION_V0_OUT msgresponse */ 462 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 463 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 464 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff /* enum */ 465 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_BOOTROM 0xb0070000 /* enum */ 466 467 /* MC_CMD_GET_VERSION_OUT msgresponse */ 468 #define MC_CMD_GET_VERSION_OUT_LEN 32 469 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 470 /* Enum values, see field(s): */ 471 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 472 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 473 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 474 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 475 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 476 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 477 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 478 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 479 480 481 /***********************************/ 482 /* MC_CMD_GET_FPGAREG 483 * Read multiple bytes from PTP FPGA. 484 */ 485 #define MC_CMD_GET_FPGAREG 0x9 486 487 /* MC_CMD_GET_FPGAREG_IN msgrequest */ 488 #define MC_CMD_GET_FPGAREG_IN_LEN 8 489 #define MC_CMD_GET_FPGAREG_IN_ADDR_OFST 0 490 #define MC_CMD_GET_FPGAREG_IN_NUMBYTES_OFST 4 491 492 /* MC_CMD_GET_FPGAREG_OUT msgresponse */ 493 #define MC_CMD_GET_FPGAREG_OUT_LENMIN 1 494 #define MC_CMD_GET_FPGAREG_OUT_LENMAX 255 495 #define MC_CMD_GET_FPGAREG_OUT_LEN(num) (0+1*(num)) 496 #define MC_CMD_GET_FPGAREG_OUT_BUFFER_OFST 0 497 #define MC_CMD_GET_FPGAREG_OUT_BUFFER_LEN 1 498 #define MC_CMD_GET_FPGAREG_OUT_BUFFER_MINNUM 1 499 #define MC_CMD_GET_FPGAREG_OUT_BUFFER_MAXNUM 255 500 501 502 /***********************************/ 503 /* MC_CMD_PUT_FPGAREG 504 * Write multiple bytes to PTP FPGA. 505 */ 506 #define MC_CMD_PUT_FPGAREG 0xa 507 508 /* MC_CMD_PUT_FPGAREG_IN msgrequest */ 509 #define MC_CMD_PUT_FPGAREG_IN_LENMIN 5 510 #define MC_CMD_PUT_FPGAREG_IN_LENMAX 255 511 #define MC_CMD_PUT_FPGAREG_IN_LEN(num) (4+1*(num)) 512 #define MC_CMD_PUT_FPGAREG_IN_ADDR_OFST 0 513 #define MC_CMD_PUT_FPGAREG_IN_BUFFER_OFST 4 514 #define MC_CMD_PUT_FPGAREG_IN_BUFFER_LEN 1 515 #define MC_CMD_PUT_FPGAREG_IN_BUFFER_MINNUM 1 516 #define MC_CMD_PUT_FPGAREG_IN_BUFFER_MAXNUM 251 517 518 /* MC_CMD_PUT_FPGAREG_OUT msgresponse */ 519 #define MC_CMD_PUT_FPGAREG_OUT_LEN 0 520 521 522 /***********************************/ 523 /* MC_CMD_PTP 524 * Perform PTP operation 525 */ 526 #define MC_CMD_PTP 0xb 527 528 /* MC_CMD_PTP_IN msgrequest */ 529 #define MC_CMD_PTP_IN_LEN 1 530 #define MC_CMD_PTP_IN_OP_OFST 0 531 #define MC_CMD_PTP_IN_OP_LEN 1 532 #define MC_CMD_PTP_OP_ENABLE 0x1 /* enum */ 533 #define MC_CMD_PTP_OP_DISABLE 0x2 /* enum */ 534 #define MC_CMD_PTP_OP_TRANSMIT 0x3 /* enum */ 535 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 /* enum */ 536 #define MC_CMD_PTP_OP_STATUS 0x5 /* enum */ 537 #define MC_CMD_PTP_OP_ADJUST 0x6 /* enum */ 538 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 /* enum */ 539 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 /* enum */ 540 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 /* enum */ 541 #define MC_CMD_PTP_OP_RESET_STATS 0xa /* enum */ 542 #define MC_CMD_PTP_OP_DEBUG 0xb /* enum */ 543 #define MC_CMD_PTP_OP_MAX 0xc /* enum */ 544 545 /* MC_CMD_PTP_IN_ENABLE msgrequest */ 546 #define MC_CMD_PTP_IN_ENABLE_LEN 16 547 #define MC_CMD_PTP_IN_CMD_OFST 0 548 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 549 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 550 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 551 #define MC_CMD_PTP_MODE_V1 0x0 /* enum */ 552 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 /* enum */ 553 #define MC_CMD_PTP_MODE_V2 0x2 /* enum */ 554 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 /* enum */ 555 556 /* MC_CMD_PTP_IN_DISABLE msgrequest */ 557 #define MC_CMD_PTP_IN_DISABLE_LEN 8 558 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 559 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 560 561 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 562 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 563 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 255 564 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 565 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 566 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 567 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 568 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 569 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 570 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 571 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 243 572 573 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 574 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 575 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 576 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 577 578 /* MC_CMD_PTP_IN_STATUS msgrequest */ 579 #define MC_CMD_PTP_IN_STATUS_LEN 8 580 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 581 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 582 583 /* MC_CMD_PTP_IN_ADJUST msgrequest */ 584 #define MC_CMD_PTP_IN_ADJUST_LEN 24 585 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 586 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 587 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 588 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 589 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 590 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 591 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 /* enum */ 592 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 593 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 594 595 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 596 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 597 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 598 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 599 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 600 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 601 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 602 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 603 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 604 605 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 606 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 607 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 608 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 609 610 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 611 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 612 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 613 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 614 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 615 616 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ 617 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 618 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 619 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 620 621 /* MC_CMD_PTP_IN_DEBUG msgrequest */ 622 #define MC_CMD_PTP_IN_DEBUG_LEN 12 623 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 624 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 625 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 626 627 /* MC_CMD_PTP_OUT msgresponse */ 628 #define MC_CMD_PTP_OUT_LEN 0 629 630 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 631 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 632 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 633 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 634 635 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 636 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 637 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 638 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 639 640 /* MC_CMD_PTP_OUT_STATUS msgresponse */ 641 #define MC_CMD_PTP_OUT_STATUS_LEN 64 642 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 643 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 644 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 645 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 646 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 647 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 648 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 649 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 650 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 651 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 652 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 653 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 654 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 655 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 656 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 657 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 658 659 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 660 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 661 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 662 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 663 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 664 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 665 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 666 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 667 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 668 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 669 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 670 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 671 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 672 673 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 674 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 675 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 676 #define MC_CMD_PTP_MANF_SUCCESS 0x0 /* enum */ 677 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 /* enum */ 678 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 /* enum */ 679 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 /* enum */ 680 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 /* enum */ 681 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 /* enum */ 682 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 /* enum */ 683 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 /* enum */ 684 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 /* enum */ 685 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 /* enum */ 686 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 687 688 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 689 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 690 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 691 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 692 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 693 694 695 /***********************************/ 696 /* MC_CMD_CSR_READ32 697 * Read 32bit words from the indirect memory map. 698 */ 699 #define MC_CMD_CSR_READ32 0xc 700 701 /* MC_CMD_CSR_READ32_IN msgrequest */ 702 #define MC_CMD_CSR_READ32_IN_LEN 12 703 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 704 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 705 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 706 707 /* MC_CMD_CSR_READ32_OUT msgresponse */ 708 #define MC_CMD_CSR_READ32_OUT_LENMIN 4 709 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 710 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 711 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 712 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 713 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 714 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 715 716 717 /***********************************/ 718 /* MC_CMD_CSR_WRITE32 719 * Write 32bit dwords to the indirect memory map. 720 */ 721 #define MC_CMD_CSR_WRITE32 0xd 722 723 /* MC_CMD_CSR_WRITE32_IN msgrequest */ 724 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 725 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 726 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 727 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 728 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 729 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 730 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 731 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 732 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 733 734 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 735 #define MC_CMD_CSR_WRITE32_OUT_LEN 4 736 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 737 738 739 /***********************************/ 740 /* MC_CMD_STACKINFO 741 * Get stack information. 742 */ 743 #define MC_CMD_STACKINFO 0xf 744 745 /* MC_CMD_STACKINFO_IN msgrequest */ 746 #define MC_CMD_STACKINFO_IN_LEN 0 747 748 /* MC_CMD_STACKINFO_OUT msgresponse */ 749 #define MC_CMD_STACKINFO_OUT_LENMIN 12 750 #define MC_CMD_STACKINFO_OUT_LENMAX 252 751 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 752 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 753 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 754 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 755 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 756 757 758 /***********************************/ 759 /* MC_CMD_MDIO_READ 760 * MDIO register read. 761 */ 762 #define MC_CMD_MDIO_READ 0x10 763 764 /* MC_CMD_MDIO_READ_IN msgrequest */ 765 #define MC_CMD_MDIO_READ_IN_LEN 16 766 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 767 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 /* enum */ 768 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 /* enum */ 769 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 770 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 771 #define MC_CMD_MDIO_CLAUSE22 0x20 /* enum */ 772 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 773 774 /* MC_CMD_MDIO_READ_OUT msgresponse */ 775 #define MC_CMD_MDIO_READ_OUT_LEN 8 776 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 777 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 778 #define MC_CMD_MDIO_STATUS_GOOD 0x8 /* enum */ 779 780 781 /***********************************/ 782 /* MC_CMD_MDIO_WRITE 783 * MDIO register write. 784 */ 785 #define MC_CMD_MDIO_WRITE 0x11 786 787 /* MC_CMD_MDIO_WRITE_IN msgrequest */ 788 #define MC_CMD_MDIO_WRITE_IN_LEN 20 789 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 790 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 791 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 792 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 793 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 794 /* MC_CMD_MDIO_CLAUSE22 0x20 */ 795 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 796 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 797 798 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 799 #define MC_CMD_MDIO_WRITE_OUT_LEN 4 800 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 801 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 802 803 804 /***********************************/ 805 /* MC_CMD_DBI_WRITE 806 * Write DBI register(s). 807 */ 808 #define MC_CMD_DBI_WRITE 0x12 809 810 /* MC_CMD_DBI_WRITE_IN msgrequest */ 811 #define MC_CMD_DBI_WRITE_IN_LENMIN 12 812 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 813 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 814 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 815 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 816 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 817 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 818 819 /* MC_CMD_DBI_WRITE_OUT msgresponse */ 820 #define MC_CMD_DBI_WRITE_OUT_LEN 0 821 822 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 823 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 824 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 825 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 826 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 827 #define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST 4 828 #define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_LBN 32 829 #define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_WIDTH 32 830 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 831 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 832 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 833 834 835 /***********************************/ 836 /* MC_CMD_PORT_READ32 837 * Read a 32-bit register from the indirect port register map. 838 */ 839 #define MC_CMD_PORT_READ32 0x14 840 841 /* MC_CMD_PORT_READ32_IN msgrequest */ 842 #define MC_CMD_PORT_READ32_IN_LEN 4 843 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 844 845 /* MC_CMD_PORT_READ32_OUT msgresponse */ 846 #define MC_CMD_PORT_READ32_OUT_LEN 8 847 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 848 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 849 850 851 /***********************************/ 852 /* MC_CMD_PORT_WRITE32 853 * Write a 32-bit register to the indirect port register map. 854 */ 855 #define MC_CMD_PORT_WRITE32 0x15 856 857 /* MC_CMD_PORT_WRITE32_IN msgrequest */ 858 #define MC_CMD_PORT_WRITE32_IN_LEN 8 859 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 860 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 861 862 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 863 #define MC_CMD_PORT_WRITE32_OUT_LEN 4 864 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 865 866 867 /***********************************/ 868 /* MC_CMD_PORT_READ128 869 * Read a 128-bit register from the indirect port register map. 870 */ 871 #define MC_CMD_PORT_READ128 0x16 872 873 /* MC_CMD_PORT_READ128_IN msgrequest */ 874 #define MC_CMD_PORT_READ128_IN_LEN 4 875 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 876 877 /* MC_CMD_PORT_READ128_OUT msgresponse */ 878 #define MC_CMD_PORT_READ128_OUT_LEN 20 879 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 880 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 881 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 882 883 884 /***********************************/ 885 /* MC_CMD_PORT_WRITE128 886 * Write a 128-bit register to the indirect port register map. 887 */ 888 #define MC_CMD_PORT_WRITE128 0x17 889 890 /* MC_CMD_PORT_WRITE128_IN msgrequest */ 891 #define MC_CMD_PORT_WRITE128_IN_LEN 20 892 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 893 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 894 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 895 896 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 897 #define MC_CMD_PORT_WRITE128_OUT_LEN 4 898 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 899 900 901 /***********************************/ 902 /* MC_CMD_GET_BOARD_CFG 903 * Returns the MC firmware configuration structure. 904 */ 905 #define MC_CMD_GET_BOARD_CFG 0x18 906 907 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 908 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 909 910 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 911 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 912 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 913 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 914 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 915 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 916 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 917 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 918 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0x0 /* enum */ 919 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 0x1 /* enum */ 920 #define MC_CMD_CAPABILITIES_TURBO_LBN 0x1 /* enum */ 921 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 0x1 /* enum */ 922 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 0x2 /* enum */ 923 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 0x1 /* enum */ 924 #define MC_CMD_CAPABILITIES_PTP_LBN 0x3 /* enum */ 925 #define MC_CMD_CAPABILITIES_PTP_WIDTH 0x1 /* enum */ 926 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 927 /* Enum values, see field(s): */ 928 /* CAPABILITIES_PORT0 */ 929 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 930 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 931 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 932 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 933 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 934 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 935 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 936 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 937 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 938 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 939 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 940 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 941 942 943 /***********************************/ 944 /* MC_CMD_DBI_READX 945 * Read DBI register(s). 946 */ 947 #define MC_CMD_DBI_READX 0x19 948 949 /* MC_CMD_DBI_READX_IN msgrequest */ 950 #define MC_CMD_DBI_READX_IN_LENMIN 8 951 #define MC_CMD_DBI_READX_IN_LENMAX 248 952 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 953 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 954 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 955 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 956 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 957 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 958 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 959 960 /* MC_CMD_DBI_READX_OUT msgresponse */ 961 #define MC_CMD_DBI_READX_OUT_LENMIN 4 962 #define MC_CMD_DBI_READX_OUT_LENMAX 252 963 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 964 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 965 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 966 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 967 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 968 969 970 /***********************************/ 971 /* MC_CMD_SET_RAND_SEED 972 * Set the 16byte seed for the MC pseudo-random generator. 973 */ 974 #define MC_CMD_SET_RAND_SEED 0x1a 975 976 /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 977 #define MC_CMD_SET_RAND_SEED_IN_LEN 16 978 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 979 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 980 981 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 982 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 983 984 985 /***********************************/ 986 /* MC_CMD_LTSSM_HIST 987 * Retrieve the history of the PCIE LTSSM. 988 */ 989 #define MC_CMD_LTSSM_HIST 0x1b 990 991 /* MC_CMD_LTSSM_HIST_IN msgrequest */ 992 #define MC_CMD_LTSSM_HIST_IN_LEN 0 993 994 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 995 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 996 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 997 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 998 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 999 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 1000 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 1001 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 1002 1003 1004 /***********************************/ 1005 /* MC_CMD_DRV_ATTACH 1006 * Inform MCPU that this port is managed on the host. 1007 */ 1008 #define MC_CMD_DRV_ATTACH 0x1c 1009 1010 /* MC_CMD_DRV_ATTACH_IN msgrequest */ 1011 #define MC_CMD_DRV_ATTACH_IN_LEN 8 1012 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 1013 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 1014 1015 /* MC_CMD_DRV_ATTACH_OUT msgresponse */ 1016 #define MC_CMD_DRV_ATTACH_OUT_LEN 4 1017 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 1018 1019 1020 /***********************************/ 1021 /* MC_CMD_NCSI_PROD 1022 * Trigger an NC-SI event. 1023 */ 1024 #define MC_CMD_NCSI_PROD 0x1d 1025 1026 /* MC_CMD_NCSI_PROD_IN msgrequest */ 1027 #define MC_CMD_NCSI_PROD_IN_LEN 4 1028 #define MC_CMD_NCSI_PROD_IN_EVENTS_OFST 0 1029 #define MC_CMD_NCSI_PROD_LINKCHANGE 0x0 /* enum */ 1030 #define MC_CMD_NCSI_PROD_RESET 0x1 /* enum */ 1031 #define MC_CMD_NCSI_PROD_DRVATTACH 0x2 /* enum */ 1032 #define MC_CMD_NCSI_PROD_IN_LINKCHANGE_LBN 0 1033 #define MC_CMD_NCSI_PROD_IN_LINKCHANGE_WIDTH 1 1034 #define MC_CMD_NCSI_PROD_IN_RESET_LBN 1 1035 #define MC_CMD_NCSI_PROD_IN_RESET_WIDTH 1 1036 #define MC_CMD_NCSI_PROD_IN_DRVATTACH_LBN 2 1037 #define MC_CMD_NCSI_PROD_IN_DRVATTACH_WIDTH 1 1038 1039 /* MC_CMD_NCSI_PROD_OUT msgresponse */ 1040 #define MC_CMD_NCSI_PROD_OUT_LEN 0 1041 1042 1043 /***********************************/ 1044 /* MC_CMD_SHMUART 1045 * Route UART output to circular buffer in shared memory instead. 1046 */ 1047 #define MC_CMD_SHMUART 0x1f 1048 1049 /* MC_CMD_SHMUART_IN msgrequest */ 1050 #define MC_CMD_SHMUART_IN_LEN 4 1051 #define MC_CMD_SHMUART_IN_FLAG_OFST 0 1052 1053 /* MC_CMD_SHMUART_OUT msgresponse */ 1054 #define MC_CMD_SHMUART_OUT_LEN 0 1055 1056 1057 /***********************************/ 1058 /* MC_CMD_ENTITY_RESET 1059 * Generic per-port reset. 1060 */ 1061 #define MC_CMD_ENTITY_RESET 0x20 1062 1063 /* MC_CMD_ENTITY_RESET_IN msgrequest */ 1064 #define MC_CMD_ENTITY_RESET_IN_LEN 4 1065 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 1066 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 1067 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 1068 1069 /* MC_CMD_ENTITY_RESET_OUT msgresponse */ 1070 #define MC_CMD_ENTITY_RESET_OUT_LEN 0 1071 1072 1073 /***********************************/ 1074 /* MC_CMD_PCIE_CREDITS 1075 * Read instantaneous and minimum flow control thresholds. 1076 */ 1077 #define MC_CMD_PCIE_CREDITS 0x21 1078 1079 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 1080 #define MC_CMD_PCIE_CREDITS_IN_LEN 8 1081 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 1082 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 1083 1084 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 1085 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 1086 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 1087 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 1088 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 1089 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 1090 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 1091 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 1092 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 1093 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 1094 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 1095 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 1096 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 1097 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 1098 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 1099 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 1100 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 1101 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 1102 1103 1104 /***********************************/ 1105 /* MC_CMD_RXD_MONITOR 1106 * Get histogram of RX queue fill level. 1107 */ 1108 #define MC_CMD_RXD_MONITOR 0x22 1109 1110 /* MC_CMD_RXD_MONITOR_IN msgrequest */ 1111 #define MC_CMD_RXD_MONITOR_IN_LEN 12 1112 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 1113 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 1114 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 1115 1116 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 1117 #define MC_CMD_RXD_MONITOR_OUT_LEN 80 1118 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 1119 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 1120 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 1121 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 1122 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 1123 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 1124 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 1125 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 1126 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 1127 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 1128 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 1129 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 1130 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 1131 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 1132 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 1133 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 1134 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 1135 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 1136 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 1137 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 1138 1139 1140 /***********************************/ 1141 /* MC_CMD_PUTS 1142 * puts(3) implementation over MCDI 1143 */ 1144 #define MC_CMD_PUTS 0x23 1145 1146 /* MC_CMD_PUTS_IN msgrequest */ 1147 #define MC_CMD_PUTS_IN_LENMIN 13 1148 #define MC_CMD_PUTS_IN_LENMAX 255 1149 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 1150 #define MC_CMD_PUTS_IN_DEST_OFST 0 1151 #define MC_CMD_PUTS_IN_UART_LBN 0 1152 #define MC_CMD_PUTS_IN_UART_WIDTH 1 1153 #define MC_CMD_PUTS_IN_PORT_LBN 1 1154 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 1155 #define MC_CMD_PUTS_IN_DHOST_OFST 4 1156 #define MC_CMD_PUTS_IN_DHOST_LEN 6 1157 #define MC_CMD_PUTS_IN_STRING_OFST 12 1158 #define MC_CMD_PUTS_IN_STRING_LEN 1 1159 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 1160 #define MC_CMD_PUTS_IN_STRING_MAXNUM 243 1161 1162 /* MC_CMD_PUTS_OUT msgresponse */ 1163 #define MC_CMD_PUTS_OUT_LEN 0 1164 1165 1166 /***********************************/ 1167 /* MC_CMD_GET_PHY_CFG 1168 * Report PHY configuration. 1169 */ 1170 #define MC_CMD_GET_PHY_CFG 0x24 1171 1172 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 1173 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 1174 1175 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 1176 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 1177 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 1178 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 1179 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 1180 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 1181 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 1182 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 1183 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 1184 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 1185 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 1186 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 1187 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 1188 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 1189 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 1190 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 1191 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 1192 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 1193 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 1194 #define MC_CMD_PHY_CAP_10HDX_LBN 1 1195 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 1196 #define MC_CMD_PHY_CAP_10FDX_LBN 2 1197 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 1198 #define MC_CMD_PHY_CAP_100HDX_LBN 3 1199 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 1200 #define MC_CMD_PHY_CAP_100FDX_LBN 4 1201 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 1202 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 1203 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 1204 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 1205 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 1206 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 1207 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 1208 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 1209 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 1210 #define MC_CMD_PHY_CAP_ASYM_LBN 9 1211 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 1212 #define MC_CMD_PHY_CAP_AN_LBN 10 1213 #define MC_CMD_PHY_CAP_AN_WIDTH 1 1214 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 1215 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 1216 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 1217 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 1218 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 1219 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 1220 #define MC_CMD_MEDIA_XAUI 0x1 /* enum */ 1221 #define MC_CMD_MEDIA_CX4 0x2 /* enum */ 1222 #define MC_CMD_MEDIA_KX4 0x3 /* enum */ 1223 #define MC_CMD_MEDIA_XFP 0x4 /* enum */ 1224 #define MC_CMD_MEDIA_SFP_PLUS 0x5 /* enum */ 1225 #define MC_CMD_MEDIA_BASE_T 0x6 /* enum */ 1226 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 1227 #define MC_CMD_MMD_CLAUSE22 0x0 /* enum */ 1228 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 1229 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 1230 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 1231 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 1232 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 1233 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 1234 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 1235 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d /* enum */ 1236 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 1237 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 1238 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 1239 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 1240 1241 1242 /***********************************/ 1243 /* MC_CMD_START_BIST 1244 * Start a BIST test on the PHY. 1245 */ 1246 #define MC_CMD_START_BIST 0x25 1247 1248 /* MC_CMD_START_BIST_IN msgrequest */ 1249 #define MC_CMD_START_BIST_IN_LEN 4 1250 #define MC_CMD_START_BIST_IN_TYPE_OFST 0 1251 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 /* enum */ 1252 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 /* enum */ 1253 #define MC_CMD_BPX_SERDES_BIST 0x3 /* enum */ 1254 #define MC_CMD_MC_LOOPBACK_BIST 0x4 /* enum */ 1255 #define MC_CMD_PHY_BIST 0x5 /* enum */ 1256 1257 /* MC_CMD_START_BIST_OUT msgresponse */ 1258 #define MC_CMD_START_BIST_OUT_LEN 0 1259 1260 1261 /***********************************/ 1262 /* MC_CMD_POLL_BIST 1263 * Poll for BIST completion. 1264 */ 1265 #define MC_CMD_POLL_BIST 0x26 1266 1267 /* MC_CMD_POLL_BIST_IN msgrequest */ 1268 #define MC_CMD_POLL_BIST_IN_LEN 0 1269 1270 /* MC_CMD_POLL_BIST_OUT msgresponse */ 1271 #define MC_CMD_POLL_BIST_OUT_LEN 8 1272 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 1273 #define MC_CMD_POLL_BIST_RUNNING 0x1 /* enum */ 1274 #define MC_CMD_POLL_BIST_PASSED 0x2 /* enum */ 1275 #define MC_CMD_POLL_BIST_FAILED 0x3 /* enum */ 1276 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 /* enum */ 1277 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 1278 1279 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 1280 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 1281 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 1282 /* Enum values, see field(s): */ 1283 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 1284 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 1285 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 1286 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 1287 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 1288 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 1289 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 /* enum */ 1290 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 /* enum */ 1291 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 /* enum */ 1292 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 /* enum */ 1293 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 /* enum */ 1294 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 1295 /* Enum values, see field(s): */ 1296 /* CABLE_STATUS_A */ 1297 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 1298 /* Enum values, see field(s): */ 1299 /* CABLE_STATUS_A */ 1300 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 1301 /* Enum values, see field(s): */ 1302 /* CABLE_STATUS_A */ 1303 1304 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 1305 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 1306 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 1307 /* Enum values, see field(s): */ 1308 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 1309 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 1310 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 /* enum */ 1311 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 /* enum */ 1312 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 /* enum */ 1313 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 /* enum */ 1314 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 /* enum */ 1315 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 /* enum */ 1316 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 /* enum */ 1317 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 /* enum */ 1318 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 /* enum */ 1319 1320 1321 /***********************************/ 1322 /* MC_CMD_FLUSH_RX_QUEUES 1323 * Flush receive queue(s). 1324 */ 1325 #define MC_CMD_FLUSH_RX_QUEUES 0x27 1326 1327 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 1328 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 1329 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 1330 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 1331 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 1332 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 1333 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 1334 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 1335 1336 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 1337 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 1338 1339 1340 /***********************************/ 1341 /* MC_CMD_GET_LOOPBACK_MODES 1342 * Get port's loopback modes. 1343 */ 1344 #define MC_CMD_GET_LOOPBACK_MODES 0x28 1345 1346 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 1347 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 1348 1349 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 1350 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 32 1351 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 1352 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 1353 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 1354 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 1355 #define MC_CMD_LOOPBACK_NONE 0x0 /* enum */ 1356 #define MC_CMD_LOOPBACK_DATA 0x1 /* enum */ 1357 #define MC_CMD_LOOPBACK_GMAC 0x2 /* enum */ 1358 #define MC_CMD_LOOPBACK_XGMII 0x3 /* enum */ 1359 #define MC_CMD_LOOPBACK_XGXS 0x4 /* enum */ 1360 #define MC_CMD_LOOPBACK_XAUI 0x5 /* enum */ 1361 #define MC_CMD_LOOPBACK_GMII 0x6 /* enum */ 1362 #define MC_CMD_LOOPBACK_SGMII 0x7 /* enum */ 1363 #define MC_CMD_LOOPBACK_XGBR 0x8 /* enum */ 1364 #define MC_CMD_LOOPBACK_XFI 0x9 /* enum */ 1365 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa /* enum */ 1366 #define MC_CMD_LOOPBACK_GMII_FAR 0xb /* enum */ 1367 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc /* enum */ 1368 #define MC_CMD_LOOPBACK_XFI_FAR 0xd /* enum */ 1369 #define MC_CMD_LOOPBACK_GPHY 0xe /* enum */ 1370 #define MC_CMD_LOOPBACK_PHYXS 0xf /* enum */ 1371 #define MC_CMD_LOOPBACK_PCS 0x10 /* enum */ 1372 #define MC_CMD_LOOPBACK_PMAPMD 0x11 /* enum */ 1373 #define MC_CMD_LOOPBACK_XPORT 0x12 /* enum */ 1374 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 /* enum */ 1375 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 /* enum */ 1376 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 /* enum */ 1377 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 /* enum */ 1378 #define MC_CMD_LOOPBACK_GMII_WS 0x17 /* enum */ 1379 #define MC_CMD_LOOPBACK_XFI_WS 0x18 /* enum */ 1380 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 /* enum */ 1381 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a /* enum */ 1382 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 1383 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 1384 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 1385 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 1386 /* Enum values, see field(s): */ 1387 /* 100M */ 1388 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 1389 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 1390 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 1391 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 1392 /* Enum values, see field(s): */ 1393 /* 100M */ 1394 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 1395 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 1396 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 1397 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 1398 /* Enum values, see field(s): */ 1399 /* 100M */ 1400 1401 1402 /***********************************/ 1403 /* MC_CMD_GET_LINK 1404 * Read the unified MAC/PHY link state. 1405 */ 1406 #define MC_CMD_GET_LINK 0x29 1407 1408 /* MC_CMD_GET_LINK_IN msgrequest */ 1409 #define MC_CMD_GET_LINK_IN_LEN 0 1410 1411 /* MC_CMD_GET_LINK_OUT msgresponse */ 1412 #define MC_CMD_GET_LINK_OUT_LEN 28 1413 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 1414 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 1415 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 1416 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 1417 /* Enum values, see field(s): */ 1418 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 1419 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 1420 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 1421 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 1422 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 1423 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 1424 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 1425 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 1426 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 1427 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 1428 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 1429 #define MC_CMD_FCNTL_OFF 0x0 /* enum */ 1430 #define MC_CMD_FCNTL_RESPOND 0x1 /* enum */ 1431 #define MC_CMD_FCNTL_BIDIR 0x2 /* enum */ 1432 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 1433 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 1434 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 1435 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 1436 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 1437 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 1438 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 1439 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 1440 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 1441 1442 1443 /***********************************/ 1444 /* MC_CMD_SET_LINK 1445 * Write the unified MAC/PHY link configuration. 1446 */ 1447 #define MC_CMD_SET_LINK 0x2a 1448 1449 /* MC_CMD_SET_LINK_IN msgrequest */ 1450 #define MC_CMD_SET_LINK_IN_LEN 16 1451 #define MC_CMD_SET_LINK_IN_CAP_OFST 0 1452 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 1453 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 1454 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 1455 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 1456 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 1457 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 1458 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 1459 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 1460 /* Enum values, see field(s): */ 1461 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 1462 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 1463 1464 /* MC_CMD_SET_LINK_OUT msgresponse */ 1465 #define MC_CMD_SET_LINK_OUT_LEN 0 1466 1467 1468 /***********************************/ 1469 /* MC_CMD_SET_ID_LED 1470 * Set indentification LED state. 1471 */ 1472 #define MC_CMD_SET_ID_LED 0x2b 1473 1474 /* MC_CMD_SET_ID_LED_IN msgrequest */ 1475 #define MC_CMD_SET_ID_LED_IN_LEN 4 1476 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 1477 #define MC_CMD_LED_OFF 0x0 /* enum */ 1478 #define MC_CMD_LED_ON 0x1 /* enum */ 1479 #define MC_CMD_LED_DEFAULT 0x2 /* enum */ 1480 1481 /* MC_CMD_SET_ID_LED_OUT msgresponse */ 1482 #define MC_CMD_SET_ID_LED_OUT_LEN 0 1483 1484 1485 /***********************************/ 1486 /* MC_CMD_SET_MAC 1487 * Set MAC configuration. 1488 */ 1489 #define MC_CMD_SET_MAC 0x2c 1490 1491 /* MC_CMD_SET_MAC_IN msgrequest */ 1492 #define MC_CMD_SET_MAC_IN_LEN 24 1493 #define MC_CMD_SET_MAC_IN_MTU_OFST 0 1494 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 1495 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 1496 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 1497 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 1498 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 1499 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 1500 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 1501 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 1502 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 1503 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 1504 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 1505 /* MC_CMD_FCNTL_OFF 0x0 */ 1506 /* MC_CMD_FCNTL_RESPOND 0x1 */ 1507 /* MC_CMD_FCNTL_BIDIR 0x2 */ 1508 #define MC_CMD_FCNTL_AUTO 0x3 /* enum */ 1509 1510 /* MC_CMD_SET_MAC_OUT msgresponse */ 1511 #define MC_CMD_SET_MAC_OUT_LEN 0 1512 1513 1514 /***********************************/ 1515 /* MC_CMD_PHY_STATS 1516 * Get generic PHY statistics. 1517 */ 1518 #define MC_CMD_PHY_STATS 0x2d 1519 1520 /* MC_CMD_PHY_STATS_IN msgrequest */ 1521 #define MC_CMD_PHY_STATS_IN_LEN 8 1522 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 1523 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 1524 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 1525 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 1526 1527 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 1528 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 1529 1530 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 1531 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 1532 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 1533 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 1534 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 1535 #define MC_CMD_OUI 0x0 /* enum */ 1536 #define MC_CMD_PMA_PMD_LINK_UP 0x1 /* enum */ 1537 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 /* enum */ 1538 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 /* enum */ 1539 #define MC_CMD_PMA_PMD_SIGNAL 0x4 /* enum */ 1540 #define MC_CMD_PMA_PMD_SNR_A 0x5 /* enum */ 1541 #define MC_CMD_PMA_PMD_SNR_B 0x6 /* enum */ 1542 #define MC_CMD_PMA_PMD_SNR_C 0x7 /* enum */ 1543 #define MC_CMD_PMA_PMD_SNR_D 0x8 /* enum */ 1544 #define MC_CMD_PCS_LINK_UP 0x9 /* enum */ 1545 #define MC_CMD_PCS_RX_FAULT 0xa /* enum */ 1546 #define MC_CMD_PCS_TX_FAULT 0xb /* enum */ 1547 #define MC_CMD_PCS_BER 0xc /* enum */ 1548 #define MC_CMD_PCS_BLOCK_ERRORS 0xd /* enum */ 1549 #define MC_CMD_PHYXS_LINK_UP 0xe /* enum */ 1550 #define MC_CMD_PHYXS_RX_FAULT 0xf /* enum */ 1551 #define MC_CMD_PHYXS_TX_FAULT 0x10 /* enum */ 1552 #define MC_CMD_PHYXS_ALIGN 0x11 /* enum */ 1553 #define MC_CMD_PHYXS_SYNC 0x12 /* enum */ 1554 #define MC_CMD_AN_LINK_UP 0x13 /* enum */ 1555 #define MC_CMD_AN_COMPLETE 0x14 /* enum */ 1556 #define MC_CMD_AN_10GBT_STATUS 0x15 /* enum */ 1557 #define MC_CMD_CL22_LINK_UP 0x16 /* enum */ 1558 #define MC_CMD_PHY_NSTATS 0x17 /* enum */ 1559 1560 1561 /***********************************/ 1562 /* MC_CMD_MAC_STATS 1563 * Get generic MAC statistics. 1564 */ 1565 #define MC_CMD_MAC_STATS 0x2e 1566 1567 /* MC_CMD_MAC_STATS_IN msgrequest */ 1568 #define MC_CMD_MAC_STATS_IN_LEN 16 1569 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 1570 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 1571 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 1572 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 1573 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 1574 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 1575 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 1576 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 1577 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 1578 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 1579 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 1580 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 1581 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 1582 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 1583 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 1584 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 1585 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 1586 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 1587 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 1588 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 1589 1590 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 1591 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 1592 1593 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 1594 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 1595 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 1596 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 1597 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 1598 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 1599 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 1600 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 1601 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 1602 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 1603 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 1604 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 1605 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 1606 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 1607 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 1608 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 1609 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 1610 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 1611 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 1612 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 1613 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 1614 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 1615 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 1616 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 1617 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 1618 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 1619 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 1620 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 1621 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 1622 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 1623 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 1624 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 1625 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 1626 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 1627 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 1628 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 1629 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 1630 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 1631 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 1632 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 1633 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 1634 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 1635 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 1636 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 1637 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 1638 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 1639 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 1640 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 1641 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 1642 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 1643 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 1644 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 1645 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 1646 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 1647 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 1648 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 1649 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 1650 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 1651 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 1652 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 1653 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 1654 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 1655 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 1656 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 1657 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 1658 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 1659 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 1660 #define MC_CMD_GMAC_DMABUF_START 0x40 /* enum */ 1661 #define MC_CMD_GMAC_DMABUF_END 0x5f /* enum */ 1662 #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ 1663 #define MC_CMD_MAC_NSTATS 0x61 /* enum */ 1664 1665 1666 /***********************************/ 1667 /* MC_CMD_SRIOV 1668 * to be documented 1669 */ 1670 #define MC_CMD_SRIOV 0x30 1671 1672 /* MC_CMD_SRIOV_IN msgrequest */ 1673 #define MC_CMD_SRIOV_IN_LEN 12 1674 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 1675 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 1676 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 1677 1678 /* MC_CMD_SRIOV_OUT msgresponse */ 1679 #define MC_CMD_SRIOV_OUT_LEN 8 1680 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 1681 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 1682 1683 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 1684 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 1685 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 1686 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 1687 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 1688 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 1689 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 1690 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 1691 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 1692 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 1693 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 1694 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 1695 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 1696 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 1697 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 1698 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 1699 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 1700 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 1701 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 1702 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 1703 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 1704 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 1705 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 1706 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 1707 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 1708 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 1709 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 1710 1711 1712 /***********************************/ 1713 /* MC_CMD_MEMCPY 1714 * Perform memory copy operation. 1715 */ 1716 #define MC_CMD_MEMCPY 0x31 1717 1718 /* MC_CMD_MEMCPY_IN msgrequest */ 1719 #define MC_CMD_MEMCPY_IN_LENMIN 32 1720 #define MC_CMD_MEMCPY_IN_LENMAX 224 1721 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 1722 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 1723 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 1724 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 1725 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 1726 1727 /* MC_CMD_MEMCPY_OUT msgresponse */ 1728 #define MC_CMD_MEMCPY_OUT_LEN 0 1729 1730 1731 /***********************************/ 1732 /* MC_CMD_WOL_FILTER_SET 1733 * Set a WoL filter. 1734 */ 1735 #define MC_CMD_WOL_FILTER_SET 0x32 1736 1737 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 1738 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 1739 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 1740 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 1741 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 1742 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 1743 #define MC_CMD_WOL_TYPE_MAGIC 0x0 /* enum */ 1744 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 /* enum */ 1745 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 /* enum */ 1746 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 /* enum */ 1747 #define MC_CMD_WOL_TYPE_BITMAP 0x5 /* enum */ 1748 #define MC_CMD_WOL_TYPE_LINK 0x6 /* enum */ 1749 #define MC_CMD_WOL_TYPE_MAX 0x7 /* enum */ 1750 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 1751 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 1752 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 1753 1754 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 1755 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 1756 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 1757 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 1758 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 1759 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 1760 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 1761 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 1762 1763 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 1764 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 1765 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 1766 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 1767 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 1768 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 1769 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 1770 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 1771 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 1772 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 1773 1774 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 1775 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 1776 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 1777 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 1778 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 1779 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 1780 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 1781 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 1782 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 1783 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 1784 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 1785 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 1786 1787 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 1788 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 1789 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 1790 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 1791 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 1792 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 1793 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 1794 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 1795 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 1796 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 1797 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 1798 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 1799 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 1800 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 1801 1802 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 1803 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 1804 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 1805 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 1806 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 1807 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 1808 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 1809 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 1810 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 1811 1812 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 1813 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 1814 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 1815 1816 1817 /***********************************/ 1818 /* MC_CMD_WOL_FILTER_REMOVE 1819 * Remove a WoL filter. 1820 */ 1821 #define MC_CMD_WOL_FILTER_REMOVE 0x33 1822 1823 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 1824 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 1825 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 1826 1827 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 1828 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 1829 1830 1831 /***********************************/ 1832 /* MC_CMD_WOL_FILTER_RESET 1833 * Reset (i.e. remove all) WoL filters. 1834 */ 1835 #define MC_CMD_WOL_FILTER_RESET 0x34 1836 1837 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 1838 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 1839 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 1840 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 1841 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 1842 1843 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 1844 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 1845 1846 1847 /***********************************/ 1848 /* MC_CMD_SET_MCAST_HASH 1849 * Set the MCASH hash value. 1850 */ 1851 #define MC_CMD_SET_MCAST_HASH 0x35 1852 1853 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 1854 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 1855 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 1856 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 1857 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 1858 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 1859 1860 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 1861 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 1862 1863 1864 /***********************************/ 1865 /* MC_CMD_NVRAM_TYPES 1866 * Get virtual NVRAM partitions information. 1867 */ 1868 #define MC_CMD_NVRAM_TYPES 0x36 1869 1870 /* MC_CMD_NVRAM_TYPES_IN msgrequest */ 1871 #define MC_CMD_NVRAM_TYPES_IN_LEN 0 1872 1873 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 1874 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 1875 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 1876 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 /* enum */ 1877 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 /* enum */ 1878 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 /* enum */ 1879 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 /* enum */ 1880 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 /* enum */ 1881 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 /* enum */ 1882 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 /* enum */ 1883 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 /* enum */ 1884 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 /* enum */ 1885 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 /* enum */ 1886 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa /* enum */ 1887 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb /* enum */ 1888 #define MC_CMD_NVRAM_TYPE_LOG 0xc /* enum */ 1889 #define MC_CMD_NVRAM_TYPE_FPGA 0xd /* enum */ 1890 1891 1892 /***********************************/ 1893 /* MC_CMD_NVRAM_INFO 1894 * Read info about a virtual NVRAM partition. 1895 */ 1896 #define MC_CMD_NVRAM_INFO 0x37 1897 1898 /* MC_CMD_NVRAM_INFO_IN msgrequest */ 1899 #define MC_CMD_NVRAM_INFO_IN_LEN 4 1900 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 1901 /* Enum values, see field(s): */ 1902 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1903 1904 /* MC_CMD_NVRAM_INFO_OUT msgresponse */ 1905 #define MC_CMD_NVRAM_INFO_OUT_LEN 24 1906 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 1907 /* Enum values, see field(s): */ 1908 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1909 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 1910 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 1911 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 1912 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 1913 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 1914 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 1915 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 1916 1917 1918 /***********************************/ 1919 /* MC_CMD_NVRAM_UPDATE_START 1920 * Start a group of update operations on a virtual NVRAM partition. 1921 */ 1922 #define MC_CMD_NVRAM_UPDATE_START 0x38 1923 1924 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */ 1925 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 1926 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 1927 /* Enum values, see field(s): */ 1928 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1929 1930 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 1931 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 1932 1933 1934 /***********************************/ 1935 /* MC_CMD_NVRAM_READ 1936 * Read data from a virtual NVRAM partition. 1937 */ 1938 #define MC_CMD_NVRAM_READ 0x39 1939 1940 /* MC_CMD_NVRAM_READ_IN msgrequest */ 1941 #define MC_CMD_NVRAM_READ_IN_LEN 12 1942 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 1943 /* Enum values, see field(s): */ 1944 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1945 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 1946 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 1947 1948 /* MC_CMD_NVRAM_READ_OUT msgresponse */ 1949 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 1950 #define MC_CMD_NVRAM_READ_OUT_LENMAX 255 1951 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 1952 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 1953 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 1954 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 1955 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 255 1956 1957 1958 /***********************************/ 1959 /* MC_CMD_NVRAM_WRITE 1960 * Write data to a virtual NVRAM partition. 1961 */ 1962 #define MC_CMD_NVRAM_WRITE 0x3a 1963 1964 /* MC_CMD_NVRAM_WRITE_IN msgrequest */ 1965 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 1966 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 255 1967 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 1968 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 1969 /* Enum values, see field(s): */ 1970 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1971 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 1972 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 1973 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 1974 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 1975 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 1976 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 243 1977 1978 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 1979 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 1980 1981 1982 /***********************************/ 1983 /* MC_CMD_NVRAM_ERASE 1984 * Erase sector(s) from a virtual NVRAM partition. 1985 */ 1986 #define MC_CMD_NVRAM_ERASE 0x3b 1987 1988 /* MC_CMD_NVRAM_ERASE_IN msgrequest */ 1989 #define MC_CMD_NVRAM_ERASE_IN_LEN 12 1990 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 1991 /* Enum values, see field(s): */ 1992 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1993 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 1994 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 1995 1996 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 1997 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 1998 1999 2000 /***********************************/ 2001 /* MC_CMD_NVRAM_UPDATE_FINISH 2002 * Finish a group of update operations on a virtual NVRAM partition. 2003 */ 2004 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 2005 2006 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */ 2007 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 2008 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 2009 /* Enum values, see field(s): */ 2010 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 2011 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 2012 2013 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */ 2014 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 2015 2016 2017 /***********************************/ 2018 /* MC_CMD_REBOOT 2019 * Reboot the MC. 2020 */ 2021 #define MC_CMD_REBOOT 0x3d 2022 2023 /* MC_CMD_REBOOT_IN msgrequest */ 2024 #define MC_CMD_REBOOT_IN_LEN 4 2025 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 2026 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 2027 2028 /* MC_CMD_REBOOT_OUT msgresponse */ 2029 #define MC_CMD_REBOOT_OUT_LEN 0 2030 2031 2032 /***********************************/ 2033 /* MC_CMD_SCHEDINFO 2034 * Request scheduler info. 2035 */ 2036 #define MC_CMD_SCHEDINFO 0x3e 2037 2038 /* MC_CMD_SCHEDINFO_IN msgrequest */ 2039 #define MC_CMD_SCHEDINFO_IN_LEN 0 2040 2041 /* MC_CMD_SCHEDINFO_OUT msgresponse */ 2042 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 2043 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 2044 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 2045 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 2046 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 2047 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 2048 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 2049 2050 2051 /***********************************/ 2052 /* MC_CMD_REBOOT_MODE 2053 */ 2054 #define MC_CMD_REBOOT_MODE 0x3f 2055 2056 /* MC_CMD_REBOOT_MODE_IN msgrequest */ 2057 #define MC_CMD_REBOOT_MODE_IN_LEN 4 2058 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 2059 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 /* enum */ 2060 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 /* enum */ 2061 2062 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 2063 #define MC_CMD_REBOOT_MODE_OUT_LEN 4 2064 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 2065 2066 2067 /***********************************/ 2068 /* MC_CMD_SENSOR_INFO 2069 * Returns information about every available sensor. 2070 */ 2071 #define MC_CMD_SENSOR_INFO 0x41 2072 2073 /* MC_CMD_SENSOR_INFO_IN msgrequest */ 2074 #define MC_CMD_SENSOR_INFO_IN_LEN 0 2075 2076 /* MC_CMD_SENSOR_INFO_OUT msgresponse */ 2077 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 12 2078 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 2079 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 2080 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 2081 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 /* enum */ 2082 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 /* enum */ 2083 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 /* enum */ 2084 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 /* enum */ 2085 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 /* enum */ 2086 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 /* enum */ 2087 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 /* enum */ 2088 #define MC_CMD_SENSOR_IN_1V0 0x7 /* enum */ 2089 #define MC_CMD_SENSOR_IN_1V2 0x8 /* enum */ 2090 #define MC_CMD_SENSOR_IN_1V8 0x9 /* enum */ 2091 #define MC_CMD_SENSOR_IN_2V5 0xa /* enum */ 2092 #define MC_CMD_SENSOR_IN_3V3 0xb /* enum */ 2093 #define MC_CMD_SENSOR_IN_12V0 0xc /* enum */ 2094 #define MC_CMD_SENSOR_IN_1V2A 0xd /* enum */ 2095 #define MC_CMD_SENSOR_IN_VREF 0xe /* enum */ 2096 #define MC_CMD_SENSOR_ENTRY_OFST 4 2097 #define MC_CMD_SENSOR_ENTRY_LEN 8 2098 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 2099 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 2100 #define MC_CMD_SENSOR_ENTRY_MINNUM 1 2101 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 2102 2103 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 2104 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 2105 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 2106 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 2107 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 2108 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 2109 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 2110 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 2111 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 2112 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 2113 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 2114 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 2115 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 2116 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 2117 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 2118 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 2119 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 2120 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 2121 2122 2123 /***********************************/ 2124 /* MC_CMD_READ_SENSORS 2125 * Returns the current reading from each sensor. 2126 */ 2127 #define MC_CMD_READ_SENSORS 0x42 2128 2129 /* MC_CMD_READ_SENSORS_IN msgrequest */ 2130 #define MC_CMD_READ_SENSORS_IN_LEN 8 2131 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 2132 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 2133 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 2134 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 2135 2136 /* MC_CMD_READ_SENSORS_OUT msgresponse */ 2137 #define MC_CMD_READ_SENSORS_OUT_LEN 0 2138 2139 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 2140 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 3 2141 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 2142 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 2143 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 2144 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 2145 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 2146 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 2147 #define MC_CMD_SENSOR_STATE_OK 0x0 /* enum */ 2148 #define MC_CMD_SENSOR_STATE_WARNING 0x1 /* enum */ 2149 #define MC_CMD_SENSOR_STATE_FATAL 0x2 /* enum */ 2150 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 /* enum */ 2151 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 2152 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 2153 2154 2155 /***********************************/ 2156 /* MC_CMD_GET_PHY_STATE 2157 * Report current state of PHY. 2158 */ 2159 #define MC_CMD_GET_PHY_STATE 0x43 2160 2161 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 2162 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 2163 2164 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 2165 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 2166 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 2167 #define MC_CMD_PHY_STATE_OK 0x1 /* enum */ 2168 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 /* enum */ 2169 2170 2171 /***********************************/ 2172 /* MC_CMD_SETUP_8021QBB 2173 * 802.1Qbb control. 2174 */ 2175 #define MC_CMD_SETUP_8021QBB 0x44 2176 2177 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 2178 #define MC_CMD_SETUP_8021QBB_IN_LEN 32 2179 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 2180 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 2181 2182 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 2183 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 2184 2185 2186 /***********************************/ 2187 /* MC_CMD_WOL_FILTER_GET 2188 * Retrieve ID of any WoL filters. 2189 */ 2190 #define MC_CMD_WOL_FILTER_GET 0x45 2191 2192 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 2193 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 2194 2195 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 2196 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 2197 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 2198 2199 2200 /***********************************/ 2201 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 2202 * Add a protocol offload to NIC for lights-out state. 2203 */ 2204 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 2205 2206 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 2207 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 2208 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 2209 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 2210 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 2211 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 2212 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 2213 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 2214 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 2215 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 2216 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 2217 2218 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 2219 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 2220 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 2221 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 2222 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 2223 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 2224 2225 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 2226 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 2227 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 2228 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 2229 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 2230 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 2231 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 2232 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 2233 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 2234 2235 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 2236 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 2237 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 2238 2239 2240 /***********************************/ 2241 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 2242 * Remove a protocol offload from NIC for lights-out state. 2243 */ 2244 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 2245 2246 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 2247 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 2248 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 2249 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 2250 2251 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 2252 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 2253 2254 2255 /***********************************/ 2256 /* MC_CMD_MAC_RESET_RESTORE 2257 * Restore MAC after block reset. 2258 */ 2259 #define MC_CMD_MAC_RESET_RESTORE 0x48 2260 2261 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 2262 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 2263 2264 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 2265 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 2266 2267 2268 /***********************************/ 2269 /* MC_CMD_TESTASSERT 2270 */ 2271 #define MC_CMD_TESTASSERT 0x49 2272 2273 /* MC_CMD_TESTASSERT_IN msgrequest */ 2274 #define MC_CMD_TESTASSERT_IN_LEN 0 2275 2276 /* MC_CMD_TESTASSERT_OUT msgresponse */ 2277 #define MC_CMD_TESTASSERT_OUT_LEN 0 2278 2279 2280 /***********************************/ 2281 /* MC_CMD_WORKAROUND 2282 * Enable/Disable a given workaround. 2283 */ 2284 #define MC_CMD_WORKAROUND 0x4a 2285 2286 /* MC_CMD_WORKAROUND_IN msgrequest */ 2287 #define MC_CMD_WORKAROUND_IN_LEN 8 2288 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 2289 #define MC_CMD_WORKAROUND_BUG17230 0x1 /* enum */ 2290 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 2291 2292 /* MC_CMD_WORKAROUND_OUT msgresponse */ 2293 #define MC_CMD_WORKAROUND_OUT_LEN 0 2294 2295 2296 /***********************************/ 2297 /* MC_CMD_GET_PHY_MEDIA_INFO 2298 * Read media-specific data from PHY. 2299 */ 2300 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 2301 2302 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 2303 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 2304 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 2305 2306 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 2307 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 2308 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 255 2309 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 2310 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 2311 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 2312 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 2313 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 2314 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 251 2315 2316 2317 /***********************************/ 2318 /* MC_CMD_NVRAM_TEST 2319 * Test a particular NVRAM partition. 2320 */ 2321 #define MC_CMD_NVRAM_TEST 0x4c 2322 2323 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 2324 #define MC_CMD_NVRAM_TEST_IN_LEN 4 2325 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 2326 /* Enum values, see field(s): */ 2327 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 2328 2329 /* MC_CMD_NVRAM_TEST_OUT msgresponse */ 2330 #define MC_CMD_NVRAM_TEST_OUT_LEN 4 2331 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 2332 #define MC_CMD_NVRAM_TEST_PASS 0x0 /* enum */ 2333 #define MC_CMD_NVRAM_TEST_FAIL 0x1 /* enum */ 2334 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 /* enum */ 2335 2336 2337 /***********************************/ 2338 /* MC_CMD_MRSFP_TWEAK 2339 * Read status and/or set parameters for the 'mrsfp' driver. 2340 */ 2341 #define MC_CMD_MRSFP_TWEAK 0x4d 2342 2343 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 2344 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 2345 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 2346 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 2347 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 2348 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 2349 2350 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 2351 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 2352 2353 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 2354 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 2355 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 2356 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 2357 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 2358 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 /* enum */ 2359 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 /* enum */ 2360 2361 2362 /***********************************/ 2363 /* MC_CMD_SENSOR_SET_LIMS 2364 * Adjusts the sensor limits. 2365 */ 2366 #define MC_CMD_SENSOR_SET_LIMS 0x4e 2367 2368 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 2369 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 2370 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 2371 /* Enum values, see field(s): */ 2372 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 2373 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 2374 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 2375 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 2376 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 2377 2378 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 2379 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 2380 2381 2382 /***********************************/ 2383 /* MC_CMD_GET_RESOURCE_LIMITS 2384 */ 2385 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 2386 2387 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 2388 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 2389 2390 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 2391 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 2392 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 2393 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 2394 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 2395 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 2396 2397 /* MC_CMD_RESOURCE_SPECIFIER enum */ 2398 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff /* enum */ 2399 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */ 2400 2401 2402 #endif /* MCDI_PCOL_H */ 2403