1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2006-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #ifndef EFX_IO_H 12 #define EFX_IO_H 13 14 #include <linux/io.h> 15 #include <linux/spinlock.h> 16 17 /************************************************************************** 18 * 19 * NIC register I/O 20 * 21 ************************************************************************** 22 * 23 * Notes on locking strategy for the Falcon architecture: 24 * 25 * Many CSRs are very wide and cannot be read or written atomically. 26 * Writes from the host are buffered by the Bus Interface Unit (BIU) 27 * up to 128 bits. Whenever the host writes part of such a register, 28 * the BIU collects the written value and does not write to the 29 * underlying register until all 4 dwords have been written. A 30 * similar buffering scheme applies to host access to the NIC's 64-bit 31 * SRAM. 32 * 33 * Writes to different CSRs and 64-bit SRAM words must be serialised, 34 * since interleaved access can result in lost writes. We use 35 * efx_nic::biu_lock for this. 36 * 37 * We also serialise reads from 128-bit CSRs and SRAM with the same 38 * spinlock. This may not be necessary, but it doesn't really matter 39 * as there are no such reads on the fast path. 40 * 41 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 42 * 128-bit but are special-cased in the BIU to avoid the need for 43 * locking in the host: 44 * 45 * - They are write-only. 46 * - The semantics of writing to these registers are such that 47 * replacing the low 96 bits with zero does not affect functionality. 48 * - If the host writes to the last dword address of such a register 49 * (i.e. the high 32 bits) the underlying register will always be 50 * written. If the collector and the current write together do not 51 * provide values for all 128 bits of the register, the low 96 bits 52 * will be written as zero. 53 * - If the host writes to the address of any other part of such a 54 * register while the collector already holds values for some other 55 * register, the write is discarded and the collector maintains its 56 * current state. 57 * 58 * The EF10 architecture exposes very few registers to the host and 59 * most of them are only 32 bits wide. The only exceptions are the MC 60 * doorbell register pair, which has its own latching, and 61 * TX_DESC_UPD, which works in a similar way to the Falcon 62 * architecture. 63 */ 64 65 #if BITS_PER_LONG == 64 66 #define EFX_USE_QWORD_IO 1 67 #endif 68 69 /* PIO is a win only if write-combining is possible */ 70 #ifdef ARCH_HAS_IOREMAP_WC 71 #define EFX_USE_PIO 1 72 #endif 73 74 #ifdef EFX_USE_QWORD_IO 75 static inline void _efx_writeq(struct efx_nic *efx, __le64 value, 76 unsigned int reg) 77 { 78 __raw_writeq((__force u64)value, efx->membase + reg); 79 } 80 static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg) 81 { 82 return (__force __le64)__raw_readq(efx->membase + reg); 83 } 84 #endif 85 86 static inline void _efx_writed(struct efx_nic *efx, __le32 value, 87 unsigned int reg) 88 { 89 __raw_writel((__force u32)value, efx->membase + reg); 90 } 91 static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg) 92 { 93 return (__force __le32)__raw_readl(efx->membase + reg); 94 } 95 96 /* Write a normal 128-bit CSR, locking as appropriate. */ 97 static inline void efx_writeo(struct efx_nic *efx, const efx_oword_t *value, 98 unsigned int reg) 99 { 100 unsigned long flags __attribute__ ((unused)); 101 102 netif_vdbg(efx, hw, efx->net_dev, 103 "writing register %x with " EFX_OWORD_FMT "\n", reg, 104 EFX_OWORD_VAL(*value)); 105 106 spin_lock_irqsave(&efx->biu_lock, flags); 107 #ifdef EFX_USE_QWORD_IO 108 _efx_writeq(efx, value->u64[0], reg + 0); 109 _efx_writeq(efx, value->u64[1], reg + 8); 110 #else 111 _efx_writed(efx, value->u32[0], reg + 0); 112 _efx_writed(efx, value->u32[1], reg + 4); 113 _efx_writed(efx, value->u32[2], reg + 8); 114 _efx_writed(efx, value->u32[3], reg + 12); 115 #endif 116 mmiowb(); 117 spin_unlock_irqrestore(&efx->biu_lock, flags); 118 } 119 120 /* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */ 121 static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase, 122 const efx_qword_t *value, unsigned int index) 123 { 124 unsigned int addr = index * sizeof(*value); 125 unsigned long flags __attribute__ ((unused)); 126 127 netif_vdbg(efx, hw, efx->net_dev, 128 "writing SRAM address %x with " EFX_QWORD_FMT "\n", 129 addr, EFX_QWORD_VAL(*value)); 130 131 spin_lock_irqsave(&efx->biu_lock, flags); 132 #ifdef EFX_USE_QWORD_IO 133 __raw_writeq((__force u64)value->u64[0], membase + addr); 134 #else 135 __raw_writel((__force u32)value->u32[0], membase + addr); 136 __raw_writel((__force u32)value->u32[1], membase + addr + 4); 137 #endif 138 mmiowb(); 139 spin_unlock_irqrestore(&efx->biu_lock, flags); 140 } 141 142 /* Write a 32-bit CSR or the last dword of a special 128-bit CSR */ 143 static inline void efx_writed(struct efx_nic *efx, const efx_dword_t *value, 144 unsigned int reg) 145 { 146 netif_vdbg(efx, hw, efx->net_dev, 147 "writing register %x with "EFX_DWORD_FMT"\n", 148 reg, EFX_DWORD_VAL(*value)); 149 150 /* No lock required */ 151 _efx_writed(efx, value->u32[0], reg); 152 } 153 154 /* Read a 128-bit CSR, locking as appropriate. */ 155 static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value, 156 unsigned int reg) 157 { 158 unsigned long flags __attribute__ ((unused)); 159 160 spin_lock_irqsave(&efx->biu_lock, flags); 161 value->u32[0] = _efx_readd(efx, reg + 0); 162 value->u32[1] = _efx_readd(efx, reg + 4); 163 value->u32[2] = _efx_readd(efx, reg + 8); 164 value->u32[3] = _efx_readd(efx, reg + 12); 165 spin_unlock_irqrestore(&efx->biu_lock, flags); 166 167 netif_vdbg(efx, hw, efx->net_dev, 168 "read from register %x, got " EFX_OWORD_FMT "\n", reg, 169 EFX_OWORD_VAL(*value)); 170 } 171 172 /* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */ 173 static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase, 174 efx_qword_t *value, unsigned int index) 175 { 176 unsigned int addr = index * sizeof(*value); 177 unsigned long flags __attribute__ ((unused)); 178 179 spin_lock_irqsave(&efx->biu_lock, flags); 180 #ifdef EFX_USE_QWORD_IO 181 value->u64[0] = (__force __le64)__raw_readq(membase + addr); 182 #else 183 value->u32[0] = (__force __le32)__raw_readl(membase + addr); 184 value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4); 185 #endif 186 spin_unlock_irqrestore(&efx->biu_lock, flags); 187 188 netif_vdbg(efx, hw, efx->net_dev, 189 "read from SRAM address %x, got "EFX_QWORD_FMT"\n", 190 addr, EFX_QWORD_VAL(*value)); 191 } 192 193 /* Read a 32-bit CSR or SRAM */ 194 static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value, 195 unsigned int reg) 196 { 197 value->u32[0] = _efx_readd(efx, reg); 198 netif_vdbg(efx, hw, efx->net_dev, 199 "read from register %x, got "EFX_DWORD_FMT"\n", 200 reg, EFX_DWORD_VAL(*value)); 201 } 202 203 /* Write a 128-bit CSR forming part of a table */ 204 static inline void 205 efx_writeo_table(struct efx_nic *efx, const efx_oword_t *value, 206 unsigned int reg, unsigned int index) 207 { 208 efx_writeo(efx, value, reg + index * sizeof(efx_oword_t)); 209 } 210 211 /* Read a 128-bit CSR forming part of a table */ 212 static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value, 213 unsigned int reg, unsigned int index) 214 { 215 efx_reado(efx, value, reg + index * sizeof(efx_oword_t)); 216 } 217 218 /* Page size used as step between per-VI registers */ 219 #define EFX_VI_PAGE_SIZE 0x2000 220 221 /* Calculate offset to page-mapped register */ 222 #define EFX_PAGED_REG(page, reg) \ 223 ((page) * EFX_VI_PAGE_SIZE + (reg)) 224 225 /* Write the whole of RX_DESC_UPD or TX_DESC_UPD */ 226 static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value, 227 unsigned int reg, unsigned int page) 228 { 229 reg = EFX_PAGED_REG(page, reg); 230 231 netif_vdbg(efx, hw, efx->net_dev, 232 "writing register %x with " EFX_OWORD_FMT "\n", reg, 233 EFX_OWORD_VAL(*value)); 234 235 #ifdef EFX_USE_QWORD_IO 236 _efx_writeq(efx, value->u64[0], reg + 0); 237 _efx_writeq(efx, value->u64[1], reg + 8); 238 #else 239 _efx_writed(efx, value->u32[0], reg + 0); 240 _efx_writed(efx, value->u32[1], reg + 4); 241 _efx_writed(efx, value->u32[2], reg + 8); 242 _efx_writed(efx, value->u32[3], reg + 12); 243 #endif 244 } 245 #define efx_writeo_page(efx, value, reg, page) \ 246 _efx_writeo_page(efx, value, \ 247 reg + \ 248 BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \ 249 page) 250 251 /* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the 252 * high bits of RX_DESC_UPD or TX_DESC_UPD) 253 */ 254 static inline void 255 _efx_writed_page(struct efx_nic *efx, const efx_dword_t *value, 256 unsigned int reg, unsigned int page) 257 { 258 efx_writed(efx, value, EFX_PAGED_REG(page, reg)); 259 } 260 #define efx_writed_page(efx, value, reg, page) \ 261 _efx_writed_page(efx, value, \ 262 reg + \ 263 BUILD_BUG_ON_ZERO((reg) != 0x400 && \ 264 (reg) != 0x420 && \ 265 (reg) != 0x830 && \ 266 (reg) != 0x83c && \ 267 (reg) != 0xa18 && \ 268 (reg) != 0xa1c), \ 269 page) 270 271 /* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug 272 * in the BIU means that writes to TIMER_COMMAND[0] invalidate the 273 * collector register. 274 */ 275 static inline void _efx_writed_page_locked(struct efx_nic *efx, 276 const efx_dword_t *value, 277 unsigned int reg, 278 unsigned int page) 279 { 280 unsigned long flags __attribute__ ((unused)); 281 282 if (page == 0) { 283 spin_lock_irqsave(&efx->biu_lock, flags); 284 efx_writed(efx, value, EFX_PAGED_REG(page, reg)); 285 spin_unlock_irqrestore(&efx->biu_lock, flags); 286 } else { 287 efx_writed(efx, value, EFX_PAGED_REG(page, reg)); 288 } 289 } 290 #define efx_writed_page_locked(efx, value, reg, page) \ 291 _efx_writed_page_locked(efx, value, \ 292 reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \ 293 page) 294 295 #endif /* EFX_IO_H */ 296