1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
25a6681e2SEdward Cree /****************************************************************************
35a6681e2SEdward Cree * Driver for Solarflare network controllers and boards
45a6681e2SEdward Cree * Copyright 2005-2006 Fen Systems Ltd.
55a6681e2SEdward Cree * Copyright 2005-2013 Solarflare Communications Inc.
65a6681e2SEdward Cree */
75a6681e2SEdward Cree
85a6681e2SEdward Cree #include <linux/pci.h>
95a6681e2SEdward Cree #include <linux/tcp.h>
105a6681e2SEdward Cree #include <linux/ip.h>
115a6681e2SEdward Cree #include <linux/in.h>
125a6681e2SEdward Cree #include <linux/ipv6.h>
135a6681e2SEdward Cree #include <linux/slab.h>
145a6681e2SEdward Cree #include <net/ipv6.h>
155a6681e2SEdward Cree #include <linux/if_ether.h>
165a6681e2SEdward Cree #include <linux/highmem.h>
175a6681e2SEdward Cree #include <linux/cache.h>
185a6681e2SEdward Cree #include "net_driver.h"
195a6681e2SEdward Cree #include "efx.h"
205a6681e2SEdward Cree #include "io.h"
215a6681e2SEdward Cree #include "nic.h"
225a6681e2SEdward Cree #include "tx.h"
235a6681e2SEdward Cree #include "workarounds.h"
245a6681e2SEdward Cree
ef4_tx_get_copy_buffer(struct ef4_tx_queue * tx_queue,struct ef4_tx_buffer * buffer)255a6681e2SEdward Cree static inline u8 *ef4_tx_get_copy_buffer(struct ef4_tx_queue *tx_queue,
265a6681e2SEdward Cree struct ef4_tx_buffer *buffer)
275a6681e2SEdward Cree {
285a6681e2SEdward Cree unsigned int index = ef4_tx_queue_get_insert_index(tx_queue);
295a6681e2SEdward Cree struct ef4_buffer *page_buf =
305a6681e2SEdward Cree &tx_queue->cb_page[index >> (PAGE_SHIFT - EF4_TX_CB_ORDER)];
315a6681e2SEdward Cree unsigned int offset =
325a6681e2SEdward Cree ((index << EF4_TX_CB_ORDER) + NET_IP_ALIGN) & (PAGE_SIZE - 1);
335a6681e2SEdward Cree
345a6681e2SEdward Cree if (unlikely(!page_buf->addr) &&
355a6681e2SEdward Cree ef4_nic_alloc_buffer(tx_queue->efx, page_buf, PAGE_SIZE,
365a6681e2SEdward Cree GFP_ATOMIC))
375a6681e2SEdward Cree return NULL;
385a6681e2SEdward Cree buffer->dma_addr = page_buf->dma_addr + offset;
395a6681e2SEdward Cree buffer->unmap_len = 0;
405a6681e2SEdward Cree return (u8 *)page_buf->addr + offset;
415a6681e2SEdward Cree }
425a6681e2SEdward Cree
ef4_tx_get_copy_buffer_limited(struct ef4_tx_queue * tx_queue,struct ef4_tx_buffer * buffer,size_t len)435a6681e2SEdward Cree u8 *ef4_tx_get_copy_buffer_limited(struct ef4_tx_queue *tx_queue,
445a6681e2SEdward Cree struct ef4_tx_buffer *buffer, size_t len)
455a6681e2SEdward Cree {
465a6681e2SEdward Cree if (len > EF4_TX_CB_SIZE)
475a6681e2SEdward Cree return NULL;
485a6681e2SEdward Cree return ef4_tx_get_copy_buffer(tx_queue, buffer);
495a6681e2SEdward Cree }
505a6681e2SEdward Cree
ef4_dequeue_buffer(struct ef4_tx_queue * tx_queue,struct ef4_tx_buffer * buffer,unsigned int * pkts_compl,unsigned int * bytes_compl)515a6681e2SEdward Cree static void ef4_dequeue_buffer(struct ef4_tx_queue *tx_queue,
525a6681e2SEdward Cree struct ef4_tx_buffer *buffer,
535a6681e2SEdward Cree unsigned int *pkts_compl,
545a6681e2SEdward Cree unsigned int *bytes_compl)
555a6681e2SEdward Cree {
565a6681e2SEdward Cree if (buffer->unmap_len) {
575a6681e2SEdward Cree struct device *dma_dev = &tx_queue->efx->pci_dev->dev;
585a6681e2SEdward Cree dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset;
595a6681e2SEdward Cree if (buffer->flags & EF4_TX_BUF_MAP_SINGLE)
605a6681e2SEdward Cree dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len,
615a6681e2SEdward Cree DMA_TO_DEVICE);
625a6681e2SEdward Cree else
635a6681e2SEdward Cree dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len,
645a6681e2SEdward Cree DMA_TO_DEVICE);
655a6681e2SEdward Cree buffer->unmap_len = 0;
665a6681e2SEdward Cree }
675a6681e2SEdward Cree
685a6681e2SEdward Cree if (buffer->flags & EF4_TX_BUF_SKB) {
695a6681e2SEdward Cree (*pkts_compl)++;
705a6681e2SEdward Cree (*bytes_compl) += buffer->skb->len;
715a6681e2SEdward Cree dev_consume_skb_any((struct sk_buff *)buffer->skb);
725a6681e2SEdward Cree netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
735a6681e2SEdward Cree "TX queue %d transmission id %x complete\n",
745a6681e2SEdward Cree tx_queue->queue, tx_queue->read_count);
755a6681e2SEdward Cree }
765a6681e2SEdward Cree
775a6681e2SEdward Cree buffer->len = 0;
785a6681e2SEdward Cree buffer->flags = 0;
795a6681e2SEdward Cree }
805a6681e2SEdward Cree
ef4_tx_max_skb_descs(struct ef4_nic * efx)815a6681e2SEdward Cree unsigned int ef4_tx_max_skb_descs(struct ef4_nic *efx)
825a6681e2SEdward Cree {
835a6681e2SEdward Cree /* This is probably too much since we don't have any TSO support;
845a6681e2SEdward Cree * it's a left-over from when we had Software TSO. But it's safer
855a6681e2SEdward Cree * to leave it as-is than try to determine a new bound.
865a6681e2SEdward Cree */
875a6681e2SEdward Cree /* Header and payload descriptor for each output segment, plus
885a6681e2SEdward Cree * one for every input fragment boundary within a segment
895a6681e2SEdward Cree */
905a6681e2SEdward Cree unsigned int max_descs = EF4_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS;
915a6681e2SEdward Cree
925a6681e2SEdward Cree /* Possibly one more per segment for the alignment workaround,
935a6681e2SEdward Cree * or for option descriptors
945a6681e2SEdward Cree */
955a6681e2SEdward Cree if (EF4_WORKAROUND_5391(efx))
965a6681e2SEdward Cree max_descs += EF4_TSO_MAX_SEGS;
975a6681e2SEdward Cree
985a6681e2SEdward Cree /* Possibly more for PCIe page boundaries within input fragments */
995a6681e2SEdward Cree if (PAGE_SIZE > EF4_PAGE_SIZE)
1005a6681e2SEdward Cree max_descs += max_t(unsigned int, MAX_SKB_FRAGS,
101*7c4e983cSAlexander Duyck DIV_ROUND_UP(GSO_LEGACY_MAX_SIZE,
102*7c4e983cSAlexander Duyck EF4_PAGE_SIZE));
1035a6681e2SEdward Cree
1045a6681e2SEdward Cree return max_descs;
1055a6681e2SEdward Cree }
1065a6681e2SEdward Cree
ef4_tx_maybe_stop_queue(struct ef4_tx_queue * txq1)1075a6681e2SEdward Cree static void ef4_tx_maybe_stop_queue(struct ef4_tx_queue *txq1)
1085a6681e2SEdward Cree {
1095a6681e2SEdward Cree /* We need to consider both queues that the net core sees as one */
1105a6681e2SEdward Cree struct ef4_tx_queue *txq2 = ef4_tx_queue_partner(txq1);
1115a6681e2SEdward Cree struct ef4_nic *efx = txq1->efx;
1125a6681e2SEdward Cree unsigned int fill_level;
1135a6681e2SEdward Cree
1145a6681e2SEdward Cree fill_level = max(txq1->insert_count - txq1->old_read_count,
1155a6681e2SEdward Cree txq2->insert_count - txq2->old_read_count);
1165a6681e2SEdward Cree if (likely(fill_level < efx->txq_stop_thresh))
1175a6681e2SEdward Cree return;
1185a6681e2SEdward Cree
1195a6681e2SEdward Cree /* We used the stale old_read_count above, which gives us a
1205a6681e2SEdward Cree * pessimistic estimate of the fill level (which may even
1215a6681e2SEdward Cree * validly be >= efx->txq_entries). Now try again using
1225a6681e2SEdward Cree * read_count (more likely to be a cache miss).
1235a6681e2SEdward Cree *
1245a6681e2SEdward Cree * If we read read_count and then conditionally stop the
1255a6681e2SEdward Cree * queue, it is possible for the completion path to race with
1265a6681e2SEdward Cree * us and complete all outstanding descriptors in the middle,
1275a6681e2SEdward Cree * after which there will be no more completions to wake it.
1285a6681e2SEdward Cree * Therefore we stop the queue first, then read read_count
1295a6681e2SEdward Cree * (with a memory barrier to ensure the ordering), then
1305a6681e2SEdward Cree * restart the queue if the fill level turns out to be low
1315a6681e2SEdward Cree * enough.
1325a6681e2SEdward Cree */
1335a6681e2SEdward Cree netif_tx_stop_queue(txq1->core_txq);
1345a6681e2SEdward Cree smp_mb();
1356aa7de05SMark Rutland txq1->old_read_count = READ_ONCE(txq1->read_count);
1366aa7de05SMark Rutland txq2->old_read_count = READ_ONCE(txq2->read_count);
1375a6681e2SEdward Cree
1385a6681e2SEdward Cree fill_level = max(txq1->insert_count - txq1->old_read_count,
1395a6681e2SEdward Cree txq2->insert_count - txq2->old_read_count);
1405a6681e2SEdward Cree EF4_BUG_ON_PARANOID(fill_level >= efx->txq_entries);
1415a6681e2SEdward Cree if (likely(fill_level < efx->txq_stop_thresh)) {
1425a6681e2SEdward Cree smp_mb();
1435a6681e2SEdward Cree if (likely(!efx->loopback_selftest))
1445a6681e2SEdward Cree netif_tx_start_queue(txq1->core_txq);
1455a6681e2SEdward Cree }
1465a6681e2SEdward Cree }
1475a6681e2SEdward Cree
ef4_enqueue_skb_copy(struct ef4_tx_queue * tx_queue,struct sk_buff * skb)1485a6681e2SEdward Cree static int ef4_enqueue_skb_copy(struct ef4_tx_queue *tx_queue,
1495a6681e2SEdward Cree struct sk_buff *skb)
1505a6681e2SEdward Cree {
1515a6681e2SEdward Cree unsigned int min_len = tx_queue->tx_min_size;
1525a6681e2SEdward Cree unsigned int copy_len = skb->len;
1535a6681e2SEdward Cree struct ef4_tx_buffer *buffer;
1545a6681e2SEdward Cree u8 *copy_buffer;
1555a6681e2SEdward Cree int rc;
1565a6681e2SEdward Cree
1575a6681e2SEdward Cree EF4_BUG_ON_PARANOID(copy_len > EF4_TX_CB_SIZE);
1585a6681e2SEdward Cree
1595a6681e2SEdward Cree buffer = ef4_tx_queue_get_insert_buffer(tx_queue);
1605a6681e2SEdward Cree
1615a6681e2SEdward Cree copy_buffer = ef4_tx_get_copy_buffer(tx_queue, buffer);
1625a6681e2SEdward Cree if (unlikely(!copy_buffer))
1635a6681e2SEdward Cree return -ENOMEM;
1645a6681e2SEdward Cree
1655a6681e2SEdward Cree rc = skb_copy_bits(skb, 0, copy_buffer, copy_len);
1665a6681e2SEdward Cree EF4_WARN_ON_PARANOID(rc);
1675a6681e2SEdward Cree if (unlikely(copy_len < min_len)) {
1685a6681e2SEdward Cree memset(copy_buffer + copy_len, 0, min_len - copy_len);
1695a6681e2SEdward Cree buffer->len = min_len;
1705a6681e2SEdward Cree } else {
1715a6681e2SEdward Cree buffer->len = copy_len;
1725a6681e2SEdward Cree }
1735a6681e2SEdward Cree
1745a6681e2SEdward Cree buffer->skb = skb;
1755a6681e2SEdward Cree buffer->flags = EF4_TX_BUF_SKB;
1765a6681e2SEdward Cree
1775a6681e2SEdward Cree ++tx_queue->insert_count;
1785a6681e2SEdward Cree return rc;
1795a6681e2SEdward Cree }
1805a6681e2SEdward Cree
ef4_tx_map_chunk(struct ef4_tx_queue * tx_queue,dma_addr_t dma_addr,size_t len)1815a6681e2SEdward Cree static struct ef4_tx_buffer *ef4_tx_map_chunk(struct ef4_tx_queue *tx_queue,
1825a6681e2SEdward Cree dma_addr_t dma_addr,
1835a6681e2SEdward Cree size_t len)
1845a6681e2SEdward Cree {
1855a6681e2SEdward Cree const struct ef4_nic_type *nic_type = tx_queue->efx->type;
1865a6681e2SEdward Cree struct ef4_tx_buffer *buffer;
1875a6681e2SEdward Cree unsigned int dma_len;
1885a6681e2SEdward Cree
1895a6681e2SEdward Cree /* Map the fragment taking account of NIC-dependent DMA limits. */
1905a6681e2SEdward Cree do {
1915a6681e2SEdward Cree buffer = ef4_tx_queue_get_insert_buffer(tx_queue);
1925a6681e2SEdward Cree dma_len = nic_type->tx_limit_len(tx_queue, dma_addr, len);
1935a6681e2SEdward Cree
1945a6681e2SEdward Cree buffer->len = dma_len;
1955a6681e2SEdward Cree buffer->dma_addr = dma_addr;
1965a6681e2SEdward Cree buffer->flags = EF4_TX_BUF_CONT;
1975a6681e2SEdward Cree len -= dma_len;
1985a6681e2SEdward Cree dma_addr += dma_len;
1995a6681e2SEdward Cree ++tx_queue->insert_count;
2005a6681e2SEdward Cree } while (len);
2015a6681e2SEdward Cree
2025a6681e2SEdward Cree return buffer;
2035a6681e2SEdward Cree }
2045a6681e2SEdward Cree
2055a6681e2SEdward Cree /* Map all data from an SKB for DMA and create descriptors on the queue.
2065a6681e2SEdward Cree */
ef4_tx_map_data(struct ef4_tx_queue * tx_queue,struct sk_buff * skb)2075a6681e2SEdward Cree static int ef4_tx_map_data(struct ef4_tx_queue *tx_queue, struct sk_buff *skb)
2085a6681e2SEdward Cree {
2095a6681e2SEdward Cree struct ef4_nic *efx = tx_queue->efx;
2105a6681e2SEdward Cree struct device *dma_dev = &efx->pci_dev->dev;
2115a6681e2SEdward Cree unsigned int frag_index, nr_frags;
2125a6681e2SEdward Cree dma_addr_t dma_addr, unmap_addr;
2135a6681e2SEdward Cree unsigned short dma_flags;
2145a6681e2SEdward Cree size_t len, unmap_len;
2155a6681e2SEdward Cree
2165a6681e2SEdward Cree nr_frags = skb_shinfo(skb)->nr_frags;
2175a6681e2SEdward Cree frag_index = 0;
2185a6681e2SEdward Cree
2195a6681e2SEdward Cree /* Map header data. */
2205a6681e2SEdward Cree len = skb_headlen(skb);
2215a6681e2SEdward Cree dma_addr = dma_map_single(dma_dev, skb->data, len, DMA_TO_DEVICE);
2225a6681e2SEdward Cree dma_flags = EF4_TX_BUF_MAP_SINGLE;
2235a6681e2SEdward Cree unmap_len = len;
2245a6681e2SEdward Cree unmap_addr = dma_addr;
2255a6681e2SEdward Cree
2265a6681e2SEdward Cree if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
2275a6681e2SEdward Cree return -EIO;
2285a6681e2SEdward Cree
2295a6681e2SEdward Cree /* Add descriptors for each fragment. */
2305a6681e2SEdward Cree do {
2315a6681e2SEdward Cree struct ef4_tx_buffer *buffer;
2325a6681e2SEdward Cree skb_frag_t *fragment;
2335a6681e2SEdward Cree
2345a6681e2SEdward Cree buffer = ef4_tx_map_chunk(tx_queue, dma_addr, len);
2355a6681e2SEdward Cree
2365a6681e2SEdward Cree /* The final descriptor for a fragment is responsible for
2375a6681e2SEdward Cree * unmapping the whole fragment.
2385a6681e2SEdward Cree */
2395a6681e2SEdward Cree buffer->flags = EF4_TX_BUF_CONT | dma_flags;
2405a6681e2SEdward Cree buffer->unmap_len = unmap_len;
2415a6681e2SEdward Cree buffer->dma_offset = buffer->dma_addr - unmap_addr;
2425a6681e2SEdward Cree
2435a6681e2SEdward Cree if (frag_index >= nr_frags) {
2445a6681e2SEdward Cree /* Store SKB details with the final buffer for
2455a6681e2SEdward Cree * the completion.
2465a6681e2SEdward Cree */
2475a6681e2SEdward Cree buffer->skb = skb;
2485a6681e2SEdward Cree buffer->flags = EF4_TX_BUF_SKB | dma_flags;
2495a6681e2SEdward Cree return 0;
2505a6681e2SEdward Cree }
2515a6681e2SEdward Cree
2525a6681e2SEdward Cree /* Move on to the next fragment. */
2535a6681e2SEdward Cree fragment = &skb_shinfo(skb)->frags[frag_index++];
2545a6681e2SEdward Cree len = skb_frag_size(fragment);
2555a6681e2SEdward Cree dma_addr = skb_frag_dma_map(dma_dev, fragment,
2565a6681e2SEdward Cree 0, len, DMA_TO_DEVICE);
2575a6681e2SEdward Cree dma_flags = 0;
2585a6681e2SEdward Cree unmap_len = len;
2595a6681e2SEdward Cree unmap_addr = dma_addr;
2605a6681e2SEdward Cree
2615a6681e2SEdward Cree if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
2625a6681e2SEdward Cree return -EIO;
2635a6681e2SEdward Cree } while (1);
2645a6681e2SEdward Cree }
2655a6681e2SEdward Cree
2665a6681e2SEdward Cree /* Remove buffers put into a tx_queue. None of the buffers must have
2675a6681e2SEdward Cree * an skb attached.
2685a6681e2SEdward Cree */
ef4_enqueue_unwind(struct ef4_tx_queue * tx_queue)2695a6681e2SEdward Cree static void ef4_enqueue_unwind(struct ef4_tx_queue *tx_queue)
2705a6681e2SEdward Cree {
2715a6681e2SEdward Cree struct ef4_tx_buffer *buffer;
2725a6681e2SEdward Cree
2735a6681e2SEdward Cree /* Work backwards until we hit the original insert pointer value */
2745a6681e2SEdward Cree while (tx_queue->insert_count != tx_queue->write_count) {
2755a6681e2SEdward Cree --tx_queue->insert_count;
2765a6681e2SEdward Cree buffer = __ef4_tx_queue_get_insert_buffer(tx_queue);
2775a6681e2SEdward Cree ef4_dequeue_buffer(tx_queue, buffer, NULL, NULL);
2785a6681e2SEdward Cree }
2795a6681e2SEdward Cree }
2805a6681e2SEdward Cree
2815a6681e2SEdward Cree /*
2825a6681e2SEdward Cree * Add a socket buffer to a TX queue
2835a6681e2SEdward Cree *
2845a6681e2SEdward Cree * This maps all fragments of a socket buffer for DMA and adds them to
2855a6681e2SEdward Cree * the TX queue. The queue's insert pointer will be incremented by
2865a6681e2SEdward Cree * the number of fragments in the socket buffer.
2875a6681e2SEdward Cree *
2885a6681e2SEdward Cree * If any DMA mapping fails, any mapped fragments will be unmapped,
2895a6681e2SEdward Cree * the queue's insert pointer will be restored to its original value.
2905a6681e2SEdward Cree *
2915a6681e2SEdward Cree * This function is split out from ef4_hard_start_xmit to allow the
2925a6681e2SEdward Cree * loopback test to direct packets via specific TX queues.
2935a6681e2SEdward Cree *
2945a6681e2SEdward Cree * Returns NETDEV_TX_OK.
2955a6681e2SEdward Cree * You must hold netif_tx_lock() to call this function.
2965a6681e2SEdward Cree */
ef4_enqueue_skb(struct ef4_tx_queue * tx_queue,struct sk_buff * skb)2975a6681e2SEdward Cree netdev_tx_t ef4_enqueue_skb(struct ef4_tx_queue *tx_queue, struct sk_buff *skb)
2985a6681e2SEdward Cree {
2995a6681e2SEdward Cree bool data_mapped = false;
3005a6681e2SEdward Cree unsigned int skb_len;
3015a6681e2SEdward Cree
3025a6681e2SEdward Cree skb_len = skb->len;
3035a6681e2SEdward Cree EF4_WARN_ON_PARANOID(skb_is_gso(skb));
3045a6681e2SEdward Cree
3055a6681e2SEdward Cree if (skb_len < tx_queue->tx_min_size ||
3065a6681e2SEdward Cree (skb->data_len && skb_len <= EF4_TX_CB_SIZE)) {
3075a6681e2SEdward Cree /* Pad short packets or coalesce short fragmented packets. */
3085a6681e2SEdward Cree if (ef4_enqueue_skb_copy(tx_queue, skb))
3095a6681e2SEdward Cree goto err;
3105a6681e2SEdward Cree tx_queue->cb_packets++;
3115a6681e2SEdward Cree data_mapped = true;
3125a6681e2SEdward Cree }
3135a6681e2SEdward Cree
3145a6681e2SEdward Cree /* Map for DMA and create descriptors if we haven't done so already. */
3155a6681e2SEdward Cree if (!data_mapped && (ef4_tx_map_data(tx_queue, skb)))
3165a6681e2SEdward Cree goto err;
3175a6681e2SEdward Cree
3185a6681e2SEdward Cree /* Update BQL */
3195a6681e2SEdward Cree netdev_tx_sent_queue(tx_queue->core_txq, skb_len);
3205a6681e2SEdward Cree
3215a6681e2SEdward Cree /* Pass off to hardware */
322f79c957aSFlorian Westphal if (!netdev_xmit_more() || netif_xmit_stopped(tx_queue->core_txq)) {
3235a6681e2SEdward Cree struct ef4_tx_queue *txq2 = ef4_tx_queue_partner(tx_queue);
3245a6681e2SEdward Cree
3255a6681e2SEdward Cree /* There could be packets left on the partner queue if those
3265a6681e2SEdward Cree * SKBs had skb->xmit_more set. If we do not push those they
3275a6681e2SEdward Cree * could be left for a long time and cause a netdev watchdog.
3285a6681e2SEdward Cree */
3295a6681e2SEdward Cree if (txq2->xmit_more_available)
3305a6681e2SEdward Cree ef4_nic_push_buffers(txq2);
3315a6681e2SEdward Cree
3325a6681e2SEdward Cree ef4_nic_push_buffers(tx_queue);
3335a6681e2SEdward Cree } else {
334f79c957aSFlorian Westphal tx_queue->xmit_more_available = netdev_xmit_more();
3355a6681e2SEdward Cree }
3365a6681e2SEdward Cree
3375a6681e2SEdward Cree tx_queue->tx_packets++;
3385a6681e2SEdward Cree
3395a6681e2SEdward Cree ef4_tx_maybe_stop_queue(tx_queue);
3405a6681e2SEdward Cree
3415a6681e2SEdward Cree return NETDEV_TX_OK;
3425a6681e2SEdward Cree
3435a6681e2SEdward Cree
3445a6681e2SEdward Cree err:
3455a6681e2SEdward Cree ef4_enqueue_unwind(tx_queue);
3465a6681e2SEdward Cree dev_kfree_skb_any(skb);
3475a6681e2SEdward Cree return NETDEV_TX_OK;
3485a6681e2SEdward Cree }
3495a6681e2SEdward Cree
3505a6681e2SEdward Cree /* Remove packets from the TX queue
3515a6681e2SEdward Cree *
3525a6681e2SEdward Cree * This removes packets from the TX queue, up to and including the
3535a6681e2SEdward Cree * specified index.
3545a6681e2SEdward Cree */
ef4_dequeue_buffers(struct ef4_tx_queue * tx_queue,unsigned int index,unsigned int * pkts_compl,unsigned int * bytes_compl)3555a6681e2SEdward Cree static void ef4_dequeue_buffers(struct ef4_tx_queue *tx_queue,
3565a6681e2SEdward Cree unsigned int index,
3575a6681e2SEdward Cree unsigned int *pkts_compl,
3585a6681e2SEdward Cree unsigned int *bytes_compl)
3595a6681e2SEdward Cree {
3605a6681e2SEdward Cree struct ef4_nic *efx = tx_queue->efx;
3615a6681e2SEdward Cree unsigned int stop_index, read_ptr;
3625a6681e2SEdward Cree
3635a6681e2SEdward Cree stop_index = (index + 1) & tx_queue->ptr_mask;
3645a6681e2SEdward Cree read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
3655a6681e2SEdward Cree
3665a6681e2SEdward Cree while (read_ptr != stop_index) {
3675a6681e2SEdward Cree struct ef4_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
3685a6681e2SEdward Cree
3695a6681e2SEdward Cree if (!(buffer->flags & EF4_TX_BUF_OPTION) &&
3705a6681e2SEdward Cree unlikely(buffer->len == 0)) {
3715a6681e2SEdward Cree netif_err(efx, tx_err, efx->net_dev,
3725a6681e2SEdward Cree "TX queue %d spurious TX completion id %x\n",
3735a6681e2SEdward Cree tx_queue->queue, read_ptr);
3745a6681e2SEdward Cree ef4_schedule_reset(efx, RESET_TYPE_TX_SKIP);
3755a6681e2SEdward Cree return;
3765a6681e2SEdward Cree }
3775a6681e2SEdward Cree
3785a6681e2SEdward Cree ef4_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl);
3795a6681e2SEdward Cree
3805a6681e2SEdward Cree ++tx_queue->read_count;
3815a6681e2SEdward Cree read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
3825a6681e2SEdward Cree }
3835a6681e2SEdward Cree }
3845a6681e2SEdward Cree
3855a6681e2SEdward Cree /* Initiate a packet transmission. We use one channel per CPU
3865a6681e2SEdward Cree * (sharing when we have more CPUs than channels). On Falcon, the TX
3875a6681e2SEdward Cree * completion events will be directed back to the CPU that transmitted
3885a6681e2SEdward Cree * the packet, which should be cache-efficient.
3895a6681e2SEdward Cree *
3905a6681e2SEdward Cree * Context: non-blocking.
3915a6681e2SEdward Cree * Note that returning anything other than NETDEV_TX_OK will cause the
3925a6681e2SEdward Cree * OS to free the skb.
3935a6681e2SEdward Cree */
ef4_hard_start_xmit(struct sk_buff * skb,struct net_device * net_dev)3945a6681e2SEdward Cree netdev_tx_t ef4_hard_start_xmit(struct sk_buff *skb,
3955a6681e2SEdward Cree struct net_device *net_dev)
3965a6681e2SEdward Cree {
3975a6681e2SEdward Cree struct ef4_nic *efx = netdev_priv(net_dev);
3985a6681e2SEdward Cree struct ef4_tx_queue *tx_queue;
3995a6681e2SEdward Cree unsigned index, type;
4005a6681e2SEdward Cree
4015a6681e2SEdward Cree EF4_WARN_ON_PARANOID(!netif_device_present(net_dev));
4025a6681e2SEdward Cree
4035a6681e2SEdward Cree index = skb_get_queue_mapping(skb);
4045a6681e2SEdward Cree type = skb->ip_summed == CHECKSUM_PARTIAL ? EF4_TXQ_TYPE_OFFLOAD : 0;
4055a6681e2SEdward Cree if (index >= efx->n_tx_channels) {
4065a6681e2SEdward Cree index -= efx->n_tx_channels;
4075a6681e2SEdward Cree type |= EF4_TXQ_TYPE_HIGHPRI;
4085a6681e2SEdward Cree }
4095a6681e2SEdward Cree tx_queue = ef4_get_tx_queue(efx, index, type);
4105a6681e2SEdward Cree
4115a6681e2SEdward Cree return ef4_enqueue_skb(tx_queue, skb);
4125a6681e2SEdward Cree }
4135a6681e2SEdward Cree
ef4_init_tx_queue_core_txq(struct ef4_tx_queue * tx_queue)4145a6681e2SEdward Cree void ef4_init_tx_queue_core_txq(struct ef4_tx_queue *tx_queue)
4155a6681e2SEdward Cree {
4165a6681e2SEdward Cree struct ef4_nic *efx = tx_queue->efx;
4175a6681e2SEdward Cree
4185a6681e2SEdward Cree /* Must be inverse of queue lookup in ef4_hard_start_xmit() */
4195a6681e2SEdward Cree tx_queue->core_txq =
4205a6681e2SEdward Cree netdev_get_tx_queue(efx->net_dev,
4215a6681e2SEdward Cree tx_queue->queue / EF4_TXQ_TYPES +
4225a6681e2SEdward Cree ((tx_queue->queue & EF4_TXQ_TYPE_HIGHPRI) ?
4235a6681e2SEdward Cree efx->n_tx_channels : 0));
4245a6681e2SEdward Cree }
4255a6681e2SEdward Cree
ef4_setup_tc(struct net_device * net_dev,enum tc_setup_type type,void * type_data)4262572ac53SJiri Pirko int ef4_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
427de4784caSJiri Pirko void *type_data)
4285a6681e2SEdward Cree {
4295a6681e2SEdward Cree struct ef4_nic *efx = netdev_priv(net_dev);
430de4784caSJiri Pirko struct tc_mqprio_qopt *mqprio = type_data;
4315a6681e2SEdward Cree struct ef4_channel *channel;
4325a6681e2SEdward Cree struct ef4_tx_queue *tx_queue;
4335a6681e2SEdward Cree unsigned tc, num_tc;
4345a6681e2SEdward Cree int rc;
4355a6681e2SEdward Cree
436575ed7d3SNogah Frankel if (type != TC_SETUP_QDISC_MQPRIO)
43738cf0426SJiri Pirko return -EOPNOTSUPP;
4385a6681e2SEdward Cree
439de4784caSJiri Pirko num_tc = mqprio->num_tc;
4405a6681e2SEdward Cree
4415a6681e2SEdward Cree if (ef4_nic_rev(efx) < EF4_REV_FALCON_B0 || num_tc > EF4_MAX_TX_TC)
4425a6681e2SEdward Cree return -EINVAL;
4435a6681e2SEdward Cree
444de4784caSJiri Pirko mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
44556f36acdSAmritha Nambiar
4465a6681e2SEdward Cree if (num_tc == net_dev->num_tc)
4475a6681e2SEdward Cree return 0;
4485a6681e2SEdward Cree
4495a6681e2SEdward Cree for (tc = 0; tc < num_tc; tc++) {
4505a6681e2SEdward Cree net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels;
4515a6681e2SEdward Cree net_dev->tc_to_txq[tc].count = efx->n_tx_channels;
4525a6681e2SEdward Cree }
4535a6681e2SEdward Cree
4545a6681e2SEdward Cree if (num_tc > net_dev->num_tc) {
4555a6681e2SEdward Cree /* Initialise high-priority queues as necessary */
4565a6681e2SEdward Cree ef4_for_each_channel(channel, efx) {
4575a6681e2SEdward Cree ef4_for_each_possible_channel_tx_queue(tx_queue,
4585a6681e2SEdward Cree channel) {
4595a6681e2SEdward Cree if (!(tx_queue->queue & EF4_TXQ_TYPE_HIGHPRI))
4605a6681e2SEdward Cree continue;
4615a6681e2SEdward Cree if (!tx_queue->buffer) {
4625a6681e2SEdward Cree rc = ef4_probe_tx_queue(tx_queue);
4635a6681e2SEdward Cree if (rc)
4645a6681e2SEdward Cree return rc;
4655a6681e2SEdward Cree }
4665a6681e2SEdward Cree if (!tx_queue->initialised)
4675a6681e2SEdward Cree ef4_init_tx_queue(tx_queue);
4685a6681e2SEdward Cree ef4_init_tx_queue_core_txq(tx_queue);
4695a6681e2SEdward Cree }
4705a6681e2SEdward Cree }
4715a6681e2SEdward Cree } else {
4725a6681e2SEdward Cree /* Reduce number of classes before number of queues */
4735a6681e2SEdward Cree net_dev->num_tc = num_tc;
4745a6681e2SEdward Cree }
4755a6681e2SEdward Cree
4765a6681e2SEdward Cree rc = netif_set_real_num_tx_queues(net_dev,
4775a6681e2SEdward Cree max_t(int, num_tc, 1) *
4785a6681e2SEdward Cree efx->n_tx_channels);
4795a6681e2SEdward Cree if (rc)
4805a6681e2SEdward Cree return rc;
4815a6681e2SEdward Cree
4825a6681e2SEdward Cree /* Do not destroy high-priority queues when they become
4835a6681e2SEdward Cree * unused. We would have to flush them first, and it is
4845a6681e2SEdward Cree * fairly difficult to flush a subset of TX queues. Leave
4855a6681e2SEdward Cree * it to ef4_fini_channels().
4865a6681e2SEdward Cree */
4875a6681e2SEdward Cree
4885a6681e2SEdward Cree net_dev->num_tc = num_tc;
4895a6681e2SEdward Cree return 0;
4905a6681e2SEdward Cree }
4915a6681e2SEdward Cree
ef4_xmit_done(struct ef4_tx_queue * tx_queue,unsigned int index)4925a6681e2SEdward Cree void ef4_xmit_done(struct ef4_tx_queue *tx_queue, unsigned int index)
4935a6681e2SEdward Cree {
4945a6681e2SEdward Cree unsigned fill_level;
4955a6681e2SEdward Cree struct ef4_nic *efx = tx_queue->efx;
4965a6681e2SEdward Cree struct ef4_tx_queue *txq2;
4975a6681e2SEdward Cree unsigned int pkts_compl = 0, bytes_compl = 0;
4985a6681e2SEdward Cree
4995a6681e2SEdward Cree EF4_BUG_ON_PARANOID(index > tx_queue->ptr_mask);
5005a6681e2SEdward Cree
5015a6681e2SEdward Cree ef4_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl);
5025a6681e2SEdward Cree tx_queue->pkts_compl += pkts_compl;
5035a6681e2SEdward Cree tx_queue->bytes_compl += bytes_compl;
5045a6681e2SEdward Cree
5055a6681e2SEdward Cree if (pkts_compl > 1)
5065a6681e2SEdward Cree ++tx_queue->merge_events;
5075a6681e2SEdward Cree
5085a6681e2SEdward Cree /* See if we need to restart the netif queue. This memory
5095a6681e2SEdward Cree * barrier ensures that we write read_count (inside
5105a6681e2SEdward Cree * ef4_dequeue_buffers()) before reading the queue status.
5115a6681e2SEdward Cree */
5125a6681e2SEdward Cree smp_mb();
5135a6681e2SEdward Cree if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) &&
5145a6681e2SEdward Cree likely(efx->port_enabled) &&
5155a6681e2SEdward Cree likely(netif_device_present(efx->net_dev))) {
5165a6681e2SEdward Cree txq2 = ef4_tx_queue_partner(tx_queue);
5175a6681e2SEdward Cree fill_level = max(tx_queue->insert_count - tx_queue->read_count,
5185a6681e2SEdward Cree txq2->insert_count - txq2->read_count);
5195a6681e2SEdward Cree if (fill_level <= efx->txq_wake_thresh)
5205a6681e2SEdward Cree netif_tx_wake_queue(tx_queue->core_txq);
5215a6681e2SEdward Cree }
5225a6681e2SEdward Cree
5235a6681e2SEdward Cree /* Check whether the hardware queue is now empty */
5245a6681e2SEdward Cree if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) {
5256aa7de05SMark Rutland tx_queue->old_write_count = READ_ONCE(tx_queue->write_count);
5265a6681e2SEdward Cree if (tx_queue->read_count == tx_queue->old_write_count) {
5275a6681e2SEdward Cree smp_mb();
5285a6681e2SEdward Cree tx_queue->empty_read_count =
5295a6681e2SEdward Cree tx_queue->read_count | EF4_EMPTY_COUNT_VALID;
5305a6681e2SEdward Cree }
5315a6681e2SEdward Cree }
5325a6681e2SEdward Cree }
5335a6681e2SEdward Cree
ef4_tx_cb_page_count(struct ef4_tx_queue * tx_queue)5345a6681e2SEdward Cree static unsigned int ef4_tx_cb_page_count(struct ef4_tx_queue *tx_queue)
5355a6681e2SEdward Cree {
5365a6681e2SEdward Cree return DIV_ROUND_UP(tx_queue->ptr_mask + 1, PAGE_SIZE >> EF4_TX_CB_ORDER);
5375a6681e2SEdward Cree }
5385a6681e2SEdward Cree
ef4_probe_tx_queue(struct ef4_tx_queue * tx_queue)5395a6681e2SEdward Cree int ef4_probe_tx_queue(struct ef4_tx_queue *tx_queue)
5405a6681e2SEdward Cree {
5415a6681e2SEdward Cree struct ef4_nic *efx = tx_queue->efx;
5425a6681e2SEdward Cree unsigned int entries;
5435a6681e2SEdward Cree int rc;
5445a6681e2SEdward Cree
5455a6681e2SEdward Cree /* Create the smallest power-of-two aligned ring */
5465a6681e2SEdward Cree entries = max(roundup_pow_of_two(efx->txq_entries), EF4_MIN_DMAQ_SIZE);
5475a6681e2SEdward Cree EF4_BUG_ON_PARANOID(entries > EF4_MAX_DMAQ_SIZE);
5485a6681e2SEdward Cree tx_queue->ptr_mask = entries - 1;
5495a6681e2SEdward Cree
5505a6681e2SEdward Cree netif_dbg(efx, probe, efx->net_dev,
5515a6681e2SEdward Cree "creating TX queue %d size %#x mask %#x\n",
5525a6681e2SEdward Cree tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
5535a6681e2SEdward Cree
5545a6681e2SEdward Cree /* Allocate software ring */
5555a6681e2SEdward Cree tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer),
5565a6681e2SEdward Cree GFP_KERNEL);
5575a6681e2SEdward Cree if (!tx_queue->buffer)
5585a6681e2SEdward Cree return -ENOMEM;
5595a6681e2SEdward Cree
5605a6681e2SEdward Cree tx_queue->cb_page = kcalloc(ef4_tx_cb_page_count(tx_queue),
5615a6681e2SEdward Cree sizeof(tx_queue->cb_page[0]), GFP_KERNEL);
5625a6681e2SEdward Cree if (!tx_queue->cb_page) {
5635a6681e2SEdward Cree rc = -ENOMEM;
5645a6681e2SEdward Cree goto fail1;
5655a6681e2SEdward Cree }
5665a6681e2SEdward Cree
5675a6681e2SEdward Cree /* Allocate hardware ring */
5685a6681e2SEdward Cree rc = ef4_nic_probe_tx(tx_queue);
5695a6681e2SEdward Cree if (rc)
5705a6681e2SEdward Cree goto fail2;
5715a6681e2SEdward Cree
5725a6681e2SEdward Cree return 0;
5735a6681e2SEdward Cree
5745a6681e2SEdward Cree fail2:
5755a6681e2SEdward Cree kfree(tx_queue->cb_page);
5765a6681e2SEdward Cree tx_queue->cb_page = NULL;
5775a6681e2SEdward Cree fail1:
5785a6681e2SEdward Cree kfree(tx_queue->buffer);
5795a6681e2SEdward Cree tx_queue->buffer = NULL;
5805a6681e2SEdward Cree return rc;
5815a6681e2SEdward Cree }
5825a6681e2SEdward Cree
ef4_init_tx_queue(struct ef4_tx_queue * tx_queue)5835a6681e2SEdward Cree void ef4_init_tx_queue(struct ef4_tx_queue *tx_queue)
5845a6681e2SEdward Cree {
5855a6681e2SEdward Cree struct ef4_nic *efx = tx_queue->efx;
5865a6681e2SEdward Cree
5875a6681e2SEdward Cree netif_dbg(efx, drv, efx->net_dev,
5885a6681e2SEdward Cree "initialising TX queue %d\n", tx_queue->queue);
5895a6681e2SEdward Cree
5905a6681e2SEdward Cree tx_queue->insert_count = 0;
5915a6681e2SEdward Cree tx_queue->write_count = 0;
5925a6681e2SEdward Cree tx_queue->old_write_count = 0;
5935a6681e2SEdward Cree tx_queue->read_count = 0;
5945a6681e2SEdward Cree tx_queue->old_read_count = 0;
5955a6681e2SEdward Cree tx_queue->empty_read_count = 0 | EF4_EMPTY_COUNT_VALID;
5965a6681e2SEdward Cree tx_queue->xmit_more_available = false;
5975a6681e2SEdward Cree
5985a6681e2SEdward Cree /* Some older hardware requires Tx writes larger than 32. */
5995a6681e2SEdward Cree tx_queue->tx_min_size = EF4_WORKAROUND_15592(efx) ? 33 : 0;
6005a6681e2SEdward Cree
6015a6681e2SEdward Cree /* Set up TX descriptor ring */
6025a6681e2SEdward Cree ef4_nic_init_tx(tx_queue);
6035a6681e2SEdward Cree
6045a6681e2SEdward Cree tx_queue->initialised = true;
6055a6681e2SEdward Cree }
6065a6681e2SEdward Cree
ef4_fini_tx_queue(struct ef4_tx_queue * tx_queue)6075a6681e2SEdward Cree void ef4_fini_tx_queue(struct ef4_tx_queue *tx_queue)
6085a6681e2SEdward Cree {
6095a6681e2SEdward Cree struct ef4_tx_buffer *buffer;
6105a6681e2SEdward Cree
6115a6681e2SEdward Cree netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
6125a6681e2SEdward Cree "shutting down TX queue %d\n", tx_queue->queue);
6135a6681e2SEdward Cree
6145a6681e2SEdward Cree if (!tx_queue->buffer)
6155a6681e2SEdward Cree return;
6165a6681e2SEdward Cree
6175a6681e2SEdward Cree /* Free any buffers left in the ring */
6185a6681e2SEdward Cree while (tx_queue->read_count != tx_queue->write_count) {
6195a6681e2SEdward Cree unsigned int pkts_compl = 0, bytes_compl = 0;
6205a6681e2SEdward Cree buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
6215a6681e2SEdward Cree ef4_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
6225a6681e2SEdward Cree
6235a6681e2SEdward Cree ++tx_queue->read_count;
6245a6681e2SEdward Cree }
6255a6681e2SEdward Cree tx_queue->xmit_more_available = false;
6265a6681e2SEdward Cree netdev_tx_reset_queue(tx_queue->core_txq);
6275a6681e2SEdward Cree }
6285a6681e2SEdward Cree
ef4_remove_tx_queue(struct ef4_tx_queue * tx_queue)6295a6681e2SEdward Cree void ef4_remove_tx_queue(struct ef4_tx_queue *tx_queue)
6305a6681e2SEdward Cree {
6315a6681e2SEdward Cree int i;
6325a6681e2SEdward Cree
6335a6681e2SEdward Cree if (!tx_queue->buffer)
6345a6681e2SEdward Cree return;
6355a6681e2SEdward Cree
6365a6681e2SEdward Cree netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
6375a6681e2SEdward Cree "destroying TX queue %d\n", tx_queue->queue);
6385a6681e2SEdward Cree ef4_nic_remove_tx(tx_queue);
6395a6681e2SEdward Cree
6405a6681e2SEdward Cree if (tx_queue->cb_page) {
6415a6681e2SEdward Cree for (i = 0; i < ef4_tx_cb_page_count(tx_queue); i++)
6425a6681e2SEdward Cree ef4_nic_free_buffer(tx_queue->efx,
6435a6681e2SEdward Cree &tx_queue->cb_page[i]);
6445a6681e2SEdward Cree kfree(tx_queue->cb_page);
6455a6681e2SEdward Cree tx_queue->cb_page = NULL;
6465a6681e2SEdward Cree }
6475a6681e2SEdward Cree
6485a6681e2SEdward Cree kfree(tx_queue->buffer);
6495a6681e2SEdward Cree tx_queue->buffer = NULL;
6505a6681e2SEdward Cree }
651