1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2006-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #ifndef EF4_NIC_H 12 #define EF4_NIC_H 13 14 #include <linux/net_tstamp.h> 15 #include <linux/i2c-algo-bit.h> 16 #include "net_driver.h" 17 #include "efx.h" 18 19 enum { 20 EF4_REV_FALCON_A0 = 0, 21 EF4_REV_FALCON_A1 = 1, 22 EF4_REV_FALCON_B0 = 2, 23 }; 24 25 static inline int ef4_nic_rev(struct ef4_nic *efx) 26 { 27 return efx->type->revision; 28 } 29 30 u32 ef4_farch_fpga_ver(struct ef4_nic *efx); 31 32 /* NIC has two interlinked PCI functions for the same port. */ 33 static inline bool ef4_nic_is_dual_func(struct ef4_nic *efx) 34 { 35 return ef4_nic_rev(efx) < EF4_REV_FALCON_B0; 36 } 37 38 /* Read the current event from the event queue */ 39 static inline ef4_qword_t *ef4_event(struct ef4_channel *channel, 40 unsigned int index) 41 { 42 return ((ef4_qword_t *) (channel->eventq.buf.addr)) + 43 (index & channel->eventq_mask); 44 } 45 46 /* See if an event is present 47 * 48 * We check both the high and low dword of the event for all ones. We 49 * wrote all ones when we cleared the event, and no valid event can 50 * have all ones in either its high or low dwords. This approach is 51 * robust against reordering. 52 * 53 * Note that using a single 64-bit comparison is incorrect; even 54 * though the CPU read will be atomic, the DMA write may not be. 55 */ 56 static inline int ef4_event_present(ef4_qword_t *event) 57 { 58 return !(EF4_DWORD_IS_ALL_ONES(event->dword[0]) | 59 EF4_DWORD_IS_ALL_ONES(event->dword[1])); 60 } 61 62 /* Returns a pointer to the specified transmit descriptor in the TX 63 * descriptor queue belonging to the specified channel. 64 */ 65 static inline ef4_qword_t * 66 ef4_tx_desc(struct ef4_tx_queue *tx_queue, unsigned int index) 67 { 68 return ((ef4_qword_t *) (tx_queue->txd.buf.addr)) + index; 69 } 70 71 /* Get partner of a TX queue, seen as part of the same net core queue */ 72 static inline struct ef4_tx_queue *ef4_tx_queue_partner(struct ef4_tx_queue *tx_queue) 73 { 74 if (tx_queue->queue & EF4_TXQ_TYPE_OFFLOAD) 75 return tx_queue - EF4_TXQ_TYPE_OFFLOAD; 76 else 77 return tx_queue + EF4_TXQ_TYPE_OFFLOAD; 78 } 79 80 /* Report whether this TX queue would be empty for the given write_count. 81 * May return false negative. 82 */ 83 static inline bool __ef4_nic_tx_is_empty(struct ef4_tx_queue *tx_queue, 84 unsigned int write_count) 85 { 86 unsigned int empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count); 87 88 if (empty_read_count == 0) 89 return false; 90 91 return ((empty_read_count ^ write_count) & ~EF4_EMPTY_COUNT_VALID) == 0; 92 } 93 94 /* Decide whether to push a TX descriptor to the NIC vs merely writing 95 * the doorbell. This can reduce latency when we are adding a single 96 * descriptor to an empty queue, but is otherwise pointless. Further, 97 * Falcon and Siena have hardware bugs (SF bug 33851) that may be 98 * triggered if we don't check this. 99 * We use the write_count used for the last doorbell push, to get the 100 * NIC's view of the tx queue. 101 */ 102 static inline bool ef4_nic_may_push_tx_desc(struct ef4_tx_queue *tx_queue, 103 unsigned int write_count) 104 { 105 bool was_empty = __ef4_nic_tx_is_empty(tx_queue, write_count); 106 107 tx_queue->empty_read_count = 0; 108 return was_empty && tx_queue->write_count - write_count == 1; 109 } 110 111 /* Returns a pointer to the specified descriptor in the RX descriptor queue */ 112 static inline ef4_qword_t * 113 ef4_rx_desc(struct ef4_rx_queue *rx_queue, unsigned int index) 114 { 115 return ((ef4_qword_t *) (rx_queue->rxd.buf.addr)) + index; 116 } 117 118 enum { 119 PHY_TYPE_NONE = 0, 120 PHY_TYPE_TXC43128 = 1, 121 PHY_TYPE_88E1111 = 2, 122 PHY_TYPE_SFX7101 = 3, 123 PHY_TYPE_QT2022C2 = 4, 124 PHY_TYPE_PM8358 = 6, 125 PHY_TYPE_SFT9001A = 8, 126 PHY_TYPE_QT2025C = 9, 127 PHY_TYPE_SFT9001B = 10, 128 }; 129 130 #define FALCON_XMAC_LOOPBACKS \ 131 ((1 << LOOPBACK_XGMII) | \ 132 (1 << LOOPBACK_XGXS) | \ 133 (1 << LOOPBACK_XAUI)) 134 135 /* Alignment of PCIe DMA boundaries (4KB) */ 136 #define EF4_PAGE_SIZE 4096 137 /* Size and alignment of buffer table entries (same) */ 138 #define EF4_BUF_SIZE EF4_PAGE_SIZE 139 140 /* NIC-generic software stats */ 141 enum { 142 GENERIC_STAT_rx_noskb_drops, 143 GENERIC_STAT_rx_nodesc_trunc, 144 GENERIC_STAT_COUNT 145 }; 146 147 /** 148 * struct falcon_board_type - board operations and type information 149 * @id: Board type id, as found in NVRAM 150 * @init: Allocate resources and initialise peripheral hardware 151 * @init_phy: Do board-specific PHY initialisation 152 * @fini: Shut down hardware and free resources 153 * @set_id_led: Set state of identifying LED or revert to automatic function 154 * @monitor: Board-specific health check function 155 */ 156 struct falcon_board_type { 157 u8 id; 158 int (*init) (struct ef4_nic *nic); 159 void (*init_phy) (struct ef4_nic *efx); 160 void (*fini) (struct ef4_nic *nic); 161 void (*set_id_led) (struct ef4_nic *efx, enum ef4_led_mode mode); 162 int (*monitor) (struct ef4_nic *nic); 163 }; 164 165 /** 166 * struct falcon_board - board information 167 * @type: Type of board 168 * @major: Major rev. ('A', 'B' ...) 169 * @minor: Minor rev. (0, 1, ...) 170 * @i2c_adap: I2C adapter for on-board peripherals 171 * @i2c_data: Data for bit-banging algorithm 172 * @hwmon_client: I2C client for hardware monitor 173 * @ioexp_client: I2C client for power/port control 174 */ 175 struct falcon_board { 176 const struct falcon_board_type *type; 177 int major; 178 int minor; 179 struct i2c_adapter i2c_adap; 180 struct i2c_algo_bit_data i2c_data; 181 struct i2c_client *hwmon_client, *ioexp_client; 182 }; 183 184 /** 185 * struct falcon_spi_device - a Falcon SPI (Serial Peripheral Interface) device 186 * @device_id: Controller's id for the device 187 * @size: Size (in bytes) 188 * @addr_len: Number of address bytes in read/write commands 189 * @munge_address: Flag whether addresses should be munged. 190 * Some devices with 9-bit addresses (e.g. AT25040A EEPROM) 191 * use bit 3 of the command byte as address bit A8, rather 192 * than having a two-byte address. If this flag is set, then 193 * commands should be munged in this way. 194 * @erase_command: Erase command (or 0 if sector erase not needed). 195 * @erase_size: Erase sector size (in bytes) 196 * Erase commands affect sectors with this size and alignment. 197 * This must be a power of two. 198 * @block_size: Write block size (in bytes). 199 * Write commands are limited to blocks with this size and alignment. 200 */ 201 struct falcon_spi_device { 202 int device_id; 203 unsigned int size; 204 unsigned int addr_len; 205 unsigned int munge_address:1; 206 u8 erase_command; 207 unsigned int erase_size; 208 unsigned int block_size; 209 }; 210 211 static inline bool falcon_spi_present(const struct falcon_spi_device *spi) 212 { 213 return spi->size != 0; 214 } 215 216 enum { 217 FALCON_STAT_tx_bytes = GENERIC_STAT_COUNT, 218 FALCON_STAT_tx_packets, 219 FALCON_STAT_tx_pause, 220 FALCON_STAT_tx_control, 221 FALCON_STAT_tx_unicast, 222 FALCON_STAT_tx_multicast, 223 FALCON_STAT_tx_broadcast, 224 FALCON_STAT_tx_lt64, 225 FALCON_STAT_tx_64, 226 FALCON_STAT_tx_65_to_127, 227 FALCON_STAT_tx_128_to_255, 228 FALCON_STAT_tx_256_to_511, 229 FALCON_STAT_tx_512_to_1023, 230 FALCON_STAT_tx_1024_to_15xx, 231 FALCON_STAT_tx_15xx_to_jumbo, 232 FALCON_STAT_tx_gtjumbo, 233 FALCON_STAT_tx_non_tcpudp, 234 FALCON_STAT_tx_mac_src_error, 235 FALCON_STAT_tx_ip_src_error, 236 FALCON_STAT_rx_bytes, 237 FALCON_STAT_rx_good_bytes, 238 FALCON_STAT_rx_bad_bytes, 239 FALCON_STAT_rx_packets, 240 FALCON_STAT_rx_good, 241 FALCON_STAT_rx_bad, 242 FALCON_STAT_rx_pause, 243 FALCON_STAT_rx_control, 244 FALCON_STAT_rx_unicast, 245 FALCON_STAT_rx_multicast, 246 FALCON_STAT_rx_broadcast, 247 FALCON_STAT_rx_lt64, 248 FALCON_STAT_rx_64, 249 FALCON_STAT_rx_65_to_127, 250 FALCON_STAT_rx_128_to_255, 251 FALCON_STAT_rx_256_to_511, 252 FALCON_STAT_rx_512_to_1023, 253 FALCON_STAT_rx_1024_to_15xx, 254 FALCON_STAT_rx_15xx_to_jumbo, 255 FALCON_STAT_rx_gtjumbo, 256 FALCON_STAT_rx_bad_lt64, 257 FALCON_STAT_rx_bad_gtjumbo, 258 FALCON_STAT_rx_overflow, 259 FALCON_STAT_rx_symbol_error, 260 FALCON_STAT_rx_align_error, 261 FALCON_STAT_rx_length_error, 262 FALCON_STAT_rx_internal_error, 263 FALCON_STAT_rx_nodesc_drop_cnt, 264 FALCON_STAT_COUNT 265 }; 266 267 /** 268 * struct falcon_nic_data - Falcon NIC state 269 * @pci_dev2: Secondary function of Falcon A 270 * @board: Board state and functions 271 * @stats: Hardware statistics 272 * @stats_disable_count: Nest count for disabling statistics fetches 273 * @stats_pending: Is there a pending DMA of MAC statistics. 274 * @stats_timer: A timer for regularly fetching MAC statistics. 275 * @spi_flash: SPI flash device 276 * @spi_eeprom: SPI EEPROM device 277 * @spi_lock: SPI bus lock 278 * @mdio_lock: MDIO bus lock 279 * @xmac_poll_required: XMAC link state needs polling 280 */ 281 struct falcon_nic_data { 282 struct pci_dev *pci_dev2; 283 struct falcon_board board; 284 u64 stats[FALCON_STAT_COUNT]; 285 unsigned int stats_disable_count; 286 bool stats_pending; 287 struct timer_list stats_timer; 288 struct falcon_spi_device spi_flash; 289 struct falcon_spi_device spi_eeprom; 290 struct mutex spi_lock; 291 struct mutex mdio_lock; 292 bool xmac_poll_required; 293 }; 294 295 static inline struct falcon_board *falcon_board(struct ef4_nic *efx) 296 { 297 struct falcon_nic_data *data = efx->nic_data; 298 return &data->board; 299 } 300 301 struct ethtool_ts_info; 302 303 extern const struct ef4_nic_type falcon_a1_nic_type; 304 extern const struct ef4_nic_type falcon_b0_nic_type; 305 306 /************************************************************************** 307 * 308 * Externs 309 * 310 ************************************************************************** 311 */ 312 313 int falcon_probe_board(struct ef4_nic *efx, u16 revision_info); 314 315 /* TX data path */ 316 static inline int ef4_nic_probe_tx(struct ef4_tx_queue *tx_queue) 317 { 318 return tx_queue->efx->type->tx_probe(tx_queue); 319 } 320 static inline void ef4_nic_init_tx(struct ef4_tx_queue *tx_queue) 321 { 322 tx_queue->efx->type->tx_init(tx_queue); 323 } 324 static inline void ef4_nic_remove_tx(struct ef4_tx_queue *tx_queue) 325 { 326 tx_queue->efx->type->tx_remove(tx_queue); 327 } 328 static inline void ef4_nic_push_buffers(struct ef4_tx_queue *tx_queue) 329 { 330 tx_queue->efx->type->tx_write(tx_queue); 331 } 332 333 /* RX data path */ 334 static inline int ef4_nic_probe_rx(struct ef4_rx_queue *rx_queue) 335 { 336 return rx_queue->efx->type->rx_probe(rx_queue); 337 } 338 static inline void ef4_nic_init_rx(struct ef4_rx_queue *rx_queue) 339 { 340 rx_queue->efx->type->rx_init(rx_queue); 341 } 342 static inline void ef4_nic_remove_rx(struct ef4_rx_queue *rx_queue) 343 { 344 rx_queue->efx->type->rx_remove(rx_queue); 345 } 346 static inline void ef4_nic_notify_rx_desc(struct ef4_rx_queue *rx_queue) 347 { 348 rx_queue->efx->type->rx_write(rx_queue); 349 } 350 static inline void ef4_nic_generate_fill_event(struct ef4_rx_queue *rx_queue) 351 { 352 rx_queue->efx->type->rx_defer_refill(rx_queue); 353 } 354 355 /* Event data path */ 356 static inline int ef4_nic_probe_eventq(struct ef4_channel *channel) 357 { 358 return channel->efx->type->ev_probe(channel); 359 } 360 static inline int ef4_nic_init_eventq(struct ef4_channel *channel) 361 { 362 return channel->efx->type->ev_init(channel); 363 } 364 static inline void ef4_nic_fini_eventq(struct ef4_channel *channel) 365 { 366 channel->efx->type->ev_fini(channel); 367 } 368 static inline void ef4_nic_remove_eventq(struct ef4_channel *channel) 369 { 370 channel->efx->type->ev_remove(channel); 371 } 372 static inline int 373 ef4_nic_process_eventq(struct ef4_channel *channel, int quota) 374 { 375 return channel->efx->type->ev_process(channel, quota); 376 } 377 static inline void ef4_nic_eventq_read_ack(struct ef4_channel *channel) 378 { 379 channel->efx->type->ev_read_ack(channel); 380 } 381 void ef4_nic_event_test_start(struct ef4_channel *channel); 382 383 /* queue operations */ 384 int ef4_farch_tx_probe(struct ef4_tx_queue *tx_queue); 385 void ef4_farch_tx_init(struct ef4_tx_queue *tx_queue); 386 void ef4_farch_tx_fini(struct ef4_tx_queue *tx_queue); 387 void ef4_farch_tx_remove(struct ef4_tx_queue *tx_queue); 388 void ef4_farch_tx_write(struct ef4_tx_queue *tx_queue); 389 unsigned int ef4_farch_tx_limit_len(struct ef4_tx_queue *tx_queue, 390 dma_addr_t dma_addr, unsigned int len); 391 int ef4_farch_rx_probe(struct ef4_rx_queue *rx_queue); 392 void ef4_farch_rx_init(struct ef4_rx_queue *rx_queue); 393 void ef4_farch_rx_fini(struct ef4_rx_queue *rx_queue); 394 void ef4_farch_rx_remove(struct ef4_rx_queue *rx_queue); 395 void ef4_farch_rx_write(struct ef4_rx_queue *rx_queue); 396 void ef4_farch_rx_defer_refill(struct ef4_rx_queue *rx_queue); 397 int ef4_farch_ev_probe(struct ef4_channel *channel); 398 int ef4_farch_ev_init(struct ef4_channel *channel); 399 void ef4_farch_ev_fini(struct ef4_channel *channel); 400 void ef4_farch_ev_remove(struct ef4_channel *channel); 401 int ef4_farch_ev_process(struct ef4_channel *channel, int quota); 402 void ef4_farch_ev_read_ack(struct ef4_channel *channel); 403 void ef4_farch_ev_test_generate(struct ef4_channel *channel); 404 405 /* filter operations */ 406 int ef4_farch_filter_table_probe(struct ef4_nic *efx); 407 void ef4_farch_filter_table_restore(struct ef4_nic *efx); 408 void ef4_farch_filter_table_remove(struct ef4_nic *efx); 409 void ef4_farch_filter_update_rx_scatter(struct ef4_nic *efx); 410 s32 ef4_farch_filter_insert(struct ef4_nic *efx, struct ef4_filter_spec *spec, 411 bool replace); 412 int ef4_farch_filter_remove_safe(struct ef4_nic *efx, 413 enum ef4_filter_priority priority, 414 u32 filter_id); 415 int ef4_farch_filter_get_safe(struct ef4_nic *efx, 416 enum ef4_filter_priority priority, u32 filter_id, 417 struct ef4_filter_spec *); 418 int ef4_farch_filter_clear_rx(struct ef4_nic *efx, 419 enum ef4_filter_priority priority); 420 u32 ef4_farch_filter_count_rx_used(struct ef4_nic *efx, 421 enum ef4_filter_priority priority); 422 u32 ef4_farch_filter_get_rx_id_limit(struct ef4_nic *efx); 423 s32 ef4_farch_filter_get_rx_ids(struct ef4_nic *efx, 424 enum ef4_filter_priority priority, u32 *buf, 425 u32 size); 426 #ifdef CONFIG_RFS_ACCEL 427 s32 ef4_farch_filter_rfs_insert(struct ef4_nic *efx, 428 struct ef4_filter_spec *spec); 429 bool ef4_farch_filter_rfs_expire_one(struct ef4_nic *efx, u32 flow_id, 430 unsigned int index); 431 #endif 432 void ef4_farch_filter_sync_rx_mode(struct ef4_nic *efx); 433 434 bool ef4_nic_event_present(struct ef4_channel *channel); 435 436 /* Some statistics are computed as A - B where A and B each increase 437 * linearly with some hardware counter(s) and the counters are read 438 * asynchronously. If the counters contributing to B are always read 439 * after those contributing to A, the computed value may be lower than 440 * the true value by some variable amount, and may decrease between 441 * subsequent computations. 442 * 443 * We should never allow statistics to decrease or to exceed the true 444 * value. Since the computed value will never be greater than the 445 * true value, we can achieve this by only storing the computed value 446 * when it increases. 447 */ 448 static inline void ef4_update_diff_stat(u64 *stat, u64 diff) 449 { 450 if ((s64)(diff - *stat) > 0) 451 *stat = diff; 452 } 453 454 /* Interrupts */ 455 int ef4_nic_init_interrupt(struct ef4_nic *efx); 456 int ef4_nic_irq_test_start(struct ef4_nic *efx); 457 void ef4_nic_fini_interrupt(struct ef4_nic *efx); 458 void ef4_farch_irq_enable_master(struct ef4_nic *efx); 459 int ef4_farch_irq_test_generate(struct ef4_nic *efx); 460 void ef4_farch_irq_disable_master(struct ef4_nic *efx); 461 irqreturn_t ef4_farch_msi_interrupt(int irq, void *dev_id); 462 irqreturn_t ef4_farch_legacy_interrupt(int irq, void *dev_id); 463 irqreturn_t ef4_farch_fatal_interrupt(struct ef4_nic *efx); 464 465 static inline int ef4_nic_event_test_irq_cpu(struct ef4_channel *channel) 466 { 467 return ACCESS_ONCE(channel->event_test_cpu); 468 } 469 static inline int ef4_nic_irq_test_irq_cpu(struct ef4_nic *efx) 470 { 471 return ACCESS_ONCE(efx->last_irq_cpu); 472 } 473 474 /* Global Resources */ 475 int ef4_nic_flush_queues(struct ef4_nic *efx); 476 int ef4_farch_fini_dmaq(struct ef4_nic *efx); 477 void ef4_farch_finish_flr(struct ef4_nic *efx); 478 void falcon_start_nic_stats(struct ef4_nic *efx); 479 void falcon_stop_nic_stats(struct ef4_nic *efx); 480 int falcon_reset_xaui(struct ef4_nic *efx); 481 void ef4_farch_dimension_resources(struct ef4_nic *efx, unsigned sram_lim_qw); 482 void ef4_farch_init_common(struct ef4_nic *efx); 483 void ef4_farch_rx_push_indir_table(struct ef4_nic *efx); 484 485 int ef4_nic_alloc_buffer(struct ef4_nic *efx, struct ef4_buffer *buffer, 486 unsigned int len, gfp_t gfp_flags); 487 void ef4_nic_free_buffer(struct ef4_nic *efx, struct ef4_buffer *buffer); 488 489 /* Tests */ 490 struct ef4_farch_register_test { 491 unsigned address; 492 ef4_oword_t mask; 493 }; 494 int ef4_farch_test_registers(struct ef4_nic *efx, 495 const struct ef4_farch_register_test *regs, 496 size_t n_regs); 497 498 size_t ef4_nic_get_regs_len(struct ef4_nic *efx); 499 void ef4_nic_get_regs(struct ef4_nic *efx, void *buf); 500 501 size_t ef4_nic_describe_stats(const struct ef4_hw_stat_desc *desc, size_t count, 502 const unsigned long *mask, u8 *names); 503 void ef4_nic_update_stats(const struct ef4_hw_stat_desc *desc, size_t count, 504 const unsigned long *mask, u64 *stats, 505 const void *dma_buf, bool accumulate); 506 void ef4_nic_fix_nodesc_drop_stat(struct ef4_nic *efx, u64 *stat); 507 508 #define EF4_MAX_FLUSH_TIME 5000 509 510 void ef4_farch_generate_event(struct ef4_nic *efx, unsigned int evq, 511 ef4_qword_t *event); 512 513 #endif /* EF4_NIC_H */ 514