1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
25a6681e2SEdward Cree /****************************************************************************
35a6681e2SEdward Cree  * Driver for Solarflare network controllers and boards
45a6681e2SEdward Cree  * Copyright 2006-2011 Solarflare Communications Inc.
55a6681e2SEdward Cree  */
65a6681e2SEdward Cree 
75a6681e2SEdward Cree #ifndef EF4_MDIO_10G_H
85a6681e2SEdward Cree #define EF4_MDIO_10G_H
95a6681e2SEdward Cree 
105a6681e2SEdward Cree #include <linux/mdio.h>
115a6681e2SEdward Cree 
125a6681e2SEdward Cree /*
135a6681e2SEdward Cree  * Helper functions for doing 10G MDIO as specified in IEEE 802.3 clause 45.
145a6681e2SEdward Cree  */
155a6681e2SEdward Cree 
165a6681e2SEdward Cree #include "efx.h"
175a6681e2SEdward Cree 
ef4_mdio_id_rev(u32 id)185a6681e2SEdward Cree static inline unsigned ef4_mdio_id_rev(u32 id) { return id & 0xf; }
ef4_mdio_id_model(u32 id)195a6681e2SEdward Cree static inline unsigned ef4_mdio_id_model(u32 id) { return (id >> 4) & 0x3f; }
205a6681e2SEdward Cree unsigned ef4_mdio_id_oui(u32 id);
215a6681e2SEdward Cree 
ef4_mdio_read(struct ef4_nic * efx,int devad,int addr)225a6681e2SEdward Cree static inline int ef4_mdio_read(struct ef4_nic *efx, int devad, int addr)
235a6681e2SEdward Cree {
245a6681e2SEdward Cree 	return efx->mdio.mdio_read(efx->net_dev, efx->mdio.prtad, devad, addr);
255a6681e2SEdward Cree }
265a6681e2SEdward Cree 
275a6681e2SEdward Cree static inline void
ef4_mdio_write(struct ef4_nic * efx,int devad,int addr,int value)285a6681e2SEdward Cree ef4_mdio_write(struct ef4_nic *efx, int devad, int addr, int value)
295a6681e2SEdward Cree {
305a6681e2SEdward Cree 	efx->mdio.mdio_write(efx->net_dev, efx->mdio.prtad, devad, addr, value);
315a6681e2SEdward Cree }
325a6681e2SEdward Cree 
ef4_mdio_read_id(struct ef4_nic * efx,int mmd)335a6681e2SEdward Cree static inline u32 ef4_mdio_read_id(struct ef4_nic *efx, int mmd)
345a6681e2SEdward Cree {
355a6681e2SEdward Cree 	u16 id_low = ef4_mdio_read(efx, mmd, MDIO_DEVID2);
365a6681e2SEdward Cree 	u16 id_hi = ef4_mdio_read(efx, mmd, MDIO_DEVID1);
375a6681e2SEdward Cree 	return (id_hi << 16) | (id_low);
385a6681e2SEdward Cree }
395a6681e2SEdward Cree 
ef4_mdio_phyxgxs_lane_sync(struct ef4_nic * efx)405a6681e2SEdward Cree static inline bool ef4_mdio_phyxgxs_lane_sync(struct ef4_nic *efx)
415a6681e2SEdward Cree {
425a6681e2SEdward Cree 	int i, lane_status;
435a6681e2SEdward Cree 	bool sync;
445a6681e2SEdward Cree 
455a6681e2SEdward Cree 	for (i = 0; i < 2; ++i)
465a6681e2SEdward Cree 		lane_status = ef4_mdio_read(efx, MDIO_MMD_PHYXS,
475a6681e2SEdward Cree 					    MDIO_PHYXS_LNSTAT);
485a6681e2SEdward Cree 
495a6681e2SEdward Cree 	sync = !!(lane_status & MDIO_PHYXS_LNSTAT_ALIGN);
505a6681e2SEdward Cree 	if (!sync)
515a6681e2SEdward Cree 		netif_dbg(efx, hw, efx->net_dev, "XGXS lane status: %x\n",
525a6681e2SEdward Cree 			  lane_status);
535a6681e2SEdward Cree 	return sync;
545a6681e2SEdward Cree }
555a6681e2SEdward Cree 
565a6681e2SEdward Cree const char *ef4_mdio_mmd_name(int mmd);
575a6681e2SEdward Cree 
585a6681e2SEdward Cree /*
595a6681e2SEdward Cree  * Reset a specific MMD and wait for reset to clear.
605a6681e2SEdward Cree  * Return number of spins left (>0) on success, -%ETIMEDOUT on failure.
615a6681e2SEdward Cree  *
625a6681e2SEdward Cree  * This function will sleep
635a6681e2SEdward Cree  */
645a6681e2SEdward Cree int ef4_mdio_reset_mmd(struct ef4_nic *efx, int mmd, int spins, int spintime);
655a6681e2SEdward Cree 
665a6681e2SEdward Cree /* As ef4_mdio_check_mmd but for multiple MMDs */
675a6681e2SEdward Cree int ef4_mdio_check_mmds(struct ef4_nic *efx, unsigned int mmd_mask);
685a6681e2SEdward Cree 
695a6681e2SEdward Cree /* Check the link status of specified mmds in bit mask */
705a6681e2SEdward Cree bool ef4_mdio_links_ok(struct ef4_nic *efx, unsigned int mmd_mask);
715a6681e2SEdward Cree 
725a6681e2SEdward Cree /* Generic transmit disable support though PMAPMD */
735a6681e2SEdward Cree void ef4_mdio_transmit_disable(struct ef4_nic *efx);
745a6681e2SEdward Cree 
755a6681e2SEdward Cree /* Generic part of reconfigure: set/clear loopback bits */
765a6681e2SEdward Cree void ef4_mdio_phy_reconfigure(struct ef4_nic *efx);
775a6681e2SEdward Cree 
785a6681e2SEdward Cree /* Set the power state of the specified MMDs */
795a6681e2SEdward Cree void ef4_mdio_set_mmds_lpower(struct ef4_nic *efx, int low_power,
805a6681e2SEdward Cree 			      unsigned int mmd_mask);
815a6681e2SEdward Cree 
825a6681e2SEdward Cree /* Set (some of) the PHY settings over MDIO */
83e938ed15SPhilippe Reynes int ef4_mdio_set_link_ksettings(struct ef4_nic *efx,
84e938ed15SPhilippe Reynes 				const struct ethtool_link_ksettings *cmd);
855a6681e2SEdward Cree 
865a6681e2SEdward Cree /* Push advertising flags and restart autonegotiation */
875a6681e2SEdward Cree void ef4_mdio_an_reconfigure(struct ef4_nic *efx);
885a6681e2SEdward Cree 
895a6681e2SEdward Cree /* Get pause parameters from AN if available (otherwise return
905a6681e2SEdward Cree  * requested pause parameters)
915a6681e2SEdward Cree  */
925a6681e2SEdward Cree u8 ef4_mdio_get_pause(struct ef4_nic *efx);
935a6681e2SEdward Cree 
945a6681e2SEdward Cree /* Wait for specified MMDs to exit reset within a timeout */
955a6681e2SEdward Cree int ef4_mdio_wait_reset_mmds(struct ef4_nic *efx, unsigned int mmd_mask);
965a6681e2SEdward Cree 
975a6681e2SEdward Cree /* Set or clear flag, debouncing */
985a6681e2SEdward Cree static inline void
ef4_mdio_set_flag(struct ef4_nic * efx,int devad,int addr,int mask,bool state)995a6681e2SEdward Cree ef4_mdio_set_flag(struct ef4_nic *efx, int devad, int addr,
1005a6681e2SEdward Cree 		  int mask, bool state)
1015a6681e2SEdward Cree {
1025a6681e2SEdward Cree 	mdio_set_flag(&efx->mdio, efx->mdio.prtad, devad, addr, mask, state);
1035a6681e2SEdward Cree }
1045a6681e2SEdward Cree 
1055a6681e2SEdward Cree /* Liveness self-test for MDIO PHYs */
1065a6681e2SEdward Cree int ef4_mdio_test_alive(struct ef4_nic *efx);
1075a6681e2SEdward Cree 
1085a6681e2SEdward Cree #endif /* EF4_MDIO_10G_H */
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