15a6681e2SEdward Cree /**************************************************************************** 25a6681e2SEdward Cree * Driver for Solarflare network controllers and boards 35a6681e2SEdward Cree * Copyright 2006-2011 Solarflare Communications Inc. 45a6681e2SEdward Cree * 55a6681e2SEdward Cree * This program is free software; you can redistribute it and/or modify it 65a6681e2SEdward Cree * under the terms of the GNU General Public License version 2 as published 75a6681e2SEdward Cree * by the Free Software Foundation, incorporated herein by reference. 85a6681e2SEdward Cree */ 95a6681e2SEdward Cree /* 105a6681e2SEdward Cree * Useful functions for working with MDIO clause 45 PHYs 115a6681e2SEdward Cree */ 125a6681e2SEdward Cree #include <linux/types.h> 135a6681e2SEdward Cree #include <linux/ethtool.h> 145a6681e2SEdward Cree #include <linux/delay.h> 155a6681e2SEdward Cree #include "net_driver.h" 165a6681e2SEdward Cree #include "mdio_10g.h" 175a6681e2SEdward Cree #include "workarounds.h" 185a6681e2SEdward Cree 195a6681e2SEdward Cree unsigned ef4_mdio_id_oui(u32 id) 205a6681e2SEdward Cree { 215a6681e2SEdward Cree unsigned oui = 0; 225a6681e2SEdward Cree int i; 235a6681e2SEdward Cree 245a6681e2SEdward Cree /* The bits of the OUI are designated a..x, with a=0 and b variable. 255a6681e2SEdward Cree * In the id register c is the MSB but the OUI is conventionally 265a6681e2SEdward Cree * written as bytes h..a, p..i, x..q. Reorder the bits accordingly. */ 275a6681e2SEdward Cree for (i = 0; i < 22; ++i) 285a6681e2SEdward Cree if (id & (1 << (i + 10))) 295a6681e2SEdward Cree oui |= 1 << (i ^ 7); 305a6681e2SEdward Cree 315a6681e2SEdward Cree return oui; 325a6681e2SEdward Cree } 335a6681e2SEdward Cree 345a6681e2SEdward Cree int ef4_mdio_reset_mmd(struct ef4_nic *port, int mmd, 355a6681e2SEdward Cree int spins, int spintime) 365a6681e2SEdward Cree { 375a6681e2SEdward Cree u32 ctrl; 385a6681e2SEdward Cree 395a6681e2SEdward Cree /* Catch callers passing values in the wrong units (or just silly) */ 405a6681e2SEdward Cree EF4_BUG_ON_PARANOID(spins * spintime >= 5000); 415a6681e2SEdward Cree 425a6681e2SEdward Cree ef4_mdio_write(port, mmd, MDIO_CTRL1, MDIO_CTRL1_RESET); 435a6681e2SEdward Cree /* Wait for the reset bit to clear. */ 445a6681e2SEdward Cree do { 455a6681e2SEdward Cree msleep(spintime); 465a6681e2SEdward Cree ctrl = ef4_mdio_read(port, mmd, MDIO_CTRL1); 475a6681e2SEdward Cree spins--; 485a6681e2SEdward Cree 495a6681e2SEdward Cree } while (spins && (ctrl & MDIO_CTRL1_RESET)); 505a6681e2SEdward Cree 515a6681e2SEdward Cree return spins ? spins : -ETIMEDOUT; 525a6681e2SEdward Cree } 535a6681e2SEdward Cree 545a6681e2SEdward Cree static int ef4_mdio_check_mmd(struct ef4_nic *efx, int mmd) 555a6681e2SEdward Cree { 565a6681e2SEdward Cree int status; 575a6681e2SEdward Cree 585a6681e2SEdward Cree if (mmd != MDIO_MMD_AN) { 595a6681e2SEdward Cree /* Read MMD STATUS2 to check it is responding. */ 605a6681e2SEdward Cree status = ef4_mdio_read(efx, mmd, MDIO_STAT2); 615a6681e2SEdward Cree if ((status & MDIO_STAT2_DEVPRST) != MDIO_STAT2_DEVPRST_VAL) { 625a6681e2SEdward Cree netif_err(efx, hw, efx->net_dev, 635a6681e2SEdward Cree "PHY MMD %d not responding.\n", mmd); 645a6681e2SEdward Cree return -EIO; 655a6681e2SEdward Cree } 665a6681e2SEdward Cree } 675a6681e2SEdward Cree 685a6681e2SEdward Cree return 0; 695a6681e2SEdward Cree } 705a6681e2SEdward Cree 715a6681e2SEdward Cree /* This ought to be ridiculous overkill. We expect it to fail rarely */ 725a6681e2SEdward Cree #define MDIO45_RESET_TIME 1000 /* ms */ 735a6681e2SEdward Cree #define MDIO45_RESET_ITERS 100 745a6681e2SEdward Cree 755a6681e2SEdward Cree int ef4_mdio_wait_reset_mmds(struct ef4_nic *efx, unsigned int mmd_mask) 765a6681e2SEdward Cree { 775a6681e2SEdward Cree const int spintime = MDIO45_RESET_TIME / MDIO45_RESET_ITERS; 785a6681e2SEdward Cree int tries = MDIO45_RESET_ITERS; 795a6681e2SEdward Cree int rc = 0; 805a6681e2SEdward Cree int in_reset; 815a6681e2SEdward Cree 825a6681e2SEdward Cree while (tries) { 835a6681e2SEdward Cree int mask = mmd_mask; 845a6681e2SEdward Cree int mmd = 0; 855a6681e2SEdward Cree int stat; 865a6681e2SEdward Cree in_reset = 0; 875a6681e2SEdward Cree while (mask) { 885a6681e2SEdward Cree if (mask & 1) { 895a6681e2SEdward Cree stat = ef4_mdio_read(efx, mmd, MDIO_CTRL1); 905a6681e2SEdward Cree if (stat < 0) { 915a6681e2SEdward Cree netif_err(efx, hw, efx->net_dev, 925a6681e2SEdward Cree "failed to read status of" 935a6681e2SEdward Cree " MMD %d\n", mmd); 945a6681e2SEdward Cree return -EIO; 955a6681e2SEdward Cree } 965a6681e2SEdward Cree if (stat & MDIO_CTRL1_RESET) 975a6681e2SEdward Cree in_reset |= (1 << mmd); 985a6681e2SEdward Cree } 995a6681e2SEdward Cree mask = mask >> 1; 1005a6681e2SEdward Cree mmd++; 1015a6681e2SEdward Cree } 1025a6681e2SEdward Cree if (!in_reset) 1035a6681e2SEdward Cree break; 1045a6681e2SEdward Cree tries--; 1055a6681e2SEdward Cree msleep(spintime); 1065a6681e2SEdward Cree } 1075a6681e2SEdward Cree if (in_reset != 0) { 1085a6681e2SEdward Cree netif_err(efx, hw, efx->net_dev, 1095a6681e2SEdward Cree "not all MMDs came out of reset in time." 1105a6681e2SEdward Cree " MMDs still in reset: %x\n", in_reset); 1115a6681e2SEdward Cree rc = -ETIMEDOUT; 1125a6681e2SEdward Cree } 1135a6681e2SEdward Cree return rc; 1145a6681e2SEdward Cree } 1155a6681e2SEdward Cree 1165a6681e2SEdward Cree int ef4_mdio_check_mmds(struct ef4_nic *efx, unsigned int mmd_mask) 1175a6681e2SEdward Cree { 1185a6681e2SEdward Cree int mmd = 0, probe_mmd, devs1, devs2; 1195a6681e2SEdward Cree u32 devices; 1205a6681e2SEdward Cree 1215a6681e2SEdward Cree /* Historically we have probed the PHYXS to find out what devices are 1225a6681e2SEdward Cree * present,but that doesn't work so well if the PHYXS isn't expected 1235a6681e2SEdward Cree * to exist, if so just find the first item in the list supplied. */ 1245a6681e2SEdward Cree probe_mmd = (mmd_mask & MDIO_DEVS_PHYXS) ? MDIO_MMD_PHYXS : 1255a6681e2SEdward Cree __ffs(mmd_mask); 1265a6681e2SEdward Cree 1275a6681e2SEdward Cree /* Check all the expected MMDs are present */ 1285a6681e2SEdward Cree devs1 = ef4_mdio_read(efx, probe_mmd, MDIO_DEVS1); 1295a6681e2SEdward Cree devs2 = ef4_mdio_read(efx, probe_mmd, MDIO_DEVS2); 1305a6681e2SEdward Cree if (devs1 < 0 || devs2 < 0) { 1315a6681e2SEdward Cree netif_err(efx, hw, efx->net_dev, 1325a6681e2SEdward Cree "failed to read devices present\n"); 1335a6681e2SEdward Cree return -EIO; 1345a6681e2SEdward Cree } 1355a6681e2SEdward Cree devices = devs1 | (devs2 << 16); 1365a6681e2SEdward Cree if ((devices & mmd_mask) != mmd_mask) { 1375a6681e2SEdward Cree netif_err(efx, hw, efx->net_dev, 1385a6681e2SEdward Cree "required MMDs not present: got %x, wanted %x\n", 1395a6681e2SEdward Cree devices, mmd_mask); 1405a6681e2SEdward Cree return -ENODEV; 1415a6681e2SEdward Cree } 1425a6681e2SEdward Cree netif_vdbg(efx, hw, efx->net_dev, "Devices present: %x\n", devices); 1435a6681e2SEdward Cree 1445a6681e2SEdward Cree /* Check all required MMDs are responding and happy. */ 1455a6681e2SEdward Cree while (mmd_mask) { 1465a6681e2SEdward Cree if ((mmd_mask & 1) && ef4_mdio_check_mmd(efx, mmd)) 1475a6681e2SEdward Cree return -EIO; 1485a6681e2SEdward Cree mmd_mask = mmd_mask >> 1; 1495a6681e2SEdward Cree mmd++; 1505a6681e2SEdward Cree } 1515a6681e2SEdward Cree 1525a6681e2SEdward Cree return 0; 1535a6681e2SEdward Cree } 1545a6681e2SEdward Cree 1555a6681e2SEdward Cree bool ef4_mdio_links_ok(struct ef4_nic *efx, unsigned int mmd_mask) 1565a6681e2SEdward Cree { 1575a6681e2SEdward Cree /* If the port is in loopback, then we should only consider a subset 1585a6681e2SEdward Cree * of mmd's */ 1595a6681e2SEdward Cree if (LOOPBACK_INTERNAL(efx)) 1605a6681e2SEdward Cree return true; 1615a6681e2SEdward Cree else if (LOOPBACK_MASK(efx) & LOOPBACKS_WS) 1625a6681e2SEdward Cree return false; 1635a6681e2SEdward Cree else if (ef4_phy_mode_disabled(efx->phy_mode)) 1645a6681e2SEdward Cree return false; 1655a6681e2SEdward Cree else if (efx->loopback_mode == LOOPBACK_PHYXS) 1665a6681e2SEdward Cree mmd_mask &= ~(MDIO_DEVS_PHYXS | 1675a6681e2SEdward Cree MDIO_DEVS_PCS | 1685a6681e2SEdward Cree MDIO_DEVS_PMAPMD | 1695a6681e2SEdward Cree MDIO_DEVS_AN); 1705a6681e2SEdward Cree else if (efx->loopback_mode == LOOPBACK_PCS) 1715a6681e2SEdward Cree mmd_mask &= ~(MDIO_DEVS_PCS | 1725a6681e2SEdward Cree MDIO_DEVS_PMAPMD | 1735a6681e2SEdward Cree MDIO_DEVS_AN); 1745a6681e2SEdward Cree else if (efx->loopback_mode == LOOPBACK_PMAPMD) 1755a6681e2SEdward Cree mmd_mask &= ~(MDIO_DEVS_PMAPMD | 1765a6681e2SEdward Cree MDIO_DEVS_AN); 1775a6681e2SEdward Cree 1785a6681e2SEdward Cree return mdio45_links_ok(&efx->mdio, mmd_mask); 1795a6681e2SEdward Cree } 1805a6681e2SEdward Cree 1815a6681e2SEdward Cree void ef4_mdio_transmit_disable(struct ef4_nic *efx) 1825a6681e2SEdward Cree { 1835a6681e2SEdward Cree ef4_mdio_set_flag(efx, MDIO_MMD_PMAPMD, 1845a6681e2SEdward Cree MDIO_PMA_TXDIS, MDIO_PMD_TXDIS_GLOBAL, 1855a6681e2SEdward Cree efx->phy_mode & PHY_MODE_TX_DISABLED); 1865a6681e2SEdward Cree } 1875a6681e2SEdward Cree 1885a6681e2SEdward Cree void ef4_mdio_phy_reconfigure(struct ef4_nic *efx) 1895a6681e2SEdward Cree { 1905a6681e2SEdward Cree ef4_mdio_set_flag(efx, MDIO_MMD_PMAPMD, 1915a6681e2SEdward Cree MDIO_CTRL1, MDIO_PMA_CTRL1_LOOPBACK, 1925a6681e2SEdward Cree efx->loopback_mode == LOOPBACK_PMAPMD); 1935a6681e2SEdward Cree ef4_mdio_set_flag(efx, MDIO_MMD_PCS, 1945a6681e2SEdward Cree MDIO_CTRL1, MDIO_PCS_CTRL1_LOOPBACK, 1955a6681e2SEdward Cree efx->loopback_mode == LOOPBACK_PCS); 1965a6681e2SEdward Cree ef4_mdio_set_flag(efx, MDIO_MMD_PHYXS, 1975a6681e2SEdward Cree MDIO_CTRL1, MDIO_PHYXS_CTRL1_LOOPBACK, 1985a6681e2SEdward Cree efx->loopback_mode == LOOPBACK_PHYXS_WS); 1995a6681e2SEdward Cree } 2005a6681e2SEdward Cree 2015a6681e2SEdward Cree static void ef4_mdio_set_mmd_lpower(struct ef4_nic *efx, 2025a6681e2SEdward Cree int lpower, int mmd) 2035a6681e2SEdward Cree { 2045a6681e2SEdward Cree int stat = ef4_mdio_read(efx, mmd, MDIO_STAT1); 2055a6681e2SEdward Cree 2065a6681e2SEdward Cree netif_vdbg(efx, drv, efx->net_dev, "Setting low power mode for MMD %d to %d\n", 2075a6681e2SEdward Cree mmd, lpower); 2085a6681e2SEdward Cree 2095a6681e2SEdward Cree if (stat & MDIO_STAT1_LPOWERABLE) { 2105a6681e2SEdward Cree ef4_mdio_set_flag(efx, mmd, MDIO_CTRL1, 2115a6681e2SEdward Cree MDIO_CTRL1_LPOWER, lpower); 2125a6681e2SEdward Cree } 2135a6681e2SEdward Cree } 2145a6681e2SEdward Cree 2155a6681e2SEdward Cree void ef4_mdio_set_mmds_lpower(struct ef4_nic *efx, 2165a6681e2SEdward Cree int low_power, unsigned int mmd_mask) 2175a6681e2SEdward Cree { 2185a6681e2SEdward Cree int mmd = 0; 2195a6681e2SEdward Cree mmd_mask &= ~MDIO_DEVS_AN; 2205a6681e2SEdward Cree while (mmd_mask) { 2215a6681e2SEdward Cree if (mmd_mask & 1) 2225a6681e2SEdward Cree ef4_mdio_set_mmd_lpower(efx, low_power, mmd); 2235a6681e2SEdward Cree mmd_mask = (mmd_mask >> 1); 2245a6681e2SEdward Cree mmd++; 2255a6681e2SEdward Cree } 2265a6681e2SEdward Cree } 2275a6681e2SEdward Cree 2285a6681e2SEdward Cree /** 229e938ed15SPhilippe Reynes * ef4_mdio_set_link_ksettings - Set (some of) the PHY settings over MDIO. 2305a6681e2SEdward Cree * @efx: Efx NIC 231e938ed15SPhilippe Reynes * @cmd: New settings 2325a6681e2SEdward Cree */ 233e938ed15SPhilippe Reynes int ef4_mdio_set_link_ksettings(struct ef4_nic *efx, 234e938ed15SPhilippe Reynes const struct ethtool_link_ksettings *cmd) 2355a6681e2SEdward Cree { 236e938ed15SPhilippe Reynes struct ethtool_link_ksettings prev = { 237e938ed15SPhilippe Reynes .base.cmd = ETHTOOL_GLINKSETTINGS 238e938ed15SPhilippe Reynes }; 239e938ed15SPhilippe Reynes u32 prev_advertising, advertising; 240e938ed15SPhilippe Reynes u32 prev_supported; 2415a6681e2SEdward Cree 242e938ed15SPhilippe Reynes efx->phy_op->get_link_ksettings(efx, &prev); 2435a6681e2SEdward Cree 244e938ed15SPhilippe Reynes ethtool_convert_link_mode_to_legacy_u32(&advertising, 245e938ed15SPhilippe Reynes cmd->link_modes.advertising); 246e938ed15SPhilippe Reynes ethtool_convert_link_mode_to_legacy_u32(&prev_advertising, 247e938ed15SPhilippe Reynes prev.link_modes.advertising); 248e938ed15SPhilippe Reynes ethtool_convert_link_mode_to_legacy_u32(&prev_supported, 249e938ed15SPhilippe Reynes prev.link_modes.supported); 250e938ed15SPhilippe Reynes 251e938ed15SPhilippe Reynes if (advertising == prev_advertising && 252e938ed15SPhilippe Reynes cmd->base.speed == prev.base.speed && 253e938ed15SPhilippe Reynes cmd->base.duplex == prev.base.duplex && 254e938ed15SPhilippe Reynes cmd->base.port == prev.base.port && 255e938ed15SPhilippe Reynes cmd->base.autoneg == prev.base.autoneg) 2565a6681e2SEdward Cree return 0; 2575a6681e2SEdward Cree 2585a6681e2SEdward Cree /* We can only change these settings for -T PHYs */ 259e938ed15SPhilippe Reynes if (prev.base.port != PORT_TP || cmd->base.port != PORT_TP) 2605a6681e2SEdward Cree return -EINVAL; 2615a6681e2SEdward Cree 2625a6681e2SEdward Cree /* Check that PHY supports these settings */ 263e938ed15SPhilippe Reynes if (!cmd->base.autoneg || 264e938ed15SPhilippe Reynes (advertising | SUPPORTED_Autoneg) & ~prev_supported) 2655a6681e2SEdward Cree return -EINVAL; 2665a6681e2SEdward Cree 267e938ed15SPhilippe Reynes ef4_link_set_advertising(efx, advertising | ADVERTISED_Autoneg); 2685a6681e2SEdward Cree ef4_mdio_an_reconfigure(efx); 2695a6681e2SEdward Cree return 0; 2705a6681e2SEdward Cree } 2715a6681e2SEdward Cree 2725a6681e2SEdward Cree /** 2735a6681e2SEdward Cree * ef4_mdio_an_reconfigure - Push advertising flags and restart autonegotiation 2745a6681e2SEdward Cree * @efx: Efx NIC 2755a6681e2SEdward Cree */ 2765a6681e2SEdward Cree void ef4_mdio_an_reconfigure(struct ef4_nic *efx) 2775a6681e2SEdward Cree { 2785a6681e2SEdward Cree int reg; 2795a6681e2SEdward Cree 2805a6681e2SEdward Cree WARN_ON(!(efx->mdio.mmds & MDIO_DEVS_AN)); 2815a6681e2SEdward Cree 2825a6681e2SEdward Cree /* Set up the base page */ 2835a6681e2SEdward Cree reg = ADVERTISE_CSMA | ADVERTISE_RESV; 2845a6681e2SEdward Cree if (efx->link_advertising & ADVERTISED_Pause) 2855a6681e2SEdward Cree reg |= ADVERTISE_PAUSE_CAP; 2865a6681e2SEdward Cree if (efx->link_advertising & ADVERTISED_Asym_Pause) 2875a6681e2SEdward Cree reg |= ADVERTISE_PAUSE_ASYM; 2885a6681e2SEdward Cree ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); 2895a6681e2SEdward Cree 2905a6681e2SEdward Cree /* Set up the (extended) next page */ 2915a6681e2SEdward Cree efx->phy_op->set_npage_adv(efx, efx->link_advertising); 2925a6681e2SEdward Cree 2935a6681e2SEdward Cree /* Enable and restart AN */ 2945a6681e2SEdward Cree reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1); 2955a6681e2SEdward Cree reg |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART | MDIO_AN_CTRL1_XNP; 2965a6681e2SEdward Cree ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg); 2975a6681e2SEdward Cree } 2985a6681e2SEdward Cree 2995a6681e2SEdward Cree u8 ef4_mdio_get_pause(struct ef4_nic *efx) 3005a6681e2SEdward Cree { 3015a6681e2SEdward Cree BUILD_BUG_ON(EF4_FC_AUTO & (EF4_FC_RX | EF4_FC_TX)); 3025a6681e2SEdward Cree 3035a6681e2SEdward Cree if (!(efx->wanted_fc & EF4_FC_AUTO)) 3045a6681e2SEdward Cree return efx->wanted_fc; 3055a6681e2SEdward Cree 3065a6681e2SEdward Cree WARN_ON(!(efx->mdio.mmds & MDIO_DEVS_AN)); 3075a6681e2SEdward Cree 3085a6681e2SEdward Cree return mii_resolve_flowctrl_fdx( 3095a6681e2SEdward Cree mii_advertise_flowctrl(efx->wanted_fc), 3105a6681e2SEdward Cree ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_LPA)); 3115a6681e2SEdward Cree } 3125a6681e2SEdward Cree 3135a6681e2SEdward Cree int ef4_mdio_test_alive(struct ef4_nic *efx) 3145a6681e2SEdward Cree { 3155a6681e2SEdward Cree int rc; 3165a6681e2SEdward Cree int devad = __ffs(efx->mdio.mmds); 3175a6681e2SEdward Cree u16 physid1, physid2; 3185a6681e2SEdward Cree 3195a6681e2SEdward Cree mutex_lock(&efx->mac_lock); 3205a6681e2SEdward Cree 3215a6681e2SEdward Cree physid1 = ef4_mdio_read(efx, devad, MDIO_DEVID1); 3225a6681e2SEdward Cree physid2 = ef4_mdio_read(efx, devad, MDIO_DEVID2); 3235a6681e2SEdward Cree 3245a6681e2SEdward Cree if ((physid1 == 0x0000) || (physid1 == 0xffff) || 3255a6681e2SEdward Cree (physid2 == 0x0000) || (physid2 == 0xffff)) { 3265a6681e2SEdward Cree netif_err(efx, hw, efx->net_dev, 3275a6681e2SEdward Cree "no MDIO PHY present with ID %d\n", efx->mdio.prtad); 3285a6681e2SEdward Cree rc = -EINVAL; 3295a6681e2SEdward Cree } else { 3305a6681e2SEdward Cree rc = ef4_mdio_check_mmds(efx, efx->mdio.mmds); 3315a6681e2SEdward Cree } 3325a6681e2SEdward Cree 3335a6681e2SEdward Cree mutex_unlock(&efx->mac_lock); 3345a6681e2SEdward Cree return rc; 3355a6681e2SEdward Cree } 336